drm/i915: move error state to own compilation unit
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_drv.h
1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
2 */
3 /*
4 *
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
28 */
29
30 #ifndef _I915_DRV_H_
31 #define _I915_DRV_H_
32
33 #include <uapi/drm/i915_drm.h>
34
35 #include "i915_reg.h"
36 #include "intel_bios.h"
37 #include "intel_ringbuffer.h"
38 #include <linux/io-mapping.h>
39 #include <linux/i2c.h>
40 #include <linux/i2c-algo-bit.h>
41 #include <drm/intel-gtt.h>
42 #include <linux/backlight.h>
43 #include <linux/intel-iommu.h>
44 #include <linux/kref.h>
45 #include <linux/pm_qos.h>
46
47 /* General customization:
48 */
49
50 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
51
52 #define DRIVER_NAME "i915"
53 #define DRIVER_DESC "Intel Graphics"
54 #define DRIVER_DATE "20080730"
55
56 enum pipe {
57 PIPE_A = 0,
58 PIPE_B,
59 PIPE_C,
60 I915_MAX_PIPES
61 };
62 #define pipe_name(p) ((p) + 'A')
63
64 enum transcoder {
65 TRANSCODER_A = 0,
66 TRANSCODER_B,
67 TRANSCODER_C,
68 TRANSCODER_EDP = 0xF,
69 };
70 #define transcoder_name(t) ((t) + 'A')
71
72 enum plane {
73 PLANE_A = 0,
74 PLANE_B,
75 PLANE_C,
76 };
77 #define plane_name(p) ((p) + 'A')
78
79 #define sprite_name(p, s) ((p) * dev_priv->num_plane + (s) + 'A')
80
81 enum port {
82 PORT_A = 0,
83 PORT_B,
84 PORT_C,
85 PORT_D,
86 PORT_E,
87 I915_MAX_PORTS
88 };
89 #define port_name(p) ((p) + 'A')
90
91 enum intel_display_power_domain {
92 POWER_DOMAIN_PIPE_A,
93 POWER_DOMAIN_PIPE_B,
94 POWER_DOMAIN_PIPE_C,
95 POWER_DOMAIN_PIPE_A_PANEL_FITTER,
96 POWER_DOMAIN_PIPE_B_PANEL_FITTER,
97 POWER_DOMAIN_PIPE_C_PANEL_FITTER,
98 POWER_DOMAIN_TRANSCODER_A,
99 POWER_DOMAIN_TRANSCODER_B,
100 POWER_DOMAIN_TRANSCODER_C,
101 POWER_DOMAIN_TRANSCODER_EDP = POWER_DOMAIN_TRANSCODER_A + 0xF,
102 };
103
104 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
105 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
106 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
107 #define POWER_DOMAIN_TRANSCODER(tran) ((tran) + POWER_DOMAIN_TRANSCODER_A)
108
109 enum hpd_pin {
110 HPD_NONE = 0,
111 HPD_PORT_A = HPD_NONE, /* PORT_A is internal */
112 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
113 HPD_CRT,
114 HPD_SDVO_B,
115 HPD_SDVO_C,
116 HPD_PORT_B,
117 HPD_PORT_C,
118 HPD_PORT_D,
119 HPD_NUM_PINS
120 };
121
122 #define I915_GEM_GPU_DOMAINS \
123 (I915_GEM_DOMAIN_RENDER | \
124 I915_GEM_DOMAIN_SAMPLER | \
125 I915_GEM_DOMAIN_COMMAND | \
126 I915_GEM_DOMAIN_INSTRUCTION | \
127 I915_GEM_DOMAIN_VERTEX)
128
129 #define for_each_pipe(p) for ((p) = 0; (p) < INTEL_INFO(dev)->num_pipes; (p)++)
130
131 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
132 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
133 if ((intel_encoder)->base.crtc == (__crtc))
134
135 struct drm_i915_private;
136
137 enum intel_dpll_id {
138 DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
139 /* real shared dpll ids must be >= 0 */
140 DPLL_ID_PCH_PLL_A,
141 DPLL_ID_PCH_PLL_B,
142 };
143 #define I915_NUM_PLLS 2
144
145 struct intel_dpll_hw_state {
146 uint32_t dpll;
147 uint32_t dpll_md;
148 uint32_t fp0;
149 uint32_t fp1;
150 };
151
152 struct intel_shared_dpll {
153 int refcount; /* count of number of CRTCs sharing this PLL */
154 int active; /* count of number of active CRTCs (i.e. DPMS on) */
155 bool on; /* is the PLL actually active? Disabled during modeset */
156 const char *name;
157 /* should match the index in the dev_priv->shared_dplls array */
158 enum intel_dpll_id id;
159 struct intel_dpll_hw_state hw_state;
160 void (*mode_set)(struct drm_i915_private *dev_priv,
161 struct intel_shared_dpll *pll);
162 void (*enable)(struct drm_i915_private *dev_priv,
163 struct intel_shared_dpll *pll);
164 void (*disable)(struct drm_i915_private *dev_priv,
165 struct intel_shared_dpll *pll);
166 bool (*get_hw_state)(struct drm_i915_private *dev_priv,
167 struct intel_shared_dpll *pll,
168 struct intel_dpll_hw_state *hw_state);
169 };
170
171 /* Used by dp and fdi links */
172 struct intel_link_m_n {
173 uint32_t tu;
174 uint32_t gmch_m;
175 uint32_t gmch_n;
176 uint32_t link_m;
177 uint32_t link_n;
178 };
179
180 void intel_link_compute_m_n(int bpp, int nlanes,
181 int pixel_clock, int link_clock,
182 struct intel_link_m_n *m_n);
183
184 struct intel_ddi_plls {
185 int spll_refcount;
186 int wrpll1_refcount;
187 int wrpll2_refcount;
188 };
189
190 /* Interface history:
191 *
192 * 1.1: Original.
193 * 1.2: Add Power Management
194 * 1.3: Add vblank support
195 * 1.4: Fix cmdbuffer path, add heap destroy
196 * 1.5: Add vblank pipe configuration
197 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
198 * - Support vertical blank on secondary display pipe
199 */
200 #define DRIVER_MAJOR 1
201 #define DRIVER_MINOR 6
202 #define DRIVER_PATCHLEVEL 0
203
204 #define WATCH_COHERENCY 0
205 #define WATCH_LISTS 0
206 #define WATCH_GTT 0
207
208 #define I915_GEM_PHYS_CURSOR_0 1
209 #define I915_GEM_PHYS_CURSOR_1 2
210 #define I915_GEM_PHYS_OVERLAY_REGS 3
211 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
212
213 struct drm_i915_gem_phys_object {
214 int id;
215 struct page **page_list;
216 drm_dma_handle_t *handle;
217 struct drm_i915_gem_object *cur_obj;
218 };
219
220 struct opregion_header;
221 struct opregion_acpi;
222 struct opregion_swsci;
223 struct opregion_asle;
224
225 struct intel_opregion {
226 struct opregion_header __iomem *header;
227 struct opregion_acpi __iomem *acpi;
228 struct opregion_swsci __iomem *swsci;
229 struct opregion_asle __iomem *asle;
230 void __iomem *vbt;
231 u32 __iomem *lid_state;
232 };
233 #define OPREGION_SIZE (8*1024)
234
235 struct intel_overlay;
236 struct intel_overlay_error_state;
237
238 struct drm_i915_master_private {
239 drm_local_map_t *sarea;
240 struct _drm_i915_sarea *sarea_priv;
241 };
242 #define I915_FENCE_REG_NONE -1
243 #define I915_MAX_NUM_FENCES 32
244 /* 32 fences + sign bit for FENCE_REG_NONE */
245 #define I915_MAX_NUM_FENCE_BITS 6
246
247 struct drm_i915_fence_reg {
248 struct list_head lru_list;
249 struct drm_i915_gem_object *obj;
250 int pin_count;
251 };
252
253 struct sdvo_device_mapping {
254 u8 initialized;
255 u8 dvo_port;
256 u8 slave_addr;
257 u8 dvo_wiring;
258 u8 i2c_pin;
259 u8 ddc_pin;
260 };
261
262 struct intel_display_error_state;
263
264 struct drm_i915_error_state {
265 struct kref ref;
266 u32 eir;
267 u32 pgtbl_er;
268 u32 ier;
269 u32 ccid;
270 u32 derrmr;
271 u32 forcewake;
272 bool waiting[I915_NUM_RINGS];
273 u32 pipestat[I915_MAX_PIPES];
274 u32 tail[I915_NUM_RINGS];
275 u32 head[I915_NUM_RINGS];
276 u32 ctl[I915_NUM_RINGS];
277 u32 ipeir[I915_NUM_RINGS];
278 u32 ipehr[I915_NUM_RINGS];
279 u32 instdone[I915_NUM_RINGS];
280 u32 acthd[I915_NUM_RINGS];
281 u32 semaphore_mboxes[I915_NUM_RINGS][I915_NUM_RINGS - 1];
282 u32 semaphore_seqno[I915_NUM_RINGS][I915_NUM_RINGS - 1];
283 u32 rc_psmi[I915_NUM_RINGS]; /* sleep state */
284 /* our own tracking of ring head and tail */
285 u32 cpu_ring_head[I915_NUM_RINGS];
286 u32 cpu_ring_tail[I915_NUM_RINGS];
287 u32 error; /* gen6+ */
288 u32 err_int; /* gen7 */
289 u32 instpm[I915_NUM_RINGS];
290 u32 instps[I915_NUM_RINGS];
291 u32 extra_instdone[I915_NUM_INSTDONE_REG];
292 u32 seqno[I915_NUM_RINGS];
293 u64 bbaddr;
294 u32 fault_reg[I915_NUM_RINGS];
295 u32 done_reg;
296 u32 faddr[I915_NUM_RINGS];
297 u64 fence[I915_MAX_NUM_FENCES];
298 struct timeval time;
299 struct drm_i915_error_ring {
300 struct drm_i915_error_object {
301 int page_count;
302 u32 gtt_offset;
303 u32 *pages[0];
304 } *ringbuffer, *batchbuffer, *ctx;
305 struct drm_i915_error_request {
306 long jiffies;
307 u32 seqno;
308 u32 tail;
309 } *requests;
310 int num_requests;
311 } ring[I915_NUM_RINGS];
312 struct drm_i915_error_buffer {
313 u32 size;
314 u32 name;
315 u32 rseqno, wseqno;
316 u32 gtt_offset;
317 u32 read_domains;
318 u32 write_domain;
319 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
320 s32 pinned:2;
321 u32 tiling:2;
322 u32 dirty:1;
323 u32 purgeable:1;
324 s32 ring:4;
325 u32 cache_level:2;
326 } *active_bo, *pinned_bo;
327 u32 active_bo_count, pinned_bo_count;
328 struct intel_overlay_error_state *overlay;
329 struct intel_display_error_state *display;
330 };
331
332 struct intel_crtc_config;
333 struct intel_crtc;
334 struct intel_limit;
335 struct dpll;
336
337 struct drm_i915_display_funcs {
338 bool (*fbc_enabled)(struct drm_device *dev);
339 void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);
340 void (*disable_fbc)(struct drm_device *dev);
341 int (*get_display_clock_speed)(struct drm_device *dev);
342 int (*get_fifo_size)(struct drm_device *dev, int plane);
343 /**
344 * find_dpll() - Find the best values for the PLL
345 * @limit: limits for the PLL
346 * @crtc: current CRTC
347 * @target: target frequency in kHz
348 * @refclk: reference clock frequency in kHz
349 * @match_clock: if provided, @best_clock P divider must
350 * match the P divider from @match_clock
351 * used for LVDS downclocking
352 * @best_clock: best PLL values found
353 *
354 * Returns true on success, false on failure.
355 */
356 bool (*find_dpll)(const struct intel_limit *limit,
357 struct drm_crtc *crtc,
358 int target, int refclk,
359 struct dpll *match_clock,
360 struct dpll *best_clock);
361 void (*update_wm)(struct drm_device *dev);
362 void (*update_sprite_wm)(struct drm_device *dev, int pipe,
363 uint32_t sprite_width, int pixel_size,
364 bool enable);
365 void (*modeset_global_resources)(struct drm_device *dev);
366 /* Returns the active state of the crtc, and if the crtc is active,
367 * fills out the pipe-config with the hw state. */
368 bool (*get_pipe_config)(struct intel_crtc *,
369 struct intel_crtc_config *);
370 void (*get_clock)(struct intel_crtc *, struct intel_crtc_config *);
371 int (*crtc_mode_set)(struct drm_crtc *crtc,
372 int x, int y,
373 struct drm_framebuffer *old_fb);
374 void (*crtc_enable)(struct drm_crtc *crtc);
375 void (*crtc_disable)(struct drm_crtc *crtc);
376 void (*off)(struct drm_crtc *crtc);
377 void (*write_eld)(struct drm_connector *connector,
378 struct drm_crtc *crtc);
379 void (*fdi_link_train)(struct drm_crtc *crtc);
380 void (*init_clock_gating)(struct drm_device *dev);
381 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
382 struct drm_framebuffer *fb,
383 struct drm_i915_gem_object *obj);
384 int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb,
385 int x, int y);
386 void (*hpd_irq_setup)(struct drm_device *dev);
387 /* clock updates for mode set */
388 /* cursor updates */
389 /* render clock increase/decrease */
390 /* display clock increase/decrease */
391 /* pll clock increase/decrease */
392 };
393
394 struct drm_i915_gt_funcs {
395 void (*force_wake_get)(struct drm_i915_private *dev_priv);
396 void (*force_wake_put)(struct drm_i915_private *dev_priv);
397 };
398
399 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
400 func(is_mobile) sep \
401 func(is_i85x) sep \
402 func(is_i915g) sep \
403 func(is_i945gm) sep \
404 func(is_g33) sep \
405 func(need_gfx_hws) sep \
406 func(is_g4x) sep \
407 func(is_pineview) sep \
408 func(is_broadwater) sep \
409 func(is_crestline) sep \
410 func(is_ivybridge) sep \
411 func(is_valleyview) sep \
412 func(is_haswell) sep \
413 func(has_force_wake) sep \
414 func(has_fbc) sep \
415 func(has_pipe_cxsr) sep \
416 func(has_hotplug) sep \
417 func(cursor_needs_physical) sep \
418 func(has_overlay) sep \
419 func(overlay_needs_physical) sep \
420 func(supports_tv) sep \
421 func(has_bsd_ring) sep \
422 func(has_blt_ring) sep \
423 func(has_vebox_ring) sep \
424 func(has_llc) sep \
425 func(has_ddi) sep \
426 func(has_fpga_dbg)
427
428 #define DEFINE_FLAG(name) u8 name:1
429 #define SEP_SEMICOLON ;
430
431 struct intel_device_info {
432 u32 display_mmio_offset;
433 u8 num_pipes:3;
434 u8 gen;
435 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
436 };
437
438 #undef DEFINE_FLAG
439 #undef SEP_SEMICOLON
440
441 enum i915_cache_level {
442 I915_CACHE_NONE = 0,
443 I915_CACHE_LLC,
444 I915_CACHE_LLC_MLC, /* gen6+, in docs at least! */
445 };
446
447 typedef uint32_t gen6_gtt_pte_t;
448
449 /* The Graphics Translation Table is the way in which GEN hardware translates a
450 * Graphics Virtual Address into a Physical Address. In addition to the normal
451 * collateral associated with any va->pa translations GEN hardware also has a
452 * portion of the GTT which can be mapped by the CPU and remain both coherent
453 * and correct (in cases like swizzling). That region is referred to as GMADR in
454 * the spec.
455 */
456 struct i915_gtt {
457 unsigned long start; /* Start offset of used GTT */
458 size_t total; /* Total size GTT can map */
459 size_t stolen_size; /* Total size of stolen memory */
460
461 unsigned long mappable_end; /* End offset that we can CPU map */
462 struct io_mapping *mappable; /* Mapping to our CPU mappable region */
463 phys_addr_t mappable_base; /* PA of our GMADR */
464
465 /** "Graphics Stolen Memory" holds the global PTEs */
466 void __iomem *gsm;
467
468 bool do_idle_maps;
469 struct {
470 dma_addr_t addr;
471 struct page *page;
472 } scratch;
473
474 int mtrr;
475
476 /* global gtt ops */
477 int (*gtt_probe)(struct drm_device *dev, size_t *gtt_total,
478 size_t *stolen, phys_addr_t *mappable_base,
479 unsigned long *mappable_end);
480 void (*gtt_remove)(struct drm_device *dev);
481 void (*gtt_clear_range)(struct drm_device *dev,
482 unsigned int first_entry,
483 unsigned int num_entries);
484 void (*gtt_insert_entries)(struct drm_device *dev,
485 struct sg_table *st,
486 unsigned int pg_start,
487 enum i915_cache_level cache_level);
488 gen6_gtt_pte_t (*pte_encode)(dma_addr_t addr,
489 enum i915_cache_level level);
490 };
491 #define gtt_total_entries(gtt) ((gtt).total >> PAGE_SHIFT)
492
493 struct i915_hw_ppgtt {
494 struct drm_device *dev;
495 unsigned num_pd_entries;
496 struct page **pt_pages;
497 uint32_t pd_offset;
498 dma_addr_t *pt_dma_addr;
499
500 /* pte functions, mirroring the interface of the global gtt. */
501 void (*clear_range)(struct i915_hw_ppgtt *ppgtt,
502 unsigned int first_entry,
503 unsigned int num_entries);
504 void (*insert_entries)(struct i915_hw_ppgtt *ppgtt,
505 struct sg_table *st,
506 unsigned int pg_start,
507 enum i915_cache_level cache_level);
508 gen6_gtt_pte_t (*pte_encode)(dma_addr_t addr,
509 enum i915_cache_level level);
510 int (*enable)(struct drm_device *dev);
511 void (*cleanup)(struct i915_hw_ppgtt *ppgtt);
512 };
513
514 struct i915_ctx_hang_stats {
515 /* This context had batch pending when hang was declared */
516 unsigned batch_pending;
517
518 /* This context had batch active when hang was declared */
519 unsigned batch_active;
520 };
521
522 /* This must match up with the value previously used for execbuf2.rsvd1. */
523 #define DEFAULT_CONTEXT_ID 0
524 struct i915_hw_context {
525 struct kref ref;
526 int id;
527 bool is_initialized;
528 struct drm_i915_file_private *file_priv;
529 struct intel_ring_buffer *ring;
530 struct drm_i915_gem_object *obj;
531 struct i915_ctx_hang_stats hang_stats;
532 };
533
534 struct i915_fbc {
535 unsigned long size;
536 unsigned int fb_id;
537 enum plane plane;
538 int y;
539
540 struct drm_mm_node *compressed_fb;
541 struct drm_mm_node *compressed_llb;
542
543 struct intel_fbc_work {
544 struct delayed_work work;
545 struct drm_crtc *crtc;
546 struct drm_framebuffer *fb;
547 int interval;
548 } *fbc_work;
549
550 enum {
551 FBC_NO_OUTPUT, /* no outputs enabled to compress */
552 FBC_STOLEN_TOO_SMALL, /* not enough space for buffers */
553 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
554 FBC_MODE_TOO_LARGE, /* mode too large for compression */
555 FBC_BAD_PLANE, /* fbc not supported on plane */
556 FBC_NOT_TILED, /* buffer not tiled */
557 FBC_MULTIPLE_PIPES, /* more than one pipe active */
558 FBC_MODULE_PARAM,
559 FBC_CHIP_DEFAULT, /* disabled by default on this chip */
560 } no_fbc_reason;
561 };
562
563
564 enum intel_pch {
565 PCH_NONE = 0, /* No PCH present */
566 PCH_IBX, /* Ibexpeak PCH */
567 PCH_CPT, /* Cougarpoint PCH */
568 PCH_LPT, /* Lynxpoint PCH */
569 PCH_NOP,
570 };
571
572 enum intel_sbi_destination {
573 SBI_ICLK,
574 SBI_MPHY,
575 };
576
577 #define QUIRK_PIPEA_FORCE (1<<0)
578 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
579 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
580
581 struct intel_fbdev;
582 struct intel_fbc_work;
583
584 struct intel_gmbus {
585 struct i2c_adapter adapter;
586 u32 force_bit;
587 u32 reg0;
588 u32 gpio_reg;
589 struct i2c_algo_bit_data bit_algo;
590 struct drm_i915_private *dev_priv;
591 };
592
593 struct i915_suspend_saved_registers {
594 u8 saveLBB;
595 u32 saveDSPACNTR;
596 u32 saveDSPBCNTR;
597 u32 saveDSPARB;
598 u32 savePIPEACONF;
599 u32 savePIPEBCONF;
600 u32 savePIPEASRC;
601 u32 savePIPEBSRC;
602 u32 saveFPA0;
603 u32 saveFPA1;
604 u32 saveDPLL_A;
605 u32 saveDPLL_A_MD;
606 u32 saveHTOTAL_A;
607 u32 saveHBLANK_A;
608 u32 saveHSYNC_A;
609 u32 saveVTOTAL_A;
610 u32 saveVBLANK_A;
611 u32 saveVSYNC_A;
612 u32 saveBCLRPAT_A;
613 u32 saveTRANSACONF;
614 u32 saveTRANS_HTOTAL_A;
615 u32 saveTRANS_HBLANK_A;
616 u32 saveTRANS_HSYNC_A;
617 u32 saveTRANS_VTOTAL_A;
618 u32 saveTRANS_VBLANK_A;
619 u32 saveTRANS_VSYNC_A;
620 u32 savePIPEASTAT;
621 u32 saveDSPASTRIDE;
622 u32 saveDSPASIZE;
623 u32 saveDSPAPOS;
624 u32 saveDSPAADDR;
625 u32 saveDSPASURF;
626 u32 saveDSPATILEOFF;
627 u32 savePFIT_PGM_RATIOS;
628 u32 saveBLC_HIST_CTL;
629 u32 saveBLC_PWM_CTL;
630 u32 saveBLC_PWM_CTL2;
631 u32 saveBLC_CPU_PWM_CTL;
632 u32 saveBLC_CPU_PWM_CTL2;
633 u32 saveFPB0;
634 u32 saveFPB1;
635 u32 saveDPLL_B;
636 u32 saveDPLL_B_MD;
637 u32 saveHTOTAL_B;
638 u32 saveHBLANK_B;
639 u32 saveHSYNC_B;
640 u32 saveVTOTAL_B;
641 u32 saveVBLANK_B;
642 u32 saveVSYNC_B;
643 u32 saveBCLRPAT_B;
644 u32 saveTRANSBCONF;
645 u32 saveTRANS_HTOTAL_B;
646 u32 saveTRANS_HBLANK_B;
647 u32 saveTRANS_HSYNC_B;
648 u32 saveTRANS_VTOTAL_B;
649 u32 saveTRANS_VBLANK_B;
650 u32 saveTRANS_VSYNC_B;
651 u32 savePIPEBSTAT;
652 u32 saveDSPBSTRIDE;
653 u32 saveDSPBSIZE;
654 u32 saveDSPBPOS;
655 u32 saveDSPBADDR;
656 u32 saveDSPBSURF;
657 u32 saveDSPBTILEOFF;
658 u32 saveVGA0;
659 u32 saveVGA1;
660 u32 saveVGA_PD;
661 u32 saveVGACNTRL;
662 u32 saveADPA;
663 u32 saveLVDS;
664 u32 savePP_ON_DELAYS;
665 u32 savePP_OFF_DELAYS;
666 u32 saveDVOA;
667 u32 saveDVOB;
668 u32 saveDVOC;
669 u32 savePP_ON;
670 u32 savePP_OFF;
671 u32 savePP_CONTROL;
672 u32 savePP_DIVISOR;
673 u32 savePFIT_CONTROL;
674 u32 save_palette_a[256];
675 u32 save_palette_b[256];
676 u32 saveDPFC_CB_BASE;
677 u32 saveFBC_CFB_BASE;
678 u32 saveFBC_LL_BASE;
679 u32 saveFBC_CONTROL;
680 u32 saveFBC_CONTROL2;
681 u32 saveIER;
682 u32 saveIIR;
683 u32 saveIMR;
684 u32 saveDEIER;
685 u32 saveDEIMR;
686 u32 saveGTIER;
687 u32 saveGTIMR;
688 u32 saveFDI_RXA_IMR;
689 u32 saveFDI_RXB_IMR;
690 u32 saveCACHE_MODE_0;
691 u32 saveMI_ARB_STATE;
692 u32 saveSWF0[16];
693 u32 saveSWF1[16];
694 u32 saveSWF2[3];
695 u8 saveMSR;
696 u8 saveSR[8];
697 u8 saveGR[25];
698 u8 saveAR_INDEX;
699 u8 saveAR[21];
700 u8 saveDACMASK;
701 u8 saveCR[37];
702 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
703 u32 saveCURACNTR;
704 u32 saveCURAPOS;
705 u32 saveCURABASE;
706 u32 saveCURBCNTR;
707 u32 saveCURBPOS;
708 u32 saveCURBBASE;
709 u32 saveCURSIZE;
710 u32 saveDP_B;
711 u32 saveDP_C;
712 u32 saveDP_D;
713 u32 savePIPEA_GMCH_DATA_M;
714 u32 savePIPEB_GMCH_DATA_M;
715 u32 savePIPEA_GMCH_DATA_N;
716 u32 savePIPEB_GMCH_DATA_N;
717 u32 savePIPEA_DP_LINK_M;
718 u32 savePIPEB_DP_LINK_M;
719 u32 savePIPEA_DP_LINK_N;
720 u32 savePIPEB_DP_LINK_N;
721 u32 saveFDI_RXA_CTL;
722 u32 saveFDI_TXA_CTL;
723 u32 saveFDI_RXB_CTL;
724 u32 saveFDI_TXB_CTL;
725 u32 savePFA_CTL_1;
726 u32 savePFB_CTL_1;
727 u32 savePFA_WIN_SZ;
728 u32 savePFB_WIN_SZ;
729 u32 savePFA_WIN_POS;
730 u32 savePFB_WIN_POS;
731 u32 savePCH_DREF_CONTROL;
732 u32 saveDISP_ARB_CTL;
733 u32 savePIPEA_DATA_M1;
734 u32 savePIPEA_DATA_N1;
735 u32 savePIPEA_LINK_M1;
736 u32 savePIPEA_LINK_N1;
737 u32 savePIPEB_DATA_M1;
738 u32 savePIPEB_DATA_N1;
739 u32 savePIPEB_LINK_M1;
740 u32 savePIPEB_LINK_N1;
741 u32 saveMCHBAR_RENDER_STANDBY;
742 u32 savePCH_PORT_HOTPLUG;
743 };
744
745 struct intel_gen6_power_mgmt {
746 /* work and pm_iir are protected by dev_priv->irq_lock */
747 struct work_struct work;
748 u32 pm_iir;
749
750 /* On vlv we need to manually drop to Vmin with a delayed work. */
751 struct delayed_work vlv_work;
752
753 /* The below variables an all the rps hw state are protected by
754 * dev->struct mutext. */
755 u8 cur_delay;
756 u8 min_delay;
757 u8 max_delay;
758 u8 rpe_delay;
759 u8 hw_max;
760
761 struct delayed_work delayed_resume_work;
762
763 /*
764 * Protects RPS/RC6 register access and PCU communication.
765 * Must be taken after struct_mutex if nested.
766 */
767 struct mutex hw_lock;
768 };
769
770 /* defined intel_pm.c */
771 extern spinlock_t mchdev_lock;
772
773 struct intel_ilk_power_mgmt {
774 u8 cur_delay;
775 u8 min_delay;
776 u8 max_delay;
777 u8 fmax;
778 u8 fstart;
779
780 u64 last_count1;
781 unsigned long last_time1;
782 unsigned long chipset_power;
783 u64 last_count2;
784 struct timespec last_time2;
785 unsigned long gfx_power;
786 u8 corr;
787
788 int c_m;
789 int r_t;
790
791 struct drm_i915_gem_object *pwrctx;
792 struct drm_i915_gem_object *renderctx;
793 };
794
795 /* Power well structure for haswell */
796 struct i915_power_well {
797 struct drm_device *device;
798 spinlock_t lock;
799 /* power well enable/disable usage count */
800 int count;
801 int i915_request;
802 };
803
804 struct i915_dri1_state {
805 unsigned allow_batchbuffer : 1;
806 u32 __iomem *gfx_hws_cpu_addr;
807
808 unsigned int cpp;
809 int back_offset;
810 int front_offset;
811 int current_page;
812 int page_flipping;
813
814 uint32_t counter;
815 };
816
817 struct i915_ums_state {
818 /**
819 * Flag if the X Server, and thus DRM, is not currently in
820 * control of the device.
821 *
822 * This is set between LeaveVT and EnterVT. It needs to be
823 * replaced with a semaphore. It also needs to be
824 * transitioned away from for kernel modesetting.
825 */
826 int mm_suspended;
827 };
828
829 struct intel_l3_parity {
830 u32 *remap_info;
831 struct work_struct error_work;
832 };
833
834 struct i915_gem_mm {
835 /** Memory allocator for GTT stolen memory */
836 struct drm_mm stolen;
837 /** Memory allocator for GTT */
838 struct drm_mm gtt_space;
839 /** List of all objects in gtt_space. Used to restore gtt
840 * mappings on resume */
841 struct list_head bound_list;
842 /**
843 * List of objects which are not bound to the GTT (thus
844 * are idle and not used by the GPU) but still have
845 * (presumably uncached) pages still attached.
846 */
847 struct list_head unbound_list;
848
849 /** Usable portion of the GTT for GEM */
850 unsigned long stolen_base; /* limited to low memory (32-bit) */
851
852 /** PPGTT used for aliasing the PPGTT with the GTT */
853 struct i915_hw_ppgtt *aliasing_ppgtt;
854
855 struct shrinker inactive_shrinker;
856 bool shrinker_no_lock_stealing;
857
858 /**
859 * List of objects currently involved in rendering.
860 *
861 * Includes buffers having the contents of their GPU caches
862 * flushed, not necessarily primitives. last_rendering_seqno
863 * represents when the rendering involved will be completed.
864 *
865 * A reference is held on the buffer while on this list.
866 */
867 struct list_head active_list;
868
869 /**
870 * LRU list of objects which are not in the ringbuffer and
871 * are ready to unbind, but are still in the GTT.
872 *
873 * last_rendering_seqno is 0 while an object is in this list.
874 *
875 * A reference is not held on the buffer while on this list,
876 * as merely being GTT-bound shouldn't prevent its being
877 * freed, and we'll pull it off the list in the free path.
878 */
879 struct list_head inactive_list;
880
881 /** LRU list of objects with fence regs on them. */
882 struct list_head fence_list;
883
884 /**
885 * We leave the user IRQ off as much as possible,
886 * but this means that requests will finish and never
887 * be retired once the system goes idle. Set a timer to
888 * fire periodically while the ring is running. When it
889 * fires, go retire requests.
890 */
891 struct delayed_work retire_work;
892
893 /**
894 * Are we in a non-interruptible section of code like
895 * modesetting?
896 */
897 bool interruptible;
898
899 /** Bit 6 swizzling required for X tiling */
900 uint32_t bit_6_swizzle_x;
901 /** Bit 6 swizzling required for Y tiling */
902 uint32_t bit_6_swizzle_y;
903
904 /* storage for physical objects */
905 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
906
907 /* accounting, useful for userland debugging */
908 size_t object_memory;
909 u32 object_count;
910 };
911
912 struct drm_i915_error_state_buf {
913 unsigned bytes;
914 unsigned size;
915 int err;
916 u8 *buf;
917 loff_t start;
918 loff_t pos;
919 };
920
921 struct i915_error_state_file_priv {
922 struct drm_device *dev;
923 struct drm_i915_error_state *error;
924 };
925
926 struct i915_gpu_error {
927 /* For hangcheck timer */
928 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
929 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
930 struct timer_list hangcheck_timer;
931
932 /* For reset and error_state handling. */
933 spinlock_t lock;
934 /* Protected by the above dev->gpu_error.lock. */
935 struct drm_i915_error_state *first_error;
936 struct work_struct work;
937
938 unsigned long last_reset;
939
940 /**
941 * State variable and reset counter controlling the reset flow
942 *
943 * Upper bits are for the reset counter. This counter is used by the
944 * wait_seqno code to race-free noticed that a reset event happened and
945 * that it needs to restart the entire ioctl (since most likely the
946 * seqno it waited for won't ever signal anytime soon).
947 *
948 * This is important for lock-free wait paths, where no contended lock
949 * naturally enforces the correct ordering between the bail-out of the
950 * waiter and the gpu reset work code.
951 *
952 * Lowest bit controls the reset state machine: Set means a reset is in
953 * progress. This state will (presuming we don't have any bugs) decay
954 * into either unset (successful reset) or the special WEDGED value (hw
955 * terminally sour). All waiters on the reset_queue will be woken when
956 * that happens.
957 */
958 atomic_t reset_counter;
959
960 /**
961 * Special values/flags for reset_counter
962 *
963 * Note that the code relies on
964 * I915_WEDGED & I915_RESET_IN_PROGRESS_FLAG
965 * being true.
966 */
967 #define I915_RESET_IN_PROGRESS_FLAG 1
968 #define I915_WEDGED 0xffffffff
969
970 /**
971 * Waitqueue to signal when the reset has completed. Used by clients
972 * that wait for dev_priv->mm.wedged to settle.
973 */
974 wait_queue_head_t reset_queue;
975
976 /* For gpu hang simulation. */
977 unsigned int stop_rings;
978 };
979
980 enum modeset_restore {
981 MODESET_ON_LID_OPEN,
982 MODESET_DONE,
983 MODESET_SUSPENDED,
984 };
985
986 struct intel_vbt_data {
987 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
988 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
989
990 /* Feature bits */
991 unsigned int int_tv_support:1;
992 unsigned int lvds_dither:1;
993 unsigned int lvds_vbt:1;
994 unsigned int int_crt_support:1;
995 unsigned int lvds_use_ssc:1;
996 unsigned int display_clock_mode:1;
997 unsigned int fdi_rx_polarity_inverted:1;
998 int lvds_ssc_freq;
999 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1000
1001 /* eDP */
1002 int edp_rate;
1003 int edp_lanes;
1004 int edp_preemphasis;
1005 int edp_vswing;
1006 bool edp_initialized;
1007 bool edp_support;
1008 int edp_bpp;
1009 struct edp_power_seq edp_pps;
1010
1011 int crt_ddc_pin;
1012
1013 int child_dev_num;
1014 struct child_device_config *child_dev;
1015 };
1016
1017 typedef struct drm_i915_private {
1018 struct drm_device *dev;
1019 struct kmem_cache *slab;
1020
1021 const struct intel_device_info *info;
1022
1023 int relative_constants_mode;
1024
1025 void __iomem *regs;
1026
1027 struct drm_i915_gt_funcs gt;
1028 /** gt_fifo_count and the subsequent register write are synchronized
1029 * with dev->struct_mutex. */
1030 unsigned gt_fifo_count;
1031 /** forcewake_count is protected by gt_lock */
1032 unsigned forcewake_count;
1033 /** gt_lock is also taken in irq contexts. */
1034 spinlock_t gt_lock;
1035
1036 struct intel_gmbus gmbus[GMBUS_NUM_PORTS];
1037
1038
1039 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1040 * controller on different i2c buses. */
1041 struct mutex gmbus_mutex;
1042
1043 /**
1044 * Base address of the gmbus and gpio block.
1045 */
1046 uint32_t gpio_mmio_base;
1047
1048 wait_queue_head_t gmbus_wait_queue;
1049
1050 struct pci_dev *bridge_dev;
1051 struct intel_ring_buffer ring[I915_NUM_RINGS];
1052 uint32_t last_seqno, next_seqno;
1053
1054 drm_dma_handle_t *status_page_dmah;
1055 struct resource mch_res;
1056
1057 atomic_t irq_received;
1058
1059 /* protects the irq masks */
1060 spinlock_t irq_lock;
1061
1062 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1063 struct pm_qos_request pm_qos;
1064
1065 /* DPIO indirect register protection */
1066 struct mutex dpio_lock;
1067
1068 /** Cached value of IMR to avoid reads in updating the bitfield */
1069 u32 irq_mask;
1070 u32 gt_irq_mask;
1071
1072 struct work_struct hotplug_work;
1073 bool enable_hotplug_processing;
1074 struct {
1075 unsigned long hpd_last_jiffies;
1076 int hpd_cnt;
1077 enum {
1078 HPD_ENABLED = 0,
1079 HPD_DISABLED = 1,
1080 HPD_MARK_DISABLED = 2
1081 } hpd_mark;
1082 } hpd_stats[HPD_NUM_PINS];
1083 u32 hpd_event_bits;
1084 struct timer_list hotplug_reenable_timer;
1085
1086 int num_plane;
1087
1088 struct i915_fbc fbc;
1089 struct intel_opregion opregion;
1090 struct intel_vbt_data vbt;
1091
1092 /* overlay */
1093 struct intel_overlay *overlay;
1094 unsigned int sprite_scaling_enabled;
1095
1096 /* backlight */
1097 struct {
1098 int level;
1099 bool enabled;
1100 spinlock_t lock; /* bl registers and the above bl fields */
1101 struct backlight_device *device;
1102 } backlight;
1103
1104 /* LVDS info */
1105 bool no_aux_handshake;
1106
1107 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
1108 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
1109 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
1110
1111 unsigned int fsb_freq, mem_freq, is_ddr3;
1112
1113 struct workqueue_struct *wq;
1114
1115 /* Display functions */
1116 struct drm_i915_display_funcs display;
1117
1118 /* PCH chipset type */
1119 enum intel_pch pch_type;
1120 unsigned short pch_id;
1121
1122 unsigned long quirks;
1123
1124 enum modeset_restore modeset_restore;
1125 struct mutex modeset_restore_lock;
1126
1127 struct i915_gtt gtt;
1128
1129 struct i915_gem_mm mm;
1130
1131 /* Kernel Modesetting */
1132
1133 struct sdvo_device_mapping sdvo_mappings[2];
1134
1135 struct drm_crtc *plane_to_crtc_mapping[3];
1136 struct drm_crtc *pipe_to_crtc_mapping[3];
1137 wait_queue_head_t pending_flip_queue;
1138
1139 int num_shared_dpll;
1140 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1141 struct intel_ddi_plls ddi_plls;
1142
1143 /* Reclocking support */
1144 bool render_reclock_avail;
1145 bool lvds_downclock_avail;
1146 /* indicates the reduced downclock for LVDS*/
1147 int lvds_downclock;
1148 u16 orig_clock;
1149
1150 bool mchbar_need_disable;
1151
1152 struct intel_l3_parity l3_parity;
1153
1154 /* gen6+ rps state */
1155 struct intel_gen6_power_mgmt rps;
1156
1157 /* ilk-only ips/rps state. Everything in here is protected by the global
1158 * mchdev_lock in intel_pm.c */
1159 struct intel_ilk_power_mgmt ips;
1160
1161 /* Haswell power well */
1162 struct i915_power_well power_well;
1163
1164 struct i915_gpu_error gpu_error;
1165
1166 struct drm_i915_gem_object *vlv_pctx;
1167
1168 /* list of fbdev register on this device */
1169 struct intel_fbdev *fbdev;
1170
1171 /*
1172 * The console may be contended at resume, but we don't
1173 * want it to block on it.
1174 */
1175 struct work_struct console_resume_work;
1176
1177 struct drm_property *broadcast_rgb_property;
1178 struct drm_property *force_audio_property;
1179
1180 bool hw_contexts_disabled;
1181 uint32_t hw_context_size;
1182
1183 u32 fdi_rx_config;
1184
1185 struct i915_suspend_saved_registers regfile;
1186
1187 /* Old dri1 support infrastructure, beware the dragons ya fools entering
1188 * here! */
1189 struct i915_dri1_state dri1;
1190 /* Old ums support infrastructure, same warning applies. */
1191 struct i915_ums_state ums;
1192 } drm_i915_private_t;
1193
1194 /* Iterate over initialised rings */
1195 #define for_each_ring(ring__, dev_priv__, i__) \
1196 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
1197 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
1198
1199 enum hdmi_force_audio {
1200 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
1201 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
1202 HDMI_AUDIO_AUTO, /* trust EDID */
1203 HDMI_AUDIO_ON, /* force turn on HDMI audio */
1204 };
1205
1206 #define I915_GTT_OFFSET_NONE ((u32)-1)
1207
1208 struct drm_i915_gem_object_ops {
1209 /* Interface between the GEM object and its backing storage.
1210 * get_pages() is called once prior to the use of the associated set
1211 * of pages before to binding them into the GTT, and put_pages() is
1212 * called after we no longer need them. As we expect there to be
1213 * associated cost with migrating pages between the backing storage
1214 * and making them available for the GPU (e.g. clflush), we may hold
1215 * onto the pages after they are no longer referenced by the GPU
1216 * in case they may be used again shortly (for example migrating the
1217 * pages to a different memory domain within the GTT). put_pages()
1218 * will therefore most likely be called when the object itself is
1219 * being released or under memory pressure (where we attempt to
1220 * reap pages for the shrinker).
1221 */
1222 int (*get_pages)(struct drm_i915_gem_object *);
1223 void (*put_pages)(struct drm_i915_gem_object *);
1224 };
1225
1226 struct drm_i915_gem_object {
1227 struct drm_gem_object base;
1228
1229 const struct drm_i915_gem_object_ops *ops;
1230
1231 /** Current space allocated to this object in the GTT, if any. */
1232 struct drm_mm_node gtt_space;
1233 /** Stolen memory for this object, instead of being backed by shmem. */
1234 struct drm_mm_node *stolen;
1235 struct list_head global_list;
1236
1237 /** This object's place on the active/inactive lists */
1238 struct list_head ring_list;
1239 struct list_head mm_list;
1240 /** This object's place in the batchbuffer or on the eviction list */
1241 struct list_head exec_list;
1242
1243 /**
1244 * This is set if the object is on the active lists (has pending
1245 * rendering and so a non-zero seqno), and is not set if it i s on
1246 * inactive (ready to be unbound) list.
1247 */
1248 unsigned int active:1;
1249
1250 /**
1251 * This is set if the object has been written to since last bound
1252 * to the GTT
1253 */
1254 unsigned int dirty:1;
1255
1256 /**
1257 * Fence register bits (if any) for this object. Will be set
1258 * as needed when mapped into the GTT.
1259 * Protected by dev->struct_mutex.
1260 */
1261 signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
1262
1263 /**
1264 * Advice: are the backing pages purgeable?
1265 */
1266 unsigned int madv:2;
1267
1268 /**
1269 * Current tiling mode for the object.
1270 */
1271 unsigned int tiling_mode:2;
1272 /**
1273 * Whether the tiling parameters for the currently associated fence
1274 * register have changed. Note that for the purposes of tracking
1275 * tiling changes we also treat the unfenced register, the register
1276 * slot that the object occupies whilst it executes a fenced
1277 * command (such as BLT on gen2/3), as a "fence".
1278 */
1279 unsigned int fence_dirty:1;
1280
1281 /** How many users have pinned this object in GTT space. The following
1282 * users can each hold at most one reference: pwrite/pread, pin_ioctl
1283 * (via user_pin_count), execbuffer (objects are not allowed multiple
1284 * times for the same batchbuffer), and the framebuffer code. When
1285 * switching/pageflipping, the framebuffer code has at most two buffers
1286 * pinned per crtc.
1287 *
1288 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
1289 * bits with absolutely no headroom. So use 4 bits. */
1290 unsigned int pin_count:4;
1291 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
1292
1293 /**
1294 * Is the object at the current location in the gtt mappable and
1295 * fenceable? Used to avoid costly recalculations.
1296 */
1297 unsigned int map_and_fenceable:1;
1298
1299 /**
1300 * Whether the current gtt mapping needs to be mappable (and isn't just
1301 * mappable by accident). Track pin and fault separate for a more
1302 * accurate mappable working set.
1303 */
1304 unsigned int fault_mappable:1;
1305 unsigned int pin_mappable:1;
1306
1307 /*
1308 * Is the GPU currently using a fence to access this buffer,
1309 */
1310 unsigned int pending_fenced_gpu_access:1;
1311 unsigned int fenced_gpu_access:1;
1312
1313 unsigned int cache_level:2;
1314
1315 unsigned int has_aliasing_ppgtt_mapping:1;
1316 unsigned int has_global_gtt_mapping:1;
1317 unsigned int has_dma_mapping:1;
1318
1319 struct sg_table *pages;
1320 int pages_pin_count;
1321
1322 /* prime dma-buf support */
1323 void *dma_buf_vmapping;
1324 int vmapping_count;
1325
1326 /**
1327 * Used for performing relocations during execbuffer insertion.
1328 */
1329 struct hlist_node exec_node;
1330 unsigned long exec_handle;
1331 struct drm_i915_gem_exec_object2 *exec_entry;
1332
1333 struct intel_ring_buffer *ring;
1334
1335 /** Breadcrumb of last rendering to the buffer. */
1336 uint32_t last_read_seqno;
1337 uint32_t last_write_seqno;
1338 /** Breadcrumb of last fenced GPU access to the buffer. */
1339 uint32_t last_fenced_seqno;
1340
1341 /** Current tiling stride for the object, if it's tiled. */
1342 uint32_t stride;
1343
1344 /** Record of address bit 17 of each page at last unbind. */
1345 unsigned long *bit_17;
1346
1347 /** User space pin count and filp owning the pin */
1348 uint32_t user_pin_count;
1349 struct drm_file *pin_filp;
1350
1351 /** for phy allocated objects */
1352 struct drm_i915_gem_phys_object *phys_obj;
1353 };
1354 #define to_gem_object(obj) (&((struct drm_i915_gem_object *)(obj))->base)
1355
1356 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
1357
1358 /* Offset of the first PTE pointing to this object */
1359 static inline unsigned long
1360 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *o)
1361 {
1362 return o->gtt_space.start;
1363 }
1364
1365 /* Whether or not this object is currently mapped by the translation tables */
1366 static inline bool
1367 i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *o)
1368 {
1369 return drm_mm_node_allocated(&o->gtt_space);
1370 }
1371
1372 /* The size used in the translation tables may be larger than the actual size of
1373 * the object on GEN2/GEN3 because of the way tiling is handled. See
1374 * i915_gem_get_gtt_size() for more details.
1375 */
1376 static inline unsigned long
1377 i915_gem_obj_ggtt_size(struct drm_i915_gem_object *o)
1378 {
1379 return o->gtt_space.size;
1380 }
1381
1382 static inline void
1383 i915_gem_obj_ggtt_set_color(struct drm_i915_gem_object *o,
1384 enum i915_cache_level color)
1385 {
1386 o->gtt_space.color = color;
1387 }
1388
1389 /**
1390 * Request queue structure.
1391 *
1392 * The request queue allows us to note sequence numbers that have been emitted
1393 * and may be associated with active buffers to be retired.
1394 *
1395 * By keeping this list, we can avoid having to do questionable
1396 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
1397 * an emission time with seqnos for tracking how far ahead of the GPU we are.
1398 */
1399 struct drm_i915_gem_request {
1400 /** On Which ring this request was generated */
1401 struct intel_ring_buffer *ring;
1402
1403 /** GEM sequence number associated with this request. */
1404 uint32_t seqno;
1405
1406 /** Position in the ringbuffer of the start of the request */
1407 u32 head;
1408
1409 /** Position in the ringbuffer of the end of the request */
1410 u32 tail;
1411
1412 /** Context related to this request */
1413 struct i915_hw_context *ctx;
1414
1415 /** Batch buffer related to this request if any */
1416 struct drm_i915_gem_object *batch_obj;
1417
1418 /** Time at which this request was emitted, in jiffies. */
1419 unsigned long emitted_jiffies;
1420
1421 /** global list entry for this request */
1422 struct list_head list;
1423
1424 struct drm_i915_file_private *file_priv;
1425 /** file_priv list entry for this request */
1426 struct list_head client_list;
1427 };
1428
1429 struct drm_i915_file_private {
1430 struct {
1431 spinlock_t lock;
1432 struct list_head request_list;
1433 } mm;
1434 struct idr context_idr;
1435
1436 struct i915_ctx_hang_stats hang_stats;
1437 };
1438
1439 #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
1440
1441 #define IS_I830(dev) ((dev)->pci_device == 0x3577)
1442 #define IS_845G(dev) ((dev)->pci_device == 0x2562)
1443 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
1444 #define IS_I865G(dev) ((dev)->pci_device == 0x2572)
1445 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
1446 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
1447 #define IS_I945G(dev) ((dev)->pci_device == 0x2772)
1448 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
1449 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
1450 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
1451 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
1452 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
1453 #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001)
1454 #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011)
1455 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
1456 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
1457 #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042)
1458 #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
1459 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
1460 #define IS_IVB_GT1(dev) ((dev)->pci_device == 0x0156 || \
1461 (dev)->pci_device == 0x0152 || \
1462 (dev)->pci_device == 0x015a)
1463 #define IS_SNB_GT1(dev) ((dev)->pci_device == 0x0102 || \
1464 (dev)->pci_device == 0x0106 || \
1465 (dev)->pci_device == 0x010A)
1466 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
1467 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
1468 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
1469 #define IS_ULT(dev) (IS_HASWELL(dev) && \
1470 ((dev)->pci_device & 0xFF00) == 0x0A00)
1471
1472 /*
1473 * The genX designation typically refers to the render engine, so render
1474 * capability related checks should use IS_GEN, while display and other checks
1475 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
1476 * chips, etc.).
1477 */
1478 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
1479 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
1480 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
1481 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
1482 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
1483 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
1484
1485 #define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring)
1486 #define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring)
1487 #define HAS_VEBOX(dev) (INTEL_INFO(dev)->has_vebox_ring)
1488 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
1489 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
1490
1491 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
1492 #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6 && !IS_VALLEYVIEW(dev))
1493
1494 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
1495 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
1496
1497 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
1498 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
1499
1500 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1501 * rows, which changed the alignment requirements and fence programming.
1502 */
1503 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
1504 IS_I915GM(dev)))
1505 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
1506 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
1507 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
1508 #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev))
1509 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
1510 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
1511 /* dsparb controlled by hw only */
1512 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1513
1514 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
1515 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
1516 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
1517
1518 #define HAS_IPS(dev) (IS_ULT(dev))
1519
1520 #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5)
1521
1522 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
1523 #define HAS_POWER_WELL(dev) (IS_HASWELL(dev))
1524 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
1525
1526 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
1527 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
1528 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
1529 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
1530 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
1531 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
1532
1533 #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
1534 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
1535 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
1536 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
1537 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
1538 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
1539
1540 #define HAS_FORCE_WAKE(dev) (INTEL_INFO(dev)->has_force_wake)
1541
1542 #define HAS_L3_GPU_CACHE(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1543
1544 #define GT_FREQUENCY_MULTIPLIER 50
1545
1546 #include "i915_trace.h"
1547
1548 /**
1549 * RC6 is a special power stage which allows the GPU to enter an very
1550 * low-voltage mode when idle, using down to 0V while at this stage. This
1551 * stage is entered automatically when the GPU is idle when RC6 support is
1552 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
1553 *
1554 * There are different RC6 modes available in Intel GPU, which differentiate
1555 * among each other with the latency required to enter and leave RC6 and
1556 * voltage consumed by the GPU in different states.
1557 *
1558 * The combination of the following flags define which states GPU is allowed
1559 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
1560 * RC6pp is deepest RC6. Their support by hardware varies according to the
1561 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
1562 * which brings the most power savings; deeper states save more power, but
1563 * require higher latency to switch to and wake up.
1564 */
1565 #define INTEL_RC6_ENABLE (1<<0)
1566 #define INTEL_RC6p_ENABLE (1<<1)
1567 #define INTEL_RC6pp_ENABLE (1<<2)
1568
1569 extern struct drm_ioctl_desc i915_ioctls[];
1570 extern int i915_max_ioctl;
1571 extern unsigned int i915_fbpercrtc __always_unused;
1572 extern int i915_panel_ignore_lid __read_mostly;
1573 extern unsigned int i915_powersave __read_mostly;
1574 extern int i915_semaphores __read_mostly;
1575 extern unsigned int i915_lvds_downclock __read_mostly;
1576 extern int i915_lvds_channel_mode __read_mostly;
1577 extern int i915_panel_use_ssc __read_mostly;
1578 extern int i915_vbt_sdvo_panel_type __read_mostly;
1579 extern int i915_enable_rc6 __read_mostly;
1580 extern int i915_enable_fbc __read_mostly;
1581 extern bool i915_enable_hangcheck __read_mostly;
1582 extern int i915_enable_ppgtt __read_mostly;
1583 extern unsigned int i915_preliminary_hw_support __read_mostly;
1584 extern int i915_disable_power_well __read_mostly;
1585 extern int i915_enable_ips __read_mostly;
1586 extern bool i915_fastboot __read_mostly;
1587
1588 extern int i915_suspend(struct drm_device *dev, pm_message_t state);
1589 extern int i915_resume(struct drm_device *dev);
1590 extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
1591 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
1592
1593 /* i915_dma.c */
1594 void i915_update_dri1_breadcrumb(struct drm_device *dev);
1595 extern void i915_kernel_lost_context(struct drm_device * dev);
1596 extern int i915_driver_load(struct drm_device *, unsigned long flags);
1597 extern int i915_driver_unload(struct drm_device *);
1598 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
1599 extern void i915_driver_lastclose(struct drm_device * dev);
1600 extern void i915_driver_preclose(struct drm_device *dev,
1601 struct drm_file *file_priv);
1602 extern void i915_driver_postclose(struct drm_device *dev,
1603 struct drm_file *file_priv);
1604 extern int i915_driver_device_is_agp(struct drm_device * dev);
1605 #ifdef CONFIG_COMPAT
1606 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
1607 unsigned long arg);
1608 #endif
1609 extern int i915_emit_box(struct drm_device *dev,
1610 struct drm_clip_rect *box,
1611 int DR1, int DR4);
1612 extern int intel_gpu_reset(struct drm_device *dev);
1613 extern int i915_reset(struct drm_device *dev);
1614 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
1615 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
1616 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
1617 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
1618
1619 extern void intel_console_resume(struct work_struct *work);
1620
1621 /* i915_irq.c */
1622 void i915_hangcheck_elapsed(unsigned long data);
1623 void i915_handle_error(struct drm_device *dev, bool wedged);
1624
1625 extern void intel_irq_init(struct drm_device *dev);
1626 extern void intel_hpd_init(struct drm_device *dev);
1627 extern void intel_gt_init(struct drm_device *dev);
1628 extern void intel_gt_reset(struct drm_device *dev);
1629
1630 void
1631 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1632
1633 void
1634 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1635
1636 /* i915_gem.c */
1637 int i915_gem_init_ioctl(struct drm_device *dev, void *data,
1638 struct drm_file *file_priv);
1639 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
1640 struct drm_file *file_priv);
1641 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
1642 struct drm_file *file_priv);
1643 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1644 struct drm_file *file_priv);
1645 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1646 struct drm_file *file_priv);
1647 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1648 struct drm_file *file_priv);
1649 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1650 struct drm_file *file_priv);
1651 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1652 struct drm_file *file_priv);
1653 int i915_gem_execbuffer(struct drm_device *dev, void *data,
1654 struct drm_file *file_priv);
1655 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
1656 struct drm_file *file_priv);
1657 int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
1658 struct drm_file *file_priv);
1659 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
1660 struct drm_file *file_priv);
1661 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
1662 struct drm_file *file_priv);
1663 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
1664 struct drm_file *file);
1665 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
1666 struct drm_file *file);
1667 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
1668 struct drm_file *file_priv);
1669 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
1670 struct drm_file *file_priv);
1671 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
1672 struct drm_file *file_priv);
1673 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
1674 struct drm_file *file_priv);
1675 int i915_gem_set_tiling(struct drm_device *dev, void *data,
1676 struct drm_file *file_priv);
1677 int i915_gem_get_tiling(struct drm_device *dev, void *data,
1678 struct drm_file *file_priv);
1679 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
1680 struct drm_file *file_priv);
1681 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
1682 struct drm_file *file_priv);
1683 void i915_gem_load(struct drm_device *dev);
1684 void *i915_gem_object_alloc(struct drm_device *dev);
1685 void i915_gem_object_free(struct drm_i915_gem_object *obj);
1686 int i915_gem_init_object(struct drm_gem_object *obj);
1687 void i915_gem_object_init(struct drm_i915_gem_object *obj,
1688 const struct drm_i915_gem_object_ops *ops);
1689 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
1690 size_t size);
1691 void i915_gem_free_object(struct drm_gem_object *obj);
1692
1693 int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
1694 uint32_t alignment,
1695 bool map_and_fenceable,
1696 bool nonblocking);
1697 void i915_gem_object_unpin(struct drm_i915_gem_object *obj);
1698 int __must_check i915_gem_object_unbind(struct drm_i915_gem_object *obj);
1699 int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
1700 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
1701 void i915_gem_lastclose(struct drm_device *dev);
1702
1703 int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
1704 static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
1705 {
1706 struct sg_page_iter sg_iter;
1707
1708 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, n)
1709 return sg_page_iter_page(&sg_iter);
1710
1711 return NULL;
1712 }
1713 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
1714 {
1715 BUG_ON(obj->pages == NULL);
1716 obj->pages_pin_count++;
1717 }
1718 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
1719 {
1720 BUG_ON(obj->pages_pin_count == 0);
1721 obj->pages_pin_count--;
1722 }
1723
1724 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
1725 int i915_gem_object_sync(struct drm_i915_gem_object *obj,
1726 struct intel_ring_buffer *to);
1727 void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1728 struct intel_ring_buffer *ring);
1729
1730 int i915_gem_dumb_create(struct drm_file *file_priv,
1731 struct drm_device *dev,
1732 struct drm_mode_create_dumb *args);
1733 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
1734 uint32_t handle, uint64_t *offset);
1735 int i915_gem_dumb_destroy(struct drm_file *file_priv, struct drm_device *dev,
1736 uint32_t handle);
1737 /**
1738 * Returns true if seq1 is later than seq2.
1739 */
1740 static inline bool
1741 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1742 {
1743 return (int32_t)(seq1 - seq2) >= 0;
1744 }
1745
1746 int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
1747 int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
1748 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
1749 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
1750
1751 static inline bool
1752 i915_gem_object_pin_fence(struct drm_i915_gem_object *obj)
1753 {
1754 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1755 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1756 dev_priv->fence_regs[obj->fence_reg].pin_count++;
1757 return true;
1758 } else
1759 return false;
1760 }
1761
1762 static inline void
1763 i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
1764 {
1765 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1766 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1767 WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0);
1768 dev_priv->fence_regs[obj->fence_reg].pin_count--;
1769 }
1770 }
1771
1772 void i915_gem_retire_requests(struct drm_device *dev);
1773 void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring);
1774 int __must_check i915_gem_check_wedge(struct i915_gpu_error *error,
1775 bool interruptible);
1776 static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
1777 {
1778 return unlikely(atomic_read(&error->reset_counter)
1779 & I915_RESET_IN_PROGRESS_FLAG);
1780 }
1781
1782 static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
1783 {
1784 return atomic_read(&error->reset_counter) == I915_WEDGED;
1785 }
1786
1787 void i915_gem_reset(struct drm_device *dev);
1788 void i915_gem_clflush_object(struct drm_i915_gem_object *obj);
1789 int __must_check i915_gem_object_set_domain(struct drm_i915_gem_object *obj,
1790 uint32_t read_domains,
1791 uint32_t write_domain);
1792 int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
1793 int __must_check i915_gem_init(struct drm_device *dev);
1794 int __must_check i915_gem_init_hw(struct drm_device *dev);
1795 void i915_gem_l3_remap(struct drm_device *dev);
1796 void i915_gem_init_swizzling(struct drm_device *dev);
1797 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
1798 int __must_check i915_gpu_idle(struct drm_device *dev);
1799 int __must_check i915_gem_idle(struct drm_device *dev);
1800 int __i915_add_request(struct intel_ring_buffer *ring,
1801 struct drm_file *file,
1802 struct drm_i915_gem_object *batch_obj,
1803 u32 *seqno);
1804 #define i915_add_request(ring, seqno) \
1805 __i915_add_request(ring, NULL, NULL, seqno)
1806 int __must_check i915_wait_seqno(struct intel_ring_buffer *ring,
1807 uint32_t seqno);
1808 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
1809 int __must_check
1810 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
1811 bool write);
1812 int __must_check
1813 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
1814 int __must_check
1815 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
1816 u32 alignment,
1817 struct intel_ring_buffer *pipelined);
1818 int i915_gem_attach_phys_object(struct drm_device *dev,
1819 struct drm_i915_gem_object *obj,
1820 int id,
1821 int align);
1822 void i915_gem_detach_phys_object(struct drm_device *dev,
1823 struct drm_i915_gem_object *obj);
1824 void i915_gem_free_all_phys_object(struct drm_device *dev);
1825 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
1826
1827 uint32_t
1828 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
1829 uint32_t
1830 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
1831 int tiling_mode, bool fenced);
1832
1833 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
1834 enum i915_cache_level cache_level);
1835
1836 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
1837 struct dma_buf *dma_buf);
1838
1839 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
1840 struct drm_gem_object *gem_obj, int flags);
1841
1842 /* i915_gem_context.c */
1843 void i915_gem_context_init(struct drm_device *dev);
1844 void i915_gem_context_fini(struct drm_device *dev);
1845 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
1846 int i915_switch_context(struct intel_ring_buffer *ring,
1847 struct drm_file *file, int to_id);
1848 void i915_gem_context_free(struct kref *ctx_ref);
1849 static inline void i915_gem_context_reference(struct i915_hw_context *ctx)
1850 {
1851 kref_get(&ctx->ref);
1852 }
1853
1854 static inline void i915_gem_context_unreference(struct i915_hw_context *ctx)
1855 {
1856 kref_put(&ctx->ref, i915_gem_context_free);
1857 }
1858
1859 struct i915_ctx_hang_stats * __must_check
1860 i915_gem_context_get_hang_stats(struct intel_ring_buffer *ring,
1861 struct drm_file *file,
1862 u32 id);
1863 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
1864 struct drm_file *file);
1865 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
1866 struct drm_file *file);
1867
1868 /* i915_gem_gtt.c */
1869 void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev);
1870 void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt,
1871 struct drm_i915_gem_object *obj,
1872 enum i915_cache_level cache_level);
1873 void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt,
1874 struct drm_i915_gem_object *obj);
1875
1876 void i915_gem_restore_gtt_mappings(struct drm_device *dev);
1877 int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj);
1878 void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj,
1879 enum i915_cache_level cache_level);
1880 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj);
1881 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj);
1882 void i915_gem_init_global_gtt(struct drm_device *dev);
1883 void i915_gem_setup_global_gtt(struct drm_device *dev, unsigned long start,
1884 unsigned long mappable_end, unsigned long end);
1885 int i915_gem_gtt_init(struct drm_device *dev);
1886 static inline void i915_gem_chipset_flush(struct drm_device *dev)
1887 {
1888 if (INTEL_INFO(dev)->gen < 6)
1889 intel_gtt_chipset_flush();
1890 }
1891
1892
1893 /* i915_gem_evict.c */
1894 int __must_check i915_gem_evict_something(struct drm_device *dev, int min_size,
1895 unsigned alignment,
1896 unsigned cache_level,
1897 bool mappable,
1898 bool nonblock);
1899 int i915_gem_evict_everything(struct drm_device *dev);
1900
1901 /* i915_gem_stolen.c */
1902 int i915_gem_init_stolen(struct drm_device *dev);
1903 int i915_gem_stolen_setup_compression(struct drm_device *dev, int size);
1904 void i915_gem_stolen_cleanup_compression(struct drm_device *dev);
1905 void i915_gem_cleanup_stolen(struct drm_device *dev);
1906 struct drm_i915_gem_object *
1907 i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
1908 struct drm_i915_gem_object *
1909 i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
1910 u32 stolen_offset,
1911 u32 gtt_offset,
1912 u32 size);
1913 void i915_gem_object_release_stolen(struct drm_i915_gem_object *obj);
1914
1915 /* i915_gem_tiling.c */
1916 inline static bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
1917 {
1918 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
1919
1920 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
1921 obj->tiling_mode != I915_TILING_NONE;
1922 }
1923
1924 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
1925 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
1926 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
1927
1928 /* i915_gem_debug.c */
1929 void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
1930 const char *where, uint32_t mark);
1931 #if WATCH_LISTS
1932 int i915_verify_lists(struct drm_device *dev);
1933 #else
1934 #define i915_verify_lists(dev) 0
1935 #endif
1936 void i915_gem_object_check_coherency(struct drm_i915_gem_object *obj,
1937 int handle);
1938 void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
1939 const char *where, uint32_t mark);
1940
1941 /* i915_debugfs.c */
1942 int i915_debugfs_init(struct drm_minor *minor);
1943 void i915_debugfs_cleanup(struct drm_minor *minor);
1944
1945 /* i915_gpu_error.c */
1946 __printf(2, 3)
1947 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
1948 int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
1949 const struct i915_error_state_file_priv *error);
1950 int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
1951 size_t count, loff_t pos);
1952 static inline void i915_error_state_buf_release(
1953 struct drm_i915_error_state_buf *eb)
1954 {
1955 kfree(eb->buf);
1956 }
1957 void i915_capture_error_state(struct drm_device *dev);
1958 void i915_error_state_get(struct drm_device *dev,
1959 struct i915_error_state_file_priv *error_priv);
1960 void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
1961 void i915_destroy_error_state(struct drm_device *dev);
1962
1963 void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone);
1964 const char *i915_cache_level_str(int type);
1965
1966 /* i915_suspend.c */
1967 extern int i915_save_state(struct drm_device *dev);
1968 extern int i915_restore_state(struct drm_device *dev);
1969
1970 /* i915_ums.c */
1971 void i915_save_display_reg(struct drm_device *dev);
1972 void i915_restore_display_reg(struct drm_device *dev);
1973
1974 /* i915_sysfs.c */
1975 void i915_setup_sysfs(struct drm_device *dev_priv);
1976 void i915_teardown_sysfs(struct drm_device *dev_priv);
1977
1978 /* intel_i2c.c */
1979 extern int intel_setup_gmbus(struct drm_device *dev);
1980 extern void intel_teardown_gmbus(struct drm_device *dev);
1981 static inline bool intel_gmbus_is_port_valid(unsigned port)
1982 {
1983 return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD);
1984 }
1985
1986 extern struct i2c_adapter *intel_gmbus_get_adapter(
1987 struct drm_i915_private *dev_priv, unsigned port);
1988 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
1989 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
1990 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
1991 {
1992 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
1993 }
1994 extern void intel_i2c_reset(struct drm_device *dev);
1995
1996 /* intel_opregion.c */
1997 extern int intel_opregion_setup(struct drm_device *dev);
1998 #ifdef CONFIG_ACPI
1999 extern void intel_opregion_init(struct drm_device *dev);
2000 extern void intel_opregion_fini(struct drm_device *dev);
2001 extern void intel_opregion_asle_intr(struct drm_device *dev);
2002 #else
2003 static inline void intel_opregion_init(struct drm_device *dev) { return; }
2004 static inline void intel_opregion_fini(struct drm_device *dev) { return; }
2005 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
2006 #endif
2007
2008 /* intel_acpi.c */
2009 #ifdef CONFIG_ACPI
2010 extern void intel_register_dsm_handler(void);
2011 extern void intel_unregister_dsm_handler(void);
2012 #else
2013 static inline void intel_register_dsm_handler(void) { return; }
2014 static inline void intel_unregister_dsm_handler(void) { return; }
2015 #endif /* CONFIG_ACPI */
2016
2017 /* modesetting */
2018 extern void intel_modeset_init_hw(struct drm_device *dev);
2019 extern void intel_modeset_suspend_hw(struct drm_device *dev);
2020 extern void intel_modeset_init(struct drm_device *dev);
2021 extern void intel_modeset_gem_init(struct drm_device *dev);
2022 extern void intel_modeset_cleanup(struct drm_device *dev);
2023 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
2024 extern void intel_modeset_setup_hw_state(struct drm_device *dev,
2025 bool force_restore);
2026 extern void i915_redisable_vga(struct drm_device *dev);
2027 extern bool intel_fbc_enabled(struct drm_device *dev);
2028 extern void intel_disable_fbc(struct drm_device *dev);
2029 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
2030 extern void intel_init_pch_refclk(struct drm_device *dev);
2031 extern void gen6_set_rps(struct drm_device *dev, u8 val);
2032 extern void valleyview_set_rps(struct drm_device *dev, u8 val);
2033 extern int valleyview_rps_max_freq(struct drm_i915_private *dev_priv);
2034 extern int valleyview_rps_min_freq(struct drm_i915_private *dev_priv);
2035 extern void intel_detect_pch(struct drm_device *dev);
2036 extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
2037 extern int intel_enable_rc6(const struct drm_device *dev);
2038
2039 extern bool i915_semaphore_is_enabled(struct drm_device *dev);
2040 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
2041 struct drm_file *file);
2042
2043 /* overlay */
2044 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
2045 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
2046 struct intel_overlay_error_state *error);
2047
2048 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
2049 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
2050 struct drm_device *dev,
2051 struct intel_display_error_state *error);
2052
2053 /* On SNB platform, before reading ring registers forcewake bit
2054 * must be set to prevent GT core from power down and stale values being
2055 * returned.
2056 */
2057 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);
2058 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);
2059 int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv);
2060
2061 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val);
2062 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val);
2063
2064 /* intel_sideband.c */
2065 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr);
2066 void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val);
2067 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
2068 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, int reg);
2069 void vlv_dpio_write(struct drm_i915_private *dev_priv, int reg, u32 val);
2070 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
2071 enum intel_sbi_destination destination);
2072 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
2073 enum intel_sbi_destination destination);
2074
2075 int vlv_gpu_freq(int ddr_freq, int val);
2076 int vlv_freq_opcode(int ddr_freq, int val);
2077
2078 #define __i915_read(x, y) \
2079 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg);
2080
2081 __i915_read(8, b)
2082 __i915_read(16, w)
2083 __i915_read(32, l)
2084 __i915_read(64, q)
2085 #undef __i915_read
2086
2087 #define __i915_write(x, y) \
2088 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val);
2089
2090 __i915_write(8, b)
2091 __i915_write(16, w)
2092 __i915_write(32, l)
2093 __i915_write(64, q)
2094 #undef __i915_write
2095
2096 #define I915_READ8(reg) i915_read8(dev_priv, (reg))
2097 #define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val))
2098
2099 #define I915_READ16(reg) i915_read16(dev_priv, (reg))
2100 #define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val))
2101 #define I915_READ16_NOTRACE(reg) readw(dev_priv->regs + (reg))
2102 #define I915_WRITE16_NOTRACE(reg, val) writew(val, dev_priv->regs + (reg))
2103
2104 #define I915_READ(reg) i915_read32(dev_priv, (reg))
2105 #define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val))
2106 #define I915_READ_NOTRACE(reg) readl(dev_priv->regs + (reg))
2107 #define I915_WRITE_NOTRACE(reg, val) writel(val, dev_priv->regs + (reg))
2108
2109 #define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val))
2110 #define I915_READ64(reg) i915_read64(dev_priv, (reg))
2111
2112 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
2113 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
2114
2115 /* "Broadcast RGB" property */
2116 #define INTEL_BROADCAST_RGB_AUTO 0
2117 #define INTEL_BROADCAST_RGB_FULL 1
2118 #define INTEL_BROADCAST_RGB_LIMITED 2
2119
2120 static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev)
2121 {
2122 if (HAS_PCH_SPLIT(dev))
2123 return CPU_VGACNTRL;
2124 else if (IS_VALLEYVIEW(dev))
2125 return VLV_VGACNTRL;
2126 else
2127 return VGACNTRL;
2128 }
2129
2130 static inline void __user *to_user_ptr(u64 address)
2131 {
2132 return (void __user *)(uintptr_t)address;
2133 }
2134
2135 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
2136 {
2137 unsigned long j = msecs_to_jiffies(m);
2138
2139 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
2140 }
2141
2142 static inline unsigned long
2143 timespec_to_jiffies_timeout(const struct timespec *value)
2144 {
2145 unsigned long j = timespec_to_jiffies(value);
2146
2147 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
2148 }
2149
2150 #endif
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