1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
36 #include "intel_bios.h"
37 #include "intel_ringbuffer.h"
38 #include <linux/io-mapping.h>
39 #include <linux/i2c.h>
40 #include <linux/i2c-algo-bit.h>
41 #include <drm/intel-gtt.h>
42 #include <linux/backlight.h>
43 #include <linux/intel-iommu.h>
44 #include <linux/kref.h>
45 #include <linux/pm_qos.h>
47 /* General customization:
50 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
52 #define DRIVER_NAME "i915"
53 #define DRIVER_DESC "Intel Graphics"
54 #define DRIVER_DATE "20080730"
62 #define pipe_name(p) ((p) + 'A')
70 #define transcoder_name(t) ((t) + 'A')
77 #define plane_name(p) ((p) + 'A')
79 #define sprite_name(p, s) ((p) * dev_priv->num_plane + (s) + 'A')
89 #define port_name(p) ((p) + 'A')
91 enum intel_display_power_domain
{
95 POWER_DOMAIN_PIPE_A_PANEL_FITTER
,
96 POWER_DOMAIN_PIPE_B_PANEL_FITTER
,
97 POWER_DOMAIN_PIPE_C_PANEL_FITTER
,
98 POWER_DOMAIN_TRANSCODER_A
,
99 POWER_DOMAIN_TRANSCODER_B
,
100 POWER_DOMAIN_TRANSCODER_C
,
101 POWER_DOMAIN_TRANSCODER_EDP
= POWER_DOMAIN_TRANSCODER_A
+ 0xF,
105 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
106 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
107 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
108 #define POWER_DOMAIN_TRANSCODER(tran) ((tran) + POWER_DOMAIN_TRANSCODER_A)
112 HPD_PORT_A
= HPD_NONE
, /* PORT_A is internal */
113 HPD_TV
= HPD_NONE
, /* TV is known to be unreliable */
123 #define I915_GEM_GPU_DOMAINS \
124 (I915_GEM_DOMAIN_RENDER | \
125 I915_GEM_DOMAIN_SAMPLER | \
126 I915_GEM_DOMAIN_COMMAND | \
127 I915_GEM_DOMAIN_INSTRUCTION | \
128 I915_GEM_DOMAIN_VERTEX)
130 #define for_each_pipe(p) for ((p) = 0; (p) < INTEL_INFO(dev)->num_pipes; (p)++)
132 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
133 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
134 if ((intel_encoder)->base.crtc == (__crtc))
136 struct drm_i915_private
;
139 DPLL_ID_PRIVATE
= -1, /* non-shared dpll in use */
140 /* real shared dpll ids must be >= 0 */
144 #define I915_NUM_PLLS 2
146 struct intel_dpll_hw_state
{
153 struct intel_shared_dpll
{
154 int refcount
; /* count of number of CRTCs sharing this PLL */
155 int active
; /* count of number of active CRTCs (i.e. DPMS on) */
156 bool on
; /* is the PLL actually active? Disabled during modeset */
158 /* should match the index in the dev_priv->shared_dplls array */
159 enum intel_dpll_id id
;
160 struct intel_dpll_hw_state hw_state
;
161 void (*mode_set
)(struct drm_i915_private
*dev_priv
,
162 struct intel_shared_dpll
*pll
);
163 void (*enable
)(struct drm_i915_private
*dev_priv
,
164 struct intel_shared_dpll
*pll
);
165 void (*disable
)(struct drm_i915_private
*dev_priv
,
166 struct intel_shared_dpll
*pll
);
167 bool (*get_hw_state
)(struct drm_i915_private
*dev_priv
,
168 struct intel_shared_dpll
*pll
,
169 struct intel_dpll_hw_state
*hw_state
);
172 /* Used by dp and fdi links */
173 struct intel_link_m_n
{
181 void intel_link_compute_m_n(int bpp
, int nlanes
,
182 int pixel_clock
, int link_clock
,
183 struct intel_link_m_n
*m_n
);
185 struct intel_ddi_plls
{
191 /* Interface history:
194 * 1.2: Add Power Management
195 * 1.3: Add vblank support
196 * 1.4: Fix cmdbuffer path, add heap destroy
197 * 1.5: Add vblank pipe configuration
198 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
199 * - Support vertical blank on secondary display pipe
201 #define DRIVER_MAJOR 1
202 #define DRIVER_MINOR 6
203 #define DRIVER_PATCHLEVEL 0
205 #define WATCH_LISTS 0
208 #define I915_GEM_PHYS_CURSOR_0 1
209 #define I915_GEM_PHYS_CURSOR_1 2
210 #define I915_GEM_PHYS_OVERLAY_REGS 3
211 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
213 struct drm_i915_gem_phys_object
{
215 struct page
**page_list
;
216 drm_dma_handle_t
*handle
;
217 struct drm_i915_gem_object
*cur_obj
;
220 struct opregion_header
;
221 struct opregion_acpi
;
222 struct opregion_swsci
;
223 struct opregion_asle
;
225 struct intel_opregion
{
226 struct opregion_header __iomem
*header
;
227 struct opregion_acpi __iomem
*acpi
;
228 struct opregion_swsci __iomem
*swsci
;
229 u32 swsci_gbda_sub_functions
;
230 u32 swsci_sbcb_sub_functions
;
231 struct opregion_asle __iomem
*asle
;
233 u32 __iomem
*lid_state
;
235 #define OPREGION_SIZE (8*1024)
237 struct intel_overlay
;
238 struct intel_overlay_error_state
;
240 struct drm_i915_master_private
{
241 drm_local_map_t
*sarea
;
242 struct _drm_i915_sarea
*sarea_priv
;
244 #define I915_FENCE_REG_NONE -1
245 #define I915_MAX_NUM_FENCES 32
246 /* 32 fences + sign bit for FENCE_REG_NONE */
247 #define I915_MAX_NUM_FENCE_BITS 6
249 struct drm_i915_fence_reg
{
250 struct list_head lru_list
;
251 struct drm_i915_gem_object
*obj
;
255 struct sdvo_device_mapping
{
264 struct intel_display_error_state
;
266 struct drm_i915_error_state
{
274 bool waiting
[I915_NUM_RINGS
];
275 u32 pipestat
[I915_MAX_PIPES
];
276 u32 tail
[I915_NUM_RINGS
];
277 u32 head
[I915_NUM_RINGS
];
278 u32 ctl
[I915_NUM_RINGS
];
279 u32 ipeir
[I915_NUM_RINGS
];
280 u32 ipehr
[I915_NUM_RINGS
];
281 u32 instdone
[I915_NUM_RINGS
];
282 u32 acthd
[I915_NUM_RINGS
];
283 u32 semaphore_mboxes
[I915_NUM_RINGS
][I915_NUM_RINGS
- 1];
284 u32 semaphore_seqno
[I915_NUM_RINGS
][I915_NUM_RINGS
- 1];
285 u32 rc_psmi
[I915_NUM_RINGS
]; /* sleep state */
286 /* our own tracking of ring head and tail */
287 u32 cpu_ring_head
[I915_NUM_RINGS
];
288 u32 cpu_ring_tail
[I915_NUM_RINGS
];
289 u32 error
; /* gen6+ */
290 u32 err_int
; /* gen7 */
291 u32 instpm
[I915_NUM_RINGS
];
292 u32 instps
[I915_NUM_RINGS
];
293 u32 extra_instdone
[I915_NUM_INSTDONE_REG
];
294 u32 seqno
[I915_NUM_RINGS
];
296 u32 fault_reg
[I915_NUM_RINGS
];
298 u32 faddr
[I915_NUM_RINGS
];
299 u64 fence
[I915_MAX_NUM_FENCES
];
301 struct drm_i915_error_ring
{
302 struct drm_i915_error_object
{
306 } *ringbuffer
, *batchbuffer
, *ctx
;
307 struct drm_i915_error_request
{
313 } ring
[I915_NUM_RINGS
];
314 struct drm_i915_error_buffer
{
321 s32 fence_reg
:I915_MAX_NUM_FENCE_BITS
;
328 } **active_bo
, **pinned_bo
;
329 u32
*active_bo_count
, *pinned_bo_count
;
330 struct intel_overlay_error_state
*overlay
;
331 struct intel_display_error_state
*display
;
332 int hangcheck_score
[I915_NUM_RINGS
];
333 enum intel_ring_hangcheck_action hangcheck_action
[I915_NUM_RINGS
];
336 struct intel_crtc_config
;
341 struct drm_i915_display_funcs
{
342 bool (*fbc_enabled
)(struct drm_device
*dev
);
343 void (*enable_fbc
)(struct drm_crtc
*crtc
, unsigned long interval
);
344 void (*disable_fbc
)(struct drm_device
*dev
);
345 int (*get_display_clock_speed
)(struct drm_device
*dev
);
346 int (*get_fifo_size
)(struct drm_device
*dev
, int plane
);
348 * find_dpll() - Find the best values for the PLL
349 * @limit: limits for the PLL
350 * @crtc: current CRTC
351 * @target: target frequency in kHz
352 * @refclk: reference clock frequency in kHz
353 * @match_clock: if provided, @best_clock P divider must
354 * match the P divider from @match_clock
355 * used for LVDS downclocking
356 * @best_clock: best PLL values found
358 * Returns true on success, false on failure.
360 bool (*find_dpll
)(const struct intel_limit
*limit
,
361 struct drm_crtc
*crtc
,
362 int target
, int refclk
,
363 struct dpll
*match_clock
,
364 struct dpll
*best_clock
);
365 void (*update_wm
)(struct drm_crtc
*crtc
);
366 void (*update_sprite_wm
)(struct drm_plane
*plane
,
367 struct drm_crtc
*crtc
,
368 uint32_t sprite_width
, int pixel_size
,
369 bool enable
, bool scaled
);
370 void (*modeset_global_resources
)(struct drm_device
*dev
);
371 /* Returns the active state of the crtc, and if the crtc is active,
372 * fills out the pipe-config with the hw state. */
373 bool (*get_pipe_config
)(struct intel_crtc
*,
374 struct intel_crtc_config
*);
375 int (*crtc_mode_set
)(struct drm_crtc
*crtc
,
377 struct drm_framebuffer
*old_fb
);
378 void (*crtc_enable
)(struct drm_crtc
*crtc
);
379 void (*crtc_disable
)(struct drm_crtc
*crtc
);
380 void (*off
)(struct drm_crtc
*crtc
);
381 void (*write_eld
)(struct drm_connector
*connector
,
382 struct drm_crtc
*crtc
);
383 void (*fdi_link_train
)(struct drm_crtc
*crtc
);
384 void (*init_clock_gating
)(struct drm_device
*dev
);
385 int (*queue_flip
)(struct drm_device
*dev
, struct drm_crtc
*crtc
,
386 struct drm_framebuffer
*fb
,
387 struct drm_i915_gem_object
*obj
,
389 int (*update_plane
)(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
391 void (*hpd_irq_setup
)(struct drm_device
*dev
);
392 /* clock updates for mode set */
394 /* render clock increase/decrease */
395 /* display clock increase/decrease */
396 /* pll clock increase/decrease */
399 struct intel_uncore_funcs
{
400 void (*force_wake_get
)(struct drm_i915_private
*dev_priv
);
401 void (*force_wake_put
)(struct drm_i915_private
*dev_priv
);
404 struct intel_uncore
{
405 spinlock_t lock
; /** lock is also taken in irq contexts. */
407 struct intel_uncore_funcs funcs
;
410 unsigned forcewake_count
;
412 struct delayed_work force_wake_work
;
415 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
416 func(is_mobile) sep \
419 func(is_i945gm) sep \
421 func(need_gfx_hws) sep \
423 func(is_pineview) sep \
424 func(is_broadwater) sep \
425 func(is_crestline) sep \
426 func(is_ivybridge) sep \
427 func(is_valleyview) sep \
428 func(is_haswell) sep \
429 func(is_preliminary) sep \
430 func(has_force_wake) sep \
432 func(has_pipe_cxsr) sep \
433 func(has_hotplug) sep \
434 func(cursor_needs_physical) sep \
435 func(has_overlay) sep \
436 func(overlay_needs_physical) sep \
437 func(supports_tv) sep \
438 func(has_bsd_ring) sep \
439 func(has_blt_ring) sep \
440 func(has_vebox_ring) sep \
445 #define DEFINE_FLAG(name) u8 name:1
446 #define SEP_SEMICOLON ;
448 struct intel_device_info
{
449 u32 display_mmio_offset
;
452 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG
, SEP_SEMICOLON
);
458 enum i915_cache_level
{
460 I915_CACHE_LLC
, /* also used for snoopable memory on non-LLC */
461 I915_CACHE_L3_LLC
, /* gen7+, L3 sits between the domain specifc
462 caches, eg sampler/render caches, and the
463 large Last-Level-Cache. LLC is coherent with
464 the CPU, but L3 is only visible to the GPU. */
465 I915_CACHE_WT
, /* hsw:gt3e WriteThrough for scanouts */
468 typedef uint32_t gen6_gtt_pte_t
;
470 struct i915_address_space
{
472 struct drm_device
*dev
;
473 struct list_head global_link
;
474 unsigned long start
; /* Start offset always 0 for dri2 */
475 size_t total
; /* size addr space maps (ex. 2GB for ggtt) */
483 * List of objects currently involved in rendering.
485 * Includes buffers having the contents of their GPU caches
486 * flushed, not necessarily primitives. last_rendering_seqno
487 * represents when the rendering involved will be completed.
489 * A reference is held on the buffer while on this list.
491 struct list_head active_list
;
494 * LRU list of objects which are not in the ringbuffer and
495 * are ready to unbind, but are still in the GTT.
497 * last_rendering_seqno is 0 while an object is in this list.
499 * A reference is not held on the buffer while on this list,
500 * as merely being GTT-bound shouldn't prevent its being
501 * freed, and we'll pull it off the list in the free path.
503 struct list_head inactive_list
;
505 /* FIXME: Need a more generic return type */
506 gen6_gtt_pte_t (*pte_encode
)(dma_addr_t addr
,
507 enum i915_cache_level level
);
508 void (*clear_range
)(struct i915_address_space
*vm
,
509 unsigned int first_entry
,
510 unsigned int num_entries
);
511 void (*insert_entries
)(struct i915_address_space
*vm
,
513 unsigned int first_entry
,
514 enum i915_cache_level cache_level
);
515 void (*cleanup
)(struct i915_address_space
*vm
);
518 /* The Graphics Translation Table is the way in which GEN hardware translates a
519 * Graphics Virtual Address into a Physical Address. In addition to the normal
520 * collateral associated with any va->pa translations GEN hardware also has a
521 * portion of the GTT which can be mapped by the CPU and remain both coherent
522 * and correct (in cases like swizzling). That region is referred to as GMADR in
526 struct i915_address_space base
;
527 size_t stolen_size
; /* Total size of stolen memory */
529 unsigned long mappable_end
; /* End offset that we can CPU map */
530 struct io_mapping
*mappable
; /* Mapping to our CPU mappable region */
531 phys_addr_t mappable_base
; /* PA of our GMADR */
533 /** "Graphics Stolen Memory" holds the global PTEs */
541 int (*gtt_probe
)(struct drm_device
*dev
, size_t *gtt_total
,
542 size_t *stolen
, phys_addr_t
*mappable_base
,
543 unsigned long *mappable_end
);
545 #define gtt_total_entries(gtt) ((gtt).base.total >> PAGE_SHIFT)
547 struct i915_hw_ppgtt
{
548 struct i915_address_space base
;
549 unsigned num_pd_entries
;
550 struct page
**pt_pages
;
552 dma_addr_t
*pt_dma_addr
;
554 int (*enable
)(struct drm_device
*dev
);
558 * A VMA represents a GEM BO that is bound into an address space. Therefore, a
559 * VMA's presence cannot be guaranteed before binding, or after unbinding the
560 * object into/from the address space.
562 * To make things as simple as possible (ie. no refcounting), a VMA's lifetime
563 * will always be <= an objects lifetime. So object refcounting should cover us.
566 struct drm_mm_node node
;
567 struct drm_i915_gem_object
*obj
;
568 struct i915_address_space
*vm
;
570 /** This object's place on the active/inactive lists */
571 struct list_head mm_list
;
573 struct list_head vma_link
; /* Link in the object's VMA list */
575 /** This vma's place in the batchbuffer or on the eviction list */
576 struct list_head exec_list
;
579 * Used for performing relocations during execbuffer insertion.
581 struct hlist_node exec_node
;
582 unsigned long exec_handle
;
583 struct drm_i915_gem_exec_object2
*exec_entry
;
587 struct i915_ctx_hang_stats
{
588 /* This context had batch pending when hang was declared */
589 unsigned batch_pending
;
591 /* This context had batch active when hang was declared */
592 unsigned batch_active
;
594 /* Time when this context was last blamed for a GPU reset */
595 unsigned long guilty_ts
;
597 /* This context is banned to submit more work */
601 /* This must match up with the value previously used for execbuf2.rsvd1. */
602 #define DEFAULT_CONTEXT_ID 0
603 struct i915_hw_context
{
608 struct drm_i915_file_private
*file_priv
;
609 struct intel_ring_buffer
*ring
;
610 struct drm_i915_gem_object
*obj
;
611 struct i915_ctx_hang_stats hang_stats
;
613 struct list_head link
;
622 struct drm_mm_node
*compressed_fb
;
623 struct drm_mm_node
*compressed_llb
;
625 struct intel_fbc_work
{
626 struct delayed_work work
;
627 struct drm_crtc
*crtc
;
628 struct drm_framebuffer
*fb
;
633 FBC_OK
, /* FBC is enabled */
634 FBC_UNSUPPORTED
, /* FBC is not supported by this chipset */
635 FBC_NO_OUTPUT
, /* no outputs enabled to compress */
636 FBC_STOLEN_TOO_SMALL
, /* not enough space for buffers */
637 FBC_UNSUPPORTED_MODE
, /* interlace or doublescanned mode */
638 FBC_MODE_TOO_LARGE
, /* mode too large for compression */
639 FBC_BAD_PLANE
, /* fbc not supported on plane */
640 FBC_NOT_TILED
, /* buffer not tiled */
641 FBC_MULTIPLE_PIPES
, /* more than one pipe active */
643 FBC_CHIP_DEFAULT
, /* disabled by default on this chip */
653 PCH_NONE
= 0, /* No PCH present */
654 PCH_IBX
, /* Ibexpeak PCH */
655 PCH_CPT
, /* Cougarpoint PCH */
656 PCH_LPT
, /* Lynxpoint PCH */
660 enum intel_sbi_destination
{
665 #define QUIRK_PIPEA_FORCE (1<<0)
666 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
667 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
668 #define QUIRK_NO_PCH_PWM_ENABLE (1<<3)
671 struct intel_fbc_work
;
674 struct i2c_adapter adapter
;
678 struct i2c_algo_bit_data bit_algo
;
679 struct drm_i915_private
*dev_priv
;
682 struct i915_suspend_saved_registers
{
703 u32 saveTRANS_HTOTAL_A
;
704 u32 saveTRANS_HBLANK_A
;
705 u32 saveTRANS_HSYNC_A
;
706 u32 saveTRANS_VTOTAL_A
;
707 u32 saveTRANS_VBLANK_A
;
708 u32 saveTRANS_VSYNC_A
;
716 u32 savePFIT_PGM_RATIOS
;
717 u32 saveBLC_HIST_CTL
;
719 u32 saveBLC_PWM_CTL2
;
720 u32 saveBLC_CPU_PWM_CTL
;
721 u32 saveBLC_CPU_PWM_CTL2
;
734 u32 saveTRANS_HTOTAL_B
;
735 u32 saveTRANS_HBLANK_B
;
736 u32 saveTRANS_HSYNC_B
;
737 u32 saveTRANS_VTOTAL_B
;
738 u32 saveTRANS_VBLANK_B
;
739 u32 saveTRANS_VSYNC_B
;
753 u32 savePP_ON_DELAYS
;
754 u32 savePP_OFF_DELAYS
;
762 u32 savePFIT_CONTROL
;
763 u32 save_palette_a
[256];
764 u32 save_palette_b
[256];
765 u32 saveDPFC_CB_BASE
;
766 u32 saveFBC_CFB_BASE
;
769 u32 saveFBC_CONTROL2
;
779 u32 saveCACHE_MODE_0
;
780 u32 saveMI_ARB_STATE
;
791 uint64_t saveFENCE
[I915_MAX_NUM_FENCES
];
802 u32 savePIPEA_GMCH_DATA_M
;
803 u32 savePIPEB_GMCH_DATA_M
;
804 u32 savePIPEA_GMCH_DATA_N
;
805 u32 savePIPEB_GMCH_DATA_N
;
806 u32 savePIPEA_DP_LINK_M
;
807 u32 savePIPEB_DP_LINK_M
;
808 u32 savePIPEA_DP_LINK_N
;
809 u32 savePIPEB_DP_LINK_N
;
820 u32 savePCH_DREF_CONTROL
;
821 u32 saveDISP_ARB_CTL
;
822 u32 savePIPEA_DATA_M1
;
823 u32 savePIPEA_DATA_N1
;
824 u32 savePIPEA_LINK_M1
;
825 u32 savePIPEA_LINK_N1
;
826 u32 savePIPEB_DATA_M1
;
827 u32 savePIPEB_DATA_N1
;
828 u32 savePIPEB_LINK_M1
;
829 u32 savePIPEB_LINK_N1
;
830 u32 saveMCHBAR_RENDER_STANDBY
;
831 u32 savePCH_PORT_HOTPLUG
;
834 struct intel_gen6_power_mgmt
{
835 /* work and pm_iir are protected by dev_priv->irq_lock */
836 struct work_struct work
;
839 /* The below variables an all the rps hw state are protected by
840 * dev->struct mutext. */
850 enum { LOW_POWER
, BETWEEN
, HIGH_POWER
} power
;
852 struct delayed_work delayed_resume_work
;
855 * Protects RPS/RC6 register access and PCU communication.
856 * Must be taken after struct_mutex if nested.
858 struct mutex hw_lock
;
861 /* defined intel_pm.c */
862 extern spinlock_t mchdev_lock
;
864 struct intel_ilk_power_mgmt
{
872 unsigned long last_time1
;
873 unsigned long chipset_power
;
875 struct timespec last_time2
;
876 unsigned long gfx_power
;
882 struct drm_i915_gem_object
*pwrctx
;
883 struct drm_i915_gem_object
*renderctx
;
886 /* Power well structure for haswell */
887 struct i915_power_well
{
888 struct drm_device
*device
;
890 /* power well enable/disable usage count */
895 struct i915_dri1_state
{
896 unsigned allow_batchbuffer
: 1;
897 u32 __iomem
*gfx_hws_cpu_addr
;
908 struct i915_ums_state
{
910 * Flag if the X Server, and thus DRM, is not currently in
911 * control of the device.
913 * This is set between LeaveVT and EnterVT. It needs to be
914 * replaced with a semaphore. It also needs to be
915 * transitioned away from for kernel modesetting.
920 #define MAX_L3_SLICES 2
921 struct intel_l3_parity
{
922 u32
*remap_info
[MAX_L3_SLICES
];
923 struct work_struct error_work
;
928 /** Memory allocator for GTT stolen memory */
929 struct drm_mm stolen
;
930 /** List of all objects in gtt_space. Used to restore gtt
931 * mappings on resume */
932 struct list_head bound_list
;
934 * List of objects which are not bound to the GTT (thus
935 * are idle and not used by the GPU) but still have
936 * (presumably uncached) pages still attached.
938 struct list_head unbound_list
;
940 /** Usable portion of the GTT for GEM */
941 unsigned long stolen_base
; /* limited to low memory (32-bit) */
943 /** PPGTT used for aliasing the PPGTT with the GTT */
944 struct i915_hw_ppgtt
*aliasing_ppgtt
;
946 struct shrinker inactive_shrinker
;
947 bool shrinker_no_lock_stealing
;
949 /** LRU list of objects with fence regs on them. */
950 struct list_head fence_list
;
953 * We leave the user IRQ off as much as possible,
954 * but this means that requests will finish and never
955 * be retired once the system goes idle. Set a timer to
956 * fire periodically while the ring is running. When it
957 * fires, go retire requests.
959 struct delayed_work retire_work
;
962 * When we detect an idle GPU, we want to turn on
963 * powersaving features. So once we see that there
964 * are no more requests outstanding and no more
965 * arrive within a small period of time, we fire
968 struct delayed_work idle_work
;
971 * Are we in a non-interruptible section of code like
976 /** Bit 6 swizzling required for X tiling */
977 uint32_t bit_6_swizzle_x
;
978 /** Bit 6 swizzling required for Y tiling */
979 uint32_t bit_6_swizzle_y
;
981 /* storage for physical objects */
982 struct drm_i915_gem_phys_object
*phys_objs
[I915_MAX_PHYS_OBJECT
];
984 /* accounting, useful for userland debugging */
985 spinlock_t object_stat_lock
;
986 size_t object_memory
;
990 struct drm_i915_error_state_buf
{
999 struct i915_error_state_file_priv
{
1000 struct drm_device
*dev
;
1001 struct drm_i915_error_state
*error
;
1004 struct i915_gpu_error
{
1005 /* For hangcheck timer */
1006 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1007 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1008 /* Hang gpu twice in this window and your context gets banned */
1009 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1011 struct timer_list hangcheck_timer
;
1013 /* For reset and error_state handling. */
1015 /* Protected by the above dev->gpu_error.lock. */
1016 struct drm_i915_error_state
*first_error
;
1017 struct work_struct work
;
1020 unsigned long missed_irq_rings
;
1023 * State variable and reset counter controlling the reset flow
1025 * Upper bits are for the reset counter. This counter is used by the
1026 * wait_seqno code to race-free noticed that a reset event happened and
1027 * that it needs to restart the entire ioctl (since most likely the
1028 * seqno it waited for won't ever signal anytime soon).
1030 * This is important for lock-free wait paths, where no contended lock
1031 * naturally enforces the correct ordering between the bail-out of the
1032 * waiter and the gpu reset work code.
1034 * Lowest bit controls the reset state machine: Set means a reset is in
1035 * progress. This state will (presuming we don't have any bugs) decay
1036 * into either unset (successful reset) or the special WEDGED value (hw
1037 * terminally sour). All waiters on the reset_queue will be woken when
1040 atomic_t reset_counter
;
1043 * Special values/flags for reset_counter
1045 * Note that the code relies on
1046 * I915_WEDGED & I915_RESET_IN_PROGRESS_FLAG
1049 #define I915_RESET_IN_PROGRESS_FLAG 1
1050 #define I915_WEDGED 0xffffffff
1053 * Waitqueue to signal when the reset has completed. Used by clients
1054 * that wait for dev_priv->mm.wedged to settle.
1056 wait_queue_head_t reset_queue
;
1058 /* For gpu hang simulation. */
1059 unsigned int stop_rings
;
1061 /* For missed irq/seqno simulation. */
1062 unsigned int test_irq_rings
;
1065 enum modeset_restore
{
1066 MODESET_ON_LID_OPEN
,
1071 struct ddi_vbt_port_info
{
1072 uint8_t hdmi_level_shift
;
1074 uint8_t supports_dvi
:1;
1075 uint8_t supports_hdmi
:1;
1076 uint8_t supports_dp
:1;
1079 struct intel_vbt_data
{
1080 struct drm_display_mode
*lfp_lvds_vbt_mode
; /* if any */
1081 struct drm_display_mode
*sdvo_lvds_vbt_mode
; /* if any */
1084 unsigned int int_tv_support
:1;
1085 unsigned int lvds_dither
:1;
1086 unsigned int lvds_vbt
:1;
1087 unsigned int int_crt_support
:1;
1088 unsigned int lvds_use_ssc
:1;
1089 unsigned int display_clock_mode
:1;
1090 unsigned int fdi_rx_polarity_inverted
:1;
1092 unsigned int bios_lvds_val
; /* initial [PCH_]LVDS reg val in VBIOS */
1097 int edp_preemphasis
;
1099 bool edp_initialized
;
1102 struct edp_power_seq edp_pps
;
1112 union child_device_config
*child_dev
;
1114 struct ddi_vbt_port_info ddi_port_info
[I915_MAX_PORTS
];
1117 enum intel_ddb_partitioning
{
1119 INTEL_DDB_PART_5_6
, /* IVB+ */
1122 struct intel_wm_level
{
1131 * This struct tracks the state needed for the Package C8+ feature.
1133 * Package states C8 and deeper are really deep PC states that can only be
1134 * reached when all the devices on the system allow it, so even if the graphics
1135 * device allows PC8+, it doesn't mean the system will actually get to these
1138 * Our driver only allows PC8+ when all the outputs are disabled, the power well
1139 * is disabled and the GPU is idle. When these conditions are met, we manually
1140 * do the other conditions: disable the interrupts, clocks and switch LCPLL
1143 * When we really reach PC8 or deeper states (not just when we allow it) we lose
1144 * the state of some registers, so when we come back from PC8+ we need to
1145 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
1146 * need to take care of the registers kept by RC6.
1148 * The interrupt disabling is part of the requirements. We can only leave the
1149 * PCH HPD interrupts enabled. If we're in PC8+ and we get another interrupt we
1150 * can lock the machine.
1152 * Ideally every piece of our code that needs PC8+ disabled would call
1153 * hsw_disable_package_c8, which would increment disable_count and prevent the
1154 * system from reaching PC8+. But we don't have a symmetric way to do this for
1155 * everything, so we have the requirements_met and gpu_idle variables. When we
1156 * switch requirements_met or gpu_idle to true we decrease disable_count, and
1157 * increase it in the opposite case. The requirements_met variable is true when
1158 * all the CRTCs, encoders and the power well are disabled. The gpu_idle
1159 * variable is true when the GPU is idle.
1161 * In addition to everything, we only actually enable PC8+ if disable_count
1162 * stays at zero for at least some seconds. This is implemented with the
1163 * enable_work variable. We do this so we don't enable/disable PC8 dozens of
1164 * consecutive times when all screens are disabled and some background app
1165 * queries the state of our connectors, or we have some application constantly
1166 * waking up to use the GPU. Only after the enable_work function actually
1167 * enables PC8+ the "enable" variable will become true, which means that it can
1168 * be false even if disable_count is 0.
1170 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1171 * goes back to false exactly before we reenable the IRQs. We use this variable
1172 * to check if someone is trying to enable/disable IRQs while they're supposed
1173 * to be disabled. This shouldn't happen and we'll print some error messages in
1174 * case it happens, but if it actually happens we'll also update the variables
1175 * inside struct regsave so when we restore the IRQs they will contain the
1176 * latest expected values.
1178 * For more, read "Display Sequences for Package C8" on our documentation.
1180 struct i915_package_c8
{
1181 bool requirements_met
;
1184 /* Only true after the delayed work task actually enables it. */
1188 struct delayed_work enable_work
;
1195 uint32_t gen6_pmimr
;
1199 typedef struct drm_i915_private
{
1200 struct drm_device
*dev
;
1201 struct kmem_cache
*slab
;
1203 const struct intel_device_info
*info
;
1205 int relative_constants_mode
;
1209 struct intel_uncore uncore
;
1211 struct intel_gmbus gmbus
[GMBUS_NUM_PORTS
];
1214 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1215 * controller on different i2c buses. */
1216 struct mutex gmbus_mutex
;
1219 * Base address of the gmbus and gpio block.
1221 uint32_t gpio_mmio_base
;
1223 wait_queue_head_t gmbus_wait_queue
;
1225 struct pci_dev
*bridge_dev
;
1226 struct intel_ring_buffer ring
[I915_NUM_RINGS
];
1227 uint32_t last_seqno
, next_seqno
;
1229 drm_dma_handle_t
*status_page_dmah
;
1230 struct resource mch_res
;
1232 atomic_t irq_received
;
1234 /* protects the irq masks */
1235 spinlock_t irq_lock
;
1237 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1238 struct pm_qos_request pm_qos
;
1240 /* DPIO indirect register protection */
1241 struct mutex dpio_lock
;
1243 /** Cached value of IMR to avoid reads in updating the bitfield */
1248 struct work_struct hotplug_work
;
1249 bool enable_hotplug_processing
;
1251 unsigned long hpd_last_jiffies
;
1256 HPD_MARK_DISABLED
= 2
1258 } hpd_stats
[HPD_NUM_PINS
];
1260 struct timer_list hotplug_reenable_timer
;
1264 struct i915_fbc fbc
;
1265 struct intel_opregion opregion
;
1266 struct intel_vbt_data vbt
;
1269 struct intel_overlay
*overlay
;
1270 unsigned int sprite_scaling_enabled
;
1276 spinlock_t lock
; /* bl registers and the above bl fields */
1277 struct backlight_device
*device
;
1281 bool no_aux_handshake
;
1283 struct drm_i915_fence_reg fence_regs
[I915_MAX_NUM_FENCES
]; /* assume 965 */
1284 int fence_reg_start
; /* 4 if userland hasn't ioctl'd us yet */
1285 int num_fence_regs
; /* 8 on pre-965, 16 otherwise */
1287 unsigned int fsb_freq
, mem_freq
, is_ddr3
;
1290 * wq - Driver workqueue for GEM.
1292 * NOTE: Work items scheduled here are not allowed to grab any modeset
1293 * locks, for otherwise the flushing done in the pageflip code will
1294 * result in deadlocks.
1296 struct workqueue_struct
*wq
;
1298 /* Display functions */
1299 struct drm_i915_display_funcs display
;
1301 /* PCH chipset type */
1302 enum intel_pch pch_type
;
1303 unsigned short pch_id
;
1305 unsigned long quirks
;
1307 enum modeset_restore modeset_restore
;
1308 struct mutex modeset_restore_lock
;
1310 struct list_head vm_list
; /* Global list of all address spaces */
1311 struct i915_gtt gtt
; /* VMA representing the global address space */
1313 struct i915_gem_mm mm
;
1315 /* Kernel Modesetting */
1317 struct sdvo_device_mapping sdvo_mappings
[2];
1319 struct drm_crtc
*plane_to_crtc_mapping
[3];
1320 struct drm_crtc
*pipe_to_crtc_mapping
[3];
1321 wait_queue_head_t pending_flip_queue
;
1323 int num_shared_dpll
;
1324 struct intel_shared_dpll shared_dplls
[I915_NUM_PLLS
];
1325 struct intel_ddi_plls ddi_plls
;
1327 /* Reclocking support */
1328 bool render_reclock_avail
;
1329 bool lvds_downclock_avail
;
1330 /* indicates the reduced downclock for LVDS*/
1334 bool mchbar_need_disable
;
1336 struct intel_l3_parity l3_parity
;
1338 /* Cannot be determined by PCIID. You must always read a register. */
1341 /* gen6+ rps state */
1342 struct intel_gen6_power_mgmt rps
;
1344 /* ilk-only ips/rps state. Everything in here is protected by the global
1345 * mchdev_lock in intel_pm.c */
1346 struct intel_ilk_power_mgmt ips
;
1348 /* Haswell power well */
1349 struct i915_power_well power_well
;
1351 struct i915_psr psr
;
1353 struct i915_gpu_error gpu_error
;
1355 struct drm_i915_gem_object
*vlv_pctx
;
1357 /* list of fbdev register on this device */
1358 struct intel_fbdev
*fbdev
;
1361 * The console may be contended at resume, but we don't
1362 * want it to block on it.
1364 struct work_struct console_resume_work
;
1366 struct drm_property
*broadcast_rgb_property
;
1367 struct drm_property
*force_audio_property
;
1369 bool hw_contexts_disabled
;
1370 uint32_t hw_context_size
;
1371 struct list_head context_list
;
1375 struct i915_suspend_saved_registers regfile
;
1379 * Raw watermark latency values:
1380 * in 0.1us units for WM0,
1381 * in 0.5us units for WM1+.
1384 uint16_t pri_latency
[5];
1386 uint16_t spr_latency
[5];
1388 uint16_t cur_latency
[5];
1391 struct i915_package_c8 pc8
;
1393 /* Old dri1 support infrastructure, beware the dragons ya fools entering
1395 struct i915_dri1_state dri1
;
1396 /* Old ums support infrastructure, same warning applies. */
1397 struct i915_ums_state ums
;
1398 } drm_i915_private_t
;
1400 static inline struct drm_i915_private
*to_i915(const struct drm_device
*dev
)
1402 return dev
->dev_private
;
1405 /* Iterate over initialised rings */
1406 #define for_each_ring(ring__, dev_priv__, i__) \
1407 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
1408 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
1410 enum hdmi_force_audio
{
1411 HDMI_AUDIO_OFF_DVI
= -2, /* no aux data for HDMI-DVI converter */
1412 HDMI_AUDIO_OFF
, /* force turn off HDMI audio */
1413 HDMI_AUDIO_AUTO
, /* trust EDID */
1414 HDMI_AUDIO_ON
, /* force turn on HDMI audio */
1417 #define I915_GTT_OFFSET_NONE ((u32)-1)
1419 struct drm_i915_gem_object_ops
{
1420 /* Interface between the GEM object and its backing storage.
1421 * get_pages() is called once prior to the use of the associated set
1422 * of pages before to binding them into the GTT, and put_pages() is
1423 * called after we no longer need them. As we expect there to be
1424 * associated cost with migrating pages between the backing storage
1425 * and making them available for the GPU (e.g. clflush), we may hold
1426 * onto the pages after they are no longer referenced by the GPU
1427 * in case they may be used again shortly (for example migrating the
1428 * pages to a different memory domain within the GTT). put_pages()
1429 * will therefore most likely be called when the object itself is
1430 * being released or under memory pressure (where we attempt to
1431 * reap pages for the shrinker).
1433 int (*get_pages
)(struct drm_i915_gem_object
*);
1434 void (*put_pages
)(struct drm_i915_gem_object
*);
1437 struct drm_i915_gem_object
{
1438 struct drm_gem_object base
;
1440 const struct drm_i915_gem_object_ops
*ops
;
1442 /** List of VMAs backed by this object */
1443 struct list_head vma_list
;
1445 /** Stolen memory for this object, instead of being backed by shmem. */
1446 struct drm_mm_node
*stolen
;
1447 struct list_head global_list
;
1449 struct list_head ring_list
;
1450 /** Used in execbuf to temporarily hold a ref */
1451 struct list_head obj_exec_link
;
1454 * This is set if the object is on the active lists (has pending
1455 * rendering and so a non-zero seqno), and is not set if it i s on
1456 * inactive (ready to be unbound) list.
1458 unsigned int active
:1;
1461 * This is set if the object has been written to since last bound
1464 unsigned int dirty
:1;
1467 * Fence register bits (if any) for this object. Will be set
1468 * as needed when mapped into the GTT.
1469 * Protected by dev->struct_mutex.
1471 signed int fence_reg
:I915_MAX_NUM_FENCE_BITS
;
1474 * Advice: are the backing pages purgeable?
1476 unsigned int madv
:2;
1479 * Current tiling mode for the object.
1481 unsigned int tiling_mode
:2;
1483 * Whether the tiling parameters for the currently associated fence
1484 * register have changed. Note that for the purposes of tracking
1485 * tiling changes we also treat the unfenced register, the register
1486 * slot that the object occupies whilst it executes a fenced
1487 * command (such as BLT on gen2/3), as a "fence".
1489 unsigned int fence_dirty
:1;
1491 /** How many users have pinned this object in GTT space. The following
1492 * users can each hold at most one reference: pwrite/pread, pin_ioctl
1493 * (via user_pin_count), execbuffer (objects are not allowed multiple
1494 * times for the same batchbuffer), and the framebuffer code. When
1495 * switching/pageflipping, the framebuffer code has at most two buffers
1498 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
1499 * bits with absolutely no headroom. So use 4 bits. */
1500 unsigned int pin_count
:4;
1501 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
1504 * Is the object at the current location in the gtt mappable and
1505 * fenceable? Used to avoid costly recalculations.
1507 unsigned int map_and_fenceable
:1;
1510 * Whether the current gtt mapping needs to be mappable (and isn't just
1511 * mappable by accident). Track pin and fault separate for a more
1512 * accurate mappable working set.
1514 unsigned int fault_mappable
:1;
1515 unsigned int pin_mappable
:1;
1516 unsigned int pin_display
:1;
1519 * Is the GPU currently using a fence to access this buffer,
1521 unsigned int pending_fenced_gpu_access
:1;
1522 unsigned int fenced_gpu_access
:1;
1524 unsigned int cache_level
:3;
1526 unsigned int has_aliasing_ppgtt_mapping
:1;
1527 unsigned int has_global_gtt_mapping
:1;
1528 unsigned int has_dma_mapping
:1;
1530 struct sg_table
*pages
;
1531 int pages_pin_count
;
1533 /* prime dma-buf support */
1534 void *dma_buf_vmapping
;
1537 struct intel_ring_buffer
*ring
;
1539 /** Breadcrumb of last rendering to the buffer. */
1540 uint32_t last_read_seqno
;
1541 uint32_t last_write_seqno
;
1542 /** Breadcrumb of last fenced GPU access to the buffer. */
1543 uint32_t last_fenced_seqno
;
1545 /** Current tiling stride for the object, if it's tiled. */
1548 /** Record of address bit 17 of each page at last unbind. */
1549 unsigned long *bit_17
;
1551 /** User space pin count and filp owning the pin */
1552 uint32_t user_pin_count
;
1553 struct drm_file
*pin_filp
;
1555 /** for phy allocated objects */
1556 struct drm_i915_gem_phys_object
*phys_obj
;
1558 #define to_gem_object(obj) (&((struct drm_i915_gem_object *)(obj))->base)
1560 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
1563 * Request queue structure.
1565 * The request queue allows us to note sequence numbers that have been emitted
1566 * and may be associated with active buffers to be retired.
1568 * By keeping this list, we can avoid having to do questionable
1569 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
1570 * an emission time with seqnos for tracking how far ahead of the GPU we are.
1572 struct drm_i915_gem_request
{
1573 /** On Which ring this request was generated */
1574 struct intel_ring_buffer
*ring
;
1576 /** GEM sequence number associated with this request. */
1579 /** Position in the ringbuffer of the start of the request */
1582 /** Position in the ringbuffer of the end of the request */
1585 /** Context related to this request */
1586 struct i915_hw_context
*ctx
;
1588 /** Batch buffer related to this request if any */
1589 struct drm_i915_gem_object
*batch_obj
;
1591 /** Time at which this request was emitted, in jiffies. */
1592 unsigned long emitted_jiffies
;
1594 /** global list entry for this request */
1595 struct list_head list
;
1597 struct drm_i915_file_private
*file_priv
;
1598 /** file_priv list entry for this request */
1599 struct list_head client_list
;
1602 struct drm_i915_file_private
{
1603 struct drm_i915_private
*dev_priv
;
1607 struct list_head request_list
;
1608 struct delayed_work idle_work
;
1610 struct idr context_idr
;
1612 struct i915_ctx_hang_stats hang_stats
;
1613 atomic_t rps_wait_boost
;
1616 #define INTEL_INFO(dev) (to_i915(dev)->info)
1618 #define IS_I830(dev) ((dev)->pdev->device == 0x3577)
1619 #define IS_845G(dev) ((dev)->pdev->device == 0x2562)
1620 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
1621 #define IS_I865G(dev) ((dev)->pdev->device == 0x2572)
1622 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
1623 #define IS_I915GM(dev) ((dev)->pdev->device == 0x2592)
1624 #define IS_I945G(dev) ((dev)->pdev->device == 0x2772)
1625 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
1626 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
1627 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
1628 #define IS_GM45(dev) ((dev)->pdev->device == 0x2A42)
1629 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
1630 #define IS_PINEVIEW_G(dev) ((dev)->pdev->device == 0xa001)
1631 #define IS_PINEVIEW_M(dev) ((dev)->pdev->device == 0xa011)
1632 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
1633 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
1634 #define IS_IRONLAKE_M(dev) ((dev)->pdev->device == 0x0046)
1635 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
1636 #define IS_IVB_GT1(dev) ((dev)->pdev->device == 0x0156 || \
1637 (dev)->pdev->device == 0x0152 || \
1638 (dev)->pdev->device == 0x015a)
1639 #define IS_SNB_GT1(dev) ((dev)->pdev->device == 0x0102 || \
1640 (dev)->pdev->device == 0x0106 || \
1641 (dev)->pdev->device == 0x010A)
1642 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
1643 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
1644 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
1645 #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
1646 ((dev)->pdev->device & 0xFF00) == 0x0C00)
1647 #define IS_ULT(dev) (IS_HASWELL(dev) && \
1648 ((dev)->pdev->device & 0xFF00) == 0x0A00)
1649 #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
1650 ((dev)->pdev->device & 0x00F0) == 0x0020)
1651 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
1654 * The genX designation typically refers to the render engine, so render
1655 * capability related checks should use IS_GEN, while display and other checks
1656 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
1659 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
1660 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
1661 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
1662 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
1663 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
1664 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
1666 #define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring)
1667 #define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring)
1668 #define HAS_VEBOX(dev) (INTEL_INFO(dev)->has_vebox_ring)
1669 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
1670 #define HAS_WT(dev) (IS_HASWELL(dev) && to_i915(dev)->ellc_size)
1671 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
1673 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
1674 #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6 && !IS_VALLEYVIEW(dev))
1676 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
1677 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
1679 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
1680 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
1682 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1683 * rows, which changed the alignment requirements and fence programming.
1685 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
1687 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
1688 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
1689 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
1690 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
1691 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
1693 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
1694 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
1695 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
1697 #define HAS_IPS(dev) (IS_ULT(dev))
1699 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
1700 #define HAS_POWER_WELL(dev) (IS_HASWELL(dev))
1701 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
1702 #define HAS_PSR(dev) (IS_HASWELL(dev))
1704 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
1705 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
1706 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
1707 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
1708 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
1709 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
1711 #define INTEL_PCH_TYPE(dev) (to_i915(dev)->pch_type)
1712 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
1713 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
1714 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
1715 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
1716 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
1718 #define HAS_FORCE_WAKE(dev) (INTEL_INFO(dev)->has_force_wake)
1720 /* DPF == dynamic parity feature */
1721 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1722 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
1724 #define GT_FREQUENCY_MULTIPLIER 50
1726 #include "i915_trace.h"
1729 * RC6 is a special power stage which allows the GPU to enter an very
1730 * low-voltage mode when idle, using down to 0V while at this stage. This
1731 * stage is entered automatically when the GPU is idle when RC6 support is
1732 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
1734 * There are different RC6 modes available in Intel GPU, which differentiate
1735 * among each other with the latency required to enter and leave RC6 and
1736 * voltage consumed by the GPU in different states.
1738 * The combination of the following flags define which states GPU is allowed
1739 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
1740 * RC6pp is deepest RC6. Their support by hardware varies according to the
1741 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
1742 * which brings the most power savings; deeper states save more power, but
1743 * require higher latency to switch to and wake up.
1745 #define INTEL_RC6_ENABLE (1<<0)
1746 #define INTEL_RC6p_ENABLE (1<<1)
1747 #define INTEL_RC6pp_ENABLE (1<<2)
1749 extern const struct drm_ioctl_desc i915_ioctls
[];
1750 extern int i915_max_ioctl
;
1751 extern unsigned int i915_fbpercrtc __always_unused
;
1752 extern int i915_panel_ignore_lid __read_mostly
;
1753 extern unsigned int i915_powersave __read_mostly
;
1754 extern int i915_semaphores __read_mostly
;
1755 extern unsigned int i915_lvds_downclock __read_mostly
;
1756 extern int i915_lvds_channel_mode __read_mostly
;
1757 extern int i915_panel_use_ssc __read_mostly
;
1758 extern int i915_vbt_sdvo_panel_type __read_mostly
;
1759 extern int i915_enable_rc6 __read_mostly
;
1760 extern int i915_enable_fbc __read_mostly
;
1761 extern bool i915_enable_hangcheck __read_mostly
;
1762 extern int i915_enable_ppgtt __read_mostly
;
1763 extern int i915_enable_psr __read_mostly
;
1764 extern unsigned int i915_preliminary_hw_support __read_mostly
;
1765 extern int i915_disable_power_well __read_mostly
;
1766 extern int i915_enable_ips __read_mostly
;
1767 extern bool i915_fastboot __read_mostly
;
1768 extern int i915_enable_pc8 __read_mostly
;
1769 extern int i915_pc8_timeout __read_mostly
;
1770 extern bool i915_prefault_disable __read_mostly
;
1772 extern int i915_suspend(struct drm_device
*dev
, pm_message_t state
);
1773 extern int i915_resume(struct drm_device
*dev
);
1774 extern int i915_master_create(struct drm_device
*dev
, struct drm_master
*master
);
1775 extern void i915_master_destroy(struct drm_device
*dev
, struct drm_master
*master
);
1778 void i915_update_dri1_breadcrumb(struct drm_device
*dev
);
1779 extern void i915_kernel_lost_context(struct drm_device
* dev
);
1780 extern int i915_driver_load(struct drm_device
*, unsigned long flags
);
1781 extern int i915_driver_unload(struct drm_device
*);
1782 extern int i915_driver_open(struct drm_device
*dev
, struct drm_file
*file_priv
);
1783 extern void i915_driver_lastclose(struct drm_device
* dev
);
1784 extern void i915_driver_preclose(struct drm_device
*dev
,
1785 struct drm_file
*file_priv
);
1786 extern void i915_driver_postclose(struct drm_device
*dev
,
1787 struct drm_file
*file_priv
);
1788 extern int i915_driver_device_is_agp(struct drm_device
* dev
);
1789 #ifdef CONFIG_COMPAT
1790 extern long i915_compat_ioctl(struct file
*filp
, unsigned int cmd
,
1793 extern int i915_emit_box(struct drm_device
*dev
,
1794 struct drm_clip_rect
*box
,
1796 extern int intel_gpu_reset(struct drm_device
*dev
);
1797 extern int i915_reset(struct drm_device
*dev
);
1798 extern unsigned long i915_chipset_val(struct drm_i915_private
*dev_priv
);
1799 extern unsigned long i915_mch_val(struct drm_i915_private
*dev_priv
);
1800 extern unsigned long i915_gfx_val(struct drm_i915_private
*dev_priv
);
1801 extern void i915_update_gfx_val(struct drm_i915_private
*dev_priv
);
1803 extern void intel_console_resume(struct work_struct
*work
);
1806 void i915_queue_hangcheck(struct drm_device
*dev
);
1807 void i915_handle_error(struct drm_device
*dev
, bool wedged
);
1809 extern void intel_irq_init(struct drm_device
*dev
);
1810 extern void intel_pm_init(struct drm_device
*dev
);
1811 extern void intel_hpd_init(struct drm_device
*dev
);
1812 extern void intel_pm_init(struct drm_device
*dev
);
1814 extern void intel_uncore_sanitize(struct drm_device
*dev
);
1815 extern void intel_uncore_early_sanitize(struct drm_device
*dev
);
1816 extern void intel_uncore_init(struct drm_device
*dev
);
1817 extern void intel_uncore_clear_errors(struct drm_device
*dev
);
1818 extern void intel_uncore_check_errors(struct drm_device
*dev
);
1819 extern void intel_uncore_fini(struct drm_device
*dev
);
1822 i915_enable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
);
1825 i915_disable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
);
1828 int i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
1829 struct drm_file
*file_priv
);
1830 int i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
1831 struct drm_file
*file_priv
);
1832 int i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
1833 struct drm_file
*file_priv
);
1834 int i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
1835 struct drm_file
*file_priv
);
1836 int i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1837 struct drm_file
*file_priv
);
1838 int i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
1839 struct drm_file
*file_priv
);
1840 int i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
1841 struct drm_file
*file_priv
);
1842 int i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1843 struct drm_file
*file_priv
);
1844 int i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
1845 struct drm_file
*file_priv
);
1846 int i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
1847 struct drm_file
*file_priv
);
1848 int i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
1849 struct drm_file
*file_priv
);
1850 int i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
1851 struct drm_file
*file_priv
);
1852 int i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
1853 struct drm_file
*file_priv
);
1854 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
1855 struct drm_file
*file
);
1856 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
1857 struct drm_file
*file
);
1858 int i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
1859 struct drm_file
*file_priv
);
1860 int i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
1861 struct drm_file
*file_priv
);
1862 int i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
1863 struct drm_file
*file_priv
);
1864 int i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
1865 struct drm_file
*file_priv
);
1866 int i915_gem_set_tiling(struct drm_device
*dev
, void *data
,
1867 struct drm_file
*file_priv
);
1868 int i915_gem_get_tiling(struct drm_device
*dev
, void *data
,
1869 struct drm_file
*file_priv
);
1870 int i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
1871 struct drm_file
*file_priv
);
1872 int i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
,
1873 struct drm_file
*file_priv
);
1874 void i915_gem_load(struct drm_device
*dev
);
1875 void *i915_gem_object_alloc(struct drm_device
*dev
);
1876 void i915_gem_object_free(struct drm_i915_gem_object
*obj
);
1877 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
1878 const struct drm_i915_gem_object_ops
*ops
);
1879 struct drm_i915_gem_object
*i915_gem_alloc_object(struct drm_device
*dev
,
1881 void i915_gem_free_object(struct drm_gem_object
*obj
);
1882 void i915_gem_vma_destroy(struct i915_vma
*vma
);
1884 int __must_check
i915_gem_object_pin(struct drm_i915_gem_object
*obj
,
1885 struct i915_address_space
*vm
,
1887 bool map_and_fenceable
,
1889 void i915_gem_object_unpin(struct drm_i915_gem_object
*obj
);
1890 int __must_check
i915_vma_unbind(struct i915_vma
*vma
);
1891 int __must_check
i915_gem_object_ggtt_unbind(struct drm_i915_gem_object
*obj
);
1892 int i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
);
1893 void i915_gem_release_mmap(struct drm_i915_gem_object
*obj
);
1894 void i915_gem_lastclose(struct drm_device
*dev
);
1896 int __must_check
i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
);
1897 static inline struct page
*i915_gem_object_get_page(struct drm_i915_gem_object
*obj
, int n
)
1899 struct sg_page_iter sg_iter
;
1901 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
, n
)
1902 return sg_page_iter_page(&sg_iter
);
1906 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object
*obj
)
1908 BUG_ON(obj
->pages
== NULL
);
1909 obj
->pages_pin_count
++;
1911 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object
*obj
)
1913 BUG_ON(obj
->pages_pin_count
== 0);
1914 obj
->pages_pin_count
--;
1917 int __must_check
i915_mutex_lock_interruptible(struct drm_device
*dev
);
1918 int i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
1919 struct intel_ring_buffer
*to
);
1920 void i915_vma_move_to_active(struct i915_vma
*vma
,
1921 struct intel_ring_buffer
*ring
);
1922 int i915_gem_dumb_create(struct drm_file
*file_priv
,
1923 struct drm_device
*dev
,
1924 struct drm_mode_create_dumb
*args
);
1925 int i915_gem_mmap_gtt(struct drm_file
*file_priv
, struct drm_device
*dev
,
1926 uint32_t handle
, uint64_t *offset
);
1928 * Returns true if seq1 is later than seq2.
1931 i915_seqno_passed(uint32_t seq1
, uint32_t seq2
)
1933 return (int32_t)(seq1
- seq2
) >= 0;
1936 int __must_check
i915_gem_get_seqno(struct drm_device
*dev
, u32
*seqno
);
1937 int __must_check
i915_gem_set_seqno(struct drm_device
*dev
, u32 seqno
);
1938 int __must_check
i915_gem_object_get_fence(struct drm_i915_gem_object
*obj
);
1939 int __must_check
i915_gem_object_put_fence(struct drm_i915_gem_object
*obj
);
1942 i915_gem_object_pin_fence(struct drm_i915_gem_object
*obj
)
1944 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
1945 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
1946 dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
++;
1953 i915_gem_object_unpin_fence(struct drm_i915_gem_object
*obj
)
1955 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
1956 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
1957 WARN_ON(dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
<= 0);
1958 dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
--;
1962 bool i915_gem_retire_requests(struct drm_device
*dev
);
1963 void i915_gem_retire_requests_ring(struct intel_ring_buffer
*ring
);
1964 int __must_check
i915_gem_check_wedge(struct i915_gpu_error
*error
,
1965 bool interruptible
);
1966 static inline bool i915_reset_in_progress(struct i915_gpu_error
*error
)
1968 return unlikely(atomic_read(&error
->reset_counter
)
1969 & I915_RESET_IN_PROGRESS_FLAG
);
1972 static inline bool i915_terminally_wedged(struct i915_gpu_error
*error
)
1974 return atomic_read(&error
->reset_counter
) == I915_WEDGED
;
1977 void i915_gem_reset(struct drm_device
*dev
);
1978 bool i915_gem_clflush_object(struct drm_i915_gem_object
*obj
, bool force
);
1979 int __must_check
i915_gem_object_finish_gpu(struct drm_i915_gem_object
*obj
);
1980 int __must_check
i915_gem_init(struct drm_device
*dev
);
1981 int __must_check
i915_gem_init_hw(struct drm_device
*dev
);
1982 int i915_gem_l3_remap(struct intel_ring_buffer
*ring
, int slice
);
1983 void i915_gem_init_swizzling(struct drm_device
*dev
);
1984 void i915_gem_cleanup_ringbuffer(struct drm_device
*dev
);
1985 int __must_check
i915_gpu_idle(struct drm_device
*dev
);
1986 int __must_check
i915_gem_idle(struct drm_device
*dev
);
1987 int __i915_add_request(struct intel_ring_buffer
*ring
,
1988 struct drm_file
*file
,
1989 struct drm_i915_gem_object
*batch_obj
,
1991 #define i915_add_request(ring, seqno) \
1992 __i915_add_request(ring, NULL, NULL, seqno)
1993 int __must_check
i915_wait_seqno(struct intel_ring_buffer
*ring
,
1995 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
);
1997 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
,
2000 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
);
2002 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
2004 struct intel_ring_buffer
*pipelined
);
2005 void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object
*obj
);
2006 int i915_gem_attach_phys_object(struct drm_device
*dev
,
2007 struct drm_i915_gem_object
*obj
,
2010 void i915_gem_detach_phys_object(struct drm_device
*dev
,
2011 struct drm_i915_gem_object
*obj
);
2012 void i915_gem_free_all_phys_object(struct drm_device
*dev
);
2013 int i915_gem_open(struct drm_device
*dev
, struct drm_file
*file
);
2014 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
);
2017 i915_gem_get_gtt_size(struct drm_device
*dev
, uint32_t size
, int tiling_mode
);
2019 i915_gem_get_gtt_alignment(struct drm_device
*dev
, uint32_t size
,
2020 int tiling_mode
, bool fenced
);
2022 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
2023 enum i915_cache_level cache_level
);
2025 struct drm_gem_object
*i915_gem_prime_import(struct drm_device
*dev
,
2026 struct dma_buf
*dma_buf
);
2028 struct dma_buf
*i915_gem_prime_export(struct drm_device
*dev
,
2029 struct drm_gem_object
*gem_obj
, int flags
);
2031 void i915_gem_restore_fences(struct drm_device
*dev
);
2033 unsigned long i915_gem_obj_offset(struct drm_i915_gem_object
*o
,
2034 struct i915_address_space
*vm
);
2035 bool i915_gem_obj_bound_any(struct drm_i915_gem_object
*o
);
2036 bool i915_gem_obj_bound(struct drm_i915_gem_object
*o
,
2037 struct i915_address_space
*vm
);
2038 unsigned long i915_gem_obj_size(struct drm_i915_gem_object
*o
,
2039 struct i915_address_space
*vm
);
2040 struct i915_vma
*i915_gem_obj_to_vma(struct drm_i915_gem_object
*obj
,
2041 struct i915_address_space
*vm
);
2043 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object
*obj
,
2044 struct i915_address_space
*vm
);
2046 struct i915_vma
*i915_gem_obj_to_ggtt(struct drm_i915_gem_object
*obj
);
2048 /* Some GGTT VM helpers */
2049 #define obj_to_ggtt(obj) \
2050 (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
2051 static inline bool i915_is_ggtt(struct i915_address_space
*vm
)
2053 struct i915_address_space
*ggtt
=
2054 &((struct drm_i915_private
*)(vm
)->dev
->dev_private
)->gtt
.base
;
2058 static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object
*obj
)
2060 return i915_gem_obj_bound(obj
, obj_to_ggtt(obj
));
2063 static inline unsigned long
2064 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object
*obj
)
2066 return i915_gem_obj_offset(obj
, obj_to_ggtt(obj
));
2069 static inline unsigned long
2070 i915_gem_obj_ggtt_size(struct drm_i915_gem_object
*obj
)
2072 return i915_gem_obj_size(obj
, obj_to_ggtt(obj
));
2075 static inline int __must_check
2076 i915_gem_obj_ggtt_pin(struct drm_i915_gem_object
*obj
,
2078 bool map_and_fenceable
,
2081 return i915_gem_object_pin(obj
, obj_to_ggtt(obj
), alignment
,
2082 map_and_fenceable
, nonblocking
);
2085 /* i915_gem_context.c */
2086 void i915_gem_context_init(struct drm_device
*dev
);
2087 void i915_gem_context_fini(struct drm_device
*dev
);
2088 void i915_gem_context_close(struct drm_device
*dev
, struct drm_file
*file
);
2089 int i915_switch_context(struct intel_ring_buffer
*ring
,
2090 struct drm_file
*file
, int to_id
);
2091 void i915_gem_context_free(struct kref
*ctx_ref
);
2092 static inline void i915_gem_context_reference(struct i915_hw_context
*ctx
)
2094 kref_get(&ctx
->ref
);
2097 static inline void i915_gem_context_unreference(struct i915_hw_context
*ctx
)
2099 kref_put(&ctx
->ref
, i915_gem_context_free
);
2102 struct i915_ctx_hang_stats
* __must_check
2103 i915_gem_context_get_hang_stats(struct drm_device
*dev
,
2104 struct drm_file
*file
,
2106 int i915_gem_context_create_ioctl(struct drm_device
*dev
, void *data
,
2107 struct drm_file
*file
);
2108 int i915_gem_context_destroy_ioctl(struct drm_device
*dev
, void *data
,
2109 struct drm_file
*file
);
2111 /* i915_gem_gtt.c */
2112 void i915_gem_cleanup_aliasing_ppgtt(struct drm_device
*dev
);
2113 void i915_ppgtt_bind_object(struct i915_hw_ppgtt
*ppgtt
,
2114 struct drm_i915_gem_object
*obj
,
2115 enum i915_cache_level cache_level
);
2116 void i915_ppgtt_unbind_object(struct i915_hw_ppgtt
*ppgtt
,
2117 struct drm_i915_gem_object
*obj
);
2119 void i915_gem_restore_gtt_mappings(struct drm_device
*dev
);
2120 int __must_check
i915_gem_gtt_prepare_object(struct drm_i915_gem_object
*obj
);
2121 void i915_gem_gtt_bind_object(struct drm_i915_gem_object
*obj
,
2122 enum i915_cache_level cache_level
);
2123 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object
*obj
);
2124 void i915_gem_gtt_finish_object(struct drm_i915_gem_object
*obj
);
2125 void i915_gem_init_global_gtt(struct drm_device
*dev
);
2126 void i915_gem_setup_global_gtt(struct drm_device
*dev
, unsigned long start
,
2127 unsigned long mappable_end
, unsigned long end
);
2128 int i915_gem_gtt_init(struct drm_device
*dev
);
2129 static inline void i915_gem_chipset_flush(struct drm_device
*dev
)
2131 if (INTEL_INFO(dev
)->gen
< 6)
2132 intel_gtt_chipset_flush();
2136 /* i915_gem_evict.c */
2137 int __must_check
i915_gem_evict_something(struct drm_device
*dev
,
2138 struct i915_address_space
*vm
,
2141 unsigned cache_level
,
2144 int i915_gem_evict_vm(struct i915_address_space
*vm
, bool do_idle
);
2145 int i915_gem_evict_everything(struct drm_device
*dev
);
2147 /* i915_gem_stolen.c */
2148 int i915_gem_init_stolen(struct drm_device
*dev
);
2149 int i915_gem_stolen_setup_compression(struct drm_device
*dev
, int size
);
2150 void i915_gem_stolen_cleanup_compression(struct drm_device
*dev
);
2151 void i915_gem_cleanup_stolen(struct drm_device
*dev
);
2152 struct drm_i915_gem_object
*
2153 i915_gem_object_create_stolen(struct drm_device
*dev
, u32 size
);
2154 struct drm_i915_gem_object
*
2155 i915_gem_object_create_stolen_for_preallocated(struct drm_device
*dev
,
2159 void i915_gem_object_release_stolen(struct drm_i915_gem_object
*obj
);
2161 /* i915_gem_tiling.c */
2162 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object
*obj
)
2164 drm_i915_private_t
*dev_priv
= obj
->base
.dev
->dev_private
;
2166 return dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_9_10_17
&&
2167 obj
->tiling_mode
!= I915_TILING_NONE
;
2170 void i915_gem_detect_bit_6_swizzle(struct drm_device
*dev
);
2171 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
2172 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
2174 /* i915_gem_debug.c */
2176 int i915_verify_lists(struct drm_device
*dev
);
2178 #define i915_verify_lists(dev) 0
2181 /* i915_debugfs.c */
2182 int i915_debugfs_init(struct drm_minor
*minor
);
2183 void i915_debugfs_cleanup(struct drm_minor
*minor
);
2185 /* i915_gpu_error.c */
2187 void i915_error_printf(struct drm_i915_error_state_buf
*e
, const char *f
, ...);
2188 int i915_error_state_to_str(struct drm_i915_error_state_buf
*estr
,
2189 const struct i915_error_state_file_priv
*error
);
2190 int i915_error_state_buf_init(struct drm_i915_error_state_buf
*eb
,
2191 size_t count
, loff_t pos
);
2192 static inline void i915_error_state_buf_release(
2193 struct drm_i915_error_state_buf
*eb
)
2197 void i915_capture_error_state(struct drm_device
*dev
);
2198 void i915_error_state_get(struct drm_device
*dev
,
2199 struct i915_error_state_file_priv
*error_priv
);
2200 void i915_error_state_put(struct i915_error_state_file_priv
*error_priv
);
2201 void i915_destroy_error_state(struct drm_device
*dev
);
2203 void i915_get_extra_instdone(struct drm_device
*dev
, uint32_t *instdone
);
2204 const char *i915_cache_level_str(int type
);
2206 /* i915_suspend.c */
2207 extern int i915_save_state(struct drm_device
*dev
);
2208 extern int i915_restore_state(struct drm_device
*dev
);
2211 void i915_save_display_reg(struct drm_device
*dev
);
2212 void i915_restore_display_reg(struct drm_device
*dev
);
2215 void i915_setup_sysfs(struct drm_device
*dev_priv
);
2216 void i915_teardown_sysfs(struct drm_device
*dev_priv
);
2219 extern int intel_setup_gmbus(struct drm_device
*dev
);
2220 extern void intel_teardown_gmbus(struct drm_device
*dev
);
2221 static inline bool intel_gmbus_is_port_valid(unsigned port
)
2223 return (port
>= GMBUS_PORT_SSC
&& port
<= GMBUS_PORT_DPD
);
2226 extern struct i2c_adapter
*intel_gmbus_get_adapter(
2227 struct drm_i915_private
*dev_priv
, unsigned port
);
2228 extern void intel_gmbus_set_speed(struct i2c_adapter
*adapter
, int speed
);
2229 extern void intel_gmbus_force_bit(struct i2c_adapter
*adapter
, bool force_bit
);
2230 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter
*adapter
)
2232 return container_of(adapter
, struct intel_gmbus
, adapter
)->force_bit
;
2234 extern void intel_i2c_reset(struct drm_device
*dev
);
2236 /* intel_opregion.c */
2237 struct intel_encoder
;
2238 extern int intel_opregion_setup(struct drm_device
*dev
);
2240 extern void intel_opregion_init(struct drm_device
*dev
);
2241 extern void intel_opregion_fini(struct drm_device
*dev
);
2242 extern void intel_opregion_asle_intr(struct drm_device
*dev
);
2243 extern int intel_opregion_notify_encoder(struct intel_encoder
*intel_encoder
,
2245 extern int intel_opregion_notify_adapter(struct drm_device
*dev
,
2248 static inline void intel_opregion_init(struct drm_device
*dev
) { return; }
2249 static inline void intel_opregion_fini(struct drm_device
*dev
) { return; }
2250 static inline void intel_opregion_asle_intr(struct drm_device
*dev
) { return; }
2252 intel_opregion_notify_encoder(struct intel_encoder
*intel_encoder
, bool enable
)
2257 intel_opregion_notify_adapter(struct drm_device
*dev
, pci_power_t state
)
2265 extern void intel_register_dsm_handler(void);
2266 extern void intel_unregister_dsm_handler(void);
2268 static inline void intel_register_dsm_handler(void) { return; }
2269 static inline void intel_unregister_dsm_handler(void) { return; }
2270 #endif /* CONFIG_ACPI */
2273 extern void intel_modeset_init_hw(struct drm_device
*dev
);
2274 extern void intel_modeset_suspend_hw(struct drm_device
*dev
);
2275 extern void intel_modeset_init(struct drm_device
*dev
);
2276 extern void intel_modeset_gem_init(struct drm_device
*dev
);
2277 extern void intel_modeset_cleanup(struct drm_device
*dev
);
2278 extern int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
);
2279 extern void intel_modeset_setup_hw_state(struct drm_device
*dev
,
2280 bool force_restore
);
2281 extern void i915_redisable_vga(struct drm_device
*dev
);
2282 extern bool intel_fbc_enabled(struct drm_device
*dev
);
2283 extern void intel_disable_fbc(struct drm_device
*dev
);
2284 extern bool ironlake_set_drps(struct drm_device
*dev
, u8 val
);
2285 extern void intel_init_pch_refclk(struct drm_device
*dev
);
2286 extern void gen6_set_rps(struct drm_device
*dev
, u8 val
);
2287 extern void valleyview_set_rps(struct drm_device
*dev
, u8 val
);
2288 extern int valleyview_rps_max_freq(struct drm_i915_private
*dev_priv
);
2289 extern int valleyview_rps_min_freq(struct drm_i915_private
*dev_priv
);
2290 extern void intel_detect_pch(struct drm_device
*dev
);
2291 extern int intel_trans_dp_port_sel(struct drm_crtc
*crtc
);
2292 extern int intel_enable_rc6(const struct drm_device
*dev
);
2294 extern bool i915_semaphore_is_enabled(struct drm_device
*dev
);
2295 int i915_reg_read_ioctl(struct drm_device
*dev
, void *data
,
2296 struct drm_file
*file
);
2299 extern struct intel_overlay_error_state
*intel_overlay_capture_error_state(struct drm_device
*dev
);
2300 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf
*e
,
2301 struct intel_overlay_error_state
*error
);
2303 extern struct intel_display_error_state
*intel_display_capture_error_state(struct drm_device
*dev
);
2304 extern void intel_display_print_error_state(struct drm_i915_error_state_buf
*e
,
2305 struct drm_device
*dev
,
2306 struct intel_display_error_state
*error
);
2308 /* On SNB platform, before reading ring registers forcewake bit
2309 * must be set to prevent GT core from power down and stale values being
2312 void gen6_gt_force_wake_get(struct drm_i915_private
*dev_priv
);
2313 void gen6_gt_force_wake_put(struct drm_i915_private
*dev_priv
);
2315 int sandybridge_pcode_read(struct drm_i915_private
*dev_priv
, u8 mbox
, u32
*val
);
2316 int sandybridge_pcode_write(struct drm_i915_private
*dev_priv
, u8 mbox
, u32 val
);
2318 /* intel_sideband.c */
2319 u32
vlv_punit_read(struct drm_i915_private
*dev_priv
, u8 addr
);
2320 void vlv_punit_write(struct drm_i915_private
*dev_priv
, u8 addr
, u32 val
);
2321 u32
vlv_nc_read(struct drm_i915_private
*dev_priv
, u8 addr
);
2322 u32
vlv_gpio_nc_read(struct drm_i915_private
*dev_priv
, u32 reg
);
2323 void vlv_gpio_nc_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
2324 u32
vlv_cck_read(struct drm_i915_private
*dev_priv
, u32 reg
);
2325 void vlv_cck_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
2326 u32
vlv_ccu_read(struct drm_i915_private
*dev_priv
, u32 reg
);
2327 void vlv_ccu_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
2328 u32
vlv_gps_core_read(struct drm_i915_private
*dev_priv
, u32 reg
);
2329 void vlv_gps_core_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
2330 u32
vlv_dpio_read(struct drm_i915_private
*dev_priv
, enum pipe pipe
, int reg
);
2331 void vlv_dpio_write(struct drm_i915_private
*dev_priv
, enum pipe pipe
, int reg
, u32 val
);
2332 u32
intel_sbi_read(struct drm_i915_private
*dev_priv
, u16 reg
,
2333 enum intel_sbi_destination destination
);
2334 void intel_sbi_write(struct drm_i915_private
*dev_priv
, u16 reg
, u32 value
,
2335 enum intel_sbi_destination destination
);
2337 int vlv_gpu_freq(int ddr_freq
, int val
);
2338 int vlv_freq_opcode(int ddr_freq
, int val
);
2340 #define __i915_read(x) \
2341 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg, bool trace);
2348 #define __i915_write(x) \
2349 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val, bool trace);
2356 #define I915_READ8(reg) i915_read8(dev_priv, (reg), true)
2357 #define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val), true)
2359 #define I915_READ16(reg) i915_read16(dev_priv, (reg), true)
2360 #define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val), true)
2361 #define I915_READ16_NOTRACE(reg) i915_read16(dev_priv, (reg), false)
2362 #define I915_WRITE16_NOTRACE(reg, val) i915_write16(dev_priv, (reg), (val), false)
2364 #define I915_READ(reg) i915_read32(dev_priv, (reg), true)
2365 #define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val), true)
2366 #define I915_READ_NOTRACE(reg) i915_read32(dev_priv, (reg), false)
2367 #define I915_WRITE_NOTRACE(reg, val) i915_write32(dev_priv, (reg), (val), false)
2369 #define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val), true)
2370 #define I915_READ64(reg) i915_read64(dev_priv, (reg), true)
2372 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
2373 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
2375 /* "Broadcast RGB" property */
2376 #define INTEL_BROADCAST_RGB_AUTO 0
2377 #define INTEL_BROADCAST_RGB_FULL 1
2378 #define INTEL_BROADCAST_RGB_LIMITED 2
2380 static inline uint32_t i915_vgacntrl_reg(struct drm_device
*dev
)
2382 if (HAS_PCH_SPLIT(dev
))
2383 return CPU_VGACNTRL
;
2384 else if (IS_VALLEYVIEW(dev
))
2385 return VLV_VGACNTRL
;
2390 static inline void __user
*to_user_ptr(u64 address
)
2392 return (void __user
*)(uintptr_t)address
;
2395 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m
)
2397 unsigned long j
= msecs_to_jiffies(m
);
2399 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);
2402 static inline unsigned long
2403 timespec_to_jiffies_timeout(const struct timespec
*value
)
2405 unsigned long j
= timespec_to_jiffies(value
);
2407 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);