1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
34 #include <uapi/drm/drm_fourcc.h>
37 #include "i915_params.h"
39 #include "intel_bios.h"
40 #include "intel_ringbuffer.h"
41 #include "intel_lrc.h"
42 #include "i915_gem_gtt.h"
43 #include "i915_gem_render_state.h"
44 #include <linux/io-mapping.h>
45 #include <linux/i2c.h>
46 #include <linux/i2c-algo-bit.h>
47 #include <drm/intel-gtt.h>
48 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
49 #include <drm/drm_gem.h>
50 #include <linux/backlight.h>
51 #include <linux/hashtable.h>
52 #include <linux/intel-iommu.h>
53 #include <linux/kref.h>
54 #include <linux/pm_qos.h>
55 #include "intel_guc.h"
57 /* General customization:
60 #define DRIVER_NAME "i915"
61 #define DRIVER_DESC "Intel Graphics"
62 #define DRIVER_DATE "20160124"
65 /* Many gcc seem to no see through this and fall over :( */
67 #define WARN_ON(x) ({ \
68 bool __i915_warn_cond = (x); \
69 if (__builtin_constant_p(__i915_warn_cond)) \
70 BUILD_BUG_ON(__i915_warn_cond); \
71 WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
73 #define WARN_ON(x) WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
77 #define WARN_ON_ONCE(x) WARN_ONCE((x), "%s", "WARN_ON_ONCE(" __stringify(x) ")")
79 #define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
80 (long) (x), __func__);
82 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
83 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
84 * which may not necessarily be a user visible problem. This will either
85 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
86 * enable distros and users to tailor their preferred amount of i915 abrt
89 #define I915_STATE_WARN(condition, format...) ({ \
90 int __ret_warn_on = !!(condition); \
91 if (unlikely(__ret_warn_on)) \
92 if (!WARN(i915.verbose_state_checks, format)) \
94 unlikely(__ret_warn_on); \
97 #define I915_STATE_WARN_ON(x) \
98 I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
100 static inline const char *yesno(bool v
)
102 return v
? "yes" : "no";
105 static inline const char *onoff(bool v
)
107 return v
? "on" : "off";
116 I915_MAX_PIPES
= _PIPE_EDP
118 #define pipe_name(p) ((p) + 'A')
127 #define transcoder_name(t) ((t) + 'A')
130 * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
131 * number of planes per CRTC. Not all platforms really have this many planes,
132 * which means some arrays of size I915_MAX_PLANES may have unused entries
133 * between the topmost sprite plane and the cursor plane.
142 #define plane_name(p) ((p) + 'A')
144 #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
154 #define port_name(p) ((p) + 'A')
156 #define I915_NUM_PHYS_VLV 2
168 enum intel_display_power_domain
{
172 POWER_DOMAIN_PIPE_A_PANEL_FITTER
,
173 POWER_DOMAIN_PIPE_B_PANEL_FITTER
,
174 POWER_DOMAIN_PIPE_C_PANEL_FITTER
,
175 POWER_DOMAIN_TRANSCODER_A
,
176 POWER_DOMAIN_TRANSCODER_B
,
177 POWER_DOMAIN_TRANSCODER_C
,
178 POWER_DOMAIN_TRANSCODER_EDP
,
179 POWER_DOMAIN_PORT_DDI_A_LANES
,
180 POWER_DOMAIN_PORT_DDI_B_LANES
,
181 POWER_DOMAIN_PORT_DDI_C_LANES
,
182 POWER_DOMAIN_PORT_DDI_D_LANES
,
183 POWER_DOMAIN_PORT_DDI_E_LANES
,
184 POWER_DOMAIN_PORT_DSI
,
185 POWER_DOMAIN_PORT_CRT
,
186 POWER_DOMAIN_PORT_OTHER
,
195 POWER_DOMAIN_MODESET
,
201 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
202 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
203 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
204 #define POWER_DOMAIN_TRANSCODER(tran) \
205 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
206 (tran) + POWER_DOMAIN_TRANSCODER_A)
210 HPD_TV
= HPD_NONE
, /* TV is known to be unreliable */
222 #define for_each_hpd_pin(__pin) \
223 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
225 struct i915_hotplug
{
226 struct work_struct hotplug_work
;
229 unsigned long last_jiffies
;
234 HPD_MARK_DISABLED
= 2
236 } stats
[HPD_NUM_PINS
];
238 struct delayed_work reenable_work
;
240 struct intel_digital_port
*irq_port
[I915_MAX_PORTS
];
243 struct work_struct dig_port_work
;
246 * if we get a HPD irq from DP and a HPD irq from non-DP
247 * the non-DP HPD could block the workqueue on a mode config
248 * mutex getting, that userspace may have taken. However
249 * userspace is waiting on the DP workqueue to run which is
250 * blocked behind the non-DP one.
252 struct workqueue_struct
*dp_wq
;
255 #define I915_GEM_GPU_DOMAINS \
256 (I915_GEM_DOMAIN_RENDER | \
257 I915_GEM_DOMAIN_SAMPLER | \
258 I915_GEM_DOMAIN_COMMAND | \
259 I915_GEM_DOMAIN_INSTRUCTION | \
260 I915_GEM_DOMAIN_VERTEX)
262 #define for_each_pipe(__dev_priv, __p) \
263 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
264 #define for_each_plane(__dev_priv, __pipe, __p) \
266 (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
268 #define for_each_sprite(__dev_priv, __p, __s) \
270 (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \
273 #define for_each_crtc(dev, crtc) \
274 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
276 #define for_each_intel_plane(dev, intel_plane) \
277 list_for_each_entry(intel_plane, \
278 &dev->mode_config.plane_list, \
281 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
282 list_for_each_entry(intel_plane, \
283 &(dev)->mode_config.plane_list, \
285 for_each_if ((intel_plane)->pipe == (intel_crtc)->pipe)
287 #define for_each_intel_crtc(dev, intel_crtc) \
288 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)
290 #define for_each_intel_encoder(dev, intel_encoder) \
291 list_for_each_entry(intel_encoder, \
292 &(dev)->mode_config.encoder_list, \
295 #define for_each_intel_connector(dev, intel_connector) \
296 list_for_each_entry(intel_connector, \
297 &dev->mode_config.connector_list, \
300 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
301 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
302 for_each_if ((intel_encoder)->base.crtc == (__crtc))
304 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
305 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
306 for_each_if ((intel_connector)->base.encoder == (__encoder))
308 #define for_each_power_domain(domain, mask) \
309 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
310 for_each_if ((1 << (domain)) & (mask))
312 struct drm_i915_private
;
313 struct i915_mm_struct
;
314 struct i915_mmu_object
;
316 struct drm_i915_file_private
{
317 struct drm_i915_private
*dev_priv
;
318 struct drm_file
*file
;
322 struct list_head request_list
;
323 /* 20ms is a fairly arbitrary limit (greater than the average frame time)
324 * chosen to prevent the CPU getting more than a frame ahead of the GPU
325 * (when using lax throttling for the frontbuffer). We also use it to
326 * offer free GPU waitboosts for severely congested workloads.
328 #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
330 struct idr context_idr
;
332 struct intel_rps_client
{
333 struct list_head link
;
337 unsigned int bsd_ring
;
341 DPLL_ID_PRIVATE
= -1, /* non-shared dpll in use */
342 /* real shared dpll ids must be >= 0 */
343 DPLL_ID_PCH_PLL_A
= 0,
344 DPLL_ID_PCH_PLL_B
= 1,
351 DPLL_ID_SKL_DPLL1
= 0,
352 DPLL_ID_SKL_DPLL2
= 1,
353 DPLL_ID_SKL_DPLL3
= 2,
355 #define I915_NUM_PLLS 3
357 struct intel_dpll_hw_state
{
370 * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in
371 * lower part of ctrl1 and they get shifted into position when writing
372 * the register. This allows us to easily compare the state to share
376 /* HDMI only, 0 when used for DP */
377 uint32_t cfgcr1
, cfgcr2
;
380 uint32_t ebb0
, ebb4
, pll0
, pll1
, pll2
, pll3
, pll6
, pll8
, pll9
, pll10
,
384 struct intel_shared_dpll_config
{
385 unsigned crtc_mask
; /* mask of CRTCs sharing this PLL */
386 struct intel_dpll_hw_state hw_state
;
389 struct intel_shared_dpll
{
390 struct intel_shared_dpll_config config
;
392 int active
; /* count of number of active CRTCs (i.e. DPMS on) */
393 bool on
; /* is the PLL actually active? Disabled during modeset */
395 /* should match the index in the dev_priv->shared_dplls array */
396 enum intel_dpll_id id
;
397 /* The mode_set hook is optional and should be used together with the
398 * intel_prepare_shared_dpll function. */
399 void (*mode_set
)(struct drm_i915_private
*dev_priv
,
400 struct intel_shared_dpll
*pll
);
401 void (*enable
)(struct drm_i915_private
*dev_priv
,
402 struct intel_shared_dpll
*pll
);
403 void (*disable
)(struct drm_i915_private
*dev_priv
,
404 struct intel_shared_dpll
*pll
);
405 bool (*get_hw_state
)(struct drm_i915_private
*dev_priv
,
406 struct intel_shared_dpll
*pll
,
407 struct intel_dpll_hw_state
*hw_state
);
415 /* Used by dp and fdi links */
416 struct intel_link_m_n
{
424 void intel_link_compute_m_n(int bpp
, int nlanes
,
425 int pixel_clock
, int link_clock
,
426 struct intel_link_m_n
*m_n
);
428 /* Interface history:
431 * 1.2: Add Power Management
432 * 1.3: Add vblank support
433 * 1.4: Fix cmdbuffer path, add heap destroy
434 * 1.5: Add vblank pipe configuration
435 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
436 * - Support vertical blank on secondary display pipe
438 #define DRIVER_MAJOR 1
439 #define DRIVER_MINOR 6
440 #define DRIVER_PATCHLEVEL 0
442 #define WATCH_LISTS 0
444 struct opregion_header
;
445 struct opregion_acpi
;
446 struct opregion_swsci
;
447 struct opregion_asle
;
449 struct intel_opregion
{
450 struct opregion_header
*header
;
451 struct opregion_acpi
*acpi
;
452 struct opregion_swsci
*swsci
;
453 u32 swsci_gbda_sub_functions
;
454 u32 swsci_sbcb_sub_functions
;
455 struct opregion_asle
*asle
;
460 struct work_struct asle_work
;
462 #define OPREGION_SIZE (8*1024)
464 struct intel_overlay
;
465 struct intel_overlay_error_state
;
467 #define I915_FENCE_REG_NONE -1
468 #define I915_MAX_NUM_FENCES 32
469 /* 32 fences + sign bit for FENCE_REG_NONE */
470 #define I915_MAX_NUM_FENCE_BITS 6
472 struct drm_i915_fence_reg
{
473 struct list_head lru_list
;
474 struct drm_i915_gem_object
*obj
;
478 struct sdvo_device_mapping
{
487 struct intel_display_error_state
;
489 struct drm_i915_error_state
{
498 /* Generic register state */
506 u32 error
; /* gen6+ */
507 u32 err_int
; /* gen7 */
508 u32 fault_data0
; /* gen8, gen9 */
509 u32 fault_data1
; /* gen8, gen9 */
515 u32 extra_instdone
[I915_NUM_INSTDONE_REG
];
516 u64 fence
[I915_MAX_NUM_FENCES
];
517 struct intel_overlay_error_state
*overlay
;
518 struct intel_display_error_state
*display
;
519 struct drm_i915_error_object
*semaphore_obj
;
521 struct drm_i915_error_ring
{
523 /* Software tracked state */
526 enum intel_ring_hangcheck_action hangcheck_action
;
529 /* our own tracking of ring head and tail */
533 u32 semaphore_seqno
[I915_NUM_RINGS
- 1];
552 u32 rc_psmi
; /* sleep state */
553 u32 semaphore_mboxes
[I915_NUM_RINGS
- 1];
555 struct drm_i915_error_object
{
559 } *ringbuffer
, *batchbuffer
, *wa_batchbuffer
, *ctx
, *hws_page
;
561 struct drm_i915_error_request
{
576 char comm
[TASK_COMM_LEN
];
577 } ring
[I915_NUM_RINGS
];
579 struct drm_i915_error_buffer
{
582 u32 rseqno
[I915_NUM_RINGS
], wseqno
;
586 s32 fence_reg
:I915_MAX_NUM_FENCE_BITS
;
594 } **active_bo
, **pinned_bo
;
596 u32
*active_bo_count
, *pinned_bo_count
;
600 struct intel_connector
;
601 struct intel_encoder
;
602 struct intel_crtc_state
;
603 struct intel_initial_plane_config
;
608 struct drm_i915_display_funcs
{
609 int (*get_display_clock_speed
)(struct drm_device
*dev
);
610 int (*get_fifo_size
)(struct drm_device
*dev
, int plane
);
612 * find_dpll() - Find the best values for the PLL
613 * @limit: limits for the PLL
614 * @crtc: current CRTC
615 * @target: target frequency in kHz
616 * @refclk: reference clock frequency in kHz
617 * @match_clock: if provided, @best_clock P divider must
618 * match the P divider from @match_clock
619 * used for LVDS downclocking
620 * @best_clock: best PLL values found
622 * Returns true on success, false on failure.
624 bool (*find_dpll
)(const struct intel_limit
*limit
,
625 struct intel_crtc_state
*crtc_state
,
626 int target
, int refclk
,
627 struct dpll
*match_clock
,
628 struct dpll
*best_clock
);
629 int (*compute_pipe_wm
)(struct intel_crtc
*crtc
,
630 struct drm_atomic_state
*state
);
631 void (*program_watermarks
)(struct intel_crtc_state
*cstate
);
632 void (*update_wm
)(struct drm_crtc
*crtc
);
633 int (*modeset_calc_cdclk
)(struct drm_atomic_state
*state
);
634 void (*modeset_commit_cdclk
)(struct drm_atomic_state
*state
);
635 /* Returns the active state of the crtc, and if the crtc is active,
636 * fills out the pipe-config with the hw state. */
637 bool (*get_pipe_config
)(struct intel_crtc
*,
638 struct intel_crtc_state
*);
639 void (*get_initial_plane_config
)(struct intel_crtc
*,
640 struct intel_initial_plane_config
*);
641 int (*crtc_compute_clock
)(struct intel_crtc
*crtc
,
642 struct intel_crtc_state
*crtc_state
);
643 void (*crtc_enable
)(struct drm_crtc
*crtc
);
644 void (*crtc_disable
)(struct drm_crtc
*crtc
);
645 void (*audio_codec_enable
)(struct drm_connector
*connector
,
646 struct intel_encoder
*encoder
,
647 const struct drm_display_mode
*adjusted_mode
);
648 void (*audio_codec_disable
)(struct intel_encoder
*encoder
);
649 void (*fdi_link_train
)(struct drm_crtc
*crtc
);
650 void (*init_clock_gating
)(struct drm_device
*dev
);
651 int (*queue_flip
)(struct drm_device
*dev
, struct drm_crtc
*crtc
,
652 struct drm_framebuffer
*fb
,
653 struct drm_i915_gem_object
*obj
,
654 struct drm_i915_gem_request
*req
,
656 void (*hpd_irq_setup
)(struct drm_device
*dev
);
657 /* clock updates for mode set */
659 /* render clock increase/decrease */
660 /* display clock increase/decrease */
661 /* pll clock increase/decrease */
664 enum forcewake_domain_id
{
665 FW_DOMAIN_ID_RENDER
= 0,
666 FW_DOMAIN_ID_BLITTER
,
672 enum forcewake_domains
{
673 FORCEWAKE_RENDER
= (1 << FW_DOMAIN_ID_RENDER
),
674 FORCEWAKE_BLITTER
= (1 << FW_DOMAIN_ID_BLITTER
),
675 FORCEWAKE_MEDIA
= (1 << FW_DOMAIN_ID_MEDIA
),
676 FORCEWAKE_ALL
= (FORCEWAKE_RENDER
|
681 struct intel_uncore_funcs
{
682 void (*force_wake_get
)(struct drm_i915_private
*dev_priv
,
683 enum forcewake_domains domains
);
684 void (*force_wake_put
)(struct drm_i915_private
*dev_priv
,
685 enum forcewake_domains domains
);
687 uint8_t (*mmio_readb
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
, bool trace
);
688 uint16_t (*mmio_readw
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
, bool trace
);
689 uint32_t (*mmio_readl
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
, bool trace
);
690 uint64_t (*mmio_readq
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
, bool trace
);
692 void (*mmio_writeb
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
,
693 uint8_t val
, bool trace
);
694 void (*mmio_writew
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
,
695 uint16_t val
, bool trace
);
696 void (*mmio_writel
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
,
697 uint32_t val
, bool trace
);
698 void (*mmio_writeq
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
,
699 uint64_t val
, bool trace
);
702 struct intel_uncore
{
703 spinlock_t lock
; /** lock is also taken in irq contexts. */
705 struct intel_uncore_funcs funcs
;
708 enum forcewake_domains fw_domains
;
710 struct intel_uncore_forcewake_domain
{
711 struct drm_i915_private
*i915
;
712 enum forcewake_domain_id id
;
714 struct timer_list timer
;
721 } fw_domain
[FW_DOMAIN_ID_COUNT
];
723 int unclaimed_mmio_check
;
726 /* Iterate over initialised fw domains */
727 #define for_each_fw_domain_mask(domain__, mask__, dev_priv__, i__) \
728 for ((i__) = 0, (domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
729 (i__) < FW_DOMAIN_ID_COUNT; \
730 (i__)++, (domain__) = &(dev_priv__)->uncore.fw_domain[i__]) \
731 for_each_if (((mask__) & (dev_priv__)->uncore.fw_domains) & (1 << (i__)))
733 #define for_each_fw_domain(domain__, dev_priv__, i__) \
734 for_each_fw_domain_mask(domain__, FORCEWAKE_ALL, dev_priv__, i__)
736 #define CSR_VERSION(major, minor) ((major) << 16 | (minor))
737 #define CSR_VERSION_MAJOR(version) ((version) >> 16)
738 #define CSR_VERSION_MINOR(version) ((version) & 0xffff)
741 struct work_struct work
;
743 uint32_t *dmc_payload
;
744 uint32_t dmc_fw_size
;
747 i915_reg_t mmioaddr
[8];
748 uint32_t mmiodata
[8];
751 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
752 func(is_mobile) sep \
755 func(is_i945gm) sep \
757 func(need_gfx_hws) sep \
759 func(is_pineview) sep \
760 func(is_broadwater) sep \
761 func(is_crestline) sep \
762 func(is_ivybridge) sep \
763 func(is_valleyview) sep \
764 func(is_cherryview) sep \
765 func(is_haswell) sep \
766 func(is_skylake) sep \
767 func(is_broxton) sep \
768 func(is_kabylake) sep \
769 func(is_preliminary) sep \
771 func(has_pipe_cxsr) sep \
772 func(has_hotplug) sep \
773 func(cursor_needs_physical) sep \
774 func(has_overlay) sep \
775 func(overlay_needs_physical) sep \
776 func(supports_tv) sep \
781 #define DEFINE_FLAG(name) u8 name:1
782 #define SEP_SEMICOLON ;
784 struct intel_device_info
{
785 u32 display_mmio_offset
;
788 u8 num_sprites
[I915_MAX_PIPES
];
790 u8 ring_mask
; /* Rings supported by the HW */
791 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG
, SEP_SEMICOLON
);
792 /* Register offsets for the various display pipes and transcoders */
793 int pipe_offsets
[I915_MAX_TRANSCODERS
];
794 int trans_offsets
[I915_MAX_TRANSCODERS
];
795 int palette_offsets
[I915_MAX_PIPES
];
796 int cursor_offsets
[I915_MAX_PIPES
];
798 /* Slice/subslice/EU info */
801 u8 subslice_per_slice
;
804 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
807 u8 has_subslice_pg
:1;
814 enum i915_cache_level
{
816 I915_CACHE_LLC
, /* also used for snoopable memory on non-LLC */
817 I915_CACHE_L3_LLC
, /* gen7+, L3 sits between the domain specifc
818 caches, eg sampler/render caches, and the
819 large Last-Level-Cache. LLC is coherent with
820 the CPU, but L3 is only visible to the GPU. */
821 I915_CACHE_WT
, /* hsw:gt3e WriteThrough for scanouts */
824 struct i915_ctx_hang_stats
{
825 /* This context had batch pending when hang was declared */
826 unsigned batch_pending
;
828 /* This context had batch active when hang was declared */
829 unsigned batch_active
;
831 /* Time when this context was last blamed for a GPU reset */
832 unsigned long guilty_ts
;
834 /* If the contexts causes a second GPU hang within this time,
835 * it is permanently banned from submitting any more work.
837 unsigned long ban_period_seconds
;
839 /* This context is banned to submit more work */
843 /* This must match up with the value previously used for execbuf2.rsvd1. */
844 #define DEFAULT_CONTEXT_HANDLE 0
846 #define CONTEXT_NO_ZEROMAP (1<<0)
848 * struct intel_context - as the name implies, represents a context.
849 * @ref: reference count.
850 * @user_handle: userspace tracking identity for this context.
851 * @remap_slice: l3 row remapping information.
852 * @flags: context specific flags:
853 * CONTEXT_NO_ZEROMAP: do not allow mapping things to page 0.
854 * @file_priv: filp associated with this context (NULL for global default
856 * @hang_stats: information about the role of this context in possible GPU
858 * @ppgtt: virtual memory space used by this context.
859 * @legacy_hw_ctx: render context backing object and whether it is correctly
860 * initialized (legacy ring submission mechanism only).
861 * @link: link in the global list of contexts.
863 * Contexts are memory images used by the hardware to store copies of their
866 struct intel_context
{
870 struct drm_i915_private
*i915
;
872 struct drm_i915_file_private
*file_priv
;
873 struct i915_ctx_hang_stats hang_stats
;
874 struct i915_hw_ppgtt
*ppgtt
;
876 /* Legacy ring buffer submission */
878 struct drm_i915_gem_object
*rcs_state
;
884 struct drm_i915_gem_object
*state
;
885 struct intel_ringbuffer
*ringbuf
;
887 struct i915_vma
*lrc_vma
;
889 uint32_t *lrc_reg_state
;
890 } engine
[I915_NUM_RINGS
];
892 struct list_head link
;
904 /* This is always the inner lock when overlapping with struct_mutex and
905 * it's the outer lock when overlapping with stolen_lock. */
908 unsigned int possible_framebuffer_bits
;
909 unsigned int busy_bits
;
910 unsigned int visible_pipes_mask
;
911 struct intel_crtc
*crtc
;
913 struct drm_mm_node compressed_fb
;
914 struct drm_mm_node
*compressed_llb
;
921 struct intel_fbc_state_cache
{
923 unsigned int mode_flags
;
924 uint32_t hsw_bdw_pixel_rate
;
928 unsigned int rotation
;
936 uint32_t pixel_format
;
939 unsigned int tiling_mode
;
943 struct intel_fbc_reg_params
{
947 unsigned int fence_y_offset
;
952 uint32_t pixel_format
;
960 struct intel_fbc_work
{
962 u32 scheduled_vblank
;
963 struct work_struct work
;
966 const char *no_fbc_reason
;
968 bool (*is_active
)(struct drm_i915_private
*dev_priv
);
969 void (*activate
)(struct drm_i915_private
*dev_priv
);
970 void (*deactivate
)(struct drm_i915_private
*dev_priv
);
974 * HIGH_RR is the highest eDP panel refresh rate read from EDID
975 * LOW_RR is the lowest eDP panel refresh rate found from EDID
976 * parsing for same resolution.
978 enum drrs_refresh_rate_type
{
981 DRRS_MAX_RR
, /* RR count */
984 enum drrs_support_type
{
985 DRRS_NOT_SUPPORTED
= 0,
986 STATIC_DRRS_SUPPORT
= 1,
987 SEAMLESS_DRRS_SUPPORT
= 2
993 struct delayed_work work
;
995 unsigned busy_frontbuffer_bits
;
996 enum drrs_refresh_rate_type refresh_rate_type
;
997 enum drrs_support_type type
;
1004 struct intel_dp
*enabled
;
1006 struct delayed_work work
;
1007 unsigned busy_frontbuffer_bits
;
1009 bool aux_frame_sync
;
1013 PCH_NONE
= 0, /* No PCH present */
1014 PCH_IBX
, /* Ibexpeak PCH */
1015 PCH_CPT
, /* Cougarpoint PCH */
1016 PCH_LPT
, /* Lynxpoint PCH */
1017 PCH_SPT
, /* Sunrisepoint PCH */
1021 enum intel_sbi_destination
{
1026 #define QUIRK_PIPEA_FORCE (1<<0)
1027 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
1028 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
1029 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
1030 #define QUIRK_PIPEB_FORCE (1<<4)
1031 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
1034 struct intel_fbc_work
;
1036 struct intel_gmbus
{
1037 struct i2c_adapter adapter
;
1040 i915_reg_t gpio_reg
;
1041 struct i2c_algo_bit_data bit_algo
;
1042 struct drm_i915_private
*dev_priv
;
1045 struct i915_suspend_saved_registers
{
1048 u32 savePP_ON_DELAYS
;
1049 u32 savePP_OFF_DELAYS
;
1054 u32 saveFBC_CONTROL
;
1055 u32 saveCACHE_MODE_0
;
1056 u32 saveMI_ARB_STATE
;
1060 uint64_t saveFENCE
[I915_MAX_NUM_FENCES
];
1061 u32 savePCH_PORT_HOTPLUG
;
1065 struct vlv_s0ix_state
{
1072 u32 lra_limits
[GEN7_LRA_LIMITS_REG_NUM
];
1073 u32 media_max_req_count
;
1074 u32 gfx_max_req_count
;
1100 u32 rp_down_timeout
;
1106 /* Display 1 CZ domain */
1111 u32 gt_scratch
[GEN7_GT_SCRATCH_REG_NUM
];
1113 /* GT SA CZ domain */
1120 /* Display 2 CZ domain */
1124 u32 clock_gate_dis2
;
1127 struct intel_rps_ei
{
1133 struct intel_gen6_power_mgmt
{
1135 * work, interrupts_enabled and pm_iir are protected by
1136 * dev_priv->irq_lock
1138 struct work_struct work
;
1139 bool interrupts_enabled
;
1142 /* Frequencies are stored in potentially platform dependent multiples.
1143 * In other words, *_freq needs to be multiplied by X to be interesting.
1144 * Soft limits are those which are used for the dynamic reclocking done
1145 * by the driver (raise frequencies under heavy loads, and lower for
1146 * lighter loads). Hard limits are those imposed by the hardware.
1148 * A distinction is made for overclocking, which is never enabled by
1149 * default, and is considered to be above the hard limit if it's
1152 u8 cur_freq
; /* Current frequency (cached, may not == HW) */
1153 u8 min_freq_softlimit
; /* Minimum frequency permitted by the driver */
1154 u8 max_freq_softlimit
; /* Max frequency permitted by the driver */
1155 u8 max_freq
; /* Maximum frequency, RP0 if not overclocking */
1156 u8 min_freq
; /* AKA RPn. Minimum frequency */
1157 u8 idle_freq
; /* Frequency to request when we are idle */
1158 u8 efficient_freq
; /* AKA RPe. Pre-determined balanced frequency */
1159 u8 rp1_freq
; /* "less than" RP0 power/freqency */
1160 u8 rp0_freq
; /* Non-overclocked max frequency. */
1162 u8 up_threshold
; /* Current %busy required to uplock */
1163 u8 down_threshold
; /* Current %busy required to downclock */
1166 enum { LOW_POWER
, BETWEEN
, HIGH_POWER
} power
;
1168 spinlock_t client_lock
;
1169 struct list_head clients
;
1173 struct delayed_work delayed_resume_work
;
1176 struct intel_rps_client semaphores
, mmioflips
;
1178 /* manual wa residency calculations */
1179 struct intel_rps_ei up_ei
, down_ei
;
1182 * Protects RPS/RC6 register access and PCU communication.
1183 * Must be taken after struct_mutex if nested. Note that
1184 * this lock may be held for long periods of time when
1185 * talking to hw - so only take it when talking to hw!
1187 struct mutex hw_lock
;
1190 /* defined intel_pm.c */
1191 extern spinlock_t mchdev_lock
;
1193 struct intel_ilk_power_mgmt
{
1201 unsigned long last_time1
;
1202 unsigned long chipset_power
;
1205 unsigned long gfx_power
;
1212 struct drm_i915_private
;
1213 struct i915_power_well
;
1215 struct i915_power_well_ops
{
1217 * Synchronize the well's hw state to match the current sw state, for
1218 * example enable/disable it based on the current refcount. Called
1219 * during driver init and resume time, possibly after first calling
1220 * the enable/disable handlers.
1222 void (*sync_hw
)(struct drm_i915_private
*dev_priv
,
1223 struct i915_power_well
*power_well
);
1225 * Enable the well and resources that depend on it (for example
1226 * interrupts located on the well). Called after the 0->1 refcount
1229 void (*enable
)(struct drm_i915_private
*dev_priv
,
1230 struct i915_power_well
*power_well
);
1232 * Disable the well and resources that depend on it. Called after
1233 * the 1->0 refcount transition.
1235 void (*disable
)(struct drm_i915_private
*dev_priv
,
1236 struct i915_power_well
*power_well
);
1237 /* Returns the hw enabled state. */
1238 bool (*is_enabled
)(struct drm_i915_private
*dev_priv
,
1239 struct i915_power_well
*power_well
);
1242 /* Power well structure for haswell */
1243 struct i915_power_well
{
1246 /* power well enable/disable usage count */
1248 /* cached hw enabled state */
1250 unsigned long domains
;
1252 const struct i915_power_well_ops
*ops
;
1255 struct i915_power_domains
{
1257 * Power wells needed for initialization at driver init and suspend
1258 * time are on. They are kept on until after the first modeset.
1262 int power_well_count
;
1265 int domain_use_count
[POWER_DOMAIN_NUM
];
1266 struct i915_power_well
*power_wells
;
1269 #define MAX_L3_SLICES 2
1270 struct intel_l3_parity
{
1271 u32
*remap_info
[MAX_L3_SLICES
];
1272 struct work_struct error_work
;
1276 struct i915_gem_mm
{
1277 /** Memory allocator for GTT stolen memory */
1278 struct drm_mm stolen
;
1279 /** Protects the usage of the GTT stolen memory allocator. This is
1280 * always the inner lock when overlapping with struct_mutex. */
1281 struct mutex stolen_lock
;
1283 /** List of all objects in gtt_space. Used to restore gtt
1284 * mappings on resume */
1285 struct list_head bound_list
;
1287 * List of objects which are not bound to the GTT (thus
1288 * are idle and not used by the GPU) but still have
1289 * (presumably uncached) pages still attached.
1291 struct list_head unbound_list
;
1293 /** Usable portion of the GTT for GEM */
1294 unsigned long stolen_base
; /* limited to low memory (32-bit) */
1296 /** PPGTT used for aliasing the PPGTT with the GTT */
1297 struct i915_hw_ppgtt
*aliasing_ppgtt
;
1299 struct notifier_block oom_notifier
;
1300 struct shrinker shrinker
;
1301 bool shrinker_no_lock_stealing
;
1303 /** LRU list of objects with fence regs on them. */
1304 struct list_head fence_list
;
1307 * We leave the user IRQ off as much as possible,
1308 * but this means that requests will finish and never
1309 * be retired once the system goes idle. Set a timer to
1310 * fire periodically while the ring is running. When it
1311 * fires, go retire requests.
1313 struct delayed_work retire_work
;
1316 * When we detect an idle GPU, we want to turn on
1317 * powersaving features. So once we see that there
1318 * are no more requests outstanding and no more
1319 * arrive within a small period of time, we fire
1320 * off the idle_work.
1322 struct delayed_work idle_work
;
1325 * Are we in a non-interruptible section of code like
1331 * Is the GPU currently considered idle, or busy executing userspace
1332 * requests? Whilst idle, we attempt to power down the hardware and
1333 * display clocks. In order to reduce the effect on performance, there
1334 * is a slight delay before we do so.
1338 /* the indicator for dispatch video commands on two BSD rings */
1339 unsigned int bsd_ring_dispatch_index
;
1341 /** Bit 6 swizzling required for X tiling */
1342 uint32_t bit_6_swizzle_x
;
1343 /** Bit 6 swizzling required for Y tiling */
1344 uint32_t bit_6_swizzle_y
;
1346 /* accounting, useful for userland debugging */
1347 spinlock_t object_stat_lock
;
1348 size_t object_memory
;
1352 struct drm_i915_error_state_buf
{
1353 struct drm_i915_private
*i915
;
1362 struct i915_error_state_file_priv
{
1363 struct drm_device
*dev
;
1364 struct drm_i915_error_state
*error
;
1367 struct i915_gpu_error
{
1368 /* For hangcheck timer */
1369 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1370 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1371 /* Hang gpu twice in this window and your context gets banned */
1372 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1374 struct workqueue_struct
*hangcheck_wq
;
1375 struct delayed_work hangcheck_work
;
1377 /* For reset and error_state handling. */
1379 /* Protected by the above dev->gpu_error.lock. */
1380 struct drm_i915_error_state
*first_error
;
1382 unsigned long missed_irq_rings
;
1385 * State variable controlling the reset flow and count
1387 * This is a counter which gets incremented when reset is triggered,
1388 * and again when reset has been handled. So odd values (lowest bit set)
1389 * means that reset is in progress and even values that
1390 * (reset_counter >> 1):th reset was successfully completed.
1392 * If reset is not completed succesfully, the I915_WEDGE bit is
1393 * set meaning that hardware is terminally sour and there is no
1394 * recovery. All waiters on the reset_queue will be woken when
1397 * This counter is used by the wait_seqno code to notice that reset
1398 * event happened and it needs to restart the entire ioctl (since most
1399 * likely the seqno it waited for won't ever signal anytime soon).
1401 * This is important for lock-free wait paths, where no contended lock
1402 * naturally enforces the correct ordering between the bail-out of the
1403 * waiter and the gpu reset work code.
1405 atomic_t reset_counter
;
1407 #define I915_RESET_IN_PROGRESS_FLAG 1
1408 #define I915_WEDGED (1 << 31)
1411 * Waitqueue to signal when the reset has completed. Used by clients
1412 * that wait for dev_priv->mm.wedged to settle.
1414 wait_queue_head_t reset_queue
;
1416 /* Userspace knobs for gpu hang simulation;
1417 * combines both a ring mask, and extra flags
1420 #define I915_STOP_RING_ALLOW_BAN (1 << 31)
1421 #define I915_STOP_RING_ALLOW_WARN (1 << 30)
1423 /* For missed irq/seqno simulation. */
1424 unsigned int test_irq_rings
;
1426 /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
1427 bool reload_in_reset
;
1430 enum modeset_restore
{
1431 MODESET_ON_LID_OPEN
,
1436 #define DP_AUX_A 0x40
1437 #define DP_AUX_B 0x10
1438 #define DP_AUX_C 0x20
1439 #define DP_AUX_D 0x30
1441 #define DDC_PIN_B 0x05
1442 #define DDC_PIN_C 0x04
1443 #define DDC_PIN_D 0x06
1445 struct ddi_vbt_port_info
{
1447 * This is an index in the HDMI/DVI DDI buffer translation table.
1448 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1449 * populate this field.
1451 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1452 uint8_t hdmi_level_shift
;
1454 uint8_t supports_dvi
:1;
1455 uint8_t supports_hdmi
:1;
1456 uint8_t supports_dp
:1;
1458 uint8_t alternate_aux_channel
;
1459 uint8_t alternate_ddc_pin
;
1461 uint8_t dp_boost_level
;
1462 uint8_t hdmi_boost_level
;
1465 enum psr_lines_to_wait
{
1466 PSR_0_LINES_TO_WAIT
= 0,
1468 PSR_4_LINES_TO_WAIT
,
1472 struct intel_vbt_data
{
1473 struct drm_display_mode
*lfp_lvds_vbt_mode
; /* if any */
1474 struct drm_display_mode
*sdvo_lvds_vbt_mode
; /* if any */
1477 unsigned int int_tv_support
:1;
1478 unsigned int lvds_dither
:1;
1479 unsigned int lvds_vbt
:1;
1480 unsigned int int_crt_support
:1;
1481 unsigned int lvds_use_ssc
:1;
1482 unsigned int display_clock_mode
:1;
1483 unsigned int fdi_rx_polarity_inverted
:1;
1484 unsigned int has_mipi
:1;
1486 unsigned int bios_lvds_val
; /* initial [PCH_]LVDS reg val in VBIOS */
1488 enum drrs_support_type drrs_type
;
1493 int edp_preemphasis
;
1495 bool edp_initialized
;
1498 struct edp_power_seq edp_pps
;
1502 bool require_aux_wakeup
;
1504 enum psr_lines_to_wait lines_to_wait
;
1505 int tp1_wakeup_time
;
1506 int tp2_tp3_wakeup_time
;
1512 bool active_low_pwm
;
1513 u8 min_brightness
; /* min_brightness/255 of max */
1520 struct mipi_config
*config
;
1521 struct mipi_pps_data
*pps
;
1525 const u8
*sequence
[MIPI_SEQ_MAX
];
1531 union child_device_config
*child_dev
;
1533 struct ddi_vbt_port_info ddi_port_info
[I915_MAX_PORTS
];
1536 enum intel_ddb_partitioning
{
1538 INTEL_DDB_PART_5_6
, /* IVB+ */
1541 struct intel_wm_level
{
1549 struct ilk_wm_values
{
1550 uint32_t wm_pipe
[3];
1552 uint32_t wm_lp_spr
[3];
1553 uint32_t wm_linetime
[3];
1555 enum intel_ddb_partitioning partitioning
;
1558 struct vlv_pipe_wm
{
1569 struct vlv_wm_values
{
1570 struct vlv_pipe_wm pipe
[3];
1571 struct vlv_sr_wm sr
;
1581 struct skl_ddb_entry
{
1582 uint16_t start
, end
; /* in number of blocks, 'end' is exclusive */
1585 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry
*entry
)
1587 return entry
->end
- entry
->start
;
1590 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry
*e1
,
1591 const struct skl_ddb_entry
*e2
)
1593 if (e1
->start
== e2
->start
&& e1
->end
== e2
->end
)
1599 struct skl_ddb_allocation
{
1600 struct skl_ddb_entry pipe
[I915_MAX_PIPES
];
1601 struct skl_ddb_entry plane
[I915_MAX_PIPES
][I915_MAX_PLANES
]; /* packed/uv */
1602 struct skl_ddb_entry y_plane
[I915_MAX_PIPES
][I915_MAX_PLANES
];
1605 struct skl_wm_values
{
1606 bool dirty
[I915_MAX_PIPES
];
1607 struct skl_ddb_allocation ddb
;
1608 uint32_t wm_linetime
[I915_MAX_PIPES
];
1609 uint32_t plane
[I915_MAX_PIPES
][I915_MAX_PLANES
][8];
1610 uint32_t plane_trans
[I915_MAX_PIPES
][I915_MAX_PLANES
];
1613 struct skl_wm_level
{
1614 bool plane_en
[I915_MAX_PLANES
];
1615 uint16_t plane_res_b
[I915_MAX_PLANES
];
1616 uint8_t plane_res_l
[I915_MAX_PLANES
];
1620 * This struct helps tracking the state needed for runtime PM, which puts the
1621 * device in PCI D3 state. Notice that when this happens, nothing on the
1622 * graphics device works, even register access, so we don't get interrupts nor
1625 * Every piece of our code that needs to actually touch the hardware needs to
1626 * either call intel_runtime_pm_get or call intel_display_power_get with the
1627 * appropriate power domain.
1629 * Our driver uses the autosuspend delay feature, which means we'll only really
1630 * suspend if we stay with zero refcount for a certain amount of time. The
1631 * default value is currently very conservative (see intel_runtime_pm_enable), but
1632 * it can be changed with the standard runtime PM files from sysfs.
1634 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1635 * goes back to false exactly before we reenable the IRQs. We use this variable
1636 * to check if someone is trying to enable/disable IRQs while they're supposed
1637 * to be disabled. This shouldn't happen and we'll print some error messages in
1640 * For more, read the Documentation/power/runtime_pm.txt.
1642 struct i915_runtime_pm
{
1643 atomic_t wakeref_count
;
1644 atomic_t atomic_seq
;
1649 enum intel_pipe_crc_source
{
1650 INTEL_PIPE_CRC_SOURCE_NONE
,
1651 INTEL_PIPE_CRC_SOURCE_PLANE1
,
1652 INTEL_PIPE_CRC_SOURCE_PLANE2
,
1653 INTEL_PIPE_CRC_SOURCE_PF
,
1654 INTEL_PIPE_CRC_SOURCE_PIPE
,
1655 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1656 INTEL_PIPE_CRC_SOURCE_TV
,
1657 INTEL_PIPE_CRC_SOURCE_DP_B
,
1658 INTEL_PIPE_CRC_SOURCE_DP_C
,
1659 INTEL_PIPE_CRC_SOURCE_DP_D
,
1660 INTEL_PIPE_CRC_SOURCE_AUTO
,
1661 INTEL_PIPE_CRC_SOURCE_MAX
,
1664 struct intel_pipe_crc_entry
{
1669 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1670 struct intel_pipe_crc
{
1672 bool opened
; /* exclusive access to the result file */
1673 struct intel_pipe_crc_entry
*entries
;
1674 enum intel_pipe_crc_source source
;
1676 wait_queue_head_t wq
;
1679 struct i915_frontbuffer_tracking
{
1683 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1690 struct i915_wa_reg
{
1693 /* bitmask representing WA bits */
1698 * RING_MAX_NONPRIV_SLOTS is per-engine but at this point we are only
1699 * allowing it for RCS as we don't foresee any requirement of having
1700 * a whitelist for other engines. When it is really required for
1701 * other engines then the limit need to be increased.
1703 #define I915_MAX_WA_REGS (16 + RING_MAX_NONPRIV_SLOTS)
1705 struct i915_workarounds
{
1706 struct i915_wa_reg reg
[I915_MAX_WA_REGS
];
1708 u32 hw_whitelist_count
[I915_NUM_RINGS
];
1711 struct i915_virtual_gpu
{
1715 struct i915_execbuffer_params
{
1716 struct drm_device
*dev
;
1717 struct drm_file
*file
;
1718 uint32_t dispatch_flags
;
1719 uint32_t args_batch_start_offset
;
1720 uint64_t batch_obj_vm_offset
;
1721 struct intel_engine_cs
*ring
;
1722 struct drm_i915_gem_object
*batch_obj
;
1723 struct intel_context
*ctx
;
1724 struct drm_i915_gem_request
*request
;
1727 /* used in computing the new watermarks state */
1728 struct intel_wm_config
{
1729 unsigned int num_pipes_active
;
1730 bool sprites_enabled
;
1731 bool sprites_scaled
;
1734 struct drm_i915_private
{
1735 struct drm_device
*dev
;
1736 struct kmem_cache
*objects
;
1737 struct kmem_cache
*vmas
;
1738 struct kmem_cache
*requests
;
1740 const struct intel_device_info info
;
1742 int relative_constants_mode
;
1746 struct intel_uncore uncore
;
1748 struct i915_virtual_gpu vgpu
;
1750 struct intel_guc guc
;
1752 struct intel_csr csr
;
1754 struct intel_gmbus gmbus
[GMBUS_NUM_PINS
];
1756 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1757 * controller on different i2c buses. */
1758 struct mutex gmbus_mutex
;
1761 * Base address of the gmbus and gpio block.
1763 uint32_t gpio_mmio_base
;
1765 /* MMIO base address for MIPI regs */
1766 uint32_t mipi_mmio_base
;
1768 uint32_t psr_mmio_base
;
1770 wait_queue_head_t gmbus_wait_queue
;
1772 struct pci_dev
*bridge_dev
;
1773 struct intel_engine_cs ring
[I915_NUM_RINGS
];
1774 struct drm_i915_gem_object
*semaphore_obj
;
1775 uint32_t last_seqno
, next_seqno
;
1777 struct drm_dma_handle
*status_page_dmah
;
1778 struct resource mch_res
;
1780 /* protects the irq masks */
1781 spinlock_t irq_lock
;
1783 /* protects the mmio flip data */
1784 spinlock_t mmio_flip_lock
;
1786 bool display_irqs_enabled
;
1788 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1789 struct pm_qos_request pm_qos
;
1791 /* Sideband mailbox protection */
1792 struct mutex sb_lock
;
1794 /** Cached value of IMR to avoid reads in updating the bitfield */
1797 u32 de_irq_mask
[I915_MAX_PIPES
];
1802 u32 pipestat_irq_mask
[I915_MAX_PIPES
];
1804 struct i915_hotplug hotplug
;
1805 struct intel_fbc fbc
;
1806 struct i915_drrs drrs
;
1807 struct intel_opregion opregion
;
1808 struct intel_vbt_data vbt
;
1810 bool preserve_bios_swizzle
;
1813 struct intel_overlay
*overlay
;
1815 /* backlight registers and fields in struct intel_panel */
1816 struct mutex backlight_lock
;
1819 bool no_aux_handshake
;
1821 /* protects panel power sequencer state */
1822 struct mutex pps_mutex
;
1824 struct drm_i915_fence_reg fence_regs
[I915_MAX_NUM_FENCES
]; /* assume 965 */
1825 int num_fence_regs
; /* 8 on pre-965, 16 otherwise */
1827 unsigned int fsb_freq
, mem_freq
, is_ddr3
;
1828 unsigned int skl_boot_cdclk
;
1829 unsigned int cdclk_freq
, max_cdclk_freq
, atomic_cdclk_freq
;
1830 unsigned int max_dotclk_freq
;
1831 unsigned int hpll_freq
;
1832 unsigned int czclk_freq
;
1835 * wq - Driver workqueue for GEM.
1837 * NOTE: Work items scheduled here are not allowed to grab any modeset
1838 * locks, for otherwise the flushing done in the pageflip code will
1839 * result in deadlocks.
1841 struct workqueue_struct
*wq
;
1843 /* Display functions */
1844 struct drm_i915_display_funcs display
;
1846 /* PCH chipset type */
1847 enum intel_pch pch_type
;
1848 unsigned short pch_id
;
1850 unsigned long quirks
;
1852 enum modeset_restore modeset_restore
;
1853 struct mutex modeset_restore_lock
;
1855 struct list_head vm_list
; /* Global list of all address spaces */
1856 struct i915_gtt gtt
; /* VM representing the global address space */
1858 struct i915_gem_mm mm
;
1859 DECLARE_HASHTABLE(mm_structs
, 7);
1860 struct mutex mm_lock
;
1862 /* Kernel Modesetting */
1864 struct sdvo_device_mapping sdvo_mappings
[2];
1866 struct drm_crtc
*plane_to_crtc_mapping
[I915_MAX_PIPES
];
1867 struct drm_crtc
*pipe_to_crtc_mapping
[I915_MAX_PIPES
];
1868 wait_queue_head_t pending_flip_queue
;
1870 #ifdef CONFIG_DEBUG_FS
1871 struct intel_pipe_crc pipe_crc
[I915_MAX_PIPES
];
1874 /* dpll and cdclk state is protected by connection_mutex */
1875 int num_shared_dpll
;
1876 struct intel_shared_dpll shared_dplls
[I915_NUM_PLLS
];
1878 unsigned int active_crtcs
;
1879 unsigned int min_pixclk
[I915_MAX_PIPES
];
1881 int dpio_phy_iosf_port
[I915_NUM_PHYS_VLV
];
1883 struct i915_workarounds workarounds
;
1885 /* Reclocking support */
1886 bool render_reclock_avail
;
1888 struct i915_frontbuffer_tracking fb_tracking
;
1892 bool mchbar_need_disable
;
1894 struct intel_l3_parity l3_parity
;
1896 /* Cannot be determined by PCIID. You must always read a register. */
1899 /* gen6+ rps state */
1900 struct intel_gen6_power_mgmt rps
;
1902 /* ilk-only ips/rps state. Everything in here is protected by the global
1903 * mchdev_lock in intel_pm.c */
1904 struct intel_ilk_power_mgmt ips
;
1906 struct i915_power_domains power_domains
;
1908 struct i915_psr psr
;
1910 struct i915_gpu_error gpu_error
;
1912 struct drm_i915_gem_object
*vlv_pctx
;
1914 #ifdef CONFIG_DRM_FBDEV_EMULATION
1915 /* list of fbdev register on this device */
1916 struct intel_fbdev
*fbdev
;
1917 struct work_struct fbdev_suspend_work
;
1920 struct drm_property
*broadcast_rgb_property
;
1921 struct drm_property
*force_audio_property
;
1923 /* hda/i915 audio component */
1924 struct i915_audio_component
*audio_component
;
1925 bool audio_component_registered
;
1927 * av_mutex - mutex for audio/video sync
1930 struct mutex av_mutex
;
1932 uint32_t hw_context_size
;
1933 struct list_head context_list
;
1937 u32 chv_phy_control
;
1940 bool suspended_to_idle
;
1941 struct i915_suspend_saved_registers regfile
;
1942 struct vlv_s0ix_state vlv_s0ix_state
;
1946 * Raw watermark latency values:
1947 * in 0.1us units for WM0,
1948 * in 0.5us units for WM1+.
1951 uint16_t pri_latency
[5];
1953 uint16_t spr_latency
[5];
1955 uint16_t cur_latency
[5];
1957 * Raw watermark memory latency values
1958 * for SKL for all 8 levels
1961 uint16_t skl_latency
[8];
1963 /* Committed wm config */
1964 struct intel_wm_config config
;
1967 * The skl_wm_values structure is a bit too big for stack
1968 * allocation, so we keep the staging struct where we store
1969 * intermediate results here instead.
1971 struct skl_wm_values skl_results
;
1973 /* current hardware state */
1975 struct ilk_wm_values hw
;
1976 struct skl_wm_values skl_hw
;
1977 struct vlv_wm_values vlv
;
1983 struct i915_runtime_pm pm
;
1985 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
1987 int (*execbuf_submit
)(struct i915_execbuffer_params
*params
,
1988 struct drm_i915_gem_execbuffer2
*args
,
1989 struct list_head
*vmas
);
1990 int (*init_rings
)(struct drm_device
*dev
);
1991 void (*cleanup_ring
)(struct intel_engine_cs
*ring
);
1992 void (*stop_ring
)(struct intel_engine_cs
*ring
);
1995 struct intel_context
*kernel_context
;
1997 bool edp_low_vswing
;
1999 /* perform PHY state sanity checks? */
2000 bool chv_phy_assert
[2];
2002 struct intel_encoder
*dig_port_map
[I915_MAX_PORTS
];
2005 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
2006 * will be rejected. Instead look for a better place.
2010 static inline struct drm_i915_private
*to_i915(const struct drm_device
*dev
)
2012 return dev
->dev_private
;
2015 static inline struct drm_i915_private
*dev_to_i915(struct device
*dev
)
2017 return to_i915(dev_get_drvdata(dev
));
2020 static inline struct drm_i915_private
*guc_to_i915(struct intel_guc
*guc
)
2022 return container_of(guc
, struct drm_i915_private
, guc
);
2025 /* Iterate over initialised rings */
2026 #define for_each_ring(ring__, dev_priv__, i__) \
2027 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
2028 for_each_if ((((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__))))
2030 enum hdmi_force_audio
{
2031 HDMI_AUDIO_OFF_DVI
= -2, /* no aux data for HDMI-DVI converter */
2032 HDMI_AUDIO_OFF
, /* force turn off HDMI audio */
2033 HDMI_AUDIO_AUTO
, /* trust EDID */
2034 HDMI_AUDIO_ON
, /* force turn on HDMI audio */
2037 #define I915_GTT_OFFSET_NONE ((u32)-1)
2039 struct drm_i915_gem_object_ops
{
2040 /* Interface between the GEM object and its backing storage.
2041 * get_pages() is called once prior to the use of the associated set
2042 * of pages before to binding them into the GTT, and put_pages() is
2043 * called after we no longer need them. As we expect there to be
2044 * associated cost with migrating pages between the backing storage
2045 * and making them available for the GPU (e.g. clflush), we may hold
2046 * onto the pages after they are no longer referenced by the GPU
2047 * in case they may be used again shortly (for example migrating the
2048 * pages to a different memory domain within the GTT). put_pages()
2049 * will therefore most likely be called when the object itself is
2050 * being released or under memory pressure (where we attempt to
2051 * reap pages for the shrinker).
2053 int (*get_pages
)(struct drm_i915_gem_object
*);
2054 void (*put_pages
)(struct drm_i915_gem_object
*);
2055 int (*dmabuf_export
)(struct drm_i915_gem_object
*);
2056 void (*release
)(struct drm_i915_gem_object
*);
2060 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2061 * considered to be the frontbuffer for the given plane interface-wise. This
2062 * doesn't mean that the hw necessarily already scans it out, but that any
2063 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
2065 * We have one bit per pipe and per scanout plane type.
2067 #define INTEL_MAX_SPRITE_BITS_PER_PIPE 5
2068 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2069 #define INTEL_FRONTBUFFER_BITS \
2070 (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES)
2071 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
2072 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2073 #define INTEL_FRONTBUFFER_CURSOR(pipe) \
2074 (1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2075 #define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \
2076 (1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2077 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2078 (1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2079 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2080 (0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2082 struct drm_i915_gem_object
{
2083 struct drm_gem_object base
;
2085 const struct drm_i915_gem_object_ops
*ops
;
2087 /** List of VMAs backed by this object */
2088 struct list_head vma_list
;
2090 /** Stolen memory for this object, instead of being backed by shmem. */
2091 struct drm_mm_node
*stolen
;
2092 struct list_head global_list
;
2094 struct list_head ring_list
[I915_NUM_RINGS
];
2095 /** Used in execbuf to temporarily hold a ref */
2096 struct list_head obj_exec_link
;
2098 struct list_head batch_pool_link
;
2101 * This is set if the object is on the active lists (has pending
2102 * rendering and so a non-zero seqno), and is not set if it i s on
2103 * inactive (ready to be unbound) list.
2105 unsigned int active
:I915_NUM_RINGS
;
2108 * This is set if the object has been written to since last bound
2111 unsigned int dirty
:1;
2114 * Fence register bits (if any) for this object. Will be set
2115 * as needed when mapped into the GTT.
2116 * Protected by dev->struct_mutex.
2118 signed int fence_reg
:I915_MAX_NUM_FENCE_BITS
;
2121 * Advice: are the backing pages purgeable?
2123 unsigned int madv
:2;
2126 * Current tiling mode for the object.
2128 unsigned int tiling_mode
:2;
2130 * Whether the tiling parameters for the currently associated fence
2131 * register have changed. Note that for the purposes of tracking
2132 * tiling changes we also treat the unfenced register, the register
2133 * slot that the object occupies whilst it executes a fenced
2134 * command (such as BLT on gen2/3), as a "fence".
2136 unsigned int fence_dirty
:1;
2139 * Is the object at the current location in the gtt mappable and
2140 * fenceable? Used to avoid costly recalculations.
2142 unsigned int map_and_fenceable
:1;
2145 * Whether the current gtt mapping needs to be mappable (and isn't just
2146 * mappable by accident). Track pin and fault separate for a more
2147 * accurate mappable working set.
2149 unsigned int fault_mappable
:1;
2152 * Is the object to be mapped as read-only to the GPU
2153 * Only honoured if hardware has relevant pte bit
2155 unsigned long gt_ro
:1;
2156 unsigned int cache_level
:3;
2157 unsigned int cache_dirty
:1;
2159 unsigned int frontbuffer_bits
:INTEL_FRONTBUFFER_BITS
;
2161 unsigned int pin_display
;
2163 struct sg_table
*pages
;
2164 int pages_pin_count
;
2166 struct scatterlist
*sg
;
2170 /* prime dma-buf support */
2171 void *dma_buf_vmapping
;
2174 /** Breadcrumb of last rendering to the buffer.
2175 * There can only be one writer, but we allow for multiple readers.
2176 * If there is a writer that necessarily implies that all other
2177 * read requests are complete - but we may only be lazily clearing
2178 * the read requests. A read request is naturally the most recent
2179 * request on a ring, so we may have two different write and read
2180 * requests on one ring where the write request is older than the
2181 * read request. This allows for the CPU to read from an active
2182 * buffer by only waiting for the write to complete.
2184 struct drm_i915_gem_request
*last_read_req
[I915_NUM_RINGS
];
2185 struct drm_i915_gem_request
*last_write_req
;
2186 /** Breadcrumb of last fenced GPU access to the buffer. */
2187 struct drm_i915_gem_request
*last_fenced_req
;
2189 /** Current tiling stride for the object, if it's tiled. */
2192 /** References from framebuffers, locks out tiling changes. */
2193 unsigned long framebuffer_references
;
2195 /** Record of address bit 17 of each page at last unbind. */
2196 unsigned long *bit_17
;
2199 /** for phy allocated objects */
2200 struct drm_dma_handle
*phys_handle
;
2202 struct i915_gem_userptr
{
2204 unsigned read_only
:1;
2205 unsigned workers
:4;
2206 #define I915_GEM_USERPTR_MAX_WORKERS 15
2208 struct i915_mm_struct
*mm
;
2209 struct i915_mmu_object
*mmu_object
;
2210 struct work_struct
*work
;
2214 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
2216 void i915_gem_track_fb(struct drm_i915_gem_object
*old
,
2217 struct drm_i915_gem_object
*new,
2218 unsigned frontbuffer_bits
);
2221 * Request queue structure.
2223 * The request queue allows us to note sequence numbers that have been emitted
2224 * and may be associated with active buffers to be retired.
2226 * By keeping this list, we can avoid having to do questionable sequence
2227 * number comparisons on buffer last_read|write_seqno. It also allows an
2228 * emission time to be associated with the request for tracking how far ahead
2229 * of the GPU the submission is.
2231 * The requests are reference counted, so upon creation they should have an
2232 * initial reference taken using kref_init
2234 struct drm_i915_gem_request
{
2237 /** On Which ring this request was generated */
2238 struct drm_i915_private
*i915
;
2239 struct intel_engine_cs
*ring
;
2241 /** GEM sequence number associated with the previous request,
2242 * when the HWS breadcrumb is equal to this the GPU is processing
2247 /** GEM sequence number associated with this request,
2248 * when the HWS breadcrumb is equal or greater than this the GPU
2249 * has finished processing this request.
2253 /** Position in the ringbuffer of the start of the request */
2257 * Position in the ringbuffer of the start of the postfix.
2258 * This is required to calculate the maximum available ringbuffer
2259 * space without overwriting the postfix.
2263 /** Position in the ringbuffer of the end of the whole request */
2267 * Context and ring buffer related to this request
2268 * Contexts are refcounted, so when this request is associated with a
2269 * context, we must increment the context's refcount, to guarantee that
2270 * it persists while any request is linked to it. Requests themselves
2271 * are also refcounted, so the request will only be freed when the last
2272 * reference to it is dismissed, and the code in
2273 * i915_gem_request_free() will then decrement the refcount on the
2276 struct intel_context
*ctx
;
2277 struct intel_ringbuffer
*ringbuf
;
2279 /** Batch buffer related to this request if any (used for
2280 error state dump only) */
2281 struct drm_i915_gem_object
*batch_obj
;
2283 /** Time at which this request was emitted, in jiffies. */
2284 unsigned long emitted_jiffies
;
2286 /** global list entry for this request */
2287 struct list_head list
;
2289 struct drm_i915_file_private
*file_priv
;
2290 /** file_priv list entry for this request */
2291 struct list_head client_list
;
2293 /** process identifier submitting this request */
2297 * The ELSP only accepts two elements at a time, so we queue
2298 * context/tail pairs on a given queue (ring->execlist_queue) until the
2299 * hardware is available. The queue serves a double purpose: we also use
2300 * it to keep track of the up to 2 contexts currently in the hardware
2301 * (usually one in execution and the other queued up by the GPU): We
2302 * only remove elements from the head of the queue when the hardware
2303 * informs us that an element has been completed.
2305 * All accesses to the queue are mediated by a spinlock
2306 * (ring->execlist_lock).
2309 /** Execlist link in the submission queue.*/
2310 struct list_head execlist_link
;
2312 /** Execlists no. of times this request has been sent to the ELSP */
2317 struct drm_i915_gem_request
* __must_check
2318 i915_gem_request_alloc(struct intel_engine_cs
*engine
,
2319 struct intel_context
*ctx
);
2320 void i915_gem_request_cancel(struct drm_i915_gem_request
*req
);
2321 void i915_gem_request_free(struct kref
*req_ref
);
2322 int i915_gem_request_add_to_client(struct drm_i915_gem_request
*req
,
2323 struct drm_file
*file
);
2325 static inline uint32_t
2326 i915_gem_request_get_seqno(struct drm_i915_gem_request
*req
)
2328 return req
? req
->seqno
: 0;
2331 static inline struct intel_engine_cs
*
2332 i915_gem_request_get_ring(struct drm_i915_gem_request
*req
)
2334 return req
? req
->ring
: NULL
;
2337 static inline struct drm_i915_gem_request
*
2338 i915_gem_request_reference(struct drm_i915_gem_request
*req
)
2341 kref_get(&req
->ref
);
2346 i915_gem_request_unreference(struct drm_i915_gem_request
*req
)
2348 WARN_ON(!mutex_is_locked(&req
->ring
->dev
->struct_mutex
));
2349 kref_put(&req
->ref
, i915_gem_request_free
);
2353 i915_gem_request_unreference__unlocked(struct drm_i915_gem_request
*req
)
2355 struct drm_device
*dev
;
2360 dev
= req
->ring
->dev
;
2361 if (kref_put_mutex(&req
->ref
, i915_gem_request_free
, &dev
->struct_mutex
))
2362 mutex_unlock(&dev
->struct_mutex
);
2365 static inline void i915_gem_request_assign(struct drm_i915_gem_request
**pdst
,
2366 struct drm_i915_gem_request
*src
)
2369 i915_gem_request_reference(src
);
2372 i915_gem_request_unreference(*pdst
);
2378 * XXX: i915_gem_request_completed should be here but currently needs the
2379 * definition of i915_seqno_passed() which is below. It will be moved in
2380 * a later patch when the call to i915_seqno_passed() is obsoleted...
2384 * A command that requires special handling by the command parser.
2386 struct drm_i915_cmd_descriptor
{
2388 * Flags describing how the command parser processes the command.
2390 * CMD_DESC_FIXED: The command has a fixed length if this is set,
2391 * a length mask if not set
2392 * CMD_DESC_SKIP: The command is allowed but does not follow the
2393 * standard length encoding for the opcode range in
2395 * CMD_DESC_REJECT: The command is never allowed
2396 * CMD_DESC_REGISTER: The command should be checked against the
2397 * register whitelist for the appropriate ring
2398 * CMD_DESC_MASTER: The command is allowed if the submitting process
2402 #define CMD_DESC_FIXED (1<<0)
2403 #define CMD_DESC_SKIP (1<<1)
2404 #define CMD_DESC_REJECT (1<<2)
2405 #define CMD_DESC_REGISTER (1<<3)
2406 #define CMD_DESC_BITMASK (1<<4)
2407 #define CMD_DESC_MASTER (1<<5)
2410 * The command's unique identification bits and the bitmask to get them.
2411 * This isn't strictly the opcode field as defined in the spec and may
2412 * also include type, subtype, and/or subop fields.
2420 * The command's length. The command is either fixed length (i.e. does
2421 * not include a length field) or has a length field mask. The flag
2422 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
2423 * a length mask. All command entries in a command table must include
2424 * length information.
2432 * Describes where to find a register address in the command to check
2433 * against the ring's register whitelist. Only valid if flags has the
2434 * CMD_DESC_REGISTER bit set.
2436 * A non-zero step value implies that the command may access multiple
2437 * registers in sequence (e.g. LRI), in that case step gives the
2438 * distance in dwords between individual offset fields.
2446 #define MAX_CMD_DESC_BITMASKS 3
2448 * Describes command checks where a particular dword is masked and
2449 * compared against an expected value. If the command does not match
2450 * the expected value, the parser rejects it. Only valid if flags has
2451 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
2454 * If the check specifies a non-zero condition_mask then the parser
2455 * only performs the check when the bits specified by condition_mask
2462 u32 condition_offset
;
2464 } bits
[MAX_CMD_DESC_BITMASKS
];
2468 * A table of commands requiring special handling by the command parser.
2470 * Each ring has an array of tables. Each table consists of an array of command
2471 * descriptors, which must be sorted with command opcodes in ascending order.
2473 struct drm_i915_cmd_table
{
2474 const struct drm_i915_cmd_descriptor
*table
;
2478 /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
2479 #define __I915__(p) ({ \
2480 struct drm_i915_private *__p; \
2481 if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
2482 __p = (struct drm_i915_private *)p; \
2483 else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
2484 __p = to_i915((struct drm_device *)p); \
2489 #define INTEL_INFO(p) (&__I915__(p)->info)
2490 #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id)
2491 #define INTEL_REVID(p) (__I915__(p)->dev->pdev->revision)
2493 #define REVID_FOREVER 0xff
2495 * Return true if revision is in range [since,until] inclusive.
2497 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
2499 #define IS_REVID(p, since, until) \
2500 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
2502 #define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577)
2503 #define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562)
2504 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
2505 #define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572)
2506 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
2507 #define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592)
2508 #define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772)
2509 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
2510 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
2511 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
2512 #define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42)
2513 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
2514 #define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001)
2515 #define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011)
2516 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
2517 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
2518 #define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046)
2519 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
2520 #define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \
2521 INTEL_DEVID(dev) == 0x0152 || \
2522 INTEL_DEVID(dev) == 0x015a)
2523 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
2524 #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_cherryview)
2525 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
2526 #define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_cherryview && IS_GEN8(dev))
2527 #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake)
2528 #define IS_BROXTON(dev) (INTEL_INFO(dev)->is_broxton)
2529 #define IS_KABYLAKE(dev) (INTEL_INFO(dev)->is_kabylake)
2530 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
2531 #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
2532 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
2533 #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
2534 ((INTEL_DEVID(dev) & 0xf) == 0x6 || \
2535 (INTEL_DEVID(dev) & 0xf) == 0xb || \
2536 (INTEL_DEVID(dev) & 0xf) == 0xe))
2537 /* ULX machines are also considered ULT. */
2538 #define IS_BDW_ULX(dev) (IS_BROADWELL(dev) && \
2539 (INTEL_DEVID(dev) & 0xf) == 0xe)
2540 #define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \
2541 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2542 #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
2543 (INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
2544 #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
2545 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2546 /* ULX machines are also considered ULT. */
2547 #define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \
2548 INTEL_DEVID(dev) == 0x0A1E)
2549 #define IS_SKL_ULT(dev) (INTEL_DEVID(dev) == 0x1906 || \
2550 INTEL_DEVID(dev) == 0x1913 || \
2551 INTEL_DEVID(dev) == 0x1916 || \
2552 INTEL_DEVID(dev) == 0x1921 || \
2553 INTEL_DEVID(dev) == 0x1926)
2554 #define IS_SKL_ULX(dev) (INTEL_DEVID(dev) == 0x190E || \
2555 INTEL_DEVID(dev) == 0x1915 || \
2556 INTEL_DEVID(dev) == 0x191E)
2557 #define IS_KBL_ULT(dev) (INTEL_DEVID(dev) == 0x5906 || \
2558 INTEL_DEVID(dev) == 0x5913 || \
2559 INTEL_DEVID(dev) == 0x5916 || \
2560 INTEL_DEVID(dev) == 0x5921 || \
2561 INTEL_DEVID(dev) == 0x5926)
2562 #define IS_KBL_ULX(dev) (INTEL_DEVID(dev) == 0x590E || \
2563 INTEL_DEVID(dev) == 0x5915 || \
2564 INTEL_DEVID(dev) == 0x591E)
2565 #define IS_SKL_GT3(dev) (IS_SKYLAKE(dev) && \
2566 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2567 #define IS_SKL_GT4(dev) (IS_SKYLAKE(dev) && \
2568 (INTEL_DEVID(dev) & 0x00F0) == 0x0030)
2570 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
2572 #define SKL_REVID_A0 0x0
2573 #define SKL_REVID_B0 0x1
2574 #define SKL_REVID_C0 0x2
2575 #define SKL_REVID_D0 0x3
2576 #define SKL_REVID_E0 0x4
2577 #define SKL_REVID_F0 0x5
2579 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
2581 #define BXT_REVID_A0 0x0
2582 #define BXT_REVID_A1 0x1
2583 #define BXT_REVID_B0 0x3
2584 #define BXT_REVID_C0 0x9
2586 #define IS_BXT_REVID(p, since, until) (IS_BROXTON(p) && IS_REVID(p, since, until))
2589 * The genX designation typically refers to the render engine, so render
2590 * capability related checks should use IS_GEN, while display and other checks
2591 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2594 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
2595 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
2596 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
2597 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
2598 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
2599 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
2600 #define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8)
2601 #define IS_GEN9(dev) (INTEL_INFO(dev)->gen == 9)
2603 #define RENDER_RING (1<<RCS)
2604 #define BSD_RING (1<<VCS)
2605 #define BLT_RING (1<<BCS)
2606 #define VEBOX_RING (1<<VECS)
2607 #define BSD2_RING (1<<VCS2)
2608 #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING)
2609 #define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING)
2610 #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING)
2611 #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
2612 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
2613 #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
2614 __I915__(dev)->ellc_size)
2615 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
2617 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
2618 #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8)
2619 #define USES_PPGTT(dev) (i915.enable_ppgtt)
2620 #define USES_FULL_PPGTT(dev) (i915.enable_ppgtt >= 2)
2621 #define USES_FULL_48BIT_PPGTT(dev) (i915.enable_ppgtt == 3)
2623 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
2624 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
2626 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2627 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
2629 /* WaRsDisableCoarsePowerGating:skl,bxt */
2630 #define NEEDS_WaRsDisableCoarsePowerGating(dev) (IS_BXT_REVID(dev, 0, BXT_REVID_A1) || \
2631 ((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) && \
2632 IS_SKL_REVID(dev, 0, SKL_REVID_F0)))
2634 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2635 * even when in MSI mode. This results in spurious interrupt warnings if the
2636 * legacy irq no. is shared with another device. The kernel then disables that
2637 * interrupt source and so prevents the other device from working properly.
2639 #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2640 #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2642 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2643 * rows, which changed the alignment requirements and fence programming.
2645 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
2647 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
2648 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
2650 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
2651 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
2652 #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
2654 #define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev))
2656 #define HAS_DP_MST(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2657 INTEL_INFO(dev)->gen >= 9)
2659 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
2660 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
2661 #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2662 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \
2663 IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
2664 #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \
2665 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \
2666 IS_CHERRYVIEW(dev) || IS_SKYLAKE(dev) || \
2668 #define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6)
2669 #define HAS_RC6p(dev) (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
2671 #define HAS_CSR(dev) (IS_GEN9(dev))
2673 #define HAS_GUC_UCODE(dev) (IS_GEN9(dev) && !IS_KABYLAKE(dev))
2674 #define HAS_GUC_SCHED(dev) (IS_GEN9(dev) && !IS_KABYLAKE(dev))
2676 #define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \
2677 INTEL_INFO(dev)->gen >= 8)
2679 #define HAS_CORE_RING_FREQ(dev) (INTEL_INFO(dev)->gen >= 6 && \
2680 !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && \
2683 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
2684 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2685 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2686 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2687 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2688 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2689 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2690 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2691 #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
2692 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
2694 #define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
2695 #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
2696 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
2697 #define HAS_PCH_LPT_LP(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
2698 #define HAS_PCH_LPT_H(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
2699 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
2700 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
2701 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
2702 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
2704 #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || \
2705 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
2707 /* DPF == dynamic parity feature */
2708 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
2709 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
2711 #define GT_FREQUENCY_MULTIPLIER 50
2712 #define GEN9_FREQ_SCALER 3
2714 #include "i915_trace.h"
2716 extern const struct drm_ioctl_desc i915_ioctls
[];
2717 extern int i915_max_ioctl
;
2719 extern int i915_suspend_switcheroo(struct drm_device
*dev
, pm_message_t state
);
2720 extern int i915_resume_switcheroo(struct drm_device
*dev
);
2723 extern int i915_driver_load(struct drm_device
*, unsigned long flags
);
2724 extern int i915_driver_unload(struct drm_device
*);
2725 extern int i915_driver_open(struct drm_device
*dev
, struct drm_file
*file
);
2726 extern void i915_driver_lastclose(struct drm_device
* dev
);
2727 extern void i915_driver_preclose(struct drm_device
*dev
,
2728 struct drm_file
*file
);
2729 extern void i915_driver_postclose(struct drm_device
*dev
,
2730 struct drm_file
*file
);
2731 #ifdef CONFIG_COMPAT
2732 extern long i915_compat_ioctl(struct file
*filp
, unsigned int cmd
,
2735 extern int intel_gpu_reset(struct drm_device
*dev
);
2736 extern bool intel_has_gpu_reset(struct drm_device
*dev
);
2737 extern int i915_reset(struct drm_device
*dev
);
2738 extern unsigned long i915_chipset_val(struct drm_i915_private
*dev_priv
);
2739 extern unsigned long i915_mch_val(struct drm_i915_private
*dev_priv
);
2740 extern unsigned long i915_gfx_val(struct drm_i915_private
*dev_priv
);
2741 extern void i915_update_gfx_val(struct drm_i915_private
*dev_priv
);
2742 int vlv_force_gfx_clock(struct drm_i915_private
*dev_priv
, bool on
);
2744 /* intel_hotplug.c */
2745 void intel_hpd_irq_handler(struct drm_device
*dev
, u32 pin_mask
, u32 long_mask
);
2746 void intel_hpd_init(struct drm_i915_private
*dev_priv
);
2747 void intel_hpd_init_work(struct drm_i915_private
*dev_priv
);
2748 void intel_hpd_cancel_work(struct drm_i915_private
*dev_priv
);
2749 bool intel_hpd_pin_to_port(enum hpd_pin pin
, enum port
*port
);
2752 void i915_queue_hangcheck(struct drm_device
*dev
);
2754 void i915_handle_error(struct drm_device
*dev
, bool wedged
,
2755 const char *fmt
, ...);
2757 extern void intel_irq_init(struct drm_i915_private
*dev_priv
);
2758 int intel_irq_install(struct drm_i915_private
*dev_priv
);
2759 void intel_irq_uninstall(struct drm_i915_private
*dev_priv
);
2761 extern void intel_uncore_sanitize(struct drm_device
*dev
);
2762 extern void intel_uncore_early_sanitize(struct drm_device
*dev
,
2763 bool restore_forcewake
);
2764 extern void intel_uncore_init(struct drm_device
*dev
);
2765 extern bool intel_uncore_unclaimed_mmio(struct drm_i915_private
*dev_priv
);
2766 extern bool intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private
*dev_priv
);
2767 extern void intel_uncore_fini(struct drm_device
*dev
);
2768 extern void intel_uncore_forcewake_reset(struct drm_device
*dev
, bool restore
);
2769 const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id
);
2770 void intel_uncore_forcewake_get(struct drm_i915_private
*dev_priv
,
2771 enum forcewake_domains domains
);
2772 void intel_uncore_forcewake_put(struct drm_i915_private
*dev_priv
,
2773 enum forcewake_domains domains
);
2774 /* Like above but the caller must manage the uncore.lock itself.
2775 * Must be used with I915_READ_FW and friends.
2777 void intel_uncore_forcewake_get__locked(struct drm_i915_private
*dev_priv
,
2778 enum forcewake_domains domains
);
2779 void intel_uncore_forcewake_put__locked(struct drm_i915_private
*dev_priv
,
2780 enum forcewake_domains domains
);
2781 void assert_forcewakes_inactive(struct drm_i915_private
*dev_priv
);
2782 static inline bool intel_vgpu_active(struct drm_device
*dev
)
2784 return to_i915(dev
)->vgpu
.active
;
2788 i915_enable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
2792 i915_disable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
2795 void valleyview_enable_display_irqs(struct drm_i915_private
*dev_priv
);
2796 void valleyview_disable_display_irqs(struct drm_i915_private
*dev_priv
);
2797 void i915_hotplug_interrupt_update(struct drm_i915_private
*dev_priv
,
2800 void ilk_update_display_irq(struct drm_i915_private
*dev_priv
,
2801 uint32_t interrupt_mask
,
2802 uint32_t enabled_irq_mask
);
2804 ilk_enable_display_irq(struct drm_i915_private
*dev_priv
, uint32_t bits
)
2806 ilk_update_display_irq(dev_priv
, bits
, bits
);
2809 ilk_disable_display_irq(struct drm_i915_private
*dev_priv
, uint32_t bits
)
2811 ilk_update_display_irq(dev_priv
, bits
, 0);
2813 void bdw_update_pipe_irq(struct drm_i915_private
*dev_priv
,
2815 uint32_t interrupt_mask
,
2816 uint32_t enabled_irq_mask
);
2817 static inline void bdw_enable_pipe_irq(struct drm_i915_private
*dev_priv
,
2818 enum pipe pipe
, uint32_t bits
)
2820 bdw_update_pipe_irq(dev_priv
, pipe
, bits
, bits
);
2822 static inline void bdw_disable_pipe_irq(struct drm_i915_private
*dev_priv
,
2823 enum pipe pipe
, uint32_t bits
)
2825 bdw_update_pipe_irq(dev_priv
, pipe
, bits
, 0);
2827 void ibx_display_interrupt_update(struct drm_i915_private
*dev_priv
,
2828 uint32_t interrupt_mask
,
2829 uint32_t enabled_irq_mask
);
2831 ibx_enable_display_interrupt(struct drm_i915_private
*dev_priv
, uint32_t bits
)
2833 ibx_display_interrupt_update(dev_priv
, bits
, bits
);
2836 ibx_disable_display_interrupt(struct drm_i915_private
*dev_priv
, uint32_t bits
)
2838 ibx_display_interrupt_update(dev_priv
, bits
, 0);
2843 int i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
2844 struct drm_file
*file_priv
);
2845 int i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
2846 struct drm_file
*file_priv
);
2847 int i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
2848 struct drm_file
*file_priv
);
2849 int i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
2850 struct drm_file
*file_priv
);
2851 int i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
2852 struct drm_file
*file_priv
);
2853 int i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
2854 struct drm_file
*file_priv
);
2855 int i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
2856 struct drm_file
*file_priv
);
2857 void i915_gem_execbuffer_move_to_active(struct list_head
*vmas
,
2858 struct drm_i915_gem_request
*req
);
2859 void i915_gem_execbuffer_retire_commands(struct i915_execbuffer_params
*params
);
2860 int i915_gem_ringbuffer_submission(struct i915_execbuffer_params
*params
,
2861 struct drm_i915_gem_execbuffer2
*args
,
2862 struct list_head
*vmas
);
2863 int i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
2864 struct drm_file
*file_priv
);
2865 int i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
2866 struct drm_file
*file_priv
);
2867 int i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
2868 struct drm_file
*file_priv
);
2869 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
2870 struct drm_file
*file
);
2871 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
2872 struct drm_file
*file
);
2873 int i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
2874 struct drm_file
*file_priv
);
2875 int i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
2876 struct drm_file
*file_priv
);
2877 int i915_gem_set_tiling(struct drm_device
*dev
, void *data
,
2878 struct drm_file
*file_priv
);
2879 int i915_gem_get_tiling(struct drm_device
*dev
, void *data
,
2880 struct drm_file
*file_priv
);
2881 int i915_gem_init_userptr(struct drm_device
*dev
);
2882 int i915_gem_userptr_ioctl(struct drm_device
*dev
, void *data
,
2883 struct drm_file
*file
);
2884 int i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
2885 struct drm_file
*file_priv
);
2886 int i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
,
2887 struct drm_file
*file_priv
);
2888 void i915_gem_load_init(struct drm_device
*dev
);
2889 void i915_gem_load_cleanup(struct drm_device
*dev
);
2890 void *i915_gem_object_alloc(struct drm_device
*dev
);
2891 void i915_gem_object_free(struct drm_i915_gem_object
*obj
);
2892 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
2893 const struct drm_i915_gem_object_ops
*ops
);
2894 struct drm_i915_gem_object
*i915_gem_alloc_object(struct drm_device
*dev
,
2896 struct drm_i915_gem_object
*i915_gem_object_create_from_data(
2897 struct drm_device
*dev
, const void *data
, size_t size
);
2898 void i915_gem_free_object(struct drm_gem_object
*obj
);
2899 void i915_gem_vma_destroy(struct i915_vma
*vma
);
2901 /* Flags used by pin/bind&friends. */
2902 #define PIN_MAPPABLE (1<<0)
2903 #define PIN_NONBLOCK (1<<1)
2904 #define PIN_GLOBAL (1<<2)
2905 #define PIN_OFFSET_BIAS (1<<3)
2906 #define PIN_USER (1<<4)
2907 #define PIN_UPDATE (1<<5)
2908 #define PIN_ZONE_4G (1<<6)
2909 #define PIN_HIGH (1<<7)
2910 #define PIN_OFFSET_FIXED (1<<8)
2911 #define PIN_OFFSET_MASK (~4095)
2913 i915_gem_object_pin(struct drm_i915_gem_object
*obj
,
2914 struct i915_address_space
*vm
,
2918 i915_gem_object_ggtt_pin(struct drm_i915_gem_object
*obj
,
2919 const struct i915_ggtt_view
*view
,
2923 int i915_vma_bind(struct i915_vma
*vma
, enum i915_cache_level cache_level
,
2925 void __i915_vma_set_map_and_fenceable(struct i915_vma
*vma
);
2926 int __must_check
i915_vma_unbind(struct i915_vma
*vma
);
2928 * BEWARE: Do not use the function below unless you can _absolutely_
2929 * _guarantee_ VMA in question is _not in use_ anywhere.
2931 int __must_check
__i915_vma_unbind_no_wait(struct i915_vma
*vma
);
2932 int i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
);
2933 void i915_gem_release_all_mmaps(struct drm_i915_private
*dev_priv
);
2934 void i915_gem_release_mmap(struct drm_i915_gem_object
*obj
);
2936 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object
*obj
,
2937 int *needs_clflush
);
2939 int __must_check
i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
);
2941 static inline int __sg_page_count(struct scatterlist
*sg
)
2943 return sg
->length
>> PAGE_SHIFT
;
2947 i915_gem_object_get_dirty_page(struct drm_i915_gem_object
*obj
, int n
);
2949 static inline struct page
*
2950 i915_gem_object_get_page(struct drm_i915_gem_object
*obj
, int n
)
2952 if (WARN_ON(n
>= obj
->base
.size
>> PAGE_SHIFT
))
2955 if (n
< obj
->get_page
.last
) {
2956 obj
->get_page
.sg
= obj
->pages
->sgl
;
2957 obj
->get_page
.last
= 0;
2960 while (obj
->get_page
.last
+ __sg_page_count(obj
->get_page
.sg
) <= n
) {
2961 obj
->get_page
.last
+= __sg_page_count(obj
->get_page
.sg
++);
2962 if (unlikely(sg_is_chain(obj
->get_page
.sg
)))
2963 obj
->get_page
.sg
= sg_chain_ptr(obj
->get_page
.sg
);
2966 return nth_page(sg_page(obj
->get_page
.sg
), n
- obj
->get_page
.last
);
2969 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object
*obj
)
2971 BUG_ON(obj
->pages
== NULL
);
2972 obj
->pages_pin_count
++;
2974 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object
*obj
)
2976 BUG_ON(obj
->pages_pin_count
== 0);
2977 obj
->pages_pin_count
--;
2980 int __must_check
i915_mutex_lock_interruptible(struct drm_device
*dev
);
2981 int i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
2982 struct intel_engine_cs
*to
,
2983 struct drm_i915_gem_request
**to_req
);
2984 void i915_vma_move_to_active(struct i915_vma
*vma
,
2985 struct drm_i915_gem_request
*req
);
2986 int i915_gem_dumb_create(struct drm_file
*file_priv
,
2987 struct drm_device
*dev
,
2988 struct drm_mode_create_dumb
*args
);
2989 int i915_gem_mmap_gtt(struct drm_file
*file_priv
, struct drm_device
*dev
,
2990 uint32_t handle
, uint64_t *offset
);
2992 * Returns true if seq1 is later than seq2.
2995 i915_seqno_passed(uint32_t seq1
, uint32_t seq2
)
2997 return (int32_t)(seq1
- seq2
) >= 0;
3000 static inline bool i915_gem_request_started(struct drm_i915_gem_request
*req
,
3001 bool lazy_coherency
)
3003 u32 seqno
= req
->ring
->get_seqno(req
->ring
, lazy_coherency
);
3004 return i915_seqno_passed(seqno
, req
->previous_seqno
);
3007 static inline bool i915_gem_request_completed(struct drm_i915_gem_request
*req
,
3008 bool lazy_coherency
)
3010 u32 seqno
= req
->ring
->get_seqno(req
->ring
, lazy_coherency
);
3011 return i915_seqno_passed(seqno
, req
->seqno
);
3014 int __must_check
i915_gem_get_seqno(struct drm_device
*dev
, u32
*seqno
);
3015 int __must_check
i915_gem_set_seqno(struct drm_device
*dev
, u32 seqno
);
3017 struct drm_i915_gem_request
*
3018 i915_gem_find_active_request(struct intel_engine_cs
*ring
);
3020 bool i915_gem_retire_requests(struct drm_device
*dev
);
3021 void i915_gem_retire_requests_ring(struct intel_engine_cs
*ring
);
3022 int __must_check
i915_gem_check_wedge(struct i915_gpu_error
*error
,
3023 bool interruptible
);
3025 static inline bool i915_reset_in_progress(struct i915_gpu_error
*error
)
3027 return unlikely(atomic_read(&error
->reset_counter
)
3028 & (I915_RESET_IN_PROGRESS_FLAG
| I915_WEDGED
));
3031 static inline bool i915_terminally_wedged(struct i915_gpu_error
*error
)
3033 return atomic_read(&error
->reset_counter
) & I915_WEDGED
;
3036 static inline u32
i915_reset_count(struct i915_gpu_error
*error
)
3038 return ((atomic_read(&error
->reset_counter
) & ~I915_WEDGED
) + 1) / 2;
3041 static inline bool i915_stop_ring_allow_ban(struct drm_i915_private
*dev_priv
)
3043 return dev_priv
->gpu_error
.stop_rings
== 0 ||
3044 dev_priv
->gpu_error
.stop_rings
& I915_STOP_RING_ALLOW_BAN
;
3047 static inline bool i915_stop_ring_allow_warn(struct drm_i915_private
*dev_priv
)
3049 return dev_priv
->gpu_error
.stop_rings
== 0 ||
3050 dev_priv
->gpu_error
.stop_rings
& I915_STOP_RING_ALLOW_WARN
;
3053 void i915_gem_reset(struct drm_device
*dev
);
3054 bool i915_gem_clflush_object(struct drm_i915_gem_object
*obj
, bool force
);
3055 int __must_check
i915_gem_init(struct drm_device
*dev
);
3056 int i915_gem_init_rings(struct drm_device
*dev
);
3057 int __must_check
i915_gem_init_hw(struct drm_device
*dev
);
3058 int i915_gem_l3_remap(struct drm_i915_gem_request
*req
, int slice
);
3059 void i915_gem_init_swizzling(struct drm_device
*dev
);
3060 void i915_gem_cleanup_ringbuffer(struct drm_device
*dev
);
3061 int __must_check
i915_gpu_idle(struct drm_device
*dev
);
3062 int __must_check
i915_gem_suspend(struct drm_device
*dev
);
3063 void __i915_add_request(struct drm_i915_gem_request
*req
,
3064 struct drm_i915_gem_object
*batch_obj
,
3066 #define i915_add_request(req) \
3067 __i915_add_request(req, NULL, true)
3068 #define i915_add_request_no_flush(req) \
3069 __i915_add_request(req, NULL, false)
3070 int __i915_wait_request(struct drm_i915_gem_request
*req
,
3071 unsigned reset_counter
,
3074 struct intel_rps_client
*rps
);
3075 int __must_check
i915_wait_request(struct drm_i915_gem_request
*req
);
3076 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
);
3078 i915_gem_object_wait_rendering(struct drm_i915_gem_object
*obj
,
3081 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
,
3084 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
);
3086 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
3088 const struct i915_ggtt_view
*view
);
3089 void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object
*obj
,
3090 const struct i915_ggtt_view
*view
);
3091 int i915_gem_object_attach_phys(struct drm_i915_gem_object
*obj
,
3093 int i915_gem_open(struct drm_device
*dev
, struct drm_file
*file
);
3094 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
);
3097 i915_gem_get_gtt_size(struct drm_device
*dev
, uint32_t size
, int tiling_mode
);
3099 i915_gem_get_gtt_alignment(struct drm_device
*dev
, uint32_t size
,
3100 int tiling_mode
, bool fenced
);
3102 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
3103 enum i915_cache_level cache_level
);
3105 struct drm_gem_object
*i915_gem_prime_import(struct drm_device
*dev
,
3106 struct dma_buf
*dma_buf
);
3108 struct dma_buf
*i915_gem_prime_export(struct drm_device
*dev
,
3109 struct drm_gem_object
*gem_obj
, int flags
);
3111 u64
i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object
*o
,
3112 const struct i915_ggtt_view
*view
);
3113 u64
i915_gem_obj_offset(struct drm_i915_gem_object
*o
,
3114 struct i915_address_space
*vm
);
3116 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object
*o
)
3118 return i915_gem_obj_ggtt_offset_view(o
, &i915_ggtt_view_normal
);
3121 bool i915_gem_obj_bound_any(struct drm_i915_gem_object
*o
);
3122 bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object
*o
,
3123 const struct i915_ggtt_view
*view
);
3124 bool i915_gem_obj_bound(struct drm_i915_gem_object
*o
,
3125 struct i915_address_space
*vm
);
3127 unsigned long i915_gem_obj_size(struct drm_i915_gem_object
*o
,
3128 struct i915_address_space
*vm
);
3130 i915_gem_obj_to_vma(struct drm_i915_gem_object
*obj
,
3131 struct i915_address_space
*vm
);
3133 i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object
*obj
,
3134 const struct i915_ggtt_view
*view
);
3137 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object
*obj
,
3138 struct i915_address_space
*vm
);
3140 i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object
*obj
,
3141 const struct i915_ggtt_view
*view
);
3143 static inline struct i915_vma
*
3144 i915_gem_obj_to_ggtt(struct drm_i915_gem_object
*obj
)
3146 return i915_gem_obj_to_ggtt_view(obj
, &i915_ggtt_view_normal
);
3148 bool i915_gem_obj_is_pinned(struct drm_i915_gem_object
*obj
);
3150 /* Some GGTT VM helpers */
3151 #define i915_obj_to_ggtt(obj) \
3152 (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
3153 static inline bool i915_is_ggtt(struct i915_address_space
*vm
)
3155 struct i915_address_space
*ggtt
=
3156 &((struct drm_i915_private
*)(vm
)->dev
->dev_private
)->gtt
.base
;
3160 static inline struct i915_hw_ppgtt
*
3161 i915_vm_to_ppgtt(struct i915_address_space
*vm
)
3163 WARN_ON(i915_is_ggtt(vm
));
3165 return container_of(vm
, struct i915_hw_ppgtt
, base
);
3169 static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object
*obj
)
3171 return i915_gem_obj_ggtt_bound_view(obj
, &i915_ggtt_view_normal
);
3174 static inline unsigned long
3175 i915_gem_obj_ggtt_size(struct drm_i915_gem_object
*obj
)
3177 return i915_gem_obj_size(obj
, i915_obj_to_ggtt(obj
));
3180 static inline int __must_check
3181 i915_gem_obj_ggtt_pin(struct drm_i915_gem_object
*obj
,
3185 return i915_gem_object_pin(obj
, i915_obj_to_ggtt(obj
),
3186 alignment
, flags
| PIN_GLOBAL
);
3190 i915_gem_object_ggtt_unbind(struct drm_i915_gem_object
*obj
)
3192 return i915_vma_unbind(i915_gem_obj_to_ggtt(obj
));
3195 void i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object
*obj
,
3196 const struct i915_ggtt_view
*view
);
3198 i915_gem_object_ggtt_unpin(struct drm_i915_gem_object
*obj
)
3200 i915_gem_object_ggtt_unpin_view(obj
, &i915_ggtt_view_normal
);
3203 /* i915_gem_fence.c */
3204 int __must_check
i915_gem_object_get_fence(struct drm_i915_gem_object
*obj
);
3205 int __must_check
i915_gem_object_put_fence(struct drm_i915_gem_object
*obj
);
3207 bool i915_gem_object_pin_fence(struct drm_i915_gem_object
*obj
);
3208 void i915_gem_object_unpin_fence(struct drm_i915_gem_object
*obj
);
3210 void i915_gem_restore_fences(struct drm_device
*dev
);
3212 void i915_gem_detect_bit_6_swizzle(struct drm_device
*dev
);
3213 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
3214 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
3216 /* i915_gem_context.c */
3217 int __must_check
i915_gem_context_init(struct drm_device
*dev
);
3218 void i915_gem_context_fini(struct drm_device
*dev
);
3219 void i915_gem_context_reset(struct drm_device
*dev
);
3220 int i915_gem_context_open(struct drm_device
*dev
, struct drm_file
*file
);
3221 int i915_gem_context_enable(struct drm_i915_gem_request
*req
);
3222 void i915_gem_context_close(struct drm_device
*dev
, struct drm_file
*file
);
3223 int i915_switch_context(struct drm_i915_gem_request
*req
);
3224 struct intel_context
*
3225 i915_gem_context_get(struct drm_i915_file_private
*file_priv
, u32 id
);
3226 void i915_gem_context_free(struct kref
*ctx_ref
);
3227 struct drm_i915_gem_object
*
3228 i915_gem_alloc_context_obj(struct drm_device
*dev
, size_t size
);
3229 static inline void i915_gem_context_reference(struct intel_context
*ctx
)
3231 kref_get(&ctx
->ref
);
3234 static inline void i915_gem_context_unreference(struct intel_context
*ctx
)
3236 kref_put(&ctx
->ref
, i915_gem_context_free
);
3239 static inline bool i915_gem_context_is_default(const struct intel_context
*c
)
3241 return c
->user_handle
== DEFAULT_CONTEXT_HANDLE
;
3244 int i915_gem_context_create_ioctl(struct drm_device
*dev
, void *data
,
3245 struct drm_file
*file
);
3246 int i915_gem_context_destroy_ioctl(struct drm_device
*dev
, void *data
,
3247 struct drm_file
*file
);
3248 int i915_gem_context_getparam_ioctl(struct drm_device
*dev
, void *data
,
3249 struct drm_file
*file_priv
);
3250 int i915_gem_context_setparam_ioctl(struct drm_device
*dev
, void *data
,
3251 struct drm_file
*file_priv
);
3253 /* i915_gem_evict.c */
3254 int __must_check
i915_gem_evict_something(struct drm_device
*dev
,
3255 struct i915_address_space
*vm
,
3258 unsigned cache_level
,
3259 unsigned long start
,
3262 int __must_check
i915_gem_evict_for_vma(struct i915_vma
*target
);
3263 int i915_gem_evict_vm(struct i915_address_space
*vm
, bool do_idle
);
3265 /* belongs in i915_gem_gtt.h */
3266 static inline void i915_gem_chipset_flush(struct drm_device
*dev
)
3268 if (INTEL_INFO(dev
)->gen
< 6)
3269 intel_gtt_chipset_flush();
3272 /* i915_gem_stolen.c */
3273 int i915_gem_stolen_insert_node(struct drm_i915_private
*dev_priv
,
3274 struct drm_mm_node
*node
, u64 size
,
3275 unsigned alignment
);
3276 int i915_gem_stolen_insert_node_in_range(struct drm_i915_private
*dev_priv
,
3277 struct drm_mm_node
*node
, u64 size
,
3278 unsigned alignment
, u64 start
,
3280 void i915_gem_stolen_remove_node(struct drm_i915_private
*dev_priv
,
3281 struct drm_mm_node
*node
);
3282 int i915_gem_init_stolen(struct drm_device
*dev
);
3283 void i915_gem_cleanup_stolen(struct drm_device
*dev
);
3284 struct drm_i915_gem_object
*
3285 i915_gem_object_create_stolen(struct drm_device
*dev
, u32 size
);
3286 struct drm_i915_gem_object
*
3287 i915_gem_object_create_stolen_for_preallocated(struct drm_device
*dev
,
3292 /* i915_gem_shrinker.c */
3293 unsigned long i915_gem_shrink(struct drm_i915_private
*dev_priv
,
3294 unsigned long target
,
3296 #define I915_SHRINK_PURGEABLE 0x1
3297 #define I915_SHRINK_UNBOUND 0x2
3298 #define I915_SHRINK_BOUND 0x4
3299 #define I915_SHRINK_ACTIVE 0x8
3300 unsigned long i915_gem_shrink_all(struct drm_i915_private
*dev_priv
);
3301 void i915_gem_shrinker_init(struct drm_i915_private
*dev_priv
);
3302 void i915_gem_shrinker_cleanup(struct drm_i915_private
*dev_priv
);
3305 /* i915_gem_tiling.c */
3306 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object
*obj
)
3308 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
3310 return dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_9_10_17
&&
3311 obj
->tiling_mode
!= I915_TILING_NONE
;
3314 /* i915_gem_debug.c */
3316 int i915_verify_lists(struct drm_device
*dev
);
3318 #define i915_verify_lists(dev) 0
3321 /* i915_debugfs.c */
3322 int i915_debugfs_init(struct drm_minor
*minor
);
3323 void i915_debugfs_cleanup(struct drm_minor
*minor
);
3324 #ifdef CONFIG_DEBUG_FS
3325 int i915_debugfs_connector_add(struct drm_connector
*connector
);
3326 void intel_display_crc_init(struct drm_device
*dev
);
3328 static inline int i915_debugfs_connector_add(struct drm_connector
*connector
)
3330 static inline void intel_display_crc_init(struct drm_device
*dev
) {}
3333 /* i915_gpu_error.c */
3335 void i915_error_printf(struct drm_i915_error_state_buf
*e
, const char *f
, ...);
3336 int i915_error_state_to_str(struct drm_i915_error_state_buf
*estr
,
3337 const struct i915_error_state_file_priv
*error
);
3338 int i915_error_state_buf_init(struct drm_i915_error_state_buf
*eb
,
3339 struct drm_i915_private
*i915
,
3340 size_t count
, loff_t pos
);
3341 static inline void i915_error_state_buf_release(
3342 struct drm_i915_error_state_buf
*eb
)
3346 void i915_capture_error_state(struct drm_device
*dev
, bool wedge
,
3347 const char *error_msg
);
3348 void i915_error_state_get(struct drm_device
*dev
,
3349 struct i915_error_state_file_priv
*error_priv
);
3350 void i915_error_state_put(struct i915_error_state_file_priv
*error_priv
);
3351 void i915_destroy_error_state(struct drm_device
*dev
);
3353 void i915_get_extra_instdone(struct drm_device
*dev
, uint32_t *instdone
);
3354 const char *i915_cache_level_str(struct drm_i915_private
*i915
, int type
);
3356 /* i915_cmd_parser.c */
3357 int i915_cmd_parser_get_version(void);
3358 int i915_cmd_parser_init_ring(struct intel_engine_cs
*ring
);
3359 void i915_cmd_parser_fini_ring(struct intel_engine_cs
*ring
);
3360 bool i915_needs_cmd_parser(struct intel_engine_cs
*ring
);
3361 int i915_parse_cmds(struct intel_engine_cs
*ring
,
3362 struct drm_i915_gem_object
*batch_obj
,
3363 struct drm_i915_gem_object
*shadow_batch_obj
,
3364 u32 batch_start_offset
,
3368 /* i915_suspend.c */
3369 extern int i915_save_state(struct drm_device
*dev
);
3370 extern int i915_restore_state(struct drm_device
*dev
);
3373 void i915_setup_sysfs(struct drm_device
*dev_priv
);
3374 void i915_teardown_sysfs(struct drm_device
*dev_priv
);
3377 extern int intel_setup_gmbus(struct drm_device
*dev
);
3378 extern void intel_teardown_gmbus(struct drm_device
*dev
);
3379 extern bool intel_gmbus_is_valid_pin(struct drm_i915_private
*dev_priv
,
3382 extern struct i2c_adapter
*
3383 intel_gmbus_get_adapter(struct drm_i915_private
*dev_priv
, unsigned int pin
);
3384 extern void intel_gmbus_set_speed(struct i2c_adapter
*adapter
, int speed
);
3385 extern void intel_gmbus_force_bit(struct i2c_adapter
*adapter
, bool force_bit
);
3386 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter
*adapter
)
3388 return container_of(adapter
, struct intel_gmbus
, adapter
)->force_bit
;
3390 extern void intel_i2c_reset(struct drm_device
*dev
);
3393 int intel_bios_init(struct drm_i915_private
*dev_priv
);
3394 bool intel_bios_is_valid_vbt(const void *buf
, size_t size
);
3396 /* intel_opregion.c */
3398 extern int intel_opregion_setup(struct drm_device
*dev
);
3399 extern void intel_opregion_init(struct drm_device
*dev
);
3400 extern void intel_opregion_fini(struct drm_device
*dev
);
3401 extern void intel_opregion_asle_intr(struct drm_device
*dev
);
3402 extern int intel_opregion_notify_encoder(struct intel_encoder
*intel_encoder
,
3404 extern int intel_opregion_notify_adapter(struct drm_device
*dev
,
3407 static inline int intel_opregion_setup(struct drm_device
*dev
) { return 0; }
3408 static inline void intel_opregion_init(struct drm_device
*dev
) { return; }
3409 static inline void intel_opregion_fini(struct drm_device
*dev
) { return; }
3410 static inline void intel_opregion_asle_intr(struct drm_device
*dev
) { return; }
3412 intel_opregion_notify_encoder(struct intel_encoder
*intel_encoder
, bool enable
)
3417 intel_opregion_notify_adapter(struct drm_device
*dev
, pci_power_t state
)
3425 extern void intel_register_dsm_handler(void);
3426 extern void intel_unregister_dsm_handler(void);
3428 static inline void intel_register_dsm_handler(void) { return; }
3429 static inline void intel_unregister_dsm_handler(void) { return; }
3430 #endif /* CONFIG_ACPI */
3433 extern void intel_modeset_init_hw(struct drm_device
*dev
);
3434 extern void intel_modeset_init(struct drm_device
*dev
);
3435 extern void intel_modeset_gem_init(struct drm_device
*dev
);
3436 extern void intel_modeset_cleanup(struct drm_device
*dev
);
3437 extern void intel_connector_unregister(struct intel_connector
*);
3438 extern int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
);
3439 extern void intel_display_resume(struct drm_device
*dev
);
3440 extern void i915_redisable_vga(struct drm_device
*dev
);
3441 extern void i915_redisable_vga_power_on(struct drm_device
*dev
);
3442 extern bool ironlake_set_drps(struct drm_device
*dev
, u8 val
);
3443 extern void intel_init_pch_refclk(struct drm_device
*dev
);
3444 extern void intel_set_rps(struct drm_device
*dev
, u8 val
);
3445 extern void intel_set_memory_cxsr(struct drm_i915_private
*dev_priv
,
3447 extern void intel_detect_pch(struct drm_device
*dev
);
3448 extern int intel_enable_rc6(const struct drm_device
*dev
);
3450 extern bool i915_semaphore_is_enabled(struct drm_device
*dev
);
3451 int i915_reg_read_ioctl(struct drm_device
*dev
, void *data
,
3452 struct drm_file
*file
);
3453 int i915_get_reset_stats_ioctl(struct drm_device
*dev
, void *data
,
3454 struct drm_file
*file
);
3457 extern struct intel_overlay_error_state
*intel_overlay_capture_error_state(struct drm_device
*dev
);
3458 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf
*e
,
3459 struct intel_overlay_error_state
*error
);
3461 extern struct intel_display_error_state
*intel_display_capture_error_state(struct drm_device
*dev
);
3462 extern void intel_display_print_error_state(struct drm_i915_error_state_buf
*e
,
3463 struct drm_device
*dev
,
3464 struct intel_display_error_state
*error
);
3466 int sandybridge_pcode_read(struct drm_i915_private
*dev_priv
, u32 mbox
, u32
*val
);
3467 int sandybridge_pcode_write(struct drm_i915_private
*dev_priv
, u32 mbox
, u32 val
);
3469 /* intel_sideband.c */
3470 u32
vlv_punit_read(struct drm_i915_private
*dev_priv
, u32 addr
);
3471 void vlv_punit_write(struct drm_i915_private
*dev_priv
, u32 addr
, u32 val
);
3472 u32
vlv_nc_read(struct drm_i915_private
*dev_priv
, u8 addr
);
3473 u32
vlv_gpio_nc_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3474 void vlv_gpio_nc_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3475 u32
vlv_cck_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3476 void vlv_cck_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3477 u32
vlv_ccu_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3478 void vlv_ccu_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3479 u32
vlv_bunit_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3480 void vlv_bunit_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3481 u32
vlv_gps_core_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3482 void vlv_gps_core_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3483 u32
vlv_dpio_read(struct drm_i915_private
*dev_priv
, enum pipe pipe
, int reg
);
3484 void vlv_dpio_write(struct drm_i915_private
*dev_priv
, enum pipe pipe
, int reg
, u32 val
);
3485 u32
intel_sbi_read(struct drm_i915_private
*dev_priv
, u16 reg
,
3486 enum intel_sbi_destination destination
);
3487 void intel_sbi_write(struct drm_i915_private
*dev_priv
, u16 reg
, u32 value
,
3488 enum intel_sbi_destination destination
);
3489 u32
vlv_flisdsi_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3490 void vlv_flisdsi_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3492 int intel_gpu_freq(struct drm_i915_private
*dev_priv
, int val
);
3493 int intel_freq_opcode(struct drm_i915_private
*dev_priv
, int val
);
3495 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3496 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3498 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3499 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3500 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3501 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
3503 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3504 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3505 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3506 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3508 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
3509 * will be implemented using 2 32-bit writes in an arbitrary order with
3510 * an arbitrary delay between them. This can cause the hardware to
3511 * act upon the intermediate value, possibly leading to corruption and
3512 * machine death. You have been warned.
3514 #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
3515 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3517 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
3518 u32 upper, lower, old_upper, loop = 0; \
3519 upper = I915_READ(upper_reg); \
3521 old_upper = upper; \
3522 lower = I915_READ(lower_reg); \
3523 upper = I915_READ(upper_reg); \
3524 } while (upper != old_upper && loop++ < 2); \
3525 (u64)upper << 32 | lower; })
3527 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3528 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
3530 #define __raw_read(x, s) \
3531 static inline uint##x##_t __raw_i915_read##x(struct drm_i915_private *dev_priv, \
3534 return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
3537 #define __raw_write(x, s) \
3538 static inline void __raw_i915_write##x(struct drm_i915_private *dev_priv, \
3539 i915_reg_t reg, uint##x##_t val) \
3541 write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
3556 /* These are untraced mmio-accessors that are only valid to be used inside
3557 * criticial sections inside IRQ handlers where forcewake is explicitly
3559 * Think twice, and think again, before using these.
3560 * Note: Should only be used between intel_uncore_forcewake_irqlock() and
3561 * intel_uncore_forcewake_irqunlock().
3563 #define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
3564 #define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
3565 #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
3567 /* "Broadcast RGB" property */
3568 #define INTEL_BROADCAST_RGB_AUTO 0
3569 #define INTEL_BROADCAST_RGB_FULL 1
3570 #define INTEL_BROADCAST_RGB_LIMITED 2
3572 static inline i915_reg_t
i915_vgacntrl_reg(struct drm_device
*dev
)
3574 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
))
3575 return VLV_VGACNTRL
;
3576 else if (INTEL_INFO(dev
)->gen
>= 5)
3577 return CPU_VGACNTRL
;
3582 static inline void __user
*to_user_ptr(u64 address
)
3584 return (void __user
*)(uintptr_t)address
;
3587 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m
)
3589 unsigned long j
= msecs_to_jiffies(m
);
3591 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);
3594 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n
)
3596 return min_t(u64
, MAX_JIFFY_OFFSET
, nsecs_to_jiffies64(n
) + 1);
3599 static inline unsigned long
3600 timespec_to_jiffies_timeout(const struct timespec
*value
)
3602 unsigned long j
= timespec_to_jiffies(value
);
3604 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);
3608 * If you need to wait X milliseconds between events A and B, but event B
3609 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
3610 * when event A happened, then just before event B you call this function and
3611 * pass the timestamp as the first argument, and X as the second argument.
3614 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies
, int to_wait_ms
)
3616 unsigned long target_jiffies
, tmp_jiffies
, remaining_jiffies
;
3619 * Don't re-read the value of "jiffies" every time since it may change
3620 * behind our back and break the math.
3622 tmp_jiffies
= jiffies
;
3623 target_jiffies
= timestamp_jiffies
+
3624 msecs_to_jiffies_timeout(to_wait_ms
);
3626 if (time_after(target_jiffies
, tmp_jiffies
)) {
3627 remaining_jiffies
= target_jiffies
- tmp_jiffies
;
3628 while (remaining_jiffies
)
3630 schedule_timeout_uninterruptible(remaining_jiffies
);
3634 static inline void i915_trace_irq_get(struct intel_engine_cs
*ring
,
3635 struct drm_i915_gem_request
*req
)
3637 if (ring
->trace_irq_req
== NULL
&& ring
->irq_get(ring
))
3638 i915_gem_request_assign(&ring
->trace_irq_req
, req
);