drivers/gpu/drm/i915/i915_drv.h

   1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #ifndef _I915_DRV_H_
  31 #define _I915_DRV_H_
  32
  33 #include "i915_reg.h"
  34 #include "intel_bios.h"
  35 #include "intel_ringbuffer.h"
  36 #include <linux/io-mapping.h>
  37 #include <linux/i2c.h>
  38 #include <linux/i2c-algo-bit.h>
  39 #include <drm/intel-gtt.h>
  40 #include <linux/backlight.h>
  41 #include <linux/intel-iommu.h>
  42 #include <linux/kref.h>
  43
  44 /* General customization:
  45  */
  46
  47 #define DRIVER_AUTHOR           "Tungsten Graphics, Inc."
  48
  49 #define DRIVER_NAME             "i915"
  50 #define DRIVER_DESC             "Intel Graphics"
  51 #define DRIVER_DATE             "20080730"
  52
  53 enum pipe {
  54         PIPE_A = 0,
  55         PIPE_B,
  56         PIPE_C,
  57         I915_MAX_PIPES
  58 };
  59 #define pipe_name(p) ((p) + 'A')
  60
  61 enum plane {
  62         PLANE_A = 0,
  63         PLANE_B,
  64         PLANE_C,
  65 };
  66 #define plane_name(p) ((p) + 'A')
  67
  68 enum port {
  69         PORT_A = 0,
  70         PORT_B,
  71         PORT_C,
  72         PORT_D,
  73         PORT_E,
  74         I915_MAX_PORTS
  75 };
  76 #define port_name(p) ((p) + 'A')
  77
  78 #define I915_GEM_GPU_DOMAINS    (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
  79
  80 #define for_each_pipe(p) for ((p) = 0; (p) < dev_priv->num_pipe; (p)++)
  81
  82 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
  83         list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
  84                 if ((intel_encoder)->base.crtc == (__crtc))
  85
  86 struct intel_pch_pll {
  87         int refcount; /* count of number of CRTCs sharing this PLL */
  88         int active; /* count of number of active CRTCs (i.e. DPMS on) */
  89         bool on; /* is the PLL actually active? Disabled during modeset */
  90         int pll_reg;
  91         int fp0_reg;
  92         int fp1_reg;
  93 };
  94 #define I915_NUM_PLLS 2
  95
  96 struct intel_ddi_plls {
  97         int spll_refcount;
  98         int wrpll1_refcount;
  99         int wrpll2_refcount;
 100 };
 101
 102 /* Interface history:
 103  *
 104  * 1.1: Original.
 105  * 1.2: Add Power Management
 106  * 1.3: Add vblank support
 107  * 1.4: Fix cmdbuffer path, add heap destroy
 108  * 1.5: Add vblank pipe configuration
 109  * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
 110  *      - Support vertical blank on secondary display pipe
 111  */
 112 #define DRIVER_MAJOR            1
 113 #define DRIVER_MINOR            6
 114 #define DRIVER_PATCHLEVEL       0
 115
 116 #define WATCH_COHERENCY 0
 117 #define WATCH_LISTS     0
 118 #define WATCH_GTT       0
 119
 120 #define I915_GEM_PHYS_CURSOR_0 1
 121 #define I915_GEM_PHYS_CURSOR_1 2
 122 #define I915_GEM_PHYS_OVERLAY_REGS 3
 123 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
 124
 125 struct drm_i915_gem_phys_object {
 126         int id;
 127         struct page **page_list;
 128         drm_dma_handle_t *handle;
 129         struct drm_i915_gem_object *cur_obj;
 130 };
 131
 132 struct opregion_header;
 133 struct opregion_acpi;
 134 struct opregion_swsci;
 135 struct opregion_asle;
 136 struct drm_i915_private;
 137
 138 struct intel_opregion {
 139         struct opregion_header __iomem *header;
 140         struct opregion_acpi __iomem *acpi;
 141         struct opregion_swsci __iomem *swsci;
 142         struct opregion_asle __iomem *asle;
 143         void __iomem *vbt;
 144         u32 __iomem *lid_state;
 145 };
 146 #define OPREGION_SIZE            (8*1024)
 147
 148 struct intel_overlay;
 149 struct intel_overlay_error_state;
 150
 151 struct drm_i915_master_private {
 152         drm_local_map_t *sarea;
 153         struct _drm_i915_sarea *sarea_priv;
 154 };
 155 #define I915_FENCE_REG_NONE -1
 156 #define I915_MAX_NUM_FENCES 16
 157 /* 16 fences + sign bit for FENCE_REG_NONE */
 158 #define I915_MAX_NUM_FENCE_BITS 5
 159
 160 struct drm_i915_fence_reg {
 161         struct list_head lru_list;
 162         struct drm_i915_gem_object *obj;
 163         int pin_count;
 164 };
 165
 166 struct sdvo_device_mapping {
 167         u8 initialized;
 168         u8 dvo_port;
 169         u8 slave_addr;
 170         u8 dvo_wiring;
 171         u8 i2c_pin;
 172         u8 ddc_pin;
 173 };
 174
 175 struct intel_display_error_state;
 176
 177 struct drm_i915_error_state {
 178         struct kref ref;
 179         u32 eir;
 180         u32 pgtbl_er;
 181         u32 ier;
 182         u32 ccid;
 183         bool waiting[I915_NUM_RINGS];
 184         u32 pipestat[I915_MAX_PIPES];
 185         u32 tail[I915_NUM_RINGS];
 186         u32 head[I915_NUM_RINGS];
 187         u32 ipeir[I915_NUM_RINGS];
 188         u32 ipehr[I915_NUM_RINGS];
 189         u32 instdone[I915_NUM_RINGS];
 190         u32 acthd[I915_NUM_RINGS];
 191         u32 semaphore_mboxes[I915_NUM_RINGS][I915_NUM_RINGS - 1];
 192         u32 rc_psmi[I915_NUM_RINGS]; /* sleep state */
 193         /* our own tracking of ring head and tail */
 194         u32 cpu_ring_head[I915_NUM_RINGS];
 195         u32 cpu_ring_tail[I915_NUM_RINGS];
 196         u32 error; /* gen6+ */
 197         u32 err_int; /* gen7 */
 198         u32 instpm[I915_NUM_RINGS];
 199         u32 instps[I915_NUM_RINGS];
 200         u32 extra_instdone[I915_NUM_INSTDONE_REG];
 201         u32 seqno[I915_NUM_RINGS];
 202         u64 bbaddr;
 203         u32 fault_reg[I915_NUM_RINGS];
 204         u32 done_reg;
 205         u32 faddr[I915_NUM_RINGS];
 206         u64 fence[I915_MAX_NUM_FENCES];
 207         struct timeval time;
 208         struct drm_i915_error_ring {
 209                 struct drm_i915_error_object {
 210                         int page_count;
 211                         u32 gtt_offset;
 212                         u32 *pages[0];
 213                 } *ringbuffer, *batchbuffer;
 214                 struct drm_i915_error_request {
 215                         long jiffies;
 216                         u32 seqno;
 217                         u32 tail;
 218                 } *requests;
 219                 int num_requests;
 220         } ring[I915_NUM_RINGS];
 221         struct drm_i915_error_buffer {
 222                 u32 size;
 223                 u32 name;
 224                 u32 rseqno, wseqno;
 225                 u32 gtt_offset;
 226                 u32 read_domains;
 227                 u32 write_domain;
 228                 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
 229                 s32 pinned:2;
 230                 u32 tiling:2;
 231                 u32 dirty:1;
 232                 u32 purgeable:1;
 233                 s32 ring:4;
 234                 u32 cache_level:2;
 235         } *active_bo, *pinned_bo;
 236         u32 active_bo_count, pinned_bo_count;
 237         struct intel_overlay_error_state *overlay;
 238         struct intel_display_error_state *display;
 239 };
 240
 241 struct drm_i915_display_funcs {
 242         bool (*fbc_enabled)(struct drm_device *dev);
 243         void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);
 244         void (*disable_fbc)(struct drm_device *dev);
 245         int (*get_display_clock_speed)(struct drm_device *dev);
 246         int (*get_fifo_size)(struct drm_device *dev, int plane);
 247         void (*update_wm)(struct drm_device *dev);
 248         void (*update_sprite_wm)(struct drm_device *dev, int pipe,
 249                                  uint32_t sprite_width, int pixel_size);
 250         void (*update_linetime_wm)(struct drm_device *dev, int pipe,
 251                                  struct drm_display_mode *mode);
 252         int (*crtc_mode_set)(struct drm_crtc *crtc,
 253                              struct drm_display_mode *mode,
 254                              struct drm_display_mode *adjusted_mode,
 255                              int x, int y,
 256                              struct drm_framebuffer *old_fb);
 257         void (*crtc_enable)(struct drm_crtc *crtc);
 258         void (*crtc_disable)(struct drm_crtc *crtc);
 259         void (*off)(struct drm_crtc *crtc);
 260         void (*write_eld)(struct drm_connector *connector,
 261                           struct drm_crtc *crtc);
 262         void (*fdi_link_train)(struct drm_crtc *crtc);
 263         void (*init_clock_gating)(struct drm_device *dev);
 264         void (*init_pch_clock_gating)(struct drm_device *dev);
 265         int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
 266                           struct drm_framebuffer *fb,
 267                           struct drm_i915_gem_object *obj);
 268         int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb,
 269                             int x, int y);
 270         /* clock updates for mode set */
 271         /* cursor updates */
 272         /* render clock increase/decrease */
 273         /* display clock increase/decrease */
 274         /* pll clock increase/decrease */
 275 };
 276
 277 struct drm_i915_gt_funcs {
 278         void (*force_wake_get)(struct drm_i915_private *dev_priv);
 279         void (*force_wake_put)(struct drm_i915_private *dev_priv);
 280 };
 281
 282 #define DEV_INFO_FLAGS \
 283         DEV_INFO_FLAG(is_mobile) DEV_INFO_SEP \
 284         DEV_INFO_FLAG(is_i85x) DEV_INFO_SEP \
 285         DEV_INFO_FLAG(is_i915g) DEV_INFO_SEP \
 286         DEV_INFO_FLAG(is_i945gm) DEV_INFO_SEP \
 287         DEV_INFO_FLAG(is_g33) DEV_INFO_SEP \
 288         DEV_INFO_FLAG(need_gfx_hws) DEV_INFO_SEP \
 289         DEV_INFO_FLAG(is_g4x) DEV_INFO_SEP \
 290         DEV_INFO_FLAG(is_pineview) DEV_INFO_SEP \
 291         DEV_INFO_FLAG(is_broadwater) DEV_INFO_SEP \
 292         DEV_INFO_FLAG(is_crestline) DEV_INFO_SEP \
 293         DEV_INFO_FLAG(is_ivybridge) DEV_INFO_SEP \
 294         DEV_INFO_FLAG(is_valleyview) DEV_INFO_SEP \
 295         DEV_INFO_FLAG(is_haswell) DEV_INFO_SEP \
 296         DEV_INFO_FLAG(has_force_wake) DEV_INFO_SEP \
 297         DEV_INFO_FLAG(has_fbc) DEV_INFO_SEP \
 298         DEV_INFO_FLAG(has_pipe_cxsr) DEV_INFO_SEP \
 299         DEV_INFO_FLAG(has_hotplug) DEV_INFO_SEP \
 300         DEV_INFO_FLAG(cursor_needs_physical) DEV_INFO_SEP \
 301         DEV_INFO_FLAG(has_overlay) DEV_INFO_SEP \
 302         DEV_INFO_FLAG(overlay_needs_physical) DEV_INFO_SEP \
 303         DEV_INFO_FLAG(supports_tv) DEV_INFO_SEP \
 304         DEV_INFO_FLAG(has_bsd_ring) DEV_INFO_SEP \
 305         DEV_INFO_FLAG(has_blt_ring) DEV_INFO_SEP \
 306         DEV_INFO_FLAG(has_llc)
 307
 308 struct intel_device_info {
 309         u8 gen;
 310         u8 is_mobile:1;
 311         u8 is_i85x:1;
 312         u8 is_i915g:1;
 313         u8 is_i945gm:1;
 314         u8 is_g33:1;
 315         u8 need_gfx_hws:1;
 316         u8 is_g4x:1;
 317         u8 is_pineview:1;
 318         u8 is_broadwater:1;
 319         u8 is_crestline:1;
 320         u8 is_ivybridge:1;
 321         u8 is_valleyview:1;
 322         u8 has_force_wake:1;
 323         u8 is_haswell:1;
 324         u8 has_fbc:1;
 325         u8 has_pipe_cxsr:1;
 326         u8 has_hotplug:1;
 327         u8 cursor_needs_physical:1;
 328         u8 has_overlay:1;
 329         u8 overlay_needs_physical:1;
 330         u8 supports_tv:1;
 331         u8 has_bsd_ring:1;
 332         u8 has_blt_ring:1;
 333         u8 has_llc:1;
 334 };
 335
 336 #define I915_PPGTT_PD_ENTRIES 512
 337 #define I915_PPGTT_PT_ENTRIES 1024
 338 struct i915_hw_ppgtt {
 339         unsigned num_pd_entries;
 340         struct page **pt_pages;
 341         uint32_t pd_offset;
 342         dma_addr_t *pt_dma_addr;
 343         dma_addr_t scratch_page_dma_addr;
 344 };
 345
 346
 347 /* This must match up with the value previously used for execbuf2.rsvd1. */
 348 #define DEFAULT_CONTEXT_ID 0
 349 struct i915_hw_context {
 350         int id;
 351         bool is_initialized;
 352         struct drm_i915_file_private *file_priv;
 353         struct intel_ring_buffer *ring;
 354         struct drm_i915_gem_object *obj;
 355 };
 356
 357 enum no_fbc_reason {
 358         FBC_NO_OUTPUT, /* no outputs enabled to compress */
 359         FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */
 360         FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
 361         FBC_MODE_TOO_LARGE, /* mode too large for compression */
 362         FBC_BAD_PLANE, /* fbc not supported on plane */
 363         FBC_NOT_TILED, /* buffer not tiled */
 364         FBC_MULTIPLE_PIPES, /* more than one pipe active */
 365         FBC_MODULE_PARAM,
 366 };
 367
 368 enum intel_pch {
 369         PCH_NONE = 0,   /* No PCH present */
 370         PCH_IBX,        /* Ibexpeak PCH */
 371         PCH_CPT,        /* Cougarpoint PCH */
 372         PCH_LPT,        /* Lynxpoint PCH */
 373 };
 374
 375 #define QUIRK_PIPEA_FORCE (1<<0)
 376 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
 377 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
 378
 379 struct intel_fbdev;
 380 struct intel_fbc_work;
 381
 382 struct intel_gmbus {
 383         struct i2c_adapter adapter;
 384         bool force_bit;
 385         u32 reg0;
 386         u32 gpio_reg;
 387         struct i2c_algo_bit_data bit_algo;
 388         struct drm_i915_private *dev_priv;
 389 };
 390
 391 typedef struct drm_i915_private {
 392         struct drm_device *dev;
 393
 394         const struct intel_device_info *info;
 395
 396         int relative_constants_mode;
 397
 398         void __iomem *regs;
 399
 400         struct drm_i915_gt_funcs gt;
 401         /** gt_fifo_count and the subsequent register write are synchronized
 402          * with dev->struct_mutex. */
 403         unsigned gt_fifo_count;
 404         /** forcewake_count is protected by gt_lock */
 405         unsigned forcewake_count;
 406         /** gt_lock is also taken in irq contexts. */
 407         struct spinlock gt_lock;
 408
 409         struct intel_gmbus gmbus[GMBUS_NUM_PORTS];
 410
 411         /** gmbus_mutex protects against concurrent usage of the single hw gmbus
 412          * controller on different i2c buses. */
 413         struct mutex gmbus_mutex;
 414
 415         /**
 416          * Base address of the gmbus and gpio block.
 417          */
 418         uint32_t gpio_mmio_base;
 419
 420         struct pci_dev *bridge_dev;
 421         struct intel_ring_buffer ring[I915_NUM_RINGS];
 422         uint32_t next_seqno;
 423
 424         drm_dma_handle_t *status_page_dmah;
 425         uint32_t counter;
 426         struct drm_i915_gem_object *pwrctx;
 427         struct drm_i915_gem_object *renderctx;
 428
 429         struct resource mch_res;
 430
 431         atomic_t irq_received;
 432
 433         /* protects the irq masks */
 434         spinlock_t irq_lock;
 435
 436         /* DPIO indirect register protection */
 437         spinlock_t dpio_lock;
 438
 439         /** Cached value of IMR to avoid reads in updating the bitfield */
 440         u32 pipestat[2];
 441         u32 irq_mask;
 442         u32 gt_irq_mask;
 443         u32 pch_irq_mask;
 444
 445         u32 hotplug_supported_mask;
 446         struct work_struct hotplug_work;
 447
 448         int num_pipe;
 449         int num_pch_pll;
 450
 451         /* For hangcheck timer */
 452 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
 453 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
 454         struct timer_list hangcheck_timer;
 455         int hangcheck_count;
 456         uint32_t last_acthd[I915_NUM_RINGS];
 457         uint32_t prev_instdone[I915_NUM_INSTDONE_REG];
 458
 459         unsigned int stop_rings;
 460
 461         unsigned long cfb_size;
 462         unsigned int cfb_fb;
 463         enum plane cfb_plane;
 464         int cfb_y;
 465         struct intel_fbc_work *fbc_work;
 466
 467         struct intel_opregion opregion;
 468
 469         /* overlay */
 470         struct intel_overlay *overlay;
 471         bool sprite_scaling_enabled;
 472
 473         /* LVDS info */
 474         int backlight_level;  /* restore backlight to this value */
 475         bool backlight_enabled;
 476         struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
 477         struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
 478
 479         /* Feature bits from the VBIOS */
 480         unsigned int int_tv_support:1;
 481         unsigned int lvds_dither:1;
 482         unsigned int lvds_vbt:1;
 483         unsigned int int_crt_support:1;
 484         unsigned int lvds_use_ssc:1;
 485         unsigned int display_clock_mode:1;
 486         int lvds_ssc_freq;
 487         unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
 488         unsigned int lvds_val; /* used for checking LVDS channel mode */
 489         struct {
 490                 int rate;
 491                 int lanes;
 492                 int preemphasis;
 493                 int vswing;
 494
 495                 bool initialized;
 496                 bool support;
 497                 int bpp;
 498                 struct edp_power_seq pps;
 499         } edp;
 500         bool no_aux_handshake;
 501
 502         int crt_ddc_pin;
 503         struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
 504         int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
 505         int num_fence_regs; /* 8 on pre-965, 16 otherwise */
 506
 507         unsigned int fsb_freq, mem_freq, is_ddr3;
 508
 509         spinlock_t error_lock;
 510         /* Protected by dev->error_lock. */
 511         struct drm_i915_error_state *first_error;
 512         struct work_struct error_work;
 513         struct completion error_completion;
 514         struct workqueue_struct *wq;
 515
 516         /* Display functions */
 517         struct drm_i915_display_funcs display;
 518
 519         /* PCH chipset type */
 520         enum intel_pch pch_type;
 521
 522         unsigned long quirks;
 523
 524         /* Register state */
 525         bool modeset_on_lid;
 526         u8 saveLBB;
 527         u32 saveDSPACNTR;
 528         u32 saveDSPBCNTR;
 529         u32 saveDSPARB;
 530         u32 saveHWS;
 531         u32 savePIPEACONF;
 532         u32 savePIPEBCONF;
 533         u32 savePIPEASRC;
 534         u32 savePIPEBSRC;
 535         u32 saveFPA0;
 536         u32 saveFPA1;
 537         u32 saveDPLL_A;
 538         u32 saveDPLL_A_MD;
 539         u32 saveHTOTAL_A;
 540         u32 saveHBLANK_A;
 541         u32 saveHSYNC_A;
 542         u32 saveVTOTAL_A;
 543         u32 saveVBLANK_A;
 544         u32 saveVSYNC_A;
 545         u32 saveBCLRPAT_A;
 546         u32 saveTRANSACONF;
 547         u32 saveTRANS_HTOTAL_A;
 548         u32 saveTRANS_HBLANK_A;
 549         u32 saveTRANS_HSYNC_A;
 550         u32 saveTRANS_VTOTAL_A;
 551         u32 saveTRANS_VBLANK_A;
 552         u32 saveTRANS_VSYNC_A;
 553         u32 savePIPEASTAT;
 554         u32 saveDSPASTRIDE;
 555         u32 saveDSPASIZE;
 556         u32 saveDSPAPOS;
 557         u32 saveDSPAADDR;
 558         u32 saveDSPASURF;
 559         u32 saveDSPATILEOFF;
 560         u32 savePFIT_PGM_RATIOS;
 561         u32 saveBLC_HIST_CTL;
 562         u32 saveBLC_PWM_CTL;
 563         u32 saveBLC_PWM_CTL2;
 564         u32 saveBLC_CPU_PWM_CTL;
 565         u32 saveBLC_CPU_PWM_CTL2;
 566         u32 saveFPB0;
 567         u32 saveFPB1;
 568         u32 saveDPLL_B;
 569         u32 saveDPLL_B_MD;
 570         u32 saveHTOTAL_B;
 571         u32 saveHBLANK_B;
 572         u32 saveHSYNC_B;
 573         u32 saveVTOTAL_B;
 574         u32 saveVBLANK_B;
 575         u32 saveVSYNC_B;
 576         u32 saveBCLRPAT_B;
 577         u32 saveTRANSBCONF;
 578         u32 saveTRANS_HTOTAL_B;
 579         u32 saveTRANS_HBLANK_B;
 580         u32 saveTRANS_HSYNC_B;
 581         u32 saveTRANS_VTOTAL_B;
 582         u32 saveTRANS_VBLANK_B;
 583         u32 saveTRANS_VSYNC_B;
 584         u32 savePIPEBSTAT;
 585         u32 saveDSPBSTRIDE;
 586         u32 saveDSPBSIZE;
 587         u32 saveDSPBPOS;
 588         u32 saveDSPBADDR;
 589         u32 saveDSPBSURF;
 590         u32 saveDSPBTILEOFF;
 591         u32 saveVGA0;
 592         u32 saveVGA1;
 593         u32 saveVGA_PD;
 594         u32 saveVGACNTRL;
 595         u32 saveADPA;
 596         u32 saveLVDS;
 597         u32 savePP_ON_DELAYS;
 598         u32 savePP_OFF_DELAYS;
 599         u32 saveDVOA;
 600         u32 saveDVOB;
 601         u32 saveDVOC;
 602         u32 savePP_ON;
 603         u32 savePP_OFF;
 604         u32 savePP_CONTROL;
 605         u32 savePP_DIVISOR;
 606         u32 savePFIT_CONTROL;
 607         u32 save_palette_a[256];
 608         u32 save_palette_b[256];
 609         u32 saveDPFC_CB_BASE;
 610         u32 saveFBC_CFB_BASE;
 611         u32 saveFBC_LL_BASE;
 612         u32 saveFBC_CONTROL;
 613         u32 saveFBC_CONTROL2;
 614         u32 saveIER;
 615         u32 saveIIR;
 616         u32 saveIMR;
 617         u32 saveDEIER;
 618         u32 saveDEIMR;
 619         u32 saveGTIER;
 620         u32 saveGTIMR;
 621         u32 saveFDI_RXA_IMR;
 622         u32 saveFDI_RXB_IMR;
 623         u32 saveCACHE_MODE_0;
 624         u32 saveMI_ARB_STATE;
 625         u32 saveSWF0[16];
 626         u32 saveSWF1[16];
 627         u32 saveSWF2[3];
 628         u8 saveMSR;
 629         u8 saveSR[8];
 630         u8 saveGR[25];
 631         u8 saveAR_INDEX;
 632         u8 saveAR[21];
 633         u8 saveDACMASK;
 634         u8 saveCR[37];
 635         uint64_t saveFENCE[I915_MAX_NUM_FENCES];
 636         u32 saveCURACNTR;
 637         u32 saveCURAPOS;
 638         u32 saveCURABASE;
 639         u32 saveCURBCNTR;
 640         u32 saveCURBPOS;
 641         u32 saveCURBBASE;
 642         u32 saveCURSIZE;
 643         u32 saveDP_B;
 644         u32 saveDP_C;
 645         u32 saveDP_D;
 646         u32 savePIPEA_GMCH_DATA_M;
 647         u32 savePIPEB_GMCH_DATA_M;
 648         u32 savePIPEA_GMCH_DATA_N;
 649         u32 savePIPEB_GMCH_DATA_N;
 650         u32 savePIPEA_DP_LINK_M;
 651         u32 savePIPEB_DP_LINK_M;
 652         u32 savePIPEA_DP_LINK_N;
 653         u32 savePIPEB_DP_LINK_N;
 654         u32 saveFDI_RXA_CTL;
 655         u32 saveFDI_TXA_CTL;
 656         u32 saveFDI_RXB_CTL;
 657         u32 saveFDI_TXB_CTL;
 658         u32 savePFA_CTL_1;
 659         u32 savePFB_CTL_1;
 660         u32 savePFA_WIN_SZ;
 661         u32 savePFB_WIN_SZ;
 662         u32 savePFA_WIN_POS;
 663         u32 savePFB_WIN_POS;
 664         u32 savePCH_DREF_CONTROL;
 665         u32 saveDISP_ARB_CTL;
 666         u32 savePIPEA_DATA_M1;
 667         u32 savePIPEA_DATA_N1;
 668         u32 savePIPEA_LINK_M1;
 669         u32 savePIPEA_LINK_N1;
 670         u32 savePIPEB_DATA_M1;
 671         u32 savePIPEB_DATA_N1;
 672         u32 savePIPEB_LINK_M1;
 673         u32 savePIPEB_LINK_N1;
 674         u32 saveMCHBAR_RENDER_STANDBY;
 675         u32 savePCH_PORT_HOTPLUG;
 676
 677         struct {
 678                 /** Bridge to intel-gtt-ko */
 679                 const struct intel_gtt *gtt;
 680                 /** Memory allocator for GTT stolen memory */
 681                 struct drm_mm stolen;
 682                 /** Memory allocator for GTT */
 683                 struct drm_mm gtt_space;
 684                 /** List of all objects in gtt_space. Used to restore gtt
 685                  * mappings on resume */
 686                 struct list_head bound_list;
 687                 /**
 688                  * List of objects which are not bound to the GTT (thus
 689                  * are idle and not used by the GPU) but still have
 690                  * (presumably uncached) pages still attached.
 691                  */
 692                 struct list_head unbound_list;
 693
 694                 /** Usable portion of the GTT for GEM */
 695                 unsigned long gtt_start;
 696                 unsigned long gtt_mappable_end;
 697                 unsigned long gtt_end;
 698
 699                 struct io_mapping *gtt_mapping;
 700                 phys_addr_t gtt_base_addr;
 701                 int gtt_mtrr;
 702
 703                 /** PPGTT used for aliasing the PPGTT with the GTT */
 704                 struct i915_hw_ppgtt *aliasing_ppgtt;
 705
 706                 u32 *l3_remap_info;
 707
 708                 struct shrinker inactive_shrinker;
 709
 710                 /**
 711                  * List of objects currently involved in rendering.
 712                  *
 713                  * Includes buffers having the contents of their GPU caches
 714                  * flushed, not necessarily primitives.  last_rendering_seqno
 715                  * represents when the rendering involved will be completed.
 716                  *
 717                  * A reference is held on the buffer while on this list.
 718                  */
 719                 struct list_head active_list;
 720
 721                 /**
 722                  * LRU list of objects which are not in the ringbuffer and
 723                  * are ready to unbind, but are still in the GTT.
 724                  *
 725                  * last_rendering_seqno is 0 while an object is in this list.
 726                  *
 727                  * A reference is not held on the buffer while on this list,
 728                  * as merely being GTT-bound shouldn't prevent its being
 729                  * freed, and we'll pull it off the list in the free path.
 730                  */
 731                 struct list_head inactive_list;
 732
 733                 /** LRU list of objects with fence regs on them. */
 734                 struct list_head fence_list;
 735
 736                 /**
 737                  * We leave the user IRQ off as much as possible,
 738                  * but this means that requests will finish and never
 739                  * be retired once the system goes idle. Set a timer to
 740                  * fire periodically while the ring is running. When it
 741                  * fires, go retire requests.
 742                  */
 743                 struct delayed_work retire_work;
 744
 745                 /**
 746                  * Are we in a non-interruptible section of code like
 747                  * modesetting?
 748                  */
 749                 bool interruptible;
 750
 751                 /**
 752                  * Flag if the X Server, and thus DRM, is not currently in
 753                  * control of the device.
 754                  *
 755                  * This is set between LeaveVT and EnterVT.  It needs to be
 756                  * replaced with a semaphore.  It also needs to be
 757                  * transitioned away from for kernel modesetting.
 758                  */
 759                 int suspended;
 760
 761                 /**
 762                  * Flag if the hardware appears to be wedged.
 763                  *
 764                  * This is set when attempts to idle the device timeout.
 765                  * It prevents command submission from occurring and makes
 766                  * every pending request fail
 767                  */
 768                 atomic_t wedged;
 769
 770                 /** Bit 6 swizzling required for X tiling */
 771                 uint32_t bit_6_swizzle_x;
 772                 /** Bit 6 swizzling required for Y tiling */
 773                 uint32_t bit_6_swizzle_y;
 774
 775                 /* storage for physical objects */
 776                 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
 777
 778                 /* accounting, useful for userland debugging */
 779                 size_t gtt_total;
 780                 size_t mappable_gtt_total;
 781                 size_t object_memory;
 782                 u32 object_count;
 783         } mm;
 784
 785         /* Old dri1 support infrastructure, beware the dragons ya fools entering
 786          * here! */
 787         struct {
 788                 unsigned allow_batchbuffer : 1;
 789                 u32 __iomem *gfx_hws_cpu_addr;
 790
 791                 unsigned int cpp;
 792                 int back_offset;
 793                 int front_offset;
 794                 int current_page;
 795                 int page_flipping;
 796         } dri1;
 797
 798         /* Kernel Modesetting */
 799
 800         struct sdvo_device_mapping sdvo_mappings[2];
 801         /* indicate whether the LVDS_BORDER should be enabled or not */
 802         unsigned int lvds_border_bits;
 803         /* Panel fitter placement and size for Ironlake+ */
 804         u32 pch_pf_pos, pch_pf_size;
 805
 806         struct drm_crtc *plane_to_crtc_mapping[3];
 807         struct drm_crtc *pipe_to_crtc_mapping[3];
 808         wait_queue_head_t pending_flip_queue;
 809
 810         struct intel_pch_pll pch_plls[I915_NUM_PLLS];
 811         struct intel_ddi_plls ddi_plls;
 812
 813         /* Reclocking support */
 814         bool render_reclock_avail;
 815         bool lvds_downclock_avail;
 816         /* indicates the reduced downclock for LVDS*/
 817         int lvds_downclock;
 818         u16 orig_clock;
 819         int child_dev_num;
 820         struct child_device_config *child_dev;
 821
 822         bool mchbar_need_disable;
 823
 824         /* gen6+ rps state */
 825         struct {
 826                 struct work_struct work;
 827                 u32 pm_iir;
 828                 /* lock - irqsave spinlock that protectects the work_struct and
 829                  * pm_iir. */
 830                 spinlock_t lock;
 831
 832                 /* The below variables an all the rps hw state are protected by
 833                  * dev->struct mutext. */
 834                 u8 cur_delay;
 835                 u8 min_delay;
 836                 u8 max_delay;
 837         } rps;
 838
 839         /* ilk-only ips/rps state. Everything in here is protected by the global
 840          * mchdev_lock in intel_pm.c */
 841         struct {
 842                 u8 cur_delay;
 843                 u8 min_delay;
 844                 u8 max_delay;
 845                 u8 fmax;
 846                 u8 fstart;
 847
 848                 u64 last_count1;
 849                 unsigned long last_time1;
 850                 unsigned long chipset_power;
 851                 u64 last_count2;
 852                 struct timespec last_time2;
 853                 unsigned long gfx_power;
 854                 u8 corr;
 855
 856                 int c_m;
 857                 int r_t;
 858         } ips;
 859
 860         enum no_fbc_reason no_fbc_reason;
 861
 862         struct drm_mm_node *compressed_fb;
 863         struct drm_mm_node *compressed_llb;
 864
 865         unsigned long last_gpu_reset;
 866
 867         /* list of fbdev register on this device */
 868         struct intel_fbdev *fbdev;
 869
 870         struct backlight_device *backlight;
 871
 872         struct drm_property *broadcast_rgb_property;
 873         struct drm_property *force_audio_property;
 874
 875         struct work_struct parity_error_work;
 876         bool hw_contexts_disabled;
 877         uint32_t hw_context_size;
 878 } drm_i915_private_t;
 879
 880 /* Iterate over initialised rings */
 881 #define for_each_ring(ring__, dev_priv__, i__) \
 882         for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
 883                 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
 884
 885 enum hdmi_force_audio {
 886         HDMI_AUDIO_OFF_DVI = -2,        /* no aux data for HDMI-DVI converter */
 887         HDMI_AUDIO_OFF,                 /* force turn off HDMI audio */
 888         HDMI_AUDIO_AUTO,                /* trust EDID */
 889         HDMI_AUDIO_ON,                  /* force turn on HDMI audio */
 890 };
 891
 892 enum i915_cache_level {
 893         I915_CACHE_NONE = 0,
 894         I915_CACHE_LLC,
 895         I915_CACHE_LLC_MLC, /* gen6+, in docs at least! */
 896 };
 897
 898 struct drm_i915_gem_object_ops {
 899         /* Interface between the GEM object and its backing storage.
 900          * get_pages() is called once prior to the use of the associated set
 901          * of pages before to binding them into the GTT, and put_pages() is
 902          * called after we no longer need them. As we expect there to be
 903          * associated cost with migrating pages between the backing storage
 904          * and making them available for the GPU (e.g. clflush), we may hold
 905          * onto the pages after they are no longer referenced by the GPU
 906          * in case they may be used again shortly (for example migrating the
 907          * pages to a different memory domain within the GTT). put_pages()
 908          * will therefore most likely be called when the object itself is
 909          * being released or under memory pressure (where we attempt to
 910          * reap pages for the shrinker).
 911          */
 912         int (*get_pages)(struct drm_i915_gem_object *);
 913         void (*put_pages)(struct drm_i915_gem_object *);
 914 };
 915
 916 struct drm_i915_gem_object {
 917         struct drm_gem_object base;
 918
 919         const struct drm_i915_gem_object_ops *ops;
 920
 921         /** Current space allocated to this object in the GTT, if any. */
 922         struct drm_mm_node *gtt_space;
 923         struct list_head gtt_list;
 924
 925         /** This object's place on the active/inactive lists */
 926         struct list_head ring_list;
 927         struct list_head mm_list;
 928         /** This object's place in the batchbuffer or on the eviction list */
 929         struct list_head exec_list;
 930
 931         /**
 932          * This is set if the object is on the active lists (has pending
 933          * rendering and so a non-zero seqno), and is not set if it i s on
 934          * inactive (ready to be unbound) list.
 935          */
 936         unsigned int active:1;
 937
 938         /**
 939          * This is set if the object has been written to since last bound
 940          * to the GTT
 941          */
 942         unsigned int dirty:1;
 943
 944         /**
 945          * Fence register bits (if any) for this object.  Will be set
 946          * as needed when mapped into the GTT.
 947          * Protected by dev->struct_mutex.
 948          */
 949         signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
 950
 951         /**
 952          * Advice: are the backing pages purgeable?
 953          */
 954         unsigned int madv:2;
 955
 956         /**
 957          * Current tiling mode for the object.
 958          */
 959         unsigned int tiling_mode:2;
 960         /**
 961          * Whether the tiling parameters for the currently associated fence
 962          * register have changed. Note that for the purposes of tracking
 963          * tiling changes we also treat the unfenced register, the register
 964          * slot that the object occupies whilst it executes a fenced
 965          * command (such as BLT on gen2/3), as a "fence".
 966          */
 967         unsigned int fence_dirty:1;
 968
 969         /** How many users have pinned this object in GTT space. The following
 970          * users can each hold at most one reference: pwrite/pread, pin_ioctl
 971          * (via user_pin_count), execbuffer (objects are not allowed multiple
 972          * times for the same batchbuffer), and the framebuffer code. When
 973          * switching/pageflipping, the framebuffer code has at most two buffers
 974          * pinned per crtc.
 975          *
 976          * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
 977          * bits with absolutely no headroom. So use 4 bits. */
 978         unsigned int pin_count:4;
 979 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
 980
 981         /**
 982          * Is the object at the current location in the gtt mappable and
 983          * fenceable? Used to avoid costly recalculations.
 984          */
 985         unsigned int map_and_fenceable:1;
 986
 987         /**
 988          * Whether the current gtt mapping needs to be mappable (and isn't just
 989          * mappable by accident). Track pin and fault separate for a more
 990          * accurate mappable working set.
 991          */
 992         unsigned int fault_mappable:1;
 993         unsigned int pin_mappable:1;
 994
 995         /*
 996          * Is the GPU currently using a fence to access this buffer,
 997          */
 998         unsigned int pending_fenced_gpu_access:1;
 999         unsigned int fenced_gpu_access:1;
1000
1001         unsigned int cache_level:2;
1002
1003         unsigned int has_aliasing_ppgtt_mapping:1;
1004         unsigned int has_global_gtt_mapping:1;
1005         unsigned int has_dma_mapping:1;
1006
1007         struct sg_table *pages;
1008         int pages_pin_count;
1009
1010         /* prime dma-buf support */
1011         void *dma_buf_vmapping;
1012         int vmapping_count;
1013
1014         /**
1015          * Used for performing relocations during execbuffer insertion.
1016          */
1017         struct hlist_node exec_node;
1018         unsigned long exec_handle;
1019         struct drm_i915_gem_exec_object2 *exec_entry;
1020
1021         /**
1022          * Current offset of the object in GTT space.
1023          *
1024          * This is the same as gtt_space->start
1025          */
1026         uint32_t gtt_offset;
1027
1028         struct intel_ring_buffer *ring;
1029
1030         /** Breadcrumb of last rendering to the buffer. */
1031         uint32_t last_read_seqno;
1032         uint32_t last_write_seqno;
1033         /** Breadcrumb of last fenced GPU access to the buffer. */
1034         uint32_t last_fenced_seqno;
1035
1036         /** Current tiling stride for the object, if it's tiled. */
1037         uint32_t stride;
1038
1039         /** Record of address bit 17 of each page at last unbind. */
1040         unsigned long *bit_17;
1041
1042         /** User space pin count and filp owning the pin */
1043         uint32_t user_pin_count;
1044         struct drm_file *pin_filp;
1045
1046         /** for phy allocated objects */
1047         struct drm_i915_gem_phys_object *phys_obj;
1048
1049         /**
1050          * Number of crtcs where this object is currently the fb, but
1051          * will be page flipped away on the next vblank.  When it
1052          * reaches 0, dev_priv->pending_flip_queue will be woken up.
1053          */
1054         atomic_t pending_flip;
1055 };
1056
1057 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
1058
1059 /**
1060  * Request queue structure.
1061  *
1062  * The request queue allows us to note sequence numbers that have been emitted
1063  * and may be associated with active buffers to be retired.
1064  *
1065  * By keeping this list, we can avoid having to do questionable
1066  * sequence-number comparisons on buffer last_rendering_seqnos, and associate
1067  * an emission time with seqnos for tracking how far ahead of the GPU we are.
1068  */
1069 struct drm_i915_gem_request {
1070         /** On Which ring this request was generated */
1071         struct intel_ring_buffer *ring;
1072
1073         /** GEM sequence number associated with this request. */
1074         uint32_t seqno;
1075
1076         /** Postion in the ringbuffer of the end of the request */
1077         u32 tail;
1078
1079         /** Time at which this request was emitted, in jiffies. */
1080         unsigned long emitted_jiffies;
1081
1082         /** global list entry for this request */
1083         struct list_head list;
1084
1085         struct drm_i915_file_private *file_priv;
1086         /** file_priv list entry for this request */
1087         struct list_head client_list;
1088 };
1089
1090 struct drm_i915_file_private {
1091         struct {
1092                 struct spinlock lock;
1093                 struct list_head request_list;
1094         } mm;
1095         struct idr context_idr;
1096 };
1097
1098 #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
1099
1100 #define IS_I830(dev)            ((dev)->pci_device == 0x3577)
1101 #define IS_845G(dev)            ((dev)->pci_device == 0x2562)
1102 #define IS_I85X(dev)            (INTEL_INFO(dev)->is_i85x)
1103 #define IS_I865G(dev)           ((dev)->pci_device == 0x2572)
1104 #define IS_I915G(dev)           (INTEL_INFO(dev)->is_i915g)
1105 #define IS_I915GM(dev)          ((dev)->pci_device == 0x2592)
1106 #define IS_I945G(dev)           ((dev)->pci_device == 0x2772)
1107 #define IS_I945GM(dev)          (INTEL_INFO(dev)->is_i945gm)
1108 #define IS_BROADWATER(dev)      (INTEL_INFO(dev)->is_broadwater)
1109 #define IS_CRESTLINE(dev)       (INTEL_INFO(dev)->is_crestline)
1110 #define IS_GM45(dev)            ((dev)->pci_device == 0x2A42)
1111 #define IS_G4X(dev)             (INTEL_INFO(dev)->is_g4x)
1112 #define IS_PINEVIEW_G(dev)      ((dev)->pci_device == 0xa001)
1113 #define IS_PINEVIEW_M(dev)      ((dev)->pci_device == 0xa011)
1114 #define IS_PINEVIEW(dev)        (INTEL_INFO(dev)->is_pineview)
1115 #define IS_G33(dev)             (INTEL_INFO(dev)->is_g33)
1116 #define IS_IRONLAKE_D(dev)      ((dev)->pci_device == 0x0042)
1117 #define IS_IRONLAKE_M(dev)      ((dev)->pci_device == 0x0046)
1118 #define IS_IVYBRIDGE(dev)       (INTEL_INFO(dev)->is_ivybridge)
1119 #define IS_VALLEYVIEW(dev)      (INTEL_INFO(dev)->is_valleyview)
1120 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
1121 #define IS_MOBILE(dev)          (INTEL_INFO(dev)->is_mobile)
1122
1123 /*
1124  * The genX designation typically refers to the render engine, so render
1125  * capability related checks should use IS_GEN, while display and other checks
1126  * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
1127  * chips, etc.).
1128  */
1129 #define IS_GEN2(dev)    (INTEL_INFO(dev)->gen == 2)
1130 #define IS_GEN3(dev)    (INTEL_INFO(dev)->gen == 3)
1131 #define IS_GEN4(dev)    (INTEL_INFO(dev)->gen == 4)
1132 #define IS_GEN5(dev)    (INTEL_INFO(dev)->gen == 5)
1133 #define IS_GEN6(dev)    (INTEL_INFO(dev)->gen == 6)
1134 #define IS_GEN7(dev)    (INTEL_INFO(dev)->gen == 7)
1135
1136 #define HAS_BSD(dev)            (INTEL_INFO(dev)->has_bsd_ring)
1137 #define HAS_BLT(dev)            (INTEL_INFO(dev)->has_blt_ring)
1138 #define HAS_LLC(dev)            (INTEL_INFO(dev)->has_llc)
1139 #define I915_NEED_GFX_HWS(dev)  (INTEL_INFO(dev)->need_gfx_hws)
1140
1141 #define HAS_HW_CONTEXTS(dev)    (INTEL_INFO(dev)->gen >= 6)
1142 #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6 && !IS_VALLEYVIEW(dev))
1143
1144 #define HAS_OVERLAY(dev)                (INTEL_INFO(dev)->has_overlay)
1145 #define OVERLAY_NEEDS_PHYSICAL(dev)     (INTEL_INFO(dev)->overlay_needs_physical)
1146
1147 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1148  * rows, which changed the alignment requirements and fence programming.
1149  */
1150 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
1151                                                       IS_I915GM(dev)))
1152 #define SUPPORTS_DIGITAL_OUTPUTS(dev)   (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
1153 #define SUPPORTS_INTEGRATED_HDMI(dev)   (IS_G4X(dev) || IS_GEN5(dev))
1154 #define SUPPORTS_INTEGRATED_DP(dev)     (IS_G4X(dev) || IS_GEN5(dev))
1155 #define SUPPORTS_EDP(dev)               (IS_IRONLAKE_M(dev))
1156 #define SUPPORTS_TV(dev)                (INTEL_INFO(dev)->supports_tv)
1157 #define I915_HAS_HOTPLUG(dev)            (INTEL_INFO(dev)->has_hotplug)
1158 /* dsparb controlled by hw only */
1159 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1160
1161 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
1162 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
1163 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
1164
1165 #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5)
1166
1167 #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
1168 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
1169 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
1170 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
1171 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
1172
1173 #define HAS_FORCE_WAKE(dev) (INTEL_INFO(dev)->has_force_wake)
1174
1175 #define HAS_L3_GPU_CACHE(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1176
1177 #define GT_FREQUENCY_MULTIPLIER 50
1178
1179 #include "i915_trace.h"
1180
1181 /**
1182  * RC6 is a special power stage which allows the GPU to enter an very
1183  * low-voltage mode when idle, using down to 0V while at this stage.  This
1184  * stage is entered automatically when the GPU is idle when RC6 support is
1185  * enabled, and as soon as new workload arises GPU wakes up automatically as well.
1186  *
1187  * There are different RC6 modes available in Intel GPU, which differentiate
1188  * among each other with the latency required to enter and leave RC6 and
1189  * voltage consumed by the GPU in different states.
1190  *
1191  * The combination of the following flags define which states GPU is allowed
1192  * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
1193  * RC6pp is deepest RC6. Their support by hardware varies according to the
1194  * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
1195  * which brings the most power savings; deeper states save more power, but
1196  * require higher latency to switch to and wake up.
1197  */
1198 #define INTEL_RC6_ENABLE                        (1<<0)
1199 #define INTEL_RC6p_ENABLE                       (1<<1)
1200 #define INTEL_RC6pp_ENABLE                      (1<<2)
1201
1202 extern struct drm_ioctl_desc i915_ioctls[];
1203 extern int i915_max_ioctl;
1204 extern unsigned int i915_fbpercrtc __always_unused;
1205 extern int i915_panel_ignore_lid __read_mostly;
1206 extern unsigned int i915_powersave __read_mostly;
1207 extern int i915_semaphores __read_mostly;
1208 extern unsigned int i915_lvds_downclock __read_mostly;
1209 extern int i915_lvds_channel_mode __read_mostly;
1210 extern int i915_panel_use_ssc __read_mostly;
1211 extern int i915_vbt_sdvo_panel_type __read_mostly;
1212 extern int i915_enable_rc6 __read_mostly;
1213 extern int i915_enable_fbc __read_mostly;
1214 extern bool i915_enable_hangcheck __read_mostly;
1215 extern int i915_enable_ppgtt __read_mostly;
1216
1217 extern int i915_suspend(struct drm_device *dev, pm_message_t state);
1218 extern int i915_resume(struct drm_device *dev);
1219 extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
1220 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
1221
1222                                 /* i915_dma.c */
1223 void i915_update_dri1_breadcrumb(struct drm_device *dev);
1224 extern void i915_kernel_lost_context(struct drm_device * dev);
1225 extern int i915_driver_load(struct drm_device *, unsigned long flags);
1226 extern int i915_driver_unload(struct drm_device *);
1227 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
1228 extern void i915_driver_lastclose(struct drm_device * dev);
1229 extern void i915_driver_preclose(struct drm_device *dev,
1230                                  struct drm_file *file_priv);
1231 extern void i915_driver_postclose(struct drm_device *dev,
1232                                   struct drm_file *file_priv);
1233 extern int i915_driver_device_is_agp(struct drm_device * dev);
1234 #ifdef CONFIG_COMPAT
1235 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
1236                               unsigned long arg);
1237 #endif
1238 extern int i915_emit_box(struct drm_device *dev,
1239                          struct drm_clip_rect *box,
1240                          int DR1, int DR4);
1241 extern int intel_gpu_reset(struct drm_device *dev);
1242 extern int i915_reset(struct drm_device *dev);
1243 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
1244 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
1245 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
1246 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
1247
1248
1249 /* i915_irq.c */
1250 void i915_hangcheck_elapsed(unsigned long data);
1251 void i915_handle_error(struct drm_device *dev, bool wedged);
1252
1253 extern void intel_irq_init(struct drm_device *dev);
1254 extern void intel_gt_init(struct drm_device *dev);
1255 extern void intel_gt_reset(struct drm_device *dev);
1256
1257 void i915_error_state_free(struct kref *error_ref);
1258
1259 void
1260 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1261
1262 void
1263 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1264
1265 void intel_enable_asle(struct drm_device *dev);
1266
1267 #ifdef CONFIG_DEBUG_FS
1268 extern void i915_destroy_error_state(struct drm_device *dev);
1269 #else
1270 #define i915_destroy_error_state(x)
1271 #endif
1272
1273
1274 /* i915_gem.c */
1275 int i915_gem_init_ioctl(struct drm_device *dev, void *data,
1276                         struct drm_file *file_priv);
1277 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
1278                           struct drm_file *file_priv);
1279 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
1280                          struct drm_file *file_priv);
1281 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1282                           struct drm_file *file_priv);
1283 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1284                         struct drm_file *file_priv);
1285 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1286                         struct drm_file *file_priv);
1287 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1288                               struct drm_file *file_priv);
1289 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1290                              struct drm_file *file_priv);
1291 int i915_gem_execbuffer(struct drm_device *dev, void *data,
1292                         struct drm_file *file_priv);
1293 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
1294                          struct drm_file *file_priv);
1295 int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
1296                        struct drm_file *file_priv);
1297 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
1298                          struct drm_file *file_priv);
1299 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
1300                         struct drm_file *file_priv);
1301 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
1302                                struct drm_file *file);
1303 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
1304                                struct drm_file *file);
1305 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
1306                             struct drm_file *file_priv);
1307 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
1308                            struct drm_file *file_priv);
1309 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
1310                            struct drm_file *file_priv);
1311 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
1312                            struct drm_file *file_priv);
1313 int i915_gem_set_tiling(struct drm_device *dev, void *data,
1314                         struct drm_file *file_priv);
1315 int i915_gem_get_tiling(struct drm_device *dev, void *data,
1316                         struct drm_file *file_priv);
1317 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
1318                                 struct drm_file *file_priv);
1319 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
1320                         struct drm_file *file_priv);
1321 void i915_gem_load(struct drm_device *dev);
1322 int i915_gem_init_object(struct drm_gem_object *obj);
1323 void i915_gem_object_init(struct drm_i915_gem_object *obj,
1324                          const struct drm_i915_gem_object_ops *ops);
1325 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
1326                                                   size_t size);
1327 void i915_gem_free_object(struct drm_gem_object *obj);
1328 int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
1329                                      uint32_t alignment,
1330                                      bool map_and_fenceable,
1331                                      bool nonblocking);
1332 void i915_gem_object_unpin(struct drm_i915_gem_object *obj);
1333 int __must_check i915_gem_object_unbind(struct drm_i915_gem_object *obj);
1334 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
1335 void i915_gem_lastclose(struct drm_device *dev);
1336
1337 int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
1338 static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
1339 {
1340         struct scatterlist *sg = obj->pages->sgl;
1341         int nents = obj->pages->nents;
1342         while (nents > SG_MAX_SINGLE_ALLOC) {
1343                 if (n < SG_MAX_SINGLE_ALLOC - 1)
1344                         break;
1345
1346                 sg = sg_chain_ptr(sg + SG_MAX_SINGLE_ALLOC - 1);
1347                 n -= SG_MAX_SINGLE_ALLOC - 1;
1348                 nents -= SG_MAX_SINGLE_ALLOC - 1;
1349         }
1350         return sg_page(sg+n);
1351 }
1352 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
1353 {
1354         BUG_ON(obj->pages == NULL);
1355         obj->pages_pin_count++;
1356 }
1357 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
1358 {
1359         BUG_ON(obj->pages_pin_count == 0);
1360         obj->pages_pin_count--;
1361 }
1362
1363 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
1364 int i915_gem_object_sync(struct drm_i915_gem_object *obj,
1365                          struct intel_ring_buffer *to);
1366 void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1367                                     struct intel_ring_buffer *ring,
1368                                     u32 seqno);
1369
1370 int i915_gem_dumb_create(struct drm_file *file_priv,
1371                          struct drm_device *dev,
1372                          struct drm_mode_create_dumb *args);
1373 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
1374                       uint32_t handle, uint64_t *offset);
1375 int i915_gem_dumb_destroy(struct drm_file *file_priv, struct drm_device *dev,
1376                           uint32_t handle);
1377 /**
1378  * Returns true if seq1 is later than seq2.
1379  */
1380 static inline bool
1381 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1382 {
1383         return (int32_t)(seq1 - seq2) >= 0;
1384 }
1385
1386 u32 i915_gem_next_request_seqno(struct intel_ring_buffer *ring);
1387
1388 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
1389 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
1390
1391 static inline bool
1392 i915_gem_object_pin_fence(struct drm_i915_gem_object *obj)
1393 {
1394         if (obj->fence_reg != I915_FENCE_REG_NONE) {
1395                 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1396                 dev_priv->fence_regs[obj->fence_reg].pin_count++;
1397                 return true;
1398         } else
1399                 return false;
1400 }
1401
1402 static inline void
1403 i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
1404 {
1405         if (obj->fence_reg != I915_FENCE_REG_NONE) {
1406                 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1407                 dev_priv->fence_regs[obj->fence_reg].pin_count--;
1408         }
1409 }
1410
1411 void i915_gem_retire_requests(struct drm_device *dev);
1412 void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring);
1413 int __must_check i915_gem_check_wedge(struct drm_i915_private *dev_priv,
1414                                       bool interruptible);
1415
1416 void i915_gem_reset(struct drm_device *dev);
1417 void i915_gem_clflush_object(struct drm_i915_gem_object *obj);
1418 int __must_check i915_gem_object_set_domain(struct drm_i915_gem_object *obj,
1419                                             uint32_t read_domains,
1420                                             uint32_t write_domain);
1421 int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
1422 int __must_check i915_gem_init(struct drm_device *dev);
1423 int __must_check i915_gem_init_hw(struct drm_device *dev);
1424 void i915_gem_l3_remap(struct drm_device *dev);
1425 void i915_gem_init_swizzling(struct drm_device *dev);
1426 void i915_gem_init_ppgtt(struct drm_device *dev);
1427 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
1428 int __must_check i915_gpu_idle(struct drm_device *dev);
1429 int __must_check i915_gem_idle(struct drm_device *dev);
1430 int i915_add_request(struct intel_ring_buffer *ring,
1431                      struct drm_file *file,
1432                      u32 *seqno);
1433 int __must_check i915_wait_seqno(struct intel_ring_buffer *ring,
1434                                  uint32_t seqno);
1435 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
1436 int __must_check
1437 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
1438                                   bool write);
1439 int __must_check
1440 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
1441 int __must_check
1442 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
1443                                      u32 alignment,
1444                                      struct intel_ring_buffer *pipelined);
1445 int i915_gem_attach_phys_object(struct drm_device *dev,
1446                                 struct drm_i915_gem_object *obj,
1447                                 int id,
1448                                 int align);
1449 void i915_gem_detach_phys_object(struct drm_device *dev,
1450                                  struct drm_i915_gem_object *obj);
1451 void i915_gem_free_all_phys_object(struct drm_device *dev);
1452 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
1453
1454 uint32_t
1455 i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev,
1456                                     uint32_t size,
1457                                     int tiling_mode);
1458
1459 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
1460                                     enum i915_cache_level cache_level);
1461
1462 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
1463                                 struct dma_buf *dma_buf);
1464
1465 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
1466                                 struct drm_gem_object *gem_obj, int flags);
1467
1468 /* i915_gem_context.c */
1469 void i915_gem_context_init(struct drm_device *dev);
1470 void i915_gem_context_fini(struct drm_device *dev);
1471 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
1472 int i915_switch_context(struct intel_ring_buffer *ring,
1473                         struct drm_file *file, int to_id);
1474 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
1475                                   struct drm_file *file);
1476 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
1477                                    struct drm_file *file);
1478
1479 /* i915_gem_gtt.c */
1480 int __must_check i915_gem_init_aliasing_ppgtt(struct drm_device *dev);
1481 void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev);
1482 void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt,
1483                             struct drm_i915_gem_object *obj,
1484                             enum i915_cache_level cache_level);
1485 void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt,
1486                               struct drm_i915_gem_object *obj);
1487
1488 void i915_gem_restore_gtt_mappings(struct drm_device *dev);
1489 int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj);
1490 void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj,
1491                                 enum i915_cache_level cache_level);
1492 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj);
1493 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj);
1494 void i915_gem_init_global_gtt(struct drm_device *dev,
1495                               unsigned long start,
1496                               unsigned long mappable_end,
1497                               unsigned long end);
1498
1499 /* i915_gem_evict.c */
1500 int __must_check i915_gem_evict_something(struct drm_device *dev, int min_size,
1501                                           unsigned alignment,
1502                                           unsigned cache_level,
1503                                           bool mappable,
1504                                           bool nonblock);
1505 int i915_gem_evict_everything(struct drm_device *dev);
1506
1507 /* i915_gem_stolen.c */
1508 int i915_gem_init_stolen(struct drm_device *dev);
1509 void i915_gem_cleanup_stolen(struct drm_device *dev);
1510
1511 /* i915_gem_tiling.c */
1512 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
1513 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
1514 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
1515
1516 /* i915_gem_debug.c */
1517 void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
1518                           const char *where, uint32_t mark);
1519 #if WATCH_LISTS
1520 int i915_verify_lists(struct drm_device *dev);
1521 #else
1522 #define i915_verify_lists(dev) 0
1523 #endif
1524 void i915_gem_object_check_coherency(struct drm_i915_gem_object *obj,
1525                                      int handle);
1526 void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
1527                           const char *where, uint32_t mark);
1528
1529 /* i915_debugfs.c */
1530 int i915_debugfs_init(struct drm_minor *minor);
1531 void i915_debugfs_cleanup(struct drm_minor *minor);
1532
1533 /* i915_suspend.c */
1534 extern int i915_save_state(struct drm_device *dev);
1535 extern int i915_restore_state(struct drm_device *dev);
1536
1537 /* i915_suspend.c */
1538 extern int i915_save_state(struct drm_device *dev);
1539 extern int i915_restore_state(struct drm_device *dev);
1540
1541 /* i915_sysfs.c */
1542 void i915_setup_sysfs(struct drm_device *dev_priv);
1543 void i915_teardown_sysfs(struct drm_device *dev_priv);
1544
1545 /* intel_i2c.c */
1546 extern int intel_setup_gmbus(struct drm_device *dev);
1547 extern void intel_teardown_gmbus(struct drm_device *dev);
1548 extern inline bool intel_gmbus_is_port_valid(unsigned port)
1549 {
1550         return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD);
1551 }
1552
1553 extern struct i2c_adapter *intel_gmbus_get_adapter(
1554                 struct drm_i915_private *dev_priv, unsigned port);
1555 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
1556 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
1557 extern inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
1558 {
1559         return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
1560 }
1561 extern void intel_i2c_reset(struct drm_device *dev);
1562
1563 /* intel_opregion.c */
1564 extern int intel_opregion_setup(struct drm_device *dev);
1565 #ifdef CONFIG_ACPI
1566 extern void intel_opregion_init(struct drm_device *dev);
1567 extern void intel_opregion_fini(struct drm_device *dev);
1568 extern void intel_opregion_asle_intr(struct drm_device *dev);
1569 extern void intel_opregion_gse_intr(struct drm_device *dev);
1570 extern void intel_opregion_enable_asle(struct drm_device *dev);
1571 #else
1572 static inline void intel_opregion_init(struct drm_device *dev) { return; }
1573 static inline void intel_opregion_fini(struct drm_device *dev) { return; }
1574 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
1575 static inline void intel_opregion_gse_intr(struct drm_device *dev) { return; }
1576 static inline void intel_opregion_enable_asle(struct drm_device *dev) { return; }
1577 #endif
1578
1579 /* intel_acpi.c */
1580 #ifdef CONFIG_ACPI
1581 extern void intel_register_dsm_handler(void);
1582 extern void intel_unregister_dsm_handler(void);
1583 #else
1584 static inline void intel_register_dsm_handler(void) { return; }
1585 static inline void intel_unregister_dsm_handler(void) { return; }
1586 #endif /* CONFIG_ACPI */
1587
1588 /* modesetting */
1589 extern void intel_modeset_init_hw(struct drm_device *dev);
1590 extern void intel_modeset_init(struct drm_device *dev);
1591 extern void intel_modeset_gem_init(struct drm_device *dev);
1592 extern void intel_modeset_cleanup(struct drm_device *dev);
1593 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
1594 extern void intel_modeset_setup_hw_state(struct drm_device *dev);
1595 extern bool intel_fbc_enabled(struct drm_device *dev);
1596 extern void intel_disable_fbc(struct drm_device *dev);
1597 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
1598 extern void ironlake_init_pch_refclk(struct drm_device *dev);
1599 extern void gen6_set_rps(struct drm_device *dev, u8 val);
1600 extern void intel_detect_pch(struct drm_device *dev);
1601 extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
1602 extern int intel_enable_rc6(const struct drm_device *dev);
1603
1604 extern bool i915_semaphore_is_enabled(struct drm_device *dev);
1605 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
1606                         struct drm_file *file);
1607
1608 /* overlay */
1609 #ifdef CONFIG_DEBUG_FS
1610 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
1611 extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error);
1612
1613 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
1614 extern void intel_display_print_error_state(struct seq_file *m,
1615                                             struct drm_device *dev,
1616                                             struct intel_display_error_state *error);
1617 #endif
1618
1619 /* On SNB platform, before reading ring registers forcewake bit
1620  * must be set to prevent GT core from power down and stale values being
1621  * returned.
1622  */
1623 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);
1624 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);
1625 int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv);
1626
1627 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val);
1628 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val);
1629
1630 #define __i915_read(x, y) \
1631         u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg);
1632
1633 __i915_read(8, b)
1634 __i915_read(16, w)
1635 __i915_read(32, l)
1636 __i915_read(64, q)
1637 #undef __i915_read
1638
1639 #define __i915_write(x, y) \
1640         void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val);
1641
1642 __i915_write(8, b)
1643 __i915_write(16, w)
1644 __i915_write(32, l)
1645 __i915_write(64, q)
1646 #undef __i915_write
1647
1648 #define I915_READ8(reg)         i915_read8(dev_priv, (reg))
1649 #define I915_WRITE8(reg, val)   i915_write8(dev_priv, (reg), (val))
1650
1651 #define I915_READ16(reg)        i915_read16(dev_priv, (reg))
1652 #define I915_WRITE16(reg, val)  i915_write16(dev_priv, (reg), (val))
1653 #define I915_READ16_NOTRACE(reg)        readw(dev_priv->regs + (reg))
1654 #define I915_WRITE16_NOTRACE(reg, val)  writew(val, dev_priv->regs + (reg))
1655
1656 #define I915_READ(reg)          i915_read32(dev_priv, (reg))
1657 #define I915_WRITE(reg, val)    i915_write32(dev_priv, (reg), (val))
1658 #define I915_READ_NOTRACE(reg)          readl(dev_priv->regs + (reg))
1659 #define I915_WRITE_NOTRACE(reg, val)    writel(val, dev_priv->regs + (reg))
1660
1661 #define I915_WRITE64(reg, val)  i915_write64(dev_priv, (reg), (val))
1662 #define I915_READ64(reg)        i915_read64(dev_priv, (reg))
1663
1664 #define POSTING_READ(reg)       (void)I915_READ_NOTRACE(reg)
1665 #define POSTING_READ16(reg)     (void)I915_READ16_NOTRACE(reg)
1666
1667
1668 #endif