1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
34 #include <uapi/drm/drm_fourcc.h>
37 #include "i915_params.h"
39 #include "intel_bios.h"
40 #include "intel_ringbuffer.h"
41 #include "intel_lrc.h"
42 #include "i915_gem_gtt.h"
43 #include "i915_gem_render_state.h"
44 #include <linux/io-mapping.h>
45 #include <linux/i2c.h>
46 #include <linux/i2c-algo-bit.h>
47 #include <drm/intel-gtt.h>
48 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
49 #include <drm/drm_gem.h>
50 #include <linux/backlight.h>
51 #include <linux/hashtable.h>
52 #include <linux/intel-iommu.h>
53 #include <linux/kref.h>
54 #include <linux/pm_qos.h>
55 #include "intel_guc.h"
56 #include "intel_dpll_mgr.h"
58 /* General customization:
61 #define DRIVER_NAME "i915"
62 #define DRIVER_DESC "Intel Graphics"
63 #define DRIVER_DATE "20160411"
66 /* Many gcc seem to no see through this and fall over :( */
68 #define WARN_ON(x) ({ \
69 bool __i915_warn_cond = (x); \
70 if (__builtin_constant_p(__i915_warn_cond)) \
71 BUILD_BUG_ON(__i915_warn_cond); \
72 WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
74 #define WARN_ON(x) WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
78 #define WARN_ON_ONCE(x) WARN_ONCE((x), "%s", "WARN_ON_ONCE(" __stringify(x) ")")
80 #define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
81 (long) (x), __func__);
83 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
84 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
85 * which may not necessarily be a user visible problem. This will either
86 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
87 * enable distros and users to tailor their preferred amount of i915 abrt
90 #define I915_STATE_WARN(condition, format...) ({ \
91 int __ret_warn_on = !!(condition); \
92 if (unlikely(__ret_warn_on)) \
93 if (!WARN(i915.verbose_state_checks, format)) \
95 unlikely(__ret_warn_on); \
98 #define I915_STATE_WARN_ON(x) \
99 I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
101 bool __i915_inject_load_failure(const char *func
, int line
);
102 #define i915_inject_load_failure() \
103 __i915_inject_load_failure(__func__, __LINE__)
105 static inline const char *yesno(bool v
)
107 return v
? "yes" : "no";
110 static inline const char *onoff(bool v
)
112 return v
? "on" : "off";
121 I915_MAX_PIPES
= _PIPE_EDP
123 #define pipe_name(p) ((p) + 'A')
135 static inline const char *transcoder_name(enum transcoder transcoder
)
137 switch (transcoder
) {
146 case TRANSCODER_DSI_A
:
148 case TRANSCODER_DSI_C
:
155 static inline bool transcoder_is_dsi(enum transcoder transcoder
)
157 return transcoder
== TRANSCODER_DSI_A
|| transcoder
== TRANSCODER_DSI_C
;
161 * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
162 * number of planes per CRTC. Not all platforms really have this many planes,
163 * which means some arrays of size I915_MAX_PLANES may have unused entries
164 * between the topmost sprite plane and the cursor plane.
173 #define plane_name(p) ((p) + 'A')
175 #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
185 #define port_name(p) ((p) + 'A')
187 #define I915_NUM_PHYS_VLV 2
199 enum intel_display_power_domain
{
203 POWER_DOMAIN_PIPE_A_PANEL_FITTER
,
204 POWER_DOMAIN_PIPE_B_PANEL_FITTER
,
205 POWER_DOMAIN_PIPE_C_PANEL_FITTER
,
206 POWER_DOMAIN_TRANSCODER_A
,
207 POWER_DOMAIN_TRANSCODER_B
,
208 POWER_DOMAIN_TRANSCODER_C
,
209 POWER_DOMAIN_TRANSCODER_EDP
,
210 POWER_DOMAIN_TRANSCODER_DSI_A
,
211 POWER_DOMAIN_TRANSCODER_DSI_C
,
212 POWER_DOMAIN_PORT_DDI_A_LANES
,
213 POWER_DOMAIN_PORT_DDI_B_LANES
,
214 POWER_DOMAIN_PORT_DDI_C_LANES
,
215 POWER_DOMAIN_PORT_DDI_D_LANES
,
216 POWER_DOMAIN_PORT_DDI_E_LANES
,
217 POWER_DOMAIN_PORT_DSI
,
218 POWER_DOMAIN_PORT_CRT
,
219 POWER_DOMAIN_PORT_OTHER
,
228 POWER_DOMAIN_MODESET
,
234 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
235 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
236 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
237 #define POWER_DOMAIN_TRANSCODER(tran) \
238 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
239 (tran) + POWER_DOMAIN_TRANSCODER_A)
243 HPD_TV
= HPD_NONE
, /* TV is known to be unreliable */
255 #define for_each_hpd_pin(__pin) \
256 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
258 struct i915_hotplug
{
259 struct work_struct hotplug_work
;
262 unsigned long last_jiffies
;
267 HPD_MARK_DISABLED
= 2
269 } stats
[HPD_NUM_PINS
];
271 struct delayed_work reenable_work
;
273 struct intel_digital_port
*irq_port
[I915_MAX_PORTS
];
276 struct work_struct dig_port_work
;
279 * if we get a HPD irq from DP and a HPD irq from non-DP
280 * the non-DP HPD could block the workqueue on a mode config
281 * mutex getting, that userspace may have taken. However
282 * userspace is waiting on the DP workqueue to run which is
283 * blocked behind the non-DP one.
285 struct workqueue_struct
*dp_wq
;
288 #define I915_GEM_GPU_DOMAINS \
289 (I915_GEM_DOMAIN_RENDER | \
290 I915_GEM_DOMAIN_SAMPLER | \
291 I915_GEM_DOMAIN_COMMAND | \
292 I915_GEM_DOMAIN_INSTRUCTION | \
293 I915_GEM_DOMAIN_VERTEX)
295 #define for_each_pipe(__dev_priv, __p) \
296 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
297 #define for_each_pipe_masked(__dev_priv, __p, __mask) \
298 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \
299 for_each_if ((__mask) & (1 << (__p)))
300 #define for_each_plane(__dev_priv, __pipe, __p) \
302 (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
304 #define for_each_sprite(__dev_priv, __p, __s) \
306 (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \
309 #define for_each_port_masked(__port, __ports_mask) \
310 for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) \
311 for_each_if ((__ports_mask) & (1 << (__port)))
313 #define for_each_crtc(dev, crtc) \
314 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
316 #define for_each_intel_plane(dev, intel_plane) \
317 list_for_each_entry(intel_plane, \
318 &dev->mode_config.plane_list, \
321 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
322 list_for_each_entry(intel_plane, \
323 &(dev)->mode_config.plane_list, \
325 for_each_if ((intel_plane)->pipe == (intel_crtc)->pipe)
327 #define for_each_intel_crtc(dev, intel_crtc) \
328 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)
330 #define for_each_intel_encoder(dev, intel_encoder) \
331 list_for_each_entry(intel_encoder, \
332 &(dev)->mode_config.encoder_list, \
335 #define for_each_intel_connector(dev, intel_connector) \
336 list_for_each_entry(intel_connector, \
337 &dev->mode_config.connector_list, \
340 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
341 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
342 for_each_if ((intel_encoder)->base.crtc == (__crtc))
344 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
345 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
346 for_each_if ((intel_connector)->base.encoder == (__encoder))
348 #define for_each_power_domain(domain, mask) \
349 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
350 for_each_if ((1 << (domain)) & (mask))
352 struct drm_i915_private
;
353 struct i915_mm_struct
;
354 struct i915_mmu_object
;
356 struct drm_i915_file_private
{
357 struct drm_i915_private
*dev_priv
;
358 struct drm_file
*file
;
362 struct list_head request_list
;
363 /* 20ms is a fairly arbitrary limit (greater than the average frame time)
364 * chosen to prevent the CPU getting more than a frame ahead of the GPU
365 * (when using lax throttling for the frontbuffer). We also use it to
366 * offer free GPU waitboosts for severely congested workloads.
368 #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
370 struct idr context_idr
;
372 struct intel_rps_client
{
373 struct list_head link
;
377 unsigned int bsd_ring
;
380 /* Used by dp and fdi links */
381 struct intel_link_m_n
{
389 void intel_link_compute_m_n(int bpp
, int nlanes
,
390 int pixel_clock
, int link_clock
,
391 struct intel_link_m_n
*m_n
);
393 /* Interface history:
396 * 1.2: Add Power Management
397 * 1.3: Add vblank support
398 * 1.4: Fix cmdbuffer path, add heap destroy
399 * 1.5: Add vblank pipe configuration
400 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
401 * - Support vertical blank on secondary display pipe
403 #define DRIVER_MAJOR 1
404 #define DRIVER_MINOR 6
405 #define DRIVER_PATCHLEVEL 0
407 #define WATCH_LISTS 0
409 struct opregion_header
;
410 struct opregion_acpi
;
411 struct opregion_swsci
;
412 struct opregion_asle
;
414 struct intel_opregion
{
415 struct opregion_header
*header
;
416 struct opregion_acpi
*acpi
;
417 struct opregion_swsci
*swsci
;
418 u32 swsci_gbda_sub_functions
;
419 u32 swsci_sbcb_sub_functions
;
420 struct opregion_asle
*asle
;
425 struct work_struct asle_work
;
427 #define OPREGION_SIZE (8*1024)
429 struct intel_overlay
;
430 struct intel_overlay_error_state
;
432 #define I915_FENCE_REG_NONE -1
433 #define I915_MAX_NUM_FENCES 32
434 /* 32 fences + sign bit for FENCE_REG_NONE */
435 #define I915_MAX_NUM_FENCE_BITS 6
437 struct drm_i915_fence_reg
{
438 struct list_head lru_list
;
439 struct drm_i915_gem_object
*obj
;
443 struct sdvo_device_mapping
{
452 struct intel_display_error_state
;
454 struct drm_i915_error_state
{
463 /* Generic register state */
471 u32 error
; /* gen6+ */
472 u32 err_int
; /* gen7 */
473 u32 fault_data0
; /* gen8, gen9 */
474 u32 fault_data1
; /* gen8, gen9 */
480 u32 extra_instdone
[I915_NUM_INSTDONE_REG
];
481 u64 fence
[I915_MAX_NUM_FENCES
];
482 struct intel_overlay_error_state
*overlay
;
483 struct intel_display_error_state
*display
;
484 struct drm_i915_error_object
*semaphore_obj
;
486 struct drm_i915_error_ring
{
488 /* Software tracked state */
491 enum intel_ring_hangcheck_action hangcheck_action
;
494 /* our own tracking of ring head and tail */
499 u32 semaphore_seqno
[I915_NUM_ENGINES
- 1];
518 u32 rc_psmi
; /* sleep state */
519 u32 semaphore_mboxes
[I915_NUM_ENGINES
- 1];
521 struct drm_i915_error_object
{
525 } *ringbuffer
, *batchbuffer
, *wa_batchbuffer
, *ctx
, *hws_page
;
527 struct drm_i915_error_object
*wa_ctx
;
529 struct drm_i915_error_request
{
544 char comm
[TASK_COMM_LEN
];
545 } ring
[I915_NUM_ENGINES
];
547 struct drm_i915_error_buffer
{
550 u32 rseqno
[I915_NUM_ENGINES
], wseqno
;
554 s32 fence_reg
:I915_MAX_NUM_FENCE_BITS
;
562 } **active_bo
, **pinned_bo
;
564 u32
*active_bo_count
, *pinned_bo_count
;
568 struct intel_connector
;
569 struct intel_encoder
;
570 struct intel_crtc_state
;
571 struct intel_initial_plane_config
;
576 struct drm_i915_display_funcs
{
577 int (*get_display_clock_speed
)(struct drm_device
*dev
);
578 int (*get_fifo_size
)(struct drm_device
*dev
, int plane
);
579 int (*compute_pipe_wm
)(struct intel_crtc_state
*cstate
);
580 int (*compute_intermediate_wm
)(struct drm_device
*dev
,
581 struct intel_crtc
*intel_crtc
,
582 struct intel_crtc_state
*newstate
);
583 void (*initial_watermarks
)(struct intel_crtc_state
*cstate
);
584 void (*optimize_watermarks
)(struct intel_crtc_state
*cstate
);
585 void (*update_wm
)(struct drm_crtc
*crtc
);
586 int (*modeset_calc_cdclk
)(struct drm_atomic_state
*state
);
587 void (*modeset_commit_cdclk
)(struct drm_atomic_state
*state
);
588 /* Returns the active state of the crtc, and if the crtc is active,
589 * fills out the pipe-config with the hw state. */
590 bool (*get_pipe_config
)(struct intel_crtc
*,
591 struct intel_crtc_state
*);
592 void (*get_initial_plane_config
)(struct intel_crtc
*,
593 struct intel_initial_plane_config
*);
594 int (*crtc_compute_clock
)(struct intel_crtc
*crtc
,
595 struct intel_crtc_state
*crtc_state
);
596 void (*crtc_enable
)(struct drm_crtc
*crtc
);
597 void (*crtc_disable
)(struct drm_crtc
*crtc
);
598 void (*audio_codec_enable
)(struct drm_connector
*connector
,
599 struct intel_encoder
*encoder
,
600 const struct drm_display_mode
*adjusted_mode
);
601 void (*audio_codec_disable
)(struct intel_encoder
*encoder
);
602 void (*fdi_link_train
)(struct drm_crtc
*crtc
);
603 void (*init_clock_gating
)(struct drm_device
*dev
);
604 int (*queue_flip
)(struct drm_device
*dev
, struct drm_crtc
*crtc
,
605 struct drm_framebuffer
*fb
,
606 struct drm_i915_gem_object
*obj
,
607 struct drm_i915_gem_request
*req
,
609 void (*hpd_irq_setup
)(struct drm_device
*dev
);
610 /* clock updates for mode set */
612 /* render clock increase/decrease */
613 /* display clock increase/decrease */
614 /* pll clock increase/decrease */
616 void (*load_csc_matrix
)(struct drm_crtc_state
*crtc_state
);
617 void (*load_luts
)(struct drm_crtc_state
*crtc_state
);
620 enum forcewake_domain_id
{
621 FW_DOMAIN_ID_RENDER
= 0,
622 FW_DOMAIN_ID_BLITTER
,
628 enum forcewake_domains
{
629 FORCEWAKE_RENDER
= (1 << FW_DOMAIN_ID_RENDER
),
630 FORCEWAKE_BLITTER
= (1 << FW_DOMAIN_ID_BLITTER
),
631 FORCEWAKE_MEDIA
= (1 << FW_DOMAIN_ID_MEDIA
),
632 FORCEWAKE_ALL
= (FORCEWAKE_RENDER
|
637 struct intel_uncore_funcs
{
638 void (*force_wake_get
)(struct drm_i915_private
*dev_priv
,
639 enum forcewake_domains domains
);
640 void (*force_wake_put
)(struct drm_i915_private
*dev_priv
,
641 enum forcewake_domains domains
);
643 uint8_t (*mmio_readb
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
, bool trace
);
644 uint16_t (*mmio_readw
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
, bool trace
);
645 uint32_t (*mmio_readl
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
, bool trace
);
646 uint64_t (*mmio_readq
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
, bool trace
);
648 void (*mmio_writeb
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
,
649 uint8_t val
, bool trace
);
650 void (*mmio_writew
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
,
651 uint16_t val
, bool trace
);
652 void (*mmio_writel
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
,
653 uint32_t val
, bool trace
);
654 void (*mmio_writeq
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
,
655 uint64_t val
, bool trace
);
658 struct intel_uncore
{
659 spinlock_t lock
; /** lock is also taken in irq contexts. */
661 struct intel_uncore_funcs funcs
;
664 enum forcewake_domains fw_domains
;
666 struct intel_uncore_forcewake_domain
{
667 struct drm_i915_private
*i915
;
668 enum forcewake_domain_id id
;
670 struct timer_list timer
;
677 } fw_domain
[FW_DOMAIN_ID_COUNT
];
679 int unclaimed_mmio_check
;
682 /* Iterate over initialised fw domains */
683 #define for_each_fw_domain_mask(domain__, mask__, dev_priv__, i__) \
684 for ((i__) = 0, (domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
685 (i__) < FW_DOMAIN_ID_COUNT; \
686 (i__)++, (domain__) = &(dev_priv__)->uncore.fw_domain[i__]) \
687 for_each_if (((mask__) & (dev_priv__)->uncore.fw_domains) & (1 << (i__)))
689 #define for_each_fw_domain(domain__, dev_priv__, i__) \
690 for_each_fw_domain_mask(domain__, FORCEWAKE_ALL, dev_priv__, i__)
692 #define CSR_VERSION(major, minor) ((major) << 16 | (minor))
693 #define CSR_VERSION_MAJOR(version) ((version) >> 16)
694 #define CSR_VERSION_MINOR(version) ((version) & 0xffff)
697 struct work_struct work
;
699 uint32_t *dmc_payload
;
700 uint32_t dmc_fw_size
;
703 i915_reg_t mmioaddr
[8];
704 uint32_t mmiodata
[8];
706 uint32_t allowed_dc_mask
;
709 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
710 func(is_mobile) sep \
713 func(is_i945gm) sep \
715 func(need_gfx_hws) sep \
717 func(is_pineview) sep \
718 func(is_broadwater) sep \
719 func(is_crestline) sep \
720 func(is_ivybridge) sep \
721 func(is_valleyview) sep \
722 func(is_cherryview) sep \
723 func(is_haswell) sep \
724 func(is_skylake) sep \
725 func(is_broxton) sep \
726 func(is_kabylake) sep \
727 func(is_preliminary) sep \
729 func(has_pipe_cxsr) sep \
730 func(has_hotplug) sep \
731 func(cursor_needs_physical) sep \
732 func(has_overlay) sep \
733 func(overlay_needs_physical) sep \
734 func(supports_tv) sep \
736 func(has_snoop) sep \
740 #define DEFINE_FLAG(name) u8 name:1
741 #define SEP_SEMICOLON ;
743 struct intel_device_info
{
744 u32 display_mmio_offset
;
747 u8 num_sprites
[I915_MAX_PIPES
];
749 u8 ring_mask
; /* Rings supported by the HW */
750 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG
, SEP_SEMICOLON
);
751 /* Register offsets for the various display pipes and transcoders */
752 int pipe_offsets
[I915_MAX_TRANSCODERS
];
753 int trans_offsets
[I915_MAX_TRANSCODERS
];
754 int palette_offsets
[I915_MAX_PIPES
];
755 int cursor_offsets
[I915_MAX_PIPES
];
757 /* Slice/subslice/EU info */
760 u8 subslice_per_slice
;
763 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
766 u8 has_subslice_pg
:1;
770 u16 degamma_lut_size
;
778 enum i915_cache_level
{
780 I915_CACHE_LLC
, /* also used for snoopable memory on non-LLC */
781 I915_CACHE_L3_LLC
, /* gen7+, L3 sits between the domain specifc
782 caches, eg sampler/render caches, and the
783 large Last-Level-Cache. LLC is coherent with
784 the CPU, but L3 is only visible to the GPU. */
785 I915_CACHE_WT
, /* hsw:gt3e WriteThrough for scanouts */
788 struct i915_ctx_hang_stats
{
789 /* This context had batch pending when hang was declared */
790 unsigned batch_pending
;
792 /* This context had batch active when hang was declared */
793 unsigned batch_active
;
795 /* Time when this context was last blamed for a GPU reset */
796 unsigned long guilty_ts
;
798 /* If the contexts causes a second GPU hang within this time,
799 * it is permanently banned from submitting any more work.
801 unsigned long ban_period_seconds
;
803 /* This context is banned to submit more work */
807 /* This must match up with the value previously used for execbuf2.rsvd1. */
808 #define DEFAULT_CONTEXT_HANDLE 0
810 #define CONTEXT_NO_ZEROMAP (1<<0)
812 * struct intel_context - as the name implies, represents a context.
813 * @ref: reference count.
814 * @user_handle: userspace tracking identity for this context.
815 * @remap_slice: l3 row remapping information.
816 * @flags: context specific flags:
817 * CONTEXT_NO_ZEROMAP: do not allow mapping things to page 0.
818 * @file_priv: filp associated with this context (NULL for global default
820 * @hang_stats: information about the role of this context in possible GPU
822 * @ppgtt: virtual memory space used by this context.
823 * @legacy_hw_ctx: render context backing object and whether it is correctly
824 * initialized (legacy ring submission mechanism only).
825 * @link: link in the global list of contexts.
827 * Contexts are memory images used by the hardware to store copies of their
830 struct intel_context
{
834 struct drm_i915_private
*i915
;
836 struct drm_i915_file_private
*file_priv
;
837 struct i915_ctx_hang_stats hang_stats
;
838 struct i915_hw_ppgtt
*ppgtt
;
840 /* Legacy ring buffer submission */
842 struct drm_i915_gem_object
*rcs_state
;
848 struct drm_i915_gem_object
*state
;
849 struct intel_ringbuffer
*ringbuf
;
851 struct i915_vma
*lrc_vma
;
853 uint32_t *lrc_reg_state
;
854 } engine
[I915_NUM_ENGINES
];
856 struct list_head link
;
868 /* This is always the inner lock when overlapping with struct_mutex and
869 * it's the outer lock when overlapping with stolen_lock. */
872 unsigned int possible_framebuffer_bits
;
873 unsigned int busy_bits
;
874 unsigned int visible_pipes_mask
;
875 struct intel_crtc
*crtc
;
877 struct drm_mm_node compressed_fb
;
878 struct drm_mm_node
*compressed_llb
;
885 struct intel_fbc_state_cache
{
887 unsigned int mode_flags
;
888 uint32_t hsw_bdw_pixel_rate
;
892 unsigned int rotation
;
900 uint32_t pixel_format
;
903 unsigned int tiling_mode
;
907 struct intel_fbc_reg_params
{
911 unsigned int fence_y_offset
;
916 uint32_t pixel_format
;
924 struct intel_fbc_work
{
926 u32 scheduled_vblank
;
927 struct work_struct work
;
930 const char *no_fbc_reason
;
934 * HIGH_RR is the highest eDP panel refresh rate read from EDID
935 * LOW_RR is the lowest eDP panel refresh rate found from EDID
936 * parsing for same resolution.
938 enum drrs_refresh_rate_type
{
941 DRRS_MAX_RR
, /* RR count */
944 enum drrs_support_type
{
945 DRRS_NOT_SUPPORTED
= 0,
946 STATIC_DRRS_SUPPORT
= 1,
947 SEAMLESS_DRRS_SUPPORT
= 2
953 struct delayed_work work
;
955 unsigned busy_frontbuffer_bits
;
956 enum drrs_refresh_rate_type refresh_rate_type
;
957 enum drrs_support_type type
;
964 struct intel_dp
*enabled
;
966 struct delayed_work work
;
967 unsigned busy_frontbuffer_bits
;
974 PCH_NONE
= 0, /* No PCH present */
975 PCH_IBX
, /* Ibexpeak PCH */
976 PCH_CPT
, /* Cougarpoint PCH */
977 PCH_LPT
, /* Lynxpoint PCH */
978 PCH_SPT
, /* Sunrisepoint PCH */
982 enum intel_sbi_destination
{
987 #define QUIRK_PIPEA_FORCE (1<<0)
988 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
989 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
990 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
991 #define QUIRK_PIPEB_FORCE (1<<4)
992 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
995 struct intel_fbc_work
;
998 struct i2c_adapter adapter
;
999 #define GMBUS_FORCE_BIT_RETRY (1U << 31)
1002 i915_reg_t gpio_reg
;
1003 struct i2c_algo_bit_data bit_algo
;
1004 struct drm_i915_private
*dev_priv
;
1007 struct i915_suspend_saved_registers
{
1010 u32 savePP_ON_DELAYS
;
1011 u32 savePP_OFF_DELAYS
;
1016 u32 saveFBC_CONTROL
;
1017 u32 saveCACHE_MODE_0
;
1018 u32 saveMI_ARB_STATE
;
1022 uint64_t saveFENCE
[I915_MAX_NUM_FENCES
];
1023 u32 savePCH_PORT_HOTPLUG
;
1027 struct vlv_s0ix_state
{
1034 u32 lra_limits
[GEN7_LRA_LIMITS_REG_NUM
];
1035 u32 media_max_req_count
;
1036 u32 gfx_max_req_count
;
1062 u32 rp_down_timeout
;
1068 /* Display 1 CZ domain */
1073 u32 gt_scratch
[GEN7_GT_SCRATCH_REG_NUM
];
1075 /* GT SA CZ domain */
1082 /* Display 2 CZ domain */
1086 u32 clock_gate_dis2
;
1089 struct intel_rps_ei
{
1095 struct intel_gen6_power_mgmt
{
1097 * work, interrupts_enabled and pm_iir are protected by
1098 * dev_priv->irq_lock
1100 struct work_struct work
;
1101 bool interrupts_enabled
;
1104 /* Frequencies are stored in potentially platform dependent multiples.
1105 * In other words, *_freq needs to be multiplied by X to be interesting.
1106 * Soft limits are those which are used for the dynamic reclocking done
1107 * by the driver (raise frequencies under heavy loads, and lower for
1108 * lighter loads). Hard limits are those imposed by the hardware.
1110 * A distinction is made for overclocking, which is never enabled by
1111 * default, and is considered to be above the hard limit if it's
1114 u8 cur_freq
; /* Current frequency (cached, may not == HW) */
1115 u8 min_freq_softlimit
; /* Minimum frequency permitted by the driver */
1116 u8 max_freq_softlimit
; /* Max frequency permitted by the driver */
1117 u8 max_freq
; /* Maximum frequency, RP0 if not overclocking */
1118 u8 min_freq
; /* AKA RPn. Minimum frequency */
1119 u8 idle_freq
; /* Frequency to request when we are idle */
1120 u8 efficient_freq
; /* AKA RPe. Pre-determined balanced frequency */
1121 u8 rp1_freq
; /* "less than" RP0 power/freqency */
1122 u8 rp0_freq
; /* Non-overclocked max frequency. */
1123 u16 gpll_ref_freq
; /* vlv/chv GPLL reference frequency */
1125 u8 up_threshold
; /* Current %busy required to uplock */
1126 u8 down_threshold
; /* Current %busy required to downclock */
1129 enum { LOW_POWER
, BETWEEN
, HIGH_POWER
} power
;
1131 spinlock_t client_lock
;
1132 struct list_head clients
;
1136 struct delayed_work delayed_resume_work
;
1139 struct intel_rps_client semaphores
, mmioflips
;
1141 /* manual wa residency calculations */
1142 struct intel_rps_ei up_ei
, down_ei
;
1145 * Protects RPS/RC6 register access and PCU communication.
1146 * Must be taken after struct_mutex if nested. Note that
1147 * this lock may be held for long periods of time when
1148 * talking to hw - so only take it when talking to hw!
1150 struct mutex hw_lock
;
1153 /* defined intel_pm.c */
1154 extern spinlock_t mchdev_lock
;
1156 struct intel_ilk_power_mgmt
{
1164 unsigned long last_time1
;
1165 unsigned long chipset_power
;
1168 unsigned long gfx_power
;
1175 struct drm_i915_private
;
1176 struct i915_power_well
;
1178 struct i915_power_well_ops
{
1180 * Synchronize the well's hw state to match the current sw state, for
1181 * example enable/disable it based on the current refcount. Called
1182 * during driver init and resume time, possibly after first calling
1183 * the enable/disable handlers.
1185 void (*sync_hw
)(struct drm_i915_private
*dev_priv
,
1186 struct i915_power_well
*power_well
);
1188 * Enable the well and resources that depend on it (for example
1189 * interrupts located on the well). Called after the 0->1 refcount
1192 void (*enable
)(struct drm_i915_private
*dev_priv
,
1193 struct i915_power_well
*power_well
);
1195 * Disable the well and resources that depend on it. Called after
1196 * the 1->0 refcount transition.
1198 void (*disable
)(struct drm_i915_private
*dev_priv
,
1199 struct i915_power_well
*power_well
);
1200 /* Returns the hw enabled state. */
1201 bool (*is_enabled
)(struct drm_i915_private
*dev_priv
,
1202 struct i915_power_well
*power_well
);
1205 /* Power well structure for haswell */
1206 struct i915_power_well
{
1209 /* power well enable/disable usage count */
1211 /* cached hw enabled state */
1213 unsigned long domains
;
1215 const struct i915_power_well_ops
*ops
;
1218 struct i915_power_domains
{
1220 * Power wells needed for initialization at driver init and suspend
1221 * time are on. They are kept on until after the first modeset.
1225 int power_well_count
;
1228 int domain_use_count
[POWER_DOMAIN_NUM
];
1229 struct i915_power_well
*power_wells
;
1232 #define MAX_L3_SLICES 2
1233 struct intel_l3_parity
{
1234 u32
*remap_info
[MAX_L3_SLICES
];
1235 struct work_struct error_work
;
1239 struct i915_gem_mm
{
1240 /** Memory allocator for GTT stolen memory */
1241 struct drm_mm stolen
;
1242 /** Protects the usage of the GTT stolen memory allocator. This is
1243 * always the inner lock when overlapping with struct_mutex. */
1244 struct mutex stolen_lock
;
1246 /** List of all objects in gtt_space. Used to restore gtt
1247 * mappings on resume */
1248 struct list_head bound_list
;
1250 * List of objects which are not bound to the GTT (thus
1251 * are idle and not used by the GPU) but still have
1252 * (presumably uncached) pages still attached.
1254 struct list_head unbound_list
;
1256 /** Usable portion of the GTT for GEM */
1257 unsigned long stolen_base
; /* limited to low memory (32-bit) */
1259 /** PPGTT used for aliasing the PPGTT with the GTT */
1260 struct i915_hw_ppgtt
*aliasing_ppgtt
;
1262 struct notifier_block oom_notifier
;
1263 struct notifier_block vmap_notifier
;
1264 struct shrinker shrinker
;
1265 bool shrinker_no_lock_stealing
;
1267 /** LRU list of objects with fence regs on them. */
1268 struct list_head fence_list
;
1271 * We leave the user IRQ off as much as possible,
1272 * but this means that requests will finish and never
1273 * be retired once the system goes idle. Set a timer to
1274 * fire periodically while the ring is running. When it
1275 * fires, go retire requests.
1277 struct delayed_work retire_work
;
1280 * When we detect an idle GPU, we want to turn on
1281 * powersaving features. So once we see that there
1282 * are no more requests outstanding and no more
1283 * arrive within a small period of time, we fire
1284 * off the idle_work.
1286 struct delayed_work idle_work
;
1289 * Are we in a non-interruptible section of code like
1295 * Is the GPU currently considered idle, or busy executing userspace
1296 * requests? Whilst idle, we attempt to power down the hardware and
1297 * display clocks. In order to reduce the effect on performance, there
1298 * is a slight delay before we do so.
1302 /* the indicator for dispatch video commands on two BSD rings */
1303 unsigned int bsd_ring_dispatch_index
;
1305 /** Bit 6 swizzling required for X tiling */
1306 uint32_t bit_6_swizzle_x
;
1307 /** Bit 6 swizzling required for Y tiling */
1308 uint32_t bit_6_swizzle_y
;
1310 /* accounting, useful for userland debugging */
1311 spinlock_t object_stat_lock
;
1312 size_t object_memory
;
1316 struct drm_i915_error_state_buf
{
1317 struct drm_i915_private
*i915
;
1326 struct i915_error_state_file_priv
{
1327 struct drm_device
*dev
;
1328 struct drm_i915_error_state
*error
;
1331 struct i915_gpu_error
{
1332 /* For hangcheck timer */
1333 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1334 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1335 /* Hang gpu twice in this window and your context gets banned */
1336 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1338 struct workqueue_struct
*hangcheck_wq
;
1339 struct delayed_work hangcheck_work
;
1341 /* For reset and error_state handling. */
1343 /* Protected by the above dev->gpu_error.lock. */
1344 struct drm_i915_error_state
*first_error
;
1346 unsigned long missed_irq_rings
;
1349 * State variable controlling the reset flow and count
1351 * This is a counter which gets incremented when reset is triggered,
1352 * and again when reset has been handled. So odd values (lowest bit set)
1353 * means that reset is in progress and even values that
1354 * (reset_counter >> 1):th reset was successfully completed.
1356 * If reset is not completed succesfully, the I915_WEDGE bit is
1357 * set meaning that hardware is terminally sour and there is no
1358 * recovery. All waiters on the reset_queue will be woken when
1361 * This counter is used by the wait_seqno code to notice that reset
1362 * event happened and it needs to restart the entire ioctl (since most
1363 * likely the seqno it waited for won't ever signal anytime soon).
1365 * This is important for lock-free wait paths, where no contended lock
1366 * naturally enforces the correct ordering between the bail-out of the
1367 * waiter and the gpu reset work code.
1369 atomic_t reset_counter
;
1371 #define I915_RESET_IN_PROGRESS_FLAG 1
1372 #define I915_WEDGED (1 << 31)
1375 * Waitqueue to signal when the reset has completed. Used by clients
1376 * that wait for dev_priv->mm.wedged to settle.
1378 wait_queue_head_t reset_queue
;
1380 /* Userspace knobs for gpu hang simulation;
1381 * combines both a ring mask, and extra flags
1384 #define I915_STOP_RING_ALLOW_BAN (1 << 31)
1385 #define I915_STOP_RING_ALLOW_WARN (1 << 30)
1387 /* For missed irq/seqno simulation. */
1388 unsigned int test_irq_rings
;
1390 /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
1391 bool reload_in_reset
;
1394 enum modeset_restore
{
1395 MODESET_ON_LID_OPEN
,
1400 #define DP_AUX_A 0x40
1401 #define DP_AUX_B 0x10
1402 #define DP_AUX_C 0x20
1403 #define DP_AUX_D 0x30
1405 #define DDC_PIN_B 0x05
1406 #define DDC_PIN_C 0x04
1407 #define DDC_PIN_D 0x06
1409 struct ddi_vbt_port_info
{
1411 * This is an index in the HDMI/DVI DDI buffer translation table.
1412 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1413 * populate this field.
1415 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1416 uint8_t hdmi_level_shift
;
1418 uint8_t supports_dvi
:1;
1419 uint8_t supports_hdmi
:1;
1420 uint8_t supports_dp
:1;
1422 uint8_t alternate_aux_channel
;
1423 uint8_t alternate_ddc_pin
;
1425 uint8_t dp_boost_level
;
1426 uint8_t hdmi_boost_level
;
1429 enum psr_lines_to_wait
{
1430 PSR_0_LINES_TO_WAIT
= 0,
1432 PSR_4_LINES_TO_WAIT
,
1436 struct intel_vbt_data
{
1437 struct drm_display_mode
*lfp_lvds_vbt_mode
; /* if any */
1438 struct drm_display_mode
*sdvo_lvds_vbt_mode
; /* if any */
1441 unsigned int int_tv_support
:1;
1442 unsigned int lvds_dither
:1;
1443 unsigned int lvds_vbt
:1;
1444 unsigned int int_crt_support
:1;
1445 unsigned int lvds_use_ssc
:1;
1446 unsigned int display_clock_mode
:1;
1447 unsigned int fdi_rx_polarity_inverted
:1;
1448 unsigned int panel_type
:4;
1450 unsigned int bios_lvds_val
; /* initial [PCH_]LVDS reg val in VBIOS */
1452 enum drrs_support_type drrs_type
;
1463 struct edp_power_seq pps
;
1468 bool require_aux_wakeup
;
1470 enum psr_lines_to_wait lines_to_wait
;
1471 int tp1_wakeup_time
;
1472 int tp2_tp3_wakeup_time
;
1478 bool active_low_pwm
;
1479 u8 min_brightness
; /* min_brightness/255 of max */
1485 struct mipi_config
*config
;
1486 struct mipi_pps_data
*pps
;
1490 const u8
*sequence
[MIPI_SEQ_MAX
];
1496 union child_device_config
*child_dev
;
1498 struct ddi_vbt_port_info ddi_port_info
[I915_MAX_PORTS
];
1499 struct sdvo_device_mapping sdvo_mappings
[2];
1502 enum intel_ddb_partitioning
{
1504 INTEL_DDB_PART_5_6
, /* IVB+ */
1507 struct intel_wm_level
{
1515 struct ilk_wm_values
{
1516 uint32_t wm_pipe
[3];
1518 uint32_t wm_lp_spr
[3];
1519 uint32_t wm_linetime
[3];
1521 enum intel_ddb_partitioning partitioning
;
1524 struct vlv_pipe_wm
{
1535 struct vlv_wm_values
{
1536 struct vlv_pipe_wm pipe
[3];
1537 struct vlv_sr_wm sr
;
1547 struct skl_ddb_entry
{
1548 uint16_t start
, end
; /* in number of blocks, 'end' is exclusive */
1551 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry
*entry
)
1553 return entry
->end
- entry
->start
;
1556 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry
*e1
,
1557 const struct skl_ddb_entry
*e2
)
1559 if (e1
->start
== e2
->start
&& e1
->end
== e2
->end
)
1565 struct skl_ddb_allocation
{
1566 struct skl_ddb_entry pipe
[I915_MAX_PIPES
];
1567 struct skl_ddb_entry plane
[I915_MAX_PIPES
][I915_MAX_PLANES
]; /* packed/uv */
1568 struct skl_ddb_entry y_plane
[I915_MAX_PIPES
][I915_MAX_PLANES
];
1571 struct skl_wm_values
{
1572 bool dirty
[I915_MAX_PIPES
];
1573 struct skl_ddb_allocation ddb
;
1574 uint32_t wm_linetime
[I915_MAX_PIPES
];
1575 uint32_t plane
[I915_MAX_PIPES
][I915_MAX_PLANES
][8];
1576 uint32_t plane_trans
[I915_MAX_PIPES
][I915_MAX_PLANES
];
1579 struct skl_wm_level
{
1580 bool plane_en
[I915_MAX_PLANES
];
1581 uint16_t plane_res_b
[I915_MAX_PLANES
];
1582 uint8_t plane_res_l
[I915_MAX_PLANES
];
1586 * This struct helps tracking the state needed for runtime PM, which puts the
1587 * device in PCI D3 state. Notice that when this happens, nothing on the
1588 * graphics device works, even register access, so we don't get interrupts nor
1591 * Every piece of our code that needs to actually touch the hardware needs to
1592 * either call intel_runtime_pm_get or call intel_display_power_get with the
1593 * appropriate power domain.
1595 * Our driver uses the autosuspend delay feature, which means we'll only really
1596 * suspend if we stay with zero refcount for a certain amount of time. The
1597 * default value is currently very conservative (see intel_runtime_pm_enable), but
1598 * it can be changed with the standard runtime PM files from sysfs.
1600 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1601 * goes back to false exactly before we reenable the IRQs. We use this variable
1602 * to check if someone is trying to enable/disable IRQs while they're supposed
1603 * to be disabled. This shouldn't happen and we'll print some error messages in
1606 * For more, read the Documentation/power/runtime_pm.txt.
1608 struct i915_runtime_pm
{
1609 atomic_t wakeref_count
;
1610 atomic_t atomic_seq
;
1615 enum intel_pipe_crc_source
{
1616 INTEL_PIPE_CRC_SOURCE_NONE
,
1617 INTEL_PIPE_CRC_SOURCE_PLANE1
,
1618 INTEL_PIPE_CRC_SOURCE_PLANE2
,
1619 INTEL_PIPE_CRC_SOURCE_PF
,
1620 INTEL_PIPE_CRC_SOURCE_PIPE
,
1621 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1622 INTEL_PIPE_CRC_SOURCE_TV
,
1623 INTEL_PIPE_CRC_SOURCE_DP_B
,
1624 INTEL_PIPE_CRC_SOURCE_DP_C
,
1625 INTEL_PIPE_CRC_SOURCE_DP_D
,
1626 INTEL_PIPE_CRC_SOURCE_AUTO
,
1627 INTEL_PIPE_CRC_SOURCE_MAX
,
1630 struct intel_pipe_crc_entry
{
1635 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1636 struct intel_pipe_crc
{
1638 bool opened
; /* exclusive access to the result file */
1639 struct intel_pipe_crc_entry
*entries
;
1640 enum intel_pipe_crc_source source
;
1642 wait_queue_head_t wq
;
1645 struct i915_frontbuffer_tracking
{
1649 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1656 struct i915_wa_reg
{
1659 /* bitmask representing WA bits */
1664 * RING_MAX_NONPRIV_SLOTS is per-engine but at this point we are only
1665 * allowing it for RCS as we don't foresee any requirement of having
1666 * a whitelist for other engines. When it is really required for
1667 * other engines then the limit need to be increased.
1669 #define I915_MAX_WA_REGS (16 + RING_MAX_NONPRIV_SLOTS)
1671 struct i915_workarounds
{
1672 struct i915_wa_reg reg
[I915_MAX_WA_REGS
];
1674 u32 hw_whitelist_count
[I915_NUM_ENGINES
];
1677 struct i915_virtual_gpu
{
1681 struct i915_execbuffer_params
{
1682 struct drm_device
*dev
;
1683 struct drm_file
*file
;
1684 uint32_t dispatch_flags
;
1685 uint32_t args_batch_start_offset
;
1686 uint64_t batch_obj_vm_offset
;
1687 struct intel_engine_cs
*engine
;
1688 struct drm_i915_gem_object
*batch_obj
;
1689 struct intel_context
*ctx
;
1690 struct drm_i915_gem_request
*request
;
1693 /* used in computing the new watermarks state */
1694 struct intel_wm_config
{
1695 unsigned int num_pipes_active
;
1696 bool sprites_enabled
;
1697 bool sprites_scaled
;
1700 struct drm_i915_private
{
1701 struct drm_device
*dev
;
1702 struct kmem_cache
*objects
;
1703 struct kmem_cache
*vmas
;
1704 struct kmem_cache
*requests
;
1706 const struct intel_device_info info
;
1708 int relative_constants_mode
;
1712 struct intel_uncore uncore
;
1714 struct i915_virtual_gpu vgpu
;
1716 struct intel_guc guc
;
1718 struct intel_csr csr
;
1720 struct intel_gmbus gmbus
[GMBUS_NUM_PINS
];
1722 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1723 * controller on different i2c buses. */
1724 struct mutex gmbus_mutex
;
1727 * Base address of the gmbus and gpio block.
1729 uint32_t gpio_mmio_base
;
1731 /* MMIO base address for MIPI regs */
1732 uint32_t mipi_mmio_base
;
1734 uint32_t psr_mmio_base
;
1736 wait_queue_head_t gmbus_wait_queue
;
1738 struct pci_dev
*bridge_dev
;
1739 struct intel_engine_cs engine
[I915_NUM_ENGINES
];
1740 struct drm_i915_gem_object
*semaphore_obj
;
1741 uint32_t last_seqno
, next_seqno
;
1743 struct drm_dma_handle
*status_page_dmah
;
1744 struct resource mch_res
;
1746 /* protects the irq masks */
1747 spinlock_t irq_lock
;
1749 /* protects the mmio flip data */
1750 spinlock_t mmio_flip_lock
;
1752 bool display_irqs_enabled
;
1754 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1755 struct pm_qos_request pm_qos
;
1757 /* Sideband mailbox protection */
1758 struct mutex sb_lock
;
1760 /** Cached value of IMR to avoid reads in updating the bitfield */
1763 u32 de_irq_mask
[I915_MAX_PIPES
];
1768 u32 pipestat_irq_mask
[I915_MAX_PIPES
];
1770 struct i915_hotplug hotplug
;
1771 struct intel_fbc fbc
;
1772 struct i915_drrs drrs
;
1773 struct intel_opregion opregion
;
1774 struct intel_vbt_data vbt
;
1776 bool preserve_bios_swizzle
;
1779 struct intel_overlay
*overlay
;
1781 /* backlight registers and fields in struct intel_panel */
1782 struct mutex backlight_lock
;
1785 bool no_aux_handshake
;
1787 /* protects panel power sequencer state */
1788 struct mutex pps_mutex
;
1790 struct drm_i915_fence_reg fence_regs
[I915_MAX_NUM_FENCES
]; /* assume 965 */
1791 int num_fence_regs
; /* 8 on pre-965, 16 otherwise */
1793 unsigned int fsb_freq
, mem_freq
, is_ddr3
;
1794 unsigned int skl_boot_cdclk
;
1795 unsigned int cdclk_freq
, max_cdclk_freq
, atomic_cdclk_freq
;
1796 unsigned int max_dotclk_freq
;
1797 unsigned int rawclk_freq
;
1798 unsigned int hpll_freq
;
1799 unsigned int czclk_freq
;
1802 * wq - Driver workqueue for GEM.
1804 * NOTE: Work items scheduled here are not allowed to grab any modeset
1805 * locks, for otherwise the flushing done in the pageflip code will
1806 * result in deadlocks.
1808 struct workqueue_struct
*wq
;
1810 /* Display functions */
1811 struct drm_i915_display_funcs display
;
1813 /* PCH chipset type */
1814 enum intel_pch pch_type
;
1815 unsigned short pch_id
;
1817 unsigned long quirks
;
1819 enum modeset_restore modeset_restore
;
1820 struct mutex modeset_restore_lock
;
1821 struct drm_atomic_state
*modeset_restore_state
;
1823 struct list_head vm_list
; /* Global list of all address spaces */
1824 struct i915_ggtt ggtt
; /* VM representing the global address space */
1826 struct i915_gem_mm mm
;
1827 DECLARE_HASHTABLE(mm_structs
, 7);
1828 struct mutex mm_lock
;
1830 /* Kernel Modesetting */
1832 struct drm_crtc
*plane_to_crtc_mapping
[I915_MAX_PIPES
];
1833 struct drm_crtc
*pipe_to_crtc_mapping
[I915_MAX_PIPES
];
1834 wait_queue_head_t pending_flip_queue
;
1836 #ifdef CONFIG_DEBUG_FS
1837 struct intel_pipe_crc pipe_crc
[I915_MAX_PIPES
];
1840 /* dpll and cdclk state is protected by connection_mutex */
1841 int num_shared_dpll
;
1842 struct intel_shared_dpll shared_dplls
[I915_NUM_PLLS
];
1843 const struct intel_dpll_mgr
*dpll_mgr
;
1846 * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
1847 * Must be global rather than per dpll, because on some platforms
1848 * plls share registers.
1850 struct mutex dpll_lock
;
1852 unsigned int active_crtcs
;
1853 unsigned int min_pixclk
[I915_MAX_PIPES
];
1855 int dpio_phy_iosf_port
[I915_NUM_PHYS_VLV
];
1857 struct i915_workarounds workarounds
;
1859 struct i915_frontbuffer_tracking fb_tracking
;
1863 bool mchbar_need_disable
;
1865 struct intel_l3_parity l3_parity
;
1867 /* Cannot be determined by PCIID. You must always read a register. */
1870 /* gen6+ rps state */
1871 struct intel_gen6_power_mgmt rps
;
1873 /* ilk-only ips/rps state. Everything in here is protected by the global
1874 * mchdev_lock in intel_pm.c */
1875 struct intel_ilk_power_mgmt ips
;
1877 struct i915_power_domains power_domains
;
1879 struct i915_psr psr
;
1881 struct i915_gpu_error gpu_error
;
1883 struct drm_i915_gem_object
*vlv_pctx
;
1885 #ifdef CONFIG_DRM_FBDEV_EMULATION
1886 /* list of fbdev register on this device */
1887 struct intel_fbdev
*fbdev
;
1888 struct work_struct fbdev_suspend_work
;
1891 struct drm_property
*broadcast_rgb_property
;
1892 struct drm_property
*force_audio_property
;
1894 /* hda/i915 audio component */
1895 struct i915_audio_component
*audio_component
;
1896 bool audio_component_registered
;
1898 * av_mutex - mutex for audio/video sync
1901 struct mutex av_mutex
;
1903 uint32_t hw_context_size
;
1904 struct list_head context_list
;
1908 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
1909 u32 chv_phy_control
;
1911 * Shadows for CHV DPLL_MD regs to keep the state
1912 * checker somewhat working in the presence hardware
1913 * crappiness (can't read out DPLL_MD for pipes B & C).
1915 u32 chv_dpll_md
[I915_MAX_PIPES
];
1918 bool suspended_to_idle
;
1919 struct i915_suspend_saved_registers regfile
;
1920 struct vlv_s0ix_state vlv_s0ix_state
;
1924 * Raw watermark latency values:
1925 * in 0.1us units for WM0,
1926 * in 0.5us units for WM1+.
1929 uint16_t pri_latency
[5];
1931 uint16_t spr_latency
[5];
1933 uint16_t cur_latency
[5];
1935 * Raw watermark memory latency values
1936 * for SKL for all 8 levels
1939 uint16_t skl_latency
[8];
1941 /* Committed wm config */
1942 struct intel_wm_config config
;
1945 * The skl_wm_values structure is a bit too big for stack
1946 * allocation, so we keep the staging struct where we store
1947 * intermediate results here instead.
1949 struct skl_wm_values skl_results
;
1951 /* current hardware state */
1953 struct ilk_wm_values hw
;
1954 struct skl_wm_values skl_hw
;
1955 struct vlv_wm_values vlv
;
1961 * Should be held around atomic WM register writing; also
1962 * protects * intel_crtc->wm.active and
1963 * cstate->wm.need_postvbl_update.
1965 struct mutex wm_mutex
;
1968 struct i915_runtime_pm pm
;
1970 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
1972 int (*execbuf_submit
)(struct i915_execbuffer_params
*params
,
1973 struct drm_i915_gem_execbuffer2
*args
,
1974 struct list_head
*vmas
);
1975 int (*init_engines
)(struct drm_device
*dev
);
1976 void (*cleanup_engine
)(struct intel_engine_cs
*engine
);
1977 void (*stop_engine
)(struct intel_engine_cs
*engine
);
1980 struct intel_context
*kernel_context
;
1982 /* perform PHY state sanity checks? */
1983 bool chv_phy_assert
[2];
1985 struct intel_encoder
*dig_port_map
[I915_MAX_PORTS
];
1988 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
1989 * will be rejected. Instead look for a better place.
1993 static inline struct drm_i915_private
*to_i915(const struct drm_device
*dev
)
1995 return dev
->dev_private
;
1998 static inline struct drm_i915_private
*dev_to_i915(struct device
*dev
)
2000 return to_i915(dev_get_drvdata(dev
));
2003 static inline struct drm_i915_private
*guc_to_i915(struct intel_guc
*guc
)
2005 return container_of(guc
, struct drm_i915_private
, guc
);
2008 /* Simple iterator over all initialised engines */
2009 #define for_each_engine(engine__, dev_priv__) \
2010 for ((engine__) = &(dev_priv__)->engine[0]; \
2011 (engine__) < &(dev_priv__)->engine[I915_NUM_ENGINES]; \
2013 for_each_if (intel_engine_initialized(engine__))
2015 /* Iterator with engine_id */
2016 #define for_each_engine_id(engine__, dev_priv__, id__) \
2017 for ((engine__) = &(dev_priv__)->engine[0], (id__) = 0; \
2018 (engine__) < &(dev_priv__)->engine[I915_NUM_ENGINES]; \
2020 for_each_if (((id__) = (engine__)->id, \
2021 intel_engine_initialized(engine__)))
2023 /* Iterator over subset of engines selected by mask */
2024 #define for_each_engine_masked(engine__, dev_priv__, mask__) \
2025 for ((engine__) = &(dev_priv__)->engine[0]; \
2026 (engine__) < &(dev_priv__)->engine[I915_NUM_ENGINES]; \
2028 for_each_if (((mask__) & intel_engine_flag(engine__)) && \
2029 intel_engine_initialized(engine__))
2031 enum hdmi_force_audio
{
2032 HDMI_AUDIO_OFF_DVI
= -2, /* no aux data for HDMI-DVI converter */
2033 HDMI_AUDIO_OFF
, /* force turn off HDMI audio */
2034 HDMI_AUDIO_AUTO
, /* trust EDID */
2035 HDMI_AUDIO_ON
, /* force turn on HDMI audio */
2038 #define I915_GTT_OFFSET_NONE ((u32)-1)
2040 struct drm_i915_gem_object_ops
{
2042 #define I915_GEM_OBJECT_HAS_STRUCT_PAGE 0x1
2044 /* Interface between the GEM object and its backing storage.
2045 * get_pages() is called once prior to the use of the associated set
2046 * of pages before to binding them into the GTT, and put_pages() is
2047 * called after we no longer need them. As we expect there to be
2048 * associated cost with migrating pages between the backing storage
2049 * and making them available for the GPU (e.g. clflush), we may hold
2050 * onto the pages after they are no longer referenced by the GPU
2051 * in case they may be used again shortly (for example migrating the
2052 * pages to a different memory domain within the GTT). put_pages()
2053 * will therefore most likely be called when the object itself is
2054 * being released or under memory pressure (where we attempt to
2055 * reap pages for the shrinker).
2057 int (*get_pages
)(struct drm_i915_gem_object
*);
2058 void (*put_pages
)(struct drm_i915_gem_object
*);
2060 int (*dmabuf_export
)(struct drm_i915_gem_object
*);
2061 void (*release
)(struct drm_i915_gem_object
*);
2065 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2066 * considered to be the frontbuffer for the given plane interface-wise. This
2067 * doesn't mean that the hw necessarily already scans it out, but that any
2068 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
2070 * We have one bit per pipe and per scanout plane type.
2072 #define INTEL_MAX_SPRITE_BITS_PER_PIPE 5
2073 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2074 #define INTEL_FRONTBUFFER_BITS \
2075 (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES)
2076 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
2077 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2078 #define INTEL_FRONTBUFFER_CURSOR(pipe) \
2079 (1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2080 #define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \
2081 (1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2082 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2083 (1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2084 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2085 (0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2087 struct drm_i915_gem_object
{
2088 struct drm_gem_object base
;
2090 const struct drm_i915_gem_object_ops
*ops
;
2092 /** List of VMAs backed by this object */
2093 struct list_head vma_list
;
2095 /** Stolen memory for this object, instead of being backed by shmem. */
2096 struct drm_mm_node
*stolen
;
2097 struct list_head global_list
;
2099 struct list_head engine_list
[I915_NUM_ENGINES
];
2100 /** Used in execbuf to temporarily hold a ref */
2101 struct list_head obj_exec_link
;
2103 struct list_head batch_pool_link
;
2106 * This is set if the object is on the active lists (has pending
2107 * rendering and so a non-zero seqno), and is not set if it i s on
2108 * inactive (ready to be unbound) list.
2110 unsigned int active
:I915_NUM_ENGINES
;
2113 * This is set if the object has been written to since last bound
2116 unsigned int dirty
:1;
2119 * Fence register bits (if any) for this object. Will be set
2120 * as needed when mapped into the GTT.
2121 * Protected by dev->struct_mutex.
2123 signed int fence_reg
:I915_MAX_NUM_FENCE_BITS
;
2126 * Advice: are the backing pages purgeable?
2128 unsigned int madv
:2;
2131 * Current tiling mode for the object.
2133 unsigned int tiling_mode
:2;
2135 * Whether the tiling parameters for the currently associated fence
2136 * register have changed. Note that for the purposes of tracking
2137 * tiling changes we also treat the unfenced register, the register
2138 * slot that the object occupies whilst it executes a fenced
2139 * command (such as BLT on gen2/3), as a "fence".
2141 unsigned int fence_dirty
:1;
2144 * Is the object at the current location in the gtt mappable and
2145 * fenceable? Used to avoid costly recalculations.
2147 unsigned int map_and_fenceable
:1;
2150 * Whether the current gtt mapping needs to be mappable (and isn't just
2151 * mappable by accident). Track pin and fault separate for a more
2152 * accurate mappable working set.
2154 unsigned int fault_mappable
:1;
2157 * Is the object to be mapped as read-only to the GPU
2158 * Only honoured if hardware has relevant pte bit
2160 unsigned long gt_ro
:1;
2161 unsigned int cache_level
:3;
2162 unsigned int cache_dirty
:1;
2164 unsigned int frontbuffer_bits
:INTEL_FRONTBUFFER_BITS
;
2166 unsigned int pin_display
;
2168 struct sg_table
*pages
;
2169 int pages_pin_count
;
2171 struct scatterlist
*sg
;
2176 /** Breadcrumb of last rendering to the buffer.
2177 * There can only be one writer, but we allow for multiple readers.
2178 * If there is a writer that necessarily implies that all other
2179 * read requests are complete - but we may only be lazily clearing
2180 * the read requests. A read request is naturally the most recent
2181 * request on a ring, so we may have two different write and read
2182 * requests on one ring where the write request is older than the
2183 * read request. This allows for the CPU to read from an active
2184 * buffer by only waiting for the write to complete.
2186 struct drm_i915_gem_request
*last_read_req
[I915_NUM_ENGINES
];
2187 struct drm_i915_gem_request
*last_write_req
;
2188 /** Breadcrumb of last fenced GPU access to the buffer. */
2189 struct drm_i915_gem_request
*last_fenced_req
;
2191 /** Current tiling stride for the object, if it's tiled. */
2194 /** References from framebuffers, locks out tiling changes. */
2195 unsigned long framebuffer_references
;
2197 /** Record of address bit 17 of each page at last unbind. */
2198 unsigned long *bit_17
;
2201 /** for phy allocated objects */
2202 struct drm_dma_handle
*phys_handle
;
2204 struct i915_gem_userptr
{
2206 unsigned read_only
:1;
2207 unsigned workers
:4;
2208 #define I915_GEM_USERPTR_MAX_WORKERS 15
2210 struct i915_mm_struct
*mm
;
2211 struct i915_mmu_object
*mmu_object
;
2212 struct work_struct
*work
;
2216 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
2218 void i915_gem_track_fb(struct drm_i915_gem_object
*old
,
2219 struct drm_i915_gem_object
*new,
2220 unsigned frontbuffer_bits
);
2223 * Request queue structure.
2225 * The request queue allows us to note sequence numbers that have been emitted
2226 * and may be associated with active buffers to be retired.
2228 * By keeping this list, we can avoid having to do questionable sequence
2229 * number comparisons on buffer last_read|write_seqno. It also allows an
2230 * emission time to be associated with the request for tracking how far ahead
2231 * of the GPU the submission is.
2233 * The requests are reference counted, so upon creation they should have an
2234 * initial reference taken using kref_init
2236 struct drm_i915_gem_request
{
2239 /** On Which ring this request was generated */
2240 struct drm_i915_private
*i915
;
2241 struct intel_engine_cs
*engine
;
2243 /** GEM sequence number associated with the previous request,
2244 * when the HWS breadcrumb is equal to this the GPU is processing
2249 /** GEM sequence number associated with this request,
2250 * when the HWS breadcrumb is equal or greater than this the GPU
2251 * has finished processing this request.
2255 /** Position in the ringbuffer of the start of the request */
2259 * Position in the ringbuffer of the start of the postfix.
2260 * This is required to calculate the maximum available ringbuffer
2261 * space without overwriting the postfix.
2265 /** Position in the ringbuffer of the end of the whole request */
2269 * Context and ring buffer related to this request
2270 * Contexts are refcounted, so when this request is associated with a
2271 * context, we must increment the context's refcount, to guarantee that
2272 * it persists while any request is linked to it. Requests themselves
2273 * are also refcounted, so the request will only be freed when the last
2274 * reference to it is dismissed, and the code in
2275 * i915_gem_request_free() will then decrement the refcount on the
2278 struct intel_context
*ctx
;
2279 struct intel_ringbuffer
*ringbuf
;
2281 /** Batch buffer related to this request if any (used for
2282 error state dump only) */
2283 struct drm_i915_gem_object
*batch_obj
;
2285 /** Time at which this request was emitted, in jiffies. */
2286 unsigned long emitted_jiffies
;
2288 /** global list entry for this request */
2289 struct list_head list
;
2291 struct drm_i915_file_private
*file_priv
;
2292 /** file_priv list entry for this request */
2293 struct list_head client_list
;
2295 /** process identifier submitting this request */
2299 * The ELSP only accepts two elements at a time, so we queue
2300 * context/tail pairs on a given queue (ring->execlist_queue) until the
2301 * hardware is available. The queue serves a double purpose: we also use
2302 * it to keep track of the up to 2 contexts currently in the hardware
2303 * (usually one in execution and the other queued up by the GPU): We
2304 * only remove elements from the head of the queue when the hardware
2305 * informs us that an element has been completed.
2307 * All accesses to the queue are mediated by a spinlock
2308 * (ring->execlist_lock).
2311 /** Execlist link in the submission queue.*/
2312 struct list_head execlist_link
;
2314 /** Execlists no. of times this request has been sent to the ELSP */
2319 struct drm_i915_gem_request
* __must_check
2320 i915_gem_request_alloc(struct intel_engine_cs
*engine
,
2321 struct intel_context
*ctx
);
2322 void i915_gem_request_cancel(struct drm_i915_gem_request
*req
);
2323 void i915_gem_request_free(struct kref
*req_ref
);
2324 int i915_gem_request_add_to_client(struct drm_i915_gem_request
*req
,
2325 struct drm_file
*file
);
2327 static inline uint32_t
2328 i915_gem_request_get_seqno(struct drm_i915_gem_request
*req
)
2330 return req
? req
->seqno
: 0;
2333 static inline struct intel_engine_cs
*
2334 i915_gem_request_get_engine(struct drm_i915_gem_request
*req
)
2336 return req
? req
->engine
: NULL
;
2339 static inline struct drm_i915_gem_request
*
2340 i915_gem_request_reference(struct drm_i915_gem_request
*req
)
2343 kref_get(&req
->ref
);
2348 i915_gem_request_unreference(struct drm_i915_gem_request
*req
)
2350 WARN_ON(!mutex_is_locked(&req
->engine
->dev
->struct_mutex
));
2351 kref_put(&req
->ref
, i915_gem_request_free
);
2355 i915_gem_request_unreference__unlocked(struct drm_i915_gem_request
*req
)
2357 struct drm_device
*dev
;
2362 dev
= req
->engine
->dev
;
2363 if (kref_put_mutex(&req
->ref
, i915_gem_request_free
, &dev
->struct_mutex
))
2364 mutex_unlock(&dev
->struct_mutex
);
2367 static inline void i915_gem_request_assign(struct drm_i915_gem_request
**pdst
,
2368 struct drm_i915_gem_request
*src
)
2371 i915_gem_request_reference(src
);
2374 i915_gem_request_unreference(*pdst
);
2380 * XXX: i915_gem_request_completed should be here but currently needs the
2381 * definition of i915_seqno_passed() which is below. It will be moved in
2382 * a later patch when the call to i915_seqno_passed() is obsoleted...
2386 * A command that requires special handling by the command parser.
2388 struct drm_i915_cmd_descriptor
{
2390 * Flags describing how the command parser processes the command.
2392 * CMD_DESC_FIXED: The command has a fixed length if this is set,
2393 * a length mask if not set
2394 * CMD_DESC_SKIP: The command is allowed but does not follow the
2395 * standard length encoding for the opcode range in
2397 * CMD_DESC_REJECT: The command is never allowed
2398 * CMD_DESC_REGISTER: The command should be checked against the
2399 * register whitelist for the appropriate ring
2400 * CMD_DESC_MASTER: The command is allowed if the submitting process
2404 #define CMD_DESC_FIXED (1<<0)
2405 #define CMD_DESC_SKIP (1<<1)
2406 #define CMD_DESC_REJECT (1<<2)
2407 #define CMD_DESC_REGISTER (1<<3)
2408 #define CMD_DESC_BITMASK (1<<4)
2409 #define CMD_DESC_MASTER (1<<5)
2412 * The command's unique identification bits and the bitmask to get them.
2413 * This isn't strictly the opcode field as defined in the spec and may
2414 * also include type, subtype, and/or subop fields.
2422 * The command's length. The command is either fixed length (i.e. does
2423 * not include a length field) or has a length field mask. The flag
2424 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
2425 * a length mask. All command entries in a command table must include
2426 * length information.
2434 * Describes where to find a register address in the command to check
2435 * against the ring's register whitelist. Only valid if flags has the
2436 * CMD_DESC_REGISTER bit set.
2438 * A non-zero step value implies that the command may access multiple
2439 * registers in sequence (e.g. LRI), in that case step gives the
2440 * distance in dwords between individual offset fields.
2448 #define MAX_CMD_DESC_BITMASKS 3
2450 * Describes command checks where a particular dword is masked and
2451 * compared against an expected value. If the command does not match
2452 * the expected value, the parser rejects it. Only valid if flags has
2453 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
2456 * If the check specifies a non-zero condition_mask then the parser
2457 * only performs the check when the bits specified by condition_mask
2464 u32 condition_offset
;
2466 } bits
[MAX_CMD_DESC_BITMASKS
];
2470 * A table of commands requiring special handling by the command parser.
2472 * Each ring has an array of tables. Each table consists of an array of command
2473 * descriptors, which must be sorted with command opcodes in ascending order.
2475 struct drm_i915_cmd_table
{
2476 const struct drm_i915_cmd_descriptor
*table
;
2480 /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
2481 #define __I915__(p) ({ \
2482 struct drm_i915_private *__p; \
2483 if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
2484 __p = (struct drm_i915_private *)p; \
2485 else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
2486 __p = to_i915((struct drm_device *)p); \
2491 #define INTEL_INFO(p) (&__I915__(p)->info)
2492 #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id)
2493 #define INTEL_REVID(p) (__I915__(p)->dev->pdev->revision)
2495 #define REVID_FOREVER 0xff
2497 * Return true if revision is in range [since,until] inclusive.
2499 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
2501 #define IS_REVID(p, since, until) \
2502 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
2504 #define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577)
2505 #define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562)
2506 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
2507 #define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572)
2508 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
2509 #define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592)
2510 #define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772)
2511 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
2512 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
2513 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
2514 #define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42)
2515 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
2516 #define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001)
2517 #define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011)
2518 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
2519 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
2520 #define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046)
2521 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
2522 #define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \
2523 INTEL_DEVID(dev) == 0x0152 || \
2524 INTEL_DEVID(dev) == 0x015a)
2525 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
2526 #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_cherryview)
2527 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
2528 #define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_cherryview && IS_GEN8(dev))
2529 #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake)
2530 #define IS_BROXTON(dev) (INTEL_INFO(dev)->is_broxton)
2531 #define IS_KABYLAKE(dev) (INTEL_INFO(dev)->is_kabylake)
2532 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
2533 #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
2534 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
2535 #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
2536 ((INTEL_DEVID(dev) & 0xf) == 0x6 || \
2537 (INTEL_DEVID(dev) & 0xf) == 0xb || \
2538 (INTEL_DEVID(dev) & 0xf) == 0xe))
2539 /* ULX machines are also considered ULT. */
2540 #define IS_BDW_ULX(dev) (IS_BROADWELL(dev) && \
2541 (INTEL_DEVID(dev) & 0xf) == 0xe)
2542 #define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \
2543 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2544 #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
2545 (INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
2546 #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
2547 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2548 /* ULX machines are also considered ULT. */
2549 #define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \
2550 INTEL_DEVID(dev) == 0x0A1E)
2551 #define IS_SKL_ULT(dev) (INTEL_DEVID(dev) == 0x1906 || \
2552 INTEL_DEVID(dev) == 0x1913 || \
2553 INTEL_DEVID(dev) == 0x1916 || \
2554 INTEL_DEVID(dev) == 0x1921 || \
2555 INTEL_DEVID(dev) == 0x1926)
2556 #define IS_SKL_ULX(dev) (INTEL_DEVID(dev) == 0x190E || \
2557 INTEL_DEVID(dev) == 0x1915 || \
2558 INTEL_DEVID(dev) == 0x191E)
2559 #define IS_KBL_ULT(dev) (INTEL_DEVID(dev) == 0x5906 || \
2560 INTEL_DEVID(dev) == 0x5913 || \
2561 INTEL_DEVID(dev) == 0x5916 || \
2562 INTEL_DEVID(dev) == 0x5921 || \
2563 INTEL_DEVID(dev) == 0x5926)
2564 #define IS_KBL_ULX(dev) (INTEL_DEVID(dev) == 0x590E || \
2565 INTEL_DEVID(dev) == 0x5915 || \
2566 INTEL_DEVID(dev) == 0x591E)
2567 #define IS_SKL_GT3(dev) (IS_SKYLAKE(dev) && \
2568 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2569 #define IS_SKL_GT4(dev) (IS_SKYLAKE(dev) && \
2570 (INTEL_DEVID(dev) & 0x00F0) == 0x0030)
2572 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
2574 #define SKL_REVID_A0 0x0
2575 #define SKL_REVID_B0 0x1
2576 #define SKL_REVID_C0 0x2
2577 #define SKL_REVID_D0 0x3
2578 #define SKL_REVID_E0 0x4
2579 #define SKL_REVID_F0 0x5
2581 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
2583 #define BXT_REVID_A0 0x0
2584 #define BXT_REVID_A1 0x1
2585 #define BXT_REVID_B0 0x3
2586 #define BXT_REVID_C0 0x9
2588 #define IS_BXT_REVID(p, since, until) (IS_BROXTON(p) && IS_REVID(p, since, until))
2591 * The genX designation typically refers to the render engine, so render
2592 * capability related checks should use IS_GEN, while display and other checks
2593 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2596 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
2597 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
2598 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
2599 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
2600 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
2601 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
2602 #define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8)
2603 #define IS_GEN9(dev) (INTEL_INFO(dev)->gen == 9)
2605 #define RENDER_RING (1<<RCS)
2606 #define BSD_RING (1<<VCS)
2607 #define BLT_RING (1<<BCS)
2608 #define VEBOX_RING (1<<VECS)
2609 #define BSD2_RING (1<<VCS2)
2610 #define ALL_ENGINES (~0)
2612 #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING)
2613 #define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING)
2614 #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING)
2615 #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
2616 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
2617 #define HAS_SNOOP(dev) (INTEL_INFO(dev)->has_snoop)
2618 #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
2619 __I915__(dev)->ellc_size)
2620 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
2622 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
2623 #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8)
2624 #define USES_PPGTT(dev) (i915.enable_ppgtt)
2625 #define USES_FULL_PPGTT(dev) (i915.enable_ppgtt >= 2)
2626 #define USES_FULL_48BIT_PPGTT(dev) (i915.enable_ppgtt == 3)
2628 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
2629 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
2631 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2632 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
2634 /* WaRsDisableCoarsePowerGating:skl,bxt */
2635 #define NEEDS_WaRsDisableCoarsePowerGating(dev) (IS_BXT_REVID(dev, 0, BXT_REVID_A1) || \
2636 ((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) && \
2637 IS_SKL_REVID(dev, 0, SKL_REVID_F0)))
2639 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2640 * even when in MSI mode. This results in spurious interrupt warnings if the
2641 * legacy irq no. is shared with another device. The kernel then disables that
2642 * interrupt source and so prevents the other device from working properly.
2644 #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2645 #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2647 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2648 * rows, which changed the alignment requirements and fence programming.
2650 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
2652 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
2653 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
2655 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
2656 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
2657 #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
2659 #define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev))
2661 #define HAS_DP_MST(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2662 INTEL_INFO(dev)->gen >= 9)
2664 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
2665 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
2666 #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2667 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \
2668 IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
2669 #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \
2670 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \
2671 IS_CHERRYVIEW(dev) || IS_SKYLAKE(dev) || \
2673 #define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6)
2674 #define HAS_RC6p(dev) (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
2676 #define HAS_CSR(dev) (IS_GEN9(dev))
2678 #define HAS_GUC_UCODE(dev) (IS_GEN9(dev) && !IS_KABYLAKE(dev))
2679 #define HAS_GUC_SCHED(dev) (IS_GEN9(dev) && !IS_KABYLAKE(dev))
2681 #define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \
2682 INTEL_INFO(dev)->gen >= 8)
2684 #define HAS_CORE_RING_FREQ(dev) (INTEL_INFO(dev)->gen >= 6 && \
2685 !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && \
2688 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
2689 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2690 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2691 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2692 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2693 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2694 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2695 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2696 #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
2697 #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
2698 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
2700 #define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
2701 #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
2702 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
2703 #define HAS_PCH_LPT_LP(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
2704 #define HAS_PCH_LPT_H(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
2705 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
2706 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
2707 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
2708 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
2710 #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || \
2711 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
2713 /* DPF == dynamic parity feature */
2714 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
2715 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
2717 #define GT_FREQUENCY_MULTIPLIER 50
2718 #define GEN9_FREQ_SCALER 3
2720 #include "i915_trace.h"
2722 extern const struct drm_ioctl_desc i915_ioctls
[];
2723 extern int i915_max_ioctl
;
2725 extern int i915_suspend_switcheroo(struct drm_device
*dev
, pm_message_t state
);
2726 extern int i915_resume_switcheroo(struct drm_device
*dev
);
2730 __i915_printk(struct drm_i915_private
*dev_priv
, const char *level
,
2731 const char *fmt
, ...);
2733 #define i915_report_error(dev_priv, fmt, ...) \
2734 __i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__)
2736 extern int i915_driver_load(struct drm_device
*, unsigned long flags
);
2737 extern int i915_driver_unload(struct drm_device
*);
2738 extern int i915_driver_open(struct drm_device
*dev
, struct drm_file
*file
);
2739 extern void i915_driver_lastclose(struct drm_device
* dev
);
2740 extern void i915_driver_preclose(struct drm_device
*dev
,
2741 struct drm_file
*file
);
2742 extern void i915_driver_postclose(struct drm_device
*dev
,
2743 struct drm_file
*file
);
2744 #ifdef CONFIG_COMPAT
2745 extern long i915_compat_ioctl(struct file
*filp
, unsigned int cmd
,
2748 extern int intel_gpu_reset(struct drm_device
*dev
, u32 engine_mask
);
2749 extern bool intel_has_gpu_reset(struct drm_device
*dev
);
2750 extern int i915_reset(struct drm_device
*dev
);
2751 extern int intel_guc_reset(struct drm_i915_private
*dev_priv
);
2752 extern void intel_engine_init_hangcheck(struct intel_engine_cs
*engine
);
2753 extern unsigned long i915_chipset_val(struct drm_i915_private
*dev_priv
);
2754 extern unsigned long i915_mch_val(struct drm_i915_private
*dev_priv
);
2755 extern unsigned long i915_gfx_val(struct drm_i915_private
*dev_priv
);
2756 extern void i915_update_gfx_val(struct drm_i915_private
*dev_priv
);
2757 int vlv_force_gfx_clock(struct drm_i915_private
*dev_priv
, bool on
);
2759 /* intel_hotplug.c */
2760 void intel_hpd_irq_handler(struct drm_device
*dev
, u32 pin_mask
, u32 long_mask
);
2761 void intel_hpd_init(struct drm_i915_private
*dev_priv
);
2762 void intel_hpd_init_work(struct drm_i915_private
*dev_priv
);
2763 void intel_hpd_cancel_work(struct drm_i915_private
*dev_priv
);
2764 bool intel_hpd_pin_to_port(enum hpd_pin pin
, enum port
*port
);
2767 void i915_queue_hangcheck(struct drm_device
*dev
);
2769 void i915_handle_error(struct drm_device
*dev
, u32 engine_mask
,
2770 const char *fmt
, ...);
2772 extern void intel_irq_init(struct drm_i915_private
*dev_priv
);
2773 int intel_irq_install(struct drm_i915_private
*dev_priv
);
2774 void intel_irq_uninstall(struct drm_i915_private
*dev_priv
);
2776 extern void intel_uncore_sanitize(struct drm_device
*dev
);
2777 extern void intel_uncore_early_sanitize(struct drm_device
*dev
,
2778 bool restore_forcewake
);
2779 extern void intel_uncore_init(struct drm_device
*dev
);
2780 extern bool intel_uncore_unclaimed_mmio(struct drm_i915_private
*dev_priv
);
2781 extern bool intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private
*dev_priv
);
2782 extern void intel_uncore_fini(struct drm_device
*dev
);
2783 extern void intel_uncore_forcewake_reset(struct drm_device
*dev
, bool restore
);
2784 const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id
);
2785 void intel_uncore_forcewake_get(struct drm_i915_private
*dev_priv
,
2786 enum forcewake_domains domains
);
2787 void intel_uncore_forcewake_put(struct drm_i915_private
*dev_priv
,
2788 enum forcewake_domains domains
);
2789 /* Like above but the caller must manage the uncore.lock itself.
2790 * Must be used with I915_READ_FW and friends.
2792 void intel_uncore_forcewake_get__locked(struct drm_i915_private
*dev_priv
,
2793 enum forcewake_domains domains
);
2794 void intel_uncore_forcewake_put__locked(struct drm_i915_private
*dev_priv
,
2795 enum forcewake_domains domains
);
2796 void assert_forcewakes_inactive(struct drm_i915_private
*dev_priv
);
2797 static inline bool intel_vgpu_active(struct drm_device
*dev
)
2799 return to_i915(dev
)->vgpu
.active
;
2803 i915_enable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
2807 i915_disable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
2810 void valleyview_enable_display_irqs(struct drm_i915_private
*dev_priv
);
2811 void valleyview_disable_display_irqs(struct drm_i915_private
*dev_priv
);
2812 void i915_hotplug_interrupt_update(struct drm_i915_private
*dev_priv
,
2815 void ilk_update_display_irq(struct drm_i915_private
*dev_priv
,
2816 uint32_t interrupt_mask
,
2817 uint32_t enabled_irq_mask
);
2819 ilk_enable_display_irq(struct drm_i915_private
*dev_priv
, uint32_t bits
)
2821 ilk_update_display_irq(dev_priv
, bits
, bits
);
2824 ilk_disable_display_irq(struct drm_i915_private
*dev_priv
, uint32_t bits
)
2826 ilk_update_display_irq(dev_priv
, bits
, 0);
2828 void bdw_update_pipe_irq(struct drm_i915_private
*dev_priv
,
2830 uint32_t interrupt_mask
,
2831 uint32_t enabled_irq_mask
);
2832 static inline void bdw_enable_pipe_irq(struct drm_i915_private
*dev_priv
,
2833 enum pipe pipe
, uint32_t bits
)
2835 bdw_update_pipe_irq(dev_priv
, pipe
, bits
, bits
);
2837 static inline void bdw_disable_pipe_irq(struct drm_i915_private
*dev_priv
,
2838 enum pipe pipe
, uint32_t bits
)
2840 bdw_update_pipe_irq(dev_priv
, pipe
, bits
, 0);
2842 void ibx_display_interrupt_update(struct drm_i915_private
*dev_priv
,
2843 uint32_t interrupt_mask
,
2844 uint32_t enabled_irq_mask
);
2846 ibx_enable_display_interrupt(struct drm_i915_private
*dev_priv
, uint32_t bits
)
2848 ibx_display_interrupt_update(dev_priv
, bits
, bits
);
2851 ibx_disable_display_interrupt(struct drm_i915_private
*dev_priv
, uint32_t bits
)
2853 ibx_display_interrupt_update(dev_priv
, bits
, 0);
2858 int i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
2859 struct drm_file
*file_priv
);
2860 int i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
2861 struct drm_file
*file_priv
);
2862 int i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
2863 struct drm_file
*file_priv
);
2864 int i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
2865 struct drm_file
*file_priv
);
2866 int i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
2867 struct drm_file
*file_priv
);
2868 int i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
2869 struct drm_file
*file_priv
);
2870 int i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
2871 struct drm_file
*file_priv
);
2872 void i915_gem_execbuffer_move_to_active(struct list_head
*vmas
,
2873 struct drm_i915_gem_request
*req
);
2874 void i915_gem_execbuffer_retire_commands(struct i915_execbuffer_params
*params
);
2875 int i915_gem_ringbuffer_submission(struct i915_execbuffer_params
*params
,
2876 struct drm_i915_gem_execbuffer2
*args
,
2877 struct list_head
*vmas
);
2878 int i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
2879 struct drm_file
*file_priv
);
2880 int i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
2881 struct drm_file
*file_priv
);
2882 int i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
2883 struct drm_file
*file_priv
);
2884 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
2885 struct drm_file
*file
);
2886 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
2887 struct drm_file
*file
);
2888 int i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
2889 struct drm_file
*file_priv
);
2890 int i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
2891 struct drm_file
*file_priv
);
2892 int i915_gem_set_tiling(struct drm_device
*dev
, void *data
,
2893 struct drm_file
*file_priv
);
2894 int i915_gem_get_tiling(struct drm_device
*dev
, void *data
,
2895 struct drm_file
*file_priv
);
2896 int i915_gem_init_userptr(struct drm_device
*dev
);
2897 int i915_gem_userptr_ioctl(struct drm_device
*dev
, void *data
,
2898 struct drm_file
*file
);
2899 int i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
2900 struct drm_file
*file_priv
);
2901 int i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
,
2902 struct drm_file
*file_priv
);
2903 void i915_gem_load_init(struct drm_device
*dev
);
2904 void i915_gem_load_cleanup(struct drm_device
*dev
);
2905 void i915_gem_load_init_fences(struct drm_i915_private
*dev_priv
);
2906 void *i915_gem_object_alloc(struct drm_device
*dev
);
2907 void i915_gem_object_free(struct drm_i915_gem_object
*obj
);
2908 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
2909 const struct drm_i915_gem_object_ops
*ops
);
2910 struct drm_i915_gem_object
*i915_gem_alloc_object(struct drm_device
*dev
,
2912 struct drm_i915_gem_object
*i915_gem_object_create_from_data(
2913 struct drm_device
*dev
, const void *data
, size_t size
);
2914 void i915_gem_free_object(struct drm_gem_object
*obj
);
2915 void i915_gem_vma_destroy(struct i915_vma
*vma
);
2917 /* Flags used by pin/bind&friends. */
2918 #define PIN_MAPPABLE (1<<0)
2919 #define PIN_NONBLOCK (1<<1)
2920 #define PIN_GLOBAL (1<<2)
2921 #define PIN_OFFSET_BIAS (1<<3)
2922 #define PIN_USER (1<<4)
2923 #define PIN_UPDATE (1<<5)
2924 #define PIN_ZONE_4G (1<<6)
2925 #define PIN_HIGH (1<<7)
2926 #define PIN_OFFSET_FIXED (1<<8)
2927 #define PIN_OFFSET_MASK (~4095)
2929 i915_gem_object_pin(struct drm_i915_gem_object
*obj
,
2930 struct i915_address_space
*vm
,
2934 i915_gem_object_ggtt_pin(struct drm_i915_gem_object
*obj
,
2935 const struct i915_ggtt_view
*view
,
2939 int i915_vma_bind(struct i915_vma
*vma
, enum i915_cache_level cache_level
,
2941 void __i915_vma_set_map_and_fenceable(struct i915_vma
*vma
);
2942 int __must_check
i915_vma_unbind(struct i915_vma
*vma
);
2944 * BEWARE: Do not use the function below unless you can _absolutely_
2945 * _guarantee_ VMA in question is _not in use_ anywhere.
2947 int __must_check
__i915_vma_unbind_no_wait(struct i915_vma
*vma
);
2948 int i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
);
2949 void i915_gem_release_all_mmaps(struct drm_i915_private
*dev_priv
);
2950 void i915_gem_release_mmap(struct drm_i915_gem_object
*obj
);
2952 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object
*obj
,
2953 int *needs_clflush
);
2955 int __must_check
i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
);
2957 static inline int __sg_page_count(struct scatterlist
*sg
)
2959 return sg
->length
>> PAGE_SHIFT
;
2963 i915_gem_object_get_dirty_page(struct drm_i915_gem_object
*obj
, int n
);
2965 static inline struct page
*
2966 i915_gem_object_get_page(struct drm_i915_gem_object
*obj
, int n
)
2968 if (WARN_ON(n
>= obj
->base
.size
>> PAGE_SHIFT
))
2971 if (n
< obj
->get_page
.last
) {
2972 obj
->get_page
.sg
= obj
->pages
->sgl
;
2973 obj
->get_page
.last
= 0;
2976 while (obj
->get_page
.last
+ __sg_page_count(obj
->get_page
.sg
) <= n
) {
2977 obj
->get_page
.last
+= __sg_page_count(obj
->get_page
.sg
++);
2978 if (unlikely(sg_is_chain(obj
->get_page
.sg
)))
2979 obj
->get_page
.sg
= sg_chain_ptr(obj
->get_page
.sg
);
2982 return nth_page(sg_page(obj
->get_page
.sg
), n
- obj
->get_page
.last
);
2985 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object
*obj
)
2987 BUG_ON(obj
->pages
== NULL
);
2988 obj
->pages_pin_count
++;
2991 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object
*obj
)
2993 BUG_ON(obj
->pages_pin_count
== 0);
2994 obj
->pages_pin_count
--;
2998 * i915_gem_object_pin_map - return a contiguous mapping of the entire object
2999 * @obj - the object to map into kernel address space
3001 * Calls i915_gem_object_pin_pages() to prevent reaping of the object's
3002 * pages and then returns a contiguous mapping of the backing storage into
3003 * the kernel address space.
3005 * The caller must hold the struct_mutex.
3007 * Returns the pointer through which to access the backing storage.
3009 void *__must_check
i915_gem_object_pin_map(struct drm_i915_gem_object
*obj
);
3012 * i915_gem_object_unpin_map - releases an earlier mapping
3013 * @obj - the object to unmap
3015 * After pinning the object and mapping its pages, once you are finished
3016 * with your access, call i915_gem_object_unpin_map() to release the pin
3017 * upon the mapping. Once the pin count reaches zero, that mapping may be
3020 * The caller must hold the struct_mutex.
3022 static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object
*obj
)
3024 lockdep_assert_held(&obj
->base
.dev
->struct_mutex
);
3025 i915_gem_object_unpin_pages(obj
);
3028 int __must_check
i915_mutex_lock_interruptible(struct drm_device
*dev
);
3029 int i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
3030 struct intel_engine_cs
*to
,
3031 struct drm_i915_gem_request
**to_req
);
3032 void i915_vma_move_to_active(struct i915_vma
*vma
,
3033 struct drm_i915_gem_request
*req
);
3034 int i915_gem_dumb_create(struct drm_file
*file_priv
,
3035 struct drm_device
*dev
,
3036 struct drm_mode_create_dumb
*args
);
3037 int i915_gem_mmap_gtt(struct drm_file
*file_priv
, struct drm_device
*dev
,
3038 uint32_t handle
, uint64_t *offset
);
3040 * Returns true if seq1 is later than seq2.
3043 i915_seqno_passed(uint32_t seq1
, uint32_t seq2
)
3045 return (int32_t)(seq1
- seq2
) >= 0;
3048 static inline bool i915_gem_request_started(struct drm_i915_gem_request
*req
,
3049 bool lazy_coherency
)
3051 if (!lazy_coherency
&& req
->engine
->irq_seqno_barrier
)
3052 req
->engine
->irq_seqno_barrier(req
->engine
);
3053 return i915_seqno_passed(req
->engine
->get_seqno(req
->engine
),
3054 req
->previous_seqno
);
3057 static inline bool i915_gem_request_completed(struct drm_i915_gem_request
*req
,
3058 bool lazy_coherency
)
3060 if (!lazy_coherency
&& req
->engine
->irq_seqno_barrier
)
3061 req
->engine
->irq_seqno_barrier(req
->engine
);
3062 return i915_seqno_passed(req
->engine
->get_seqno(req
->engine
),
3066 int __must_check
i915_gem_get_seqno(struct drm_device
*dev
, u32
*seqno
);
3067 int __must_check
i915_gem_set_seqno(struct drm_device
*dev
, u32 seqno
);
3069 struct drm_i915_gem_request
*
3070 i915_gem_find_active_request(struct intel_engine_cs
*engine
);
3072 bool i915_gem_retire_requests(struct drm_device
*dev
);
3073 void i915_gem_retire_requests_ring(struct intel_engine_cs
*engine
);
3074 int __must_check
i915_gem_check_wedge(struct i915_gpu_error
*error
,
3075 bool interruptible
);
3077 static inline bool i915_reset_in_progress(struct i915_gpu_error
*error
)
3079 return unlikely(atomic_read(&error
->reset_counter
)
3080 & (I915_RESET_IN_PROGRESS_FLAG
| I915_WEDGED
));
3083 static inline bool i915_terminally_wedged(struct i915_gpu_error
*error
)
3085 return atomic_read(&error
->reset_counter
) & I915_WEDGED
;
3088 static inline u32
i915_reset_count(struct i915_gpu_error
*error
)
3090 return ((atomic_read(&error
->reset_counter
) & ~I915_WEDGED
) + 1) / 2;
3093 static inline bool i915_stop_ring_allow_ban(struct drm_i915_private
*dev_priv
)
3095 return dev_priv
->gpu_error
.stop_rings
== 0 ||
3096 dev_priv
->gpu_error
.stop_rings
& I915_STOP_RING_ALLOW_BAN
;
3099 static inline bool i915_stop_ring_allow_warn(struct drm_i915_private
*dev_priv
)
3101 return dev_priv
->gpu_error
.stop_rings
== 0 ||
3102 dev_priv
->gpu_error
.stop_rings
& I915_STOP_RING_ALLOW_WARN
;
3105 void i915_gem_reset(struct drm_device
*dev
);
3106 bool i915_gem_clflush_object(struct drm_i915_gem_object
*obj
, bool force
);
3107 int __must_check
i915_gem_init(struct drm_device
*dev
);
3108 int i915_gem_init_engines(struct drm_device
*dev
);
3109 int __must_check
i915_gem_init_hw(struct drm_device
*dev
);
3110 int i915_gem_l3_remap(struct drm_i915_gem_request
*req
, int slice
);
3111 void i915_gem_init_swizzling(struct drm_device
*dev
);
3112 void i915_gem_cleanup_engines(struct drm_device
*dev
);
3113 int __must_check
i915_gpu_idle(struct drm_device
*dev
);
3114 int __must_check
i915_gem_suspend(struct drm_device
*dev
);
3115 void __i915_add_request(struct drm_i915_gem_request
*req
,
3116 struct drm_i915_gem_object
*batch_obj
,
3118 #define i915_add_request(req) \
3119 __i915_add_request(req, NULL, true)
3120 #define i915_add_request_no_flush(req) \
3121 __i915_add_request(req, NULL, false)
3122 int __i915_wait_request(struct drm_i915_gem_request
*req
,
3123 unsigned reset_counter
,
3126 struct intel_rps_client
*rps
);
3127 int __must_check
i915_wait_request(struct drm_i915_gem_request
*req
);
3128 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
);
3130 i915_gem_object_wait_rendering(struct drm_i915_gem_object
*obj
,
3133 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
,
3136 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
);
3138 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
3140 const struct i915_ggtt_view
*view
);
3141 void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object
*obj
,
3142 const struct i915_ggtt_view
*view
);
3143 int i915_gem_object_attach_phys(struct drm_i915_gem_object
*obj
,
3145 int i915_gem_open(struct drm_device
*dev
, struct drm_file
*file
);
3146 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
);
3149 i915_gem_get_gtt_size(struct drm_device
*dev
, uint32_t size
, int tiling_mode
);
3151 i915_gem_get_gtt_alignment(struct drm_device
*dev
, uint32_t size
,
3152 int tiling_mode
, bool fenced
);
3154 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
3155 enum i915_cache_level cache_level
);
3157 struct drm_gem_object
*i915_gem_prime_import(struct drm_device
*dev
,
3158 struct dma_buf
*dma_buf
);
3160 struct dma_buf
*i915_gem_prime_export(struct drm_device
*dev
,
3161 struct drm_gem_object
*gem_obj
, int flags
);
3163 u64
i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object
*o
,
3164 const struct i915_ggtt_view
*view
);
3165 u64
i915_gem_obj_offset(struct drm_i915_gem_object
*o
,
3166 struct i915_address_space
*vm
);
3168 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object
*o
)
3170 return i915_gem_obj_ggtt_offset_view(o
, &i915_ggtt_view_normal
);
3173 bool i915_gem_obj_bound_any(struct drm_i915_gem_object
*o
);
3174 bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object
*o
,
3175 const struct i915_ggtt_view
*view
);
3176 bool i915_gem_obj_bound(struct drm_i915_gem_object
*o
,
3177 struct i915_address_space
*vm
);
3179 unsigned long i915_gem_obj_size(struct drm_i915_gem_object
*o
,
3180 struct i915_address_space
*vm
);
3182 i915_gem_obj_to_vma(struct drm_i915_gem_object
*obj
,
3183 struct i915_address_space
*vm
);
3185 i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object
*obj
,
3186 const struct i915_ggtt_view
*view
);
3189 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object
*obj
,
3190 struct i915_address_space
*vm
);
3192 i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object
*obj
,
3193 const struct i915_ggtt_view
*view
);
3195 static inline struct i915_vma
*
3196 i915_gem_obj_to_ggtt(struct drm_i915_gem_object
*obj
)
3198 return i915_gem_obj_to_ggtt_view(obj
, &i915_ggtt_view_normal
);
3200 bool i915_gem_obj_is_pinned(struct drm_i915_gem_object
*obj
);
3202 /* Some GGTT VM helpers */
3203 static inline struct i915_hw_ppgtt
*
3204 i915_vm_to_ppgtt(struct i915_address_space
*vm
)
3206 return container_of(vm
, struct i915_hw_ppgtt
, base
);
3210 static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object
*obj
)
3212 return i915_gem_obj_ggtt_bound_view(obj
, &i915_ggtt_view_normal
);
3215 static inline unsigned long
3216 i915_gem_obj_ggtt_size(struct drm_i915_gem_object
*obj
)
3218 struct drm_i915_private
*dev_priv
= to_i915(obj
->base
.dev
);
3219 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
3221 return i915_gem_obj_size(obj
, &ggtt
->base
);
3224 static inline int __must_check
3225 i915_gem_obj_ggtt_pin(struct drm_i915_gem_object
*obj
,
3229 struct drm_i915_private
*dev_priv
= to_i915(obj
->base
.dev
);
3230 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
3232 return i915_gem_object_pin(obj
, &ggtt
->base
,
3233 alignment
, flags
| PIN_GLOBAL
);
3237 i915_gem_object_ggtt_unbind(struct drm_i915_gem_object
*obj
)
3239 return i915_vma_unbind(i915_gem_obj_to_ggtt(obj
));
3242 void i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object
*obj
,
3243 const struct i915_ggtt_view
*view
);
3245 i915_gem_object_ggtt_unpin(struct drm_i915_gem_object
*obj
)
3247 i915_gem_object_ggtt_unpin_view(obj
, &i915_ggtt_view_normal
);
3250 /* i915_gem_fence.c */
3251 int __must_check
i915_gem_object_get_fence(struct drm_i915_gem_object
*obj
);
3252 int __must_check
i915_gem_object_put_fence(struct drm_i915_gem_object
*obj
);
3254 bool i915_gem_object_pin_fence(struct drm_i915_gem_object
*obj
);
3255 void i915_gem_object_unpin_fence(struct drm_i915_gem_object
*obj
);
3257 void i915_gem_restore_fences(struct drm_device
*dev
);
3259 void i915_gem_detect_bit_6_swizzle(struct drm_device
*dev
);
3260 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
3261 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
3263 /* i915_gem_context.c */
3264 int __must_check
i915_gem_context_init(struct drm_device
*dev
);
3265 void i915_gem_context_fini(struct drm_device
*dev
);
3266 void i915_gem_context_reset(struct drm_device
*dev
);
3267 int i915_gem_context_open(struct drm_device
*dev
, struct drm_file
*file
);
3268 int i915_gem_context_enable(struct drm_i915_gem_request
*req
);
3269 void i915_gem_context_close(struct drm_device
*dev
, struct drm_file
*file
);
3270 int i915_switch_context(struct drm_i915_gem_request
*req
);
3271 struct intel_context
*
3272 i915_gem_context_get(struct drm_i915_file_private
*file_priv
, u32 id
);
3273 void i915_gem_context_free(struct kref
*ctx_ref
);
3274 struct drm_i915_gem_object
*
3275 i915_gem_alloc_context_obj(struct drm_device
*dev
, size_t size
);
3276 static inline void i915_gem_context_reference(struct intel_context
*ctx
)
3278 kref_get(&ctx
->ref
);
3281 static inline void i915_gem_context_unreference(struct intel_context
*ctx
)
3283 kref_put(&ctx
->ref
, i915_gem_context_free
);
3286 static inline bool i915_gem_context_is_default(const struct intel_context
*c
)
3288 return c
->user_handle
== DEFAULT_CONTEXT_HANDLE
;
3291 int i915_gem_context_create_ioctl(struct drm_device
*dev
, void *data
,
3292 struct drm_file
*file
);
3293 int i915_gem_context_destroy_ioctl(struct drm_device
*dev
, void *data
,
3294 struct drm_file
*file
);
3295 int i915_gem_context_getparam_ioctl(struct drm_device
*dev
, void *data
,
3296 struct drm_file
*file_priv
);
3297 int i915_gem_context_setparam_ioctl(struct drm_device
*dev
, void *data
,
3298 struct drm_file
*file_priv
);
3300 /* i915_gem_evict.c */
3301 int __must_check
i915_gem_evict_something(struct drm_device
*dev
,
3302 struct i915_address_space
*vm
,
3305 unsigned cache_level
,
3306 unsigned long start
,
3309 int __must_check
i915_gem_evict_for_vma(struct i915_vma
*target
);
3310 int i915_gem_evict_vm(struct i915_address_space
*vm
, bool do_idle
);
3312 /* belongs in i915_gem_gtt.h */
3313 static inline void i915_gem_chipset_flush(struct drm_device
*dev
)
3315 if (INTEL_INFO(dev
)->gen
< 6)
3316 intel_gtt_chipset_flush();
3319 /* i915_gem_stolen.c */
3320 int i915_gem_stolen_insert_node(struct drm_i915_private
*dev_priv
,
3321 struct drm_mm_node
*node
, u64 size
,
3322 unsigned alignment
);
3323 int i915_gem_stolen_insert_node_in_range(struct drm_i915_private
*dev_priv
,
3324 struct drm_mm_node
*node
, u64 size
,
3325 unsigned alignment
, u64 start
,
3327 void i915_gem_stolen_remove_node(struct drm_i915_private
*dev_priv
,
3328 struct drm_mm_node
*node
);
3329 int i915_gem_init_stolen(struct drm_device
*dev
);
3330 void i915_gem_cleanup_stolen(struct drm_device
*dev
);
3331 struct drm_i915_gem_object
*
3332 i915_gem_object_create_stolen(struct drm_device
*dev
, u32 size
);
3333 struct drm_i915_gem_object
*
3334 i915_gem_object_create_stolen_for_preallocated(struct drm_device
*dev
,
3339 /* i915_gem_shrinker.c */
3340 unsigned long i915_gem_shrink(struct drm_i915_private
*dev_priv
,
3341 unsigned long target
,
3343 #define I915_SHRINK_PURGEABLE 0x1
3344 #define I915_SHRINK_UNBOUND 0x2
3345 #define I915_SHRINK_BOUND 0x4
3346 #define I915_SHRINK_ACTIVE 0x8
3347 #define I915_SHRINK_VMAPS 0x10
3348 unsigned long i915_gem_shrink_all(struct drm_i915_private
*dev_priv
);
3349 void i915_gem_shrinker_init(struct drm_i915_private
*dev_priv
);
3350 void i915_gem_shrinker_cleanup(struct drm_i915_private
*dev_priv
);
3353 /* i915_gem_tiling.c */
3354 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object
*obj
)
3356 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
3358 return dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_9_10_17
&&
3359 obj
->tiling_mode
!= I915_TILING_NONE
;
3362 /* i915_gem_debug.c */
3364 int i915_verify_lists(struct drm_device
*dev
);
3366 #define i915_verify_lists(dev) 0
3369 /* i915_debugfs.c */
3370 int i915_debugfs_init(struct drm_minor
*minor
);
3371 void i915_debugfs_cleanup(struct drm_minor
*minor
);
3372 #ifdef CONFIG_DEBUG_FS
3373 int i915_debugfs_connector_add(struct drm_connector
*connector
);
3374 void intel_display_crc_init(struct drm_device
*dev
);
3376 static inline int i915_debugfs_connector_add(struct drm_connector
*connector
)
3378 static inline void intel_display_crc_init(struct drm_device
*dev
) {}
3381 /* i915_gpu_error.c */
3383 void i915_error_printf(struct drm_i915_error_state_buf
*e
, const char *f
, ...);
3384 int i915_error_state_to_str(struct drm_i915_error_state_buf
*estr
,
3385 const struct i915_error_state_file_priv
*error
);
3386 int i915_error_state_buf_init(struct drm_i915_error_state_buf
*eb
,
3387 struct drm_i915_private
*i915
,
3388 size_t count
, loff_t pos
);
3389 static inline void i915_error_state_buf_release(
3390 struct drm_i915_error_state_buf
*eb
)
3394 void i915_capture_error_state(struct drm_device
*dev
, u32 engine_mask
,
3395 const char *error_msg
);
3396 void i915_error_state_get(struct drm_device
*dev
,
3397 struct i915_error_state_file_priv
*error_priv
);
3398 void i915_error_state_put(struct i915_error_state_file_priv
*error_priv
);
3399 void i915_destroy_error_state(struct drm_device
*dev
);
3401 void i915_get_extra_instdone(struct drm_device
*dev
, uint32_t *instdone
);
3402 const char *i915_cache_level_str(struct drm_i915_private
*i915
, int type
);
3404 /* i915_cmd_parser.c */
3405 int i915_cmd_parser_get_version(void);
3406 int i915_cmd_parser_init_ring(struct intel_engine_cs
*engine
);
3407 void i915_cmd_parser_fini_ring(struct intel_engine_cs
*engine
);
3408 bool i915_needs_cmd_parser(struct intel_engine_cs
*engine
);
3409 int i915_parse_cmds(struct intel_engine_cs
*engine
,
3410 struct drm_i915_gem_object
*batch_obj
,
3411 struct drm_i915_gem_object
*shadow_batch_obj
,
3412 u32 batch_start_offset
,
3416 /* i915_suspend.c */
3417 extern int i915_save_state(struct drm_device
*dev
);
3418 extern int i915_restore_state(struct drm_device
*dev
);
3421 void i915_setup_sysfs(struct drm_device
*dev_priv
);
3422 void i915_teardown_sysfs(struct drm_device
*dev_priv
);
3425 extern int intel_setup_gmbus(struct drm_device
*dev
);
3426 extern void intel_teardown_gmbus(struct drm_device
*dev
);
3427 extern bool intel_gmbus_is_valid_pin(struct drm_i915_private
*dev_priv
,
3430 extern struct i2c_adapter
*
3431 intel_gmbus_get_adapter(struct drm_i915_private
*dev_priv
, unsigned int pin
);
3432 extern void intel_gmbus_set_speed(struct i2c_adapter
*adapter
, int speed
);
3433 extern void intel_gmbus_force_bit(struct i2c_adapter
*adapter
, bool force_bit
);
3434 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter
*adapter
)
3436 return container_of(adapter
, struct intel_gmbus
, adapter
)->force_bit
;
3438 extern void intel_i2c_reset(struct drm_device
*dev
);
3441 int intel_bios_init(struct drm_i915_private
*dev_priv
);
3442 bool intel_bios_is_valid_vbt(const void *buf
, size_t size
);
3443 bool intel_bios_is_tv_present(struct drm_i915_private
*dev_priv
);
3444 bool intel_bios_is_lvds_present(struct drm_i915_private
*dev_priv
, u8
*i2c_pin
);
3445 bool intel_bios_is_port_edp(struct drm_i915_private
*dev_priv
, enum port port
);
3446 bool intel_bios_is_dsi_present(struct drm_i915_private
*dev_priv
, enum port
*port
);
3447 bool intel_bios_is_port_hpd_inverted(struct drm_i915_private
*dev_priv
,
3450 /* intel_opregion.c */
3452 extern int intel_opregion_setup(struct drm_device
*dev
);
3453 extern void intel_opregion_init(struct drm_device
*dev
);
3454 extern void intel_opregion_fini(struct drm_device
*dev
);
3455 extern void intel_opregion_asle_intr(struct drm_device
*dev
);
3456 extern int intel_opregion_notify_encoder(struct intel_encoder
*intel_encoder
,
3458 extern int intel_opregion_notify_adapter(struct drm_device
*dev
,
3460 extern int intel_opregion_get_panel_type(struct drm_device
*dev
);
3462 static inline int intel_opregion_setup(struct drm_device
*dev
) { return 0; }
3463 static inline void intel_opregion_init(struct drm_device
*dev
) { return; }
3464 static inline void intel_opregion_fini(struct drm_device
*dev
) { return; }
3465 static inline void intel_opregion_asle_intr(struct drm_device
*dev
) { return; }
3467 intel_opregion_notify_encoder(struct intel_encoder
*intel_encoder
, bool enable
)
3472 intel_opregion_notify_adapter(struct drm_device
*dev
, pci_power_t state
)
3476 static inline int intel_opregion_get_panel_type(struct drm_device
*dev
)
3484 extern void intel_register_dsm_handler(void);
3485 extern void intel_unregister_dsm_handler(void);
3487 static inline void intel_register_dsm_handler(void) { return; }
3488 static inline void intel_unregister_dsm_handler(void) { return; }
3489 #endif /* CONFIG_ACPI */
3492 extern void intel_modeset_init_hw(struct drm_device
*dev
);
3493 extern void intel_modeset_init(struct drm_device
*dev
);
3494 extern void intel_modeset_gem_init(struct drm_device
*dev
);
3495 extern void intel_modeset_cleanup(struct drm_device
*dev
);
3496 extern void intel_connector_unregister(struct intel_connector
*);
3497 extern int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
);
3498 extern void intel_display_resume(struct drm_device
*dev
);
3499 extern void i915_redisable_vga(struct drm_device
*dev
);
3500 extern void i915_redisable_vga_power_on(struct drm_device
*dev
);
3501 extern bool ironlake_set_drps(struct drm_device
*dev
, u8 val
);
3502 extern void intel_init_pch_refclk(struct drm_device
*dev
);
3503 extern void intel_set_rps(struct drm_device
*dev
, u8 val
);
3504 extern void intel_set_memory_cxsr(struct drm_i915_private
*dev_priv
,
3506 extern void intel_detect_pch(struct drm_device
*dev
);
3507 extern int intel_enable_rc6(const struct drm_device
*dev
);
3509 extern bool i915_semaphore_is_enabled(struct drm_device
*dev
);
3510 int i915_reg_read_ioctl(struct drm_device
*dev
, void *data
,
3511 struct drm_file
*file
);
3512 int i915_get_reset_stats_ioctl(struct drm_device
*dev
, void *data
,
3513 struct drm_file
*file
);
3516 extern struct intel_overlay_error_state
*intel_overlay_capture_error_state(struct drm_device
*dev
);
3517 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf
*e
,
3518 struct intel_overlay_error_state
*error
);
3520 extern struct intel_display_error_state
*intel_display_capture_error_state(struct drm_device
*dev
);
3521 extern void intel_display_print_error_state(struct drm_i915_error_state_buf
*e
,
3522 struct drm_device
*dev
,
3523 struct intel_display_error_state
*error
);
3525 int sandybridge_pcode_read(struct drm_i915_private
*dev_priv
, u32 mbox
, u32
*val
);
3526 int sandybridge_pcode_write(struct drm_i915_private
*dev_priv
, u32 mbox
, u32 val
);
3528 /* intel_sideband.c */
3529 u32
vlv_punit_read(struct drm_i915_private
*dev_priv
, u32 addr
);
3530 void vlv_punit_write(struct drm_i915_private
*dev_priv
, u32 addr
, u32 val
);
3531 u32
vlv_nc_read(struct drm_i915_private
*dev_priv
, u8 addr
);
3532 u32
vlv_iosf_sb_read(struct drm_i915_private
*dev_priv
, u8 port
, u32 reg
);
3533 void vlv_iosf_sb_write(struct drm_i915_private
*dev_priv
, u8 port
, u32 reg
, u32 val
);
3534 u32
vlv_cck_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3535 void vlv_cck_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3536 u32
vlv_ccu_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3537 void vlv_ccu_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3538 u32
vlv_bunit_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3539 void vlv_bunit_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3540 u32
vlv_dpio_read(struct drm_i915_private
*dev_priv
, enum pipe pipe
, int reg
);
3541 void vlv_dpio_write(struct drm_i915_private
*dev_priv
, enum pipe pipe
, int reg
, u32 val
);
3542 u32
intel_sbi_read(struct drm_i915_private
*dev_priv
, u16 reg
,
3543 enum intel_sbi_destination destination
);
3544 void intel_sbi_write(struct drm_i915_private
*dev_priv
, u16 reg
, u32 value
,
3545 enum intel_sbi_destination destination
);
3546 u32
vlv_flisdsi_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3547 void vlv_flisdsi_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3549 int intel_gpu_freq(struct drm_i915_private
*dev_priv
, int val
);
3550 int intel_freq_opcode(struct drm_i915_private
*dev_priv
, int val
);
3552 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3553 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3555 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3556 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3557 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3558 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
3560 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3561 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3562 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3563 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3565 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
3566 * will be implemented using 2 32-bit writes in an arbitrary order with
3567 * an arbitrary delay between them. This can cause the hardware to
3568 * act upon the intermediate value, possibly leading to corruption and
3569 * machine death. You have been warned.
3571 #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
3572 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3574 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
3575 u32 upper, lower, old_upper, loop = 0; \
3576 upper = I915_READ(upper_reg); \
3578 old_upper = upper; \
3579 lower = I915_READ(lower_reg); \
3580 upper = I915_READ(upper_reg); \
3581 } while (upper != old_upper && loop++ < 2); \
3582 (u64)upper << 32 | lower; })
3584 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3585 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
3587 #define __raw_read(x, s) \
3588 static inline uint##x##_t __raw_i915_read##x(struct drm_i915_private *dev_priv, \
3591 return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
3594 #define __raw_write(x, s) \
3595 static inline void __raw_i915_write##x(struct drm_i915_private *dev_priv, \
3596 i915_reg_t reg, uint##x##_t val) \
3598 write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
3613 /* These are untraced mmio-accessors that are only valid to be used inside
3614 * criticial sections inside IRQ handlers where forcewake is explicitly
3616 * Think twice, and think again, before using these.
3617 * Note: Should only be used between intel_uncore_forcewake_irqlock() and
3618 * intel_uncore_forcewake_irqunlock().
3620 #define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
3621 #define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
3622 #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
3624 /* "Broadcast RGB" property */
3625 #define INTEL_BROADCAST_RGB_AUTO 0
3626 #define INTEL_BROADCAST_RGB_FULL 1
3627 #define INTEL_BROADCAST_RGB_LIMITED 2
3629 static inline i915_reg_t
i915_vgacntrl_reg(struct drm_device
*dev
)
3631 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
))
3632 return VLV_VGACNTRL
;
3633 else if (INTEL_INFO(dev
)->gen
>= 5)
3634 return CPU_VGACNTRL
;
3639 static inline void __user
*to_user_ptr(u64 address
)
3641 return (void __user
*)(uintptr_t)address
;
3644 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m
)
3646 unsigned long j
= msecs_to_jiffies(m
);
3648 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);
3651 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n
)
3653 return min_t(u64
, MAX_JIFFY_OFFSET
, nsecs_to_jiffies64(n
) + 1);
3656 static inline unsigned long
3657 timespec_to_jiffies_timeout(const struct timespec
*value
)
3659 unsigned long j
= timespec_to_jiffies(value
);
3661 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);
3665 * If you need to wait X milliseconds between events A and B, but event B
3666 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
3667 * when event A happened, then just before event B you call this function and
3668 * pass the timestamp as the first argument, and X as the second argument.
3671 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies
, int to_wait_ms
)
3673 unsigned long target_jiffies
, tmp_jiffies
, remaining_jiffies
;
3676 * Don't re-read the value of "jiffies" every time since it may change
3677 * behind our back and break the math.
3679 tmp_jiffies
= jiffies
;
3680 target_jiffies
= timestamp_jiffies
+
3681 msecs_to_jiffies_timeout(to_wait_ms
);
3683 if (time_after(target_jiffies
, tmp_jiffies
)) {
3684 remaining_jiffies
= target_jiffies
- tmp_jiffies
;
3685 while (remaining_jiffies
)
3687 schedule_timeout_uninterruptible(remaining_jiffies
);
3691 static inline void i915_trace_irq_get(struct intel_engine_cs
*engine
,
3692 struct drm_i915_gem_request
*req
)
3694 if (engine
->trace_irq_req
== NULL
&& engine
->irq_get(engine
))
3695 i915_gem_request_assign(&engine
->trace_irq_req
, req
);