drivers/gpu/drm/i915/i915_drv.h

   1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #ifndef _I915_DRV_H_
  31 #define _I915_DRV_H_
  32
  33 #include "i915_reg.h"
  34 #include "intel_bios.h"
  35 #include "intel_ringbuffer.h"
  36 #include <linux/io-mapping.h>
  37 #include <linux/i2c.h>
  38 #include <linux/i2c-algo-bit.h>
  39 #include <drm/intel-gtt.h>
  40 #include <linux/backlight.h>
  41 #include <linux/intel-iommu.h>
  42 #include <linux/kref.h>
  43
  44 /* General customization:
  45  */
  46
  47 #define DRIVER_AUTHOR           "Tungsten Graphics, Inc."
  48
  49 #define DRIVER_NAME             "i915"
  50 #define DRIVER_DESC             "Intel Graphics"
  51 #define DRIVER_DATE             "20080730"
  52
  53 enum pipe {
  54         PIPE_A = 0,
  55         PIPE_B,
  56         PIPE_C,
  57         I915_MAX_PIPES
  58 };
  59 #define pipe_name(p) ((p) + 'A')
  60
  61 enum transcoder {
  62         TRANSCODER_A = 0,
  63         TRANSCODER_B,
  64         TRANSCODER_C,
  65         TRANSCODER_EDP = 0xF,
  66 };
  67 #define transcoder_name(t) ((t) + 'A')
  68
  69 enum plane {
  70         PLANE_A = 0,
  71         PLANE_B,
  72         PLANE_C,
  73 };
  74 #define plane_name(p) ((p) + 'A')
  75
  76 enum port {
  77         PORT_A = 0,
  78         PORT_B,
  79         PORT_C,
  80         PORT_D,
  81         PORT_E,
  82         I915_MAX_PORTS
  83 };
  84 #define port_name(p) ((p) + 'A')
  85
  86 #define I915_GEM_GPU_DOMAINS    (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
  87
  88 #define for_each_pipe(p) for ((p) = 0; (p) < dev_priv->num_pipe; (p)++)
  89
  90 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
  91         list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
  92                 if ((intel_encoder)->base.crtc == (__crtc))
  93
  94 struct intel_pch_pll {
  95         int refcount; /* count of number of CRTCs sharing this PLL */
  96         int active; /* count of number of active CRTCs (i.e. DPMS on) */
  97         bool on; /* is the PLL actually active? Disabled during modeset */
  98         int pll_reg;
  99         int fp0_reg;
 100         int fp1_reg;
 101 };
 102 #define I915_NUM_PLLS 2
 103
 104 struct intel_ddi_plls {
 105         int spll_refcount;
 106         int wrpll1_refcount;
 107         int wrpll2_refcount;
 108 };
 109
 110 /* Interface history:
 111  *
 112  * 1.1: Original.
 113  * 1.2: Add Power Management
 114  * 1.3: Add vblank support
 115  * 1.4: Fix cmdbuffer path, add heap destroy
 116  * 1.5: Add vblank pipe configuration
 117  * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
 118  *      - Support vertical blank on secondary display pipe
 119  */
 120 #define DRIVER_MAJOR            1
 121 #define DRIVER_MINOR            6
 122 #define DRIVER_PATCHLEVEL       0
 123
 124 #define WATCH_COHERENCY 0
 125 #define WATCH_LISTS     0
 126 #define WATCH_GTT       0
 127
 128 #define I915_GEM_PHYS_CURSOR_0 1
 129 #define I915_GEM_PHYS_CURSOR_1 2
 130 #define I915_GEM_PHYS_OVERLAY_REGS 3
 131 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
 132
 133 struct drm_i915_gem_phys_object {
 134         int id;
 135         struct page **page_list;
 136         drm_dma_handle_t *handle;
 137         struct drm_i915_gem_object *cur_obj;
 138 };
 139
 140 struct opregion_header;
 141 struct opregion_acpi;
 142 struct opregion_swsci;
 143 struct opregion_asle;
 144 struct drm_i915_private;
 145
 146 struct intel_opregion {
 147         struct opregion_header __iomem *header;
 148         struct opregion_acpi __iomem *acpi;
 149         struct opregion_swsci __iomem *swsci;
 150         struct opregion_asle __iomem *asle;
 151         void __iomem *vbt;
 152         u32 __iomem *lid_state;
 153 };
 154 #define OPREGION_SIZE            (8*1024)
 155
 156 struct intel_overlay;
 157 struct intel_overlay_error_state;
 158
 159 struct drm_i915_master_private {
 160         drm_local_map_t *sarea;
 161         struct _drm_i915_sarea *sarea_priv;
 162 };
 163 #define I915_FENCE_REG_NONE -1
 164 #define I915_MAX_NUM_FENCES 16
 165 /* 16 fences + sign bit for FENCE_REG_NONE */
 166 #define I915_MAX_NUM_FENCE_BITS 5
 167
 168 struct drm_i915_fence_reg {
 169         struct list_head lru_list;
 170         struct drm_i915_gem_object *obj;
 171         int pin_count;
 172 };
 173
 174 struct sdvo_device_mapping {
 175         u8 initialized;
 176         u8 dvo_port;
 177         u8 slave_addr;
 178         u8 dvo_wiring;
 179         u8 i2c_pin;
 180         u8 ddc_pin;
 181 };
 182
 183 struct intel_display_error_state;
 184
 185 struct drm_i915_error_state {
 186         struct kref ref;
 187         u32 eir;
 188         u32 pgtbl_er;
 189         u32 ier;
 190         u32 ccid;
 191         bool waiting[I915_NUM_RINGS];
 192         u32 pipestat[I915_MAX_PIPES];
 193         u32 tail[I915_NUM_RINGS];
 194         u32 head[I915_NUM_RINGS];
 195         u32 ipeir[I915_NUM_RINGS];
 196         u32 ipehr[I915_NUM_RINGS];
 197         u32 instdone[I915_NUM_RINGS];
 198         u32 acthd[I915_NUM_RINGS];
 199         u32 semaphore_mboxes[I915_NUM_RINGS][I915_NUM_RINGS - 1];
 200         u32 rc_psmi[I915_NUM_RINGS]; /* sleep state */
 201         /* our own tracking of ring head and tail */
 202         u32 cpu_ring_head[I915_NUM_RINGS];
 203         u32 cpu_ring_tail[I915_NUM_RINGS];
 204         u32 error; /* gen6+ */
 205         u32 err_int; /* gen7 */
 206         u32 instpm[I915_NUM_RINGS];
 207         u32 instps[I915_NUM_RINGS];
 208         u32 extra_instdone[I915_NUM_INSTDONE_REG];
 209         u32 seqno[I915_NUM_RINGS];
 210         u64 bbaddr;
 211         u32 fault_reg[I915_NUM_RINGS];
 212         u32 done_reg;
 213         u32 faddr[I915_NUM_RINGS];
 214         u64 fence[I915_MAX_NUM_FENCES];
 215         struct timeval time;
 216         struct drm_i915_error_ring {
 217                 struct drm_i915_error_object {
 218                         int page_count;
 219                         u32 gtt_offset;
 220                         u32 *pages[0];
 221                 } *ringbuffer, *batchbuffer;
 222                 struct drm_i915_error_request {
 223                         long jiffies;
 224                         u32 seqno;
 225                         u32 tail;
 226                 } *requests;
 227                 int num_requests;
 228         } ring[I915_NUM_RINGS];
 229         struct drm_i915_error_buffer {
 230                 u32 size;
 231                 u32 name;
 232                 u32 rseqno, wseqno;
 233                 u32 gtt_offset;
 234                 u32 read_domains;
 235                 u32 write_domain;
 236                 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
 237                 s32 pinned:2;
 238                 u32 tiling:2;
 239                 u32 dirty:1;
 240                 u32 purgeable:1;
 241                 s32 ring:4;
 242                 u32 cache_level:2;
 243         } *active_bo, *pinned_bo;
 244         u32 active_bo_count, pinned_bo_count;
 245         struct intel_overlay_error_state *overlay;
 246         struct intel_display_error_state *display;
 247 };
 248
 249 struct drm_i915_display_funcs {
 250         bool (*fbc_enabled)(struct drm_device *dev);
 251         void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);
 252         void (*disable_fbc)(struct drm_device *dev);
 253         int (*get_display_clock_speed)(struct drm_device *dev);
 254         int (*get_fifo_size)(struct drm_device *dev, int plane);
 255         void (*update_wm)(struct drm_device *dev);
 256         void (*update_sprite_wm)(struct drm_device *dev, int pipe,
 257                                  uint32_t sprite_width, int pixel_size);
 258         void (*update_linetime_wm)(struct drm_device *dev, int pipe,
 259                                  struct drm_display_mode *mode);
 260         void (*modeset_global_resources)(struct drm_device *dev);
 261         int (*crtc_mode_set)(struct drm_crtc *crtc,
 262                              struct drm_display_mode *mode,
 263                              struct drm_display_mode *adjusted_mode,
 264                              int x, int y,
 265                              struct drm_framebuffer *old_fb);
 266         void (*crtc_enable)(struct drm_crtc *crtc);
 267         void (*crtc_disable)(struct drm_crtc *crtc);
 268         void (*off)(struct drm_crtc *crtc);
 269         void (*write_eld)(struct drm_connector *connector,
 270                           struct drm_crtc *crtc);
 271         void (*fdi_link_train)(struct drm_crtc *crtc);
 272         void (*init_clock_gating)(struct drm_device *dev);
 273         int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
 274                           struct drm_framebuffer *fb,
 275                           struct drm_i915_gem_object *obj);
 276         int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb,
 277                             int x, int y);
 278         /* clock updates for mode set */
 279         /* cursor updates */
 280         /* render clock increase/decrease */
 281         /* display clock increase/decrease */
 282         /* pll clock increase/decrease */
 283 };
 284
 285 struct drm_i915_gt_funcs {
 286         void (*force_wake_get)(struct drm_i915_private *dev_priv);
 287         void (*force_wake_put)(struct drm_i915_private *dev_priv);
 288 };
 289
 290 #define DEV_INFO_FLAGS \
 291         DEV_INFO_FLAG(is_mobile) DEV_INFO_SEP \
 292         DEV_INFO_FLAG(is_i85x) DEV_INFO_SEP \
 293         DEV_INFO_FLAG(is_i915g) DEV_INFO_SEP \
 294         DEV_INFO_FLAG(is_i945gm) DEV_INFO_SEP \
 295         DEV_INFO_FLAG(is_g33) DEV_INFO_SEP \
 296         DEV_INFO_FLAG(need_gfx_hws) DEV_INFO_SEP \
 297         DEV_INFO_FLAG(is_g4x) DEV_INFO_SEP \
 298         DEV_INFO_FLAG(is_pineview) DEV_INFO_SEP \
 299         DEV_INFO_FLAG(is_broadwater) DEV_INFO_SEP \
 300         DEV_INFO_FLAG(is_crestline) DEV_INFO_SEP \
 301         DEV_INFO_FLAG(is_ivybridge) DEV_INFO_SEP \
 302         DEV_INFO_FLAG(is_valleyview) DEV_INFO_SEP \
 303         DEV_INFO_FLAG(is_haswell) DEV_INFO_SEP \
 304         DEV_INFO_FLAG(has_force_wake) DEV_INFO_SEP \
 305         DEV_INFO_FLAG(has_fbc) DEV_INFO_SEP \
 306         DEV_INFO_FLAG(has_pipe_cxsr) DEV_INFO_SEP \
 307         DEV_INFO_FLAG(has_hotplug) DEV_INFO_SEP \
 308         DEV_INFO_FLAG(cursor_needs_physical) DEV_INFO_SEP \
 309         DEV_INFO_FLAG(has_overlay) DEV_INFO_SEP \
 310         DEV_INFO_FLAG(overlay_needs_physical) DEV_INFO_SEP \
 311         DEV_INFO_FLAG(supports_tv) DEV_INFO_SEP \
 312         DEV_INFO_FLAG(has_bsd_ring) DEV_INFO_SEP \
 313         DEV_INFO_FLAG(has_blt_ring) DEV_INFO_SEP \
 314         DEV_INFO_FLAG(has_llc)
 315
 316 struct intel_device_info {
 317         u8 gen;
 318         u8 is_mobile:1;
 319         u8 is_i85x:1;
 320         u8 is_i915g:1;
 321         u8 is_i945gm:1;
 322         u8 is_g33:1;
 323         u8 need_gfx_hws:1;
 324         u8 is_g4x:1;
 325         u8 is_pineview:1;
 326         u8 is_broadwater:1;
 327         u8 is_crestline:1;
 328         u8 is_ivybridge:1;
 329         u8 is_valleyview:1;
 330         u8 has_force_wake:1;
 331         u8 is_haswell:1;
 332         u8 has_fbc:1;
 333         u8 has_pipe_cxsr:1;
 334         u8 has_hotplug:1;
 335         u8 cursor_needs_physical:1;
 336         u8 has_overlay:1;
 337         u8 overlay_needs_physical:1;
 338         u8 supports_tv:1;
 339         u8 has_bsd_ring:1;
 340         u8 has_blt_ring:1;
 341         u8 has_llc:1;
 342 };
 343
 344 #define I915_PPGTT_PD_ENTRIES 512
 345 #define I915_PPGTT_PT_ENTRIES 1024
 346 struct i915_hw_ppgtt {
 347         struct drm_device *dev;
 348         unsigned num_pd_entries;
 349         struct page **pt_pages;
 350         uint32_t pd_offset;
 351         dma_addr_t *pt_dma_addr;
 352         dma_addr_t scratch_page_dma_addr;
 353 };
 354
 355
 356 /* This must match up with the value previously used for execbuf2.rsvd1. */
 357 #define DEFAULT_CONTEXT_ID 0
 358 struct i915_hw_context {
 359         int id;
 360         bool is_initialized;
 361         struct drm_i915_file_private *file_priv;
 362         struct intel_ring_buffer *ring;
 363         struct drm_i915_gem_object *obj;
 364 };
 365
 366 enum no_fbc_reason {
 367         FBC_NO_OUTPUT, /* no outputs enabled to compress */
 368         FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */
 369         FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
 370         FBC_MODE_TOO_LARGE, /* mode too large for compression */
 371         FBC_BAD_PLANE, /* fbc not supported on plane */
 372         FBC_NOT_TILED, /* buffer not tiled */
 373         FBC_MULTIPLE_PIPES, /* more than one pipe active */
 374         FBC_MODULE_PARAM,
 375 };
 376
 377 enum intel_pch {
 378         PCH_NONE = 0,   /* No PCH present */
 379         PCH_IBX,        /* Ibexpeak PCH */
 380         PCH_CPT,        /* Cougarpoint PCH */
 381         PCH_LPT,        /* Lynxpoint PCH */
 382 };
 383
 384 #define QUIRK_PIPEA_FORCE (1<<0)
 385 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
 386 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
 387
 388 struct intel_fbdev;
 389 struct intel_fbc_work;
 390
 391 struct intel_gmbus {
 392         struct i2c_adapter adapter;
 393         bool force_bit;
 394         u32 reg0;
 395         u32 gpio_reg;
 396         struct i2c_algo_bit_data bit_algo;
 397         struct drm_i915_private *dev_priv;
 398 };
 399
 400 struct i915_suspend_saved_registers {
 401         u8 saveLBB;
 402         u32 saveDSPACNTR;
 403         u32 saveDSPBCNTR;
 404         u32 saveDSPARB;
 405         u32 saveHWS;
 406         u32 savePIPEACONF;
 407         u32 savePIPEBCONF;
 408         u32 savePIPEASRC;
 409         u32 savePIPEBSRC;
 410         u32 saveFPA0;
 411         u32 saveFPA1;
 412         u32 saveDPLL_A;
 413         u32 saveDPLL_A_MD;
 414         u32 saveHTOTAL_A;
 415         u32 saveHBLANK_A;
 416         u32 saveHSYNC_A;
 417         u32 saveVTOTAL_A;
 418         u32 saveVBLANK_A;
 419         u32 saveVSYNC_A;
 420         u32 saveBCLRPAT_A;
 421         u32 saveTRANSACONF;
 422         u32 saveTRANS_HTOTAL_A;
 423         u32 saveTRANS_HBLANK_A;
 424         u32 saveTRANS_HSYNC_A;
 425         u32 saveTRANS_VTOTAL_A;
 426         u32 saveTRANS_VBLANK_A;
 427         u32 saveTRANS_VSYNC_A;
 428         u32 savePIPEASTAT;
 429         u32 saveDSPASTRIDE;
 430         u32 saveDSPASIZE;
 431         u32 saveDSPAPOS;
 432         u32 saveDSPAADDR;
 433         u32 saveDSPASURF;
 434         u32 saveDSPATILEOFF;
 435         u32 savePFIT_PGM_RATIOS;
 436         u32 saveBLC_HIST_CTL;
 437         u32 saveBLC_PWM_CTL;
 438         u32 saveBLC_PWM_CTL2;
 439         u32 saveBLC_CPU_PWM_CTL;
 440         u32 saveBLC_CPU_PWM_CTL2;
 441         u32 saveFPB0;
 442         u32 saveFPB1;
 443         u32 saveDPLL_B;
 444         u32 saveDPLL_B_MD;
 445         u32 saveHTOTAL_B;
 446         u32 saveHBLANK_B;
 447         u32 saveHSYNC_B;
 448         u32 saveVTOTAL_B;
 449         u32 saveVBLANK_B;
 450         u32 saveVSYNC_B;
 451         u32 saveBCLRPAT_B;
 452         u32 saveTRANSBCONF;
 453         u32 saveTRANS_HTOTAL_B;
 454         u32 saveTRANS_HBLANK_B;
 455         u32 saveTRANS_HSYNC_B;
 456         u32 saveTRANS_VTOTAL_B;
 457         u32 saveTRANS_VBLANK_B;
 458         u32 saveTRANS_VSYNC_B;
 459         u32 savePIPEBSTAT;
 460         u32 saveDSPBSTRIDE;
 461         u32 saveDSPBSIZE;
 462         u32 saveDSPBPOS;
 463         u32 saveDSPBADDR;
 464         u32 saveDSPBSURF;
 465         u32 saveDSPBTILEOFF;
 466         u32 saveVGA0;
 467         u32 saveVGA1;
 468         u32 saveVGA_PD;
 469         u32 saveVGACNTRL;
 470         u32 saveADPA;
 471         u32 saveLVDS;
 472         u32 savePP_ON_DELAYS;
 473         u32 savePP_OFF_DELAYS;
 474         u32 saveDVOA;
 475         u32 saveDVOB;
 476         u32 saveDVOC;
 477         u32 savePP_ON;
 478         u32 savePP_OFF;
 479         u32 savePP_CONTROL;
 480         u32 savePP_DIVISOR;
 481         u32 savePFIT_CONTROL;
 482         u32 save_palette_a[256];
 483         u32 save_palette_b[256];
 484         u32 saveDPFC_CB_BASE;
 485         u32 saveFBC_CFB_BASE;
 486         u32 saveFBC_LL_BASE;
 487         u32 saveFBC_CONTROL;
 488         u32 saveFBC_CONTROL2;
 489         u32 saveIER;
 490         u32 saveIIR;
 491         u32 saveIMR;
 492         u32 saveDEIER;
 493         u32 saveDEIMR;
 494         u32 saveGTIER;
 495         u32 saveGTIMR;
 496         u32 saveFDI_RXA_IMR;
 497         u32 saveFDI_RXB_IMR;
 498         u32 saveCACHE_MODE_0;
 499         u32 saveMI_ARB_STATE;
 500         u32 saveSWF0[16];
 501         u32 saveSWF1[16];
 502         u32 saveSWF2[3];
 503         u8 saveMSR;
 504         u8 saveSR[8];
 505         u8 saveGR[25];
 506         u8 saveAR_INDEX;
 507         u8 saveAR[21];
 508         u8 saveDACMASK;
 509         u8 saveCR[37];
 510         uint64_t saveFENCE[I915_MAX_NUM_FENCES];
 511         u32 saveCURACNTR;
 512         u32 saveCURAPOS;
 513         u32 saveCURABASE;
 514         u32 saveCURBCNTR;
 515         u32 saveCURBPOS;
 516         u32 saveCURBBASE;
 517         u32 saveCURSIZE;
 518         u32 saveDP_B;
 519         u32 saveDP_C;
 520         u32 saveDP_D;
 521         u32 savePIPEA_GMCH_DATA_M;
 522         u32 savePIPEB_GMCH_DATA_M;
 523         u32 savePIPEA_GMCH_DATA_N;
 524         u32 savePIPEB_GMCH_DATA_N;
 525         u32 savePIPEA_DP_LINK_M;
 526         u32 savePIPEB_DP_LINK_M;
 527         u32 savePIPEA_DP_LINK_N;
 528         u32 savePIPEB_DP_LINK_N;
 529         u32 saveFDI_RXA_CTL;
 530         u32 saveFDI_TXA_CTL;
 531         u32 saveFDI_RXB_CTL;
 532         u32 saveFDI_TXB_CTL;
 533         u32 savePFA_CTL_1;
 534         u32 savePFB_CTL_1;
 535         u32 savePFA_WIN_SZ;
 536         u32 savePFB_WIN_SZ;
 537         u32 savePFA_WIN_POS;
 538         u32 savePFB_WIN_POS;
 539         u32 savePCH_DREF_CONTROL;
 540         u32 saveDISP_ARB_CTL;
 541         u32 savePIPEA_DATA_M1;
 542         u32 savePIPEA_DATA_N1;
 543         u32 savePIPEA_LINK_M1;
 544         u32 savePIPEA_LINK_N1;
 545         u32 savePIPEB_DATA_M1;
 546         u32 savePIPEB_DATA_N1;
 547         u32 savePIPEB_LINK_M1;
 548         u32 savePIPEB_LINK_N1;
 549         u32 saveMCHBAR_RENDER_STANDBY;
 550         u32 savePCH_PORT_HOTPLUG;
 551 };
 552
 553 struct intel_gen6_power_mgmt {
 554         struct work_struct work;
 555         u32 pm_iir;
 556         /* lock - irqsave spinlock that protectects the work_struct and
 557          * pm_iir. */
 558         spinlock_t lock;
 559
 560         /* The below variables an all the rps hw state are protected by
 561          * dev->struct mutext. */
 562         u8 cur_delay;
 563         u8 min_delay;
 564         u8 max_delay;
 565 };
 566
 567 struct intel_ilk_power_mgmt {
 568         u8 cur_delay;
 569         u8 min_delay;
 570         u8 max_delay;
 571         u8 fmax;
 572         u8 fstart;
 573
 574         u64 last_count1;
 575         unsigned long last_time1;
 576         unsigned long chipset_power;
 577         u64 last_count2;
 578         struct timespec last_time2;
 579         unsigned long gfx_power;
 580         u8 corr;
 581
 582         int c_m;
 583         int r_t;
 584
 585         struct drm_i915_gem_object *pwrctx;
 586         struct drm_i915_gem_object *renderctx;
 587 };
 588
 589 struct i915_dri1_state {
 590         unsigned allow_batchbuffer : 1;
 591         u32 __iomem *gfx_hws_cpu_addr;
 592
 593         unsigned int cpp;
 594         int back_offset;
 595         int front_offset;
 596         int current_page;
 597         int page_flipping;
 598
 599         uint32_t counter;
 600 };
 601
 602 struct intel_l3_parity {
 603         u32 *remap_info;
 604         struct work_struct error_work;
 605 };
 606
 607 typedef struct drm_i915_private {
 608         struct drm_device *dev;
 609
 610         const struct intel_device_info *info;
 611
 612         int relative_constants_mode;
 613
 614         void __iomem *regs;
 615
 616         struct drm_i915_gt_funcs gt;
 617         /** gt_fifo_count and the subsequent register write are synchronized
 618          * with dev->struct_mutex. */
 619         unsigned gt_fifo_count;
 620         /** forcewake_count is protected by gt_lock */
 621         unsigned forcewake_count;
 622         /** gt_lock is also taken in irq contexts. */
 623         struct spinlock gt_lock;
 624
 625         struct intel_gmbus gmbus[GMBUS_NUM_PORTS];
 626
 627         /** gmbus_mutex protects against concurrent usage of the single hw gmbus
 628          * controller on different i2c buses. */
 629         struct mutex gmbus_mutex;
 630
 631         /**
 632          * Base address of the gmbus and gpio block.
 633          */
 634         uint32_t gpio_mmio_base;
 635
 636         struct pci_dev *bridge_dev;
 637         struct intel_ring_buffer ring[I915_NUM_RINGS];
 638         uint32_t next_seqno;
 639
 640         drm_dma_handle_t *status_page_dmah;
 641         struct resource mch_res;
 642
 643         atomic_t irq_received;
 644
 645         /* protects the irq masks */
 646         spinlock_t irq_lock;
 647
 648         /* DPIO indirect register protection */
 649         spinlock_t dpio_lock;
 650
 651         /** Cached value of IMR to avoid reads in updating the bitfield */
 652         u32 pipestat[2];
 653         u32 irq_mask;
 654         u32 gt_irq_mask;
 655         u32 pch_irq_mask;
 656
 657         u32 hotplug_supported_mask;
 658         struct work_struct hotplug_work;
 659
 660         int num_pipe;
 661         int num_pch_pll;
 662
 663         /* For hangcheck timer */
 664 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
 665 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
 666         struct timer_list hangcheck_timer;
 667         int hangcheck_count;
 668         uint32_t last_acthd[I915_NUM_RINGS];
 669         uint32_t prev_instdone[I915_NUM_INSTDONE_REG];
 670
 671         unsigned int stop_rings;
 672
 673         unsigned long cfb_size;
 674         unsigned int cfb_fb;
 675         enum plane cfb_plane;
 676         int cfb_y;
 677         struct intel_fbc_work *fbc_work;
 678
 679         struct intel_opregion opregion;
 680
 681         /* overlay */
 682         struct intel_overlay *overlay;
 683         bool sprite_scaling_enabled;
 684
 685         /* LVDS info */
 686         int backlight_level;  /* restore backlight to this value */
 687         bool backlight_enabled;
 688         struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
 689         struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
 690
 691         /* Feature bits from the VBIOS */
 692         unsigned int int_tv_support:1;
 693         unsigned int lvds_dither:1;
 694         unsigned int lvds_vbt:1;
 695         unsigned int int_crt_support:1;
 696         unsigned int lvds_use_ssc:1;
 697         unsigned int display_clock_mode:1;
 698         int lvds_ssc_freq;
 699         unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
 700         unsigned int lvds_val; /* used for checking LVDS channel mode */
 701         struct {
 702                 int rate;
 703                 int lanes;
 704                 int preemphasis;
 705                 int vswing;
 706
 707                 bool initialized;
 708                 bool support;
 709                 int bpp;
 710                 struct edp_power_seq pps;
 711         } edp;
 712         bool no_aux_handshake;
 713
 714         int crt_ddc_pin;
 715         struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
 716         int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
 717         int num_fence_regs; /* 8 on pre-965, 16 otherwise */
 718
 719         unsigned int fsb_freq, mem_freq, is_ddr3;
 720
 721         spinlock_t error_lock;
 722         /* Protected by dev->error_lock. */
 723         struct drm_i915_error_state *first_error;
 724         struct work_struct error_work;
 725         struct completion error_completion;
 726         struct workqueue_struct *wq;
 727
 728         /* Display functions */
 729         struct drm_i915_display_funcs display;
 730
 731         /* PCH chipset type */
 732         enum intel_pch pch_type;
 733
 734         unsigned long quirks;
 735
 736         /* Register state */
 737         bool modeset_on_lid;
 738
 739         struct {
 740                 /** Bridge to intel-gtt-ko */
 741                 const struct intel_gtt *gtt;
 742                 /** Memory allocator for GTT stolen memory */
 743                 struct drm_mm stolen;
 744                 /** Memory allocator for GTT */
 745                 struct drm_mm gtt_space;
 746                 /** List of all objects in gtt_space. Used to restore gtt
 747                  * mappings on resume */
 748                 struct list_head bound_list;
 749                 /**
 750                  * List of objects which are not bound to the GTT (thus
 751                  * are idle and not used by the GPU) but still have
 752                  * (presumably uncached) pages still attached.
 753                  */
 754                 struct list_head unbound_list;
 755
 756                 /** Usable portion of the GTT for GEM */
 757                 unsigned long gtt_start;
 758                 unsigned long gtt_mappable_end;
 759                 unsigned long gtt_end;
 760
 761                 struct io_mapping *gtt_mapping;
 762                 phys_addr_t gtt_base_addr;
 763                 int gtt_mtrr;
 764
 765                 /** PPGTT used for aliasing the PPGTT with the GTT */
 766                 struct i915_hw_ppgtt *aliasing_ppgtt;
 767
 768                 struct shrinker inactive_shrinker;
 769
 770                 /**
 771                  * List of objects currently involved in rendering.
 772                  *
 773                  * Includes buffers having the contents of their GPU caches
 774                  * flushed, not necessarily primitives.  last_rendering_seqno
 775                  * represents when the rendering involved will be completed.
 776                  *
 777                  * A reference is held on the buffer while on this list.
 778                  */
 779                 struct list_head active_list;
 780
 781                 /**
 782                  * LRU list of objects which are not in the ringbuffer and
 783                  * are ready to unbind, but are still in the GTT.
 784                  *
 785                  * last_rendering_seqno is 0 while an object is in this list.
 786                  *
 787                  * A reference is not held on the buffer while on this list,
 788                  * as merely being GTT-bound shouldn't prevent its being
 789                  * freed, and we'll pull it off the list in the free path.
 790                  */
 791                 struct list_head inactive_list;
 792
 793                 /** LRU list of objects with fence regs on them. */
 794                 struct list_head fence_list;
 795
 796                 /**
 797                  * We leave the user IRQ off as much as possible,
 798                  * but this means that requests will finish and never
 799                  * be retired once the system goes idle. Set a timer to
 800                  * fire periodically while the ring is running. When it
 801                  * fires, go retire requests.
 802                  */
 803                 struct delayed_work retire_work;
 804
 805                 /**
 806                  * Are we in a non-interruptible section of code like
 807                  * modesetting?
 808                  */
 809                 bool interruptible;
 810
 811                 /**
 812                  * Flag if the X Server, and thus DRM, is not currently in
 813                  * control of the device.
 814                  *
 815                  * This is set between LeaveVT and EnterVT.  It needs to be
 816                  * replaced with a semaphore.  It also needs to be
 817                  * transitioned away from for kernel modesetting.
 818                  */
 819                 int suspended;
 820
 821                 /**
 822                  * Flag if the hardware appears to be wedged.
 823                  *
 824                  * This is set when attempts to idle the device timeout.
 825                  * It prevents command submission from occurring and makes
 826                  * every pending request fail
 827                  */
 828                 atomic_t wedged;
 829
 830                 /** Bit 6 swizzling required for X tiling */
 831                 uint32_t bit_6_swizzle_x;
 832                 /** Bit 6 swizzling required for Y tiling */
 833                 uint32_t bit_6_swizzle_y;
 834
 835                 /* storage for physical objects */
 836                 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
 837
 838                 /* accounting, useful for userland debugging */
 839                 size_t gtt_total;
 840                 size_t mappable_gtt_total;
 841                 size_t object_memory;
 842                 u32 object_count;
 843         } mm;
 844
 845         /* Kernel Modesetting */
 846
 847         struct sdvo_device_mapping sdvo_mappings[2];
 848         /* indicate whether the LVDS_BORDER should be enabled or not */
 849         unsigned int lvds_border_bits;
 850         /* Panel fitter placement and size for Ironlake+ */
 851         u32 pch_pf_pos, pch_pf_size;
 852
 853         struct drm_crtc *plane_to_crtc_mapping[3];
 854         struct drm_crtc *pipe_to_crtc_mapping[3];
 855         wait_queue_head_t pending_flip_queue;
 856
 857         struct intel_pch_pll pch_plls[I915_NUM_PLLS];
 858         struct intel_ddi_plls ddi_plls;
 859
 860         /* Reclocking support */
 861         bool render_reclock_avail;
 862         bool lvds_downclock_avail;
 863         /* indicates the reduced downclock for LVDS*/
 864         int lvds_downclock;
 865         u16 orig_clock;
 866         int child_dev_num;
 867         struct child_device_config *child_dev;
 868
 869         bool mchbar_need_disable;
 870
 871         struct intel_l3_parity l3_parity;
 872
 873         /* gen6+ rps state */
 874         struct intel_gen6_power_mgmt rps;
 875
 876         /* ilk-only ips/rps state. Everything in here is protected by the global
 877          * mchdev_lock in intel_pm.c */
 878         struct intel_ilk_power_mgmt ips;
 879
 880         enum no_fbc_reason no_fbc_reason;
 881
 882         struct drm_mm_node *compressed_fb;
 883         struct drm_mm_node *compressed_llb;
 884
 885         unsigned long last_gpu_reset;
 886
 887         /* list of fbdev register on this device */
 888         struct intel_fbdev *fbdev;
 889
 890         struct backlight_device *backlight;
 891
 892         struct drm_property *broadcast_rgb_property;
 893         struct drm_property *force_audio_property;
 894
 895         bool hw_contexts_disabled;
 896         uint32_t hw_context_size;
 897
 898         struct i915_suspend_saved_registers regfile;
 899
 900         /* Old dri1 support infrastructure, beware the dragons ya fools entering
 901          * here! */
 902         struct i915_dri1_state dri1;
 903 } drm_i915_private_t;
 904
 905 /* Iterate over initialised rings */
 906 #define for_each_ring(ring__, dev_priv__, i__) \
 907         for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
 908                 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
 909
 910 enum hdmi_force_audio {
 911         HDMI_AUDIO_OFF_DVI = -2,        /* no aux data for HDMI-DVI converter */
 912         HDMI_AUDIO_OFF,                 /* force turn off HDMI audio */
 913         HDMI_AUDIO_AUTO,                /* trust EDID */
 914         HDMI_AUDIO_ON,                  /* force turn on HDMI audio */
 915 };
 916
 917 enum i915_cache_level {
 918         I915_CACHE_NONE = 0,
 919         I915_CACHE_LLC,
 920         I915_CACHE_LLC_MLC, /* gen6+, in docs at least! */
 921 };
 922
 923 struct drm_i915_gem_object_ops {
 924         /* Interface between the GEM object and its backing storage.
 925          * get_pages() is called once prior to the use of the associated set
 926          * of pages before to binding them into the GTT, and put_pages() is
 927          * called after we no longer need them. As we expect there to be
 928          * associated cost with migrating pages between the backing storage
 929          * and making them available for the GPU (e.g. clflush), we may hold
 930          * onto the pages after they are no longer referenced by the GPU
 931          * in case they may be used again shortly (for example migrating the
 932          * pages to a different memory domain within the GTT). put_pages()
 933          * will therefore most likely be called when the object itself is
 934          * being released or under memory pressure (where we attempt to
 935          * reap pages for the shrinker).
 936          */
 937         int (*get_pages)(struct drm_i915_gem_object *);
 938         void (*put_pages)(struct drm_i915_gem_object *);
 939 };
 940
 941 struct drm_i915_gem_object {
 942         struct drm_gem_object base;
 943
 944         const struct drm_i915_gem_object_ops *ops;
 945
 946         /** Current space allocated to this object in the GTT, if any. */
 947         struct drm_mm_node *gtt_space;
 948         struct list_head gtt_list;
 949
 950         /** This object's place on the active/inactive lists */
 951         struct list_head ring_list;
 952         struct list_head mm_list;
 953         /** This object's place in the batchbuffer or on the eviction list */
 954         struct list_head exec_list;
 955
 956         /**
 957          * This is set if the object is on the active lists (has pending
 958          * rendering and so a non-zero seqno), and is not set if it i s on
 959          * inactive (ready to be unbound) list.
 960          */
 961         unsigned int active:1;
 962
 963         /**
 964          * This is set if the object has been written to since last bound
 965          * to the GTT
 966          */
 967         unsigned int dirty:1;
 968
 969         /**
 970          * Fence register bits (if any) for this object.  Will be set
 971          * as needed when mapped into the GTT.
 972          * Protected by dev->struct_mutex.
 973          */
 974         signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
 975
 976         /**
 977          * Advice: are the backing pages purgeable?
 978          */
 979         unsigned int madv:2;
 980
 981         /**
 982          * Current tiling mode for the object.
 983          */
 984         unsigned int tiling_mode:2;
 985         /**
 986          * Whether the tiling parameters for the currently associated fence
 987          * register have changed. Note that for the purposes of tracking
 988          * tiling changes we also treat the unfenced register, the register
 989          * slot that the object occupies whilst it executes a fenced
 990          * command (such as BLT on gen2/3), as a "fence".
 991          */
 992         unsigned int fence_dirty:1;
 993
 994         /** How many users have pinned this object in GTT space. The following
 995          * users can each hold at most one reference: pwrite/pread, pin_ioctl
 996          * (via user_pin_count), execbuffer (objects are not allowed multiple
 997          * times for the same batchbuffer), and the framebuffer code. When
 998          * switching/pageflipping, the framebuffer code has at most two buffers
 999          * pinned per crtc.
1000          *
1001          * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
1002          * bits with absolutely no headroom. So use 4 bits. */
1003         unsigned int pin_count:4;
1004 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
1005
1006         /**
1007          * Is the object at the current location in the gtt mappable and
1008          * fenceable? Used to avoid costly recalculations.
1009          */
1010         unsigned int map_and_fenceable:1;
1011
1012         /**
1013          * Whether the current gtt mapping needs to be mappable (and isn't just
1014          * mappable by accident). Track pin and fault separate for a more
1015          * accurate mappable working set.
1016          */
1017         unsigned int fault_mappable:1;
1018         unsigned int pin_mappable:1;
1019
1020         /*
1021          * Is the GPU currently using a fence to access this buffer,
1022          */
1023         unsigned int pending_fenced_gpu_access:1;
1024         unsigned int fenced_gpu_access:1;
1025
1026         unsigned int cache_level:2;
1027
1028         unsigned int has_aliasing_ppgtt_mapping:1;
1029         unsigned int has_global_gtt_mapping:1;
1030         unsigned int has_dma_mapping:1;
1031
1032         struct sg_table *pages;
1033         int pages_pin_count;
1034
1035         /* prime dma-buf support */
1036         void *dma_buf_vmapping;
1037         int vmapping_count;
1038
1039         /**
1040          * Used for performing relocations during execbuffer insertion.
1041          */
1042         struct hlist_node exec_node;
1043         unsigned long exec_handle;
1044         struct drm_i915_gem_exec_object2 *exec_entry;
1045
1046         /**
1047          * Current offset of the object in GTT space.
1048          *
1049          * This is the same as gtt_space->start
1050          */
1051         uint32_t gtt_offset;
1052
1053         struct intel_ring_buffer *ring;
1054
1055         /** Breadcrumb of last rendering to the buffer. */
1056         uint32_t last_read_seqno;
1057         uint32_t last_write_seqno;
1058         /** Breadcrumb of last fenced GPU access to the buffer. */
1059         uint32_t last_fenced_seqno;
1060
1061         /** Current tiling stride for the object, if it's tiled. */
1062         uint32_t stride;
1063
1064         /** Record of address bit 17 of each page at last unbind. */
1065         unsigned long *bit_17;
1066
1067         /** User space pin count and filp owning the pin */
1068         uint32_t user_pin_count;
1069         struct drm_file *pin_filp;
1070
1071         /** for phy allocated objects */
1072         struct drm_i915_gem_phys_object *phys_obj;
1073
1074         /**
1075          * Number of crtcs where this object is currently the fb, but
1076          * will be page flipped away on the next vblank.  When it
1077          * reaches 0, dev_priv->pending_flip_queue will be woken up.
1078          */
1079         atomic_t pending_flip;
1080 };
1081
1082 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
1083
1084 /**
1085  * Request queue structure.
1086  *
1087  * The request queue allows us to note sequence numbers that have been emitted
1088  * and may be associated with active buffers to be retired.
1089  *
1090  * By keeping this list, we can avoid having to do questionable
1091  * sequence-number comparisons on buffer last_rendering_seqnos, and associate
1092  * an emission time with seqnos for tracking how far ahead of the GPU we are.
1093  */
1094 struct drm_i915_gem_request {
1095         /** On Which ring this request was generated */
1096         struct intel_ring_buffer *ring;
1097
1098         /** GEM sequence number associated with this request. */
1099         uint32_t seqno;
1100
1101         /** Postion in the ringbuffer of the end of the request */
1102         u32 tail;
1103
1104         /** Time at which this request was emitted, in jiffies. */
1105         unsigned long emitted_jiffies;
1106
1107         /** global list entry for this request */
1108         struct list_head list;
1109
1110         struct drm_i915_file_private *file_priv;
1111         /** file_priv list entry for this request */
1112         struct list_head client_list;
1113 };
1114
1115 struct drm_i915_file_private {
1116         struct {
1117                 struct spinlock lock;
1118                 struct list_head request_list;
1119         } mm;
1120         struct idr context_idr;
1121 };
1122
1123 #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
1124
1125 #define IS_I830(dev)            ((dev)->pci_device == 0x3577)
1126 #define IS_845G(dev)            ((dev)->pci_device == 0x2562)
1127 #define IS_I85X(dev)            (INTEL_INFO(dev)->is_i85x)
1128 #define IS_I865G(dev)           ((dev)->pci_device == 0x2572)
1129 #define IS_I915G(dev)           (INTEL_INFO(dev)->is_i915g)
1130 #define IS_I915GM(dev)          ((dev)->pci_device == 0x2592)
1131 #define IS_I945G(dev)           ((dev)->pci_device == 0x2772)
1132 #define IS_I945GM(dev)          (INTEL_INFO(dev)->is_i945gm)
1133 #define IS_BROADWATER(dev)      (INTEL_INFO(dev)->is_broadwater)
1134 #define IS_CRESTLINE(dev)       (INTEL_INFO(dev)->is_crestline)
1135 #define IS_GM45(dev)            ((dev)->pci_device == 0x2A42)
1136 #define IS_G4X(dev)             (INTEL_INFO(dev)->is_g4x)
1137 #define IS_PINEVIEW_G(dev)      ((dev)->pci_device == 0xa001)
1138 #define IS_PINEVIEW_M(dev)      ((dev)->pci_device == 0xa011)
1139 #define IS_PINEVIEW(dev)        (INTEL_INFO(dev)->is_pineview)
1140 #define IS_G33(dev)             (INTEL_INFO(dev)->is_g33)
1141 #define IS_IRONLAKE_D(dev)      ((dev)->pci_device == 0x0042)
1142 #define IS_IRONLAKE_M(dev)      ((dev)->pci_device == 0x0046)
1143 #define IS_IVYBRIDGE(dev)       (INTEL_INFO(dev)->is_ivybridge)
1144 #define IS_IVB_GT1(dev)         ((dev)->pci_device == 0x0156 || \
1145                                  (dev)->pci_device == 0x0152 || \
1146                                  (dev)->pci_device == 0x015a)
1147 #define IS_VALLEYVIEW(dev)      (INTEL_INFO(dev)->is_valleyview)
1148 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
1149 #define IS_MOBILE(dev)          (INTEL_INFO(dev)->is_mobile)
1150
1151 /*
1152  * The genX designation typically refers to the render engine, so render
1153  * capability related checks should use IS_GEN, while display and other checks
1154  * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
1155  * chips, etc.).
1156  */
1157 #define IS_GEN2(dev)    (INTEL_INFO(dev)->gen == 2)
1158 #define IS_GEN3(dev)    (INTEL_INFO(dev)->gen == 3)
1159 #define IS_GEN4(dev)    (INTEL_INFO(dev)->gen == 4)
1160 #define IS_GEN5(dev)    (INTEL_INFO(dev)->gen == 5)
1161 #define IS_GEN6(dev)    (INTEL_INFO(dev)->gen == 6)
1162 #define IS_GEN7(dev)    (INTEL_INFO(dev)->gen == 7)
1163
1164 #define HAS_BSD(dev)            (INTEL_INFO(dev)->has_bsd_ring)
1165 #define HAS_BLT(dev)            (INTEL_INFO(dev)->has_blt_ring)
1166 #define HAS_LLC(dev)            (INTEL_INFO(dev)->has_llc)
1167 #define I915_NEED_GFX_HWS(dev)  (INTEL_INFO(dev)->need_gfx_hws)
1168
1169 #define HAS_HW_CONTEXTS(dev)    (INTEL_INFO(dev)->gen >= 6)
1170 #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6 && !IS_VALLEYVIEW(dev))
1171
1172 #define HAS_OVERLAY(dev)                (INTEL_INFO(dev)->has_overlay)
1173 #define OVERLAY_NEEDS_PHYSICAL(dev)     (INTEL_INFO(dev)->overlay_needs_physical)
1174
1175 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1176  * rows, which changed the alignment requirements and fence programming.
1177  */
1178 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
1179                                                       IS_I915GM(dev)))
1180 #define SUPPORTS_DIGITAL_OUTPUTS(dev)   (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
1181 #define SUPPORTS_INTEGRATED_HDMI(dev)   (IS_G4X(dev) || IS_GEN5(dev))
1182 #define SUPPORTS_INTEGRATED_DP(dev)     (IS_G4X(dev) || IS_GEN5(dev))
1183 #define SUPPORTS_EDP(dev)               (IS_IRONLAKE_M(dev))
1184 #define SUPPORTS_TV(dev)                (INTEL_INFO(dev)->supports_tv)
1185 #define I915_HAS_HOTPLUG(dev)            (INTEL_INFO(dev)->has_hotplug)
1186 /* dsparb controlled by hw only */
1187 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1188
1189 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
1190 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
1191 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
1192
1193 #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5)
1194
1195 #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
1196 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
1197 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
1198 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
1199 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
1200
1201 #define HAS_FORCE_WAKE(dev) (INTEL_INFO(dev)->has_force_wake)
1202
1203 #define HAS_L3_GPU_CACHE(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1204
1205 #define GT_FREQUENCY_MULTIPLIER 50
1206
1207 #include "i915_trace.h"
1208
1209 /**
1210  * RC6 is a special power stage which allows the GPU to enter an very
1211  * low-voltage mode when idle, using down to 0V while at this stage.  This
1212  * stage is entered automatically when the GPU is idle when RC6 support is
1213  * enabled, and as soon as new workload arises GPU wakes up automatically as well.
1214  *
1215  * There are different RC6 modes available in Intel GPU, which differentiate
1216  * among each other with the latency required to enter and leave RC6 and
1217  * voltage consumed by the GPU in different states.
1218  *
1219  * The combination of the following flags define which states GPU is allowed
1220  * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
1221  * RC6pp is deepest RC6. Their support by hardware varies according to the
1222  * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
1223  * which brings the most power savings; deeper states save more power, but
1224  * require higher latency to switch to and wake up.
1225  */
1226 #define INTEL_RC6_ENABLE                        (1<<0)
1227 #define INTEL_RC6p_ENABLE                       (1<<1)
1228 #define INTEL_RC6pp_ENABLE                      (1<<2)
1229
1230 extern struct drm_ioctl_desc i915_ioctls[];
1231 extern int i915_max_ioctl;
1232 extern unsigned int i915_fbpercrtc __always_unused;
1233 extern int i915_panel_ignore_lid __read_mostly;
1234 extern unsigned int i915_powersave __read_mostly;
1235 extern int i915_semaphores __read_mostly;
1236 extern unsigned int i915_lvds_downclock __read_mostly;
1237 extern int i915_lvds_channel_mode __read_mostly;
1238 extern int i915_panel_use_ssc __read_mostly;
1239 extern int i915_vbt_sdvo_panel_type __read_mostly;
1240 extern int i915_enable_rc6 __read_mostly;
1241 extern int i915_enable_fbc __read_mostly;
1242 extern bool i915_enable_hangcheck __read_mostly;
1243 extern int i915_enable_ppgtt __read_mostly;
1244
1245 extern int i915_suspend(struct drm_device *dev, pm_message_t state);
1246 extern int i915_resume(struct drm_device *dev);
1247 extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
1248 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
1249
1250                                 /* i915_dma.c */
1251 void i915_update_dri1_breadcrumb(struct drm_device *dev);
1252 extern void i915_kernel_lost_context(struct drm_device * dev);
1253 extern int i915_driver_load(struct drm_device *, unsigned long flags);
1254 extern int i915_driver_unload(struct drm_device *);
1255 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
1256 extern void i915_driver_lastclose(struct drm_device * dev);
1257 extern void i915_driver_preclose(struct drm_device *dev,
1258                                  struct drm_file *file_priv);
1259 extern void i915_driver_postclose(struct drm_device *dev,
1260                                   struct drm_file *file_priv);
1261 extern int i915_driver_device_is_agp(struct drm_device * dev);
1262 #ifdef CONFIG_COMPAT
1263 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
1264                               unsigned long arg);
1265 #endif
1266 extern int i915_emit_box(struct drm_device *dev,
1267                          struct drm_clip_rect *box,
1268                          int DR1, int DR4);
1269 extern int intel_gpu_reset(struct drm_device *dev);
1270 extern int i915_reset(struct drm_device *dev);
1271 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
1272 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
1273 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
1274 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
1275
1276
1277 /* i915_irq.c */
1278 void i915_hangcheck_elapsed(unsigned long data);
1279 void i915_handle_error(struct drm_device *dev, bool wedged);
1280
1281 extern void intel_irq_init(struct drm_device *dev);
1282 extern void intel_gt_init(struct drm_device *dev);
1283 extern void intel_gt_reset(struct drm_device *dev);
1284
1285 void i915_error_state_free(struct kref *error_ref);
1286
1287 void
1288 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1289
1290 void
1291 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1292
1293 void intel_enable_asle(struct drm_device *dev);
1294
1295 #ifdef CONFIG_DEBUG_FS
1296 extern void i915_destroy_error_state(struct drm_device *dev);
1297 #else
1298 #define i915_destroy_error_state(x)
1299 #endif
1300
1301
1302 /* i915_gem.c */
1303 int i915_gem_init_ioctl(struct drm_device *dev, void *data,
1304                         struct drm_file *file_priv);
1305 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
1306                           struct drm_file *file_priv);
1307 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
1308                          struct drm_file *file_priv);
1309 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1310                           struct drm_file *file_priv);
1311 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1312                         struct drm_file *file_priv);
1313 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1314                         struct drm_file *file_priv);
1315 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1316                               struct drm_file *file_priv);
1317 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1318                              struct drm_file *file_priv);
1319 int i915_gem_execbuffer(struct drm_device *dev, void *data,
1320                         struct drm_file *file_priv);
1321 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
1322                          struct drm_file *file_priv);
1323 int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
1324                        struct drm_file *file_priv);
1325 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
1326                          struct drm_file *file_priv);
1327 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
1328                         struct drm_file *file_priv);
1329 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
1330                                struct drm_file *file);
1331 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
1332                                struct drm_file *file);
1333 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
1334                             struct drm_file *file_priv);
1335 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
1336                            struct drm_file *file_priv);
1337 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
1338                            struct drm_file *file_priv);
1339 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
1340                            struct drm_file *file_priv);
1341 int i915_gem_set_tiling(struct drm_device *dev, void *data,
1342                         struct drm_file *file_priv);
1343 int i915_gem_get_tiling(struct drm_device *dev, void *data,
1344                         struct drm_file *file_priv);
1345 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
1346                                 struct drm_file *file_priv);
1347 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
1348                         struct drm_file *file_priv);
1349 void i915_gem_load(struct drm_device *dev);
1350 int i915_gem_init_object(struct drm_gem_object *obj);
1351 void i915_gem_object_init(struct drm_i915_gem_object *obj,
1352                          const struct drm_i915_gem_object_ops *ops);
1353 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
1354                                                   size_t size);
1355 void i915_gem_free_object(struct drm_gem_object *obj);
1356 int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
1357                                      uint32_t alignment,
1358                                      bool map_and_fenceable,
1359                                      bool nonblocking);
1360 void i915_gem_object_unpin(struct drm_i915_gem_object *obj);
1361 int __must_check i915_gem_object_unbind(struct drm_i915_gem_object *obj);
1362 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
1363 void i915_gem_lastclose(struct drm_device *dev);
1364
1365 int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
1366 static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
1367 {
1368         struct scatterlist *sg = obj->pages->sgl;
1369         int nents = obj->pages->nents;
1370         while (nents > SG_MAX_SINGLE_ALLOC) {
1371                 if (n < SG_MAX_SINGLE_ALLOC - 1)
1372                         break;
1373
1374                 sg = sg_chain_ptr(sg + SG_MAX_SINGLE_ALLOC - 1);
1375                 n -= SG_MAX_SINGLE_ALLOC - 1;
1376                 nents -= SG_MAX_SINGLE_ALLOC - 1;
1377         }
1378         return sg_page(sg+n);
1379 }
1380 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
1381 {
1382         BUG_ON(obj->pages == NULL);
1383         obj->pages_pin_count++;
1384 }
1385 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
1386 {
1387         BUG_ON(obj->pages_pin_count == 0);
1388         obj->pages_pin_count--;
1389 }
1390
1391 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
1392 int i915_gem_object_sync(struct drm_i915_gem_object *obj,
1393                          struct intel_ring_buffer *to);
1394 void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1395                                     struct intel_ring_buffer *ring,
1396                                     u32 seqno);
1397
1398 int i915_gem_dumb_create(struct drm_file *file_priv,
1399                          struct drm_device *dev,
1400                          struct drm_mode_create_dumb *args);
1401 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
1402                       uint32_t handle, uint64_t *offset);
1403 int i915_gem_dumb_destroy(struct drm_file *file_priv, struct drm_device *dev,
1404                           uint32_t handle);
1405 /**
1406  * Returns true if seq1 is later than seq2.
1407  */
1408 static inline bool
1409 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1410 {
1411         return (int32_t)(seq1 - seq2) >= 0;
1412 }
1413
1414 u32 i915_gem_next_request_seqno(struct intel_ring_buffer *ring);
1415
1416 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
1417 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
1418
1419 static inline bool
1420 i915_gem_object_pin_fence(struct drm_i915_gem_object *obj)
1421 {
1422         if (obj->fence_reg != I915_FENCE_REG_NONE) {
1423                 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1424                 dev_priv->fence_regs[obj->fence_reg].pin_count++;
1425                 return true;
1426         } else
1427                 return false;
1428 }
1429
1430 static inline void
1431 i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
1432 {
1433         if (obj->fence_reg != I915_FENCE_REG_NONE) {
1434                 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1435                 dev_priv->fence_regs[obj->fence_reg].pin_count--;
1436         }
1437 }
1438
1439 void i915_gem_retire_requests(struct drm_device *dev);
1440 void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring);
1441 int __must_check i915_gem_check_wedge(struct drm_i915_private *dev_priv,
1442                                       bool interruptible);
1443
1444 void i915_gem_reset(struct drm_device *dev);
1445 void i915_gem_clflush_object(struct drm_i915_gem_object *obj);
1446 int __must_check i915_gem_object_set_domain(struct drm_i915_gem_object *obj,
1447                                             uint32_t read_domains,
1448                                             uint32_t write_domain);
1449 int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
1450 int __must_check i915_gem_init(struct drm_device *dev);
1451 int __must_check i915_gem_init_hw(struct drm_device *dev);
1452 void i915_gem_l3_remap(struct drm_device *dev);
1453 void i915_gem_init_swizzling(struct drm_device *dev);
1454 void i915_gem_init_ppgtt(struct drm_device *dev);
1455 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
1456 int __must_check i915_gpu_idle(struct drm_device *dev);
1457 int __must_check i915_gem_idle(struct drm_device *dev);
1458 int i915_add_request(struct intel_ring_buffer *ring,
1459                      struct drm_file *file,
1460                      u32 *seqno);
1461 int __must_check i915_wait_seqno(struct intel_ring_buffer *ring,
1462                                  uint32_t seqno);
1463 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
1464 int __must_check
1465 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
1466                                   bool write);
1467 int __must_check
1468 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
1469 int __must_check
1470 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
1471                                      u32 alignment,
1472                                      struct intel_ring_buffer *pipelined);
1473 int i915_gem_attach_phys_object(struct drm_device *dev,
1474                                 struct drm_i915_gem_object *obj,
1475                                 int id,
1476                                 int align);
1477 void i915_gem_detach_phys_object(struct drm_device *dev,
1478                                  struct drm_i915_gem_object *obj);
1479 void i915_gem_free_all_phys_object(struct drm_device *dev);
1480 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
1481
1482 uint32_t
1483 i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev,
1484                                     uint32_t size,
1485                                     int tiling_mode);
1486
1487 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
1488                                     enum i915_cache_level cache_level);
1489
1490 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
1491                                 struct dma_buf *dma_buf);
1492
1493 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
1494                                 struct drm_gem_object *gem_obj, int flags);
1495
1496 /* i915_gem_context.c */
1497 void i915_gem_context_init(struct drm_device *dev);
1498 void i915_gem_context_fini(struct drm_device *dev);
1499 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
1500 int i915_switch_context(struct intel_ring_buffer *ring,
1501                         struct drm_file *file, int to_id);
1502 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
1503                                   struct drm_file *file);
1504 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
1505                                    struct drm_file *file);
1506
1507 /* i915_gem_gtt.c */
1508 int __must_check i915_gem_init_aliasing_ppgtt(struct drm_device *dev);
1509 void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev);
1510 void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt,
1511                             struct drm_i915_gem_object *obj,
1512                             enum i915_cache_level cache_level);
1513 void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt,
1514                               struct drm_i915_gem_object *obj);
1515
1516 void i915_gem_restore_gtt_mappings(struct drm_device *dev);
1517 int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj);
1518 void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj,
1519                                 enum i915_cache_level cache_level);
1520 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj);
1521 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj);
1522 void i915_gem_init_global_gtt(struct drm_device *dev,
1523                               unsigned long start,
1524                               unsigned long mappable_end,
1525                               unsigned long end);
1526
1527 /* i915_gem_evict.c */
1528 int __must_check i915_gem_evict_something(struct drm_device *dev, int min_size,
1529                                           unsigned alignment,
1530                                           unsigned cache_level,
1531                                           bool mappable,
1532                                           bool nonblock);
1533 int i915_gem_evict_everything(struct drm_device *dev);
1534
1535 /* i915_gem_stolen.c */
1536 int i915_gem_init_stolen(struct drm_device *dev);
1537 void i915_gem_cleanup_stolen(struct drm_device *dev);
1538
1539 /* i915_gem_tiling.c */
1540 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
1541 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
1542 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
1543
1544 /* i915_gem_debug.c */
1545 void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
1546                           const char *where, uint32_t mark);
1547 #if WATCH_LISTS
1548 int i915_verify_lists(struct drm_device *dev);
1549 #else
1550 #define i915_verify_lists(dev) 0
1551 #endif
1552 void i915_gem_object_check_coherency(struct drm_i915_gem_object *obj,
1553                                      int handle);
1554 void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
1555                           const char *where, uint32_t mark);
1556
1557 /* i915_debugfs.c */
1558 int i915_debugfs_init(struct drm_minor *minor);
1559 void i915_debugfs_cleanup(struct drm_minor *minor);
1560
1561 /* i915_suspend.c */
1562 extern int i915_save_state(struct drm_device *dev);
1563 extern int i915_restore_state(struct drm_device *dev);
1564
1565 /* i915_suspend.c */
1566 extern int i915_save_state(struct drm_device *dev);
1567 extern int i915_restore_state(struct drm_device *dev);
1568
1569 /* i915_sysfs.c */
1570 void i915_setup_sysfs(struct drm_device *dev_priv);
1571 void i915_teardown_sysfs(struct drm_device *dev_priv);
1572
1573 /* intel_i2c.c */
1574 extern int intel_setup_gmbus(struct drm_device *dev);
1575 extern void intel_teardown_gmbus(struct drm_device *dev);
1576 extern inline bool intel_gmbus_is_port_valid(unsigned port)
1577 {
1578         return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD);
1579 }
1580
1581 extern struct i2c_adapter *intel_gmbus_get_adapter(
1582                 struct drm_i915_private *dev_priv, unsigned port);
1583 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
1584 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
1585 extern inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
1586 {
1587         return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
1588 }
1589 extern void intel_i2c_reset(struct drm_device *dev);
1590
1591 /* intel_opregion.c */
1592 extern int intel_opregion_setup(struct drm_device *dev);
1593 #ifdef CONFIG_ACPI
1594 extern void intel_opregion_init(struct drm_device *dev);
1595 extern void intel_opregion_fini(struct drm_device *dev);
1596 extern void intel_opregion_asle_intr(struct drm_device *dev);
1597 extern void intel_opregion_gse_intr(struct drm_device *dev);
1598 extern void intel_opregion_enable_asle(struct drm_device *dev);
1599 #else
1600 static inline void intel_opregion_init(struct drm_device *dev) { return; }
1601 static inline void intel_opregion_fini(struct drm_device *dev) { return; }
1602 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
1603 static inline void intel_opregion_gse_intr(struct drm_device *dev) { return; }
1604 static inline void intel_opregion_enable_asle(struct drm_device *dev) { return; }
1605 #endif
1606
1607 /* intel_acpi.c */
1608 #ifdef CONFIG_ACPI
1609 extern void intel_register_dsm_handler(void);
1610 extern void intel_unregister_dsm_handler(void);
1611 #else
1612 static inline void intel_register_dsm_handler(void) { return; }
1613 static inline void intel_unregister_dsm_handler(void) { return; }
1614 #endif /* CONFIG_ACPI */
1615
1616 /* modesetting */
1617 extern void intel_modeset_init_hw(struct drm_device *dev);
1618 extern void intel_modeset_init(struct drm_device *dev);
1619 extern void intel_modeset_gem_init(struct drm_device *dev);
1620 extern void intel_modeset_cleanup(struct drm_device *dev);
1621 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
1622 extern void intel_modeset_setup_hw_state(struct drm_device *dev);
1623 extern bool intel_fbc_enabled(struct drm_device *dev);
1624 extern void intel_disable_fbc(struct drm_device *dev);
1625 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
1626 extern void ironlake_init_pch_refclk(struct drm_device *dev);
1627 extern void gen6_set_rps(struct drm_device *dev, u8 val);
1628 extern void intel_detect_pch(struct drm_device *dev);
1629 extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
1630 extern int intel_enable_rc6(const struct drm_device *dev);
1631
1632 extern bool i915_semaphore_is_enabled(struct drm_device *dev);
1633 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
1634                         struct drm_file *file);
1635
1636 /* overlay */
1637 #ifdef CONFIG_DEBUG_FS
1638 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
1639 extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error);
1640
1641 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
1642 extern void intel_display_print_error_state(struct seq_file *m,
1643                                             struct drm_device *dev,
1644                                             struct intel_display_error_state *error);
1645 #endif
1646
1647 /* On SNB platform, before reading ring registers forcewake bit
1648  * must be set to prevent GT core from power down and stale values being
1649  * returned.
1650  */
1651 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);
1652 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);
1653 int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv);
1654
1655 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val);
1656 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val);
1657
1658 #define __i915_read(x, y) \
1659         u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg);
1660
1661 __i915_read(8, b)
1662 __i915_read(16, w)
1663 __i915_read(32, l)
1664 __i915_read(64, q)
1665 #undef __i915_read
1666
1667 #define __i915_write(x, y) \
1668         void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val);
1669
1670 __i915_write(8, b)
1671 __i915_write(16, w)
1672 __i915_write(32, l)
1673 __i915_write(64, q)
1674 #undef __i915_write
1675
1676 #define I915_READ8(reg)         i915_read8(dev_priv, (reg))
1677 #define I915_WRITE8(reg, val)   i915_write8(dev_priv, (reg), (val))
1678
1679 #define I915_READ16(reg)        i915_read16(dev_priv, (reg))
1680 #define I915_WRITE16(reg, val)  i915_write16(dev_priv, (reg), (val))
1681 #define I915_READ16_NOTRACE(reg)        readw(dev_priv->regs + (reg))
1682 #define I915_WRITE16_NOTRACE(reg, val)  writew(val, dev_priv->regs + (reg))
1683
1684 #define I915_READ(reg)          i915_read32(dev_priv, (reg))
1685 #define I915_WRITE(reg, val)    i915_write32(dev_priv, (reg), (val))
1686 #define I915_READ_NOTRACE(reg)          readl(dev_priv->regs + (reg))
1687 #define I915_WRITE_NOTRACE(reg, val)    writel(val, dev_priv->regs + (reg))
1688
1689 #define I915_WRITE64(reg, val)  i915_write64(dev_priv, (reg), (val))
1690 #define I915_READ64(reg)        i915_read64(dev_priv, (reg))
1691
1692 #define POSTING_READ(reg)       (void)I915_READ_NOTRACE(reg)
1693 #define POSTING_READ16(reg)     (void)I915_READ16_NOTRACE(reg)
1694
1695
1696 #endif