1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
34 #include <uapi/drm/drm_fourcc.h>
37 #include "i915_params.h"
39 #include "intel_bios.h"
40 #include "intel_ringbuffer.h"
41 #include "intel_lrc.h"
42 #include "i915_gem_gtt.h"
43 #include "i915_gem_render_state.h"
44 #include <linux/io-mapping.h>
45 #include <linux/i2c.h>
46 #include <linux/i2c-algo-bit.h>
47 #include <drm/intel-gtt.h>
48 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
49 #include <drm/drm_gem.h>
50 #include <linux/backlight.h>
51 #include <linux/hashtable.h>
52 #include <linux/intel-iommu.h>
53 #include <linux/kref.h>
54 #include <linux/pm_qos.h>
55 #include "intel_guc.h"
57 /* General customization:
60 #define DRIVER_NAME "i915"
61 #define DRIVER_DESC "Intel Graphics"
62 #define DRIVER_DATE "20160124"
65 /* Many gcc seem to no see through this and fall over :( */
67 #define WARN_ON(x) ({ \
68 bool __i915_warn_cond = (x); \
69 if (__builtin_constant_p(__i915_warn_cond)) \
70 BUILD_BUG_ON(__i915_warn_cond); \
71 WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
73 #define WARN_ON(x) WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
77 #define WARN_ON_ONCE(x) WARN_ONCE((x), "%s", "WARN_ON_ONCE(" __stringify(x) ")")
79 #define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
80 (long) (x), __func__);
82 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
83 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
84 * which may not necessarily be a user visible problem. This will either
85 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
86 * enable distros and users to tailor their preferred amount of i915 abrt
89 #define I915_STATE_WARN(condition, format...) ({ \
90 int __ret_warn_on = !!(condition); \
91 if (unlikely(__ret_warn_on)) \
92 if (!WARN(i915.verbose_state_checks, format)) \
94 unlikely(__ret_warn_on); \
97 #define I915_STATE_WARN_ON(x) \
98 I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
100 static inline const char *yesno(bool v
)
102 return v
? "yes" : "no";
105 static inline const char *onoff(bool v
)
107 return v
? "on" : "off";
116 I915_MAX_PIPES
= _PIPE_EDP
118 #define pipe_name(p) ((p) + 'A')
127 #define transcoder_name(t) ((t) + 'A')
130 * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
131 * number of planes per CRTC. Not all platforms really have this many planes,
132 * which means some arrays of size I915_MAX_PLANES may have unused entries
133 * between the topmost sprite plane and the cursor plane.
142 #define plane_name(p) ((p) + 'A')
144 #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
154 #define port_name(p) ((p) + 'A')
156 #define I915_NUM_PHYS_VLV 2
168 enum intel_display_power_domain
{
172 POWER_DOMAIN_PIPE_A_PANEL_FITTER
,
173 POWER_DOMAIN_PIPE_B_PANEL_FITTER
,
174 POWER_DOMAIN_PIPE_C_PANEL_FITTER
,
175 POWER_DOMAIN_TRANSCODER_A
,
176 POWER_DOMAIN_TRANSCODER_B
,
177 POWER_DOMAIN_TRANSCODER_C
,
178 POWER_DOMAIN_TRANSCODER_EDP
,
179 POWER_DOMAIN_PORT_DDI_A_LANES
,
180 POWER_DOMAIN_PORT_DDI_B_LANES
,
181 POWER_DOMAIN_PORT_DDI_C_LANES
,
182 POWER_DOMAIN_PORT_DDI_D_LANES
,
183 POWER_DOMAIN_PORT_DDI_E_LANES
,
184 POWER_DOMAIN_PORT_DSI
,
185 POWER_DOMAIN_PORT_CRT
,
186 POWER_DOMAIN_PORT_OTHER
,
195 POWER_DOMAIN_MODESET
,
201 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
202 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
203 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
204 #define POWER_DOMAIN_TRANSCODER(tran) \
205 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
206 (tran) + POWER_DOMAIN_TRANSCODER_A)
210 HPD_TV
= HPD_NONE
, /* TV is known to be unreliable */
222 #define for_each_hpd_pin(__pin) \
223 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
225 struct i915_hotplug
{
226 struct work_struct hotplug_work
;
229 unsigned long last_jiffies
;
234 HPD_MARK_DISABLED
= 2
236 } stats
[HPD_NUM_PINS
];
238 struct delayed_work reenable_work
;
240 struct intel_digital_port
*irq_port
[I915_MAX_PORTS
];
243 struct work_struct dig_port_work
;
246 * if we get a HPD irq from DP and a HPD irq from non-DP
247 * the non-DP HPD could block the workqueue on a mode config
248 * mutex getting, that userspace may have taken. However
249 * userspace is waiting on the DP workqueue to run which is
250 * blocked behind the non-DP one.
252 struct workqueue_struct
*dp_wq
;
255 #define I915_GEM_GPU_DOMAINS \
256 (I915_GEM_DOMAIN_RENDER | \
257 I915_GEM_DOMAIN_SAMPLER | \
258 I915_GEM_DOMAIN_COMMAND | \
259 I915_GEM_DOMAIN_INSTRUCTION | \
260 I915_GEM_DOMAIN_VERTEX)
262 #define for_each_pipe(__dev_priv, __p) \
263 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
264 #define for_each_plane(__dev_priv, __pipe, __p) \
266 (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
268 #define for_each_sprite(__dev_priv, __p, __s) \
270 (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \
273 #define for_each_crtc(dev, crtc) \
274 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
276 #define for_each_intel_plane(dev, intel_plane) \
277 list_for_each_entry(intel_plane, \
278 &dev->mode_config.plane_list, \
281 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
282 list_for_each_entry(intel_plane, \
283 &(dev)->mode_config.plane_list, \
285 for_each_if ((intel_plane)->pipe == (intel_crtc)->pipe)
287 #define for_each_intel_crtc(dev, intel_crtc) \
288 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)
290 #define for_each_intel_encoder(dev, intel_encoder) \
291 list_for_each_entry(intel_encoder, \
292 &(dev)->mode_config.encoder_list, \
295 #define for_each_intel_connector(dev, intel_connector) \
296 list_for_each_entry(intel_connector, \
297 &dev->mode_config.connector_list, \
300 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
301 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
302 for_each_if ((intel_encoder)->base.crtc == (__crtc))
304 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
305 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
306 for_each_if ((intel_connector)->base.encoder == (__encoder))
308 #define for_each_power_domain(domain, mask) \
309 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
310 for_each_if ((1 << (domain)) & (mask))
312 struct drm_i915_private
;
313 struct i915_mm_struct
;
314 struct i915_mmu_object
;
316 struct drm_i915_file_private
{
317 struct drm_i915_private
*dev_priv
;
318 struct drm_file
*file
;
322 struct list_head request_list
;
323 /* 20ms is a fairly arbitrary limit (greater than the average frame time)
324 * chosen to prevent the CPU getting more than a frame ahead of the GPU
325 * (when using lax throttling for the frontbuffer). We also use it to
326 * offer free GPU waitboosts for severely congested workloads.
328 #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
330 struct idr context_idr
;
332 struct intel_rps_client
{
333 struct list_head link
;
337 unsigned int bsd_ring
;
341 DPLL_ID_PRIVATE
= -1, /* non-shared dpll in use */
342 /* real shared dpll ids must be >= 0 */
343 DPLL_ID_PCH_PLL_A
= 0,
344 DPLL_ID_PCH_PLL_B
= 1,
351 DPLL_ID_SKL_DPLL1
= 0,
352 DPLL_ID_SKL_DPLL2
= 1,
353 DPLL_ID_SKL_DPLL3
= 2,
355 #define I915_NUM_PLLS 3
357 struct intel_dpll_hw_state
{
370 * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in
371 * lower part of ctrl1 and they get shifted into position when writing
372 * the register. This allows us to easily compare the state to share
376 /* HDMI only, 0 when used for DP */
377 uint32_t cfgcr1
, cfgcr2
;
380 uint32_t ebb0
, ebb4
, pll0
, pll1
, pll2
, pll3
, pll6
, pll8
, pll9
, pll10
,
384 struct intel_shared_dpll_config
{
385 unsigned crtc_mask
; /* mask of CRTCs sharing this PLL */
386 struct intel_dpll_hw_state hw_state
;
389 struct intel_shared_dpll
{
390 struct intel_shared_dpll_config config
;
392 int active
; /* count of number of active CRTCs (i.e. DPMS on) */
393 bool on
; /* is the PLL actually active? Disabled during modeset */
395 /* should match the index in the dev_priv->shared_dplls array */
396 enum intel_dpll_id id
;
397 /* The mode_set hook is optional and should be used together with the
398 * intel_prepare_shared_dpll function. */
399 void (*mode_set
)(struct drm_i915_private
*dev_priv
,
400 struct intel_shared_dpll
*pll
);
401 void (*enable
)(struct drm_i915_private
*dev_priv
,
402 struct intel_shared_dpll
*pll
);
403 void (*disable
)(struct drm_i915_private
*dev_priv
,
404 struct intel_shared_dpll
*pll
);
405 bool (*get_hw_state
)(struct drm_i915_private
*dev_priv
,
406 struct intel_shared_dpll
*pll
,
407 struct intel_dpll_hw_state
*hw_state
);
415 /* Used by dp and fdi links */
416 struct intel_link_m_n
{
424 void intel_link_compute_m_n(int bpp
, int nlanes
,
425 int pixel_clock
, int link_clock
,
426 struct intel_link_m_n
*m_n
);
428 /* Interface history:
431 * 1.2: Add Power Management
432 * 1.3: Add vblank support
433 * 1.4: Fix cmdbuffer path, add heap destroy
434 * 1.5: Add vblank pipe configuration
435 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
436 * - Support vertical blank on secondary display pipe
438 #define DRIVER_MAJOR 1
439 #define DRIVER_MINOR 6
440 #define DRIVER_PATCHLEVEL 0
442 #define WATCH_LISTS 0
444 struct opregion_header
;
445 struct opregion_acpi
;
446 struct opregion_swsci
;
447 struct opregion_asle
;
449 struct intel_opregion
{
450 struct opregion_header
*header
;
451 struct opregion_acpi
*acpi
;
452 struct opregion_swsci
*swsci
;
453 u32 swsci_gbda_sub_functions
;
454 u32 swsci_sbcb_sub_functions
;
455 struct opregion_asle
*asle
;
460 struct work_struct asle_work
;
462 #define OPREGION_SIZE (8*1024)
464 struct intel_overlay
;
465 struct intel_overlay_error_state
;
467 #define I915_FENCE_REG_NONE -1
468 #define I915_MAX_NUM_FENCES 32
469 /* 32 fences + sign bit for FENCE_REG_NONE */
470 #define I915_MAX_NUM_FENCE_BITS 6
472 struct drm_i915_fence_reg
{
473 struct list_head lru_list
;
474 struct drm_i915_gem_object
*obj
;
478 struct sdvo_device_mapping
{
487 struct intel_display_error_state
;
489 struct drm_i915_error_state
{
498 /* Generic register state */
506 u32 error
; /* gen6+ */
507 u32 err_int
; /* gen7 */
508 u32 fault_data0
; /* gen8, gen9 */
509 u32 fault_data1
; /* gen8, gen9 */
515 u32 extra_instdone
[I915_NUM_INSTDONE_REG
];
516 u64 fence
[I915_MAX_NUM_FENCES
];
517 struct intel_overlay_error_state
*overlay
;
518 struct intel_display_error_state
*display
;
519 struct drm_i915_error_object
*semaphore_obj
;
521 struct drm_i915_error_ring
{
523 /* Software tracked state */
526 enum intel_ring_hangcheck_action hangcheck_action
;
529 /* our own tracking of ring head and tail */
533 u32 semaphore_seqno
[I915_NUM_RINGS
- 1];
552 u32 rc_psmi
; /* sleep state */
553 u32 semaphore_mboxes
[I915_NUM_RINGS
- 1];
555 struct drm_i915_error_object
{
559 } *ringbuffer
, *batchbuffer
, *wa_batchbuffer
, *ctx
, *hws_page
;
561 struct drm_i915_error_request
{
576 char comm
[TASK_COMM_LEN
];
577 } ring
[I915_NUM_RINGS
];
579 struct drm_i915_error_buffer
{
582 u32 rseqno
[I915_NUM_RINGS
], wseqno
;
586 s32 fence_reg
:I915_MAX_NUM_FENCE_BITS
;
594 } **active_bo
, **pinned_bo
;
596 u32
*active_bo_count
, *pinned_bo_count
;
600 struct intel_connector
;
601 struct intel_encoder
;
602 struct intel_crtc_state
;
603 struct intel_initial_plane_config
;
608 struct drm_i915_display_funcs
{
609 int (*get_display_clock_speed
)(struct drm_device
*dev
);
610 int (*get_fifo_size
)(struct drm_device
*dev
, int plane
);
612 * find_dpll() - Find the best values for the PLL
613 * @limit: limits for the PLL
614 * @crtc: current CRTC
615 * @target: target frequency in kHz
616 * @refclk: reference clock frequency in kHz
617 * @match_clock: if provided, @best_clock P divider must
618 * match the P divider from @match_clock
619 * used for LVDS downclocking
620 * @best_clock: best PLL values found
622 * Returns true on success, false on failure.
624 bool (*find_dpll
)(const struct intel_limit
*limit
,
625 struct intel_crtc_state
*crtc_state
,
626 int target
, int refclk
,
627 struct dpll
*match_clock
,
628 struct dpll
*best_clock
);
629 int (*compute_pipe_wm
)(struct intel_crtc
*crtc
,
630 struct drm_atomic_state
*state
);
631 void (*program_watermarks
)(struct intel_crtc_state
*cstate
);
632 void (*update_wm
)(struct drm_crtc
*crtc
);
633 int (*modeset_calc_cdclk
)(struct drm_atomic_state
*state
);
634 void (*modeset_commit_cdclk
)(struct drm_atomic_state
*state
);
635 /* Returns the active state of the crtc, and if the crtc is active,
636 * fills out the pipe-config with the hw state. */
637 bool (*get_pipe_config
)(struct intel_crtc
*,
638 struct intel_crtc_state
*);
639 void (*get_initial_plane_config
)(struct intel_crtc
*,
640 struct intel_initial_plane_config
*);
641 int (*crtc_compute_clock
)(struct intel_crtc
*crtc
,
642 struct intel_crtc_state
*crtc_state
);
643 void (*crtc_enable
)(struct drm_crtc
*crtc
);
644 void (*crtc_disable
)(struct drm_crtc
*crtc
);
645 void (*audio_codec_enable
)(struct drm_connector
*connector
,
646 struct intel_encoder
*encoder
,
647 const struct drm_display_mode
*adjusted_mode
);
648 void (*audio_codec_disable
)(struct intel_encoder
*encoder
);
649 void (*fdi_link_train
)(struct drm_crtc
*crtc
);
650 void (*init_clock_gating
)(struct drm_device
*dev
);
651 int (*queue_flip
)(struct drm_device
*dev
, struct drm_crtc
*crtc
,
652 struct drm_framebuffer
*fb
,
653 struct drm_i915_gem_object
*obj
,
654 struct drm_i915_gem_request
*req
,
656 void (*hpd_irq_setup
)(struct drm_device
*dev
);
657 /* clock updates for mode set */
659 /* render clock increase/decrease */
660 /* display clock increase/decrease */
661 /* pll clock increase/decrease */
664 enum forcewake_domain_id
{
665 FW_DOMAIN_ID_RENDER
= 0,
666 FW_DOMAIN_ID_BLITTER
,
672 enum forcewake_domains
{
673 FORCEWAKE_RENDER
= (1 << FW_DOMAIN_ID_RENDER
),
674 FORCEWAKE_BLITTER
= (1 << FW_DOMAIN_ID_BLITTER
),
675 FORCEWAKE_MEDIA
= (1 << FW_DOMAIN_ID_MEDIA
),
676 FORCEWAKE_ALL
= (FORCEWAKE_RENDER
|
681 struct intel_uncore_funcs
{
682 void (*force_wake_get
)(struct drm_i915_private
*dev_priv
,
683 enum forcewake_domains domains
);
684 void (*force_wake_put
)(struct drm_i915_private
*dev_priv
,
685 enum forcewake_domains domains
);
687 uint8_t (*mmio_readb
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
, bool trace
);
688 uint16_t (*mmio_readw
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
, bool trace
);
689 uint32_t (*mmio_readl
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
, bool trace
);
690 uint64_t (*mmio_readq
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
, bool trace
);
692 void (*mmio_writeb
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
,
693 uint8_t val
, bool trace
);
694 void (*mmio_writew
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
,
695 uint16_t val
, bool trace
);
696 void (*mmio_writel
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
,
697 uint32_t val
, bool trace
);
698 void (*mmio_writeq
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
,
699 uint64_t val
, bool trace
);
702 struct intel_uncore
{
703 spinlock_t lock
; /** lock is also taken in irq contexts. */
705 struct intel_uncore_funcs funcs
;
708 enum forcewake_domains fw_domains
;
710 struct intel_uncore_forcewake_domain
{
711 struct drm_i915_private
*i915
;
712 enum forcewake_domain_id id
;
714 struct timer_list timer
;
721 } fw_domain
[FW_DOMAIN_ID_COUNT
];
723 int unclaimed_mmio_check
;
726 /* Iterate over initialised fw domains */
727 #define for_each_fw_domain_mask(domain__, mask__, dev_priv__, i__) \
728 for ((i__) = 0, (domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
729 (i__) < FW_DOMAIN_ID_COUNT; \
730 (i__)++, (domain__) = &(dev_priv__)->uncore.fw_domain[i__]) \
731 for_each_if (((mask__) & (dev_priv__)->uncore.fw_domains) & (1 << (i__)))
733 #define for_each_fw_domain(domain__, dev_priv__, i__) \
734 for_each_fw_domain_mask(domain__, FORCEWAKE_ALL, dev_priv__, i__)
736 #define CSR_VERSION(major, minor) ((major) << 16 | (minor))
737 #define CSR_VERSION_MAJOR(version) ((version) >> 16)
738 #define CSR_VERSION_MINOR(version) ((version) & 0xffff)
741 struct work_struct work
;
743 uint32_t *dmc_payload
;
744 uint32_t dmc_fw_size
;
747 i915_reg_t mmioaddr
[8];
748 uint32_t mmiodata
[8];
751 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
752 func(is_mobile) sep \
755 func(is_i945gm) sep \
757 func(need_gfx_hws) sep \
759 func(is_pineview) sep \
760 func(is_broadwater) sep \
761 func(is_crestline) sep \
762 func(is_ivybridge) sep \
763 func(is_valleyview) sep \
764 func(is_cherryview) sep \
765 func(is_haswell) sep \
766 func(is_skylake) sep \
767 func(is_broxton) sep \
768 func(is_kabylake) sep \
769 func(is_preliminary) sep \
771 func(has_pipe_cxsr) sep \
772 func(has_hotplug) sep \
773 func(cursor_needs_physical) sep \
774 func(has_overlay) sep \
775 func(overlay_needs_physical) sep \
776 func(supports_tv) sep \
781 #define DEFINE_FLAG(name) u8 name:1
782 #define SEP_SEMICOLON ;
784 struct intel_device_info
{
785 u32 display_mmio_offset
;
788 u8 num_sprites
[I915_MAX_PIPES
];
790 u8 ring_mask
; /* Rings supported by the HW */
791 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG
, SEP_SEMICOLON
);
792 /* Register offsets for the various display pipes and transcoders */
793 int pipe_offsets
[I915_MAX_TRANSCODERS
];
794 int trans_offsets
[I915_MAX_TRANSCODERS
];
795 int palette_offsets
[I915_MAX_PIPES
];
796 int cursor_offsets
[I915_MAX_PIPES
];
798 /* Slice/subslice/EU info */
801 u8 subslice_per_slice
;
804 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
807 u8 has_subslice_pg
:1;
814 enum i915_cache_level
{
816 I915_CACHE_LLC
, /* also used for snoopable memory on non-LLC */
817 I915_CACHE_L3_LLC
, /* gen7+, L3 sits between the domain specifc
818 caches, eg sampler/render caches, and the
819 large Last-Level-Cache. LLC is coherent with
820 the CPU, but L3 is only visible to the GPU. */
821 I915_CACHE_WT
, /* hsw:gt3e WriteThrough for scanouts */
824 struct i915_ctx_hang_stats
{
825 /* This context had batch pending when hang was declared */
826 unsigned batch_pending
;
828 /* This context had batch active when hang was declared */
829 unsigned batch_active
;
831 /* Time when this context was last blamed for a GPU reset */
832 unsigned long guilty_ts
;
834 /* If the contexts causes a second GPU hang within this time,
835 * it is permanently banned from submitting any more work.
837 unsigned long ban_period_seconds
;
839 /* This context is banned to submit more work */
843 /* This must match up with the value previously used for execbuf2.rsvd1. */
844 #define DEFAULT_CONTEXT_HANDLE 0
846 #define CONTEXT_NO_ZEROMAP (1<<0)
848 * struct intel_context - as the name implies, represents a context.
849 * @ref: reference count.
850 * @user_handle: userspace tracking identity for this context.
851 * @remap_slice: l3 row remapping information.
852 * @flags: context specific flags:
853 * CONTEXT_NO_ZEROMAP: do not allow mapping things to page 0.
854 * @file_priv: filp associated with this context (NULL for global default
856 * @hang_stats: information about the role of this context in possible GPU
858 * @ppgtt: virtual memory space used by this context.
859 * @legacy_hw_ctx: render context backing object and whether it is correctly
860 * initialized (legacy ring submission mechanism only).
861 * @link: link in the global list of contexts.
863 * Contexts are memory images used by the hardware to store copies of their
866 struct intel_context
{
870 struct drm_i915_private
*i915
;
872 struct drm_i915_file_private
*file_priv
;
873 struct i915_ctx_hang_stats hang_stats
;
874 struct i915_hw_ppgtt
*ppgtt
;
876 /* Legacy ring buffer submission */
878 struct drm_i915_gem_object
*rcs_state
;
884 struct drm_i915_gem_object
*state
;
885 struct intel_ringbuffer
*ringbuf
;
887 struct i915_vma
*lrc_vma
;
889 uint32_t *lrc_reg_state
;
890 } engine
[I915_NUM_RINGS
];
892 struct list_head link
;
904 /* This is always the inner lock when overlapping with struct_mutex and
905 * it's the outer lock when overlapping with stolen_lock. */
908 unsigned int possible_framebuffer_bits
;
909 unsigned int busy_bits
;
910 struct intel_crtc
*crtc
;
912 struct drm_mm_node compressed_fb
;
913 struct drm_mm_node
*compressed_llb
;
920 struct intel_fbc_reg_params
{
924 unsigned int fence_y_offset
;
930 uint32_t pixel_format
;
938 struct intel_fbc_work
{
940 u32 scheduled_vblank
;
941 struct work_struct work
;
942 struct drm_framebuffer
*fb
;
945 const char *no_fbc_reason
;
947 bool (*is_active
)(struct drm_i915_private
*dev_priv
);
948 void (*activate
)(struct drm_i915_private
*dev_priv
);
949 void (*deactivate
)(struct drm_i915_private
*dev_priv
);
953 * HIGH_RR is the highest eDP panel refresh rate read from EDID
954 * LOW_RR is the lowest eDP panel refresh rate found from EDID
955 * parsing for same resolution.
957 enum drrs_refresh_rate_type
{
960 DRRS_MAX_RR
, /* RR count */
963 enum drrs_support_type
{
964 DRRS_NOT_SUPPORTED
= 0,
965 STATIC_DRRS_SUPPORT
= 1,
966 SEAMLESS_DRRS_SUPPORT
= 2
972 struct delayed_work work
;
974 unsigned busy_frontbuffer_bits
;
975 enum drrs_refresh_rate_type refresh_rate_type
;
976 enum drrs_support_type type
;
983 struct intel_dp
*enabled
;
985 struct delayed_work work
;
986 unsigned busy_frontbuffer_bits
;
992 PCH_NONE
= 0, /* No PCH present */
993 PCH_IBX
, /* Ibexpeak PCH */
994 PCH_CPT
, /* Cougarpoint PCH */
995 PCH_LPT
, /* Lynxpoint PCH */
996 PCH_SPT
, /* Sunrisepoint PCH */
1000 enum intel_sbi_destination
{
1005 #define QUIRK_PIPEA_FORCE (1<<0)
1006 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
1007 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
1008 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
1009 #define QUIRK_PIPEB_FORCE (1<<4)
1010 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
1013 struct intel_fbc_work
;
1015 struct intel_gmbus
{
1016 struct i2c_adapter adapter
;
1019 i915_reg_t gpio_reg
;
1020 struct i2c_algo_bit_data bit_algo
;
1021 struct drm_i915_private
*dev_priv
;
1024 struct i915_suspend_saved_registers
{
1027 u32 savePP_ON_DELAYS
;
1028 u32 savePP_OFF_DELAYS
;
1033 u32 saveFBC_CONTROL
;
1034 u32 saveCACHE_MODE_0
;
1035 u32 saveMI_ARB_STATE
;
1039 uint64_t saveFENCE
[I915_MAX_NUM_FENCES
];
1040 u32 savePCH_PORT_HOTPLUG
;
1044 struct vlv_s0ix_state
{
1051 u32 lra_limits
[GEN7_LRA_LIMITS_REG_NUM
];
1052 u32 media_max_req_count
;
1053 u32 gfx_max_req_count
;
1079 u32 rp_down_timeout
;
1085 /* Display 1 CZ domain */
1090 u32 gt_scratch
[GEN7_GT_SCRATCH_REG_NUM
];
1092 /* GT SA CZ domain */
1099 /* Display 2 CZ domain */
1103 u32 clock_gate_dis2
;
1106 struct intel_rps_ei
{
1112 struct intel_gen6_power_mgmt
{
1114 * work, interrupts_enabled and pm_iir are protected by
1115 * dev_priv->irq_lock
1117 struct work_struct work
;
1118 bool interrupts_enabled
;
1121 /* Frequencies are stored in potentially platform dependent multiples.
1122 * In other words, *_freq needs to be multiplied by X to be interesting.
1123 * Soft limits are those which are used for the dynamic reclocking done
1124 * by the driver (raise frequencies under heavy loads, and lower for
1125 * lighter loads). Hard limits are those imposed by the hardware.
1127 * A distinction is made for overclocking, which is never enabled by
1128 * default, and is considered to be above the hard limit if it's
1131 u8 cur_freq
; /* Current frequency (cached, may not == HW) */
1132 u8 min_freq_softlimit
; /* Minimum frequency permitted by the driver */
1133 u8 max_freq_softlimit
; /* Max frequency permitted by the driver */
1134 u8 max_freq
; /* Maximum frequency, RP0 if not overclocking */
1135 u8 min_freq
; /* AKA RPn. Minimum frequency */
1136 u8 idle_freq
; /* Frequency to request when we are idle */
1137 u8 efficient_freq
; /* AKA RPe. Pre-determined balanced frequency */
1138 u8 rp1_freq
; /* "less than" RP0 power/freqency */
1139 u8 rp0_freq
; /* Non-overclocked max frequency. */
1141 u8 up_threshold
; /* Current %busy required to uplock */
1142 u8 down_threshold
; /* Current %busy required to downclock */
1145 enum { LOW_POWER
, BETWEEN
, HIGH_POWER
} power
;
1147 spinlock_t client_lock
;
1148 struct list_head clients
;
1152 struct delayed_work delayed_resume_work
;
1155 struct intel_rps_client semaphores
, mmioflips
;
1157 /* manual wa residency calculations */
1158 struct intel_rps_ei up_ei
, down_ei
;
1161 * Protects RPS/RC6 register access and PCU communication.
1162 * Must be taken after struct_mutex if nested. Note that
1163 * this lock may be held for long periods of time when
1164 * talking to hw - so only take it when talking to hw!
1166 struct mutex hw_lock
;
1169 /* defined intel_pm.c */
1170 extern spinlock_t mchdev_lock
;
1172 struct intel_ilk_power_mgmt
{
1180 unsigned long last_time1
;
1181 unsigned long chipset_power
;
1184 unsigned long gfx_power
;
1191 struct drm_i915_private
;
1192 struct i915_power_well
;
1194 struct i915_power_well_ops
{
1196 * Synchronize the well's hw state to match the current sw state, for
1197 * example enable/disable it based on the current refcount. Called
1198 * during driver init and resume time, possibly after first calling
1199 * the enable/disable handlers.
1201 void (*sync_hw
)(struct drm_i915_private
*dev_priv
,
1202 struct i915_power_well
*power_well
);
1204 * Enable the well and resources that depend on it (for example
1205 * interrupts located on the well). Called after the 0->1 refcount
1208 void (*enable
)(struct drm_i915_private
*dev_priv
,
1209 struct i915_power_well
*power_well
);
1211 * Disable the well and resources that depend on it. Called after
1212 * the 1->0 refcount transition.
1214 void (*disable
)(struct drm_i915_private
*dev_priv
,
1215 struct i915_power_well
*power_well
);
1216 /* Returns the hw enabled state. */
1217 bool (*is_enabled
)(struct drm_i915_private
*dev_priv
,
1218 struct i915_power_well
*power_well
);
1221 /* Power well structure for haswell */
1222 struct i915_power_well
{
1225 /* power well enable/disable usage count */
1227 /* cached hw enabled state */
1229 unsigned long domains
;
1231 const struct i915_power_well_ops
*ops
;
1234 struct i915_power_domains
{
1236 * Power wells needed for initialization at driver init and suspend
1237 * time are on. They are kept on until after the first modeset.
1241 int power_well_count
;
1244 int domain_use_count
[POWER_DOMAIN_NUM
];
1245 struct i915_power_well
*power_wells
;
1248 #define MAX_L3_SLICES 2
1249 struct intel_l3_parity
{
1250 u32
*remap_info
[MAX_L3_SLICES
];
1251 struct work_struct error_work
;
1255 struct i915_gem_mm
{
1256 /** Memory allocator for GTT stolen memory */
1257 struct drm_mm stolen
;
1258 /** Protects the usage of the GTT stolen memory allocator. This is
1259 * always the inner lock when overlapping with struct_mutex. */
1260 struct mutex stolen_lock
;
1262 /** List of all objects in gtt_space. Used to restore gtt
1263 * mappings on resume */
1264 struct list_head bound_list
;
1266 * List of objects which are not bound to the GTT (thus
1267 * are idle and not used by the GPU) but still have
1268 * (presumably uncached) pages still attached.
1270 struct list_head unbound_list
;
1272 /** Usable portion of the GTT for GEM */
1273 unsigned long stolen_base
; /* limited to low memory (32-bit) */
1275 /** PPGTT used for aliasing the PPGTT with the GTT */
1276 struct i915_hw_ppgtt
*aliasing_ppgtt
;
1278 struct notifier_block oom_notifier
;
1279 struct shrinker shrinker
;
1280 bool shrinker_no_lock_stealing
;
1282 /** LRU list of objects with fence regs on them. */
1283 struct list_head fence_list
;
1286 * We leave the user IRQ off as much as possible,
1287 * but this means that requests will finish and never
1288 * be retired once the system goes idle. Set a timer to
1289 * fire periodically while the ring is running. When it
1290 * fires, go retire requests.
1292 struct delayed_work retire_work
;
1295 * When we detect an idle GPU, we want to turn on
1296 * powersaving features. So once we see that there
1297 * are no more requests outstanding and no more
1298 * arrive within a small period of time, we fire
1299 * off the idle_work.
1301 struct delayed_work idle_work
;
1304 * Are we in a non-interruptible section of code like
1310 * Is the GPU currently considered idle, or busy executing userspace
1311 * requests? Whilst idle, we attempt to power down the hardware and
1312 * display clocks. In order to reduce the effect on performance, there
1313 * is a slight delay before we do so.
1317 /* the indicator for dispatch video commands on two BSD rings */
1318 unsigned int bsd_ring_dispatch_index
;
1320 /** Bit 6 swizzling required for X tiling */
1321 uint32_t bit_6_swizzle_x
;
1322 /** Bit 6 swizzling required for Y tiling */
1323 uint32_t bit_6_swizzle_y
;
1325 /* accounting, useful for userland debugging */
1326 spinlock_t object_stat_lock
;
1327 size_t object_memory
;
1331 struct drm_i915_error_state_buf
{
1332 struct drm_i915_private
*i915
;
1341 struct i915_error_state_file_priv
{
1342 struct drm_device
*dev
;
1343 struct drm_i915_error_state
*error
;
1346 struct i915_gpu_error
{
1347 /* For hangcheck timer */
1348 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1349 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1350 /* Hang gpu twice in this window and your context gets banned */
1351 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1353 struct workqueue_struct
*hangcheck_wq
;
1354 struct delayed_work hangcheck_work
;
1356 /* For reset and error_state handling. */
1358 /* Protected by the above dev->gpu_error.lock. */
1359 struct drm_i915_error_state
*first_error
;
1361 unsigned long missed_irq_rings
;
1364 * State variable controlling the reset flow and count
1366 * This is a counter which gets incremented when reset is triggered,
1367 * and again when reset has been handled. So odd values (lowest bit set)
1368 * means that reset is in progress and even values that
1369 * (reset_counter >> 1):th reset was successfully completed.
1371 * If reset is not completed succesfully, the I915_WEDGE bit is
1372 * set meaning that hardware is terminally sour and there is no
1373 * recovery. All waiters on the reset_queue will be woken when
1376 * This counter is used by the wait_seqno code to notice that reset
1377 * event happened and it needs to restart the entire ioctl (since most
1378 * likely the seqno it waited for won't ever signal anytime soon).
1380 * This is important for lock-free wait paths, where no contended lock
1381 * naturally enforces the correct ordering between the bail-out of the
1382 * waiter and the gpu reset work code.
1384 atomic_t reset_counter
;
1386 #define I915_RESET_IN_PROGRESS_FLAG 1
1387 #define I915_WEDGED (1 << 31)
1390 * Waitqueue to signal when the reset has completed. Used by clients
1391 * that wait for dev_priv->mm.wedged to settle.
1393 wait_queue_head_t reset_queue
;
1395 /* Userspace knobs for gpu hang simulation;
1396 * combines both a ring mask, and extra flags
1399 #define I915_STOP_RING_ALLOW_BAN (1 << 31)
1400 #define I915_STOP_RING_ALLOW_WARN (1 << 30)
1402 /* For missed irq/seqno simulation. */
1403 unsigned int test_irq_rings
;
1405 /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
1406 bool reload_in_reset
;
1409 enum modeset_restore
{
1410 MODESET_ON_LID_OPEN
,
1415 #define DP_AUX_A 0x40
1416 #define DP_AUX_B 0x10
1417 #define DP_AUX_C 0x20
1418 #define DP_AUX_D 0x30
1420 #define DDC_PIN_B 0x05
1421 #define DDC_PIN_C 0x04
1422 #define DDC_PIN_D 0x06
1424 struct ddi_vbt_port_info
{
1426 * This is an index in the HDMI/DVI DDI buffer translation table.
1427 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1428 * populate this field.
1430 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1431 uint8_t hdmi_level_shift
;
1433 uint8_t supports_dvi
:1;
1434 uint8_t supports_hdmi
:1;
1435 uint8_t supports_dp
:1;
1437 uint8_t alternate_aux_channel
;
1438 uint8_t alternate_ddc_pin
;
1440 uint8_t dp_boost_level
;
1441 uint8_t hdmi_boost_level
;
1444 enum psr_lines_to_wait
{
1445 PSR_0_LINES_TO_WAIT
= 0,
1447 PSR_4_LINES_TO_WAIT
,
1451 struct intel_vbt_data
{
1452 struct drm_display_mode
*lfp_lvds_vbt_mode
; /* if any */
1453 struct drm_display_mode
*sdvo_lvds_vbt_mode
; /* if any */
1456 unsigned int int_tv_support
:1;
1457 unsigned int lvds_dither
:1;
1458 unsigned int lvds_vbt
:1;
1459 unsigned int int_crt_support
:1;
1460 unsigned int lvds_use_ssc
:1;
1461 unsigned int display_clock_mode
:1;
1462 unsigned int fdi_rx_polarity_inverted
:1;
1463 unsigned int has_mipi
:1;
1465 unsigned int bios_lvds_val
; /* initial [PCH_]LVDS reg val in VBIOS */
1467 enum drrs_support_type drrs_type
;
1472 int edp_preemphasis
;
1474 bool edp_initialized
;
1477 struct edp_power_seq edp_pps
;
1481 bool require_aux_wakeup
;
1483 enum psr_lines_to_wait lines_to_wait
;
1484 int tp1_wakeup_time
;
1485 int tp2_tp3_wakeup_time
;
1491 bool active_low_pwm
;
1492 u8 min_brightness
; /* min_brightness/255 of max */
1499 struct mipi_config
*config
;
1500 struct mipi_pps_data
*pps
;
1504 const u8
*sequence
[MIPI_SEQ_MAX
];
1510 union child_device_config
*child_dev
;
1512 struct ddi_vbt_port_info ddi_port_info
[I915_MAX_PORTS
];
1515 enum intel_ddb_partitioning
{
1517 INTEL_DDB_PART_5_6
, /* IVB+ */
1520 struct intel_wm_level
{
1528 struct ilk_wm_values
{
1529 uint32_t wm_pipe
[3];
1531 uint32_t wm_lp_spr
[3];
1532 uint32_t wm_linetime
[3];
1534 enum intel_ddb_partitioning partitioning
;
1537 struct vlv_pipe_wm
{
1548 struct vlv_wm_values
{
1549 struct vlv_pipe_wm pipe
[3];
1550 struct vlv_sr_wm sr
;
1560 struct skl_ddb_entry
{
1561 uint16_t start
, end
; /* in number of blocks, 'end' is exclusive */
1564 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry
*entry
)
1566 return entry
->end
- entry
->start
;
1569 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry
*e1
,
1570 const struct skl_ddb_entry
*e2
)
1572 if (e1
->start
== e2
->start
&& e1
->end
== e2
->end
)
1578 struct skl_ddb_allocation
{
1579 struct skl_ddb_entry pipe
[I915_MAX_PIPES
];
1580 struct skl_ddb_entry plane
[I915_MAX_PIPES
][I915_MAX_PLANES
]; /* packed/uv */
1581 struct skl_ddb_entry y_plane
[I915_MAX_PIPES
][I915_MAX_PLANES
];
1584 struct skl_wm_values
{
1585 bool dirty
[I915_MAX_PIPES
];
1586 struct skl_ddb_allocation ddb
;
1587 uint32_t wm_linetime
[I915_MAX_PIPES
];
1588 uint32_t plane
[I915_MAX_PIPES
][I915_MAX_PLANES
][8];
1589 uint32_t plane_trans
[I915_MAX_PIPES
][I915_MAX_PLANES
];
1592 struct skl_wm_level
{
1593 bool plane_en
[I915_MAX_PLANES
];
1594 uint16_t plane_res_b
[I915_MAX_PLANES
];
1595 uint8_t plane_res_l
[I915_MAX_PLANES
];
1599 * This struct helps tracking the state needed for runtime PM, which puts the
1600 * device in PCI D3 state. Notice that when this happens, nothing on the
1601 * graphics device works, even register access, so we don't get interrupts nor
1604 * Every piece of our code that needs to actually touch the hardware needs to
1605 * either call intel_runtime_pm_get or call intel_display_power_get with the
1606 * appropriate power domain.
1608 * Our driver uses the autosuspend delay feature, which means we'll only really
1609 * suspend if we stay with zero refcount for a certain amount of time. The
1610 * default value is currently very conservative (see intel_runtime_pm_enable), but
1611 * it can be changed with the standard runtime PM files from sysfs.
1613 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1614 * goes back to false exactly before we reenable the IRQs. We use this variable
1615 * to check if someone is trying to enable/disable IRQs while they're supposed
1616 * to be disabled. This shouldn't happen and we'll print some error messages in
1619 * For more, read the Documentation/power/runtime_pm.txt.
1621 struct i915_runtime_pm
{
1622 atomic_t wakeref_count
;
1623 atomic_t atomic_seq
;
1628 enum intel_pipe_crc_source
{
1629 INTEL_PIPE_CRC_SOURCE_NONE
,
1630 INTEL_PIPE_CRC_SOURCE_PLANE1
,
1631 INTEL_PIPE_CRC_SOURCE_PLANE2
,
1632 INTEL_PIPE_CRC_SOURCE_PF
,
1633 INTEL_PIPE_CRC_SOURCE_PIPE
,
1634 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1635 INTEL_PIPE_CRC_SOURCE_TV
,
1636 INTEL_PIPE_CRC_SOURCE_DP_B
,
1637 INTEL_PIPE_CRC_SOURCE_DP_C
,
1638 INTEL_PIPE_CRC_SOURCE_DP_D
,
1639 INTEL_PIPE_CRC_SOURCE_AUTO
,
1640 INTEL_PIPE_CRC_SOURCE_MAX
,
1643 struct intel_pipe_crc_entry
{
1648 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1649 struct intel_pipe_crc
{
1651 bool opened
; /* exclusive access to the result file */
1652 struct intel_pipe_crc_entry
*entries
;
1653 enum intel_pipe_crc_source source
;
1655 wait_queue_head_t wq
;
1658 struct i915_frontbuffer_tracking
{
1662 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1669 struct i915_wa_reg
{
1672 /* bitmask representing WA bits */
1677 * RING_MAX_NONPRIV_SLOTS is per-engine but at this point we are only
1678 * allowing it for RCS as we don't foresee any requirement of having
1679 * a whitelist for other engines. When it is really required for
1680 * other engines then the limit need to be increased.
1682 #define I915_MAX_WA_REGS (16 + RING_MAX_NONPRIV_SLOTS)
1684 struct i915_workarounds
{
1685 struct i915_wa_reg reg
[I915_MAX_WA_REGS
];
1687 u32 hw_whitelist_count
[I915_NUM_RINGS
];
1690 struct i915_virtual_gpu
{
1694 struct i915_execbuffer_params
{
1695 struct drm_device
*dev
;
1696 struct drm_file
*file
;
1697 uint32_t dispatch_flags
;
1698 uint32_t args_batch_start_offset
;
1699 uint64_t batch_obj_vm_offset
;
1700 struct intel_engine_cs
*ring
;
1701 struct drm_i915_gem_object
*batch_obj
;
1702 struct intel_context
*ctx
;
1703 struct drm_i915_gem_request
*request
;
1706 /* used in computing the new watermarks state */
1707 struct intel_wm_config
{
1708 unsigned int num_pipes_active
;
1709 bool sprites_enabled
;
1710 bool sprites_scaled
;
1713 struct drm_i915_private
{
1714 struct drm_device
*dev
;
1715 struct kmem_cache
*objects
;
1716 struct kmem_cache
*vmas
;
1717 struct kmem_cache
*requests
;
1719 const struct intel_device_info info
;
1721 int relative_constants_mode
;
1725 struct intel_uncore uncore
;
1727 struct i915_virtual_gpu vgpu
;
1729 struct intel_guc guc
;
1731 struct intel_csr csr
;
1733 struct intel_gmbus gmbus
[GMBUS_NUM_PINS
];
1735 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1736 * controller on different i2c buses. */
1737 struct mutex gmbus_mutex
;
1740 * Base address of the gmbus and gpio block.
1742 uint32_t gpio_mmio_base
;
1744 /* MMIO base address for MIPI regs */
1745 uint32_t mipi_mmio_base
;
1747 uint32_t psr_mmio_base
;
1749 wait_queue_head_t gmbus_wait_queue
;
1751 struct pci_dev
*bridge_dev
;
1752 struct intel_engine_cs ring
[I915_NUM_RINGS
];
1753 struct drm_i915_gem_object
*semaphore_obj
;
1754 uint32_t last_seqno
, next_seqno
;
1756 struct drm_dma_handle
*status_page_dmah
;
1757 struct resource mch_res
;
1759 /* protects the irq masks */
1760 spinlock_t irq_lock
;
1762 /* protects the mmio flip data */
1763 spinlock_t mmio_flip_lock
;
1765 bool display_irqs_enabled
;
1767 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1768 struct pm_qos_request pm_qos
;
1770 /* Sideband mailbox protection */
1771 struct mutex sb_lock
;
1773 /** Cached value of IMR to avoid reads in updating the bitfield */
1776 u32 de_irq_mask
[I915_MAX_PIPES
];
1781 u32 pipestat_irq_mask
[I915_MAX_PIPES
];
1783 struct i915_hotplug hotplug
;
1784 struct intel_fbc fbc
;
1785 struct i915_drrs drrs
;
1786 struct intel_opregion opregion
;
1787 struct intel_vbt_data vbt
;
1789 bool preserve_bios_swizzle
;
1792 struct intel_overlay
*overlay
;
1794 /* backlight registers and fields in struct intel_panel */
1795 struct mutex backlight_lock
;
1798 bool no_aux_handshake
;
1800 /* protects panel power sequencer state */
1801 struct mutex pps_mutex
;
1803 struct drm_i915_fence_reg fence_regs
[I915_MAX_NUM_FENCES
]; /* assume 965 */
1804 int num_fence_regs
; /* 8 on pre-965, 16 otherwise */
1806 unsigned int fsb_freq
, mem_freq
, is_ddr3
;
1807 unsigned int skl_boot_cdclk
;
1808 unsigned int cdclk_freq
, max_cdclk_freq
, atomic_cdclk_freq
;
1809 unsigned int max_dotclk_freq
;
1810 unsigned int hpll_freq
;
1811 unsigned int czclk_freq
;
1814 * wq - Driver workqueue for GEM.
1816 * NOTE: Work items scheduled here are not allowed to grab any modeset
1817 * locks, for otherwise the flushing done in the pageflip code will
1818 * result in deadlocks.
1820 struct workqueue_struct
*wq
;
1822 /* Display functions */
1823 struct drm_i915_display_funcs display
;
1825 /* PCH chipset type */
1826 enum intel_pch pch_type
;
1827 unsigned short pch_id
;
1829 unsigned long quirks
;
1831 enum modeset_restore modeset_restore
;
1832 struct mutex modeset_restore_lock
;
1834 struct list_head vm_list
; /* Global list of all address spaces */
1835 struct i915_gtt gtt
; /* VM representing the global address space */
1837 struct i915_gem_mm mm
;
1838 DECLARE_HASHTABLE(mm_structs
, 7);
1839 struct mutex mm_lock
;
1841 /* Kernel Modesetting */
1843 struct sdvo_device_mapping sdvo_mappings
[2];
1845 struct drm_crtc
*plane_to_crtc_mapping
[I915_MAX_PIPES
];
1846 struct drm_crtc
*pipe_to_crtc_mapping
[I915_MAX_PIPES
];
1847 wait_queue_head_t pending_flip_queue
;
1849 #ifdef CONFIG_DEBUG_FS
1850 struct intel_pipe_crc pipe_crc
[I915_MAX_PIPES
];
1853 /* dpll and cdclk state is protected by connection_mutex */
1854 int num_shared_dpll
;
1855 struct intel_shared_dpll shared_dplls
[I915_NUM_PLLS
];
1857 unsigned int active_crtcs
;
1858 unsigned int min_pixclk
[I915_MAX_PIPES
];
1860 int dpio_phy_iosf_port
[I915_NUM_PHYS_VLV
];
1862 struct i915_workarounds workarounds
;
1864 /* Reclocking support */
1865 bool render_reclock_avail
;
1867 struct i915_frontbuffer_tracking fb_tracking
;
1871 bool mchbar_need_disable
;
1873 struct intel_l3_parity l3_parity
;
1875 /* Cannot be determined by PCIID. You must always read a register. */
1878 /* gen6+ rps state */
1879 struct intel_gen6_power_mgmt rps
;
1881 /* ilk-only ips/rps state. Everything in here is protected by the global
1882 * mchdev_lock in intel_pm.c */
1883 struct intel_ilk_power_mgmt ips
;
1885 struct i915_power_domains power_domains
;
1887 struct i915_psr psr
;
1889 struct i915_gpu_error gpu_error
;
1891 struct drm_i915_gem_object
*vlv_pctx
;
1893 #ifdef CONFIG_DRM_FBDEV_EMULATION
1894 /* list of fbdev register on this device */
1895 struct intel_fbdev
*fbdev
;
1896 struct work_struct fbdev_suspend_work
;
1899 struct drm_property
*broadcast_rgb_property
;
1900 struct drm_property
*force_audio_property
;
1902 /* hda/i915 audio component */
1903 struct i915_audio_component
*audio_component
;
1904 bool audio_component_registered
;
1906 * av_mutex - mutex for audio/video sync
1909 struct mutex av_mutex
;
1911 uint32_t hw_context_size
;
1912 struct list_head context_list
;
1916 u32 chv_phy_control
;
1919 bool suspended_to_idle
;
1920 struct i915_suspend_saved_registers regfile
;
1921 struct vlv_s0ix_state vlv_s0ix_state
;
1925 * Raw watermark latency values:
1926 * in 0.1us units for WM0,
1927 * in 0.5us units for WM1+.
1930 uint16_t pri_latency
[5];
1932 uint16_t spr_latency
[5];
1934 uint16_t cur_latency
[5];
1936 * Raw watermark memory latency values
1937 * for SKL for all 8 levels
1940 uint16_t skl_latency
[8];
1942 /* Committed wm config */
1943 struct intel_wm_config config
;
1946 * The skl_wm_values structure is a bit too big for stack
1947 * allocation, so we keep the staging struct where we store
1948 * intermediate results here instead.
1950 struct skl_wm_values skl_results
;
1952 /* current hardware state */
1954 struct ilk_wm_values hw
;
1955 struct skl_wm_values skl_hw
;
1956 struct vlv_wm_values vlv
;
1962 struct i915_runtime_pm pm
;
1964 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
1966 int (*execbuf_submit
)(struct i915_execbuffer_params
*params
,
1967 struct drm_i915_gem_execbuffer2
*args
,
1968 struct list_head
*vmas
);
1969 int (*init_rings
)(struct drm_device
*dev
);
1970 void (*cleanup_ring
)(struct intel_engine_cs
*ring
);
1971 void (*stop_ring
)(struct intel_engine_cs
*ring
);
1974 struct intel_context
*kernel_context
;
1976 bool edp_low_vswing
;
1978 /* perform PHY state sanity checks? */
1979 bool chv_phy_assert
[2];
1981 struct intel_encoder
*dig_port_map
[I915_MAX_PORTS
];
1984 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
1985 * will be rejected. Instead look for a better place.
1989 static inline struct drm_i915_private
*to_i915(const struct drm_device
*dev
)
1991 return dev
->dev_private
;
1994 static inline struct drm_i915_private
*dev_to_i915(struct device
*dev
)
1996 return to_i915(dev_get_drvdata(dev
));
1999 static inline struct drm_i915_private
*guc_to_i915(struct intel_guc
*guc
)
2001 return container_of(guc
, struct drm_i915_private
, guc
);
2004 /* Iterate over initialised rings */
2005 #define for_each_ring(ring__, dev_priv__, i__) \
2006 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
2007 for_each_if ((((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__))))
2009 enum hdmi_force_audio
{
2010 HDMI_AUDIO_OFF_DVI
= -2, /* no aux data for HDMI-DVI converter */
2011 HDMI_AUDIO_OFF
, /* force turn off HDMI audio */
2012 HDMI_AUDIO_AUTO
, /* trust EDID */
2013 HDMI_AUDIO_ON
, /* force turn on HDMI audio */
2016 #define I915_GTT_OFFSET_NONE ((u32)-1)
2018 struct drm_i915_gem_object_ops
{
2019 /* Interface between the GEM object and its backing storage.
2020 * get_pages() is called once prior to the use of the associated set
2021 * of pages before to binding them into the GTT, and put_pages() is
2022 * called after we no longer need them. As we expect there to be
2023 * associated cost with migrating pages between the backing storage
2024 * and making them available for the GPU (e.g. clflush), we may hold
2025 * onto the pages after they are no longer referenced by the GPU
2026 * in case they may be used again shortly (for example migrating the
2027 * pages to a different memory domain within the GTT). put_pages()
2028 * will therefore most likely be called when the object itself is
2029 * being released or under memory pressure (where we attempt to
2030 * reap pages for the shrinker).
2032 int (*get_pages
)(struct drm_i915_gem_object
*);
2033 void (*put_pages
)(struct drm_i915_gem_object
*);
2034 int (*dmabuf_export
)(struct drm_i915_gem_object
*);
2035 void (*release
)(struct drm_i915_gem_object
*);
2039 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2040 * considered to be the frontbuffer for the given plane interface-wise. This
2041 * doesn't mean that the hw necessarily already scans it out, but that any
2042 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
2044 * We have one bit per pipe and per scanout plane type.
2046 #define INTEL_MAX_SPRITE_BITS_PER_PIPE 5
2047 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2048 #define INTEL_FRONTBUFFER_BITS \
2049 (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES)
2050 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
2051 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2052 #define INTEL_FRONTBUFFER_CURSOR(pipe) \
2053 (1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2054 #define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \
2055 (1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2056 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2057 (1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2058 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2059 (0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2061 struct drm_i915_gem_object
{
2062 struct drm_gem_object base
;
2064 const struct drm_i915_gem_object_ops
*ops
;
2066 /** List of VMAs backed by this object */
2067 struct list_head vma_list
;
2069 /** Stolen memory for this object, instead of being backed by shmem. */
2070 struct drm_mm_node
*stolen
;
2071 struct list_head global_list
;
2073 struct list_head ring_list
[I915_NUM_RINGS
];
2074 /** Used in execbuf to temporarily hold a ref */
2075 struct list_head obj_exec_link
;
2077 struct list_head batch_pool_link
;
2080 * This is set if the object is on the active lists (has pending
2081 * rendering and so a non-zero seqno), and is not set if it i s on
2082 * inactive (ready to be unbound) list.
2084 unsigned int active
:I915_NUM_RINGS
;
2087 * This is set if the object has been written to since last bound
2090 unsigned int dirty
:1;
2093 * Fence register bits (if any) for this object. Will be set
2094 * as needed when mapped into the GTT.
2095 * Protected by dev->struct_mutex.
2097 signed int fence_reg
:I915_MAX_NUM_FENCE_BITS
;
2100 * Advice: are the backing pages purgeable?
2102 unsigned int madv
:2;
2105 * Current tiling mode for the object.
2107 unsigned int tiling_mode
:2;
2109 * Whether the tiling parameters for the currently associated fence
2110 * register have changed. Note that for the purposes of tracking
2111 * tiling changes we also treat the unfenced register, the register
2112 * slot that the object occupies whilst it executes a fenced
2113 * command (such as BLT on gen2/3), as a "fence".
2115 unsigned int fence_dirty
:1;
2118 * Is the object at the current location in the gtt mappable and
2119 * fenceable? Used to avoid costly recalculations.
2121 unsigned int map_and_fenceable
:1;
2124 * Whether the current gtt mapping needs to be mappable (and isn't just
2125 * mappable by accident). Track pin and fault separate for a more
2126 * accurate mappable working set.
2128 unsigned int fault_mappable
:1;
2131 * Is the object to be mapped as read-only to the GPU
2132 * Only honoured if hardware has relevant pte bit
2134 unsigned long gt_ro
:1;
2135 unsigned int cache_level
:3;
2136 unsigned int cache_dirty
:1;
2138 unsigned int frontbuffer_bits
:INTEL_FRONTBUFFER_BITS
;
2140 unsigned int pin_display
;
2142 struct sg_table
*pages
;
2143 int pages_pin_count
;
2145 struct scatterlist
*sg
;
2149 /* prime dma-buf support */
2150 void *dma_buf_vmapping
;
2153 /** Breadcrumb of last rendering to the buffer.
2154 * There can only be one writer, but we allow for multiple readers.
2155 * If there is a writer that necessarily implies that all other
2156 * read requests are complete - but we may only be lazily clearing
2157 * the read requests. A read request is naturally the most recent
2158 * request on a ring, so we may have two different write and read
2159 * requests on one ring where the write request is older than the
2160 * read request. This allows for the CPU to read from an active
2161 * buffer by only waiting for the write to complete.
2163 struct drm_i915_gem_request
*last_read_req
[I915_NUM_RINGS
];
2164 struct drm_i915_gem_request
*last_write_req
;
2165 /** Breadcrumb of last fenced GPU access to the buffer. */
2166 struct drm_i915_gem_request
*last_fenced_req
;
2168 /** Current tiling stride for the object, if it's tiled. */
2171 /** References from framebuffers, locks out tiling changes. */
2172 unsigned long framebuffer_references
;
2174 /** Record of address bit 17 of each page at last unbind. */
2175 unsigned long *bit_17
;
2178 /** for phy allocated objects */
2179 struct drm_dma_handle
*phys_handle
;
2181 struct i915_gem_userptr
{
2183 unsigned read_only
:1;
2184 unsigned workers
:4;
2185 #define I915_GEM_USERPTR_MAX_WORKERS 15
2187 struct i915_mm_struct
*mm
;
2188 struct i915_mmu_object
*mmu_object
;
2189 struct work_struct
*work
;
2193 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
2195 void i915_gem_track_fb(struct drm_i915_gem_object
*old
,
2196 struct drm_i915_gem_object
*new,
2197 unsigned frontbuffer_bits
);
2200 * Request queue structure.
2202 * The request queue allows us to note sequence numbers that have been emitted
2203 * and may be associated with active buffers to be retired.
2205 * By keeping this list, we can avoid having to do questionable sequence
2206 * number comparisons on buffer last_read|write_seqno. It also allows an
2207 * emission time to be associated with the request for tracking how far ahead
2208 * of the GPU the submission is.
2210 * The requests are reference counted, so upon creation they should have an
2211 * initial reference taken using kref_init
2213 struct drm_i915_gem_request
{
2216 /** On Which ring this request was generated */
2217 struct drm_i915_private
*i915
;
2218 struct intel_engine_cs
*ring
;
2220 /** GEM sequence number associated with the previous request,
2221 * when the HWS breadcrumb is equal to this the GPU is processing
2226 /** GEM sequence number associated with this request,
2227 * when the HWS breadcrumb is equal or greater than this the GPU
2228 * has finished processing this request.
2232 /** Position in the ringbuffer of the start of the request */
2236 * Position in the ringbuffer of the start of the postfix.
2237 * This is required to calculate the maximum available ringbuffer
2238 * space without overwriting the postfix.
2242 /** Position in the ringbuffer of the end of the whole request */
2246 * Context and ring buffer related to this request
2247 * Contexts are refcounted, so when this request is associated with a
2248 * context, we must increment the context's refcount, to guarantee that
2249 * it persists while any request is linked to it. Requests themselves
2250 * are also refcounted, so the request will only be freed when the last
2251 * reference to it is dismissed, and the code in
2252 * i915_gem_request_free() will then decrement the refcount on the
2255 struct intel_context
*ctx
;
2256 struct intel_ringbuffer
*ringbuf
;
2258 /** Batch buffer related to this request if any (used for
2259 error state dump only) */
2260 struct drm_i915_gem_object
*batch_obj
;
2262 /** Time at which this request was emitted, in jiffies. */
2263 unsigned long emitted_jiffies
;
2265 /** global list entry for this request */
2266 struct list_head list
;
2268 struct drm_i915_file_private
*file_priv
;
2269 /** file_priv list entry for this request */
2270 struct list_head client_list
;
2272 /** process identifier submitting this request */
2276 * The ELSP only accepts two elements at a time, so we queue
2277 * context/tail pairs on a given queue (ring->execlist_queue) until the
2278 * hardware is available. The queue serves a double purpose: we also use
2279 * it to keep track of the up to 2 contexts currently in the hardware
2280 * (usually one in execution and the other queued up by the GPU): We
2281 * only remove elements from the head of the queue when the hardware
2282 * informs us that an element has been completed.
2284 * All accesses to the queue are mediated by a spinlock
2285 * (ring->execlist_lock).
2288 /** Execlist link in the submission queue.*/
2289 struct list_head execlist_link
;
2291 /** Execlists no. of times this request has been sent to the ELSP */
2296 struct drm_i915_gem_request
* __must_check
2297 i915_gem_request_alloc(struct intel_engine_cs
*engine
,
2298 struct intel_context
*ctx
);
2299 void i915_gem_request_cancel(struct drm_i915_gem_request
*req
);
2300 void i915_gem_request_free(struct kref
*req_ref
);
2301 int i915_gem_request_add_to_client(struct drm_i915_gem_request
*req
,
2302 struct drm_file
*file
);
2304 static inline uint32_t
2305 i915_gem_request_get_seqno(struct drm_i915_gem_request
*req
)
2307 return req
? req
->seqno
: 0;
2310 static inline struct intel_engine_cs
*
2311 i915_gem_request_get_ring(struct drm_i915_gem_request
*req
)
2313 return req
? req
->ring
: NULL
;
2316 static inline struct drm_i915_gem_request
*
2317 i915_gem_request_reference(struct drm_i915_gem_request
*req
)
2320 kref_get(&req
->ref
);
2325 i915_gem_request_unreference(struct drm_i915_gem_request
*req
)
2327 WARN_ON(!mutex_is_locked(&req
->ring
->dev
->struct_mutex
));
2328 kref_put(&req
->ref
, i915_gem_request_free
);
2332 i915_gem_request_unreference__unlocked(struct drm_i915_gem_request
*req
)
2334 struct drm_device
*dev
;
2339 dev
= req
->ring
->dev
;
2340 if (kref_put_mutex(&req
->ref
, i915_gem_request_free
, &dev
->struct_mutex
))
2341 mutex_unlock(&dev
->struct_mutex
);
2344 static inline void i915_gem_request_assign(struct drm_i915_gem_request
**pdst
,
2345 struct drm_i915_gem_request
*src
)
2348 i915_gem_request_reference(src
);
2351 i915_gem_request_unreference(*pdst
);
2357 * XXX: i915_gem_request_completed should be here but currently needs the
2358 * definition of i915_seqno_passed() which is below. It will be moved in
2359 * a later patch when the call to i915_seqno_passed() is obsoleted...
2363 * A command that requires special handling by the command parser.
2365 struct drm_i915_cmd_descriptor
{
2367 * Flags describing how the command parser processes the command.
2369 * CMD_DESC_FIXED: The command has a fixed length if this is set,
2370 * a length mask if not set
2371 * CMD_DESC_SKIP: The command is allowed but does not follow the
2372 * standard length encoding for the opcode range in
2374 * CMD_DESC_REJECT: The command is never allowed
2375 * CMD_DESC_REGISTER: The command should be checked against the
2376 * register whitelist for the appropriate ring
2377 * CMD_DESC_MASTER: The command is allowed if the submitting process
2381 #define CMD_DESC_FIXED (1<<0)
2382 #define CMD_DESC_SKIP (1<<1)
2383 #define CMD_DESC_REJECT (1<<2)
2384 #define CMD_DESC_REGISTER (1<<3)
2385 #define CMD_DESC_BITMASK (1<<4)
2386 #define CMD_DESC_MASTER (1<<5)
2389 * The command's unique identification bits and the bitmask to get them.
2390 * This isn't strictly the opcode field as defined in the spec and may
2391 * also include type, subtype, and/or subop fields.
2399 * The command's length. The command is either fixed length (i.e. does
2400 * not include a length field) or has a length field mask. The flag
2401 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
2402 * a length mask. All command entries in a command table must include
2403 * length information.
2411 * Describes where to find a register address in the command to check
2412 * against the ring's register whitelist. Only valid if flags has the
2413 * CMD_DESC_REGISTER bit set.
2415 * A non-zero step value implies that the command may access multiple
2416 * registers in sequence (e.g. LRI), in that case step gives the
2417 * distance in dwords between individual offset fields.
2425 #define MAX_CMD_DESC_BITMASKS 3
2427 * Describes command checks where a particular dword is masked and
2428 * compared against an expected value. If the command does not match
2429 * the expected value, the parser rejects it. Only valid if flags has
2430 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
2433 * If the check specifies a non-zero condition_mask then the parser
2434 * only performs the check when the bits specified by condition_mask
2441 u32 condition_offset
;
2443 } bits
[MAX_CMD_DESC_BITMASKS
];
2447 * A table of commands requiring special handling by the command parser.
2449 * Each ring has an array of tables. Each table consists of an array of command
2450 * descriptors, which must be sorted with command opcodes in ascending order.
2452 struct drm_i915_cmd_table
{
2453 const struct drm_i915_cmd_descriptor
*table
;
2457 /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
2458 #define __I915__(p) ({ \
2459 struct drm_i915_private *__p; \
2460 if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
2461 __p = (struct drm_i915_private *)p; \
2462 else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
2463 __p = to_i915((struct drm_device *)p); \
2468 #define INTEL_INFO(p) (&__I915__(p)->info)
2469 #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id)
2470 #define INTEL_REVID(p) (__I915__(p)->dev->pdev->revision)
2472 #define REVID_FOREVER 0xff
2474 * Return true if revision is in range [since,until] inclusive.
2476 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
2478 #define IS_REVID(p, since, until) \
2479 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
2481 #define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577)
2482 #define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562)
2483 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
2484 #define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572)
2485 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
2486 #define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592)
2487 #define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772)
2488 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
2489 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
2490 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
2491 #define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42)
2492 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
2493 #define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001)
2494 #define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011)
2495 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
2496 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
2497 #define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046)
2498 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
2499 #define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \
2500 INTEL_DEVID(dev) == 0x0152 || \
2501 INTEL_DEVID(dev) == 0x015a)
2502 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
2503 #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_cherryview)
2504 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
2505 #define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_cherryview && IS_GEN8(dev))
2506 #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake)
2507 #define IS_BROXTON(dev) (INTEL_INFO(dev)->is_broxton)
2508 #define IS_KABYLAKE(dev) (INTEL_INFO(dev)->is_kabylake)
2509 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
2510 #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
2511 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
2512 #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
2513 ((INTEL_DEVID(dev) & 0xf) == 0x6 || \
2514 (INTEL_DEVID(dev) & 0xf) == 0xb || \
2515 (INTEL_DEVID(dev) & 0xf) == 0xe))
2516 /* ULX machines are also considered ULT. */
2517 #define IS_BDW_ULX(dev) (IS_BROADWELL(dev) && \
2518 (INTEL_DEVID(dev) & 0xf) == 0xe)
2519 #define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \
2520 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2521 #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
2522 (INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
2523 #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
2524 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2525 /* ULX machines are also considered ULT. */
2526 #define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \
2527 INTEL_DEVID(dev) == 0x0A1E)
2528 #define IS_SKL_ULT(dev) (INTEL_DEVID(dev) == 0x1906 || \
2529 INTEL_DEVID(dev) == 0x1913 || \
2530 INTEL_DEVID(dev) == 0x1916 || \
2531 INTEL_DEVID(dev) == 0x1921 || \
2532 INTEL_DEVID(dev) == 0x1926)
2533 #define IS_SKL_ULX(dev) (INTEL_DEVID(dev) == 0x190E || \
2534 INTEL_DEVID(dev) == 0x1915 || \
2535 INTEL_DEVID(dev) == 0x191E)
2536 #define IS_KBL_ULT(dev) (INTEL_DEVID(dev) == 0x5906 || \
2537 INTEL_DEVID(dev) == 0x5913 || \
2538 INTEL_DEVID(dev) == 0x5916 || \
2539 INTEL_DEVID(dev) == 0x5921 || \
2540 INTEL_DEVID(dev) == 0x5926)
2541 #define IS_KBL_ULX(dev) (INTEL_DEVID(dev) == 0x590E || \
2542 INTEL_DEVID(dev) == 0x5915 || \
2543 INTEL_DEVID(dev) == 0x591E)
2544 #define IS_SKL_GT3(dev) (IS_SKYLAKE(dev) && \
2545 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2546 #define IS_SKL_GT4(dev) (IS_SKYLAKE(dev) && \
2547 (INTEL_DEVID(dev) & 0x00F0) == 0x0030)
2549 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
2551 #define SKL_REVID_A0 0x0
2552 #define SKL_REVID_B0 0x1
2553 #define SKL_REVID_C0 0x2
2554 #define SKL_REVID_D0 0x3
2555 #define SKL_REVID_E0 0x4
2556 #define SKL_REVID_F0 0x5
2558 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
2560 #define BXT_REVID_A0 0x0
2561 #define BXT_REVID_A1 0x1
2562 #define BXT_REVID_B0 0x3
2563 #define BXT_REVID_C0 0x9
2565 #define IS_BXT_REVID(p, since, until) (IS_BROXTON(p) && IS_REVID(p, since, until))
2568 * The genX designation typically refers to the render engine, so render
2569 * capability related checks should use IS_GEN, while display and other checks
2570 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2573 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
2574 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
2575 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
2576 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
2577 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
2578 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
2579 #define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8)
2580 #define IS_GEN9(dev) (INTEL_INFO(dev)->gen == 9)
2582 #define RENDER_RING (1<<RCS)
2583 #define BSD_RING (1<<VCS)
2584 #define BLT_RING (1<<BCS)
2585 #define VEBOX_RING (1<<VECS)
2586 #define BSD2_RING (1<<VCS2)
2587 #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING)
2588 #define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING)
2589 #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING)
2590 #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
2591 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
2592 #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
2593 __I915__(dev)->ellc_size)
2594 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
2596 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
2597 #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8)
2598 #define USES_PPGTT(dev) (i915.enable_ppgtt)
2599 #define USES_FULL_PPGTT(dev) (i915.enable_ppgtt >= 2)
2600 #define USES_FULL_48BIT_PPGTT(dev) (i915.enable_ppgtt == 3)
2602 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
2603 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
2605 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2606 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
2608 /* WaRsDisableCoarsePowerGating:skl,bxt */
2609 #define NEEDS_WaRsDisableCoarsePowerGating(dev) (IS_BXT_REVID(dev, 0, BXT_REVID_A1) || \
2610 ((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) && \
2611 IS_SKL_REVID(dev, 0, SKL_REVID_F0)))
2613 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2614 * even when in MSI mode. This results in spurious interrupt warnings if the
2615 * legacy irq no. is shared with another device. The kernel then disables that
2616 * interrupt source and so prevents the other device from working properly.
2618 #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2619 #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2621 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2622 * rows, which changed the alignment requirements and fence programming.
2624 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
2626 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
2627 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
2629 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
2630 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
2631 #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
2633 #define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev))
2635 #define HAS_DP_MST(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2636 INTEL_INFO(dev)->gen >= 9)
2638 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
2639 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
2640 #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2641 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \
2642 IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
2643 #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \
2644 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \
2645 IS_CHERRYVIEW(dev) || IS_SKYLAKE(dev) || \
2647 #define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6)
2648 #define HAS_RC6p(dev) (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
2650 #define HAS_CSR(dev) (IS_GEN9(dev))
2652 #define HAS_GUC_UCODE(dev) (IS_GEN9(dev) && !IS_KABYLAKE(dev))
2653 #define HAS_GUC_SCHED(dev) (IS_GEN9(dev) && !IS_KABYLAKE(dev))
2655 #define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \
2656 INTEL_INFO(dev)->gen >= 8)
2658 #define HAS_CORE_RING_FREQ(dev) (INTEL_INFO(dev)->gen >= 6 && \
2659 !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && \
2662 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
2663 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2664 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2665 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2666 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2667 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2668 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2669 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2670 #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
2671 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
2673 #define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
2674 #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
2675 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
2676 #define HAS_PCH_LPT_LP(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
2677 #define HAS_PCH_LPT_H(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
2678 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
2679 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
2680 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
2681 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
2683 #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || \
2684 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
2686 /* DPF == dynamic parity feature */
2687 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
2688 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
2690 #define GT_FREQUENCY_MULTIPLIER 50
2691 #define GEN9_FREQ_SCALER 3
2693 #include "i915_trace.h"
2695 extern const struct drm_ioctl_desc i915_ioctls
[];
2696 extern int i915_max_ioctl
;
2698 extern int i915_suspend_switcheroo(struct drm_device
*dev
, pm_message_t state
);
2699 extern int i915_resume_switcheroo(struct drm_device
*dev
);
2702 extern int i915_driver_load(struct drm_device
*, unsigned long flags
);
2703 extern int i915_driver_unload(struct drm_device
*);
2704 extern int i915_driver_open(struct drm_device
*dev
, struct drm_file
*file
);
2705 extern void i915_driver_lastclose(struct drm_device
* dev
);
2706 extern void i915_driver_preclose(struct drm_device
*dev
,
2707 struct drm_file
*file
);
2708 extern void i915_driver_postclose(struct drm_device
*dev
,
2709 struct drm_file
*file
);
2710 #ifdef CONFIG_COMPAT
2711 extern long i915_compat_ioctl(struct file
*filp
, unsigned int cmd
,
2714 extern int intel_gpu_reset(struct drm_device
*dev
);
2715 extern bool intel_has_gpu_reset(struct drm_device
*dev
);
2716 extern int i915_reset(struct drm_device
*dev
);
2717 extern unsigned long i915_chipset_val(struct drm_i915_private
*dev_priv
);
2718 extern unsigned long i915_mch_val(struct drm_i915_private
*dev_priv
);
2719 extern unsigned long i915_gfx_val(struct drm_i915_private
*dev_priv
);
2720 extern void i915_update_gfx_val(struct drm_i915_private
*dev_priv
);
2721 int vlv_force_gfx_clock(struct drm_i915_private
*dev_priv
, bool on
);
2723 /* intel_hotplug.c */
2724 void intel_hpd_irq_handler(struct drm_device
*dev
, u32 pin_mask
, u32 long_mask
);
2725 void intel_hpd_init(struct drm_i915_private
*dev_priv
);
2726 void intel_hpd_init_work(struct drm_i915_private
*dev_priv
);
2727 void intel_hpd_cancel_work(struct drm_i915_private
*dev_priv
);
2728 bool intel_hpd_pin_to_port(enum hpd_pin pin
, enum port
*port
);
2731 void i915_queue_hangcheck(struct drm_device
*dev
);
2733 void i915_handle_error(struct drm_device
*dev
, bool wedged
,
2734 const char *fmt
, ...);
2736 extern void intel_irq_init(struct drm_i915_private
*dev_priv
);
2737 int intel_irq_install(struct drm_i915_private
*dev_priv
);
2738 void intel_irq_uninstall(struct drm_i915_private
*dev_priv
);
2740 extern void intel_uncore_sanitize(struct drm_device
*dev
);
2741 extern void intel_uncore_early_sanitize(struct drm_device
*dev
,
2742 bool restore_forcewake
);
2743 extern void intel_uncore_init(struct drm_device
*dev
);
2744 extern bool intel_uncore_unclaimed_mmio(struct drm_i915_private
*dev_priv
);
2745 extern bool intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private
*dev_priv
);
2746 extern void intel_uncore_fini(struct drm_device
*dev
);
2747 extern void intel_uncore_forcewake_reset(struct drm_device
*dev
, bool restore
);
2748 const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id
);
2749 void intel_uncore_forcewake_get(struct drm_i915_private
*dev_priv
,
2750 enum forcewake_domains domains
);
2751 void intel_uncore_forcewake_put(struct drm_i915_private
*dev_priv
,
2752 enum forcewake_domains domains
);
2753 /* Like above but the caller must manage the uncore.lock itself.
2754 * Must be used with I915_READ_FW and friends.
2756 void intel_uncore_forcewake_get__locked(struct drm_i915_private
*dev_priv
,
2757 enum forcewake_domains domains
);
2758 void intel_uncore_forcewake_put__locked(struct drm_i915_private
*dev_priv
,
2759 enum forcewake_domains domains
);
2760 void assert_forcewakes_inactive(struct drm_i915_private
*dev_priv
);
2761 static inline bool intel_vgpu_active(struct drm_device
*dev
)
2763 return to_i915(dev
)->vgpu
.active
;
2767 i915_enable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
2771 i915_disable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
2774 void valleyview_enable_display_irqs(struct drm_i915_private
*dev_priv
);
2775 void valleyview_disable_display_irqs(struct drm_i915_private
*dev_priv
);
2776 void i915_hotplug_interrupt_update(struct drm_i915_private
*dev_priv
,
2779 void ilk_update_display_irq(struct drm_i915_private
*dev_priv
,
2780 uint32_t interrupt_mask
,
2781 uint32_t enabled_irq_mask
);
2783 ilk_enable_display_irq(struct drm_i915_private
*dev_priv
, uint32_t bits
)
2785 ilk_update_display_irq(dev_priv
, bits
, bits
);
2788 ilk_disable_display_irq(struct drm_i915_private
*dev_priv
, uint32_t bits
)
2790 ilk_update_display_irq(dev_priv
, bits
, 0);
2792 void bdw_update_pipe_irq(struct drm_i915_private
*dev_priv
,
2794 uint32_t interrupt_mask
,
2795 uint32_t enabled_irq_mask
);
2796 static inline void bdw_enable_pipe_irq(struct drm_i915_private
*dev_priv
,
2797 enum pipe pipe
, uint32_t bits
)
2799 bdw_update_pipe_irq(dev_priv
, pipe
, bits
, bits
);
2801 static inline void bdw_disable_pipe_irq(struct drm_i915_private
*dev_priv
,
2802 enum pipe pipe
, uint32_t bits
)
2804 bdw_update_pipe_irq(dev_priv
, pipe
, bits
, 0);
2806 void ibx_display_interrupt_update(struct drm_i915_private
*dev_priv
,
2807 uint32_t interrupt_mask
,
2808 uint32_t enabled_irq_mask
);
2810 ibx_enable_display_interrupt(struct drm_i915_private
*dev_priv
, uint32_t bits
)
2812 ibx_display_interrupt_update(dev_priv
, bits
, bits
);
2815 ibx_disable_display_interrupt(struct drm_i915_private
*dev_priv
, uint32_t bits
)
2817 ibx_display_interrupt_update(dev_priv
, bits
, 0);
2822 int i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
2823 struct drm_file
*file_priv
);
2824 int i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
2825 struct drm_file
*file_priv
);
2826 int i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
2827 struct drm_file
*file_priv
);
2828 int i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
2829 struct drm_file
*file_priv
);
2830 int i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
2831 struct drm_file
*file_priv
);
2832 int i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
2833 struct drm_file
*file_priv
);
2834 int i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
2835 struct drm_file
*file_priv
);
2836 void i915_gem_execbuffer_move_to_active(struct list_head
*vmas
,
2837 struct drm_i915_gem_request
*req
);
2838 void i915_gem_execbuffer_retire_commands(struct i915_execbuffer_params
*params
);
2839 int i915_gem_ringbuffer_submission(struct i915_execbuffer_params
*params
,
2840 struct drm_i915_gem_execbuffer2
*args
,
2841 struct list_head
*vmas
);
2842 int i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
2843 struct drm_file
*file_priv
);
2844 int i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
2845 struct drm_file
*file_priv
);
2846 int i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
2847 struct drm_file
*file_priv
);
2848 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
2849 struct drm_file
*file
);
2850 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
2851 struct drm_file
*file
);
2852 int i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
2853 struct drm_file
*file_priv
);
2854 int i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
2855 struct drm_file
*file_priv
);
2856 int i915_gem_set_tiling(struct drm_device
*dev
, void *data
,
2857 struct drm_file
*file_priv
);
2858 int i915_gem_get_tiling(struct drm_device
*dev
, void *data
,
2859 struct drm_file
*file_priv
);
2860 int i915_gem_init_userptr(struct drm_device
*dev
);
2861 int i915_gem_userptr_ioctl(struct drm_device
*dev
, void *data
,
2862 struct drm_file
*file
);
2863 int i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
2864 struct drm_file
*file_priv
);
2865 int i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
,
2866 struct drm_file
*file_priv
);
2867 void i915_gem_load_init(struct drm_device
*dev
);
2868 void i915_gem_load_cleanup(struct drm_device
*dev
);
2869 void *i915_gem_object_alloc(struct drm_device
*dev
);
2870 void i915_gem_object_free(struct drm_i915_gem_object
*obj
);
2871 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
2872 const struct drm_i915_gem_object_ops
*ops
);
2873 struct drm_i915_gem_object
*i915_gem_alloc_object(struct drm_device
*dev
,
2875 struct drm_i915_gem_object
*i915_gem_object_create_from_data(
2876 struct drm_device
*dev
, const void *data
, size_t size
);
2877 void i915_gem_free_object(struct drm_gem_object
*obj
);
2878 void i915_gem_vma_destroy(struct i915_vma
*vma
);
2880 /* Flags used by pin/bind&friends. */
2881 #define PIN_MAPPABLE (1<<0)
2882 #define PIN_NONBLOCK (1<<1)
2883 #define PIN_GLOBAL (1<<2)
2884 #define PIN_OFFSET_BIAS (1<<3)
2885 #define PIN_USER (1<<4)
2886 #define PIN_UPDATE (1<<5)
2887 #define PIN_ZONE_4G (1<<6)
2888 #define PIN_HIGH (1<<7)
2889 #define PIN_OFFSET_FIXED (1<<8)
2890 #define PIN_OFFSET_MASK (~4095)
2892 i915_gem_object_pin(struct drm_i915_gem_object
*obj
,
2893 struct i915_address_space
*vm
,
2897 i915_gem_object_ggtt_pin(struct drm_i915_gem_object
*obj
,
2898 const struct i915_ggtt_view
*view
,
2902 int i915_vma_bind(struct i915_vma
*vma
, enum i915_cache_level cache_level
,
2904 void __i915_vma_set_map_and_fenceable(struct i915_vma
*vma
);
2905 int __must_check
i915_vma_unbind(struct i915_vma
*vma
);
2907 * BEWARE: Do not use the function below unless you can _absolutely_
2908 * _guarantee_ VMA in question is _not in use_ anywhere.
2910 int __must_check
__i915_vma_unbind_no_wait(struct i915_vma
*vma
);
2911 int i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
);
2912 void i915_gem_release_all_mmaps(struct drm_i915_private
*dev_priv
);
2913 void i915_gem_release_mmap(struct drm_i915_gem_object
*obj
);
2915 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object
*obj
,
2916 int *needs_clflush
);
2918 int __must_check
i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
);
2920 static inline int __sg_page_count(struct scatterlist
*sg
)
2922 return sg
->length
>> PAGE_SHIFT
;
2926 i915_gem_object_get_dirty_page(struct drm_i915_gem_object
*obj
, int n
);
2928 static inline struct page
*
2929 i915_gem_object_get_page(struct drm_i915_gem_object
*obj
, int n
)
2931 if (WARN_ON(n
>= obj
->base
.size
>> PAGE_SHIFT
))
2934 if (n
< obj
->get_page
.last
) {
2935 obj
->get_page
.sg
= obj
->pages
->sgl
;
2936 obj
->get_page
.last
= 0;
2939 while (obj
->get_page
.last
+ __sg_page_count(obj
->get_page
.sg
) <= n
) {
2940 obj
->get_page
.last
+= __sg_page_count(obj
->get_page
.sg
++);
2941 if (unlikely(sg_is_chain(obj
->get_page
.sg
)))
2942 obj
->get_page
.sg
= sg_chain_ptr(obj
->get_page
.sg
);
2945 return nth_page(sg_page(obj
->get_page
.sg
), n
- obj
->get_page
.last
);
2948 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object
*obj
)
2950 BUG_ON(obj
->pages
== NULL
);
2951 obj
->pages_pin_count
++;
2953 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object
*obj
)
2955 BUG_ON(obj
->pages_pin_count
== 0);
2956 obj
->pages_pin_count
--;
2959 int __must_check
i915_mutex_lock_interruptible(struct drm_device
*dev
);
2960 int i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
2961 struct intel_engine_cs
*to
,
2962 struct drm_i915_gem_request
**to_req
);
2963 void i915_vma_move_to_active(struct i915_vma
*vma
,
2964 struct drm_i915_gem_request
*req
);
2965 int i915_gem_dumb_create(struct drm_file
*file_priv
,
2966 struct drm_device
*dev
,
2967 struct drm_mode_create_dumb
*args
);
2968 int i915_gem_mmap_gtt(struct drm_file
*file_priv
, struct drm_device
*dev
,
2969 uint32_t handle
, uint64_t *offset
);
2971 * Returns true if seq1 is later than seq2.
2974 i915_seqno_passed(uint32_t seq1
, uint32_t seq2
)
2976 return (int32_t)(seq1
- seq2
) >= 0;
2979 static inline bool i915_gem_request_started(struct drm_i915_gem_request
*req
,
2980 bool lazy_coherency
)
2982 u32 seqno
= req
->ring
->get_seqno(req
->ring
, lazy_coherency
);
2983 return i915_seqno_passed(seqno
, req
->previous_seqno
);
2986 static inline bool i915_gem_request_completed(struct drm_i915_gem_request
*req
,
2987 bool lazy_coherency
)
2989 u32 seqno
= req
->ring
->get_seqno(req
->ring
, lazy_coherency
);
2990 return i915_seqno_passed(seqno
, req
->seqno
);
2993 int __must_check
i915_gem_get_seqno(struct drm_device
*dev
, u32
*seqno
);
2994 int __must_check
i915_gem_set_seqno(struct drm_device
*dev
, u32 seqno
);
2996 struct drm_i915_gem_request
*
2997 i915_gem_find_active_request(struct intel_engine_cs
*ring
);
2999 bool i915_gem_retire_requests(struct drm_device
*dev
);
3000 void i915_gem_retire_requests_ring(struct intel_engine_cs
*ring
);
3001 int __must_check
i915_gem_check_wedge(struct i915_gpu_error
*error
,
3002 bool interruptible
);
3004 static inline bool i915_reset_in_progress(struct i915_gpu_error
*error
)
3006 return unlikely(atomic_read(&error
->reset_counter
)
3007 & (I915_RESET_IN_PROGRESS_FLAG
| I915_WEDGED
));
3010 static inline bool i915_terminally_wedged(struct i915_gpu_error
*error
)
3012 return atomic_read(&error
->reset_counter
) & I915_WEDGED
;
3015 static inline u32
i915_reset_count(struct i915_gpu_error
*error
)
3017 return ((atomic_read(&error
->reset_counter
) & ~I915_WEDGED
) + 1) / 2;
3020 static inline bool i915_stop_ring_allow_ban(struct drm_i915_private
*dev_priv
)
3022 return dev_priv
->gpu_error
.stop_rings
== 0 ||
3023 dev_priv
->gpu_error
.stop_rings
& I915_STOP_RING_ALLOW_BAN
;
3026 static inline bool i915_stop_ring_allow_warn(struct drm_i915_private
*dev_priv
)
3028 return dev_priv
->gpu_error
.stop_rings
== 0 ||
3029 dev_priv
->gpu_error
.stop_rings
& I915_STOP_RING_ALLOW_WARN
;
3032 void i915_gem_reset(struct drm_device
*dev
);
3033 bool i915_gem_clflush_object(struct drm_i915_gem_object
*obj
, bool force
);
3034 int __must_check
i915_gem_init(struct drm_device
*dev
);
3035 int i915_gem_init_rings(struct drm_device
*dev
);
3036 int __must_check
i915_gem_init_hw(struct drm_device
*dev
);
3037 int i915_gem_l3_remap(struct drm_i915_gem_request
*req
, int slice
);
3038 void i915_gem_init_swizzling(struct drm_device
*dev
);
3039 void i915_gem_cleanup_ringbuffer(struct drm_device
*dev
);
3040 int __must_check
i915_gpu_idle(struct drm_device
*dev
);
3041 int __must_check
i915_gem_suspend(struct drm_device
*dev
);
3042 void __i915_add_request(struct drm_i915_gem_request
*req
,
3043 struct drm_i915_gem_object
*batch_obj
,
3045 #define i915_add_request(req) \
3046 __i915_add_request(req, NULL, true)
3047 #define i915_add_request_no_flush(req) \
3048 __i915_add_request(req, NULL, false)
3049 int __i915_wait_request(struct drm_i915_gem_request
*req
,
3050 unsigned reset_counter
,
3053 struct intel_rps_client
*rps
);
3054 int __must_check
i915_wait_request(struct drm_i915_gem_request
*req
);
3055 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
);
3057 i915_gem_object_wait_rendering(struct drm_i915_gem_object
*obj
,
3060 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
,
3063 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
);
3065 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
3067 const struct i915_ggtt_view
*view
);
3068 void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object
*obj
,
3069 const struct i915_ggtt_view
*view
);
3070 int i915_gem_object_attach_phys(struct drm_i915_gem_object
*obj
,
3072 int i915_gem_open(struct drm_device
*dev
, struct drm_file
*file
);
3073 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
);
3076 i915_gem_get_gtt_size(struct drm_device
*dev
, uint32_t size
, int tiling_mode
);
3078 i915_gem_get_gtt_alignment(struct drm_device
*dev
, uint32_t size
,
3079 int tiling_mode
, bool fenced
);
3081 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
3082 enum i915_cache_level cache_level
);
3084 struct drm_gem_object
*i915_gem_prime_import(struct drm_device
*dev
,
3085 struct dma_buf
*dma_buf
);
3087 struct dma_buf
*i915_gem_prime_export(struct drm_device
*dev
,
3088 struct drm_gem_object
*gem_obj
, int flags
);
3090 u64
i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object
*o
,
3091 const struct i915_ggtt_view
*view
);
3092 u64
i915_gem_obj_offset(struct drm_i915_gem_object
*o
,
3093 struct i915_address_space
*vm
);
3095 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object
*o
)
3097 return i915_gem_obj_ggtt_offset_view(o
, &i915_ggtt_view_normal
);
3100 bool i915_gem_obj_bound_any(struct drm_i915_gem_object
*o
);
3101 bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object
*o
,
3102 const struct i915_ggtt_view
*view
);
3103 bool i915_gem_obj_bound(struct drm_i915_gem_object
*o
,
3104 struct i915_address_space
*vm
);
3106 unsigned long i915_gem_obj_size(struct drm_i915_gem_object
*o
,
3107 struct i915_address_space
*vm
);
3109 i915_gem_obj_to_vma(struct drm_i915_gem_object
*obj
,
3110 struct i915_address_space
*vm
);
3112 i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object
*obj
,
3113 const struct i915_ggtt_view
*view
);
3116 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object
*obj
,
3117 struct i915_address_space
*vm
);
3119 i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object
*obj
,
3120 const struct i915_ggtt_view
*view
);
3122 static inline struct i915_vma
*
3123 i915_gem_obj_to_ggtt(struct drm_i915_gem_object
*obj
)
3125 return i915_gem_obj_to_ggtt_view(obj
, &i915_ggtt_view_normal
);
3127 bool i915_gem_obj_is_pinned(struct drm_i915_gem_object
*obj
);
3129 /* Some GGTT VM helpers */
3130 #define i915_obj_to_ggtt(obj) \
3131 (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
3132 static inline bool i915_is_ggtt(struct i915_address_space
*vm
)
3134 struct i915_address_space
*ggtt
=
3135 &((struct drm_i915_private
*)(vm
)->dev
->dev_private
)->gtt
.base
;
3139 static inline struct i915_hw_ppgtt
*
3140 i915_vm_to_ppgtt(struct i915_address_space
*vm
)
3142 WARN_ON(i915_is_ggtt(vm
));
3144 return container_of(vm
, struct i915_hw_ppgtt
, base
);
3148 static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object
*obj
)
3150 return i915_gem_obj_ggtt_bound_view(obj
, &i915_ggtt_view_normal
);
3153 static inline unsigned long
3154 i915_gem_obj_ggtt_size(struct drm_i915_gem_object
*obj
)
3156 return i915_gem_obj_size(obj
, i915_obj_to_ggtt(obj
));
3159 static inline int __must_check
3160 i915_gem_obj_ggtt_pin(struct drm_i915_gem_object
*obj
,
3164 return i915_gem_object_pin(obj
, i915_obj_to_ggtt(obj
),
3165 alignment
, flags
| PIN_GLOBAL
);
3169 i915_gem_object_ggtt_unbind(struct drm_i915_gem_object
*obj
)
3171 return i915_vma_unbind(i915_gem_obj_to_ggtt(obj
));
3174 void i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object
*obj
,
3175 const struct i915_ggtt_view
*view
);
3177 i915_gem_object_ggtt_unpin(struct drm_i915_gem_object
*obj
)
3179 i915_gem_object_ggtt_unpin_view(obj
, &i915_ggtt_view_normal
);
3182 /* i915_gem_fence.c */
3183 int __must_check
i915_gem_object_get_fence(struct drm_i915_gem_object
*obj
);
3184 int __must_check
i915_gem_object_put_fence(struct drm_i915_gem_object
*obj
);
3186 bool i915_gem_object_pin_fence(struct drm_i915_gem_object
*obj
);
3187 void i915_gem_object_unpin_fence(struct drm_i915_gem_object
*obj
);
3189 void i915_gem_restore_fences(struct drm_device
*dev
);
3191 void i915_gem_detect_bit_6_swizzle(struct drm_device
*dev
);
3192 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
3193 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
3195 /* i915_gem_context.c */
3196 int __must_check
i915_gem_context_init(struct drm_device
*dev
);
3197 void i915_gem_context_fini(struct drm_device
*dev
);
3198 void i915_gem_context_reset(struct drm_device
*dev
);
3199 int i915_gem_context_open(struct drm_device
*dev
, struct drm_file
*file
);
3200 int i915_gem_context_enable(struct drm_i915_gem_request
*req
);
3201 void i915_gem_context_close(struct drm_device
*dev
, struct drm_file
*file
);
3202 int i915_switch_context(struct drm_i915_gem_request
*req
);
3203 struct intel_context
*
3204 i915_gem_context_get(struct drm_i915_file_private
*file_priv
, u32 id
);
3205 void i915_gem_context_free(struct kref
*ctx_ref
);
3206 struct drm_i915_gem_object
*
3207 i915_gem_alloc_context_obj(struct drm_device
*dev
, size_t size
);
3208 static inline void i915_gem_context_reference(struct intel_context
*ctx
)
3210 kref_get(&ctx
->ref
);
3213 static inline void i915_gem_context_unreference(struct intel_context
*ctx
)
3215 kref_put(&ctx
->ref
, i915_gem_context_free
);
3218 static inline bool i915_gem_context_is_default(const struct intel_context
*c
)
3220 return c
->user_handle
== DEFAULT_CONTEXT_HANDLE
;
3223 int i915_gem_context_create_ioctl(struct drm_device
*dev
, void *data
,
3224 struct drm_file
*file
);
3225 int i915_gem_context_destroy_ioctl(struct drm_device
*dev
, void *data
,
3226 struct drm_file
*file
);
3227 int i915_gem_context_getparam_ioctl(struct drm_device
*dev
, void *data
,
3228 struct drm_file
*file_priv
);
3229 int i915_gem_context_setparam_ioctl(struct drm_device
*dev
, void *data
,
3230 struct drm_file
*file_priv
);
3232 /* i915_gem_evict.c */
3233 int __must_check
i915_gem_evict_something(struct drm_device
*dev
,
3234 struct i915_address_space
*vm
,
3237 unsigned cache_level
,
3238 unsigned long start
,
3241 int __must_check
i915_gem_evict_for_vma(struct i915_vma
*target
);
3242 int i915_gem_evict_vm(struct i915_address_space
*vm
, bool do_idle
);
3244 /* belongs in i915_gem_gtt.h */
3245 static inline void i915_gem_chipset_flush(struct drm_device
*dev
)
3247 if (INTEL_INFO(dev
)->gen
< 6)
3248 intel_gtt_chipset_flush();
3251 /* i915_gem_stolen.c */
3252 int i915_gem_stolen_insert_node(struct drm_i915_private
*dev_priv
,
3253 struct drm_mm_node
*node
, u64 size
,
3254 unsigned alignment
);
3255 int i915_gem_stolen_insert_node_in_range(struct drm_i915_private
*dev_priv
,
3256 struct drm_mm_node
*node
, u64 size
,
3257 unsigned alignment
, u64 start
,
3259 void i915_gem_stolen_remove_node(struct drm_i915_private
*dev_priv
,
3260 struct drm_mm_node
*node
);
3261 int i915_gem_init_stolen(struct drm_device
*dev
);
3262 void i915_gem_cleanup_stolen(struct drm_device
*dev
);
3263 struct drm_i915_gem_object
*
3264 i915_gem_object_create_stolen(struct drm_device
*dev
, u32 size
);
3265 struct drm_i915_gem_object
*
3266 i915_gem_object_create_stolen_for_preallocated(struct drm_device
*dev
,
3271 /* i915_gem_shrinker.c */
3272 unsigned long i915_gem_shrink(struct drm_i915_private
*dev_priv
,
3273 unsigned long target
,
3275 #define I915_SHRINK_PURGEABLE 0x1
3276 #define I915_SHRINK_UNBOUND 0x2
3277 #define I915_SHRINK_BOUND 0x4
3278 #define I915_SHRINK_ACTIVE 0x8
3279 unsigned long i915_gem_shrink_all(struct drm_i915_private
*dev_priv
);
3280 void i915_gem_shrinker_init(struct drm_i915_private
*dev_priv
);
3281 void i915_gem_shrinker_cleanup(struct drm_i915_private
*dev_priv
);
3284 /* i915_gem_tiling.c */
3285 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object
*obj
)
3287 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
3289 return dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_9_10_17
&&
3290 obj
->tiling_mode
!= I915_TILING_NONE
;
3293 /* i915_gem_debug.c */
3295 int i915_verify_lists(struct drm_device
*dev
);
3297 #define i915_verify_lists(dev) 0
3300 /* i915_debugfs.c */
3301 int i915_debugfs_init(struct drm_minor
*minor
);
3302 void i915_debugfs_cleanup(struct drm_minor
*minor
);
3303 #ifdef CONFIG_DEBUG_FS
3304 int i915_debugfs_connector_add(struct drm_connector
*connector
);
3305 void intel_display_crc_init(struct drm_device
*dev
);
3307 static inline int i915_debugfs_connector_add(struct drm_connector
*connector
)
3309 static inline void intel_display_crc_init(struct drm_device
*dev
) {}
3312 /* i915_gpu_error.c */
3314 void i915_error_printf(struct drm_i915_error_state_buf
*e
, const char *f
, ...);
3315 int i915_error_state_to_str(struct drm_i915_error_state_buf
*estr
,
3316 const struct i915_error_state_file_priv
*error
);
3317 int i915_error_state_buf_init(struct drm_i915_error_state_buf
*eb
,
3318 struct drm_i915_private
*i915
,
3319 size_t count
, loff_t pos
);
3320 static inline void i915_error_state_buf_release(
3321 struct drm_i915_error_state_buf
*eb
)
3325 void i915_capture_error_state(struct drm_device
*dev
, bool wedge
,
3326 const char *error_msg
);
3327 void i915_error_state_get(struct drm_device
*dev
,
3328 struct i915_error_state_file_priv
*error_priv
);
3329 void i915_error_state_put(struct i915_error_state_file_priv
*error_priv
);
3330 void i915_destroy_error_state(struct drm_device
*dev
);
3332 void i915_get_extra_instdone(struct drm_device
*dev
, uint32_t *instdone
);
3333 const char *i915_cache_level_str(struct drm_i915_private
*i915
, int type
);
3335 /* i915_cmd_parser.c */
3336 int i915_cmd_parser_get_version(void);
3337 int i915_cmd_parser_init_ring(struct intel_engine_cs
*ring
);
3338 void i915_cmd_parser_fini_ring(struct intel_engine_cs
*ring
);
3339 bool i915_needs_cmd_parser(struct intel_engine_cs
*ring
);
3340 int i915_parse_cmds(struct intel_engine_cs
*ring
,
3341 struct drm_i915_gem_object
*batch_obj
,
3342 struct drm_i915_gem_object
*shadow_batch_obj
,
3343 u32 batch_start_offset
,
3347 /* i915_suspend.c */
3348 extern int i915_save_state(struct drm_device
*dev
);
3349 extern int i915_restore_state(struct drm_device
*dev
);
3352 void i915_setup_sysfs(struct drm_device
*dev_priv
);
3353 void i915_teardown_sysfs(struct drm_device
*dev_priv
);
3356 extern int intel_setup_gmbus(struct drm_device
*dev
);
3357 extern void intel_teardown_gmbus(struct drm_device
*dev
);
3358 extern bool intel_gmbus_is_valid_pin(struct drm_i915_private
*dev_priv
,
3361 extern struct i2c_adapter
*
3362 intel_gmbus_get_adapter(struct drm_i915_private
*dev_priv
, unsigned int pin
);
3363 extern void intel_gmbus_set_speed(struct i2c_adapter
*adapter
, int speed
);
3364 extern void intel_gmbus_force_bit(struct i2c_adapter
*adapter
, bool force_bit
);
3365 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter
*adapter
)
3367 return container_of(adapter
, struct intel_gmbus
, adapter
)->force_bit
;
3369 extern void intel_i2c_reset(struct drm_device
*dev
);
3372 int intel_bios_init(struct drm_i915_private
*dev_priv
);
3373 bool intel_bios_is_valid_vbt(const void *buf
, size_t size
);
3375 /* intel_opregion.c */
3377 extern int intel_opregion_setup(struct drm_device
*dev
);
3378 extern void intel_opregion_init(struct drm_device
*dev
);
3379 extern void intel_opregion_fini(struct drm_device
*dev
);
3380 extern void intel_opregion_asle_intr(struct drm_device
*dev
);
3381 extern int intel_opregion_notify_encoder(struct intel_encoder
*intel_encoder
,
3383 extern int intel_opregion_notify_adapter(struct drm_device
*dev
,
3386 static inline int intel_opregion_setup(struct drm_device
*dev
) { return 0; }
3387 static inline void intel_opregion_init(struct drm_device
*dev
) { return; }
3388 static inline void intel_opregion_fini(struct drm_device
*dev
) { return; }
3389 static inline void intel_opregion_asle_intr(struct drm_device
*dev
) { return; }
3391 intel_opregion_notify_encoder(struct intel_encoder
*intel_encoder
, bool enable
)
3396 intel_opregion_notify_adapter(struct drm_device
*dev
, pci_power_t state
)
3404 extern void intel_register_dsm_handler(void);
3405 extern void intel_unregister_dsm_handler(void);
3407 static inline void intel_register_dsm_handler(void) { return; }
3408 static inline void intel_unregister_dsm_handler(void) { return; }
3409 #endif /* CONFIG_ACPI */
3412 extern void intel_modeset_init_hw(struct drm_device
*dev
);
3413 extern void intel_modeset_init(struct drm_device
*dev
);
3414 extern void intel_modeset_gem_init(struct drm_device
*dev
);
3415 extern void intel_modeset_cleanup(struct drm_device
*dev
);
3416 extern void intel_connector_unregister(struct intel_connector
*);
3417 extern int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
);
3418 extern void intel_display_resume(struct drm_device
*dev
);
3419 extern void i915_redisable_vga(struct drm_device
*dev
);
3420 extern void i915_redisable_vga_power_on(struct drm_device
*dev
);
3421 extern bool ironlake_set_drps(struct drm_device
*dev
, u8 val
);
3422 extern void intel_init_pch_refclk(struct drm_device
*dev
);
3423 extern void intel_set_rps(struct drm_device
*dev
, u8 val
);
3424 extern void intel_set_memory_cxsr(struct drm_i915_private
*dev_priv
,
3426 extern void intel_detect_pch(struct drm_device
*dev
);
3427 extern int intel_enable_rc6(const struct drm_device
*dev
);
3429 extern bool i915_semaphore_is_enabled(struct drm_device
*dev
);
3430 int i915_reg_read_ioctl(struct drm_device
*dev
, void *data
,
3431 struct drm_file
*file
);
3432 int i915_get_reset_stats_ioctl(struct drm_device
*dev
, void *data
,
3433 struct drm_file
*file
);
3436 extern struct intel_overlay_error_state
*intel_overlay_capture_error_state(struct drm_device
*dev
);
3437 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf
*e
,
3438 struct intel_overlay_error_state
*error
);
3440 extern struct intel_display_error_state
*intel_display_capture_error_state(struct drm_device
*dev
);
3441 extern void intel_display_print_error_state(struct drm_i915_error_state_buf
*e
,
3442 struct drm_device
*dev
,
3443 struct intel_display_error_state
*error
);
3445 int sandybridge_pcode_read(struct drm_i915_private
*dev_priv
, u32 mbox
, u32
*val
);
3446 int sandybridge_pcode_write(struct drm_i915_private
*dev_priv
, u32 mbox
, u32 val
);
3448 /* intel_sideband.c */
3449 u32
vlv_punit_read(struct drm_i915_private
*dev_priv
, u32 addr
);
3450 void vlv_punit_write(struct drm_i915_private
*dev_priv
, u32 addr
, u32 val
);
3451 u32
vlv_nc_read(struct drm_i915_private
*dev_priv
, u8 addr
);
3452 u32
vlv_gpio_nc_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3453 void vlv_gpio_nc_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3454 u32
vlv_cck_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3455 void vlv_cck_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3456 u32
vlv_ccu_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3457 void vlv_ccu_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3458 u32
vlv_bunit_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3459 void vlv_bunit_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3460 u32
vlv_gps_core_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3461 void vlv_gps_core_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3462 u32
vlv_dpio_read(struct drm_i915_private
*dev_priv
, enum pipe pipe
, int reg
);
3463 void vlv_dpio_write(struct drm_i915_private
*dev_priv
, enum pipe pipe
, int reg
, u32 val
);
3464 u32
intel_sbi_read(struct drm_i915_private
*dev_priv
, u16 reg
,
3465 enum intel_sbi_destination destination
);
3466 void intel_sbi_write(struct drm_i915_private
*dev_priv
, u16 reg
, u32 value
,
3467 enum intel_sbi_destination destination
);
3468 u32
vlv_flisdsi_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3469 void vlv_flisdsi_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3471 int intel_gpu_freq(struct drm_i915_private
*dev_priv
, int val
);
3472 int intel_freq_opcode(struct drm_i915_private
*dev_priv
, int val
);
3474 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3475 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3477 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3478 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3479 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3480 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
3482 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3483 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3484 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3485 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3487 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
3488 * will be implemented using 2 32-bit writes in an arbitrary order with
3489 * an arbitrary delay between them. This can cause the hardware to
3490 * act upon the intermediate value, possibly leading to corruption and
3491 * machine death. You have been warned.
3493 #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
3494 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3496 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
3497 u32 upper, lower, old_upper, loop = 0; \
3498 upper = I915_READ(upper_reg); \
3500 old_upper = upper; \
3501 lower = I915_READ(lower_reg); \
3502 upper = I915_READ(upper_reg); \
3503 } while (upper != old_upper && loop++ < 2); \
3504 (u64)upper << 32 | lower; })
3506 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3507 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
3509 #define __raw_read(x, s) \
3510 static inline uint##x##_t __raw_i915_read##x(struct drm_i915_private *dev_priv, \
3513 return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
3516 #define __raw_write(x, s) \
3517 static inline void __raw_i915_write##x(struct drm_i915_private *dev_priv, \
3518 i915_reg_t reg, uint##x##_t val) \
3520 write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
3535 /* These are untraced mmio-accessors that are only valid to be used inside
3536 * criticial sections inside IRQ handlers where forcewake is explicitly
3538 * Think twice, and think again, before using these.
3539 * Note: Should only be used between intel_uncore_forcewake_irqlock() and
3540 * intel_uncore_forcewake_irqunlock().
3542 #define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
3543 #define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
3544 #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
3546 /* "Broadcast RGB" property */
3547 #define INTEL_BROADCAST_RGB_AUTO 0
3548 #define INTEL_BROADCAST_RGB_FULL 1
3549 #define INTEL_BROADCAST_RGB_LIMITED 2
3551 static inline i915_reg_t
i915_vgacntrl_reg(struct drm_device
*dev
)
3553 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
))
3554 return VLV_VGACNTRL
;
3555 else if (INTEL_INFO(dev
)->gen
>= 5)
3556 return CPU_VGACNTRL
;
3561 static inline void __user
*to_user_ptr(u64 address
)
3563 return (void __user
*)(uintptr_t)address
;
3566 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m
)
3568 unsigned long j
= msecs_to_jiffies(m
);
3570 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);
3573 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n
)
3575 return min_t(u64
, MAX_JIFFY_OFFSET
, nsecs_to_jiffies64(n
) + 1);
3578 static inline unsigned long
3579 timespec_to_jiffies_timeout(const struct timespec
*value
)
3581 unsigned long j
= timespec_to_jiffies(value
);
3583 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);
3587 * If you need to wait X milliseconds between events A and B, but event B
3588 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
3589 * when event A happened, then just before event B you call this function and
3590 * pass the timestamp as the first argument, and X as the second argument.
3593 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies
, int to_wait_ms
)
3595 unsigned long target_jiffies
, tmp_jiffies
, remaining_jiffies
;
3598 * Don't re-read the value of "jiffies" every time since it may change
3599 * behind our back and break the math.
3601 tmp_jiffies
= jiffies
;
3602 target_jiffies
= timestamp_jiffies
+
3603 msecs_to_jiffies_timeout(to_wait_ms
);
3605 if (time_after(target_jiffies
, tmp_jiffies
)) {
3606 remaining_jiffies
= target_jiffies
- tmp_jiffies
;
3607 while (remaining_jiffies
)
3609 schedule_timeout_uninterruptible(remaining_jiffies
);
3613 static inline void i915_trace_irq_get(struct intel_engine_cs
*ring
,
3614 struct drm_i915_gem_request
*req
)
3616 if (ring
->trace_irq_req
== NULL
&& ring
->irq_get(ring
))
3617 i915_gem_request_assign(&ring
->trace_irq_req
, req
);