1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
34 #include <uapi/drm/drm_fourcc.h>
36 #include <linux/io-mapping.h>
37 #include <linux/i2c.h>
38 #include <linux/i2c-algo-bit.h>
39 #include <linux/backlight.h>
40 #include <linux/hashtable.h>
41 #include <linux/intel-iommu.h>
42 #include <linux/kref.h>
43 #include <linux/pm_qos.h>
44 #include <linux/shmem_fs.h>
47 #include <drm/intel-gtt.h>
48 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
49 #include <drm/drm_gem.h>
50 #include <drm/drm_auth.h>
52 #include "i915_params.h"
55 #include "intel_bios.h"
56 #include "intel_dpll_mgr.h"
57 #include "intel_guc.h"
58 #include "intel_lrc.h"
59 #include "intel_ringbuffer.h"
62 #include "i915_gem_gtt.h"
63 #include "i915_gem_render_state.h"
64 #include "i915_gem_request.h"
66 #include "intel_gvt.h"
68 /* General customization:
71 #define DRIVER_NAME "i915"
72 #define DRIVER_DESC "Intel Graphics"
73 #define DRIVER_DATE "20160808"
76 /* Many gcc seem to no see through this and fall over :( */
78 #define WARN_ON(x) ({ \
79 bool __i915_warn_cond = (x); \
80 if (__builtin_constant_p(__i915_warn_cond)) \
81 BUILD_BUG_ON(__i915_warn_cond); \
82 WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
84 #define WARN_ON(x) WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
88 #define WARN_ON_ONCE(x) WARN_ONCE((x), "%s", "WARN_ON_ONCE(" __stringify(x) ")")
90 #define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
91 (long) (x), __func__);
93 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
94 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
95 * which may not necessarily be a user visible problem. This will either
96 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
97 * enable distros and users to tailor their preferred amount of i915 abrt
100 #define I915_STATE_WARN(condition, format...) ({ \
101 int __ret_warn_on = !!(condition); \
102 if (unlikely(__ret_warn_on)) \
103 if (!WARN(i915.verbose_state_checks, format)) \
105 unlikely(__ret_warn_on); \
108 #define I915_STATE_WARN_ON(x) \
109 I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
111 bool __i915_inject_load_failure(const char *func
, int line
);
112 #define i915_inject_load_failure() \
113 __i915_inject_load_failure(__func__, __LINE__)
115 static inline const char *yesno(bool v
)
117 return v
? "yes" : "no";
120 static inline const char *onoff(bool v
)
122 return v
? "on" : "off";
131 I915_MAX_PIPES
= _PIPE_EDP
133 #define pipe_name(p) ((p) + 'A')
145 static inline const char *transcoder_name(enum transcoder transcoder
)
147 switch (transcoder
) {
156 case TRANSCODER_DSI_A
:
158 case TRANSCODER_DSI_C
:
165 static inline bool transcoder_is_dsi(enum transcoder transcoder
)
167 return transcoder
== TRANSCODER_DSI_A
|| transcoder
== TRANSCODER_DSI_C
;
171 * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
172 * number of planes per CRTC. Not all platforms really have this many planes,
173 * which means some arrays of size I915_MAX_PLANES may have unused entries
174 * between the topmost sprite plane and the cursor plane.
183 #define plane_name(p) ((p) + 'A')
185 #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
195 #define port_name(p) ((p) + 'A')
197 #define I915_NUM_PHYS_VLV 2
209 enum intel_display_power_domain
{
213 POWER_DOMAIN_PIPE_A_PANEL_FITTER
,
214 POWER_DOMAIN_PIPE_B_PANEL_FITTER
,
215 POWER_DOMAIN_PIPE_C_PANEL_FITTER
,
216 POWER_DOMAIN_TRANSCODER_A
,
217 POWER_DOMAIN_TRANSCODER_B
,
218 POWER_DOMAIN_TRANSCODER_C
,
219 POWER_DOMAIN_TRANSCODER_EDP
,
220 POWER_DOMAIN_TRANSCODER_DSI_A
,
221 POWER_DOMAIN_TRANSCODER_DSI_C
,
222 POWER_DOMAIN_PORT_DDI_A_LANES
,
223 POWER_DOMAIN_PORT_DDI_B_LANES
,
224 POWER_DOMAIN_PORT_DDI_C_LANES
,
225 POWER_DOMAIN_PORT_DDI_D_LANES
,
226 POWER_DOMAIN_PORT_DDI_E_LANES
,
227 POWER_DOMAIN_PORT_DSI
,
228 POWER_DOMAIN_PORT_CRT
,
229 POWER_DOMAIN_PORT_OTHER
,
238 POWER_DOMAIN_MODESET
,
244 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
245 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
246 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
247 #define POWER_DOMAIN_TRANSCODER(tran) \
248 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
249 (tran) + POWER_DOMAIN_TRANSCODER_A)
253 HPD_TV
= HPD_NONE
, /* TV is known to be unreliable */
265 #define for_each_hpd_pin(__pin) \
266 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
268 struct i915_hotplug
{
269 struct work_struct hotplug_work
;
272 unsigned long last_jiffies
;
277 HPD_MARK_DISABLED
= 2
279 } stats
[HPD_NUM_PINS
];
281 struct delayed_work reenable_work
;
283 struct intel_digital_port
*irq_port
[I915_MAX_PORTS
];
286 struct work_struct dig_port_work
;
288 struct work_struct poll_init_work
;
292 * if we get a HPD irq from DP and a HPD irq from non-DP
293 * the non-DP HPD could block the workqueue on a mode config
294 * mutex getting, that userspace may have taken. However
295 * userspace is waiting on the DP workqueue to run which is
296 * blocked behind the non-DP one.
298 struct workqueue_struct
*dp_wq
;
301 #define I915_GEM_GPU_DOMAINS \
302 (I915_GEM_DOMAIN_RENDER | \
303 I915_GEM_DOMAIN_SAMPLER | \
304 I915_GEM_DOMAIN_COMMAND | \
305 I915_GEM_DOMAIN_INSTRUCTION | \
306 I915_GEM_DOMAIN_VERTEX)
308 #define for_each_pipe(__dev_priv, __p) \
309 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
310 #define for_each_pipe_masked(__dev_priv, __p, __mask) \
311 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \
312 for_each_if ((__mask) & (1 << (__p)))
313 #define for_each_plane(__dev_priv, __pipe, __p) \
315 (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
317 #define for_each_sprite(__dev_priv, __p, __s) \
319 (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \
322 #define for_each_port_masked(__port, __ports_mask) \
323 for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) \
324 for_each_if ((__ports_mask) & (1 << (__port)))
326 #define for_each_crtc(dev, crtc) \
327 list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head)
329 #define for_each_intel_plane(dev, intel_plane) \
330 list_for_each_entry(intel_plane, \
331 &(dev)->mode_config.plane_list, \
334 #define for_each_intel_plane_mask(dev, intel_plane, plane_mask) \
335 list_for_each_entry(intel_plane, \
336 &(dev)->mode_config.plane_list, \
338 for_each_if ((plane_mask) & \
339 (1 << drm_plane_index(&intel_plane->base)))
341 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
342 list_for_each_entry(intel_plane, \
343 &(dev)->mode_config.plane_list, \
345 for_each_if ((intel_plane)->pipe == (intel_crtc)->pipe)
347 #define for_each_intel_crtc(dev, intel_crtc) \
348 list_for_each_entry(intel_crtc, \
349 &(dev)->mode_config.crtc_list, \
352 #define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask) \
353 list_for_each_entry(intel_crtc, \
354 &(dev)->mode_config.crtc_list, \
356 for_each_if ((crtc_mask) & (1 << drm_crtc_index(&intel_crtc->base)))
358 #define for_each_intel_encoder(dev, intel_encoder) \
359 list_for_each_entry(intel_encoder, \
360 &(dev)->mode_config.encoder_list, \
363 #define for_each_intel_connector(dev, intel_connector) \
364 list_for_each_entry(intel_connector, \
365 &(dev)->mode_config.connector_list, \
368 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
369 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
370 for_each_if ((intel_encoder)->base.crtc == (__crtc))
372 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
373 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
374 for_each_if ((intel_connector)->base.encoder == (__encoder))
376 #define for_each_power_domain(domain, mask) \
377 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
378 for_each_if ((1 << (domain)) & (mask))
380 struct drm_i915_private
;
381 struct i915_mm_struct
;
382 struct i915_mmu_object
;
384 struct drm_i915_file_private
{
385 struct drm_i915_private
*dev_priv
;
386 struct drm_file
*file
;
390 struct list_head request_list
;
391 /* 20ms is a fairly arbitrary limit (greater than the average frame time)
392 * chosen to prevent the CPU getting more than a frame ahead of the GPU
393 * (when using lax throttling for the frontbuffer). We also use it to
394 * offer free GPU waitboosts for severely congested workloads.
396 #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
398 struct idr context_idr
;
400 struct intel_rps_client
{
401 struct list_head link
;
405 unsigned int bsd_engine
;
408 /* Used by dp and fdi links */
409 struct intel_link_m_n
{
417 void intel_link_compute_m_n(int bpp
, int nlanes
,
418 int pixel_clock
, int link_clock
,
419 struct intel_link_m_n
*m_n
);
421 /* Interface history:
424 * 1.2: Add Power Management
425 * 1.3: Add vblank support
426 * 1.4: Fix cmdbuffer path, add heap destroy
427 * 1.5: Add vblank pipe configuration
428 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
429 * - Support vertical blank on secondary display pipe
431 #define DRIVER_MAJOR 1
432 #define DRIVER_MINOR 6
433 #define DRIVER_PATCHLEVEL 0
435 struct opregion_header
;
436 struct opregion_acpi
;
437 struct opregion_swsci
;
438 struct opregion_asle
;
440 struct intel_opregion
{
441 struct opregion_header
*header
;
442 struct opregion_acpi
*acpi
;
443 struct opregion_swsci
*swsci
;
444 u32 swsci_gbda_sub_functions
;
445 u32 swsci_sbcb_sub_functions
;
446 struct opregion_asle
*asle
;
451 struct work_struct asle_work
;
453 #define OPREGION_SIZE (8*1024)
455 struct intel_overlay
;
456 struct intel_overlay_error_state
;
458 #define I915_FENCE_REG_NONE -1
459 #define I915_MAX_NUM_FENCES 32
460 /* 32 fences + sign bit for FENCE_REG_NONE */
461 #define I915_MAX_NUM_FENCE_BITS 6
463 struct drm_i915_fence_reg
{
464 struct list_head lru_list
;
465 struct drm_i915_gem_object
*obj
;
469 struct sdvo_device_mapping
{
478 struct intel_connector
;
479 struct intel_encoder
;
480 struct intel_crtc_state
;
481 struct intel_initial_plane_config
;
486 struct drm_i915_display_funcs
{
487 int (*get_display_clock_speed
)(struct drm_device
*dev
);
488 int (*get_fifo_size
)(struct drm_device
*dev
, int plane
);
489 int (*compute_pipe_wm
)(struct intel_crtc_state
*cstate
);
490 int (*compute_intermediate_wm
)(struct drm_device
*dev
,
491 struct intel_crtc
*intel_crtc
,
492 struct intel_crtc_state
*newstate
);
493 void (*initial_watermarks
)(struct intel_crtc_state
*cstate
);
494 void (*optimize_watermarks
)(struct intel_crtc_state
*cstate
);
495 int (*compute_global_watermarks
)(struct drm_atomic_state
*state
);
496 void (*update_wm
)(struct drm_crtc
*crtc
);
497 int (*modeset_calc_cdclk
)(struct drm_atomic_state
*state
);
498 void (*modeset_commit_cdclk
)(struct drm_atomic_state
*state
);
499 /* Returns the active state of the crtc, and if the crtc is active,
500 * fills out the pipe-config with the hw state. */
501 bool (*get_pipe_config
)(struct intel_crtc
*,
502 struct intel_crtc_state
*);
503 void (*get_initial_plane_config
)(struct intel_crtc
*,
504 struct intel_initial_plane_config
*);
505 int (*crtc_compute_clock
)(struct intel_crtc
*crtc
,
506 struct intel_crtc_state
*crtc_state
);
507 void (*crtc_enable
)(struct drm_crtc
*crtc
);
508 void (*crtc_disable
)(struct drm_crtc
*crtc
);
509 void (*audio_codec_enable
)(struct drm_connector
*connector
,
510 struct intel_encoder
*encoder
,
511 const struct drm_display_mode
*adjusted_mode
);
512 void (*audio_codec_disable
)(struct intel_encoder
*encoder
);
513 void (*fdi_link_train
)(struct drm_crtc
*crtc
);
514 void (*init_clock_gating
)(struct drm_device
*dev
);
515 int (*queue_flip
)(struct drm_device
*dev
, struct drm_crtc
*crtc
,
516 struct drm_framebuffer
*fb
,
517 struct drm_i915_gem_object
*obj
,
518 struct drm_i915_gem_request
*req
,
520 void (*hpd_irq_setup
)(struct drm_i915_private
*dev_priv
);
521 /* clock updates for mode set */
523 /* render clock increase/decrease */
524 /* display clock increase/decrease */
525 /* pll clock increase/decrease */
527 void (*load_csc_matrix
)(struct drm_crtc_state
*crtc_state
);
528 void (*load_luts
)(struct drm_crtc_state
*crtc_state
);
531 enum forcewake_domain_id
{
532 FW_DOMAIN_ID_RENDER
= 0,
533 FW_DOMAIN_ID_BLITTER
,
539 enum forcewake_domains
{
540 FORCEWAKE_RENDER
= (1 << FW_DOMAIN_ID_RENDER
),
541 FORCEWAKE_BLITTER
= (1 << FW_DOMAIN_ID_BLITTER
),
542 FORCEWAKE_MEDIA
= (1 << FW_DOMAIN_ID_MEDIA
),
543 FORCEWAKE_ALL
= (FORCEWAKE_RENDER
|
548 #define FW_REG_READ (1)
549 #define FW_REG_WRITE (2)
551 enum forcewake_domains
552 intel_uncore_forcewake_for_reg(struct drm_i915_private
*dev_priv
,
553 i915_reg_t reg
, unsigned int op
);
555 struct intel_uncore_funcs
{
556 void (*force_wake_get
)(struct drm_i915_private
*dev_priv
,
557 enum forcewake_domains domains
);
558 void (*force_wake_put
)(struct drm_i915_private
*dev_priv
,
559 enum forcewake_domains domains
);
561 uint8_t (*mmio_readb
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
, bool trace
);
562 uint16_t (*mmio_readw
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
, bool trace
);
563 uint32_t (*mmio_readl
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
, bool trace
);
564 uint64_t (*mmio_readq
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
, bool trace
);
566 void (*mmio_writeb
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
,
567 uint8_t val
, bool trace
);
568 void (*mmio_writew
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
,
569 uint16_t val
, bool trace
);
570 void (*mmio_writel
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
,
571 uint32_t val
, bool trace
);
572 void (*mmio_writeq
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
,
573 uint64_t val
, bool trace
);
576 struct intel_uncore
{
577 spinlock_t lock
; /** lock is also taken in irq contexts. */
579 struct intel_uncore_funcs funcs
;
582 enum forcewake_domains fw_domains
;
584 struct intel_uncore_forcewake_domain
{
585 struct drm_i915_private
*i915
;
586 enum forcewake_domain_id id
;
587 enum forcewake_domains mask
;
589 struct hrtimer timer
;
596 } fw_domain
[FW_DOMAIN_ID_COUNT
];
598 int unclaimed_mmio_check
;
601 /* Iterate over initialised fw domains */
602 #define for_each_fw_domain_masked(domain__, mask__, dev_priv__) \
603 for ((domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
604 (domain__) < &(dev_priv__)->uncore.fw_domain[FW_DOMAIN_ID_COUNT]; \
606 for_each_if ((mask__) & (domain__)->mask)
608 #define for_each_fw_domain(domain__, dev_priv__) \
609 for_each_fw_domain_masked(domain__, FORCEWAKE_ALL, dev_priv__)
611 #define CSR_VERSION(major, minor) ((major) << 16 | (minor))
612 #define CSR_VERSION_MAJOR(version) ((version) >> 16)
613 #define CSR_VERSION_MINOR(version) ((version) & 0xffff)
616 struct work_struct work
;
618 uint32_t *dmc_payload
;
619 uint32_t dmc_fw_size
;
622 i915_reg_t mmioaddr
[8];
623 uint32_t mmiodata
[8];
625 uint32_t allowed_dc_mask
;
628 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
629 func(is_mobile) sep \
632 func(is_i945gm) sep \
634 func(need_gfx_hws) sep \
636 func(is_pineview) sep \
637 func(is_broadwater) sep \
638 func(is_crestline) sep \
639 func(is_ivybridge) sep \
640 func(is_valleyview) sep \
641 func(is_cherryview) sep \
642 func(is_haswell) sep \
643 func(is_broadwell) sep \
644 func(is_skylake) sep \
645 func(is_broxton) sep \
646 func(is_kabylake) sep \
647 func(is_preliminary) sep \
649 func(has_pipe_cxsr) sep \
650 func(has_hotplug) sep \
651 func(cursor_needs_physical) sep \
652 func(has_overlay) sep \
653 func(overlay_needs_physical) sep \
654 func(supports_tv) sep \
656 func(has_snoop) sep \
658 func(has_fpga_dbg) sep \
661 #define DEFINE_FLAG(name) u8 name:1
662 #define SEP_SEMICOLON ;
664 struct intel_device_info
{
665 u32 display_mmio_offset
;
668 u8 num_sprites
[I915_MAX_PIPES
];
671 u8 ring_mask
; /* Rings supported by the HW */
673 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG
, SEP_SEMICOLON
);
674 /* Register offsets for the various display pipes and transcoders */
675 int pipe_offsets
[I915_MAX_TRANSCODERS
];
676 int trans_offsets
[I915_MAX_TRANSCODERS
];
677 int palette_offsets
[I915_MAX_PIPES
];
678 int cursor_offsets
[I915_MAX_PIPES
];
680 /* Slice/subslice/EU info */
683 u8 subslice_per_slice
;
687 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
690 u8 has_subslice_pg
:1;
694 u16 degamma_lut_size
;
702 struct intel_display_error_state
;
704 struct drm_i915_error_state
{
713 struct intel_device_info device_info
;
715 /* Generic register state */
723 u32 error
; /* gen6+ */
724 u32 err_int
; /* gen7 */
725 u32 fault_data0
; /* gen8, gen9 */
726 u32 fault_data1
; /* gen8, gen9 */
732 u32 extra_instdone
[I915_NUM_INSTDONE_REG
];
733 u64 fence
[I915_MAX_NUM_FENCES
];
734 struct intel_overlay_error_state
*overlay
;
735 struct intel_display_error_state
*display
;
736 struct drm_i915_error_object
*semaphore
;
738 struct drm_i915_error_engine
{
740 /* Software tracked state */
744 enum intel_engine_hangcheck_action hangcheck_action
;
745 struct i915_address_space
*vm
;
748 /* our own tracking of ring head and tail */
753 u32 semaphore_seqno
[I915_NUM_ENGINES
- 1];
772 u32 rc_psmi
; /* sleep state */
773 u32 semaphore_mboxes
[I915_NUM_ENGINES
- 1];
775 struct drm_i915_error_object
{
779 } *ringbuffer
, *batchbuffer
, *wa_batchbuffer
, *ctx
, *hws_page
;
781 struct drm_i915_error_object
*wa_ctx
;
783 struct drm_i915_error_request
{
791 struct drm_i915_error_waiter
{
792 char comm
[TASK_COMM_LEN
];
806 char comm
[TASK_COMM_LEN
];
807 } engine
[I915_NUM_ENGINES
];
809 struct drm_i915_error_buffer
{
812 u32 rseqno
[I915_NUM_ENGINES
], wseqno
;
816 s32 fence_reg
:I915_MAX_NUM_FENCE_BITS
;
823 } *active_bo
[I915_NUM_ENGINES
], *pinned_bo
;
824 u32 active_bo_count
[I915_NUM_ENGINES
], pinned_bo_count
;
825 struct i915_address_space
*active_vm
[I915_NUM_ENGINES
];
828 enum i915_cache_level
{
830 I915_CACHE_LLC
, /* also used for snoopable memory on non-LLC */
831 I915_CACHE_L3_LLC
, /* gen7+, L3 sits between the domain specifc
832 caches, eg sampler/render caches, and the
833 large Last-Level-Cache. LLC is coherent with
834 the CPU, but L3 is only visible to the GPU. */
835 I915_CACHE_WT
, /* hsw:gt3e WriteThrough for scanouts */
838 struct i915_ctx_hang_stats
{
839 /* This context had batch pending when hang was declared */
840 unsigned batch_pending
;
842 /* This context had batch active when hang was declared */
843 unsigned batch_active
;
845 /* Time when this context was last blamed for a GPU reset */
846 unsigned long guilty_ts
;
848 /* If the contexts causes a second GPU hang within this time,
849 * it is permanently banned from submitting any more work.
851 unsigned long ban_period_seconds
;
853 /* This context is banned to submit more work */
857 /* This must match up with the value previously used for execbuf2.rsvd1. */
858 #define DEFAULT_CONTEXT_HANDLE 0
861 * struct i915_gem_context - as the name implies, represents a context.
862 * @ref: reference count.
863 * @user_handle: userspace tracking identity for this context.
864 * @remap_slice: l3 row remapping information.
865 * @flags: context specific flags:
866 * CONTEXT_NO_ZEROMAP: do not allow mapping things to page 0.
867 * @file_priv: filp associated with this context (NULL for global default
869 * @hang_stats: information about the role of this context in possible GPU
871 * @ppgtt: virtual memory space used by this context.
872 * @legacy_hw_ctx: render context backing object and whether it is correctly
873 * initialized (legacy ring submission mechanism only).
874 * @link: link in the global list of contexts.
876 * Contexts are memory images used by the hardware to store copies of their
879 struct i915_gem_context
{
881 struct drm_i915_private
*i915
;
882 struct drm_i915_file_private
*file_priv
;
883 struct i915_hw_ppgtt
*ppgtt
;
886 struct i915_ctx_hang_stats hang_stats
;
888 /* Unique identifier for this context, used by the hw for tracking */
890 #define CONTEXT_NO_ZEROMAP BIT(0)
891 #define CONTEXT_NO_ERROR_CAPTURE BIT(1)
897 struct intel_context
{
898 struct i915_vma
*state
;
899 struct intel_ring
*ring
;
900 uint32_t *lrc_reg_state
;
904 } engine
[I915_NUM_ENGINES
];
907 struct atomic_notifier_head status_notifier
;
908 bool execlists_force_single_submission
;
910 struct list_head link
;
925 /* This is always the inner lock when overlapping with struct_mutex and
926 * it's the outer lock when overlapping with stolen_lock. */
929 unsigned int possible_framebuffer_bits
;
930 unsigned int busy_bits
;
931 unsigned int visible_pipes_mask
;
932 struct intel_crtc
*crtc
;
934 struct drm_mm_node compressed_fb
;
935 struct drm_mm_node
*compressed_llb
;
942 struct intel_fbc_state_cache
{
944 unsigned int mode_flags
;
945 uint32_t hsw_bdw_pixel_rate
;
949 unsigned int rotation
;
957 uint32_t pixel_format
;
960 unsigned int tiling_mode
;
964 struct intel_fbc_reg_params
{
968 unsigned int fence_y_offset
;
973 uint32_t pixel_format
;
981 struct intel_fbc_work
{
983 u32 scheduled_vblank
;
984 struct work_struct work
;
987 const char *no_fbc_reason
;
991 * HIGH_RR is the highest eDP panel refresh rate read from EDID
992 * LOW_RR is the lowest eDP panel refresh rate found from EDID
993 * parsing for same resolution.
995 enum drrs_refresh_rate_type
{
998 DRRS_MAX_RR
, /* RR count */
1001 enum drrs_support_type
{
1002 DRRS_NOT_SUPPORTED
= 0,
1003 STATIC_DRRS_SUPPORT
= 1,
1004 SEAMLESS_DRRS_SUPPORT
= 2
1010 struct delayed_work work
;
1011 struct intel_dp
*dp
;
1012 unsigned busy_frontbuffer_bits
;
1013 enum drrs_refresh_rate_type refresh_rate_type
;
1014 enum drrs_support_type type
;
1021 struct intel_dp
*enabled
;
1023 struct delayed_work work
;
1024 unsigned busy_frontbuffer_bits
;
1026 bool aux_frame_sync
;
1031 PCH_NONE
= 0, /* No PCH present */
1032 PCH_IBX
, /* Ibexpeak PCH */
1033 PCH_CPT
, /* Cougarpoint PCH */
1034 PCH_LPT
, /* Lynxpoint PCH */
1035 PCH_SPT
, /* Sunrisepoint PCH */
1036 PCH_KBP
, /* Kabypoint PCH */
1040 enum intel_sbi_destination
{
1045 #define QUIRK_PIPEA_FORCE (1<<0)
1046 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
1047 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
1048 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
1049 #define QUIRK_PIPEB_FORCE (1<<4)
1050 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
1053 struct intel_fbc_work
;
1055 struct intel_gmbus
{
1056 struct i2c_adapter adapter
;
1057 #define GMBUS_FORCE_BIT_RETRY (1U << 31)
1060 i915_reg_t gpio_reg
;
1061 struct i2c_algo_bit_data bit_algo
;
1062 struct drm_i915_private
*dev_priv
;
1065 struct i915_suspend_saved_registers
{
1067 u32 saveFBC_CONTROL
;
1068 u32 saveCACHE_MODE_0
;
1069 u32 saveMI_ARB_STATE
;
1073 uint64_t saveFENCE
[I915_MAX_NUM_FENCES
];
1074 u32 savePCH_PORT_HOTPLUG
;
1078 struct vlv_s0ix_state
{
1085 u32 lra_limits
[GEN7_LRA_LIMITS_REG_NUM
];
1086 u32 media_max_req_count
;
1087 u32 gfx_max_req_count
;
1113 u32 rp_down_timeout
;
1119 /* Display 1 CZ domain */
1124 u32 gt_scratch
[GEN7_GT_SCRATCH_REG_NUM
];
1126 /* GT SA CZ domain */
1133 /* Display 2 CZ domain */
1137 u32 clock_gate_dis2
;
1140 struct intel_rps_ei
{
1146 struct intel_gen6_power_mgmt
{
1148 * work, interrupts_enabled and pm_iir are protected by
1149 * dev_priv->irq_lock
1151 struct work_struct work
;
1152 bool interrupts_enabled
;
1157 /* Frequencies are stored in potentially platform dependent multiples.
1158 * In other words, *_freq needs to be multiplied by X to be interesting.
1159 * Soft limits are those which are used for the dynamic reclocking done
1160 * by the driver (raise frequencies under heavy loads, and lower for
1161 * lighter loads). Hard limits are those imposed by the hardware.
1163 * A distinction is made for overclocking, which is never enabled by
1164 * default, and is considered to be above the hard limit if it's
1167 u8 cur_freq
; /* Current frequency (cached, may not == HW) */
1168 u8 min_freq_softlimit
; /* Minimum frequency permitted by the driver */
1169 u8 max_freq_softlimit
; /* Max frequency permitted by the driver */
1170 u8 max_freq
; /* Maximum frequency, RP0 if not overclocking */
1171 u8 min_freq
; /* AKA RPn. Minimum frequency */
1172 u8 boost_freq
; /* Frequency to request when wait boosting */
1173 u8 idle_freq
; /* Frequency to request when we are idle */
1174 u8 efficient_freq
; /* AKA RPe. Pre-determined balanced frequency */
1175 u8 rp1_freq
; /* "less than" RP0 power/freqency */
1176 u8 rp0_freq
; /* Non-overclocked max frequency. */
1177 u16 gpll_ref_freq
; /* vlv/chv GPLL reference frequency */
1179 u8 up_threshold
; /* Current %busy required to uplock */
1180 u8 down_threshold
; /* Current %busy required to downclock */
1183 enum { LOW_POWER
, BETWEEN
, HIGH_POWER
} power
;
1185 spinlock_t client_lock
;
1186 struct list_head clients
;
1190 struct delayed_work autoenable_work
;
1193 /* manual wa residency calculations */
1194 struct intel_rps_ei up_ei
, down_ei
;
1197 * Protects RPS/RC6 register access and PCU communication.
1198 * Must be taken after struct_mutex if nested. Note that
1199 * this lock may be held for long periods of time when
1200 * talking to hw - so only take it when talking to hw!
1202 struct mutex hw_lock
;
1205 /* defined intel_pm.c */
1206 extern spinlock_t mchdev_lock
;
1208 struct intel_ilk_power_mgmt
{
1216 unsigned long last_time1
;
1217 unsigned long chipset_power
;
1220 unsigned long gfx_power
;
1227 struct drm_i915_private
;
1228 struct i915_power_well
;
1230 struct i915_power_well_ops
{
1232 * Synchronize the well's hw state to match the current sw state, for
1233 * example enable/disable it based on the current refcount. Called
1234 * during driver init and resume time, possibly after first calling
1235 * the enable/disable handlers.
1237 void (*sync_hw
)(struct drm_i915_private
*dev_priv
,
1238 struct i915_power_well
*power_well
);
1240 * Enable the well and resources that depend on it (for example
1241 * interrupts located on the well). Called after the 0->1 refcount
1244 void (*enable
)(struct drm_i915_private
*dev_priv
,
1245 struct i915_power_well
*power_well
);
1247 * Disable the well and resources that depend on it. Called after
1248 * the 1->0 refcount transition.
1250 void (*disable
)(struct drm_i915_private
*dev_priv
,
1251 struct i915_power_well
*power_well
);
1252 /* Returns the hw enabled state. */
1253 bool (*is_enabled
)(struct drm_i915_private
*dev_priv
,
1254 struct i915_power_well
*power_well
);
1257 /* Power well structure for haswell */
1258 struct i915_power_well
{
1261 /* power well enable/disable usage count */
1263 /* cached hw enabled state */
1265 unsigned long domains
;
1267 const struct i915_power_well_ops
*ops
;
1270 struct i915_power_domains
{
1272 * Power wells needed for initialization at driver init and suspend
1273 * time are on. They are kept on until after the first modeset.
1277 int power_well_count
;
1280 int domain_use_count
[POWER_DOMAIN_NUM
];
1281 struct i915_power_well
*power_wells
;
1284 #define MAX_L3_SLICES 2
1285 struct intel_l3_parity
{
1286 u32
*remap_info
[MAX_L3_SLICES
];
1287 struct work_struct error_work
;
1291 struct i915_gem_mm
{
1292 /** Memory allocator for GTT stolen memory */
1293 struct drm_mm stolen
;
1294 /** Protects the usage of the GTT stolen memory allocator. This is
1295 * always the inner lock when overlapping with struct_mutex. */
1296 struct mutex stolen_lock
;
1298 /** List of all objects in gtt_space. Used to restore gtt
1299 * mappings on resume */
1300 struct list_head bound_list
;
1302 * List of objects which are not bound to the GTT (thus
1303 * are idle and not used by the GPU) but still have
1304 * (presumably uncached) pages still attached.
1306 struct list_head unbound_list
;
1308 /** Usable portion of the GTT for GEM */
1309 unsigned long stolen_base
; /* limited to low memory (32-bit) */
1311 /** PPGTT used for aliasing the PPGTT with the GTT */
1312 struct i915_hw_ppgtt
*aliasing_ppgtt
;
1314 struct notifier_block oom_notifier
;
1315 struct notifier_block vmap_notifier
;
1316 struct shrinker shrinker
;
1318 /** LRU list of objects with fence regs on them. */
1319 struct list_head fence_list
;
1322 * Are we in a non-interruptible section of code like
1327 /* the indicator for dispatch video commands on two BSD rings */
1328 unsigned int bsd_engine_dispatch_index
;
1330 /** Bit 6 swizzling required for X tiling */
1331 uint32_t bit_6_swizzle_x
;
1332 /** Bit 6 swizzling required for Y tiling */
1333 uint32_t bit_6_swizzle_y
;
1335 /* accounting, useful for userland debugging */
1336 spinlock_t object_stat_lock
;
1337 size_t object_memory
;
1341 struct drm_i915_error_state_buf
{
1342 struct drm_i915_private
*i915
;
1351 struct i915_error_state_file_priv
{
1352 struct drm_device
*dev
;
1353 struct drm_i915_error_state
*error
;
1356 struct i915_gpu_error
{
1357 /* For hangcheck timer */
1358 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1359 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1360 /* Hang gpu twice in this window and your context gets banned */
1361 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1363 struct delayed_work hangcheck_work
;
1365 /* For reset and error_state handling. */
1367 /* Protected by the above dev->gpu_error.lock. */
1368 struct drm_i915_error_state
*first_error
;
1370 unsigned long missed_irq_rings
;
1373 * State variable controlling the reset flow and count
1375 * This is a counter which gets incremented when reset is triggered,
1376 * and again when reset has been handled. So odd values (lowest bit set)
1377 * means that reset is in progress and even values that
1378 * (reset_counter >> 1):th reset was successfully completed.
1380 * If reset is not completed succesfully, the I915_WEDGE bit is
1381 * set meaning that hardware is terminally sour and there is no
1382 * recovery. All waiters on the reset_queue will be woken when
1385 * This counter is used by the wait_seqno code to notice that reset
1386 * event happened and it needs to restart the entire ioctl (since most
1387 * likely the seqno it waited for won't ever signal anytime soon).
1389 * This is important for lock-free wait paths, where no contended lock
1390 * naturally enforces the correct ordering between the bail-out of the
1391 * waiter and the gpu reset work code.
1393 atomic_t reset_counter
;
1395 #define I915_RESET_IN_PROGRESS_FLAG 1
1396 #define I915_WEDGED (1 << 31)
1399 * Waitqueue to signal when a hang is detected. Used to for waiters
1400 * to release the struct_mutex for the reset to procede.
1402 wait_queue_head_t wait_queue
;
1405 * Waitqueue to signal when the reset has completed. Used by clients
1406 * that wait for dev_priv->mm.wedged to settle.
1408 wait_queue_head_t reset_queue
;
1410 /* For missed irq/seqno simulation. */
1411 unsigned long test_irq_rings
;
1414 enum modeset_restore
{
1415 MODESET_ON_LID_OPEN
,
1420 #define DP_AUX_A 0x40
1421 #define DP_AUX_B 0x10
1422 #define DP_AUX_C 0x20
1423 #define DP_AUX_D 0x30
1425 #define DDC_PIN_B 0x05
1426 #define DDC_PIN_C 0x04
1427 #define DDC_PIN_D 0x06
1429 struct ddi_vbt_port_info
{
1431 * This is an index in the HDMI/DVI DDI buffer translation table.
1432 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1433 * populate this field.
1435 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1436 uint8_t hdmi_level_shift
;
1438 uint8_t supports_dvi
:1;
1439 uint8_t supports_hdmi
:1;
1440 uint8_t supports_dp
:1;
1442 uint8_t alternate_aux_channel
;
1443 uint8_t alternate_ddc_pin
;
1445 uint8_t dp_boost_level
;
1446 uint8_t hdmi_boost_level
;
1449 enum psr_lines_to_wait
{
1450 PSR_0_LINES_TO_WAIT
= 0,
1452 PSR_4_LINES_TO_WAIT
,
1456 struct intel_vbt_data
{
1457 struct drm_display_mode
*lfp_lvds_vbt_mode
; /* if any */
1458 struct drm_display_mode
*sdvo_lvds_vbt_mode
; /* if any */
1461 unsigned int int_tv_support
:1;
1462 unsigned int lvds_dither
:1;
1463 unsigned int lvds_vbt
:1;
1464 unsigned int int_crt_support
:1;
1465 unsigned int lvds_use_ssc
:1;
1466 unsigned int display_clock_mode
:1;
1467 unsigned int fdi_rx_polarity_inverted
:1;
1468 unsigned int panel_type
:4;
1470 unsigned int bios_lvds_val
; /* initial [PCH_]LVDS reg val in VBIOS */
1472 enum drrs_support_type drrs_type
;
1483 struct edp_power_seq pps
;
1488 bool require_aux_wakeup
;
1490 enum psr_lines_to_wait lines_to_wait
;
1491 int tp1_wakeup_time
;
1492 int tp2_tp3_wakeup_time
;
1498 bool active_low_pwm
;
1499 u8 min_brightness
; /* min_brightness/255 of max */
1500 enum intel_backlight_type type
;
1506 struct mipi_config
*config
;
1507 struct mipi_pps_data
*pps
;
1511 const u8
*sequence
[MIPI_SEQ_MAX
];
1517 union child_device_config
*child_dev
;
1519 struct ddi_vbt_port_info ddi_port_info
[I915_MAX_PORTS
];
1520 struct sdvo_device_mapping sdvo_mappings
[2];
1523 enum intel_ddb_partitioning
{
1525 INTEL_DDB_PART_5_6
, /* IVB+ */
1528 struct intel_wm_level
{
1536 struct ilk_wm_values
{
1537 uint32_t wm_pipe
[3];
1539 uint32_t wm_lp_spr
[3];
1540 uint32_t wm_linetime
[3];
1542 enum intel_ddb_partitioning partitioning
;
1545 struct vlv_pipe_wm
{
1556 struct vlv_wm_values
{
1557 struct vlv_pipe_wm pipe
[3];
1558 struct vlv_sr_wm sr
;
1568 struct skl_ddb_entry
{
1569 uint16_t start
, end
; /* in number of blocks, 'end' is exclusive */
1572 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry
*entry
)
1574 return entry
->end
- entry
->start
;
1577 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry
*e1
,
1578 const struct skl_ddb_entry
*e2
)
1580 if (e1
->start
== e2
->start
&& e1
->end
== e2
->end
)
1586 struct skl_ddb_allocation
{
1587 struct skl_ddb_entry pipe
[I915_MAX_PIPES
];
1588 struct skl_ddb_entry plane
[I915_MAX_PIPES
][I915_MAX_PLANES
]; /* packed/uv */
1589 struct skl_ddb_entry y_plane
[I915_MAX_PIPES
][I915_MAX_PLANES
];
1592 struct skl_wm_values
{
1593 unsigned dirty_pipes
;
1594 struct skl_ddb_allocation ddb
;
1595 uint32_t wm_linetime
[I915_MAX_PIPES
];
1596 uint32_t plane
[I915_MAX_PIPES
][I915_MAX_PLANES
][8];
1597 uint32_t plane_trans
[I915_MAX_PIPES
][I915_MAX_PLANES
];
1600 struct skl_wm_level
{
1601 bool plane_en
[I915_MAX_PLANES
];
1602 uint16_t plane_res_b
[I915_MAX_PLANES
];
1603 uint8_t plane_res_l
[I915_MAX_PLANES
];
1607 * This struct helps tracking the state needed for runtime PM, which puts the
1608 * device in PCI D3 state. Notice that when this happens, nothing on the
1609 * graphics device works, even register access, so we don't get interrupts nor
1612 * Every piece of our code that needs to actually touch the hardware needs to
1613 * either call intel_runtime_pm_get or call intel_display_power_get with the
1614 * appropriate power domain.
1616 * Our driver uses the autosuspend delay feature, which means we'll only really
1617 * suspend if we stay with zero refcount for a certain amount of time. The
1618 * default value is currently very conservative (see intel_runtime_pm_enable), but
1619 * it can be changed with the standard runtime PM files from sysfs.
1621 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1622 * goes back to false exactly before we reenable the IRQs. We use this variable
1623 * to check if someone is trying to enable/disable IRQs while they're supposed
1624 * to be disabled. This shouldn't happen and we'll print some error messages in
1627 * For more, read the Documentation/power/runtime_pm.txt.
1629 struct i915_runtime_pm
{
1630 atomic_t wakeref_count
;
1631 atomic_t atomic_seq
;
1636 enum intel_pipe_crc_source
{
1637 INTEL_PIPE_CRC_SOURCE_NONE
,
1638 INTEL_PIPE_CRC_SOURCE_PLANE1
,
1639 INTEL_PIPE_CRC_SOURCE_PLANE2
,
1640 INTEL_PIPE_CRC_SOURCE_PF
,
1641 INTEL_PIPE_CRC_SOURCE_PIPE
,
1642 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1643 INTEL_PIPE_CRC_SOURCE_TV
,
1644 INTEL_PIPE_CRC_SOURCE_DP_B
,
1645 INTEL_PIPE_CRC_SOURCE_DP_C
,
1646 INTEL_PIPE_CRC_SOURCE_DP_D
,
1647 INTEL_PIPE_CRC_SOURCE_AUTO
,
1648 INTEL_PIPE_CRC_SOURCE_MAX
,
1651 struct intel_pipe_crc_entry
{
1656 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1657 struct intel_pipe_crc
{
1659 bool opened
; /* exclusive access to the result file */
1660 struct intel_pipe_crc_entry
*entries
;
1661 enum intel_pipe_crc_source source
;
1663 wait_queue_head_t wq
;
1666 struct i915_frontbuffer_tracking
{
1670 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1677 struct i915_wa_reg
{
1680 /* bitmask representing WA bits */
1685 * RING_MAX_NONPRIV_SLOTS is per-engine but at this point we are only
1686 * allowing it for RCS as we don't foresee any requirement of having
1687 * a whitelist for other engines. When it is really required for
1688 * other engines then the limit need to be increased.
1690 #define I915_MAX_WA_REGS (16 + RING_MAX_NONPRIV_SLOTS)
1692 struct i915_workarounds
{
1693 struct i915_wa_reg reg
[I915_MAX_WA_REGS
];
1695 u32 hw_whitelist_count
[I915_NUM_ENGINES
];
1698 struct i915_virtual_gpu
{
1702 /* used in computing the new watermarks state */
1703 struct intel_wm_config
{
1704 unsigned int num_pipes_active
;
1705 bool sprites_enabled
;
1706 bool sprites_scaled
;
1709 struct drm_i915_private
{
1710 struct drm_device drm
;
1712 struct kmem_cache
*objects
;
1713 struct kmem_cache
*vmas
;
1714 struct kmem_cache
*requests
;
1716 const struct intel_device_info info
;
1718 int relative_constants_mode
;
1722 struct intel_uncore uncore
;
1724 struct i915_virtual_gpu vgpu
;
1726 struct intel_gvt gvt
;
1728 struct intel_guc guc
;
1730 struct intel_csr csr
;
1732 struct intel_gmbus gmbus
[GMBUS_NUM_PINS
];
1734 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1735 * controller on different i2c buses. */
1736 struct mutex gmbus_mutex
;
1739 * Base address of the gmbus and gpio block.
1741 uint32_t gpio_mmio_base
;
1743 /* MMIO base address for MIPI regs */
1744 uint32_t mipi_mmio_base
;
1746 uint32_t psr_mmio_base
;
1748 uint32_t pps_mmio_base
;
1750 wait_queue_head_t gmbus_wait_queue
;
1752 struct pci_dev
*bridge_dev
;
1753 struct i915_gem_context
*kernel_context
;
1754 struct intel_engine_cs engine
[I915_NUM_ENGINES
];
1755 struct i915_vma
*semaphore
;
1758 struct drm_dma_handle
*status_page_dmah
;
1759 struct resource mch_res
;
1761 /* protects the irq masks */
1762 spinlock_t irq_lock
;
1764 /* protects the mmio flip data */
1765 spinlock_t mmio_flip_lock
;
1767 bool display_irqs_enabled
;
1769 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1770 struct pm_qos_request pm_qos
;
1772 /* Sideband mailbox protection */
1773 struct mutex sb_lock
;
1775 /** Cached value of IMR to avoid reads in updating the bitfield */
1778 u32 de_irq_mask
[I915_MAX_PIPES
];
1783 u32 pipestat_irq_mask
[I915_MAX_PIPES
];
1785 struct i915_hotplug hotplug
;
1786 struct intel_fbc fbc
;
1787 struct i915_drrs drrs
;
1788 struct intel_opregion opregion
;
1789 struct intel_vbt_data vbt
;
1791 bool preserve_bios_swizzle
;
1794 struct intel_overlay
*overlay
;
1796 /* backlight registers and fields in struct intel_panel */
1797 struct mutex backlight_lock
;
1800 bool no_aux_handshake
;
1802 /* protects panel power sequencer state */
1803 struct mutex pps_mutex
;
1805 struct drm_i915_fence_reg fence_regs
[I915_MAX_NUM_FENCES
]; /* assume 965 */
1806 int num_fence_regs
; /* 8 on pre-965, 16 otherwise */
1808 unsigned int fsb_freq
, mem_freq
, is_ddr3
;
1809 unsigned int skl_preferred_vco_freq
;
1810 unsigned int cdclk_freq
, max_cdclk_freq
, atomic_cdclk_freq
;
1811 unsigned int max_dotclk_freq
;
1812 unsigned int rawclk_freq
;
1813 unsigned int hpll_freq
;
1814 unsigned int czclk_freq
;
1817 unsigned int vco
, ref
;
1821 * wq - Driver workqueue for GEM.
1823 * NOTE: Work items scheduled here are not allowed to grab any modeset
1824 * locks, for otherwise the flushing done in the pageflip code will
1825 * result in deadlocks.
1827 struct workqueue_struct
*wq
;
1829 /* Display functions */
1830 struct drm_i915_display_funcs display
;
1832 /* PCH chipset type */
1833 enum intel_pch pch_type
;
1834 unsigned short pch_id
;
1836 unsigned long quirks
;
1838 enum modeset_restore modeset_restore
;
1839 struct mutex modeset_restore_lock
;
1840 struct drm_atomic_state
*modeset_restore_state
;
1841 struct drm_modeset_acquire_ctx reset_ctx
;
1843 struct list_head vm_list
; /* Global list of all address spaces */
1844 struct i915_ggtt ggtt
; /* VM representing the global address space */
1846 struct i915_gem_mm mm
;
1847 DECLARE_HASHTABLE(mm_structs
, 7);
1848 struct mutex mm_lock
;
1850 /* The hw wants to have a stable context identifier for the lifetime
1851 * of the context (for OA, PASID, faults, etc). This is limited
1852 * in execlists to 21 bits.
1854 struct ida context_hw_ida
;
1855 #define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
1857 /* Kernel Modesetting */
1859 struct drm_crtc
*plane_to_crtc_mapping
[I915_MAX_PIPES
];
1860 struct drm_crtc
*pipe_to_crtc_mapping
[I915_MAX_PIPES
];
1861 wait_queue_head_t pending_flip_queue
;
1863 #ifdef CONFIG_DEBUG_FS
1864 struct intel_pipe_crc pipe_crc
[I915_MAX_PIPES
];
1867 /* dpll and cdclk state is protected by connection_mutex */
1868 int num_shared_dpll
;
1869 struct intel_shared_dpll shared_dplls
[I915_NUM_PLLS
];
1870 const struct intel_dpll_mgr
*dpll_mgr
;
1873 * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
1874 * Must be global rather than per dpll, because on some platforms
1875 * plls share registers.
1877 struct mutex dpll_lock
;
1879 unsigned int active_crtcs
;
1880 unsigned int min_pixclk
[I915_MAX_PIPES
];
1882 int dpio_phy_iosf_port
[I915_NUM_PHYS_VLV
];
1884 struct i915_workarounds workarounds
;
1886 struct i915_frontbuffer_tracking fb_tracking
;
1890 bool mchbar_need_disable
;
1892 struct intel_l3_parity l3_parity
;
1894 /* Cannot be determined by PCIID. You must always read a register. */
1897 /* gen6+ rps state */
1898 struct intel_gen6_power_mgmt rps
;
1900 /* ilk-only ips/rps state. Everything in here is protected by the global
1901 * mchdev_lock in intel_pm.c */
1902 struct intel_ilk_power_mgmt ips
;
1904 struct i915_power_domains power_domains
;
1906 struct i915_psr psr
;
1908 struct i915_gpu_error gpu_error
;
1910 struct drm_i915_gem_object
*vlv_pctx
;
1912 #ifdef CONFIG_DRM_FBDEV_EMULATION
1913 /* list of fbdev register on this device */
1914 struct intel_fbdev
*fbdev
;
1915 struct work_struct fbdev_suspend_work
;
1918 struct drm_property
*broadcast_rgb_property
;
1919 struct drm_property
*force_audio_property
;
1921 /* hda/i915 audio component */
1922 struct i915_audio_component
*audio_component
;
1923 bool audio_component_registered
;
1925 * av_mutex - mutex for audio/video sync
1928 struct mutex av_mutex
;
1930 uint32_t hw_context_size
;
1931 struct list_head context_list
;
1935 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
1936 u32 chv_phy_control
;
1938 * Shadows for CHV DPLL_MD regs to keep the state
1939 * checker somewhat working in the presence hardware
1940 * crappiness (can't read out DPLL_MD for pipes B & C).
1942 u32 chv_dpll_md
[I915_MAX_PIPES
];
1946 bool suspended_to_idle
;
1947 struct i915_suspend_saved_registers regfile
;
1948 struct vlv_s0ix_state vlv_s0ix_state
;
1952 * Raw watermark latency values:
1953 * in 0.1us units for WM0,
1954 * in 0.5us units for WM1+.
1957 uint16_t pri_latency
[5];
1959 uint16_t spr_latency
[5];
1961 uint16_t cur_latency
[5];
1963 * Raw watermark memory latency values
1964 * for SKL for all 8 levels
1967 uint16_t skl_latency
[8];
1970 * The skl_wm_values structure is a bit too big for stack
1971 * allocation, so we keep the staging struct where we store
1972 * intermediate results here instead.
1974 struct skl_wm_values skl_results
;
1976 /* current hardware state */
1978 struct ilk_wm_values hw
;
1979 struct skl_wm_values skl_hw
;
1980 struct vlv_wm_values vlv
;
1986 * Should be held around atomic WM register writing; also
1987 * protects * intel_crtc->wm.active and
1988 * cstate->wm.need_postvbl_update.
1990 struct mutex wm_mutex
;
1993 * Set during HW readout of watermarks/DDB. Some platforms
1994 * need to know when we're still using BIOS-provided values
1995 * (which we don't fully trust).
1997 bool distrust_bios_wm
;
2000 struct i915_runtime_pm pm
;
2002 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
2004 void (*cleanup_engine
)(struct intel_engine_cs
*engine
);
2007 * Is the GPU currently considered idle, or busy executing
2008 * userspace requests? Whilst idle, we allow runtime power
2009 * management to power down the hardware and display clocks.
2010 * In order to reduce the effect on performance, there
2011 * is a slight delay before we do so.
2013 unsigned int active_engines
;
2017 * We leave the user IRQ off as much as possible,
2018 * but this means that requests will finish and never
2019 * be retired once the system goes idle. Set a timer to
2020 * fire periodically while the ring is running. When it
2021 * fires, go retire requests.
2023 struct delayed_work retire_work
;
2026 * When we detect an idle GPU, we want to turn on
2027 * powersaving features. So once we see that there
2028 * are no more requests outstanding and no more
2029 * arrive within a small period of time, we fire
2030 * off the idle_work.
2032 struct delayed_work idle_work
;
2035 /* perform PHY state sanity checks? */
2036 bool chv_phy_assert
[2];
2038 struct intel_encoder
*dig_port_map
[I915_MAX_PORTS
];
2041 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
2042 * will be rejected. Instead look for a better place.
2046 static inline struct drm_i915_private
*to_i915(const struct drm_device
*dev
)
2048 return container_of(dev
, struct drm_i915_private
, drm
);
2051 static inline struct drm_i915_private
*dev_to_i915(struct device
*dev
)
2053 return to_i915(dev_get_drvdata(dev
));
2056 static inline struct drm_i915_private
*guc_to_i915(struct intel_guc
*guc
)
2058 return container_of(guc
, struct drm_i915_private
, guc
);
2061 /* Simple iterator over all initialised engines */
2062 #define for_each_engine(engine__, dev_priv__) \
2063 for ((engine__) = &(dev_priv__)->engine[0]; \
2064 (engine__) < &(dev_priv__)->engine[I915_NUM_ENGINES]; \
2066 for_each_if (intel_engine_initialized(engine__))
2068 /* Iterator with engine_id */
2069 #define for_each_engine_id(engine__, dev_priv__, id__) \
2070 for ((engine__) = &(dev_priv__)->engine[0], (id__) = 0; \
2071 (engine__) < &(dev_priv__)->engine[I915_NUM_ENGINES]; \
2073 for_each_if (((id__) = (engine__)->id, \
2074 intel_engine_initialized(engine__)))
2076 /* Iterator over subset of engines selected by mask */
2077 #define for_each_engine_masked(engine__, dev_priv__, mask__) \
2078 for ((engine__) = &(dev_priv__)->engine[0]; \
2079 (engine__) < &(dev_priv__)->engine[I915_NUM_ENGINES]; \
2081 for_each_if (((mask__) & intel_engine_flag(engine__)) && \
2082 intel_engine_initialized(engine__))
2084 enum hdmi_force_audio
{
2085 HDMI_AUDIO_OFF_DVI
= -2, /* no aux data for HDMI-DVI converter */
2086 HDMI_AUDIO_OFF
, /* force turn off HDMI audio */
2087 HDMI_AUDIO_AUTO
, /* trust EDID */
2088 HDMI_AUDIO_ON
, /* force turn on HDMI audio */
2091 #define I915_GTT_OFFSET_NONE ((u32)-1)
2093 struct drm_i915_gem_object_ops
{
2095 #define I915_GEM_OBJECT_HAS_STRUCT_PAGE 0x1
2097 /* Interface between the GEM object and its backing storage.
2098 * get_pages() is called once prior to the use of the associated set
2099 * of pages before to binding them into the GTT, and put_pages() is
2100 * called after we no longer need them. As we expect there to be
2101 * associated cost with migrating pages between the backing storage
2102 * and making them available for the GPU (e.g. clflush), we may hold
2103 * onto the pages after they are no longer referenced by the GPU
2104 * in case they may be used again shortly (for example migrating the
2105 * pages to a different memory domain within the GTT). put_pages()
2106 * will therefore most likely be called when the object itself is
2107 * being released or under memory pressure (where we attempt to
2108 * reap pages for the shrinker).
2110 int (*get_pages
)(struct drm_i915_gem_object
*);
2111 void (*put_pages
)(struct drm_i915_gem_object
*);
2113 int (*dmabuf_export
)(struct drm_i915_gem_object
*);
2114 void (*release
)(struct drm_i915_gem_object
*);
2118 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2119 * considered to be the frontbuffer for the given plane interface-wise. This
2120 * doesn't mean that the hw necessarily already scans it out, but that any
2121 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
2123 * We have one bit per pipe and per scanout plane type.
2125 #define INTEL_MAX_SPRITE_BITS_PER_PIPE 5
2126 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2127 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
2128 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2129 #define INTEL_FRONTBUFFER_CURSOR(pipe) \
2130 (1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2131 #define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \
2132 (1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2133 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2134 (1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2135 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2136 (0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2138 struct drm_i915_gem_object
{
2139 struct drm_gem_object base
;
2141 const struct drm_i915_gem_object_ops
*ops
;
2143 /** List of VMAs backed by this object */
2144 struct list_head vma_list
;
2146 /** Stolen memory for this object, instead of being backed by shmem. */
2147 struct drm_mm_node
*stolen
;
2148 struct list_head global_list
;
2150 /** Used in execbuf to temporarily hold a ref */
2151 struct list_head obj_exec_link
;
2153 struct list_head batch_pool_link
;
2155 unsigned long flags
;
2157 * This is set if the object is on the active lists (has pending
2158 * rendering and so a non-zero seqno), and is not set if it i s on
2159 * inactive (ready to be unbound) list.
2161 #define I915_BO_ACTIVE_SHIFT 0
2162 #define I915_BO_ACTIVE_MASK ((1 << I915_NUM_ENGINES) - 1)
2163 #define __I915_BO_ACTIVE(bo) \
2164 ((READ_ONCE((bo)->flags) >> I915_BO_ACTIVE_SHIFT) & I915_BO_ACTIVE_MASK)
2167 * This is set if the object has been written to since last bound
2170 unsigned int dirty
:1;
2173 * Fence register bits (if any) for this object. Will be set
2174 * as needed when mapped into the GTT.
2175 * Protected by dev->struct_mutex.
2177 signed int fence_reg
:I915_MAX_NUM_FENCE_BITS
;
2180 * Advice: are the backing pages purgeable?
2182 unsigned int madv
:2;
2185 * Whether the tiling parameters for the currently associated fence
2186 * register have changed. Note that for the purposes of tracking
2187 * tiling changes we also treat the unfenced register, the register
2188 * slot that the object occupies whilst it executes a fenced
2189 * command (such as BLT on gen2/3), as a "fence".
2191 unsigned int fence_dirty
:1;
2194 * Is the object at the current location in the gtt mappable and
2195 * fenceable? Used to avoid costly recalculations.
2197 unsigned int map_and_fenceable
:1;
2200 * Whether the current gtt mapping needs to be mappable (and isn't just
2201 * mappable by accident). Track pin and fault separate for a more
2202 * accurate mappable working set.
2204 unsigned int fault_mappable
:1;
2207 * Is the object to be mapped as read-only to the GPU
2208 * Only honoured if hardware has relevant pte bit
2210 unsigned long gt_ro
:1;
2211 unsigned int cache_level
:3;
2212 unsigned int cache_dirty
:1;
2214 atomic_t frontbuffer_bits
;
2216 /** Current tiling stride for the object, if it's tiled. */
2217 unsigned int tiling_and_stride
;
2218 #define FENCE_MINIMUM_STRIDE 128 /* See i915_tiling_ok() */
2219 #define TILING_MASK (FENCE_MINIMUM_STRIDE-1)
2220 #define STRIDE_MASK (~TILING_MASK)
2222 unsigned int has_wc_mmap
;
2223 /** Count of VMA actually bound by this object */
2224 unsigned int bind_count
;
2225 unsigned int pin_display
;
2227 struct sg_table
*pages
;
2228 int pages_pin_count
;
2230 struct scatterlist
*sg
;
2235 /** Breadcrumb of last rendering to the buffer.
2236 * There can only be one writer, but we allow for multiple readers.
2237 * If there is a writer that necessarily implies that all other
2238 * read requests are complete - but we may only be lazily clearing
2239 * the read requests. A read request is naturally the most recent
2240 * request on a ring, so we may have two different write and read
2241 * requests on one ring where the write request is older than the
2242 * read request. This allows for the CPU to read from an active
2243 * buffer by only waiting for the write to complete.
2245 struct i915_gem_active last_read
[I915_NUM_ENGINES
];
2246 struct i915_gem_active last_write
;
2247 struct i915_gem_active last_fence
;
2249 /** References from framebuffers, locks out tiling changes. */
2250 unsigned long framebuffer_references
;
2252 /** Record of address bit 17 of each page at last unbind. */
2253 unsigned long *bit_17
;
2256 /** for phy allocated objects */
2257 struct drm_dma_handle
*phys_handle
;
2259 struct i915_gem_userptr
{
2261 unsigned read_only
:1;
2262 unsigned workers
:4;
2263 #define I915_GEM_USERPTR_MAX_WORKERS 15
2265 struct i915_mm_struct
*mm
;
2266 struct i915_mmu_object
*mmu_object
;
2267 struct work_struct
*work
;
2272 static inline struct drm_i915_gem_object
*
2273 to_intel_bo(struct drm_gem_object
*gem
)
2275 /* Assert that to_intel_bo(NULL) == NULL */
2276 BUILD_BUG_ON(offsetof(struct drm_i915_gem_object
, base
));
2278 return container_of(gem
, struct drm_i915_gem_object
, base
);
2281 static inline struct drm_i915_gem_object
*
2282 i915_gem_object_lookup(struct drm_file
*file
, u32 handle
)
2284 return to_intel_bo(drm_gem_object_lookup(file
, handle
));
2288 extern struct drm_gem_object
*
2289 drm_gem_object_lookup(struct drm_file
*file
, u32 handle
);
2291 __attribute__((nonnull
))
2292 static inline struct drm_i915_gem_object
*
2293 i915_gem_object_get(struct drm_i915_gem_object
*obj
)
2295 drm_gem_object_reference(&obj
->base
);
2300 extern void drm_gem_object_reference(struct drm_gem_object
*);
2302 __attribute__((nonnull
))
2304 i915_gem_object_put(struct drm_i915_gem_object
*obj
)
2306 drm_gem_object_unreference(&obj
->base
);
2310 extern void drm_gem_object_unreference(struct drm_gem_object
*);
2312 __attribute__((nonnull
))
2314 i915_gem_object_put_unlocked(struct drm_i915_gem_object
*obj
)
2316 drm_gem_object_unreference_unlocked(&obj
->base
);
2320 extern void drm_gem_object_unreference_unlocked(struct drm_gem_object
*);
2323 i915_gem_object_has_struct_page(const struct drm_i915_gem_object
*obj
)
2325 return obj
->ops
->flags
& I915_GEM_OBJECT_HAS_STRUCT_PAGE
;
2328 static inline unsigned long
2329 i915_gem_object_get_active(const struct drm_i915_gem_object
*obj
)
2331 return (obj
->flags
>> I915_BO_ACTIVE_SHIFT
) & I915_BO_ACTIVE_MASK
;
2335 i915_gem_object_is_active(const struct drm_i915_gem_object
*obj
)
2337 return i915_gem_object_get_active(obj
);
2341 i915_gem_object_set_active(struct drm_i915_gem_object
*obj
, int engine
)
2343 obj
->flags
|= BIT(engine
+ I915_BO_ACTIVE_SHIFT
);
2347 i915_gem_object_clear_active(struct drm_i915_gem_object
*obj
, int engine
)
2349 obj
->flags
&= ~BIT(engine
+ I915_BO_ACTIVE_SHIFT
);
2353 i915_gem_object_has_active_engine(const struct drm_i915_gem_object
*obj
,
2356 return obj
->flags
& BIT(engine
+ I915_BO_ACTIVE_SHIFT
);
2359 static inline unsigned int
2360 i915_gem_object_get_tiling(struct drm_i915_gem_object
*obj
)
2362 return obj
->tiling_and_stride
& TILING_MASK
;
2366 i915_gem_object_is_tiled(struct drm_i915_gem_object
*obj
)
2368 return i915_gem_object_get_tiling(obj
) != I915_TILING_NONE
;
2371 static inline unsigned int
2372 i915_gem_object_get_stride(struct drm_i915_gem_object
*obj
)
2374 return obj
->tiling_and_stride
& STRIDE_MASK
;
2377 static inline struct i915_vma
*i915_vma_get(struct i915_vma
*vma
)
2379 i915_gem_object_get(vma
->obj
);
2383 static inline void i915_vma_put(struct i915_vma
*vma
)
2385 lockdep_assert_held(&vma
->vm
->dev
->struct_mutex
);
2386 i915_gem_object_put(vma
->obj
);
2390 * Optimised SGL iterator for GEM objects
2392 static __always_inline
struct sgt_iter
{
2393 struct scatterlist
*sgp
;
2400 } __sgt_iter(struct scatterlist
*sgl
, bool dma
) {
2401 struct sgt_iter s
= { .sgp
= sgl
};
2404 s
.max
= s
.curr
= s
.sgp
->offset
;
2405 s
.max
+= s
.sgp
->length
;
2407 s
.dma
= sg_dma_address(s
.sgp
);
2409 s
.pfn
= page_to_pfn(sg_page(s
.sgp
));
2416 * __sg_next - return the next scatterlist entry in a list
2417 * @sg: The current sg entry
2420 * If the entry is the last, return NULL; otherwise, step to the next
2421 * element in the array (@sg@+1). If that's a chain pointer, follow it;
2422 * otherwise just return the pointer to the current element.
2424 static inline struct scatterlist
*__sg_next(struct scatterlist
*sg
)
2426 #ifdef CONFIG_DEBUG_SG
2427 BUG_ON(sg
->sg_magic
!= SG_MAGIC
);
2429 return sg_is_last(sg
) ? NULL
:
2430 likely(!sg_is_chain(++sg
)) ? sg
:
2435 * for_each_sgt_dma - iterate over the DMA addresses of the given sg_table
2436 * @__dmap: DMA address (output)
2437 * @__iter: 'struct sgt_iter' (iterator state, internal)
2438 * @__sgt: sg_table to iterate over (input)
2440 #define for_each_sgt_dma(__dmap, __iter, __sgt) \
2441 for ((__iter) = __sgt_iter((__sgt)->sgl, true); \
2442 ((__dmap) = (__iter).dma + (__iter).curr); \
2443 (((__iter).curr += PAGE_SIZE) < (__iter).max) || \
2444 ((__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0))
2447 * for_each_sgt_page - iterate over the pages of the given sg_table
2448 * @__pp: page pointer (output)
2449 * @__iter: 'struct sgt_iter' (iterator state, internal)
2450 * @__sgt: sg_table to iterate over (input)
2452 #define for_each_sgt_page(__pp, __iter, __sgt) \
2453 for ((__iter) = __sgt_iter((__sgt)->sgl, false); \
2454 ((__pp) = (__iter).pfn == 0 ? NULL : \
2455 pfn_to_page((__iter).pfn + ((__iter).curr >> PAGE_SHIFT))); \
2456 (((__iter).curr += PAGE_SIZE) < (__iter).max) || \
2457 ((__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0))
2460 * A command that requires special handling by the command parser.
2462 struct drm_i915_cmd_descriptor
{
2464 * Flags describing how the command parser processes the command.
2466 * CMD_DESC_FIXED: The command has a fixed length if this is set,
2467 * a length mask if not set
2468 * CMD_DESC_SKIP: The command is allowed but does not follow the
2469 * standard length encoding for the opcode range in
2471 * CMD_DESC_REJECT: The command is never allowed
2472 * CMD_DESC_REGISTER: The command should be checked against the
2473 * register whitelist for the appropriate ring
2474 * CMD_DESC_MASTER: The command is allowed if the submitting process
2478 #define CMD_DESC_FIXED (1<<0)
2479 #define CMD_DESC_SKIP (1<<1)
2480 #define CMD_DESC_REJECT (1<<2)
2481 #define CMD_DESC_REGISTER (1<<3)
2482 #define CMD_DESC_BITMASK (1<<4)
2483 #define CMD_DESC_MASTER (1<<5)
2486 * The command's unique identification bits and the bitmask to get them.
2487 * This isn't strictly the opcode field as defined in the spec and may
2488 * also include type, subtype, and/or subop fields.
2496 * The command's length. The command is either fixed length (i.e. does
2497 * not include a length field) or has a length field mask. The flag
2498 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
2499 * a length mask. All command entries in a command table must include
2500 * length information.
2508 * Describes where to find a register address in the command to check
2509 * against the ring's register whitelist. Only valid if flags has the
2510 * CMD_DESC_REGISTER bit set.
2512 * A non-zero step value implies that the command may access multiple
2513 * registers in sequence (e.g. LRI), in that case step gives the
2514 * distance in dwords between individual offset fields.
2522 #define MAX_CMD_DESC_BITMASKS 3
2524 * Describes command checks where a particular dword is masked and
2525 * compared against an expected value. If the command does not match
2526 * the expected value, the parser rejects it. Only valid if flags has
2527 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
2530 * If the check specifies a non-zero condition_mask then the parser
2531 * only performs the check when the bits specified by condition_mask
2538 u32 condition_offset
;
2540 } bits
[MAX_CMD_DESC_BITMASKS
];
2544 * A table of commands requiring special handling by the command parser.
2546 * Each engine has an array of tables. Each table consists of an array of
2547 * command descriptors, which must be sorted with command opcodes in
2550 struct drm_i915_cmd_table
{
2551 const struct drm_i915_cmd_descriptor
*table
;
2555 /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
2556 #define __I915__(p) ({ \
2557 struct drm_i915_private *__p; \
2558 if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
2559 __p = (struct drm_i915_private *)p; \
2560 else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
2561 __p = to_i915((struct drm_device *)p); \
2566 #define INTEL_INFO(p) (&__I915__(p)->info)
2567 #define INTEL_GEN(p) (INTEL_INFO(p)->gen)
2568 #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id)
2570 #define REVID_FOREVER 0xff
2571 #define INTEL_REVID(p) (__I915__(p)->drm.pdev->revision)
2573 #define GEN_FOREVER (0)
2575 * Returns true if Gen is in inclusive range [Start, End].
2577 * Use GEN_FOREVER for unbound start and or end.
2579 #define IS_GEN(p, s, e) ({ \
2580 unsigned int __s = (s), __e = (e); \
2581 BUILD_BUG_ON(!__builtin_constant_p(s)); \
2582 BUILD_BUG_ON(!__builtin_constant_p(e)); \
2583 if ((__s) != GEN_FOREVER) \
2585 if ((__e) == GEN_FOREVER) \
2586 __e = BITS_PER_LONG - 1; \
2589 !!(INTEL_INFO(p)->gen_mask & GENMASK((__e), (__s))); \
2593 * Return true if revision is in range [since,until] inclusive.
2595 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
2597 #define IS_REVID(p, since, until) \
2598 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
2600 #define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577)
2601 #define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562)
2602 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
2603 #define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572)
2604 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
2605 #define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592)
2606 #define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772)
2607 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
2608 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
2609 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
2610 #define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42)
2611 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
2612 #define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001)
2613 #define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011)
2614 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
2615 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
2616 #define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046)
2617 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
2618 #define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \
2619 INTEL_DEVID(dev) == 0x0152 || \
2620 INTEL_DEVID(dev) == 0x015a)
2621 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
2622 #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_cherryview)
2623 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
2624 #define IS_BROADWELL(dev) (INTEL_INFO(dev)->is_broadwell)
2625 #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake)
2626 #define IS_BROXTON(dev) (INTEL_INFO(dev)->is_broxton)
2627 #define IS_KABYLAKE(dev) (INTEL_INFO(dev)->is_kabylake)
2628 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
2629 #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
2630 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
2631 #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
2632 ((INTEL_DEVID(dev) & 0xf) == 0x6 || \
2633 (INTEL_DEVID(dev) & 0xf) == 0xb || \
2634 (INTEL_DEVID(dev) & 0xf) == 0xe))
2635 /* ULX machines are also considered ULT. */
2636 #define IS_BDW_ULX(dev) (IS_BROADWELL(dev) && \
2637 (INTEL_DEVID(dev) & 0xf) == 0xe)
2638 #define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \
2639 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2640 #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
2641 (INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
2642 #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
2643 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2644 /* ULX machines are also considered ULT. */
2645 #define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \
2646 INTEL_DEVID(dev) == 0x0A1E)
2647 #define IS_SKL_ULT(dev) (INTEL_DEVID(dev) == 0x1906 || \
2648 INTEL_DEVID(dev) == 0x1913 || \
2649 INTEL_DEVID(dev) == 0x1916 || \
2650 INTEL_DEVID(dev) == 0x1921 || \
2651 INTEL_DEVID(dev) == 0x1926)
2652 #define IS_SKL_ULX(dev) (INTEL_DEVID(dev) == 0x190E || \
2653 INTEL_DEVID(dev) == 0x1915 || \
2654 INTEL_DEVID(dev) == 0x191E)
2655 #define IS_KBL_ULT(dev) (INTEL_DEVID(dev) == 0x5906 || \
2656 INTEL_DEVID(dev) == 0x5913 || \
2657 INTEL_DEVID(dev) == 0x5916 || \
2658 INTEL_DEVID(dev) == 0x5921 || \
2659 INTEL_DEVID(dev) == 0x5926)
2660 #define IS_KBL_ULX(dev) (INTEL_DEVID(dev) == 0x590E || \
2661 INTEL_DEVID(dev) == 0x5915 || \
2662 INTEL_DEVID(dev) == 0x591E)
2663 #define IS_SKL_GT3(dev) (IS_SKYLAKE(dev) && \
2664 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2665 #define IS_SKL_GT4(dev) (IS_SKYLAKE(dev) && \
2666 (INTEL_DEVID(dev) & 0x00F0) == 0x0030)
2668 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
2670 #define SKL_REVID_A0 0x0
2671 #define SKL_REVID_B0 0x1
2672 #define SKL_REVID_C0 0x2
2673 #define SKL_REVID_D0 0x3
2674 #define SKL_REVID_E0 0x4
2675 #define SKL_REVID_F0 0x5
2676 #define SKL_REVID_G0 0x6
2677 #define SKL_REVID_H0 0x7
2679 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
2681 #define BXT_REVID_A0 0x0
2682 #define BXT_REVID_A1 0x1
2683 #define BXT_REVID_B0 0x3
2684 #define BXT_REVID_C0 0x9
2686 #define IS_BXT_REVID(p, since, until) (IS_BROXTON(p) && IS_REVID(p, since, until))
2688 #define KBL_REVID_A0 0x0
2689 #define KBL_REVID_B0 0x1
2690 #define KBL_REVID_C0 0x2
2691 #define KBL_REVID_D0 0x3
2692 #define KBL_REVID_E0 0x4
2694 #define IS_KBL_REVID(p, since, until) \
2695 (IS_KABYLAKE(p) && IS_REVID(p, since, until))
2698 * The genX designation typically refers to the render engine, so render
2699 * capability related checks should use IS_GEN, while display and other checks
2700 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2703 #define IS_GEN2(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(1)))
2704 #define IS_GEN3(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(2)))
2705 #define IS_GEN4(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(3)))
2706 #define IS_GEN5(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(4)))
2707 #define IS_GEN6(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(5)))
2708 #define IS_GEN7(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(6)))
2709 #define IS_GEN8(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(7)))
2710 #define IS_GEN9(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(8)))
2712 #define ENGINE_MASK(id) BIT(id)
2713 #define RENDER_RING ENGINE_MASK(RCS)
2714 #define BSD_RING ENGINE_MASK(VCS)
2715 #define BLT_RING ENGINE_MASK(BCS)
2716 #define VEBOX_RING ENGINE_MASK(VECS)
2717 #define BSD2_RING ENGINE_MASK(VCS2)
2718 #define ALL_ENGINES (~0)
2720 #define HAS_ENGINE(dev_priv, id) \
2721 (!!(INTEL_INFO(dev_priv)->ring_mask & ENGINE_MASK(id)))
2723 #define HAS_BSD(dev_priv) HAS_ENGINE(dev_priv, VCS)
2724 #define HAS_BSD2(dev_priv) HAS_ENGINE(dev_priv, VCS2)
2725 #define HAS_BLT(dev_priv) HAS_ENGINE(dev_priv, BCS)
2726 #define HAS_VEBOX(dev_priv) HAS_ENGINE(dev_priv, VECS)
2728 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
2729 #define HAS_SNOOP(dev) (INTEL_INFO(dev)->has_snoop)
2730 #define HAS_EDRAM(dev) (!!(__I915__(dev)->edram_cap & EDRAM_ENABLED))
2731 #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
2733 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
2735 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
2736 #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8)
2737 #define USES_PPGTT(dev) (i915.enable_ppgtt)
2738 #define USES_FULL_PPGTT(dev) (i915.enable_ppgtt >= 2)
2739 #define USES_FULL_48BIT_PPGTT(dev) (i915.enable_ppgtt == 3)
2741 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
2742 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
2744 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2745 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
2747 /* WaRsDisableCoarsePowerGating:skl,bxt */
2748 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
2749 (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1) || \
2750 IS_SKL_GT3(dev_priv) || \
2751 IS_SKL_GT4(dev_priv))
2754 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2755 * even when in MSI mode. This results in spurious interrupt warnings if the
2756 * legacy irq no. is shared with another device. The kernel then disables that
2757 * interrupt source and so prevents the other device from working properly.
2759 #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2760 #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2762 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2763 * rows, which changed the alignment requirements and fence programming.
2765 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
2767 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
2768 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
2770 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
2771 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
2772 #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
2774 #define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev))
2776 #define HAS_DP_MST(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2777 INTEL_INFO(dev)->gen >= 9)
2779 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
2780 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
2781 #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2782 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \
2783 IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
2784 #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \
2785 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \
2786 IS_CHERRYVIEW(dev) || IS_SKYLAKE(dev) || \
2787 IS_KABYLAKE(dev) || IS_BROXTON(dev))
2788 #define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6)
2789 #define HAS_RC6p(dev) (IS_GEN6(dev) || IS_IVYBRIDGE(dev))
2791 #define HAS_CSR(dev) (IS_GEN9(dev))
2794 * For now, anything with a GuC requires uCode loading, and then supports
2795 * command submission once loaded. But these are logically independent
2796 * properties, so we have separate macros to test them.
2798 #define HAS_GUC(dev) (IS_GEN9(dev))
2799 #define HAS_GUC_UCODE(dev) (HAS_GUC(dev))
2800 #define HAS_GUC_SCHED(dev) (HAS_GUC(dev))
2802 #define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \
2803 INTEL_INFO(dev)->gen >= 8)
2805 #define HAS_CORE_RING_FREQ(dev) (INTEL_INFO(dev)->gen >= 6 && \
2806 !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && \
2809 #define HAS_POOLED_EU(dev) (INTEL_INFO(dev)->has_pooled_eu)
2811 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
2812 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2813 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2814 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2815 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2816 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2817 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2818 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2819 #define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA200
2820 #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
2821 #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
2822 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
2824 #define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
2825 #define HAS_PCH_KBP(dev) (INTEL_PCH_TYPE(dev) == PCH_KBP)
2826 #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
2827 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
2828 #define HAS_PCH_LPT_LP(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
2829 #define HAS_PCH_LPT_H(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
2830 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
2831 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
2832 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
2833 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
2835 #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || \
2836 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
2838 /* DPF == dynamic parity feature */
2839 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
2840 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
2842 #define GT_FREQUENCY_MULTIPLIER 50
2843 #define GEN9_FREQ_SCALER 3
2845 #include "i915_trace.h"
2847 static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private
*dev_priv
)
2849 #ifdef CONFIG_INTEL_IOMMU
2850 if (INTEL_GEN(dev_priv
) >= 6 && intel_iommu_gfx_mapped
)
2856 extern int i915_suspend_switcheroo(struct drm_device
*dev
, pm_message_t state
);
2857 extern int i915_resume_switcheroo(struct drm_device
*dev
);
2859 int intel_sanitize_enable_ppgtt(struct drm_i915_private
*dev_priv
,
2862 bool intel_sanitize_semaphores(struct drm_i915_private
*dev_priv
, int value
);
2866 __i915_printk(struct drm_i915_private
*dev_priv
, const char *level
,
2867 const char *fmt
, ...);
2869 #define i915_report_error(dev_priv, fmt, ...) \
2870 __i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__)
2872 #ifdef CONFIG_COMPAT
2873 extern long i915_compat_ioctl(struct file
*filp
, unsigned int cmd
,
2876 extern int intel_gpu_reset(struct drm_i915_private
*dev_priv
, u32 engine_mask
);
2877 extern bool intel_has_gpu_reset(struct drm_i915_private
*dev_priv
);
2878 extern int i915_reset(struct drm_i915_private
*dev_priv
);
2879 extern int intel_guc_reset(struct drm_i915_private
*dev_priv
);
2880 extern void intel_engine_init_hangcheck(struct intel_engine_cs
*engine
);
2881 extern unsigned long i915_chipset_val(struct drm_i915_private
*dev_priv
);
2882 extern unsigned long i915_mch_val(struct drm_i915_private
*dev_priv
);
2883 extern unsigned long i915_gfx_val(struct drm_i915_private
*dev_priv
);
2884 extern void i915_update_gfx_val(struct drm_i915_private
*dev_priv
);
2885 int vlv_force_gfx_clock(struct drm_i915_private
*dev_priv
, bool on
);
2887 /* intel_hotplug.c */
2888 void intel_hpd_irq_handler(struct drm_i915_private
*dev_priv
,
2889 u32 pin_mask
, u32 long_mask
);
2890 void intel_hpd_init(struct drm_i915_private
*dev_priv
);
2891 void intel_hpd_init_work(struct drm_i915_private
*dev_priv
);
2892 void intel_hpd_cancel_work(struct drm_i915_private
*dev_priv
);
2893 bool intel_hpd_pin_to_port(enum hpd_pin pin
, enum port
*port
);
2894 bool intel_hpd_disable(struct drm_i915_private
*dev_priv
, enum hpd_pin pin
);
2895 void intel_hpd_enable(struct drm_i915_private
*dev_priv
, enum hpd_pin pin
);
2898 static inline void i915_queue_hangcheck(struct drm_i915_private
*dev_priv
)
2900 unsigned long delay
;
2902 if (unlikely(!i915
.enable_hangcheck
))
2905 /* Don't continually defer the hangcheck so that it is always run at
2906 * least once after work has been scheduled on any ring. Otherwise,
2907 * we will ignore a hung ring if a second ring is kept busy.
2910 delay
= round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES
);
2911 queue_delayed_work(system_long_wq
,
2912 &dev_priv
->gpu_error
.hangcheck_work
, delay
);
2916 void i915_handle_error(struct drm_i915_private
*dev_priv
,
2918 const char *fmt
, ...);
2920 extern void intel_irq_init(struct drm_i915_private
*dev_priv
);
2921 int intel_irq_install(struct drm_i915_private
*dev_priv
);
2922 void intel_irq_uninstall(struct drm_i915_private
*dev_priv
);
2924 extern void intel_uncore_sanitize(struct drm_i915_private
*dev_priv
);
2925 extern void intel_uncore_early_sanitize(struct drm_i915_private
*dev_priv
,
2926 bool restore_forcewake
);
2927 extern void intel_uncore_init(struct drm_i915_private
*dev_priv
);
2928 extern bool intel_uncore_unclaimed_mmio(struct drm_i915_private
*dev_priv
);
2929 extern bool intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private
*dev_priv
);
2930 extern void intel_uncore_fini(struct drm_i915_private
*dev_priv
);
2931 extern void intel_uncore_forcewake_reset(struct drm_i915_private
*dev_priv
,
2933 const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id
);
2934 void intel_uncore_forcewake_get(struct drm_i915_private
*dev_priv
,
2935 enum forcewake_domains domains
);
2936 void intel_uncore_forcewake_put(struct drm_i915_private
*dev_priv
,
2937 enum forcewake_domains domains
);
2938 /* Like above but the caller must manage the uncore.lock itself.
2939 * Must be used with I915_READ_FW and friends.
2941 void intel_uncore_forcewake_get__locked(struct drm_i915_private
*dev_priv
,
2942 enum forcewake_domains domains
);
2943 void intel_uncore_forcewake_put__locked(struct drm_i915_private
*dev_priv
,
2944 enum forcewake_domains domains
);
2945 u64
intel_uncore_edram_size(struct drm_i915_private
*dev_priv
);
2947 void assert_forcewakes_inactive(struct drm_i915_private
*dev_priv
);
2949 int intel_wait_for_register(struct drm_i915_private
*dev_priv
,
2953 const unsigned long timeout_ms
);
2954 int intel_wait_for_register_fw(struct drm_i915_private
*dev_priv
,
2958 const unsigned long timeout_ms
);
2960 static inline bool intel_gvt_active(struct drm_i915_private
*dev_priv
)
2962 return dev_priv
->gvt
.initialized
;
2965 static inline bool intel_vgpu_active(struct drm_i915_private
*dev_priv
)
2967 return dev_priv
->vgpu
.active
;
2971 i915_enable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
2975 i915_disable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
2978 void valleyview_enable_display_irqs(struct drm_i915_private
*dev_priv
);
2979 void valleyview_disable_display_irqs(struct drm_i915_private
*dev_priv
);
2980 void i915_hotplug_interrupt_update(struct drm_i915_private
*dev_priv
,
2983 void ilk_update_display_irq(struct drm_i915_private
*dev_priv
,
2984 uint32_t interrupt_mask
,
2985 uint32_t enabled_irq_mask
);
2987 ilk_enable_display_irq(struct drm_i915_private
*dev_priv
, uint32_t bits
)
2989 ilk_update_display_irq(dev_priv
, bits
, bits
);
2992 ilk_disable_display_irq(struct drm_i915_private
*dev_priv
, uint32_t bits
)
2994 ilk_update_display_irq(dev_priv
, bits
, 0);
2996 void bdw_update_pipe_irq(struct drm_i915_private
*dev_priv
,
2998 uint32_t interrupt_mask
,
2999 uint32_t enabled_irq_mask
);
3000 static inline void bdw_enable_pipe_irq(struct drm_i915_private
*dev_priv
,
3001 enum pipe pipe
, uint32_t bits
)
3003 bdw_update_pipe_irq(dev_priv
, pipe
, bits
, bits
);
3005 static inline void bdw_disable_pipe_irq(struct drm_i915_private
*dev_priv
,
3006 enum pipe pipe
, uint32_t bits
)
3008 bdw_update_pipe_irq(dev_priv
, pipe
, bits
, 0);
3010 void ibx_display_interrupt_update(struct drm_i915_private
*dev_priv
,
3011 uint32_t interrupt_mask
,
3012 uint32_t enabled_irq_mask
);
3014 ibx_enable_display_interrupt(struct drm_i915_private
*dev_priv
, uint32_t bits
)
3016 ibx_display_interrupt_update(dev_priv
, bits
, bits
);
3019 ibx_disable_display_interrupt(struct drm_i915_private
*dev_priv
, uint32_t bits
)
3021 ibx_display_interrupt_update(dev_priv
, bits
, 0);
3025 int i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
3026 struct drm_file
*file_priv
);
3027 int i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
3028 struct drm_file
*file_priv
);
3029 int i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
3030 struct drm_file
*file_priv
);
3031 int i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
3032 struct drm_file
*file_priv
);
3033 int i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
3034 struct drm_file
*file_priv
);
3035 int i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
3036 struct drm_file
*file_priv
);
3037 int i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
3038 struct drm_file
*file_priv
);
3039 int i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
3040 struct drm_file
*file_priv
);
3041 int i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
3042 struct drm_file
*file_priv
);
3043 int i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
3044 struct drm_file
*file_priv
);
3045 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
3046 struct drm_file
*file
);
3047 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
3048 struct drm_file
*file
);
3049 int i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
3050 struct drm_file
*file_priv
);
3051 int i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
3052 struct drm_file
*file_priv
);
3053 int i915_gem_set_tiling(struct drm_device
*dev
, void *data
,
3054 struct drm_file
*file_priv
);
3055 int i915_gem_get_tiling(struct drm_device
*dev
, void *data
,
3056 struct drm_file
*file_priv
);
3057 void i915_gem_init_userptr(struct drm_i915_private
*dev_priv
);
3058 int i915_gem_userptr_ioctl(struct drm_device
*dev
, void *data
,
3059 struct drm_file
*file
);
3060 int i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
3061 struct drm_file
*file_priv
);
3062 int i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
,
3063 struct drm_file
*file_priv
);
3064 void i915_gem_load_init(struct drm_device
*dev
);
3065 void i915_gem_load_cleanup(struct drm_device
*dev
);
3066 void i915_gem_load_init_fences(struct drm_i915_private
*dev_priv
);
3067 int i915_gem_freeze_late(struct drm_i915_private
*dev_priv
);
3069 void *i915_gem_object_alloc(struct drm_device
*dev
);
3070 void i915_gem_object_free(struct drm_i915_gem_object
*obj
);
3071 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
3072 const struct drm_i915_gem_object_ops
*ops
);
3073 struct drm_i915_gem_object
*i915_gem_object_create(struct drm_device
*dev
,
3075 struct drm_i915_gem_object
*i915_gem_object_create_from_data(
3076 struct drm_device
*dev
, const void *data
, size_t size
);
3077 void i915_gem_close_object(struct drm_gem_object
*gem
, struct drm_file
*file
);
3078 void i915_gem_free_object(struct drm_gem_object
*obj
);
3080 struct i915_vma
* __must_check
3081 i915_gem_object_ggtt_pin(struct drm_i915_gem_object
*obj
,
3082 const struct i915_ggtt_view
*view
,
3087 int i915_vma_bind(struct i915_vma
*vma
, enum i915_cache_level cache_level
,
3089 void __i915_vma_set_map_and_fenceable(struct i915_vma
*vma
);
3090 int __must_check
i915_vma_unbind(struct i915_vma
*vma
);
3091 void i915_vma_close(struct i915_vma
*vma
);
3092 void i915_vma_destroy(struct i915_vma
*vma
);
3094 int i915_gem_object_unbind(struct drm_i915_gem_object
*obj
);
3095 int i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
);
3096 void i915_gem_release_all_mmaps(struct drm_i915_private
*dev_priv
);
3097 void i915_gem_release_mmap(struct drm_i915_gem_object
*obj
);
3099 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object
*obj
,
3100 int *needs_clflush
);
3102 int __must_check
i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
);
3104 static inline int __sg_page_count(struct scatterlist
*sg
)
3106 return sg
->length
>> PAGE_SHIFT
;
3110 i915_gem_object_get_dirty_page(struct drm_i915_gem_object
*obj
, int n
);
3112 static inline dma_addr_t
3113 i915_gem_object_get_dma_address(struct drm_i915_gem_object
*obj
, int n
)
3115 if (n
< obj
->get_page
.last
) {
3116 obj
->get_page
.sg
= obj
->pages
->sgl
;
3117 obj
->get_page
.last
= 0;
3120 while (obj
->get_page
.last
+ __sg_page_count(obj
->get_page
.sg
) <= n
) {
3121 obj
->get_page
.last
+= __sg_page_count(obj
->get_page
.sg
++);
3122 if (unlikely(sg_is_chain(obj
->get_page
.sg
)))
3123 obj
->get_page
.sg
= sg_chain_ptr(obj
->get_page
.sg
);
3126 return sg_dma_address(obj
->get_page
.sg
) + ((n
- obj
->get_page
.last
) << PAGE_SHIFT
);
3129 static inline struct page
*
3130 i915_gem_object_get_page(struct drm_i915_gem_object
*obj
, int n
)
3132 if (WARN_ON(n
>= obj
->base
.size
>> PAGE_SHIFT
))
3135 if (n
< obj
->get_page
.last
) {
3136 obj
->get_page
.sg
= obj
->pages
->sgl
;
3137 obj
->get_page
.last
= 0;
3140 while (obj
->get_page
.last
+ __sg_page_count(obj
->get_page
.sg
) <= n
) {
3141 obj
->get_page
.last
+= __sg_page_count(obj
->get_page
.sg
++);
3142 if (unlikely(sg_is_chain(obj
->get_page
.sg
)))
3143 obj
->get_page
.sg
= sg_chain_ptr(obj
->get_page
.sg
);
3146 return nth_page(sg_page(obj
->get_page
.sg
), n
- obj
->get_page
.last
);
3149 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object
*obj
)
3151 BUG_ON(obj
->pages
== NULL
);
3152 obj
->pages_pin_count
++;
3155 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object
*obj
)
3157 BUG_ON(obj
->pages_pin_count
== 0);
3158 obj
->pages_pin_count
--;
3161 enum i915_map_type
{
3167 * i915_gem_object_pin_map - return a contiguous mapping of the entire object
3168 * @obj - the object to map into kernel address space
3169 * @type - the type of mapping, used to select pgprot_t
3171 * Calls i915_gem_object_pin_pages() to prevent reaping of the object's
3172 * pages and then returns a contiguous mapping of the backing storage into
3173 * the kernel address space. Based on the @type of mapping, the PTE will be
3174 * set to either WriteBack or WriteCombine (via pgprot_t).
3176 * The caller must hold the struct_mutex, and is responsible for calling
3177 * i915_gem_object_unpin_map() when the mapping is no longer required.
3179 * Returns the pointer through which to access the mapped object, or an
3180 * ERR_PTR() on error.
3182 void *__must_check
i915_gem_object_pin_map(struct drm_i915_gem_object
*obj
,
3183 enum i915_map_type type
);
3186 * i915_gem_object_unpin_map - releases an earlier mapping
3187 * @obj - the object to unmap
3189 * After pinning the object and mapping its pages, once you are finished
3190 * with your access, call i915_gem_object_unpin_map() to release the pin
3191 * upon the mapping. Once the pin count reaches zero, that mapping may be
3194 * The caller must hold the struct_mutex.
3196 static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object
*obj
)
3198 lockdep_assert_held(&obj
->base
.dev
->struct_mutex
);
3199 i915_gem_object_unpin_pages(obj
);
3202 int __must_check
i915_mutex_lock_interruptible(struct drm_device
*dev
);
3203 int i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
3204 struct drm_i915_gem_request
*to
);
3205 void i915_vma_move_to_active(struct i915_vma
*vma
,
3206 struct drm_i915_gem_request
*req
,
3207 unsigned int flags
);
3208 int i915_gem_dumb_create(struct drm_file
*file_priv
,
3209 struct drm_device
*dev
,
3210 struct drm_mode_create_dumb
*args
);
3211 int i915_gem_mmap_gtt(struct drm_file
*file_priv
, struct drm_device
*dev
,
3212 uint32_t handle
, uint64_t *offset
);
3214 void i915_gem_track_fb(struct drm_i915_gem_object
*old
,
3215 struct drm_i915_gem_object
*new,
3216 unsigned frontbuffer_bits
);
3218 int __must_check
i915_gem_set_seqno(struct drm_device
*dev
, u32 seqno
);
3220 struct drm_i915_gem_request
*
3221 i915_gem_find_active_request(struct intel_engine_cs
*engine
);
3223 void i915_gem_retire_requests(struct drm_i915_private
*dev_priv
);
3225 static inline u32
i915_reset_counter(struct i915_gpu_error
*error
)
3227 return atomic_read(&error
->reset_counter
);
3230 static inline bool __i915_reset_in_progress(u32 reset
)
3232 return unlikely(reset
& I915_RESET_IN_PROGRESS_FLAG
);
3235 static inline bool __i915_reset_in_progress_or_wedged(u32 reset
)
3237 return unlikely(reset
& (I915_RESET_IN_PROGRESS_FLAG
| I915_WEDGED
));
3240 static inline bool __i915_terminally_wedged(u32 reset
)
3242 return unlikely(reset
& I915_WEDGED
);
3245 static inline bool i915_reset_in_progress(struct i915_gpu_error
*error
)
3247 return __i915_reset_in_progress(i915_reset_counter(error
));
3250 static inline bool i915_reset_in_progress_or_wedged(struct i915_gpu_error
*error
)
3252 return __i915_reset_in_progress_or_wedged(i915_reset_counter(error
));
3255 static inline bool i915_terminally_wedged(struct i915_gpu_error
*error
)
3257 return __i915_terminally_wedged(i915_reset_counter(error
));
3260 static inline u32
i915_reset_count(struct i915_gpu_error
*error
)
3262 return ((i915_reset_counter(error
) & ~I915_WEDGED
) + 1) / 2;
3265 void i915_gem_reset(struct drm_device
*dev
);
3266 bool i915_gem_clflush_object(struct drm_i915_gem_object
*obj
, bool force
);
3267 int __must_check
i915_gem_init(struct drm_device
*dev
);
3268 int __must_check
i915_gem_init_hw(struct drm_device
*dev
);
3269 void i915_gem_init_swizzling(struct drm_device
*dev
);
3270 void i915_gem_cleanup_engines(struct drm_device
*dev
);
3271 int __must_check
i915_gem_wait_for_idle(struct drm_i915_private
*dev_priv
,
3272 bool interruptible
);
3273 int __must_check
i915_gem_suspend(struct drm_device
*dev
);
3274 void i915_gem_resume(struct drm_device
*dev
);
3275 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
);
3277 i915_gem_object_wait_rendering(struct drm_i915_gem_object
*obj
,
3280 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
,
3283 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
);
3284 struct i915_vma
* __must_check
3285 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
3287 const struct i915_ggtt_view
*view
);
3288 void i915_gem_object_unpin_from_display_plane(struct i915_vma
*vma
);
3289 int i915_gem_object_attach_phys(struct drm_i915_gem_object
*obj
,
3291 int i915_gem_open(struct drm_device
*dev
, struct drm_file
*file
);
3292 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
);
3294 u64
i915_gem_get_ggtt_size(struct drm_i915_private
*dev_priv
, u64 size
,
3296 u64
i915_gem_get_ggtt_alignment(struct drm_i915_private
*dev_priv
, u64 size
,
3297 int tiling_mode
, bool fenced
);
3299 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
3300 enum i915_cache_level cache_level
);
3302 struct drm_gem_object
*i915_gem_prime_import(struct drm_device
*dev
,
3303 struct dma_buf
*dma_buf
);
3305 struct dma_buf
*i915_gem_prime_export(struct drm_device
*dev
,
3306 struct drm_gem_object
*gem_obj
, int flags
);
3309 i915_gem_obj_to_vma(struct drm_i915_gem_object
*obj
,
3310 struct i915_address_space
*vm
,
3311 const struct i915_ggtt_view
*view
);
3314 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object
*obj
,
3315 struct i915_address_space
*vm
,
3316 const struct i915_ggtt_view
*view
);
3318 static inline struct i915_hw_ppgtt
*
3319 i915_vm_to_ppgtt(struct i915_address_space
*vm
)
3321 return container_of(vm
, struct i915_hw_ppgtt
, base
);
3324 static inline struct i915_vma
*
3325 i915_gem_object_to_ggtt(struct drm_i915_gem_object
*obj
,
3326 const struct i915_ggtt_view
*view
)
3328 return i915_gem_obj_to_vma(obj
, &to_i915(obj
->base
.dev
)->ggtt
.base
, view
);
3331 static inline unsigned long
3332 i915_gem_object_ggtt_offset(struct drm_i915_gem_object
*o
,
3333 const struct i915_ggtt_view
*view
)
3335 return i915_ggtt_offset(i915_gem_object_to_ggtt(o
, view
));
3338 /* i915_gem_fence.c */
3339 int __must_check
i915_gem_object_get_fence(struct drm_i915_gem_object
*obj
);
3340 int __must_check
i915_gem_object_put_fence(struct drm_i915_gem_object
*obj
);
3342 bool i915_gem_object_pin_fence(struct drm_i915_gem_object
*obj
);
3343 void i915_gem_object_unpin_fence(struct drm_i915_gem_object
*obj
);
3345 void i915_gem_restore_fences(struct drm_device
*dev
);
3347 void i915_gem_detect_bit_6_swizzle(struct drm_device
*dev
);
3348 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
3349 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
3351 /* i915_gem_context.c */
3352 int __must_check
i915_gem_context_init(struct drm_device
*dev
);
3353 void i915_gem_context_lost(struct drm_i915_private
*dev_priv
);
3354 void i915_gem_context_fini(struct drm_device
*dev
);
3355 void i915_gem_context_reset(struct drm_device
*dev
);
3356 int i915_gem_context_open(struct drm_device
*dev
, struct drm_file
*file
);
3357 void i915_gem_context_close(struct drm_device
*dev
, struct drm_file
*file
);
3358 int i915_switch_context(struct drm_i915_gem_request
*req
);
3359 int i915_gem_switch_to_kernel_context(struct drm_i915_private
*dev_priv
);
3360 void i915_gem_context_free(struct kref
*ctx_ref
);
3361 struct drm_i915_gem_object
*
3362 i915_gem_alloc_context_obj(struct drm_device
*dev
, size_t size
);
3363 struct i915_gem_context
*
3364 i915_gem_context_create_gvt(struct drm_device
*dev
);
3366 static inline struct i915_gem_context
*
3367 i915_gem_context_lookup(struct drm_i915_file_private
*file_priv
, u32 id
)
3369 struct i915_gem_context
*ctx
;
3371 lockdep_assert_held(&file_priv
->dev_priv
->drm
.struct_mutex
);
3373 ctx
= idr_find(&file_priv
->context_idr
, id
);
3375 return ERR_PTR(-ENOENT
);
3380 static inline struct i915_gem_context
*
3381 i915_gem_context_get(struct i915_gem_context
*ctx
)
3383 kref_get(&ctx
->ref
);
3387 static inline void i915_gem_context_put(struct i915_gem_context
*ctx
)
3389 lockdep_assert_held(&ctx
->i915
->drm
.struct_mutex
);
3390 kref_put(&ctx
->ref
, i915_gem_context_free
);
3393 static inline bool i915_gem_context_is_default(const struct i915_gem_context
*c
)
3395 return c
->user_handle
== DEFAULT_CONTEXT_HANDLE
;
3398 int i915_gem_context_create_ioctl(struct drm_device
*dev
, void *data
,
3399 struct drm_file
*file
);
3400 int i915_gem_context_destroy_ioctl(struct drm_device
*dev
, void *data
,
3401 struct drm_file
*file
);
3402 int i915_gem_context_getparam_ioctl(struct drm_device
*dev
, void *data
,
3403 struct drm_file
*file_priv
);
3404 int i915_gem_context_setparam_ioctl(struct drm_device
*dev
, void *data
,
3405 struct drm_file
*file_priv
);
3406 int i915_gem_context_reset_stats_ioctl(struct drm_device
*dev
, void *data
,
3407 struct drm_file
*file
);
3409 /* i915_gem_evict.c */
3410 int __must_check
i915_gem_evict_something(struct i915_address_space
*vm
,
3411 u64 min_size
, u64 alignment
,
3412 unsigned cache_level
,
3415 int __must_check
i915_gem_evict_for_vma(struct i915_vma
*target
);
3416 int i915_gem_evict_vm(struct i915_address_space
*vm
, bool do_idle
);
3418 /* belongs in i915_gem_gtt.h */
3419 static inline void i915_gem_chipset_flush(struct drm_i915_private
*dev_priv
)
3421 if (INTEL_GEN(dev_priv
) < 6)
3422 intel_gtt_chipset_flush();
3425 /* i915_gem_stolen.c */
3426 int i915_gem_stolen_insert_node(struct drm_i915_private
*dev_priv
,
3427 struct drm_mm_node
*node
, u64 size
,
3428 unsigned alignment
);
3429 int i915_gem_stolen_insert_node_in_range(struct drm_i915_private
*dev_priv
,
3430 struct drm_mm_node
*node
, u64 size
,
3431 unsigned alignment
, u64 start
,
3433 void i915_gem_stolen_remove_node(struct drm_i915_private
*dev_priv
,
3434 struct drm_mm_node
*node
);
3435 int i915_gem_init_stolen(struct drm_device
*dev
);
3436 void i915_gem_cleanup_stolen(struct drm_device
*dev
);
3437 struct drm_i915_gem_object
*
3438 i915_gem_object_create_stolen(struct drm_device
*dev
, u32 size
);
3439 struct drm_i915_gem_object
*
3440 i915_gem_object_create_stolen_for_preallocated(struct drm_device
*dev
,
3445 /* i915_gem_shrinker.c */
3446 unsigned long i915_gem_shrink(struct drm_i915_private
*dev_priv
,
3447 unsigned long target
,
3449 #define I915_SHRINK_PURGEABLE 0x1
3450 #define I915_SHRINK_UNBOUND 0x2
3451 #define I915_SHRINK_BOUND 0x4
3452 #define I915_SHRINK_ACTIVE 0x8
3453 #define I915_SHRINK_VMAPS 0x10
3454 unsigned long i915_gem_shrink_all(struct drm_i915_private
*dev_priv
);
3455 void i915_gem_shrinker_init(struct drm_i915_private
*dev_priv
);
3456 void i915_gem_shrinker_cleanup(struct drm_i915_private
*dev_priv
);
3459 /* i915_gem_tiling.c */
3460 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object
*obj
)
3462 struct drm_i915_private
*dev_priv
= to_i915(obj
->base
.dev
);
3464 return dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_9_10_17
&&
3465 i915_gem_object_is_tiled(obj
);
3468 /* i915_debugfs.c */
3469 #ifdef CONFIG_DEBUG_FS
3470 int i915_debugfs_register(struct drm_i915_private
*dev_priv
);
3471 void i915_debugfs_unregister(struct drm_i915_private
*dev_priv
);
3472 int i915_debugfs_connector_add(struct drm_connector
*connector
);
3473 void intel_display_crc_init(struct drm_device
*dev
);
3475 static inline int i915_debugfs_register(struct drm_i915_private
*dev_priv
) {return 0;}
3476 static inline void i915_debugfs_unregister(struct drm_i915_private
*dev_priv
) {}
3477 static inline int i915_debugfs_connector_add(struct drm_connector
*connector
)
3479 static inline void intel_display_crc_init(struct drm_device
*dev
) {}
3482 /* i915_gpu_error.c */
3484 void i915_error_printf(struct drm_i915_error_state_buf
*e
, const char *f
, ...);
3485 int i915_error_state_to_str(struct drm_i915_error_state_buf
*estr
,
3486 const struct i915_error_state_file_priv
*error
);
3487 int i915_error_state_buf_init(struct drm_i915_error_state_buf
*eb
,
3488 struct drm_i915_private
*i915
,
3489 size_t count
, loff_t pos
);
3490 static inline void i915_error_state_buf_release(
3491 struct drm_i915_error_state_buf
*eb
)
3495 void i915_capture_error_state(struct drm_i915_private
*dev_priv
,
3497 const char *error_msg
);
3498 void i915_error_state_get(struct drm_device
*dev
,
3499 struct i915_error_state_file_priv
*error_priv
);
3500 void i915_error_state_put(struct i915_error_state_file_priv
*error_priv
);
3501 void i915_destroy_error_state(struct drm_device
*dev
);
3503 void i915_get_extra_instdone(struct drm_i915_private
*dev_priv
, uint32_t *instdone
);
3504 const char *i915_cache_level_str(struct drm_i915_private
*i915
, int type
);
3506 /* i915_cmd_parser.c */
3507 int i915_cmd_parser_get_version(struct drm_i915_private
*dev_priv
);
3508 int intel_engine_init_cmd_parser(struct intel_engine_cs
*engine
);
3509 void intel_engine_cleanup_cmd_parser(struct intel_engine_cs
*engine
);
3510 bool intel_engine_needs_cmd_parser(struct intel_engine_cs
*engine
);
3511 int intel_engine_cmd_parser(struct intel_engine_cs
*engine
,
3512 struct drm_i915_gem_object
*batch_obj
,
3513 struct drm_i915_gem_object
*shadow_batch_obj
,
3514 u32 batch_start_offset
,
3518 /* i915_suspend.c */
3519 extern int i915_save_state(struct drm_device
*dev
);
3520 extern int i915_restore_state(struct drm_device
*dev
);
3523 void i915_setup_sysfs(struct drm_device
*dev_priv
);
3524 void i915_teardown_sysfs(struct drm_device
*dev_priv
);
3527 extern int intel_setup_gmbus(struct drm_device
*dev
);
3528 extern void intel_teardown_gmbus(struct drm_device
*dev
);
3529 extern bool intel_gmbus_is_valid_pin(struct drm_i915_private
*dev_priv
,
3532 extern struct i2c_adapter
*
3533 intel_gmbus_get_adapter(struct drm_i915_private
*dev_priv
, unsigned int pin
);
3534 extern void intel_gmbus_set_speed(struct i2c_adapter
*adapter
, int speed
);
3535 extern void intel_gmbus_force_bit(struct i2c_adapter
*adapter
, bool force_bit
);
3536 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter
*adapter
)
3538 return container_of(adapter
, struct intel_gmbus
, adapter
)->force_bit
;
3540 extern void intel_i2c_reset(struct drm_device
*dev
);
3543 int intel_bios_init(struct drm_i915_private
*dev_priv
);
3544 bool intel_bios_is_valid_vbt(const void *buf
, size_t size
);
3545 bool intel_bios_is_tv_present(struct drm_i915_private
*dev_priv
);
3546 bool intel_bios_is_lvds_present(struct drm_i915_private
*dev_priv
, u8
*i2c_pin
);
3547 bool intel_bios_is_port_present(struct drm_i915_private
*dev_priv
, enum port port
);
3548 bool intel_bios_is_port_edp(struct drm_i915_private
*dev_priv
, enum port port
);
3549 bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private
*dev_priv
, enum port port
);
3550 bool intel_bios_is_dsi_present(struct drm_i915_private
*dev_priv
, enum port
*port
);
3551 bool intel_bios_is_port_hpd_inverted(struct drm_i915_private
*dev_priv
,
3554 /* intel_opregion.c */
3556 extern int intel_opregion_setup(struct drm_i915_private
*dev_priv
);
3557 extern void intel_opregion_register(struct drm_i915_private
*dev_priv
);
3558 extern void intel_opregion_unregister(struct drm_i915_private
*dev_priv
);
3559 extern void intel_opregion_asle_intr(struct drm_i915_private
*dev_priv
);
3560 extern int intel_opregion_notify_encoder(struct intel_encoder
*intel_encoder
,
3562 extern int intel_opregion_notify_adapter(struct drm_i915_private
*dev_priv
,
3564 extern int intel_opregion_get_panel_type(struct drm_i915_private
*dev_priv
);
3566 static inline int intel_opregion_setup(struct drm_i915_private
*dev
) { return 0; }
3567 static inline void intel_opregion_register(struct drm_i915_private
*dev_priv
) { }
3568 static inline void intel_opregion_unregister(struct drm_i915_private
*dev_priv
) { }
3569 static inline void intel_opregion_asle_intr(struct drm_i915_private
*dev_priv
)
3573 intel_opregion_notify_encoder(struct intel_encoder
*intel_encoder
, bool enable
)
3578 intel_opregion_notify_adapter(struct drm_i915_private
*dev
, pci_power_t state
)
3582 static inline int intel_opregion_get_panel_type(struct drm_i915_private
*dev
)
3590 extern void intel_register_dsm_handler(void);
3591 extern void intel_unregister_dsm_handler(void);
3593 static inline void intel_register_dsm_handler(void) { return; }
3594 static inline void intel_unregister_dsm_handler(void) { return; }
3595 #endif /* CONFIG_ACPI */
3597 /* intel_device_info.c */
3598 static inline struct intel_device_info
*
3599 mkwrite_device_info(struct drm_i915_private
*dev_priv
)
3601 return (struct intel_device_info
*)&dev_priv
->info
;
3604 void intel_device_info_runtime_init(struct drm_i915_private
*dev_priv
);
3605 void intel_device_info_dump(struct drm_i915_private
*dev_priv
);
3608 extern void intel_modeset_init_hw(struct drm_device
*dev
);
3609 extern void intel_modeset_init(struct drm_device
*dev
);
3610 extern void intel_modeset_gem_init(struct drm_device
*dev
);
3611 extern void intel_modeset_cleanup(struct drm_device
*dev
);
3612 extern int intel_connector_register(struct drm_connector
*);
3613 extern void intel_connector_unregister(struct drm_connector
*);
3614 extern int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
);
3615 extern void intel_display_resume(struct drm_device
*dev
);
3616 extern void i915_redisable_vga(struct drm_device
*dev
);
3617 extern void i915_redisable_vga_power_on(struct drm_device
*dev
);
3618 extern bool ironlake_set_drps(struct drm_i915_private
*dev_priv
, u8 val
);
3619 extern void intel_init_pch_refclk(struct drm_device
*dev
);
3620 extern void intel_set_rps(struct drm_i915_private
*dev_priv
, u8 val
);
3621 extern void intel_set_memory_cxsr(struct drm_i915_private
*dev_priv
,
3624 int i915_reg_read_ioctl(struct drm_device
*dev
, void *data
,
3625 struct drm_file
*file
);
3628 extern struct intel_overlay_error_state
*
3629 intel_overlay_capture_error_state(struct drm_i915_private
*dev_priv
);
3630 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf
*e
,
3631 struct intel_overlay_error_state
*error
);
3633 extern struct intel_display_error_state
*
3634 intel_display_capture_error_state(struct drm_i915_private
*dev_priv
);
3635 extern void intel_display_print_error_state(struct drm_i915_error_state_buf
*e
,
3636 struct drm_device
*dev
,
3637 struct intel_display_error_state
*error
);
3639 int sandybridge_pcode_read(struct drm_i915_private
*dev_priv
, u32 mbox
, u32
*val
);
3640 int sandybridge_pcode_write(struct drm_i915_private
*dev_priv
, u32 mbox
, u32 val
);
3642 /* intel_sideband.c */
3643 u32
vlv_punit_read(struct drm_i915_private
*dev_priv
, u32 addr
);
3644 void vlv_punit_write(struct drm_i915_private
*dev_priv
, u32 addr
, u32 val
);
3645 u32
vlv_nc_read(struct drm_i915_private
*dev_priv
, u8 addr
);
3646 u32
vlv_iosf_sb_read(struct drm_i915_private
*dev_priv
, u8 port
, u32 reg
);
3647 void vlv_iosf_sb_write(struct drm_i915_private
*dev_priv
, u8 port
, u32 reg
, u32 val
);
3648 u32
vlv_cck_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3649 void vlv_cck_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3650 u32
vlv_ccu_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3651 void vlv_ccu_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3652 u32
vlv_bunit_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3653 void vlv_bunit_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3654 u32
vlv_dpio_read(struct drm_i915_private
*dev_priv
, enum pipe pipe
, int reg
);
3655 void vlv_dpio_write(struct drm_i915_private
*dev_priv
, enum pipe pipe
, int reg
, u32 val
);
3656 u32
intel_sbi_read(struct drm_i915_private
*dev_priv
, u16 reg
,
3657 enum intel_sbi_destination destination
);
3658 void intel_sbi_write(struct drm_i915_private
*dev_priv
, u16 reg
, u32 value
,
3659 enum intel_sbi_destination destination
);
3660 u32
vlv_flisdsi_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3661 void vlv_flisdsi_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3663 /* intel_dpio_phy.c */
3664 void chv_set_phy_signal_level(struct intel_encoder
*encoder
,
3665 u32 deemph_reg_value
, u32 margin_reg_value
,
3666 bool uniq_trans_scale
);
3667 void chv_data_lane_soft_reset(struct intel_encoder
*encoder
,
3669 void chv_phy_pre_pll_enable(struct intel_encoder
*encoder
);
3670 void chv_phy_pre_encoder_enable(struct intel_encoder
*encoder
);
3671 void chv_phy_release_cl2_override(struct intel_encoder
*encoder
);
3672 void chv_phy_post_pll_disable(struct intel_encoder
*encoder
);
3674 void vlv_set_phy_signal_level(struct intel_encoder
*encoder
,
3675 u32 demph_reg_value
, u32 preemph_reg_value
,
3676 u32 uniqtranscale_reg_value
, u32 tx3_demph
);
3677 void vlv_phy_pre_pll_enable(struct intel_encoder
*encoder
);
3678 void vlv_phy_pre_encoder_enable(struct intel_encoder
*encoder
);
3679 void vlv_phy_reset_lanes(struct intel_encoder
*encoder
);
3681 int intel_gpu_freq(struct drm_i915_private
*dev_priv
, int val
);
3682 int intel_freq_opcode(struct drm_i915_private
*dev_priv
, int val
);
3684 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3685 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3687 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3688 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3689 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3690 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
3692 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3693 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3694 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3695 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3697 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
3698 * will be implemented using 2 32-bit writes in an arbitrary order with
3699 * an arbitrary delay between them. This can cause the hardware to
3700 * act upon the intermediate value, possibly leading to corruption and
3701 * machine death. You have been warned.
3703 #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
3704 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3706 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
3707 u32 upper, lower, old_upper, loop = 0; \
3708 upper = I915_READ(upper_reg); \
3710 old_upper = upper; \
3711 lower = I915_READ(lower_reg); \
3712 upper = I915_READ(upper_reg); \
3713 } while (upper != old_upper && loop++ < 2); \
3714 (u64)upper << 32 | lower; })
3716 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3717 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
3719 #define __raw_read(x, s) \
3720 static inline uint##x##_t __raw_i915_read##x(struct drm_i915_private *dev_priv, \
3723 return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
3726 #define __raw_write(x, s) \
3727 static inline void __raw_i915_write##x(struct drm_i915_private *dev_priv, \
3728 i915_reg_t reg, uint##x##_t val) \
3730 write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
3745 /* These are untraced mmio-accessors that are only valid to be used inside
3746 * criticial sections inside IRQ handlers where forcewake is explicitly
3748 * Think twice, and think again, before using these.
3749 * Note: Should only be used between intel_uncore_forcewake_irqlock() and
3750 * intel_uncore_forcewake_irqunlock().
3752 #define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
3753 #define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
3754 #define I915_WRITE64_FW(reg__, val__) __raw_i915_write64(dev_priv, (reg__), (val__))
3755 #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
3757 /* "Broadcast RGB" property */
3758 #define INTEL_BROADCAST_RGB_AUTO 0
3759 #define INTEL_BROADCAST_RGB_FULL 1
3760 #define INTEL_BROADCAST_RGB_LIMITED 2
3762 static inline i915_reg_t
i915_vgacntrl_reg(struct drm_device
*dev
)
3764 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
))
3765 return VLV_VGACNTRL
;
3766 else if (INTEL_INFO(dev
)->gen
>= 5)
3767 return CPU_VGACNTRL
;
3772 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m
)
3774 unsigned long j
= msecs_to_jiffies(m
);
3776 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);
3779 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n
)
3781 return min_t(u64
, MAX_JIFFY_OFFSET
, nsecs_to_jiffies64(n
) + 1);
3784 static inline unsigned long
3785 timespec_to_jiffies_timeout(const struct timespec
*value
)
3787 unsigned long j
= timespec_to_jiffies(value
);
3789 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);
3793 * If you need to wait X milliseconds between events A and B, but event B
3794 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
3795 * when event A happened, then just before event B you call this function and
3796 * pass the timestamp as the first argument, and X as the second argument.
3799 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies
, int to_wait_ms
)
3801 unsigned long target_jiffies
, tmp_jiffies
, remaining_jiffies
;
3804 * Don't re-read the value of "jiffies" every time since it may change
3805 * behind our back and break the math.
3807 tmp_jiffies
= jiffies
;
3808 target_jiffies
= timestamp_jiffies
+
3809 msecs_to_jiffies_timeout(to_wait_ms
);
3811 if (time_after(target_jiffies
, tmp_jiffies
)) {
3812 remaining_jiffies
= target_jiffies
- tmp_jiffies
;
3813 while (remaining_jiffies
)
3815 schedule_timeout_uninterruptible(remaining_jiffies
);
3818 static inline bool __i915_request_irq_complete(struct drm_i915_gem_request
*req
)
3820 struct intel_engine_cs
*engine
= req
->engine
;
3822 /* Before we do the heavier coherent read of the seqno,
3823 * check the value (hopefully) in the CPU cacheline.
3825 if (i915_gem_request_completed(req
))
3828 /* Ensure our read of the seqno is coherent so that we
3829 * do not "miss an interrupt" (i.e. if this is the last
3830 * request and the seqno write from the GPU is not visible
3831 * by the time the interrupt fires, we will see that the
3832 * request is incomplete and go back to sleep awaiting
3833 * another interrupt that will never come.)
3835 * Strictly, we only need to do this once after an interrupt,
3836 * but it is easier and safer to do it every time the waiter
3839 if (engine
->irq_seqno_barrier
&&
3840 rcu_access_pointer(engine
->breadcrumbs
.irq_seqno_bh
) == current
&&
3841 cmpxchg_relaxed(&engine
->breadcrumbs
.irq_posted
, 1, 0)) {
3842 struct task_struct
*tsk
;
3844 /* The ordering of irq_posted versus applying the barrier
3845 * is crucial. The clearing of the current irq_posted must
3846 * be visible before we perform the barrier operation,
3847 * such that if a subsequent interrupt arrives, irq_posted
3848 * is reasserted and our task rewoken (which causes us to
3849 * do another __i915_request_irq_complete() immediately
3850 * and reapply the barrier). Conversely, if the clear
3851 * occurs after the barrier, then an interrupt that arrived
3852 * whilst we waited on the barrier would not trigger a
3853 * barrier on the next pass, and the read may not see the
3856 engine
->irq_seqno_barrier(engine
);
3858 /* If we consume the irq, but we are no longer the bottom-half,
3859 * the real bottom-half may not have serialised their own
3860 * seqno check with the irq-barrier (i.e. may have inspected
3861 * the seqno before we believe it coherent since they see
3862 * irq_posted == false but we are still running).
3865 tsk
= rcu_dereference(engine
->breadcrumbs
.irq_seqno_bh
);
3866 if (tsk
&& tsk
!= current
)
3867 /* Note that if the bottom-half is changed as we
3868 * are sending the wake-up, the new bottom-half will
3869 * be woken by whomever made the change. We only have
3870 * to worry about when we steal the irq-posted for
3873 wake_up_process(tsk
);
3876 if (i915_gem_request_completed(req
))
3880 /* We need to check whether any gpu reset happened in between
3881 * the request being submitted and now. If a reset has occurred,
3882 * the seqno will have been advance past ours and our request
3883 * is complete. If we are in the process of handling a reset,
3884 * the request is effectively complete as the rendering will
3885 * be discarded, but we need to return in order to drop the
3888 if (i915_reset_in_progress(&req
->i915
->gpu_error
))
3894 void i915_memcpy_init_early(struct drm_i915_private
*dev_priv
);
3895 bool i915_memcpy_from_wc(void *dst
, const void *src
, unsigned long len
);
3897 #define ptr_unpack_bits(ptr, bits) ({ \
3898 unsigned long __v = (unsigned long)(ptr); \
3899 (bits) = __v & ~PAGE_MASK; \
3900 (typeof(ptr))(__v & PAGE_MASK); \
3903 #define ptr_pack_bits(ptr, bits) \
3904 ((typeof(ptr))((unsigned long)(ptr) | (bits)))
3906 #define fetch_and_zero(ptr) ({ \
3907 typeof(*ptr) __T = *(ptr); \
3908 *(ptr) = (typeof(*ptr))0; \