1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
36 #include "intel_bios.h"
37 #include "intel_ringbuffer.h"
38 #include "intel_lrc.h"
39 #include "i915_gem_gtt.h"
40 #include "i915_gem_render_state.h"
41 #include <linux/io-mapping.h>
42 #include <linux/i2c.h>
43 #include <linux/i2c-algo-bit.h>
44 #include <drm/intel-gtt.h>
45 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
46 #include <drm/drm_gem.h>
47 #include <linux/backlight.h>
48 #include <linux/hashtable.h>
49 #include <linux/intel-iommu.h>
50 #include <linux/kref.h>
51 #include <linux/pm_qos.h>
53 /* General customization:
56 #define DRIVER_NAME "i915"
57 #define DRIVER_DESC "Intel Graphics"
58 #define DRIVER_DATE "20141024"
61 #define WARN_ON(x) WARN(x, "WARN_ON(" #x ")")
69 I915_MAX_PIPES
= _PIPE_EDP
71 #define pipe_name(p) ((p) + 'A')
80 #define transcoder_name(t) ((t) + 'A')
83 * This is the maximum (across all platforms) number of planes (primary +
84 * sprites) that can be active at the same time on one pipe.
86 * This value doesn't count the cursor plane.
88 #define I915_MAX_PLANES 3
95 #define plane_name(p) ((p) + 'A')
97 #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
107 #define port_name(p) ((p) + 'A')
109 #define I915_NUM_PHYS_VLV 2
121 enum intel_display_power_domain
{
125 POWER_DOMAIN_PIPE_A_PANEL_FITTER
,
126 POWER_DOMAIN_PIPE_B_PANEL_FITTER
,
127 POWER_DOMAIN_PIPE_C_PANEL_FITTER
,
128 POWER_DOMAIN_TRANSCODER_A
,
129 POWER_DOMAIN_TRANSCODER_B
,
130 POWER_DOMAIN_TRANSCODER_C
,
131 POWER_DOMAIN_TRANSCODER_EDP
,
132 POWER_DOMAIN_PORT_DDI_A_2_LANES
,
133 POWER_DOMAIN_PORT_DDI_A_4_LANES
,
134 POWER_DOMAIN_PORT_DDI_B_2_LANES
,
135 POWER_DOMAIN_PORT_DDI_B_4_LANES
,
136 POWER_DOMAIN_PORT_DDI_C_2_LANES
,
137 POWER_DOMAIN_PORT_DDI_C_4_LANES
,
138 POWER_DOMAIN_PORT_DDI_D_2_LANES
,
139 POWER_DOMAIN_PORT_DDI_D_4_LANES
,
140 POWER_DOMAIN_PORT_DSI
,
141 POWER_DOMAIN_PORT_CRT
,
142 POWER_DOMAIN_PORT_OTHER
,
151 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
152 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
153 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
154 #define POWER_DOMAIN_TRANSCODER(tran) \
155 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
156 (tran) + POWER_DOMAIN_TRANSCODER_A)
160 HPD_PORT_A
= HPD_NONE
, /* PORT_A is internal */
161 HPD_TV
= HPD_NONE
, /* TV is known to be unreliable */
171 #define I915_GEM_GPU_DOMAINS \
172 (I915_GEM_DOMAIN_RENDER | \
173 I915_GEM_DOMAIN_SAMPLER | \
174 I915_GEM_DOMAIN_COMMAND | \
175 I915_GEM_DOMAIN_INSTRUCTION | \
176 I915_GEM_DOMAIN_VERTEX)
178 #define for_each_pipe(__dev_priv, __p) \
179 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
180 #define for_each_plane(pipe, p) \
181 for ((p) = 0; (p) < INTEL_INFO(dev)->num_sprites[(pipe)] + 1; (p)++)
182 #define for_each_sprite(p, s) for ((s) = 0; (s) < INTEL_INFO(dev)->num_sprites[(p)]; (s)++)
184 #define for_each_crtc(dev, crtc) \
185 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
187 #define for_each_intel_crtc(dev, intel_crtc) \
188 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)
190 #define for_each_intel_encoder(dev, intel_encoder) \
191 list_for_each_entry(intel_encoder, \
192 &(dev)->mode_config.encoder_list, \
195 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
196 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
197 if ((intel_encoder)->base.crtc == (__crtc))
199 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
200 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
201 if ((intel_connector)->base.encoder == (__encoder))
203 #define for_each_power_domain(domain, mask) \
204 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
205 if ((1 << (domain)) & (mask))
207 struct drm_i915_private
;
208 struct i915_mm_struct
;
209 struct i915_mmu_object
;
212 DPLL_ID_PRIVATE
= -1, /* non-shared dpll in use */
213 /* real shared dpll ids must be >= 0 */
214 DPLL_ID_PCH_PLL_A
= 0,
215 DPLL_ID_PCH_PLL_B
= 1,
219 #define I915_NUM_PLLS 2
221 struct intel_dpll_hw_state
{
232 struct intel_shared_dpll
{
233 int refcount
; /* count of number of CRTCs sharing this PLL */
234 int active
; /* count of number of active CRTCs (i.e. DPMS on) */
235 bool on
; /* is the PLL actually active? Disabled during modeset */
237 /* should match the index in the dev_priv->shared_dplls array */
238 enum intel_dpll_id id
;
239 struct intel_dpll_hw_state hw_state
;
240 /* The mode_set hook is optional and should be used together with the
241 * intel_prepare_shared_dpll function. */
242 void (*mode_set
)(struct drm_i915_private
*dev_priv
,
243 struct intel_shared_dpll
*pll
);
244 void (*enable
)(struct drm_i915_private
*dev_priv
,
245 struct intel_shared_dpll
*pll
);
246 void (*disable
)(struct drm_i915_private
*dev_priv
,
247 struct intel_shared_dpll
*pll
);
248 bool (*get_hw_state
)(struct drm_i915_private
*dev_priv
,
249 struct intel_shared_dpll
*pll
,
250 struct intel_dpll_hw_state
*hw_state
);
253 /* Used by dp and fdi links */
254 struct intel_link_m_n
{
262 void intel_link_compute_m_n(int bpp
, int nlanes
,
263 int pixel_clock
, int link_clock
,
264 struct intel_link_m_n
*m_n
);
266 /* Interface history:
269 * 1.2: Add Power Management
270 * 1.3: Add vblank support
271 * 1.4: Fix cmdbuffer path, add heap destroy
272 * 1.5: Add vblank pipe configuration
273 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
274 * - Support vertical blank on secondary display pipe
276 #define DRIVER_MAJOR 1
277 #define DRIVER_MINOR 6
278 #define DRIVER_PATCHLEVEL 0
280 #define WATCH_LISTS 0
283 struct opregion_header
;
284 struct opregion_acpi
;
285 struct opregion_swsci
;
286 struct opregion_asle
;
288 struct intel_opregion
{
289 struct opregion_header __iomem
*header
;
290 struct opregion_acpi __iomem
*acpi
;
291 struct opregion_swsci __iomem
*swsci
;
292 u32 swsci_gbda_sub_functions
;
293 u32 swsci_sbcb_sub_functions
;
294 struct opregion_asle __iomem
*asle
;
296 u32 __iomem
*lid_state
;
297 struct work_struct asle_work
;
299 #define OPREGION_SIZE (8*1024)
301 struct intel_overlay
;
302 struct intel_overlay_error_state
;
304 struct drm_local_map
;
306 struct drm_i915_master_private
{
307 struct drm_local_map
*sarea
;
308 struct _drm_i915_sarea
*sarea_priv
;
310 #define I915_FENCE_REG_NONE -1
311 #define I915_MAX_NUM_FENCES 32
312 /* 32 fences + sign bit for FENCE_REG_NONE */
313 #define I915_MAX_NUM_FENCE_BITS 6
315 struct drm_i915_fence_reg
{
316 struct list_head lru_list
;
317 struct drm_i915_gem_object
*obj
;
321 struct sdvo_device_mapping
{
330 struct intel_display_error_state
;
332 struct drm_i915_error_state
{
340 /* Generic register state */
348 u32 error
; /* gen6+ */
349 u32 err_int
; /* gen7 */
355 u32 extra_instdone
[I915_NUM_INSTDONE_REG
];
356 u64 fence
[I915_MAX_NUM_FENCES
];
357 struct intel_overlay_error_state
*overlay
;
358 struct intel_display_error_state
*display
;
359 struct drm_i915_error_object
*semaphore_obj
;
361 struct drm_i915_error_ring
{
363 /* Software tracked state */
366 enum intel_ring_hangcheck_action hangcheck_action
;
369 /* our own tracking of ring head and tail */
373 u32 semaphore_seqno
[I915_NUM_RINGS
- 1];
391 u32 rc_psmi
; /* sleep state */
392 u32 semaphore_mboxes
[I915_NUM_RINGS
- 1];
394 struct drm_i915_error_object
{
398 } *ringbuffer
, *batchbuffer
, *wa_batchbuffer
, *ctx
, *hws_page
;
400 struct drm_i915_error_request
{
415 char comm
[TASK_COMM_LEN
];
416 } ring
[I915_NUM_RINGS
];
418 struct drm_i915_error_buffer
{
425 s32 fence_reg
:I915_MAX_NUM_FENCE_BITS
;
433 } **active_bo
, **pinned_bo
;
435 u32
*active_bo_count
, *pinned_bo_count
;
439 struct intel_connector
;
440 struct intel_encoder
;
441 struct intel_crtc_config
;
442 struct intel_plane_config
;
447 struct drm_i915_display_funcs
{
448 bool (*fbc_enabled
)(struct drm_device
*dev
);
449 void (*enable_fbc
)(struct drm_crtc
*crtc
);
450 void (*disable_fbc
)(struct drm_device
*dev
);
451 int (*get_display_clock_speed
)(struct drm_device
*dev
);
452 int (*get_fifo_size
)(struct drm_device
*dev
, int plane
);
454 * find_dpll() - Find the best values for the PLL
455 * @limit: limits for the PLL
456 * @crtc: current CRTC
457 * @target: target frequency in kHz
458 * @refclk: reference clock frequency in kHz
459 * @match_clock: if provided, @best_clock P divider must
460 * match the P divider from @match_clock
461 * used for LVDS downclocking
462 * @best_clock: best PLL values found
464 * Returns true on success, false on failure.
466 bool (*find_dpll
)(const struct intel_limit
*limit
,
467 struct intel_crtc
*crtc
,
468 int target
, int refclk
,
469 struct dpll
*match_clock
,
470 struct dpll
*best_clock
);
471 void (*update_wm
)(struct drm_crtc
*crtc
);
472 void (*update_sprite_wm
)(struct drm_plane
*plane
,
473 struct drm_crtc
*crtc
,
474 uint32_t sprite_width
, uint32_t sprite_height
,
475 int pixel_size
, bool enable
, bool scaled
);
476 void (*modeset_global_resources
)(struct drm_device
*dev
);
477 /* Returns the active state of the crtc, and if the crtc is active,
478 * fills out the pipe-config with the hw state. */
479 bool (*get_pipe_config
)(struct intel_crtc
*,
480 struct intel_crtc_config
*);
481 void (*get_plane_config
)(struct intel_crtc
*,
482 struct intel_plane_config
*);
483 int (*crtc_mode_set
)(struct intel_crtc
*crtc
,
485 struct drm_framebuffer
*old_fb
);
486 void (*crtc_enable
)(struct drm_crtc
*crtc
);
487 void (*crtc_disable
)(struct drm_crtc
*crtc
);
488 void (*off
)(struct drm_crtc
*crtc
);
489 void (*audio_codec_enable
)(struct drm_connector
*connector
,
490 struct intel_encoder
*encoder
,
491 struct drm_display_mode
*mode
);
492 void (*audio_codec_disable
)(struct intel_encoder
*encoder
);
493 void (*fdi_link_train
)(struct drm_crtc
*crtc
);
494 void (*init_clock_gating
)(struct drm_device
*dev
);
495 int (*queue_flip
)(struct drm_device
*dev
, struct drm_crtc
*crtc
,
496 struct drm_framebuffer
*fb
,
497 struct drm_i915_gem_object
*obj
,
498 struct intel_engine_cs
*ring
,
500 void (*update_primary_plane
)(struct drm_crtc
*crtc
,
501 struct drm_framebuffer
*fb
,
503 void (*hpd_irq_setup
)(struct drm_device
*dev
);
504 /* clock updates for mode set */
506 /* render clock increase/decrease */
507 /* display clock increase/decrease */
508 /* pll clock increase/decrease */
510 int (*setup_backlight
)(struct intel_connector
*connector
);
511 uint32_t (*get_backlight
)(struct intel_connector
*connector
);
512 void (*set_backlight
)(struct intel_connector
*connector
,
514 void (*disable_backlight
)(struct intel_connector
*connector
);
515 void (*enable_backlight
)(struct intel_connector
*connector
);
518 struct intel_uncore_funcs
{
519 void (*force_wake_get
)(struct drm_i915_private
*dev_priv
,
521 void (*force_wake_put
)(struct drm_i915_private
*dev_priv
,
524 uint8_t (*mmio_readb
)(struct drm_i915_private
*dev_priv
, off_t offset
, bool trace
);
525 uint16_t (*mmio_readw
)(struct drm_i915_private
*dev_priv
, off_t offset
, bool trace
);
526 uint32_t (*mmio_readl
)(struct drm_i915_private
*dev_priv
, off_t offset
, bool trace
);
527 uint64_t (*mmio_readq
)(struct drm_i915_private
*dev_priv
, off_t offset
, bool trace
);
529 void (*mmio_writeb
)(struct drm_i915_private
*dev_priv
, off_t offset
,
530 uint8_t val
, bool trace
);
531 void (*mmio_writew
)(struct drm_i915_private
*dev_priv
, off_t offset
,
532 uint16_t val
, bool trace
);
533 void (*mmio_writel
)(struct drm_i915_private
*dev_priv
, off_t offset
,
534 uint32_t val
, bool trace
);
535 void (*mmio_writeq
)(struct drm_i915_private
*dev_priv
, off_t offset
,
536 uint64_t val
, bool trace
);
539 struct intel_uncore
{
540 spinlock_t lock
; /** lock is also taken in irq contexts. */
542 struct intel_uncore_funcs funcs
;
545 unsigned forcewake_count
;
547 unsigned fw_rendercount
;
548 unsigned fw_mediacount
;
550 struct timer_list force_wake_timer
;
553 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
554 func(is_mobile) sep \
557 func(is_i945gm) sep \
559 func(need_gfx_hws) sep \
561 func(is_pineview) sep \
562 func(is_broadwater) sep \
563 func(is_crestline) sep \
564 func(is_ivybridge) sep \
565 func(is_valleyview) sep \
566 func(is_haswell) sep \
567 func(is_skylake) sep \
568 func(is_preliminary) sep \
570 func(has_pipe_cxsr) sep \
571 func(has_hotplug) sep \
572 func(cursor_needs_physical) sep \
573 func(has_overlay) sep \
574 func(overlay_needs_physical) sep \
575 func(supports_tv) sep \
580 #define DEFINE_FLAG(name) u8 name:1
581 #define SEP_SEMICOLON ;
583 struct intel_device_info
{
584 u32 display_mmio_offset
;
587 u8 num_sprites
[I915_MAX_PIPES
];
589 u8 ring_mask
; /* Rings supported by the HW */
590 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG
, SEP_SEMICOLON
);
591 /* Register offsets for the various display pipes and transcoders */
592 int pipe_offsets
[I915_MAX_TRANSCODERS
];
593 int trans_offsets
[I915_MAX_TRANSCODERS
];
594 int palette_offsets
[I915_MAX_PIPES
];
595 int cursor_offsets
[I915_MAX_PIPES
];
601 enum i915_cache_level
{
603 I915_CACHE_LLC
, /* also used for snoopable memory on non-LLC */
604 I915_CACHE_L3_LLC
, /* gen7+, L3 sits between the domain specifc
605 caches, eg sampler/render caches, and the
606 large Last-Level-Cache. LLC is coherent with
607 the CPU, but L3 is only visible to the GPU. */
608 I915_CACHE_WT
, /* hsw:gt3e WriteThrough for scanouts */
611 struct i915_ctx_hang_stats
{
612 /* This context had batch pending when hang was declared */
613 unsigned batch_pending
;
615 /* This context had batch active when hang was declared */
616 unsigned batch_active
;
618 /* Time when this context was last blamed for a GPU reset */
619 unsigned long guilty_ts
;
621 /* This context is banned to submit more work */
625 /* This must match up with the value previously used for execbuf2.rsvd1. */
626 #define DEFAULT_CONTEXT_HANDLE 0
628 * struct intel_context - as the name implies, represents a context.
629 * @ref: reference count.
630 * @user_handle: userspace tracking identity for this context.
631 * @remap_slice: l3 row remapping information.
632 * @file_priv: filp associated with this context (NULL for global default
634 * @hang_stats: information about the role of this context in possible GPU
636 * @vm: virtual memory space used by this context.
637 * @legacy_hw_ctx: render context backing object and whether it is correctly
638 * initialized (legacy ring submission mechanism only).
639 * @link: link in the global list of contexts.
641 * Contexts are memory images used by the hardware to store copies of their
644 struct intel_context
{
648 struct drm_i915_file_private
*file_priv
;
649 struct i915_ctx_hang_stats hang_stats
;
650 struct i915_hw_ppgtt
*ppgtt
;
652 /* Legacy ring buffer submission */
654 struct drm_i915_gem_object
*rcs_state
;
659 bool rcs_initialized
;
661 struct drm_i915_gem_object
*state
;
662 struct intel_ringbuffer
*ringbuf
;
663 } engine
[I915_NUM_RINGS
];
665 struct list_head link
;
675 struct drm_mm_node compressed_fb
;
676 struct drm_mm_node
*compressed_llb
;
680 /* Tracks whether the HW is actually enabled, not whether the feature is
684 /* On gen8 some rings cannont perform fbc clean operation so for now
685 * we are doing this on SW with mmio.
686 * This variable works in the opposite information direction
687 * of ring->fbc_dirty telling software on frontbuffer tracking
688 * to perform the cache clean on sw side.
690 bool need_sw_cache_clean
;
692 struct intel_fbc_work
{
693 struct delayed_work work
;
694 struct drm_crtc
*crtc
;
695 struct drm_framebuffer
*fb
;
699 FBC_OK
, /* FBC is enabled */
700 FBC_UNSUPPORTED
, /* FBC is not supported by this chipset */
701 FBC_NO_OUTPUT
, /* no outputs enabled to compress */
702 FBC_STOLEN_TOO_SMALL
, /* not enough space for buffers */
703 FBC_UNSUPPORTED_MODE
, /* interlace or doublescanned mode */
704 FBC_MODE_TOO_LARGE
, /* mode too large for compression */
705 FBC_BAD_PLANE
, /* fbc not supported on plane */
706 FBC_NOT_TILED
, /* buffer not tiled */
707 FBC_MULTIPLE_PIPES
, /* more than one pipe active */
709 FBC_CHIP_DEFAULT
, /* disabled by default on this chip */
714 struct intel_connector
*connector
;
722 struct intel_dp
*enabled
;
724 struct delayed_work work
;
725 unsigned busy_frontbuffer_bits
;
729 PCH_NONE
= 0, /* No PCH present */
730 PCH_IBX
, /* Ibexpeak PCH */
731 PCH_CPT
, /* Cougarpoint PCH */
732 PCH_LPT
, /* Lynxpoint PCH */
733 PCH_SPT
, /* Sunrisepoint PCH */
737 enum intel_sbi_destination
{
742 #define QUIRK_PIPEA_FORCE (1<<0)
743 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
744 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
745 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
746 #define QUIRK_PIPEB_FORCE (1<<4)
749 struct intel_fbc_work
;
752 struct i2c_adapter adapter
;
756 struct i2c_algo_bit_data bit_algo
;
757 struct drm_i915_private
*dev_priv
;
760 struct i915_suspend_saved_registers
{
781 u32 saveTRANS_HTOTAL_A
;
782 u32 saveTRANS_HBLANK_A
;
783 u32 saveTRANS_HSYNC_A
;
784 u32 saveTRANS_VTOTAL_A
;
785 u32 saveTRANS_VBLANK_A
;
786 u32 saveTRANS_VSYNC_A
;
794 u32 savePFIT_PGM_RATIOS
;
795 u32 saveBLC_HIST_CTL
;
797 u32 saveBLC_PWM_CTL2
;
798 u32 saveBLC_HIST_CTL_B
;
799 u32 saveBLC_CPU_PWM_CTL
;
800 u32 saveBLC_CPU_PWM_CTL2
;
813 u32 saveTRANS_HTOTAL_B
;
814 u32 saveTRANS_HBLANK_B
;
815 u32 saveTRANS_HSYNC_B
;
816 u32 saveTRANS_VTOTAL_B
;
817 u32 saveTRANS_VBLANK_B
;
818 u32 saveTRANS_VSYNC_B
;
832 u32 savePP_ON_DELAYS
;
833 u32 savePP_OFF_DELAYS
;
841 u32 savePFIT_CONTROL
;
842 u32 save_palette_a
[256];
843 u32 save_palette_b
[256];
854 u32 saveCACHE_MODE_0
;
855 u32 saveMI_ARB_STATE
;
866 uint64_t saveFENCE
[I915_MAX_NUM_FENCES
];
877 u32 savePIPEA_GMCH_DATA_M
;
878 u32 savePIPEB_GMCH_DATA_M
;
879 u32 savePIPEA_GMCH_DATA_N
;
880 u32 savePIPEB_GMCH_DATA_N
;
881 u32 savePIPEA_DP_LINK_M
;
882 u32 savePIPEB_DP_LINK_M
;
883 u32 savePIPEA_DP_LINK_N
;
884 u32 savePIPEB_DP_LINK_N
;
895 u32 savePCH_DREF_CONTROL
;
896 u32 saveDISP_ARB_CTL
;
897 u32 savePIPEA_DATA_M1
;
898 u32 savePIPEA_DATA_N1
;
899 u32 savePIPEA_LINK_M1
;
900 u32 savePIPEA_LINK_N1
;
901 u32 savePIPEB_DATA_M1
;
902 u32 savePIPEB_DATA_N1
;
903 u32 savePIPEB_LINK_M1
;
904 u32 savePIPEB_LINK_N1
;
905 u32 saveMCHBAR_RENDER_STANDBY
;
906 u32 savePCH_PORT_HOTPLUG
;
909 struct vlv_s0ix_state
{
916 u32 lra_limits
[GEN7_LRA_LIMITS_REG_NUM
];
917 u32 media_max_req_count
;
918 u32 gfx_max_req_count
;
950 /* Display 1 CZ domain */
955 u32 gt_scratch
[GEN7_GT_SCRATCH_REG_NUM
];
957 /* GT SA CZ domain */
964 /* Display 2 CZ domain */
970 struct intel_rps_ei
{
976 struct intel_gen6_power_mgmt
{
977 /* work and pm_iir are protected by dev_priv->irq_lock */
978 struct work_struct work
;
981 /* Frequencies are stored in potentially platform dependent multiples.
982 * In other words, *_freq needs to be multiplied by X to be interesting.
983 * Soft limits are those which are used for the dynamic reclocking done
984 * by the driver (raise frequencies under heavy loads, and lower for
985 * lighter loads). Hard limits are those imposed by the hardware.
987 * A distinction is made for overclocking, which is never enabled by
988 * default, and is considered to be above the hard limit if it's
991 u8 cur_freq
; /* Current frequency (cached, may not == HW) */
992 u8 min_freq_softlimit
; /* Minimum frequency permitted by the driver */
993 u8 max_freq_softlimit
; /* Max frequency permitted by the driver */
994 u8 max_freq
; /* Maximum frequency, RP0 if not overclocking */
995 u8 min_freq
; /* AKA RPn. Minimum frequency */
996 u8 efficient_freq
; /* AKA RPe. Pre-determined balanced frequency */
997 u8 rp1_freq
; /* "less than" RP0 power/freqency */
998 u8 rp0_freq
; /* Non-overclocked max frequency. */
1001 u32 ei_interrupt_count
;
1004 enum { LOW_POWER
, BETWEEN
, HIGH_POWER
} power
;
1007 struct delayed_work delayed_resume_work
;
1009 /* manual wa residency calculations */
1010 struct intel_rps_ei up_ei
, down_ei
;
1013 * Protects RPS/RC6 register access and PCU communication.
1014 * Must be taken after struct_mutex if nested.
1016 struct mutex hw_lock
;
1019 /* defined intel_pm.c */
1020 extern spinlock_t mchdev_lock
;
1022 struct intel_ilk_power_mgmt
{
1030 unsigned long last_time1
;
1031 unsigned long chipset_power
;
1034 unsigned long gfx_power
;
1040 struct drm_i915_gem_object
*pwrctx
;
1041 struct drm_i915_gem_object
*renderctx
;
1044 struct drm_i915_private
;
1045 struct i915_power_well
;
1047 struct i915_power_well_ops
{
1049 * Synchronize the well's hw state to match the current sw state, for
1050 * example enable/disable it based on the current refcount. Called
1051 * during driver init and resume time, possibly after first calling
1052 * the enable/disable handlers.
1054 void (*sync_hw
)(struct drm_i915_private
*dev_priv
,
1055 struct i915_power_well
*power_well
);
1057 * Enable the well and resources that depend on it (for example
1058 * interrupts located on the well). Called after the 0->1 refcount
1061 void (*enable
)(struct drm_i915_private
*dev_priv
,
1062 struct i915_power_well
*power_well
);
1064 * Disable the well and resources that depend on it. Called after
1065 * the 1->0 refcount transition.
1067 void (*disable
)(struct drm_i915_private
*dev_priv
,
1068 struct i915_power_well
*power_well
);
1069 /* Returns the hw enabled state. */
1070 bool (*is_enabled
)(struct drm_i915_private
*dev_priv
,
1071 struct i915_power_well
*power_well
);
1074 /* Power well structure for haswell */
1075 struct i915_power_well
{
1078 /* power well enable/disable usage count */
1080 /* cached hw enabled state */
1082 unsigned long domains
;
1084 const struct i915_power_well_ops
*ops
;
1087 struct i915_power_domains
{
1089 * Power wells needed for initialization at driver init and suspend
1090 * time are on. They are kept on until after the first modeset.
1094 int power_well_count
;
1097 int domain_use_count
[POWER_DOMAIN_NUM
];
1098 struct i915_power_well
*power_wells
;
1101 struct i915_dri1_state
{
1102 unsigned allow_batchbuffer
: 1;
1103 u32 __iomem
*gfx_hws_cpu_addr
;
1114 struct i915_ums_state
{
1116 * Flag if the X Server, and thus DRM, is not currently in
1117 * control of the device.
1119 * This is set between LeaveVT and EnterVT. It needs to be
1120 * replaced with a semaphore. It also needs to be
1121 * transitioned away from for kernel modesetting.
1126 #define MAX_L3_SLICES 2
1127 struct intel_l3_parity
{
1128 u32
*remap_info
[MAX_L3_SLICES
];
1129 struct work_struct error_work
;
1133 struct i915_gem_mm
{
1134 /** Memory allocator for GTT stolen memory */
1135 struct drm_mm stolen
;
1136 /** List of all objects in gtt_space. Used to restore gtt
1137 * mappings on resume */
1138 struct list_head bound_list
;
1140 * List of objects which are not bound to the GTT (thus
1141 * are idle and not used by the GPU) but still have
1142 * (presumably uncached) pages still attached.
1144 struct list_head unbound_list
;
1146 /** Usable portion of the GTT for GEM */
1147 unsigned long stolen_base
; /* limited to low memory (32-bit) */
1149 /** PPGTT used for aliasing the PPGTT with the GTT */
1150 struct i915_hw_ppgtt
*aliasing_ppgtt
;
1152 struct notifier_block oom_notifier
;
1153 struct shrinker shrinker
;
1154 bool shrinker_no_lock_stealing
;
1156 /** LRU list of objects with fence regs on them. */
1157 struct list_head fence_list
;
1160 * We leave the user IRQ off as much as possible,
1161 * but this means that requests will finish and never
1162 * be retired once the system goes idle. Set a timer to
1163 * fire periodically while the ring is running. When it
1164 * fires, go retire requests.
1166 struct delayed_work retire_work
;
1169 * When we detect an idle GPU, we want to turn on
1170 * powersaving features. So once we see that there
1171 * are no more requests outstanding and no more
1172 * arrive within a small period of time, we fire
1173 * off the idle_work.
1175 struct delayed_work idle_work
;
1178 * Are we in a non-interruptible section of code like
1184 * Is the GPU currently considered idle, or busy executing userspace
1185 * requests? Whilst idle, we attempt to power down the hardware and
1186 * display clocks. In order to reduce the effect on performance, there
1187 * is a slight delay before we do so.
1191 /* the indicator for dispatch video commands on two BSD rings */
1192 int bsd_ring_dispatch_index
;
1194 /** Bit 6 swizzling required for X tiling */
1195 uint32_t bit_6_swizzle_x
;
1196 /** Bit 6 swizzling required for Y tiling */
1197 uint32_t bit_6_swizzle_y
;
1199 /* accounting, useful for userland debugging */
1200 spinlock_t object_stat_lock
;
1201 size_t object_memory
;
1205 struct drm_i915_error_state_buf
{
1206 struct drm_i915_private
*i915
;
1215 struct i915_error_state_file_priv
{
1216 struct drm_device
*dev
;
1217 struct drm_i915_error_state
*error
;
1220 struct i915_gpu_error
{
1221 /* For hangcheck timer */
1222 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1223 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1224 /* Hang gpu twice in this window and your context gets banned */
1225 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1227 struct timer_list hangcheck_timer
;
1229 /* For reset and error_state handling. */
1231 /* Protected by the above dev->gpu_error.lock. */
1232 struct drm_i915_error_state
*first_error
;
1233 struct work_struct work
;
1236 unsigned long missed_irq_rings
;
1239 * State variable controlling the reset flow and count
1241 * This is a counter which gets incremented when reset is triggered,
1242 * and again when reset has been handled. So odd values (lowest bit set)
1243 * means that reset is in progress and even values that
1244 * (reset_counter >> 1):th reset was successfully completed.
1246 * If reset is not completed succesfully, the I915_WEDGE bit is
1247 * set meaning that hardware is terminally sour and there is no
1248 * recovery. All waiters on the reset_queue will be woken when
1251 * This counter is used by the wait_seqno code to notice that reset
1252 * event happened and it needs to restart the entire ioctl (since most
1253 * likely the seqno it waited for won't ever signal anytime soon).
1255 * This is important for lock-free wait paths, where no contended lock
1256 * naturally enforces the correct ordering between the bail-out of the
1257 * waiter and the gpu reset work code.
1259 atomic_t reset_counter
;
1261 #define I915_RESET_IN_PROGRESS_FLAG 1
1262 #define I915_WEDGED (1 << 31)
1265 * Waitqueue to signal when the reset has completed. Used by clients
1266 * that wait for dev_priv->mm.wedged to settle.
1268 wait_queue_head_t reset_queue
;
1270 /* Userspace knobs for gpu hang simulation;
1271 * combines both a ring mask, and extra flags
1274 #define I915_STOP_RING_ALLOW_BAN (1 << 31)
1275 #define I915_STOP_RING_ALLOW_WARN (1 << 30)
1277 /* For missed irq/seqno simulation. */
1278 unsigned int test_irq_rings
;
1280 /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
1281 bool reload_in_reset
;
1284 enum modeset_restore
{
1285 MODESET_ON_LID_OPEN
,
1290 struct ddi_vbt_port_info
{
1292 * This is an index in the HDMI/DVI DDI buffer translation table.
1293 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1294 * populate this field.
1296 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1297 uint8_t hdmi_level_shift
;
1299 uint8_t supports_dvi
:1;
1300 uint8_t supports_hdmi
:1;
1301 uint8_t supports_dp
:1;
1304 enum drrs_support_type
{
1305 DRRS_NOT_SUPPORTED
= 0,
1306 STATIC_DRRS_SUPPORT
= 1,
1307 SEAMLESS_DRRS_SUPPORT
= 2
1310 struct intel_vbt_data
{
1311 struct drm_display_mode
*lfp_lvds_vbt_mode
; /* if any */
1312 struct drm_display_mode
*sdvo_lvds_vbt_mode
; /* if any */
1315 unsigned int int_tv_support
:1;
1316 unsigned int lvds_dither
:1;
1317 unsigned int lvds_vbt
:1;
1318 unsigned int int_crt_support
:1;
1319 unsigned int lvds_use_ssc
:1;
1320 unsigned int display_clock_mode
:1;
1321 unsigned int fdi_rx_polarity_inverted
:1;
1322 unsigned int has_mipi
:1;
1324 unsigned int bios_lvds_val
; /* initial [PCH_]LVDS reg val in VBIOS */
1326 enum drrs_support_type drrs_type
;
1331 int edp_preemphasis
;
1333 bool edp_initialized
;
1336 struct edp_power_seq edp_pps
;
1341 bool active_low_pwm
;
1342 u8 min_brightness
; /* min_brightness/255 of max */
1349 struct mipi_config
*config
;
1350 struct mipi_pps_data
*pps
;
1354 u8
*sequence
[MIPI_SEQ_MAX
];
1360 union child_device_config
*child_dev
;
1362 struct ddi_vbt_port_info ddi_port_info
[I915_MAX_PORTS
];
1365 enum intel_ddb_partitioning
{
1367 INTEL_DDB_PART_5_6
, /* IVB+ */
1370 struct intel_wm_level
{
1378 struct ilk_wm_values
{
1379 uint32_t wm_pipe
[3];
1381 uint32_t wm_lp_spr
[3];
1382 uint32_t wm_linetime
[3];
1384 enum intel_ddb_partitioning partitioning
;
1388 * This struct helps tracking the state needed for runtime PM, which puts the
1389 * device in PCI D3 state. Notice that when this happens, nothing on the
1390 * graphics device works, even register access, so we don't get interrupts nor
1393 * Every piece of our code that needs to actually touch the hardware needs to
1394 * either call intel_runtime_pm_get or call intel_display_power_get with the
1395 * appropriate power domain.
1397 * Our driver uses the autosuspend delay feature, which means we'll only really
1398 * suspend if we stay with zero refcount for a certain amount of time. The
1399 * default value is currently very conservative (see intel_runtime_pm_enable), but
1400 * it can be changed with the standard runtime PM files from sysfs.
1402 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1403 * goes back to false exactly before we reenable the IRQs. We use this variable
1404 * to check if someone is trying to enable/disable IRQs while they're supposed
1405 * to be disabled. This shouldn't happen and we'll print some error messages in
1408 * For more, read the Documentation/power/runtime_pm.txt.
1410 struct i915_runtime_pm
{
1415 enum intel_pipe_crc_source
{
1416 INTEL_PIPE_CRC_SOURCE_NONE
,
1417 INTEL_PIPE_CRC_SOURCE_PLANE1
,
1418 INTEL_PIPE_CRC_SOURCE_PLANE2
,
1419 INTEL_PIPE_CRC_SOURCE_PF
,
1420 INTEL_PIPE_CRC_SOURCE_PIPE
,
1421 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1422 INTEL_PIPE_CRC_SOURCE_TV
,
1423 INTEL_PIPE_CRC_SOURCE_DP_B
,
1424 INTEL_PIPE_CRC_SOURCE_DP_C
,
1425 INTEL_PIPE_CRC_SOURCE_DP_D
,
1426 INTEL_PIPE_CRC_SOURCE_AUTO
,
1427 INTEL_PIPE_CRC_SOURCE_MAX
,
1430 struct intel_pipe_crc_entry
{
1435 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1436 struct intel_pipe_crc
{
1438 bool opened
; /* exclusive access to the result file */
1439 struct intel_pipe_crc_entry
*entries
;
1440 enum intel_pipe_crc_source source
;
1442 wait_queue_head_t wq
;
1445 struct i915_frontbuffer_tracking
{
1449 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1456 struct i915_wa_reg
{
1459 /* bitmask representing WA bits */
1463 #define I915_MAX_WA_REGS 16
1465 struct i915_workarounds
{
1466 struct i915_wa_reg reg
[I915_MAX_WA_REGS
];
1470 struct drm_i915_private
{
1471 struct drm_device
*dev
;
1472 struct kmem_cache
*slab
;
1474 const struct intel_device_info info
;
1476 int relative_constants_mode
;
1480 struct intel_uncore uncore
;
1482 struct intel_gmbus gmbus
[GMBUS_NUM_PORTS
];
1485 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1486 * controller on different i2c buses. */
1487 struct mutex gmbus_mutex
;
1490 * Base address of the gmbus and gpio block.
1492 uint32_t gpio_mmio_base
;
1494 /* MMIO base address for MIPI regs */
1495 uint32_t mipi_mmio_base
;
1497 wait_queue_head_t gmbus_wait_queue
;
1499 struct pci_dev
*bridge_dev
;
1500 struct intel_engine_cs ring
[I915_NUM_RINGS
];
1501 struct drm_i915_gem_object
*semaphore_obj
;
1502 uint32_t last_seqno
, next_seqno
;
1504 struct drm_dma_handle
*status_page_dmah
;
1505 struct resource mch_res
;
1507 /* protects the irq masks */
1508 spinlock_t irq_lock
;
1510 /* protects the mmio flip data */
1511 spinlock_t mmio_flip_lock
;
1513 bool display_irqs_enabled
;
1515 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1516 struct pm_qos_request pm_qos
;
1518 /* DPIO indirect register protection */
1519 struct mutex dpio_lock
;
1521 /** Cached value of IMR to avoid reads in updating the bitfield */
1524 u32 de_irq_mask
[I915_MAX_PIPES
];
1529 u32 pipestat_irq_mask
[I915_MAX_PIPES
];
1531 struct work_struct hotplug_work
;
1533 unsigned long hpd_last_jiffies
;
1538 HPD_MARK_DISABLED
= 2
1540 } hpd_stats
[HPD_NUM_PINS
];
1542 struct delayed_work hotplug_reenable_work
;
1544 struct i915_fbc fbc
;
1545 struct i915_drrs drrs
;
1546 struct intel_opregion opregion
;
1547 struct intel_vbt_data vbt
;
1549 bool preserve_bios_swizzle
;
1552 struct intel_overlay
*overlay
;
1554 /* backlight registers and fields in struct intel_panel */
1555 struct mutex backlight_lock
;
1558 bool no_aux_handshake
;
1560 /* protects panel power sequencer state */
1561 struct mutex pps_mutex
;
1563 struct drm_i915_fence_reg fence_regs
[I915_MAX_NUM_FENCES
]; /* assume 965 */
1564 int fence_reg_start
; /* 4 if userland hasn't ioctl'd us yet */
1565 int num_fence_regs
; /* 8 on pre-965, 16 otherwise */
1567 unsigned int fsb_freq
, mem_freq
, is_ddr3
;
1568 unsigned int vlv_cdclk_freq
;
1571 * wq - Driver workqueue for GEM.
1573 * NOTE: Work items scheduled here are not allowed to grab any modeset
1574 * locks, for otherwise the flushing done in the pageflip code will
1575 * result in deadlocks.
1577 struct workqueue_struct
*wq
;
1579 /* Display functions */
1580 struct drm_i915_display_funcs display
;
1582 /* PCH chipset type */
1583 enum intel_pch pch_type
;
1584 unsigned short pch_id
;
1586 unsigned long quirks
;
1588 enum modeset_restore modeset_restore
;
1589 struct mutex modeset_restore_lock
;
1591 struct list_head vm_list
; /* Global list of all address spaces */
1592 struct i915_gtt gtt
; /* VM representing the global address space */
1594 struct i915_gem_mm mm
;
1595 DECLARE_HASHTABLE(mm_structs
, 7);
1596 struct mutex mm_lock
;
1598 /* Kernel Modesetting */
1600 struct sdvo_device_mapping sdvo_mappings
[2];
1602 struct drm_crtc
*plane_to_crtc_mapping
[I915_MAX_PIPES
];
1603 struct drm_crtc
*pipe_to_crtc_mapping
[I915_MAX_PIPES
];
1604 wait_queue_head_t pending_flip_queue
;
1606 #ifdef CONFIG_DEBUG_FS
1607 struct intel_pipe_crc pipe_crc
[I915_MAX_PIPES
];
1610 int num_shared_dpll
;
1611 struct intel_shared_dpll shared_dplls
[I915_NUM_PLLS
];
1612 int dpio_phy_iosf_port
[I915_NUM_PHYS_VLV
];
1614 struct i915_workarounds workarounds
;
1616 /* Reclocking support */
1617 bool render_reclock_avail
;
1618 bool lvds_downclock_avail
;
1619 /* indicates the reduced downclock for LVDS*/
1622 struct i915_frontbuffer_tracking fb_tracking
;
1626 bool mchbar_need_disable
;
1628 struct intel_l3_parity l3_parity
;
1630 /* Cannot be determined by PCIID. You must always read a register. */
1633 /* gen6+ rps state */
1634 struct intel_gen6_power_mgmt rps
;
1636 /* ilk-only ips/rps state. Everything in here is protected by the global
1637 * mchdev_lock in intel_pm.c */
1638 struct intel_ilk_power_mgmt ips
;
1640 struct i915_power_domains power_domains
;
1642 struct i915_psr psr
;
1644 struct i915_gpu_error gpu_error
;
1646 struct drm_i915_gem_object
*vlv_pctx
;
1648 #ifdef CONFIG_DRM_I915_FBDEV
1649 /* list of fbdev register on this device */
1650 struct intel_fbdev
*fbdev
;
1651 struct work_struct fbdev_suspend_work
;
1654 struct drm_property
*broadcast_rgb_property
;
1655 struct drm_property
*force_audio_property
;
1657 uint32_t hw_context_size
;
1658 struct list_head context_list
;
1663 struct i915_suspend_saved_registers regfile
;
1664 struct vlv_s0ix_state vlv_s0ix_state
;
1668 * Raw watermark latency values:
1669 * in 0.1us units for WM0,
1670 * in 0.5us units for WM1+.
1673 uint16_t pri_latency
[5];
1675 uint16_t spr_latency
[5];
1677 uint16_t cur_latency
[5];
1679 /* current hardware state */
1680 struct ilk_wm_values hw
;
1683 struct i915_runtime_pm pm
;
1685 struct intel_digital_port
*hpd_irq_port
[I915_MAX_PORTS
];
1686 u32 long_hpd_port_mask
;
1687 u32 short_hpd_port_mask
;
1688 struct work_struct dig_port_work
;
1691 * if we get a HPD irq from DP and a HPD irq from non-DP
1692 * the non-DP HPD could block the workqueue on a mode config
1693 * mutex getting, that userspace may have taken. However
1694 * userspace is waiting on the DP workqueue to run which is
1695 * blocked behind the non-DP one.
1697 struct workqueue_struct
*dp_wq
;
1699 uint32_t bios_vgacntr
;
1701 /* Old dri1 support infrastructure, beware the dragons ya fools entering
1703 struct i915_dri1_state dri1
;
1704 /* Old ums support infrastructure, same warning applies. */
1705 struct i915_ums_state ums
;
1707 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
1709 int (*do_execbuf
)(struct drm_device
*dev
, struct drm_file
*file
,
1710 struct intel_engine_cs
*ring
,
1711 struct intel_context
*ctx
,
1712 struct drm_i915_gem_execbuffer2
*args
,
1713 struct list_head
*vmas
,
1714 struct drm_i915_gem_object
*batch_obj
,
1715 u64 exec_start
, u32 flags
);
1716 int (*init_rings
)(struct drm_device
*dev
);
1717 void (*cleanup_ring
)(struct intel_engine_cs
*ring
);
1718 void (*stop_ring
)(struct intel_engine_cs
*ring
);
1722 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
1723 * will be rejected. Instead look for a better place.
1727 static inline struct drm_i915_private
*to_i915(const struct drm_device
*dev
)
1729 return dev
->dev_private
;
1732 /* Iterate over initialised rings */
1733 #define for_each_ring(ring__, dev_priv__, i__) \
1734 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
1735 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
1737 enum hdmi_force_audio
{
1738 HDMI_AUDIO_OFF_DVI
= -2, /* no aux data for HDMI-DVI converter */
1739 HDMI_AUDIO_OFF
, /* force turn off HDMI audio */
1740 HDMI_AUDIO_AUTO
, /* trust EDID */
1741 HDMI_AUDIO_ON
, /* force turn on HDMI audio */
1744 #define I915_GTT_OFFSET_NONE ((u32)-1)
1746 struct drm_i915_gem_object_ops
{
1747 /* Interface between the GEM object and its backing storage.
1748 * get_pages() is called once prior to the use of the associated set
1749 * of pages before to binding them into the GTT, and put_pages() is
1750 * called after we no longer need them. As we expect there to be
1751 * associated cost with migrating pages between the backing storage
1752 * and making them available for the GPU (e.g. clflush), we may hold
1753 * onto the pages after they are no longer referenced by the GPU
1754 * in case they may be used again shortly (for example migrating the
1755 * pages to a different memory domain within the GTT). put_pages()
1756 * will therefore most likely be called when the object itself is
1757 * being released or under memory pressure (where we attempt to
1758 * reap pages for the shrinker).
1760 int (*get_pages
)(struct drm_i915_gem_object
*);
1761 void (*put_pages
)(struct drm_i915_gem_object
*);
1762 int (*dmabuf_export
)(struct drm_i915_gem_object
*);
1763 void (*release
)(struct drm_i915_gem_object
*);
1767 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
1768 * considered to be the frontbuffer for the given plane interface-vise. This
1769 * doesn't mean that the hw necessarily already scans it out, but that any
1770 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
1772 * We have one bit per pipe and per scanout plane type.
1774 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 4
1775 #define INTEL_FRONTBUFFER_BITS \
1776 (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES)
1777 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
1778 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
1779 #define INTEL_FRONTBUFFER_CURSOR(pipe) \
1780 (1 << (1 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1781 #define INTEL_FRONTBUFFER_SPRITE(pipe) \
1782 (1 << (2 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1783 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
1784 (1 << (3 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1785 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
1786 (0xf << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
1788 struct drm_i915_gem_object
{
1789 struct drm_gem_object base
;
1791 const struct drm_i915_gem_object_ops
*ops
;
1793 /** List of VMAs backed by this object */
1794 struct list_head vma_list
;
1796 /** Stolen memory for this object, instead of being backed by shmem. */
1797 struct drm_mm_node
*stolen
;
1798 struct list_head global_list
;
1800 struct list_head ring_list
;
1801 /** Used in execbuf to temporarily hold a ref */
1802 struct list_head obj_exec_link
;
1805 * This is set if the object is on the active lists (has pending
1806 * rendering and so a non-zero seqno), and is not set if it i s on
1807 * inactive (ready to be unbound) list.
1809 unsigned int active
:1;
1812 * This is set if the object has been written to since last bound
1815 unsigned int dirty
:1;
1818 * Fence register bits (if any) for this object. Will be set
1819 * as needed when mapped into the GTT.
1820 * Protected by dev->struct_mutex.
1822 signed int fence_reg
:I915_MAX_NUM_FENCE_BITS
;
1825 * Advice: are the backing pages purgeable?
1827 unsigned int madv
:2;
1830 * Current tiling mode for the object.
1832 unsigned int tiling_mode
:2;
1834 * Whether the tiling parameters for the currently associated fence
1835 * register have changed. Note that for the purposes of tracking
1836 * tiling changes we also treat the unfenced register, the register
1837 * slot that the object occupies whilst it executes a fenced
1838 * command (such as BLT on gen2/3), as a "fence".
1840 unsigned int fence_dirty
:1;
1843 * Is the object at the current location in the gtt mappable and
1844 * fenceable? Used to avoid costly recalculations.
1846 unsigned int map_and_fenceable
:1;
1849 * Whether the current gtt mapping needs to be mappable (and isn't just
1850 * mappable by accident). Track pin and fault separate for a more
1851 * accurate mappable working set.
1853 unsigned int fault_mappable
:1;
1854 unsigned int pin_mappable
:1;
1855 unsigned int pin_display
:1;
1858 * Is the object to be mapped as read-only to the GPU
1859 * Only honoured if hardware has relevant pte bit
1861 unsigned long gt_ro
:1;
1862 unsigned int cache_level
:3;
1864 unsigned int has_dma_mapping
:1;
1866 unsigned int frontbuffer_bits
:INTEL_FRONTBUFFER_BITS
;
1868 struct sg_table
*pages
;
1869 int pages_pin_count
;
1871 /* prime dma-buf support */
1872 void *dma_buf_vmapping
;
1875 struct intel_engine_cs
*ring
;
1877 /** Breadcrumb of last rendering to the buffer. */
1878 uint32_t last_read_seqno
;
1879 uint32_t last_write_seqno
;
1880 /** Breadcrumb of last fenced GPU access to the buffer. */
1881 uint32_t last_fenced_seqno
;
1883 /** Current tiling stride for the object, if it's tiled. */
1886 /** References from framebuffers, locks out tiling changes. */
1887 unsigned long framebuffer_references
;
1889 /** Record of address bit 17 of each page at last unbind. */
1890 unsigned long *bit_17
;
1892 /** User space pin count and filp owning the pin */
1893 unsigned long user_pin_count
;
1894 struct drm_file
*pin_filp
;
1896 /** for phy allocated objects */
1897 struct drm_dma_handle
*phys_handle
;
1900 struct i915_gem_userptr
{
1902 unsigned read_only
:1;
1903 unsigned workers
:4;
1904 #define I915_GEM_USERPTR_MAX_WORKERS 15
1906 struct i915_mm_struct
*mm
;
1907 struct i915_mmu_object
*mmu_object
;
1908 struct work_struct
*work
;
1912 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
1914 void i915_gem_track_fb(struct drm_i915_gem_object
*old
,
1915 struct drm_i915_gem_object
*new,
1916 unsigned frontbuffer_bits
);
1919 * Request queue structure.
1921 * The request queue allows us to note sequence numbers that have been emitted
1922 * and may be associated with active buffers to be retired.
1924 * By keeping this list, we can avoid having to do questionable
1925 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
1926 * an emission time with seqnos for tracking how far ahead of the GPU we are.
1928 struct drm_i915_gem_request
{
1929 /** On Which ring this request was generated */
1930 struct intel_engine_cs
*ring
;
1932 /** GEM sequence number associated with this request. */
1935 /** Position in the ringbuffer of the start of the request */
1938 /** Position in the ringbuffer of the end of the request */
1941 /** Context related to this request */
1942 struct intel_context
*ctx
;
1944 /** Batch buffer related to this request if any */
1945 struct drm_i915_gem_object
*batch_obj
;
1947 /** Time at which this request was emitted, in jiffies. */
1948 unsigned long emitted_jiffies
;
1950 /** global list entry for this request */
1951 struct list_head list
;
1953 struct drm_i915_file_private
*file_priv
;
1954 /** file_priv list entry for this request */
1955 struct list_head client_list
;
1958 struct drm_i915_file_private
{
1959 struct drm_i915_private
*dev_priv
;
1960 struct drm_file
*file
;
1964 struct list_head request_list
;
1965 struct delayed_work idle_work
;
1967 struct idr context_idr
;
1969 atomic_t rps_wait_boost
;
1970 struct intel_engine_cs
*bsd_ring
;
1974 * A command that requires special handling by the command parser.
1976 struct drm_i915_cmd_descriptor
{
1978 * Flags describing how the command parser processes the command.
1980 * CMD_DESC_FIXED: The command has a fixed length if this is set,
1981 * a length mask if not set
1982 * CMD_DESC_SKIP: The command is allowed but does not follow the
1983 * standard length encoding for the opcode range in
1985 * CMD_DESC_REJECT: The command is never allowed
1986 * CMD_DESC_REGISTER: The command should be checked against the
1987 * register whitelist for the appropriate ring
1988 * CMD_DESC_MASTER: The command is allowed if the submitting process
1992 #define CMD_DESC_FIXED (1<<0)
1993 #define CMD_DESC_SKIP (1<<1)
1994 #define CMD_DESC_REJECT (1<<2)
1995 #define CMD_DESC_REGISTER (1<<3)
1996 #define CMD_DESC_BITMASK (1<<4)
1997 #define CMD_DESC_MASTER (1<<5)
2000 * The command's unique identification bits and the bitmask to get them.
2001 * This isn't strictly the opcode field as defined in the spec and may
2002 * also include type, subtype, and/or subop fields.
2010 * The command's length. The command is either fixed length (i.e. does
2011 * not include a length field) or has a length field mask. The flag
2012 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
2013 * a length mask. All command entries in a command table must include
2014 * length information.
2022 * Describes where to find a register address in the command to check
2023 * against the ring's register whitelist. Only valid if flags has the
2024 * CMD_DESC_REGISTER bit set.
2031 #define MAX_CMD_DESC_BITMASKS 3
2033 * Describes command checks where a particular dword is masked and
2034 * compared against an expected value. If the command does not match
2035 * the expected value, the parser rejects it. Only valid if flags has
2036 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
2039 * If the check specifies a non-zero condition_mask then the parser
2040 * only performs the check when the bits specified by condition_mask
2047 u32 condition_offset
;
2049 } bits
[MAX_CMD_DESC_BITMASKS
];
2053 * A table of commands requiring special handling by the command parser.
2055 * Each ring has an array of tables. Each table consists of an array of command
2056 * descriptors, which must be sorted with command opcodes in ascending order.
2058 struct drm_i915_cmd_table
{
2059 const struct drm_i915_cmd_descriptor
*table
;
2063 /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
2064 #define __I915__(p) ({ \
2065 struct drm_i915_private *__p; \
2066 if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
2067 __p = (struct drm_i915_private *)p; \
2068 else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
2069 __p = to_i915((struct drm_device *)p); \
2074 #define INTEL_INFO(p) (&__I915__(p)->info)
2075 #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id)
2077 #define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577)
2078 #define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562)
2079 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
2080 #define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572)
2081 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
2082 #define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592)
2083 #define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772)
2084 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
2085 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
2086 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
2087 #define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42)
2088 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
2089 #define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001)
2090 #define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011)
2091 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
2092 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
2093 #define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046)
2094 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
2095 #define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \
2096 INTEL_DEVID(dev) == 0x0152 || \
2097 INTEL_DEVID(dev) == 0x015a)
2098 #define IS_SNB_GT1(dev) (INTEL_DEVID(dev) == 0x0102 || \
2099 INTEL_DEVID(dev) == 0x0106 || \
2100 INTEL_DEVID(dev) == 0x010A)
2101 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
2102 #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
2103 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
2104 #define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
2105 #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake)
2106 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
2107 #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
2108 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
2109 #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
2110 ((INTEL_DEVID(dev) & 0xf) == 0x2 || \
2111 (INTEL_DEVID(dev) & 0xf) == 0x6 || \
2112 (INTEL_DEVID(dev) & 0xf) == 0xe))
2113 #define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \
2114 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2115 #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
2116 (INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
2117 #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
2118 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2119 /* ULX machines are also considered ULT. */
2120 #define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \
2121 INTEL_DEVID(dev) == 0x0A1E)
2122 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
2125 * The genX designation typically refers to the render engine, so render
2126 * capability related checks should use IS_GEN, while display and other checks
2127 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2130 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
2131 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
2132 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
2133 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
2134 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
2135 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
2136 #define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8)
2137 #define IS_GEN9(dev) (INTEL_INFO(dev)->gen == 9)
2139 #define RENDER_RING (1<<RCS)
2140 #define BSD_RING (1<<VCS)
2141 #define BLT_RING (1<<BCS)
2142 #define VEBOX_RING (1<<VECS)
2143 #define BSD2_RING (1<<VCS2)
2144 #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING)
2145 #define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING)
2146 #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING)
2147 #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
2148 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
2149 #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
2150 __I915__(dev)->ellc_size)
2151 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
2153 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
2154 #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8)
2155 #define USES_PPGTT(dev) (i915.enable_ppgtt)
2156 #define USES_FULL_PPGTT(dev) (i915.enable_ppgtt == 2)
2158 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
2159 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
2161 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2162 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
2164 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2165 * even when in MSI mode. This results in spurious interrupt warnings if the
2166 * legacy irq no. is shared with another device. The kernel then disables that
2167 * interrupt source and so prevents the other device from working properly.
2169 #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2170 #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2172 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2173 * rows, which changed the alignment requirements and fence programming.
2175 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
2177 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
2178 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
2179 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
2180 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
2181 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
2183 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
2184 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
2185 #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
2187 #define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev))
2189 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
2190 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
2191 #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev))
2192 #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \
2193 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev))
2194 #define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6)
2195 #define HAS_RC6p(dev) (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
2197 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
2198 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2199 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2200 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2201 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2202 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2203 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2204 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2206 #define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
2207 #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
2208 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
2209 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
2210 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
2211 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
2212 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
2214 #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev))
2216 /* DPF == dynamic parity feature */
2217 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
2218 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
2220 #define GT_FREQUENCY_MULTIPLIER 50
2222 #include "i915_trace.h"
2224 extern const struct drm_ioctl_desc i915_ioctls
[];
2225 extern int i915_max_ioctl
;
2227 extern int i915_suspend_legacy(struct drm_device
*dev
, pm_message_t state
);
2228 extern int i915_resume_legacy(struct drm_device
*dev
);
2229 extern int i915_master_create(struct drm_device
*dev
, struct drm_master
*master
);
2230 extern void i915_master_destroy(struct drm_device
*dev
, struct drm_master
*master
);
2233 struct i915_params
{
2235 int panel_ignore_lid
;
2236 unsigned int powersave
;
2238 unsigned int lvds_downclock
;
2239 int lvds_channel_mode
;
2241 int vbt_sdvo_panel_type
;
2245 int enable_execlists
;
2247 unsigned int preliminary_hw_support
;
2248 int disable_power_well
;
2250 int invert_brightness
;
2251 int enable_cmd_parser
;
2252 /* leave bools at the end to not create holes */
2253 bool enable_hangcheck
;
2255 bool prefault_disable
;
2257 bool disable_display
;
2258 bool disable_vtd_wa
;
2262 extern struct i915_params i915 __read_mostly
;
2265 void i915_update_dri1_breadcrumb(struct drm_device
*dev
);
2266 extern void i915_kernel_lost_context(struct drm_device
* dev
);
2267 extern int i915_driver_load(struct drm_device
*, unsigned long flags
);
2268 extern int i915_driver_unload(struct drm_device
*);
2269 extern int i915_driver_open(struct drm_device
*dev
, struct drm_file
*file
);
2270 extern void i915_driver_lastclose(struct drm_device
* dev
);
2271 extern void i915_driver_preclose(struct drm_device
*dev
,
2272 struct drm_file
*file
);
2273 extern void i915_driver_postclose(struct drm_device
*dev
,
2274 struct drm_file
*file
);
2275 extern int i915_driver_device_is_agp(struct drm_device
* dev
);
2276 #ifdef CONFIG_COMPAT
2277 extern long i915_compat_ioctl(struct file
*filp
, unsigned int cmd
,
2280 extern int i915_emit_box(struct drm_device
*dev
,
2281 struct drm_clip_rect
*box
,
2283 extern int intel_gpu_reset(struct drm_device
*dev
);
2284 extern int i915_reset(struct drm_device
*dev
);
2285 extern unsigned long i915_chipset_val(struct drm_i915_private
*dev_priv
);
2286 extern unsigned long i915_mch_val(struct drm_i915_private
*dev_priv
);
2287 extern unsigned long i915_gfx_val(struct drm_i915_private
*dev_priv
);
2288 extern void i915_update_gfx_val(struct drm_i915_private
*dev_priv
);
2289 int vlv_force_gfx_clock(struct drm_i915_private
*dev_priv
, bool on
);
2290 void intel_hpd_cancel_work(struct drm_i915_private
*dev_priv
);
2293 void i915_queue_hangcheck(struct drm_device
*dev
);
2295 void i915_handle_error(struct drm_device
*dev
, bool wedged
,
2296 const char *fmt
, ...);
2298 void gen6_set_pm_mask(struct drm_i915_private
*dev_priv
, u32 pm_iir
,
2300 extern void intel_irq_init(struct drm_i915_private
*dev_priv
);
2301 extern void intel_hpd_init(struct drm_i915_private
*dev_priv
);
2302 int intel_irq_install(struct drm_i915_private
*dev_priv
);
2303 void intel_irq_uninstall(struct drm_i915_private
*dev_priv
);
2305 extern void intel_uncore_sanitize(struct drm_device
*dev
);
2306 extern void intel_uncore_early_sanitize(struct drm_device
*dev
,
2307 bool restore_forcewake
);
2308 extern void intel_uncore_init(struct drm_device
*dev
);
2309 extern void intel_uncore_check_errors(struct drm_device
*dev
);
2310 extern void intel_uncore_fini(struct drm_device
*dev
);
2311 extern void intel_uncore_forcewake_reset(struct drm_device
*dev
, bool restore
);
2314 i915_enable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
2318 i915_disable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
2321 void valleyview_enable_display_irqs(struct drm_i915_private
*dev_priv
);
2322 void valleyview_disable_display_irqs(struct drm_i915_private
*dev_priv
);
2324 ironlake_enable_display_irq(struct drm_i915_private
*dev_priv
, u32 mask
);
2326 ironlake_disable_display_irq(struct drm_i915_private
*dev_priv
, u32 mask
);
2327 void ibx_display_interrupt_update(struct drm_i915_private
*dev_priv
,
2328 uint32_t interrupt_mask
,
2329 uint32_t enabled_irq_mask
);
2330 #define ibx_enable_display_interrupt(dev_priv, bits) \
2331 ibx_display_interrupt_update((dev_priv), (bits), (bits))
2332 #define ibx_disable_display_interrupt(dev_priv, bits) \
2333 ibx_display_interrupt_update((dev_priv), (bits), 0)
2336 int i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
2337 struct drm_file
*file_priv
);
2338 int i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
2339 struct drm_file
*file_priv
);
2340 int i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
2341 struct drm_file
*file_priv
);
2342 int i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
2343 struct drm_file
*file_priv
);
2344 int i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
2345 struct drm_file
*file_priv
);
2346 int i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
2347 struct drm_file
*file_priv
);
2348 int i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
2349 struct drm_file
*file_priv
);
2350 int i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
2351 struct drm_file
*file_priv
);
2352 void i915_gem_execbuffer_move_to_active(struct list_head
*vmas
,
2353 struct intel_engine_cs
*ring
);
2354 void i915_gem_execbuffer_retire_commands(struct drm_device
*dev
,
2355 struct drm_file
*file
,
2356 struct intel_engine_cs
*ring
,
2357 struct drm_i915_gem_object
*obj
);
2358 int i915_gem_ringbuffer_submission(struct drm_device
*dev
,
2359 struct drm_file
*file
,
2360 struct intel_engine_cs
*ring
,
2361 struct intel_context
*ctx
,
2362 struct drm_i915_gem_execbuffer2
*args
,
2363 struct list_head
*vmas
,
2364 struct drm_i915_gem_object
*batch_obj
,
2365 u64 exec_start
, u32 flags
);
2366 int i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
2367 struct drm_file
*file_priv
);
2368 int i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
2369 struct drm_file
*file_priv
);
2370 int i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
2371 struct drm_file
*file_priv
);
2372 int i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
2373 struct drm_file
*file_priv
);
2374 int i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
2375 struct drm_file
*file_priv
);
2376 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
2377 struct drm_file
*file
);
2378 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
2379 struct drm_file
*file
);
2380 int i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
2381 struct drm_file
*file_priv
);
2382 int i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
2383 struct drm_file
*file_priv
);
2384 int i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
2385 struct drm_file
*file_priv
);
2386 int i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
2387 struct drm_file
*file_priv
);
2388 int i915_gem_set_tiling(struct drm_device
*dev
, void *data
,
2389 struct drm_file
*file_priv
);
2390 int i915_gem_get_tiling(struct drm_device
*dev
, void *data
,
2391 struct drm_file
*file_priv
);
2392 int i915_gem_init_userptr(struct drm_device
*dev
);
2393 int i915_gem_userptr_ioctl(struct drm_device
*dev
, void *data
,
2394 struct drm_file
*file
);
2395 int i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
2396 struct drm_file
*file_priv
);
2397 int i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
,
2398 struct drm_file
*file_priv
);
2399 void i915_gem_load(struct drm_device
*dev
);
2400 unsigned long i915_gem_shrink(struct drm_i915_private
*dev_priv
,
2403 #define I915_SHRINK_PURGEABLE 0x1
2404 #define I915_SHRINK_UNBOUND 0x2
2405 #define I915_SHRINK_BOUND 0x4
2406 void *i915_gem_object_alloc(struct drm_device
*dev
);
2407 void i915_gem_object_free(struct drm_i915_gem_object
*obj
);
2408 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
2409 const struct drm_i915_gem_object_ops
*ops
);
2410 struct drm_i915_gem_object
*i915_gem_alloc_object(struct drm_device
*dev
,
2412 void i915_init_vm(struct drm_i915_private
*dev_priv
,
2413 struct i915_address_space
*vm
);
2414 void i915_gem_free_object(struct drm_gem_object
*obj
);
2415 void i915_gem_vma_destroy(struct i915_vma
*vma
);
2417 #define PIN_MAPPABLE 0x1
2418 #define PIN_NONBLOCK 0x2
2419 #define PIN_GLOBAL 0x4
2420 #define PIN_OFFSET_BIAS 0x8
2421 #define PIN_OFFSET_MASK (~4095)
2422 int __must_check
i915_gem_object_pin(struct drm_i915_gem_object
*obj
,
2423 struct i915_address_space
*vm
,
2426 int __must_check
i915_vma_unbind(struct i915_vma
*vma
);
2427 int i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
);
2428 void i915_gem_release_all_mmaps(struct drm_i915_private
*dev_priv
);
2429 void i915_gem_release_mmap(struct drm_i915_gem_object
*obj
);
2430 void i915_gem_lastclose(struct drm_device
*dev
);
2432 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object
*obj
,
2433 int *needs_clflush
);
2435 int __must_check
i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
);
2436 static inline struct page
*i915_gem_object_get_page(struct drm_i915_gem_object
*obj
, int n
)
2438 struct sg_page_iter sg_iter
;
2440 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
, n
)
2441 return sg_page_iter_page(&sg_iter
);
2445 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object
*obj
)
2447 BUG_ON(obj
->pages
== NULL
);
2448 obj
->pages_pin_count
++;
2450 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object
*obj
)
2452 BUG_ON(obj
->pages_pin_count
== 0);
2453 obj
->pages_pin_count
--;
2456 int __must_check
i915_mutex_lock_interruptible(struct drm_device
*dev
);
2457 int i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
2458 struct intel_engine_cs
*to
);
2459 void i915_vma_move_to_active(struct i915_vma
*vma
,
2460 struct intel_engine_cs
*ring
);
2461 int i915_gem_dumb_create(struct drm_file
*file_priv
,
2462 struct drm_device
*dev
,
2463 struct drm_mode_create_dumb
*args
);
2464 int i915_gem_mmap_gtt(struct drm_file
*file_priv
, struct drm_device
*dev
,
2465 uint32_t handle
, uint64_t *offset
);
2467 * Returns true if seq1 is later than seq2.
2470 i915_seqno_passed(uint32_t seq1
, uint32_t seq2
)
2472 return (int32_t)(seq1
- seq2
) >= 0;
2475 int __must_check
i915_gem_get_seqno(struct drm_device
*dev
, u32
*seqno
);
2476 int __must_check
i915_gem_set_seqno(struct drm_device
*dev
, u32 seqno
);
2477 int __must_check
i915_gem_object_get_fence(struct drm_i915_gem_object
*obj
);
2478 int __must_check
i915_gem_object_put_fence(struct drm_i915_gem_object
*obj
);
2480 bool i915_gem_object_pin_fence(struct drm_i915_gem_object
*obj
);
2481 void i915_gem_object_unpin_fence(struct drm_i915_gem_object
*obj
);
2483 struct drm_i915_gem_request
*
2484 i915_gem_find_active_request(struct intel_engine_cs
*ring
);
2486 bool i915_gem_retire_requests(struct drm_device
*dev
);
2487 void i915_gem_retire_requests_ring(struct intel_engine_cs
*ring
);
2488 int __must_check
i915_gem_check_wedge(struct i915_gpu_error
*error
,
2489 bool interruptible
);
2490 int __must_check
i915_gem_check_olr(struct intel_engine_cs
*ring
, u32 seqno
);
2492 static inline bool i915_reset_in_progress(struct i915_gpu_error
*error
)
2494 return unlikely(atomic_read(&error
->reset_counter
)
2495 & (I915_RESET_IN_PROGRESS_FLAG
| I915_WEDGED
));
2498 static inline bool i915_terminally_wedged(struct i915_gpu_error
*error
)
2500 return atomic_read(&error
->reset_counter
) & I915_WEDGED
;
2503 static inline u32
i915_reset_count(struct i915_gpu_error
*error
)
2505 return ((atomic_read(&error
->reset_counter
) & ~I915_WEDGED
) + 1) / 2;
2508 static inline bool i915_stop_ring_allow_ban(struct drm_i915_private
*dev_priv
)
2510 return dev_priv
->gpu_error
.stop_rings
== 0 ||
2511 dev_priv
->gpu_error
.stop_rings
& I915_STOP_RING_ALLOW_BAN
;
2514 static inline bool i915_stop_ring_allow_warn(struct drm_i915_private
*dev_priv
)
2516 return dev_priv
->gpu_error
.stop_rings
== 0 ||
2517 dev_priv
->gpu_error
.stop_rings
& I915_STOP_RING_ALLOW_WARN
;
2520 void i915_gem_reset(struct drm_device
*dev
);
2521 bool i915_gem_clflush_object(struct drm_i915_gem_object
*obj
, bool force
);
2522 int __must_check
i915_gem_object_finish_gpu(struct drm_i915_gem_object
*obj
);
2523 int __must_check
i915_gem_init(struct drm_device
*dev
);
2524 int i915_gem_init_rings(struct drm_device
*dev
);
2525 int __must_check
i915_gem_init_hw(struct drm_device
*dev
);
2526 int i915_gem_l3_remap(struct intel_engine_cs
*ring
, int slice
);
2527 void i915_gem_init_swizzling(struct drm_device
*dev
);
2528 void i915_gem_cleanup_ringbuffer(struct drm_device
*dev
);
2529 int __must_check
i915_gpu_idle(struct drm_device
*dev
);
2530 int __must_check
i915_gem_suspend(struct drm_device
*dev
);
2531 int __i915_add_request(struct intel_engine_cs
*ring
,
2532 struct drm_file
*file
,
2533 struct drm_i915_gem_object
*batch_obj
,
2535 #define i915_add_request(ring, seqno) \
2536 __i915_add_request(ring, NULL, NULL, seqno)
2537 int __must_check
i915_wait_seqno(struct intel_engine_cs
*ring
,
2539 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
);
2541 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
,
2544 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
);
2546 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
2548 struct intel_engine_cs
*pipelined
);
2549 void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object
*obj
);
2550 int i915_gem_object_attach_phys(struct drm_i915_gem_object
*obj
,
2552 int i915_gem_open(struct drm_device
*dev
, struct drm_file
*file
);
2553 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
);
2556 i915_gem_get_gtt_size(struct drm_device
*dev
, uint32_t size
, int tiling_mode
);
2558 i915_gem_get_gtt_alignment(struct drm_device
*dev
, uint32_t size
,
2559 int tiling_mode
, bool fenced
);
2561 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
2562 enum i915_cache_level cache_level
);
2564 struct drm_gem_object
*i915_gem_prime_import(struct drm_device
*dev
,
2565 struct dma_buf
*dma_buf
);
2567 struct dma_buf
*i915_gem_prime_export(struct drm_device
*dev
,
2568 struct drm_gem_object
*gem_obj
, int flags
);
2570 void i915_gem_restore_fences(struct drm_device
*dev
);
2572 unsigned long i915_gem_obj_offset(struct drm_i915_gem_object
*o
,
2573 struct i915_address_space
*vm
);
2574 bool i915_gem_obj_bound_any(struct drm_i915_gem_object
*o
);
2575 bool i915_gem_obj_bound(struct drm_i915_gem_object
*o
,
2576 struct i915_address_space
*vm
);
2577 unsigned long i915_gem_obj_size(struct drm_i915_gem_object
*o
,
2578 struct i915_address_space
*vm
);
2579 struct i915_vma
*i915_gem_obj_to_vma(struct drm_i915_gem_object
*obj
,
2580 struct i915_address_space
*vm
);
2582 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object
*obj
,
2583 struct i915_address_space
*vm
);
2585 struct i915_vma
*i915_gem_obj_to_ggtt(struct drm_i915_gem_object
*obj
);
2586 static inline bool i915_gem_obj_is_pinned(struct drm_i915_gem_object
*obj
) {
2587 struct i915_vma
*vma
;
2588 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
2589 if (vma
->pin_count
> 0)
2594 /* Some GGTT VM helpers */
2595 #define i915_obj_to_ggtt(obj) \
2596 (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
2597 static inline bool i915_is_ggtt(struct i915_address_space
*vm
)
2599 struct i915_address_space
*ggtt
=
2600 &((struct drm_i915_private
*)(vm
)->dev
->dev_private
)->gtt
.base
;
2604 static inline struct i915_hw_ppgtt
*
2605 i915_vm_to_ppgtt(struct i915_address_space
*vm
)
2607 WARN_ON(i915_is_ggtt(vm
));
2609 return container_of(vm
, struct i915_hw_ppgtt
, base
);
2613 static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object
*obj
)
2615 return i915_gem_obj_bound(obj
, i915_obj_to_ggtt(obj
));
2618 static inline unsigned long
2619 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object
*obj
)
2621 return i915_gem_obj_offset(obj
, i915_obj_to_ggtt(obj
));
2624 static inline unsigned long
2625 i915_gem_obj_ggtt_size(struct drm_i915_gem_object
*obj
)
2627 return i915_gem_obj_size(obj
, i915_obj_to_ggtt(obj
));
2630 static inline int __must_check
2631 i915_gem_obj_ggtt_pin(struct drm_i915_gem_object
*obj
,
2635 return i915_gem_object_pin(obj
, i915_obj_to_ggtt(obj
),
2636 alignment
, flags
| PIN_GLOBAL
);
2640 i915_gem_object_ggtt_unbind(struct drm_i915_gem_object
*obj
)
2642 return i915_vma_unbind(i915_gem_obj_to_ggtt(obj
));
2645 void i915_gem_object_ggtt_unpin(struct drm_i915_gem_object
*obj
);
2647 /* i915_gem_context.c */
2648 int __must_check
i915_gem_context_init(struct drm_device
*dev
);
2649 void i915_gem_context_fini(struct drm_device
*dev
);
2650 void i915_gem_context_reset(struct drm_device
*dev
);
2651 int i915_gem_context_open(struct drm_device
*dev
, struct drm_file
*file
);
2652 int i915_gem_context_enable(struct drm_i915_private
*dev_priv
);
2653 void i915_gem_context_close(struct drm_device
*dev
, struct drm_file
*file
);
2654 int i915_switch_context(struct intel_engine_cs
*ring
,
2655 struct intel_context
*to
);
2656 struct intel_context
*
2657 i915_gem_context_get(struct drm_i915_file_private
*file_priv
, u32 id
);
2658 void i915_gem_context_free(struct kref
*ctx_ref
);
2659 struct drm_i915_gem_object
*
2660 i915_gem_alloc_context_obj(struct drm_device
*dev
, size_t size
);
2661 static inline void i915_gem_context_reference(struct intel_context
*ctx
)
2663 kref_get(&ctx
->ref
);
2666 static inline void i915_gem_context_unreference(struct intel_context
*ctx
)
2668 kref_put(&ctx
->ref
, i915_gem_context_free
);
2671 static inline bool i915_gem_context_is_default(const struct intel_context
*c
)
2673 return c
->user_handle
== DEFAULT_CONTEXT_HANDLE
;
2676 int i915_gem_context_create_ioctl(struct drm_device
*dev
, void *data
,
2677 struct drm_file
*file
);
2678 int i915_gem_context_destroy_ioctl(struct drm_device
*dev
, void *data
,
2679 struct drm_file
*file
);
2681 /* i915_gem_evict.c */
2682 int __must_check
i915_gem_evict_something(struct drm_device
*dev
,
2683 struct i915_address_space
*vm
,
2686 unsigned cache_level
,
2687 unsigned long start
,
2690 int i915_gem_evict_vm(struct i915_address_space
*vm
, bool do_idle
);
2691 int i915_gem_evict_everything(struct drm_device
*dev
);
2693 /* belongs in i915_gem_gtt.h */
2694 static inline void i915_gem_chipset_flush(struct drm_device
*dev
)
2696 if (INTEL_INFO(dev
)->gen
< 6)
2697 intel_gtt_chipset_flush();
2700 /* i915_gem_stolen.c */
2701 int i915_gem_init_stolen(struct drm_device
*dev
);
2702 int i915_gem_stolen_setup_compression(struct drm_device
*dev
, int size
, int fb_cpp
);
2703 void i915_gem_stolen_cleanup_compression(struct drm_device
*dev
);
2704 void i915_gem_cleanup_stolen(struct drm_device
*dev
);
2705 struct drm_i915_gem_object
*
2706 i915_gem_object_create_stolen(struct drm_device
*dev
, u32 size
);
2707 struct drm_i915_gem_object
*
2708 i915_gem_object_create_stolen_for_preallocated(struct drm_device
*dev
,
2713 /* i915_gem_tiling.c */
2714 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object
*obj
)
2716 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2718 return dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_9_10_17
&&
2719 obj
->tiling_mode
!= I915_TILING_NONE
;
2722 void i915_gem_detect_bit_6_swizzle(struct drm_device
*dev
);
2723 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
2724 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
2726 /* i915_gem_debug.c */
2728 int i915_verify_lists(struct drm_device
*dev
);
2730 #define i915_verify_lists(dev) 0
2733 /* i915_debugfs.c */
2734 int i915_debugfs_init(struct drm_minor
*minor
);
2735 void i915_debugfs_cleanup(struct drm_minor
*minor
);
2736 #ifdef CONFIG_DEBUG_FS
2737 void intel_display_crc_init(struct drm_device
*dev
);
2739 static inline void intel_display_crc_init(struct drm_device
*dev
) {}
2742 /* i915_gpu_error.c */
2744 void i915_error_printf(struct drm_i915_error_state_buf
*e
, const char *f
, ...);
2745 int i915_error_state_to_str(struct drm_i915_error_state_buf
*estr
,
2746 const struct i915_error_state_file_priv
*error
);
2747 int i915_error_state_buf_init(struct drm_i915_error_state_buf
*eb
,
2748 struct drm_i915_private
*i915
,
2749 size_t count
, loff_t pos
);
2750 static inline void i915_error_state_buf_release(
2751 struct drm_i915_error_state_buf
*eb
)
2755 void i915_capture_error_state(struct drm_device
*dev
, bool wedge
,
2756 const char *error_msg
);
2757 void i915_error_state_get(struct drm_device
*dev
,
2758 struct i915_error_state_file_priv
*error_priv
);
2759 void i915_error_state_put(struct i915_error_state_file_priv
*error_priv
);
2760 void i915_destroy_error_state(struct drm_device
*dev
);
2762 void i915_get_extra_instdone(struct drm_device
*dev
, uint32_t *instdone
);
2763 const char *i915_cache_level_str(struct drm_i915_private
*i915
, int type
);
2765 /* i915_cmd_parser.c */
2766 int i915_cmd_parser_get_version(void);
2767 int i915_cmd_parser_init_ring(struct intel_engine_cs
*ring
);
2768 void i915_cmd_parser_fini_ring(struct intel_engine_cs
*ring
);
2769 bool i915_needs_cmd_parser(struct intel_engine_cs
*ring
);
2770 int i915_parse_cmds(struct intel_engine_cs
*ring
,
2771 struct drm_i915_gem_object
*batch_obj
,
2772 u32 batch_start_offset
,
2775 /* i915_suspend.c */
2776 extern int i915_save_state(struct drm_device
*dev
);
2777 extern int i915_restore_state(struct drm_device
*dev
);
2780 void i915_save_display_reg(struct drm_device
*dev
);
2781 void i915_restore_display_reg(struct drm_device
*dev
);
2784 void i915_setup_sysfs(struct drm_device
*dev_priv
);
2785 void i915_teardown_sysfs(struct drm_device
*dev_priv
);
2788 extern int intel_setup_gmbus(struct drm_device
*dev
);
2789 extern void intel_teardown_gmbus(struct drm_device
*dev
);
2790 static inline bool intel_gmbus_is_port_valid(unsigned port
)
2792 return (port
>= GMBUS_PORT_SSC
&& port
<= GMBUS_PORT_DPD
);
2795 extern struct i2c_adapter
*intel_gmbus_get_adapter(
2796 struct drm_i915_private
*dev_priv
, unsigned port
);
2797 extern void intel_gmbus_set_speed(struct i2c_adapter
*adapter
, int speed
);
2798 extern void intel_gmbus_force_bit(struct i2c_adapter
*adapter
, bool force_bit
);
2799 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter
*adapter
)
2801 return container_of(adapter
, struct intel_gmbus
, adapter
)->force_bit
;
2803 extern void intel_i2c_reset(struct drm_device
*dev
);
2805 /* intel_opregion.c */
2807 extern int intel_opregion_setup(struct drm_device
*dev
);
2808 extern void intel_opregion_init(struct drm_device
*dev
);
2809 extern void intel_opregion_fini(struct drm_device
*dev
);
2810 extern void intel_opregion_asle_intr(struct drm_device
*dev
);
2811 extern int intel_opregion_notify_encoder(struct intel_encoder
*intel_encoder
,
2813 extern int intel_opregion_notify_adapter(struct drm_device
*dev
,
2816 static inline int intel_opregion_setup(struct drm_device
*dev
) { return 0; }
2817 static inline void intel_opregion_init(struct drm_device
*dev
) { return; }
2818 static inline void intel_opregion_fini(struct drm_device
*dev
) { return; }
2819 static inline void intel_opregion_asle_intr(struct drm_device
*dev
) { return; }
2821 intel_opregion_notify_encoder(struct intel_encoder
*intel_encoder
, bool enable
)
2826 intel_opregion_notify_adapter(struct drm_device
*dev
, pci_power_t state
)
2834 extern void intel_register_dsm_handler(void);
2835 extern void intel_unregister_dsm_handler(void);
2837 static inline void intel_register_dsm_handler(void) { return; }
2838 static inline void intel_unregister_dsm_handler(void) { return; }
2839 #endif /* CONFIG_ACPI */
2842 extern void intel_modeset_init_hw(struct drm_device
*dev
);
2843 extern void intel_modeset_init(struct drm_device
*dev
);
2844 extern void intel_modeset_gem_init(struct drm_device
*dev
);
2845 extern void intel_modeset_cleanup(struct drm_device
*dev
);
2846 extern void intel_connector_unregister(struct intel_connector
*);
2847 extern int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
);
2848 extern void intel_modeset_setup_hw_state(struct drm_device
*dev
,
2849 bool force_restore
);
2850 extern void i915_redisable_vga(struct drm_device
*dev
);
2851 extern void i915_redisable_vga_power_on(struct drm_device
*dev
);
2852 extern bool intel_fbc_enabled(struct drm_device
*dev
);
2853 extern void bdw_fbc_sw_flush(struct drm_device
*dev
, u32 value
);
2854 extern void intel_disable_fbc(struct drm_device
*dev
);
2855 extern bool ironlake_set_drps(struct drm_device
*dev
, u8 val
);
2856 extern void intel_init_pch_refclk(struct drm_device
*dev
);
2857 extern void gen6_set_rps(struct drm_device
*dev
, u8 val
);
2858 extern void valleyview_set_rps(struct drm_device
*dev
, u8 val
);
2859 extern void intel_set_memory_cxsr(struct drm_i915_private
*dev_priv
,
2861 extern void intel_detect_pch(struct drm_device
*dev
);
2862 extern int intel_trans_dp_port_sel(struct drm_crtc
*crtc
);
2863 extern int intel_enable_rc6(const struct drm_device
*dev
);
2865 extern bool i915_semaphore_is_enabled(struct drm_device
*dev
);
2866 int i915_reg_read_ioctl(struct drm_device
*dev
, void *data
,
2867 struct drm_file
*file
);
2868 int i915_get_reset_stats_ioctl(struct drm_device
*dev
, void *data
,
2869 struct drm_file
*file
);
2871 void intel_notify_mmio_flip(struct intel_engine_cs
*ring
);
2874 extern struct intel_overlay_error_state
*intel_overlay_capture_error_state(struct drm_device
*dev
);
2875 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf
*e
,
2876 struct intel_overlay_error_state
*error
);
2878 extern struct intel_display_error_state
*intel_display_capture_error_state(struct drm_device
*dev
);
2879 extern void intel_display_print_error_state(struct drm_i915_error_state_buf
*e
,
2880 struct drm_device
*dev
,
2881 struct intel_display_error_state
*error
);
2883 /* On SNB platform, before reading ring registers forcewake bit
2884 * must be set to prevent GT core from power down and stale values being
2887 void gen6_gt_force_wake_get(struct drm_i915_private
*dev_priv
, int fw_engine
);
2888 void gen6_gt_force_wake_put(struct drm_i915_private
*dev_priv
, int fw_engine
);
2889 void assert_force_wake_inactive(struct drm_i915_private
*dev_priv
);
2891 int sandybridge_pcode_read(struct drm_i915_private
*dev_priv
, u8 mbox
, u32
*val
);
2892 int sandybridge_pcode_write(struct drm_i915_private
*dev_priv
, u8 mbox
, u32 val
);
2894 /* intel_sideband.c */
2895 u32
vlv_punit_read(struct drm_i915_private
*dev_priv
, u8 addr
);
2896 void vlv_punit_write(struct drm_i915_private
*dev_priv
, u8 addr
, u32 val
);
2897 u32
vlv_nc_read(struct drm_i915_private
*dev_priv
, u8 addr
);
2898 u32
vlv_gpio_nc_read(struct drm_i915_private
*dev_priv
, u32 reg
);
2899 void vlv_gpio_nc_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
2900 u32
vlv_cck_read(struct drm_i915_private
*dev_priv
, u32 reg
);
2901 void vlv_cck_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
2902 u32
vlv_ccu_read(struct drm_i915_private
*dev_priv
, u32 reg
);
2903 void vlv_ccu_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
2904 u32
vlv_bunit_read(struct drm_i915_private
*dev_priv
, u32 reg
);
2905 void vlv_bunit_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
2906 u32
vlv_gps_core_read(struct drm_i915_private
*dev_priv
, u32 reg
);
2907 void vlv_gps_core_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
2908 u32
vlv_dpio_read(struct drm_i915_private
*dev_priv
, enum pipe pipe
, int reg
);
2909 void vlv_dpio_write(struct drm_i915_private
*dev_priv
, enum pipe pipe
, int reg
, u32 val
);
2910 u32
intel_sbi_read(struct drm_i915_private
*dev_priv
, u16 reg
,
2911 enum intel_sbi_destination destination
);
2912 void intel_sbi_write(struct drm_i915_private
*dev_priv
, u16 reg
, u32 value
,
2913 enum intel_sbi_destination destination
);
2914 u32
vlv_flisdsi_read(struct drm_i915_private
*dev_priv
, u32 reg
);
2915 void vlv_flisdsi_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
2917 int vlv_gpu_freq(struct drm_i915_private
*dev_priv
, int val
);
2918 int vlv_freq_opcode(struct drm_i915_private
*dev_priv
, int val
);
2920 #define FORCEWAKE_RENDER (1 << 0)
2921 #define FORCEWAKE_MEDIA (1 << 1)
2922 #define FORCEWAKE_ALL (FORCEWAKE_RENDER | FORCEWAKE_MEDIA)
2925 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
2926 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
2928 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
2929 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
2930 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
2931 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
2933 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
2934 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
2935 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
2936 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
2938 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
2939 * will be implemented using 2 32-bit writes in an arbitrary order with
2940 * an arbitrary delay between them. This can cause the hardware to
2941 * act upon the intermediate value, possibly leading to corruption and
2942 * machine death. You have been warned.
2944 #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
2945 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
2947 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
2948 u32 upper = I915_READ(upper_reg); \
2949 u32 lower = I915_READ(lower_reg); \
2950 u32 tmp = I915_READ(upper_reg); \
2951 if (upper != tmp) { \
2953 lower = I915_READ(lower_reg); \
2954 WARN_ON(I915_READ(upper_reg) != upper); \
2956 (u64)upper << 32 | lower; })
2958 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
2959 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
2961 /* "Broadcast RGB" property */
2962 #define INTEL_BROADCAST_RGB_AUTO 0
2963 #define INTEL_BROADCAST_RGB_FULL 1
2964 #define INTEL_BROADCAST_RGB_LIMITED 2
2966 static inline uint32_t i915_vgacntrl_reg(struct drm_device
*dev
)
2968 if (IS_VALLEYVIEW(dev
))
2969 return VLV_VGACNTRL
;
2970 else if (INTEL_INFO(dev
)->gen
>= 5)
2971 return CPU_VGACNTRL
;
2976 static inline void __user
*to_user_ptr(u64 address
)
2978 return (void __user
*)(uintptr_t)address
;
2981 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m
)
2983 unsigned long j
= msecs_to_jiffies(m
);
2985 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);
2988 static inline unsigned long
2989 timespec_to_jiffies_timeout(const struct timespec
*value
)
2991 unsigned long j
= timespec_to_jiffies(value
);
2993 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);
2997 * If you need to wait X milliseconds between events A and B, but event B
2998 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
2999 * when event A happened, then just before event B you call this function and
3000 * pass the timestamp as the first argument, and X as the second argument.
3003 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies
, int to_wait_ms
)
3005 unsigned long target_jiffies
, tmp_jiffies
, remaining_jiffies
;
3008 * Don't re-read the value of "jiffies" every time since it may change
3009 * behind our back and break the math.
3011 tmp_jiffies
= jiffies
;
3012 target_jiffies
= timestamp_jiffies
+
3013 msecs_to_jiffies_timeout(to_wait_ms
);
3015 if (time_after(target_jiffies
, tmp_jiffies
)) {
3016 remaining_jiffies
= target_jiffies
- tmp_jiffies
;
3017 while (remaining_jiffies
)
3019 schedule_timeout_uninterruptible(remaining_jiffies
);