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Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_drv.h
1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
2 */
3 /*
4 *
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
28 */
29
30 #ifndef _I915_DRV_H_
31 #define _I915_DRV_H_
32
33 #include <uapi/drm/i915_drm.h>
34
35 #include "i915_reg.h"
36 #include "intel_bios.h"
37 #include "intel_ringbuffer.h"
38 #include "i915_gem_gtt.h"
39 #include <linux/io-mapping.h>
40 #include <linux/i2c.h>
41 #include <linux/i2c-algo-bit.h>
42 #include <drm/intel-gtt.h>
43 #include <linux/backlight.h>
44 #include <linux/hashtable.h>
45 #include <linux/intel-iommu.h>
46 #include <linux/kref.h>
47 #include <linux/pm_qos.h>
48
49 /* General customization:
50 */
51
52 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
53
54 #define DRIVER_NAME "i915"
55 #define DRIVER_DESC "Intel Graphics"
56 #define DRIVER_DATE "20080730"
57
58 enum pipe {
59 INVALID_PIPE = -1,
60 PIPE_A = 0,
61 PIPE_B,
62 PIPE_C,
63 _PIPE_EDP,
64 I915_MAX_PIPES = _PIPE_EDP
65 };
66 #define pipe_name(p) ((p) + 'A')
67
68 enum transcoder {
69 TRANSCODER_A = 0,
70 TRANSCODER_B,
71 TRANSCODER_C,
72 TRANSCODER_EDP,
73 I915_MAX_TRANSCODERS
74 };
75 #define transcoder_name(t) ((t) + 'A')
76
77 enum plane {
78 PLANE_A = 0,
79 PLANE_B,
80 PLANE_C,
81 };
82 #define plane_name(p) ((p) + 'A')
83
84 #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
85
86 enum port {
87 PORT_A = 0,
88 PORT_B,
89 PORT_C,
90 PORT_D,
91 PORT_E,
92 I915_MAX_PORTS
93 };
94 #define port_name(p) ((p) + 'A')
95
96 #define I915_NUM_PHYS_VLV 2
97
98 enum dpio_channel {
99 DPIO_CH0,
100 DPIO_CH1
101 };
102
103 enum dpio_phy {
104 DPIO_PHY0,
105 DPIO_PHY1
106 };
107
108 enum intel_display_power_domain {
109 POWER_DOMAIN_PIPE_A,
110 POWER_DOMAIN_PIPE_B,
111 POWER_DOMAIN_PIPE_C,
112 POWER_DOMAIN_PIPE_A_PANEL_FITTER,
113 POWER_DOMAIN_PIPE_B_PANEL_FITTER,
114 POWER_DOMAIN_PIPE_C_PANEL_FITTER,
115 POWER_DOMAIN_TRANSCODER_A,
116 POWER_DOMAIN_TRANSCODER_B,
117 POWER_DOMAIN_TRANSCODER_C,
118 POWER_DOMAIN_TRANSCODER_EDP,
119 POWER_DOMAIN_PORT_DDI_A_2_LANES,
120 POWER_DOMAIN_PORT_DDI_A_4_LANES,
121 POWER_DOMAIN_PORT_DDI_B_2_LANES,
122 POWER_DOMAIN_PORT_DDI_B_4_LANES,
123 POWER_DOMAIN_PORT_DDI_C_2_LANES,
124 POWER_DOMAIN_PORT_DDI_C_4_LANES,
125 POWER_DOMAIN_PORT_DDI_D_2_LANES,
126 POWER_DOMAIN_PORT_DDI_D_4_LANES,
127 POWER_DOMAIN_PORT_DSI,
128 POWER_DOMAIN_PORT_CRT,
129 POWER_DOMAIN_PORT_OTHER,
130 POWER_DOMAIN_VGA,
131 POWER_DOMAIN_AUDIO,
132 POWER_DOMAIN_INIT,
133
134 POWER_DOMAIN_NUM,
135 };
136
137 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
138 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
139 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
140 #define POWER_DOMAIN_TRANSCODER(tran) \
141 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
142 (tran) + POWER_DOMAIN_TRANSCODER_A)
143
144 enum hpd_pin {
145 HPD_NONE = 0,
146 HPD_PORT_A = HPD_NONE, /* PORT_A is internal */
147 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
148 HPD_CRT,
149 HPD_SDVO_B,
150 HPD_SDVO_C,
151 HPD_PORT_B,
152 HPD_PORT_C,
153 HPD_PORT_D,
154 HPD_NUM_PINS
155 };
156
157 #define I915_GEM_GPU_DOMAINS \
158 (I915_GEM_DOMAIN_RENDER | \
159 I915_GEM_DOMAIN_SAMPLER | \
160 I915_GEM_DOMAIN_COMMAND | \
161 I915_GEM_DOMAIN_INSTRUCTION | \
162 I915_GEM_DOMAIN_VERTEX)
163
164 #define for_each_pipe(p) for ((p) = 0; (p) < INTEL_INFO(dev)->num_pipes; (p)++)
165 #define for_each_sprite(p, s) for ((s) = 0; (s) < INTEL_INFO(dev)->num_sprites[(p)]; (s)++)
166
167 #define for_each_crtc(dev, crtc) \
168 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
169
170 #define for_each_intel_crtc(dev, intel_crtc) \
171 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)
172
173 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
174 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
175 if ((intel_encoder)->base.crtc == (__crtc))
176
177 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
178 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
179 if ((intel_connector)->base.encoder == (__encoder))
180
181 struct drm_i915_private;
182 struct i915_mmu_object;
183
184 enum intel_dpll_id {
185 DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
186 /* real shared dpll ids must be >= 0 */
187 DPLL_ID_PCH_PLL_A,
188 DPLL_ID_PCH_PLL_B,
189 };
190 #define I915_NUM_PLLS 2
191
192 struct intel_dpll_hw_state {
193 uint32_t dpll;
194 uint32_t dpll_md;
195 uint32_t fp0;
196 uint32_t fp1;
197 };
198
199 struct intel_shared_dpll {
200 int refcount; /* count of number of CRTCs sharing this PLL */
201 int active; /* count of number of active CRTCs (i.e. DPMS on) */
202 bool on; /* is the PLL actually active? Disabled during modeset */
203 const char *name;
204 /* should match the index in the dev_priv->shared_dplls array */
205 enum intel_dpll_id id;
206 struct intel_dpll_hw_state hw_state;
207 void (*mode_set)(struct drm_i915_private *dev_priv,
208 struct intel_shared_dpll *pll);
209 void (*enable)(struct drm_i915_private *dev_priv,
210 struct intel_shared_dpll *pll);
211 void (*disable)(struct drm_i915_private *dev_priv,
212 struct intel_shared_dpll *pll);
213 bool (*get_hw_state)(struct drm_i915_private *dev_priv,
214 struct intel_shared_dpll *pll,
215 struct intel_dpll_hw_state *hw_state);
216 };
217
218 /* Used by dp and fdi links */
219 struct intel_link_m_n {
220 uint32_t tu;
221 uint32_t gmch_m;
222 uint32_t gmch_n;
223 uint32_t link_m;
224 uint32_t link_n;
225 };
226
227 void intel_link_compute_m_n(int bpp, int nlanes,
228 int pixel_clock, int link_clock,
229 struct intel_link_m_n *m_n);
230
231 struct intel_ddi_plls {
232 int spll_refcount;
233 int wrpll1_refcount;
234 int wrpll2_refcount;
235 };
236
237 /* Interface history:
238 *
239 * 1.1: Original.
240 * 1.2: Add Power Management
241 * 1.3: Add vblank support
242 * 1.4: Fix cmdbuffer path, add heap destroy
243 * 1.5: Add vblank pipe configuration
244 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
245 * - Support vertical blank on secondary display pipe
246 */
247 #define DRIVER_MAJOR 1
248 #define DRIVER_MINOR 6
249 #define DRIVER_PATCHLEVEL 0
250
251 #define WATCH_LISTS 0
252 #define WATCH_GTT 0
253
254 struct opregion_header;
255 struct opregion_acpi;
256 struct opregion_swsci;
257 struct opregion_asle;
258
259 struct intel_opregion {
260 struct opregion_header __iomem *header;
261 struct opregion_acpi __iomem *acpi;
262 struct opregion_swsci __iomem *swsci;
263 u32 swsci_gbda_sub_functions;
264 u32 swsci_sbcb_sub_functions;
265 struct opregion_asle __iomem *asle;
266 void __iomem *vbt;
267 u32 __iomem *lid_state;
268 struct work_struct asle_work;
269 };
270 #define OPREGION_SIZE (8*1024)
271
272 struct intel_overlay;
273 struct intel_overlay_error_state;
274
275 struct drm_i915_master_private {
276 drm_local_map_t *sarea;
277 struct _drm_i915_sarea *sarea_priv;
278 };
279 #define I915_FENCE_REG_NONE -1
280 #define I915_MAX_NUM_FENCES 32
281 /* 32 fences + sign bit for FENCE_REG_NONE */
282 #define I915_MAX_NUM_FENCE_BITS 6
283
284 struct drm_i915_fence_reg {
285 struct list_head lru_list;
286 struct drm_i915_gem_object *obj;
287 int pin_count;
288 };
289
290 struct sdvo_device_mapping {
291 u8 initialized;
292 u8 dvo_port;
293 u8 slave_addr;
294 u8 dvo_wiring;
295 u8 i2c_pin;
296 u8 ddc_pin;
297 };
298
299 struct intel_display_error_state;
300
301 struct drm_i915_error_state {
302 struct kref ref;
303 struct timeval time;
304
305 char error_msg[128];
306 u32 reset_count;
307 u32 suspend_count;
308
309 /* Generic register state */
310 u32 eir;
311 u32 pgtbl_er;
312 u32 ier;
313 u32 ccid;
314 u32 derrmr;
315 u32 forcewake;
316 u32 error; /* gen6+ */
317 u32 err_int; /* gen7 */
318 u32 done_reg;
319 u32 gac_eco;
320 u32 gam_ecochk;
321 u32 gab_ctl;
322 u32 gfx_mode;
323 u32 extra_instdone[I915_NUM_INSTDONE_REG];
324 u64 fence[I915_MAX_NUM_FENCES];
325 struct intel_overlay_error_state *overlay;
326 struct intel_display_error_state *display;
327
328 struct drm_i915_error_ring {
329 bool valid;
330 /* Software tracked state */
331 bool waiting;
332 int hangcheck_score;
333 enum intel_ring_hangcheck_action hangcheck_action;
334 int num_requests;
335
336 /* our own tracking of ring head and tail */
337 u32 cpu_ring_head;
338 u32 cpu_ring_tail;
339
340 u32 semaphore_seqno[I915_NUM_RINGS - 1];
341
342 /* Register state */
343 u32 tail;
344 u32 head;
345 u32 ctl;
346 u32 hws;
347 u32 ipeir;
348 u32 ipehr;
349 u32 instdone;
350 u32 bbstate;
351 u32 instpm;
352 u32 instps;
353 u32 seqno;
354 u64 bbaddr;
355 u64 acthd;
356 u32 fault_reg;
357 u64 faddr;
358 u32 rc_psmi; /* sleep state */
359 u32 semaphore_mboxes[I915_NUM_RINGS - 1];
360
361 struct drm_i915_error_object {
362 int page_count;
363 u32 gtt_offset;
364 u32 *pages[0];
365 } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
366
367 struct drm_i915_error_request {
368 long jiffies;
369 u32 seqno;
370 u32 tail;
371 } *requests;
372
373 struct {
374 u32 gfx_mode;
375 union {
376 u64 pdp[4];
377 u32 pp_dir_base;
378 };
379 } vm_info;
380
381 pid_t pid;
382 char comm[TASK_COMM_LEN];
383 } ring[I915_NUM_RINGS];
384 struct drm_i915_error_buffer {
385 u32 size;
386 u32 name;
387 u32 rseqno, wseqno;
388 u32 gtt_offset;
389 u32 read_domains;
390 u32 write_domain;
391 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
392 s32 pinned:2;
393 u32 tiling:2;
394 u32 dirty:1;
395 u32 purgeable:1;
396 u32 userptr:1;
397 s32 ring:4;
398 u32 cache_level:3;
399 } **active_bo, **pinned_bo;
400
401 u32 *active_bo_count, *pinned_bo_count;
402 };
403
404 struct intel_connector;
405 struct intel_crtc_config;
406 struct intel_plane_config;
407 struct intel_crtc;
408 struct intel_limit;
409 struct dpll;
410
411 struct drm_i915_display_funcs {
412 bool (*fbc_enabled)(struct drm_device *dev);
413 void (*enable_fbc)(struct drm_crtc *crtc);
414 void (*disable_fbc)(struct drm_device *dev);
415 int (*get_display_clock_speed)(struct drm_device *dev);
416 int (*get_fifo_size)(struct drm_device *dev, int plane);
417 /**
418 * find_dpll() - Find the best values for the PLL
419 * @limit: limits for the PLL
420 * @crtc: current CRTC
421 * @target: target frequency in kHz
422 * @refclk: reference clock frequency in kHz
423 * @match_clock: if provided, @best_clock P divider must
424 * match the P divider from @match_clock
425 * used for LVDS downclocking
426 * @best_clock: best PLL values found
427 *
428 * Returns true on success, false on failure.
429 */
430 bool (*find_dpll)(const struct intel_limit *limit,
431 struct drm_crtc *crtc,
432 int target, int refclk,
433 struct dpll *match_clock,
434 struct dpll *best_clock);
435 void (*update_wm)(struct drm_crtc *crtc);
436 void (*update_sprite_wm)(struct drm_plane *plane,
437 struct drm_crtc *crtc,
438 uint32_t sprite_width, int pixel_size,
439 bool enable, bool scaled);
440 void (*modeset_global_resources)(struct drm_device *dev);
441 /* Returns the active state of the crtc, and if the crtc is active,
442 * fills out the pipe-config with the hw state. */
443 bool (*get_pipe_config)(struct intel_crtc *,
444 struct intel_crtc_config *);
445 void (*get_plane_config)(struct intel_crtc *,
446 struct intel_plane_config *);
447 int (*crtc_mode_set)(struct drm_crtc *crtc,
448 int x, int y,
449 struct drm_framebuffer *old_fb);
450 void (*crtc_enable)(struct drm_crtc *crtc);
451 void (*crtc_disable)(struct drm_crtc *crtc);
452 void (*off)(struct drm_crtc *crtc);
453 void (*write_eld)(struct drm_connector *connector,
454 struct drm_crtc *crtc,
455 struct drm_display_mode *mode);
456 void (*fdi_link_train)(struct drm_crtc *crtc);
457 void (*init_clock_gating)(struct drm_device *dev);
458 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
459 struct drm_framebuffer *fb,
460 struct drm_i915_gem_object *obj,
461 struct intel_engine_cs *ring,
462 uint32_t flags);
463 void (*update_primary_plane)(struct drm_crtc *crtc,
464 struct drm_framebuffer *fb,
465 int x, int y);
466 void (*hpd_irq_setup)(struct drm_device *dev);
467 /* clock updates for mode set */
468 /* cursor updates */
469 /* render clock increase/decrease */
470 /* display clock increase/decrease */
471 /* pll clock increase/decrease */
472
473 int (*setup_backlight)(struct intel_connector *connector);
474 uint32_t (*get_backlight)(struct intel_connector *connector);
475 void (*set_backlight)(struct intel_connector *connector,
476 uint32_t level);
477 void (*disable_backlight)(struct intel_connector *connector);
478 void (*enable_backlight)(struct intel_connector *connector);
479 };
480
481 struct intel_uncore_funcs {
482 void (*force_wake_get)(struct drm_i915_private *dev_priv,
483 int fw_engine);
484 void (*force_wake_put)(struct drm_i915_private *dev_priv,
485 int fw_engine);
486
487 uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
488 uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
489 uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
490 uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
491
492 void (*mmio_writeb)(struct drm_i915_private *dev_priv, off_t offset,
493 uint8_t val, bool trace);
494 void (*mmio_writew)(struct drm_i915_private *dev_priv, off_t offset,
495 uint16_t val, bool trace);
496 void (*mmio_writel)(struct drm_i915_private *dev_priv, off_t offset,
497 uint32_t val, bool trace);
498 void (*mmio_writeq)(struct drm_i915_private *dev_priv, off_t offset,
499 uint64_t val, bool trace);
500 };
501
502 struct intel_uncore {
503 spinlock_t lock; /** lock is also taken in irq contexts. */
504
505 struct intel_uncore_funcs funcs;
506
507 unsigned fifo_count;
508 unsigned forcewake_count;
509
510 unsigned fw_rendercount;
511 unsigned fw_mediacount;
512
513 struct timer_list force_wake_timer;
514 };
515
516 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
517 func(is_mobile) sep \
518 func(is_i85x) sep \
519 func(is_i915g) sep \
520 func(is_i945gm) sep \
521 func(is_g33) sep \
522 func(need_gfx_hws) sep \
523 func(is_g4x) sep \
524 func(is_pineview) sep \
525 func(is_broadwater) sep \
526 func(is_crestline) sep \
527 func(is_ivybridge) sep \
528 func(is_valleyview) sep \
529 func(is_haswell) sep \
530 func(is_preliminary) sep \
531 func(has_fbc) sep \
532 func(has_pipe_cxsr) sep \
533 func(has_hotplug) sep \
534 func(cursor_needs_physical) sep \
535 func(has_overlay) sep \
536 func(overlay_needs_physical) sep \
537 func(supports_tv) sep \
538 func(has_llc) sep \
539 func(has_ddi) sep \
540 func(has_fpga_dbg)
541
542 #define DEFINE_FLAG(name) u8 name:1
543 #define SEP_SEMICOLON ;
544
545 struct intel_device_info {
546 u32 display_mmio_offset;
547 u8 num_pipes:3;
548 u8 num_sprites[I915_MAX_PIPES];
549 u8 gen;
550 u8 ring_mask; /* Rings supported by the HW */
551 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
552 /* Register offsets for the various display pipes and transcoders */
553 int pipe_offsets[I915_MAX_TRANSCODERS];
554 int trans_offsets[I915_MAX_TRANSCODERS];
555 int dpll_offsets[I915_MAX_PIPES];
556 int dpll_md_offsets[I915_MAX_PIPES];
557 int palette_offsets[I915_MAX_PIPES];
558 int cursor_offsets[I915_MAX_PIPES];
559 };
560
561 #undef DEFINE_FLAG
562 #undef SEP_SEMICOLON
563
564 enum i915_cache_level {
565 I915_CACHE_NONE = 0,
566 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
567 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
568 caches, eg sampler/render caches, and the
569 large Last-Level-Cache. LLC is coherent with
570 the CPU, but L3 is only visible to the GPU. */
571 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
572 };
573
574 struct i915_ctx_hang_stats {
575 /* This context had batch pending when hang was declared */
576 unsigned batch_pending;
577
578 /* This context had batch active when hang was declared */
579 unsigned batch_active;
580
581 /* Time when this context was last blamed for a GPU reset */
582 unsigned long guilty_ts;
583
584 /* This context is banned to submit more work */
585 bool banned;
586 };
587
588 /* This must match up with the value previously used for execbuf2.rsvd1. */
589 #define DEFAULT_CONTEXT_ID 0
590 struct intel_context {
591 struct kref ref;
592 int id;
593 bool is_initialized;
594 uint8_t remap_slice;
595 struct drm_i915_file_private *file_priv;
596 struct intel_engine_cs *last_ring;
597 struct drm_i915_gem_object *obj;
598 struct i915_ctx_hang_stats hang_stats;
599 struct i915_address_space *vm;
600
601 struct list_head link;
602 };
603
604 struct i915_fbc {
605 unsigned long size;
606 unsigned int fb_id;
607 enum plane plane;
608 int y;
609
610 struct drm_mm_node *compressed_fb;
611 struct drm_mm_node *compressed_llb;
612
613 struct intel_fbc_work {
614 struct delayed_work work;
615 struct drm_crtc *crtc;
616 struct drm_framebuffer *fb;
617 } *fbc_work;
618
619 enum no_fbc_reason {
620 FBC_OK, /* FBC is enabled */
621 FBC_UNSUPPORTED, /* FBC is not supported by this chipset */
622 FBC_NO_OUTPUT, /* no outputs enabled to compress */
623 FBC_STOLEN_TOO_SMALL, /* not enough space for buffers */
624 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
625 FBC_MODE_TOO_LARGE, /* mode too large for compression */
626 FBC_BAD_PLANE, /* fbc not supported on plane */
627 FBC_NOT_TILED, /* buffer not tiled */
628 FBC_MULTIPLE_PIPES, /* more than one pipe active */
629 FBC_MODULE_PARAM,
630 FBC_CHIP_DEFAULT, /* disabled by default on this chip */
631 } no_fbc_reason;
632 };
633
634 struct i915_drrs {
635 struct intel_connector *connector;
636 };
637
638 struct i915_psr {
639 bool sink_support;
640 bool source_ok;
641 };
642
643 enum intel_pch {
644 PCH_NONE = 0, /* No PCH present */
645 PCH_IBX, /* Ibexpeak PCH */
646 PCH_CPT, /* Cougarpoint PCH */
647 PCH_LPT, /* Lynxpoint PCH */
648 PCH_NOP,
649 };
650
651 enum intel_sbi_destination {
652 SBI_ICLK,
653 SBI_MPHY,
654 };
655
656 #define QUIRK_PIPEA_FORCE (1<<0)
657 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
658 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
659 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
660
661 struct intel_fbdev;
662 struct intel_fbc_work;
663
664 struct intel_gmbus {
665 struct i2c_adapter adapter;
666 u32 force_bit;
667 u32 reg0;
668 u32 gpio_reg;
669 struct i2c_algo_bit_data bit_algo;
670 struct drm_i915_private *dev_priv;
671 };
672
673 struct i915_suspend_saved_registers {
674 u8 saveLBB;
675 u32 saveDSPACNTR;
676 u32 saveDSPBCNTR;
677 u32 saveDSPARB;
678 u32 savePIPEACONF;
679 u32 savePIPEBCONF;
680 u32 savePIPEASRC;
681 u32 savePIPEBSRC;
682 u32 saveFPA0;
683 u32 saveFPA1;
684 u32 saveDPLL_A;
685 u32 saveDPLL_A_MD;
686 u32 saveHTOTAL_A;
687 u32 saveHBLANK_A;
688 u32 saveHSYNC_A;
689 u32 saveVTOTAL_A;
690 u32 saveVBLANK_A;
691 u32 saveVSYNC_A;
692 u32 saveBCLRPAT_A;
693 u32 saveTRANSACONF;
694 u32 saveTRANS_HTOTAL_A;
695 u32 saveTRANS_HBLANK_A;
696 u32 saveTRANS_HSYNC_A;
697 u32 saveTRANS_VTOTAL_A;
698 u32 saveTRANS_VBLANK_A;
699 u32 saveTRANS_VSYNC_A;
700 u32 savePIPEASTAT;
701 u32 saveDSPASTRIDE;
702 u32 saveDSPASIZE;
703 u32 saveDSPAPOS;
704 u32 saveDSPAADDR;
705 u32 saveDSPASURF;
706 u32 saveDSPATILEOFF;
707 u32 savePFIT_PGM_RATIOS;
708 u32 saveBLC_HIST_CTL;
709 u32 saveBLC_PWM_CTL;
710 u32 saveBLC_PWM_CTL2;
711 u32 saveBLC_HIST_CTL_B;
712 u32 saveBLC_CPU_PWM_CTL;
713 u32 saveBLC_CPU_PWM_CTL2;
714 u32 saveFPB0;
715 u32 saveFPB1;
716 u32 saveDPLL_B;
717 u32 saveDPLL_B_MD;
718 u32 saveHTOTAL_B;
719 u32 saveHBLANK_B;
720 u32 saveHSYNC_B;
721 u32 saveVTOTAL_B;
722 u32 saveVBLANK_B;
723 u32 saveVSYNC_B;
724 u32 saveBCLRPAT_B;
725 u32 saveTRANSBCONF;
726 u32 saveTRANS_HTOTAL_B;
727 u32 saveTRANS_HBLANK_B;
728 u32 saveTRANS_HSYNC_B;
729 u32 saveTRANS_VTOTAL_B;
730 u32 saveTRANS_VBLANK_B;
731 u32 saveTRANS_VSYNC_B;
732 u32 savePIPEBSTAT;
733 u32 saveDSPBSTRIDE;
734 u32 saveDSPBSIZE;
735 u32 saveDSPBPOS;
736 u32 saveDSPBADDR;
737 u32 saveDSPBSURF;
738 u32 saveDSPBTILEOFF;
739 u32 saveVGA0;
740 u32 saveVGA1;
741 u32 saveVGA_PD;
742 u32 saveVGACNTRL;
743 u32 saveADPA;
744 u32 saveLVDS;
745 u32 savePP_ON_DELAYS;
746 u32 savePP_OFF_DELAYS;
747 u32 saveDVOA;
748 u32 saveDVOB;
749 u32 saveDVOC;
750 u32 savePP_ON;
751 u32 savePP_OFF;
752 u32 savePP_CONTROL;
753 u32 savePP_DIVISOR;
754 u32 savePFIT_CONTROL;
755 u32 save_palette_a[256];
756 u32 save_palette_b[256];
757 u32 saveFBC_CONTROL;
758 u32 saveIER;
759 u32 saveIIR;
760 u32 saveIMR;
761 u32 saveDEIER;
762 u32 saveDEIMR;
763 u32 saveGTIER;
764 u32 saveGTIMR;
765 u32 saveFDI_RXA_IMR;
766 u32 saveFDI_RXB_IMR;
767 u32 saveCACHE_MODE_0;
768 u32 saveMI_ARB_STATE;
769 u32 saveSWF0[16];
770 u32 saveSWF1[16];
771 u32 saveSWF2[3];
772 u8 saveMSR;
773 u8 saveSR[8];
774 u8 saveGR[25];
775 u8 saveAR_INDEX;
776 u8 saveAR[21];
777 u8 saveDACMASK;
778 u8 saveCR[37];
779 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
780 u32 saveCURACNTR;
781 u32 saveCURAPOS;
782 u32 saveCURABASE;
783 u32 saveCURBCNTR;
784 u32 saveCURBPOS;
785 u32 saveCURBBASE;
786 u32 saveCURSIZE;
787 u32 saveDP_B;
788 u32 saveDP_C;
789 u32 saveDP_D;
790 u32 savePIPEA_GMCH_DATA_M;
791 u32 savePIPEB_GMCH_DATA_M;
792 u32 savePIPEA_GMCH_DATA_N;
793 u32 savePIPEB_GMCH_DATA_N;
794 u32 savePIPEA_DP_LINK_M;
795 u32 savePIPEB_DP_LINK_M;
796 u32 savePIPEA_DP_LINK_N;
797 u32 savePIPEB_DP_LINK_N;
798 u32 saveFDI_RXA_CTL;
799 u32 saveFDI_TXA_CTL;
800 u32 saveFDI_RXB_CTL;
801 u32 saveFDI_TXB_CTL;
802 u32 savePFA_CTL_1;
803 u32 savePFB_CTL_1;
804 u32 savePFA_WIN_SZ;
805 u32 savePFB_WIN_SZ;
806 u32 savePFA_WIN_POS;
807 u32 savePFB_WIN_POS;
808 u32 savePCH_DREF_CONTROL;
809 u32 saveDISP_ARB_CTL;
810 u32 savePIPEA_DATA_M1;
811 u32 savePIPEA_DATA_N1;
812 u32 savePIPEA_LINK_M1;
813 u32 savePIPEA_LINK_N1;
814 u32 savePIPEB_DATA_M1;
815 u32 savePIPEB_DATA_N1;
816 u32 savePIPEB_LINK_M1;
817 u32 savePIPEB_LINK_N1;
818 u32 saveMCHBAR_RENDER_STANDBY;
819 u32 savePCH_PORT_HOTPLUG;
820 };
821
822 struct vlv_s0ix_state {
823 /* GAM */
824 u32 wr_watermark;
825 u32 gfx_prio_ctrl;
826 u32 arb_mode;
827 u32 gfx_pend_tlb0;
828 u32 gfx_pend_tlb1;
829 u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
830 u32 media_max_req_count;
831 u32 gfx_max_req_count;
832 u32 render_hwsp;
833 u32 ecochk;
834 u32 bsd_hwsp;
835 u32 blt_hwsp;
836 u32 tlb_rd_addr;
837
838 /* MBC */
839 u32 g3dctl;
840 u32 gsckgctl;
841 u32 mbctl;
842
843 /* GCP */
844 u32 ucgctl1;
845 u32 ucgctl3;
846 u32 rcgctl1;
847 u32 rcgctl2;
848 u32 rstctl;
849 u32 misccpctl;
850
851 /* GPM */
852 u32 gfxpause;
853 u32 rpdeuhwtc;
854 u32 rpdeuc;
855 u32 ecobus;
856 u32 pwrdwnupctl;
857 u32 rp_down_timeout;
858 u32 rp_deucsw;
859 u32 rcubmabdtmr;
860 u32 rcedata;
861 u32 spare2gh;
862
863 /* Display 1 CZ domain */
864 u32 gt_imr;
865 u32 gt_ier;
866 u32 pm_imr;
867 u32 pm_ier;
868 u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
869
870 /* GT SA CZ domain */
871 u32 tilectl;
872 u32 gt_fifoctl;
873 u32 gtlc_wake_ctrl;
874 u32 gtlc_survive;
875 u32 pmwgicz;
876
877 /* Display 2 CZ domain */
878 u32 gu_ctl0;
879 u32 gu_ctl1;
880 u32 clock_gate_dis2;
881 };
882
883 struct intel_gen6_power_mgmt {
884 /* work and pm_iir are protected by dev_priv->irq_lock */
885 struct work_struct work;
886 u32 pm_iir;
887
888 /* Frequencies are stored in potentially platform dependent multiples.
889 * In other words, *_freq needs to be multiplied by X to be interesting.
890 * Soft limits are those which are used for the dynamic reclocking done
891 * by the driver (raise frequencies under heavy loads, and lower for
892 * lighter loads). Hard limits are those imposed by the hardware.
893 *
894 * A distinction is made for overclocking, which is never enabled by
895 * default, and is considered to be above the hard limit if it's
896 * possible at all.
897 */
898 u8 cur_freq; /* Current frequency (cached, may not == HW) */
899 u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */
900 u8 max_freq_softlimit; /* Max frequency permitted by the driver */
901 u8 max_freq; /* Maximum frequency, RP0 if not overclocking */
902 u8 min_freq; /* AKA RPn. Minimum frequency */
903 u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */
904 u8 rp1_freq; /* "less than" RP0 power/freqency */
905 u8 rp0_freq; /* Non-overclocked max frequency. */
906
907 int last_adj;
908 enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
909
910 bool enabled;
911 struct delayed_work delayed_resume_work;
912
913 /*
914 * Protects RPS/RC6 register access and PCU communication.
915 * Must be taken after struct_mutex if nested.
916 */
917 struct mutex hw_lock;
918 };
919
920 /* defined intel_pm.c */
921 extern spinlock_t mchdev_lock;
922
923 struct intel_ilk_power_mgmt {
924 u8 cur_delay;
925 u8 min_delay;
926 u8 max_delay;
927 u8 fmax;
928 u8 fstart;
929
930 u64 last_count1;
931 unsigned long last_time1;
932 unsigned long chipset_power;
933 u64 last_count2;
934 struct timespec last_time2;
935 unsigned long gfx_power;
936 u8 corr;
937
938 int c_m;
939 int r_t;
940
941 struct drm_i915_gem_object *pwrctx;
942 struct drm_i915_gem_object *renderctx;
943 };
944
945 struct drm_i915_private;
946 struct i915_power_well;
947
948 struct i915_power_well_ops {
949 /*
950 * Synchronize the well's hw state to match the current sw state, for
951 * example enable/disable it based on the current refcount. Called
952 * during driver init and resume time, possibly after first calling
953 * the enable/disable handlers.
954 */
955 void (*sync_hw)(struct drm_i915_private *dev_priv,
956 struct i915_power_well *power_well);
957 /*
958 * Enable the well and resources that depend on it (for example
959 * interrupts located on the well). Called after the 0->1 refcount
960 * transition.
961 */
962 void (*enable)(struct drm_i915_private *dev_priv,
963 struct i915_power_well *power_well);
964 /*
965 * Disable the well and resources that depend on it. Called after
966 * the 1->0 refcount transition.
967 */
968 void (*disable)(struct drm_i915_private *dev_priv,
969 struct i915_power_well *power_well);
970 /* Returns the hw enabled state. */
971 bool (*is_enabled)(struct drm_i915_private *dev_priv,
972 struct i915_power_well *power_well);
973 };
974
975 /* Power well structure for haswell */
976 struct i915_power_well {
977 const char *name;
978 bool always_on;
979 /* power well enable/disable usage count */
980 int count;
981 /* cached hw enabled state */
982 bool hw_enabled;
983 unsigned long domains;
984 unsigned long data;
985 const struct i915_power_well_ops *ops;
986 };
987
988 struct i915_power_domains {
989 /*
990 * Power wells needed for initialization at driver init and suspend
991 * time are on. They are kept on until after the first modeset.
992 */
993 bool init_power_on;
994 bool initializing;
995 int power_well_count;
996
997 struct mutex lock;
998 int domain_use_count[POWER_DOMAIN_NUM];
999 struct i915_power_well *power_wells;
1000 };
1001
1002 struct i915_dri1_state {
1003 unsigned allow_batchbuffer : 1;
1004 u32 __iomem *gfx_hws_cpu_addr;
1005
1006 unsigned int cpp;
1007 int back_offset;
1008 int front_offset;
1009 int current_page;
1010 int page_flipping;
1011
1012 uint32_t counter;
1013 };
1014
1015 struct i915_ums_state {
1016 /**
1017 * Flag if the X Server, and thus DRM, is not currently in
1018 * control of the device.
1019 *
1020 * This is set between LeaveVT and EnterVT. It needs to be
1021 * replaced with a semaphore. It also needs to be
1022 * transitioned away from for kernel modesetting.
1023 */
1024 int mm_suspended;
1025 };
1026
1027 #define MAX_L3_SLICES 2
1028 struct intel_l3_parity {
1029 u32 *remap_info[MAX_L3_SLICES];
1030 struct work_struct error_work;
1031 int which_slice;
1032 };
1033
1034 struct i915_gem_mm {
1035 /** Memory allocator for GTT stolen memory */
1036 struct drm_mm stolen;
1037 /** List of all objects in gtt_space. Used to restore gtt
1038 * mappings on resume */
1039 struct list_head bound_list;
1040 /**
1041 * List of objects which are not bound to the GTT (thus
1042 * are idle and not used by the GPU) but still have
1043 * (presumably uncached) pages still attached.
1044 */
1045 struct list_head unbound_list;
1046
1047 /** Usable portion of the GTT for GEM */
1048 unsigned long stolen_base; /* limited to low memory (32-bit) */
1049
1050 /** PPGTT used for aliasing the PPGTT with the GTT */
1051 struct i915_hw_ppgtt *aliasing_ppgtt;
1052
1053 struct notifier_block oom_notifier;
1054 struct shrinker shrinker;
1055 bool shrinker_no_lock_stealing;
1056
1057 /** LRU list of objects with fence regs on them. */
1058 struct list_head fence_list;
1059
1060 /**
1061 * We leave the user IRQ off as much as possible,
1062 * but this means that requests will finish and never
1063 * be retired once the system goes idle. Set a timer to
1064 * fire periodically while the ring is running. When it
1065 * fires, go retire requests.
1066 */
1067 struct delayed_work retire_work;
1068
1069 /**
1070 * When we detect an idle GPU, we want to turn on
1071 * powersaving features. So once we see that there
1072 * are no more requests outstanding and no more
1073 * arrive within a small period of time, we fire
1074 * off the idle_work.
1075 */
1076 struct delayed_work idle_work;
1077
1078 /**
1079 * Are we in a non-interruptible section of code like
1080 * modesetting?
1081 */
1082 bool interruptible;
1083
1084 /**
1085 * Is the GPU currently considered idle, or busy executing userspace
1086 * requests? Whilst idle, we attempt to power down the hardware and
1087 * display clocks. In order to reduce the effect on performance, there
1088 * is a slight delay before we do so.
1089 */
1090 bool busy;
1091
1092 /* the indicator for dispatch video commands on two BSD rings */
1093 int bsd_ring_dispatch_index;
1094
1095 /** Bit 6 swizzling required for X tiling */
1096 uint32_t bit_6_swizzle_x;
1097 /** Bit 6 swizzling required for Y tiling */
1098 uint32_t bit_6_swizzle_y;
1099
1100 /* accounting, useful for userland debugging */
1101 spinlock_t object_stat_lock;
1102 size_t object_memory;
1103 u32 object_count;
1104 };
1105
1106 struct drm_i915_error_state_buf {
1107 unsigned bytes;
1108 unsigned size;
1109 int err;
1110 u8 *buf;
1111 loff_t start;
1112 loff_t pos;
1113 };
1114
1115 struct i915_error_state_file_priv {
1116 struct drm_device *dev;
1117 struct drm_i915_error_state *error;
1118 };
1119
1120 struct i915_gpu_error {
1121 /* For hangcheck timer */
1122 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1123 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1124 /* Hang gpu twice in this window and your context gets banned */
1125 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1126
1127 struct timer_list hangcheck_timer;
1128
1129 /* For reset and error_state handling. */
1130 spinlock_t lock;
1131 /* Protected by the above dev->gpu_error.lock. */
1132 struct drm_i915_error_state *first_error;
1133 struct work_struct work;
1134
1135
1136 unsigned long missed_irq_rings;
1137
1138 /**
1139 * State variable controlling the reset flow and count
1140 *
1141 * This is a counter which gets incremented when reset is triggered,
1142 * and again when reset has been handled. So odd values (lowest bit set)
1143 * means that reset is in progress and even values that
1144 * (reset_counter >> 1):th reset was successfully completed.
1145 *
1146 * If reset is not completed succesfully, the I915_WEDGE bit is
1147 * set meaning that hardware is terminally sour and there is no
1148 * recovery. All waiters on the reset_queue will be woken when
1149 * that happens.
1150 *
1151 * This counter is used by the wait_seqno code to notice that reset
1152 * event happened and it needs to restart the entire ioctl (since most
1153 * likely the seqno it waited for won't ever signal anytime soon).
1154 *
1155 * This is important for lock-free wait paths, where no contended lock
1156 * naturally enforces the correct ordering between the bail-out of the
1157 * waiter and the gpu reset work code.
1158 */
1159 atomic_t reset_counter;
1160
1161 #define I915_RESET_IN_PROGRESS_FLAG 1
1162 #define I915_WEDGED (1 << 31)
1163
1164 /**
1165 * Waitqueue to signal when the reset has completed. Used by clients
1166 * that wait for dev_priv->mm.wedged to settle.
1167 */
1168 wait_queue_head_t reset_queue;
1169
1170 /* Userspace knobs for gpu hang simulation;
1171 * combines both a ring mask, and extra flags
1172 */
1173 u32 stop_rings;
1174 #define I915_STOP_RING_ALLOW_BAN (1 << 31)
1175 #define I915_STOP_RING_ALLOW_WARN (1 << 30)
1176
1177 /* For missed irq/seqno simulation. */
1178 unsigned int test_irq_rings;
1179 };
1180
1181 enum modeset_restore {
1182 MODESET_ON_LID_OPEN,
1183 MODESET_DONE,
1184 MODESET_SUSPENDED,
1185 };
1186
1187 struct ddi_vbt_port_info {
1188 uint8_t hdmi_level_shift;
1189
1190 uint8_t supports_dvi:1;
1191 uint8_t supports_hdmi:1;
1192 uint8_t supports_dp:1;
1193 };
1194
1195 enum drrs_support_type {
1196 DRRS_NOT_SUPPORTED = 0,
1197 STATIC_DRRS_SUPPORT = 1,
1198 SEAMLESS_DRRS_SUPPORT = 2
1199 };
1200
1201 struct intel_vbt_data {
1202 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1203 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1204
1205 /* Feature bits */
1206 unsigned int int_tv_support:1;
1207 unsigned int lvds_dither:1;
1208 unsigned int lvds_vbt:1;
1209 unsigned int int_crt_support:1;
1210 unsigned int lvds_use_ssc:1;
1211 unsigned int display_clock_mode:1;
1212 unsigned int fdi_rx_polarity_inverted:1;
1213 unsigned int has_mipi:1;
1214 int lvds_ssc_freq;
1215 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1216
1217 enum drrs_support_type drrs_type;
1218
1219 /* eDP */
1220 int edp_rate;
1221 int edp_lanes;
1222 int edp_preemphasis;
1223 int edp_vswing;
1224 bool edp_initialized;
1225 bool edp_support;
1226 int edp_bpp;
1227 struct edp_power_seq edp_pps;
1228
1229 struct {
1230 u16 pwm_freq_hz;
1231 bool present;
1232 bool active_low_pwm;
1233 } backlight;
1234
1235 /* MIPI DSI */
1236 struct {
1237 u16 port;
1238 u16 panel_id;
1239 struct mipi_config *config;
1240 struct mipi_pps_data *pps;
1241 u8 seq_version;
1242 u32 size;
1243 u8 *data;
1244 u8 *sequence[MIPI_SEQ_MAX];
1245 } dsi;
1246
1247 int crt_ddc_pin;
1248
1249 int child_dev_num;
1250 union child_device_config *child_dev;
1251
1252 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1253 };
1254
1255 enum intel_ddb_partitioning {
1256 INTEL_DDB_PART_1_2,
1257 INTEL_DDB_PART_5_6, /* IVB+ */
1258 };
1259
1260 struct intel_wm_level {
1261 bool enable;
1262 uint32_t pri_val;
1263 uint32_t spr_val;
1264 uint32_t cur_val;
1265 uint32_t fbc_val;
1266 };
1267
1268 struct ilk_wm_values {
1269 uint32_t wm_pipe[3];
1270 uint32_t wm_lp[3];
1271 uint32_t wm_lp_spr[3];
1272 uint32_t wm_linetime[3];
1273 bool enable_fbc_wm;
1274 enum intel_ddb_partitioning partitioning;
1275 };
1276
1277 /*
1278 * This struct helps tracking the state needed for runtime PM, which puts the
1279 * device in PCI D3 state. Notice that when this happens, nothing on the
1280 * graphics device works, even register access, so we don't get interrupts nor
1281 * anything else.
1282 *
1283 * Every piece of our code that needs to actually touch the hardware needs to
1284 * either call intel_runtime_pm_get or call intel_display_power_get with the
1285 * appropriate power domain.
1286 *
1287 * Our driver uses the autosuspend delay feature, which means we'll only really
1288 * suspend if we stay with zero refcount for a certain amount of time. The
1289 * default value is currently very conservative (see intel_init_runtime_pm), but
1290 * it can be changed with the standard runtime PM files from sysfs.
1291 *
1292 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1293 * goes back to false exactly before we reenable the IRQs. We use this variable
1294 * to check if someone is trying to enable/disable IRQs while they're supposed
1295 * to be disabled. This shouldn't happen and we'll print some error messages in
1296 * case it happens.
1297 *
1298 * For more, read the Documentation/power/runtime_pm.txt.
1299 */
1300 struct i915_runtime_pm {
1301 bool suspended;
1302 bool irqs_disabled;
1303 };
1304
1305 enum intel_pipe_crc_source {
1306 INTEL_PIPE_CRC_SOURCE_NONE,
1307 INTEL_PIPE_CRC_SOURCE_PLANE1,
1308 INTEL_PIPE_CRC_SOURCE_PLANE2,
1309 INTEL_PIPE_CRC_SOURCE_PF,
1310 INTEL_PIPE_CRC_SOURCE_PIPE,
1311 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1312 INTEL_PIPE_CRC_SOURCE_TV,
1313 INTEL_PIPE_CRC_SOURCE_DP_B,
1314 INTEL_PIPE_CRC_SOURCE_DP_C,
1315 INTEL_PIPE_CRC_SOURCE_DP_D,
1316 INTEL_PIPE_CRC_SOURCE_AUTO,
1317 INTEL_PIPE_CRC_SOURCE_MAX,
1318 };
1319
1320 struct intel_pipe_crc_entry {
1321 uint32_t frame;
1322 uint32_t crc[5];
1323 };
1324
1325 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1326 struct intel_pipe_crc {
1327 spinlock_t lock;
1328 bool opened; /* exclusive access to the result file */
1329 struct intel_pipe_crc_entry *entries;
1330 enum intel_pipe_crc_source source;
1331 int head, tail;
1332 wait_queue_head_t wq;
1333 };
1334
1335 struct drm_i915_private {
1336 struct drm_device *dev;
1337 struct kmem_cache *slab;
1338
1339 const struct intel_device_info info;
1340
1341 int relative_constants_mode;
1342
1343 void __iomem *regs;
1344
1345 struct intel_uncore uncore;
1346
1347 struct intel_gmbus gmbus[GMBUS_NUM_PORTS];
1348
1349
1350 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1351 * controller on different i2c buses. */
1352 struct mutex gmbus_mutex;
1353
1354 /**
1355 * Base address of the gmbus and gpio block.
1356 */
1357 uint32_t gpio_mmio_base;
1358
1359 /* MMIO base address for MIPI regs */
1360 uint32_t mipi_mmio_base;
1361
1362 wait_queue_head_t gmbus_wait_queue;
1363
1364 struct pci_dev *bridge_dev;
1365 struct intel_engine_cs ring[I915_NUM_RINGS];
1366 uint32_t last_seqno, next_seqno;
1367
1368 drm_dma_handle_t *status_page_dmah;
1369 struct resource mch_res;
1370
1371 /* protects the irq masks */
1372 spinlock_t irq_lock;
1373
1374 bool display_irqs_enabled;
1375
1376 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1377 struct pm_qos_request pm_qos;
1378
1379 /* DPIO indirect register protection */
1380 struct mutex dpio_lock;
1381
1382 /** Cached value of IMR to avoid reads in updating the bitfield */
1383 union {
1384 u32 irq_mask;
1385 u32 de_irq_mask[I915_MAX_PIPES];
1386 };
1387 u32 gt_irq_mask;
1388 u32 pm_irq_mask;
1389 u32 pm_rps_events;
1390 u32 pipestat_irq_mask[I915_MAX_PIPES];
1391
1392 struct work_struct hotplug_work;
1393 bool enable_hotplug_processing;
1394 struct {
1395 unsigned long hpd_last_jiffies;
1396 int hpd_cnt;
1397 enum {
1398 HPD_ENABLED = 0,
1399 HPD_DISABLED = 1,
1400 HPD_MARK_DISABLED = 2
1401 } hpd_mark;
1402 } hpd_stats[HPD_NUM_PINS];
1403 u32 hpd_event_bits;
1404 struct timer_list hotplug_reenable_timer;
1405
1406 struct i915_fbc fbc;
1407 struct i915_drrs drrs;
1408 struct intel_opregion opregion;
1409 struct intel_vbt_data vbt;
1410
1411 /* overlay */
1412 struct intel_overlay *overlay;
1413
1414 /* backlight registers and fields in struct intel_panel */
1415 spinlock_t backlight_lock;
1416
1417 /* LVDS info */
1418 bool no_aux_handshake;
1419
1420 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
1421 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
1422 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
1423
1424 unsigned int fsb_freq, mem_freq, is_ddr3;
1425 unsigned int vlv_cdclk_freq;
1426
1427 /**
1428 * wq - Driver workqueue for GEM.
1429 *
1430 * NOTE: Work items scheduled here are not allowed to grab any modeset
1431 * locks, for otherwise the flushing done in the pageflip code will
1432 * result in deadlocks.
1433 */
1434 struct workqueue_struct *wq;
1435
1436 /* Display functions */
1437 struct drm_i915_display_funcs display;
1438
1439 /* PCH chipset type */
1440 enum intel_pch pch_type;
1441 unsigned short pch_id;
1442
1443 unsigned long quirks;
1444
1445 enum modeset_restore modeset_restore;
1446 struct mutex modeset_restore_lock;
1447
1448 struct list_head vm_list; /* Global list of all address spaces */
1449 struct i915_gtt gtt; /* VM representing the global address space */
1450
1451 struct i915_gem_mm mm;
1452 #if defined(CONFIG_MMU_NOTIFIER)
1453 DECLARE_HASHTABLE(mmu_notifiers, 7);
1454 #endif
1455
1456 /* Kernel Modesetting */
1457
1458 struct sdvo_device_mapping sdvo_mappings[2];
1459
1460 struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
1461 struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1462 wait_queue_head_t pending_flip_queue;
1463
1464 #ifdef CONFIG_DEBUG_FS
1465 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1466 #endif
1467
1468 int num_shared_dpll;
1469 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1470 struct intel_ddi_plls ddi_plls;
1471 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1472
1473 /* Reclocking support */
1474 bool render_reclock_avail;
1475 bool lvds_downclock_avail;
1476 /* indicates the reduced downclock for LVDS*/
1477 int lvds_downclock;
1478 u16 orig_clock;
1479
1480 bool mchbar_need_disable;
1481
1482 struct intel_l3_parity l3_parity;
1483
1484 /* Cannot be determined by PCIID. You must always read a register. */
1485 size_t ellc_size;
1486
1487 /* gen6+ rps state */
1488 struct intel_gen6_power_mgmt rps;
1489
1490 /* ilk-only ips/rps state. Everything in here is protected by the global
1491 * mchdev_lock in intel_pm.c */
1492 struct intel_ilk_power_mgmt ips;
1493
1494 struct i915_power_domains power_domains;
1495
1496 struct i915_psr psr;
1497
1498 struct i915_gpu_error gpu_error;
1499
1500 struct drm_i915_gem_object *vlv_pctx;
1501
1502 #ifdef CONFIG_DRM_I915_FBDEV
1503 /* list of fbdev register on this device */
1504 struct intel_fbdev *fbdev;
1505 #endif
1506
1507 /*
1508 * The console may be contended at resume, but we don't
1509 * want it to block on it.
1510 */
1511 struct work_struct console_resume_work;
1512
1513 struct drm_property *broadcast_rgb_property;
1514 struct drm_property *force_audio_property;
1515
1516 uint32_t hw_context_size;
1517 struct list_head context_list;
1518
1519 u32 fdi_rx_config;
1520
1521 u32 suspend_count;
1522 struct i915_suspend_saved_registers regfile;
1523 struct vlv_s0ix_state vlv_s0ix_state;
1524
1525 struct {
1526 /*
1527 * Raw watermark latency values:
1528 * in 0.1us units for WM0,
1529 * in 0.5us units for WM1+.
1530 */
1531 /* primary */
1532 uint16_t pri_latency[5];
1533 /* sprite */
1534 uint16_t spr_latency[5];
1535 /* cursor */
1536 uint16_t cur_latency[5];
1537
1538 /* current hardware state */
1539 struct ilk_wm_values hw;
1540 } wm;
1541
1542 struct i915_runtime_pm pm;
1543
1544 /* Old dri1 support infrastructure, beware the dragons ya fools entering
1545 * here! */
1546 struct i915_dri1_state dri1;
1547 /* Old ums support infrastructure, same warning applies. */
1548 struct i915_ums_state ums;
1549
1550 /*
1551 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
1552 * will be rejected. Instead look for a better place.
1553 */
1554 };
1555
1556 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
1557 {
1558 return dev->dev_private;
1559 }
1560
1561 /* Iterate over initialised rings */
1562 #define for_each_ring(ring__, dev_priv__, i__) \
1563 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
1564 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
1565
1566 enum hdmi_force_audio {
1567 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
1568 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
1569 HDMI_AUDIO_AUTO, /* trust EDID */
1570 HDMI_AUDIO_ON, /* force turn on HDMI audio */
1571 };
1572
1573 #define I915_GTT_OFFSET_NONE ((u32)-1)
1574
1575 struct drm_i915_gem_object_ops {
1576 /* Interface between the GEM object and its backing storage.
1577 * get_pages() is called once prior to the use of the associated set
1578 * of pages before to binding them into the GTT, and put_pages() is
1579 * called after we no longer need them. As we expect there to be
1580 * associated cost with migrating pages between the backing storage
1581 * and making them available for the GPU (e.g. clflush), we may hold
1582 * onto the pages after they are no longer referenced by the GPU
1583 * in case they may be used again shortly (for example migrating the
1584 * pages to a different memory domain within the GTT). put_pages()
1585 * will therefore most likely be called when the object itself is
1586 * being released or under memory pressure (where we attempt to
1587 * reap pages for the shrinker).
1588 */
1589 int (*get_pages)(struct drm_i915_gem_object *);
1590 void (*put_pages)(struct drm_i915_gem_object *);
1591 int (*dmabuf_export)(struct drm_i915_gem_object *);
1592 void (*release)(struct drm_i915_gem_object *);
1593 };
1594
1595 struct drm_i915_gem_object {
1596 struct drm_gem_object base;
1597
1598 const struct drm_i915_gem_object_ops *ops;
1599
1600 /** List of VMAs backed by this object */
1601 struct list_head vma_list;
1602
1603 /** Stolen memory for this object, instead of being backed by shmem. */
1604 struct drm_mm_node *stolen;
1605 struct list_head global_list;
1606
1607 struct list_head ring_list;
1608 /** Used in execbuf to temporarily hold a ref */
1609 struct list_head obj_exec_link;
1610
1611 /**
1612 * This is set if the object is on the active lists (has pending
1613 * rendering and so a non-zero seqno), and is not set if it i s on
1614 * inactive (ready to be unbound) list.
1615 */
1616 unsigned int active:1;
1617
1618 /**
1619 * This is set if the object has been written to since last bound
1620 * to the GTT
1621 */
1622 unsigned int dirty:1;
1623
1624 /**
1625 * Fence register bits (if any) for this object. Will be set
1626 * as needed when mapped into the GTT.
1627 * Protected by dev->struct_mutex.
1628 */
1629 signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
1630
1631 /**
1632 * Advice: are the backing pages purgeable?
1633 */
1634 unsigned int madv:2;
1635
1636 /**
1637 * Current tiling mode for the object.
1638 */
1639 unsigned int tiling_mode:2;
1640 /**
1641 * Whether the tiling parameters for the currently associated fence
1642 * register have changed. Note that for the purposes of tracking
1643 * tiling changes we also treat the unfenced register, the register
1644 * slot that the object occupies whilst it executes a fenced
1645 * command (such as BLT on gen2/3), as a "fence".
1646 */
1647 unsigned int fence_dirty:1;
1648
1649 /**
1650 * Is the object at the current location in the gtt mappable and
1651 * fenceable? Used to avoid costly recalculations.
1652 */
1653 unsigned int map_and_fenceable:1;
1654
1655 /**
1656 * Whether the current gtt mapping needs to be mappable (and isn't just
1657 * mappable by accident). Track pin and fault separate for a more
1658 * accurate mappable working set.
1659 */
1660 unsigned int fault_mappable:1;
1661 unsigned int pin_mappable:1;
1662 unsigned int pin_display:1;
1663
1664 /*
1665 * Is the GPU currently using a fence to access this buffer,
1666 */
1667 unsigned int pending_fenced_gpu_access:1;
1668 unsigned int fenced_gpu_access:1;
1669
1670 unsigned int cache_level:3;
1671
1672 unsigned int has_aliasing_ppgtt_mapping:1;
1673 unsigned int has_global_gtt_mapping:1;
1674 unsigned int has_dma_mapping:1;
1675
1676 struct sg_table *pages;
1677 int pages_pin_count;
1678
1679 /* prime dma-buf support */
1680 void *dma_buf_vmapping;
1681 int vmapping_count;
1682
1683 struct intel_engine_cs *ring;
1684
1685 /** Breadcrumb of last rendering to the buffer. */
1686 uint32_t last_read_seqno;
1687 uint32_t last_write_seqno;
1688 /** Breadcrumb of last fenced GPU access to the buffer. */
1689 uint32_t last_fenced_seqno;
1690
1691 /** Current tiling stride for the object, if it's tiled. */
1692 uint32_t stride;
1693
1694 /** References from framebuffers, locks out tiling changes. */
1695 unsigned long framebuffer_references;
1696
1697 /** Record of address bit 17 of each page at last unbind. */
1698 unsigned long *bit_17;
1699
1700 /** User space pin count and filp owning the pin */
1701 unsigned long user_pin_count;
1702 struct drm_file *pin_filp;
1703
1704 /** for phy allocated objects */
1705 drm_dma_handle_t *phys_handle;
1706
1707 union {
1708 struct i915_gem_userptr {
1709 uintptr_t ptr;
1710 unsigned read_only :1;
1711 unsigned workers :4;
1712 #define I915_GEM_USERPTR_MAX_WORKERS 15
1713
1714 struct mm_struct *mm;
1715 struct i915_mmu_object *mn;
1716 struct work_struct *work;
1717 } userptr;
1718 };
1719 };
1720 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
1721
1722 /**
1723 * Request queue structure.
1724 *
1725 * The request queue allows us to note sequence numbers that have been emitted
1726 * and may be associated with active buffers to be retired.
1727 *
1728 * By keeping this list, we can avoid having to do questionable
1729 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
1730 * an emission time with seqnos for tracking how far ahead of the GPU we are.
1731 */
1732 struct drm_i915_gem_request {
1733 /** On Which ring this request was generated */
1734 struct intel_engine_cs *ring;
1735
1736 /** GEM sequence number associated with this request. */
1737 uint32_t seqno;
1738
1739 /** Position in the ringbuffer of the start of the request */
1740 u32 head;
1741
1742 /** Position in the ringbuffer of the end of the request */
1743 u32 tail;
1744
1745 /** Context related to this request */
1746 struct intel_context *ctx;
1747
1748 /** Batch buffer related to this request if any */
1749 struct drm_i915_gem_object *batch_obj;
1750
1751 /** Time at which this request was emitted, in jiffies. */
1752 unsigned long emitted_jiffies;
1753
1754 /** global list entry for this request */
1755 struct list_head list;
1756
1757 struct drm_i915_file_private *file_priv;
1758 /** file_priv list entry for this request */
1759 struct list_head client_list;
1760 };
1761
1762 struct drm_i915_file_private {
1763 struct drm_i915_private *dev_priv;
1764 struct drm_file *file;
1765
1766 struct {
1767 spinlock_t lock;
1768 struct list_head request_list;
1769 struct delayed_work idle_work;
1770 } mm;
1771 struct idr context_idr;
1772
1773 atomic_t rps_wait_boost;
1774 struct intel_engine_cs *bsd_ring;
1775 };
1776
1777 /*
1778 * A command that requires special handling by the command parser.
1779 */
1780 struct drm_i915_cmd_descriptor {
1781 /*
1782 * Flags describing how the command parser processes the command.
1783 *
1784 * CMD_DESC_FIXED: The command has a fixed length if this is set,
1785 * a length mask if not set
1786 * CMD_DESC_SKIP: The command is allowed but does not follow the
1787 * standard length encoding for the opcode range in
1788 * which it falls
1789 * CMD_DESC_REJECT: The command is never allowed
1790 * CMD_DESC_REGISTER: The command should be checked against the
1791 * register whitelist for the appropriate ring
1792 * CMD_DESC_MASTER: The command is allowed if the submitting process
1793 * is the DRM master
1794 */
1795 u32 flags;
1796 #define CMD_DESC_FIXED (1<<0)
1797 #define CMD_DESC_SKIP (1<<1)
1798 #define CMD_DESC_REJECT (1<<2)
1799 #define CMD_DESC_REGISTER (1<<3)
1800 #define CMD_DESC_BITMASK (1<<4)
1801 #define CMD_DESC_MASTER (1<<5)
1802
1803 /*
1804 * The command's unique identification bits and the bitmask to get them.
1805 * This isn't strictly the opcode field as defined in the spec and may
1806 * also include type, subtype, and/or subop fields.
1807 */
1808 struct {
1809 u32 value;
1810 u32 mask;
1811 } cmd;
1812
1813 /*
1814 * The command's length. The command is either fixed length (i.e. does
1815 * not include a length field) or has a length field mask. The flag
1816 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
1817 * a length mask. All command entries in a command table must include
1818 * length information.
1819 */
1820 union {
1821 u32 fixed;
1822 u32 mask;
1823 } length;
1824
1825 /*
1826 * Describes where to find a register address in the command to check
1827 * against the ring's register whitelist. Only valid if flags has the
1828 * CMD_DESC_REGISTER bit set.
1829 */
1830 struct {
1831 u32 offset;
1832 u32 mask;
1833 } reg;
1834
1835 #define MAX_CMD_DESC_BITMASKS 3
1836 /*
1837 * Describes command checks where a particular dword is masked and
1838 * compared against an expected value. If the command does not match
1839 * the expected value, the parser rejects it. Only valid if flags has
1840 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
1841 * are valid.
1842 *
1843 * If the check specifies a non-zero condition_mask then the parser
1844 * only performs the check when the bits specified by condition_mask
1845 * are non-zero.
1846 */
1847 struct {
1848 u32 offset;
1849 u32 mask;
1850 u32 expected;
1851 u32 condition_offset;
1852 u32 condition_mask;
1853 } bits[MAX_CMD_DESC_BITMASKS];
1854 };
1855
1856 /*
1857 * A table of commands requiring special handling by the command parser.
1858 *
1859 * Each ring has an array of tables. Each table consists of an array of command
1860 * descriptors, which must be sorted with command opcodes in ascending order.
1861 */
1862 struct drm_i915_cmd_table {
1863 const struct drm_i915_cmd_descriptor *table;
1864 int count;
1865 };
1866
1867 #define INTEL_INFO(dev) (&to_i915(dev)->info)
1868
1869 #define IS_I830(dev) ((dev)->pdev->device == 0x3577)
1870 #define IS_845G(dev) ((dev)->pdev->device == 0x2562)
1871 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
1872 #define IS_I865G(dev) ((dev)->pdev->device == 0x2572)
1873 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
1874 #define IS_I915GM(dev) ((dev)->pdev->device == 0x2592)
1875 #define IS_I945G(dev) ((dev)->pdev->device == 0x2772)
1876 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
1877 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
1878 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
1879 #define IS_GM45(dev) ((dev)->pdev->device == 0x2A42)
1880 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
1881 #define IS_PINEVIEW_G(dev) ((dev)->pdev->device == 0xa001)
1882 #define IS_PINEVIEW_M(dev) ((dev)->pdev->device == 0xa011)
1883 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
1884 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
1885 #define IS_IRONLAKE_M(dev) ((dev)->pdev->device == 0x0046)
1886 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
1887 #define IS_IVB_GT1(dev) ((dev)->pdev->device == 0x0156 || \
1888 (dev)->pdev->device == 0x0152 || \
1889 (dev)->pdev->device == 0x015a)
1890 #define IS_SNB_GT1(dev) ((dev)->pdev->device == 0x0102 || \
1891 (dev)->pdev->device == 0x0106 || \
1892 (dev)->pdev->device == 0x010A)
1893 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
1894 #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
1895 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
1896 #define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
1897 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
1898 #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
1899 ((dev)->pdev->device & 0xFF00) == 0x0C00)
1900 #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
1901 (((dev)->pdev->device & 0xf) == 0x2 || \
1902 ((dev)->pdev->device & 0xf) == 0x6 || \
1903 ((dev)->pdev->device & 0xf) == 0xe))
1904 #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
1905 ((dev)->pdev->device & 0xFF00) == 0x0A00)
1906 #define IS_ULT(dev) (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
1907 #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
1908 ((dev)->pdev->device & 0x00F0) == 0x0020)
1909 /* ULX machines are also considered ULT. */
1910 #define IS_HSW_ULX(dev) ((dev)->pdev->device == 0x0A0E || \
1911 (dev)->pdev->device == 0x0A1E)
1912 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
1913
1914 /*
1915 * The genX designation typically refers to the render engine, so render
1916 * capability related checks should use IS_GEN, while display and other checks
1917 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
1918 * chips, etc.).
1919 */
1920 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
1921 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
1922 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
1923 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
1924 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
1925 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
1926 #define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8)
1927
1928 #define RENDER_RING (1<<RCS)
1929 #define BSD_RING (1<<VCS)
1930 #define BLT_RING (1<<BCS)
1931 #define VEBOX_RING (1<<VECS)
1932 #define BSD2_RING (1<<VCS2)
1933 #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING)
1934 #define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING)
1935 #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING)
1936 #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
1937 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
1938 #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
1939 to_i915(dev)->ellc_size)
1940 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
1941
1942 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
1943 #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >= 6 && \
1944 (!IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)))
1945 #define HAS_PPGTT(dev) (INTEL_INFO(dev)->gen >= 7 \
1946 && !IS_GEN8(dev))
1947 #define USES_PPGTT(dev) intel_enable_ppgtt(dev, false)
1948 #define USES_FULL_PPGTT(dev) intel_enable_ppgtt(dev, true)
1949
1950 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
1951 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
1952
1953 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
1954 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
1955 /*
1956 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
1957 * even when in MSI mode. This results in spurious interrupt warnings if the
1958 * legacy irq no. is shared with another device. The kernel then disables that
1959 * interrupt source and so prevents the other device from working properly.
1960 */
1961 #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
1962 #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
1963
1964 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1965 * rows, which changed the alignment requirements and fence programming.
1966 */
1967 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
1968 IS_I915GM(dev)))
1969 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
1970 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
1971 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
1972 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
1973 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
1974
1975 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
1976 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
1977 #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
1978
1979 #define HAS_IPS(dev) (IS_ULT(dev) || IS_BROADWELL(dev))
1980
1981 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
1982 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
1983 #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev))
1984 #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \
1985 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev))
1986
1987 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
1988 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
1989 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
1990 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
1991 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
1992 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
1993
1994 #define INTEL_PCH_TYPE(dev) (to_i915(dev)->pch_type)
1995 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
1996 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
1997 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
1998 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
1999 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
2000
2001 /* DPF == dynamic parity feature */
2002 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
2003 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
2004
2005 #define GT_FREQUENCY_MULTIPLIER 50
2006
2007 #include "i915_trace.h"
2008
2009 extern const struct drm_ioctl_desc i915_ioctls[];
2010 extern int i915_max_ioctl;
2011
2012 extern int i915_suspend(struct drm_device *dev, pm_message_t state);
2013 extern int i915_resume(struct drm_device *dev);
2014 extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
2015 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
2016
2017 /* i915_params.c */
2018 struct i915_params {
2019 int modeset;
2020 int panel_ignore_lid;
2021 unsigned int powersave;
2022 int semaphores;
2023 unsigned int lvds_downclock;
2024 int lvds_channel_mode;
2025 int panel_use_ssc;
2026 int vbt_sdvo_panel_type;
2027 int enable_rc6;
2028 int enable_fbc;
2029 int enable_ppgtt;
2030 int enable_psr;
2031 unsigned int preliminary_hw_support;
2032 int disable_power_well;
2033 int enable_ips;
2034 int invert_brightness;
2035 int enable_cmd_parser;
2036 /* leave bools at the end to not create holes */
2037 bool enable_hangcheck;
2038 bool fastboot;
2039 bool prefault_disable;
2040 bool reset;
2041 bool disable_display;
2042 bool disable_vtd_wa;
2043 };
2044 extern struct i915_params i915 __read_mostly;
2045
2046 /* i915_dma.c */
2047 void i915_update_dri1_breadcrumb(struct drm_device *dev);
2048 extern void i915_kernel_lost_context(struct drm_device * dev);
2049 extern int i915_driver_load(struct drm_device *, unsigned long flags);
2050 extern int i915_driver_unload(struct drm_device *);
2051 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
2052 extern void i915_driver_lastclose(struct drm_device * dev);
2053 extern void i915_driver_preclose(struct drm_device *dev,
2054 struct drm_file *file_priv);
2055 extern void i915_driver_postclose(struct drm_device *dev,
2056 struct drm_file *file_priv);
2057 extern int i915_driver_device_is_agp(struct drm_device * dev);
2058 #ifdef CONFIG_COMPAT
2059 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
2060 unsigned long arg);
2061 #endif
2062 extern int i915_emit_box(struct drm_device *dev,
2063 struct drm_clip_rect *box,
2064 int DR1, int DR4);
2065 extern int intel_gpu_reset(struct drm_device *dev);
2066 extern int i915_reset(struct drm_device *dev);
2067 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
2068 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
2069 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
2070 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
2071 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
2072
2073 extern void intel_console_resume(struct work_struct *work);
2074
2075 /* i915_irq.c */
2076 void i915_queue_hangcheck(struct drm_device *dev);
2077 __printf(3, 4)
2078 void i915_handle_error(struct drm_device *dev, bool wedged,
2079 const char *fmt, ...);
2080
2081 void gen6_set_pm_mask(struct drm_i915_private *dev_priv, u32 pm_iir,
2082 int new_delay);
2083 extern void intel_irq_init(struct drm_device *dev);
2084 extern void intel_hpd_init(struct drm_device *dev);
2085
2086 extern void intel_uncore_sanitize(struct drm_device *dev);
2087 extern void intel_uncore_early_sanitize(struct drm_device *dev);
2088 extern void intel_uncore_init(struct drm_device *dev);
2089 extern void intel_uncore_check_errors(struct drm_device *dev);
2090 extern void intel_uncore_fini(struct drm_device *dev);
2091
2092 void
2093 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2094 u32 status_mask);
2095
2096 void
2097 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2098 u32 status_mask);
2099
2100 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
2101 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
2102
2103 /* i915_gem.c */
2104 int i915_gem_init_ioctl(struct drm_device *dev, void *data,
2105 struct drm_file *file_priv);
2106 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
2107 struct drm_file *file_priv);
2108 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
2109 struct drm_file *file_priv);
2110 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2111 struct drm_file *file_priv);
2112 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
2113 struct drm_file *file_priv);
2114 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2115 struct drm_file *file_priv);
2116 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2117 struct drm_file *file_priv);
2118 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
2119 struct drm_file *file_priv);
2120 int i915_gem_execbuffer(struct drm_device *dev, void *data,
2121 struct drm_file *file_priv);
2122 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
2123 struct drm_file *file_priv);
2124 int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
2125 struct drm_file *file_priv);
2126 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
2127 struct drm_file *file_priv);
2128 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
2129 struct drm_file *file_priv);
2130 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
2131 struct drm_file *file);
2132 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
2133 struct drm_file *file);
2134 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
2135 struct drm_file *file_priv);
2136 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
2137 struct drm_file *file_priv);
2138 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
2139 struct drm_file *file_priv);
2140 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
2141 struct drm_file *file_priv);
2142 int i915_gem_set_tiling(struct drm_device *dev, void *data,
2143 struct drm_file *file_priv);
2144 int i915_gem_get_tiling(struct drm_device *dev, void *data,
2145 struct drm_file *file_priv);
2146 int i915_gem_init_userptr(struct drm_device *dev);
2147 int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
2148 struct drm_file *file);
2149 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
2150 struct drm_file *file_priv);
2151 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
2152 struct drm_file *file_priv);
2153 void i915_gem_load(struct drm_device *dev);
2154 void *i915_gem_object_alloc(struct drm_device *dev);
2155 void i915_gem_object_free(struct drm_i915_gem_object *obj);
2156 void i915_gem_object_init(struct drm_i915_gem_object *obj,
2157 const struct drm_i915_gem_object_ops *ops);
2158 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
2159 size_t size);
2160 void i915_init_vm(struct drm_i915_private *dev_priv,
2161 struct i915_address_space *vm);
2162 void i915_gem_free_object(struct drm_gem_object *obj);
2163 void i915_gem_vma_destroy(struct i915_vma *vma);
2164
2165 #define PIN_MAPPABLE 0x1
2166 #define PIN_NONBLOCK 0x2
2167 #define PIN_GLOBAL 0x4
2168 #define PIN_OFFSET_BIAS 0x8
2169 #define PIN_OFFSET_MASK (~4095)
2170 int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
2171 struct i915_address_space *vm,
2172 uint32_t alignment,
2173 uint64_t flags);
2174 int __must_check i915_vma_unbind(struct i915_vma *vma);
2175 int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
2176 void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv);
2177 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
2178 void i915_gem_lastclose(struct drm_device *dev);
2179
2180 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
2181 int *needs_clflush);
2182
2183 int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
2184 static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
2185 {
2186 struct sg_page_iter sg_iter;
2187
2188 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, n)
2189 return sg_page_iter_page(&sg_iter);
2190
2191 return NULL;
2192 }
2193 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
2194 {
2195 BUG_ON(obj->pages == NULL);
2196 obj->pages_pin_count++;
2197 }
2198 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
2199 {
2200 BUG_ON(obj->pages_pin_count == 0);
2201 obj->pages_pin_count--;
2202 }
2203
2204 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
2205 int i915_gem_object_sync(struct drm_i915_gem_object *obj,
2206 struct intel_engine_cs *to);
2207 void i915_vma_move_to_active(struct i915_vma *vma,
2208 struct intel_engine_cs *ring);
2209 int i915_gem_dumb_create(struct drm_file *file_priv,
2210 struct drm_device *dev,
2211 struct drm_mode_create_dumb *args);
2212 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
2213 uint32_t handle, uint64_t *offset);
2214 /**
2215 * Returns true if seq1 is later than seq2.
2216 */
2217 static inline bool
2218 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
2219 {
2220 return (int32_t)(seq1 - seq2) >= 0;
2221 }
2222
2223 int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
2224 int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
2225 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
2226 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
2227
2228 bool i915_gem_object_pin_fence(struct drm_i915_gem_object *obj);
2229 void i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj);
2230
2231 struct drm_i915_gem_request *
2232 i915_gem_find_active_request(struct intel_engine_cs *ring);
2233
2234 bool i915_gem_retire_requests(struct drm_device *dev);
2235 void i915_gem_retire_requests_ring(struct intel_engine_cs *ring);
2236 int __must_check i915_gem_check_wedge(struct i915_gpu_error *error,
2237 bool interruptible);
2238 static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
2239 {
2240 return unlikely(atomic_read(&error->reset_counter)
2241 & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED));
2242 }
2243
2244 static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
2245 {
2246 return atomic_read(&error->reset_counter) & I915_WEDGED;
2247 }
2248
2249 static inline u32 i915_reset_count(struct i915_gpu_error *error)
2250 {
2251 return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2;
2252 }
2253
2254 static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv)
2255 {
2256 return dev_priv->gpu_error.stop_rings == 0 ||
2257 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_BAN;
2258 }
2259
2260 static inline bool i915_stop_ring_allow_warn(struct drm_i915_private *dev_priv)
2261 {
2262 return dev_priv->gpu_error.stop_rings == 0 ||
2263 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_WARN;
2264 }
2265
2266 void i915_gem_reset(struct drm_device *dev);
2267 bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
2268 int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
2269 int __must_check i915_gem_init(struct drm_device *dev);
2270 int __must_check i915_gem_init_hw(struct drm_device *dev);
2271 int i915_gem_l3_remap(struct intel_engine_cs *ring, int slice);
2272 void i915_gem_init_swizzling(struct drm_device *dev);
2273 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
2274 int __must_check i915_gpu_idle(struct drm_device *dev);
2275 int __must_check i915_gem_suspend(struct drm_device *dev);
2276 int __i915_add_request(struct intel_engine_cs *ring,
2277 struct drm_file *file,
2278 struct drm_i915_gem_object *batch_obj,
2279 u32 *seqno);
2280 #define i915_add_request(ring, seqno) \
2281 __i915_add_request(ring, NULL, NULL, seqno)
2282 int __must_check i915_wait_seqno(struct intel_engine_cs *ring,
2283 uint32_t seqno);
2284 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
2285 int __must_check
2286 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
2287 bool write);
2288 int __must_check
2289 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
2290 int __must_check
2291 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
2292 u32 alignment,
2293 struct intel_engine_cs *pipelined);
2294 void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj);
2295 int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
2296 int align);
2297 int i915_gem_open(struct drm_device *dev, struct drm_file *file);
2298 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
2299
2300 uint32_t
2301 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
2302 uint32_t
2303 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
2304 int tiling_mode, bool fenced);
2305
2306 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
2307 enum i915_cache_level cache_level);
2308
2309 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
2310 struct dma_buf *dma_buf);
2311
2312 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
2313 struct drm_gem_object *gem_obj, int flags);
2314
2315 void i915_gem_restore_fences(struct drm_device *dev);
2316
2317 unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o,
2318 struct i915_address_space *vm);
2319 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o);
2320 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
2321 struct i915_address_space *vm);
2322 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
2323 struct i915_address_space *vm);
2324 struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
2325 struct i915_address_space *vm);
2326 struct i915_vma *
2327 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
2328 struct i915_address_space *vm);
2329
2330 struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj);
2331 static inline bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj) {
2332 struct i915_vma *vma;
2333 list_for_each_entry(vma, &obj->vma_list, vma_link)
2334 if (vma->pin_count > 0)
2335 return true;
2336 return false;
2337 }
2338
2339 /* Some GGTT VM helpers */
2340 #define obj_to_ggtt(obj) \
2341 (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
2342 static inline bool i915_is_ggtt(struct i915_address_space *vm)
2343 {
2344 struct i915_address_space *ggtt =
2345 &((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base;
2346 return vm == ggtt;
2347 }
2348
2349 static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj)
2350 {
2351 return i915_gem_obj_bound(obj, obj_to_ggtt(obj));
2352 }
2353
2354 static inline unsigned long
2355 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *obj)
2356 {
2357 return i915_gem_obj_offset(obj, obj_to_ggtt(obj));
2358 }
2359
2360 static inline unsigned long
2361 i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj)
2362 {
2363 return i915_gem_obj_size(obj, obj_to_ggtt(obj));
2364 }
2365
2366 static inline int __must_check
2367 i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj,
2368 uint32_t alignment,
2369 unsigned flags)
2370 {
2371 return i915_gem_object_pin(obj, obj_to_ggtt(obj), alignment, flags | PIN_GLOBAL);
2372 }
2373
2374 static inline int
2375 i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj)
2376 {
2377 return i915_vma_unbind(i915_gem_obj_to_ggtt(obj));
2378 }
2379
2380 void i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj);
2381
2382 /* i915_gem_context.c */
2383 #define ctx_to_ppgtt(ctx) container_of((ctx)->vm, struct i915_hw_ppgtt, base)
2384 int __must_check i915_gem_context_init(struct drm_device *dev);
2385 void i915_gem_context_fini(struct drm_device *dev);
2386 void i915_gem_context_reset(struct drm_device *dev);
2387 int i915_gem_context_open(struct drm_device *dev, struct drm_file *file);
2388 int i915_gem_context_enable(struct drm_i915_private *dev_priv);
2389 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
2390 int i915_switch_context(struct intel_engine_cs *ring,
2391 struct intel_context *to);
2392 struct intel_context *
2393 i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id);
2394 void i915_gem_context_free(struct kref *ctx_ref);
2395 static inline void i915_gem_context_reference(struct intel_context *ctx)
2396 {
2397 kref_get(&ctx->ref);
2398 }
2399
2400 static inline void i915_gem_context_unreference(struct intel_context *ctx)
2401 {
2402 kref_put(&ctx->ref, i915_gem_context_free);
2403 }
2404
2405 static inline bool i915_gem_context_is_default(const struct intel_context *c)
2406 {
2407 return c->id == DEFAULT_CONTEXT_ID;
2408 }
2409
2410 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
2411 struct drm_file *file);
2412 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
2413 struct drm_file *file);
2414
2415 /* i915_gem_render_state.c */
2416 int i915_gem_render_state_init(struct intel_engine_cs *ring);
2417 /* i915_gem_evict.c */
2418 int __must_check i915_gem_evict_something(struct drm_device *dev,
2419 struct i915_address_space *vm,
2420 int min_size,
2421 unsigned alignment,
2422 unsigned cache_level,
2423 unsigned long start,
2424 unsigned long end,
2425 unsigned flags);
2426 int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
2427 int i915_gem_evict_everything(struct drm_device *dev);
2428
2429 /* belongs in i915_gem_gtt.h */
2430 static inline void i915_gem_chipset_flush(struct drm_device *dev)
2431 {
2432 if (INTEL_INFO(dev)->gen < 6)
2433 intel_gtt_chipset_flush();
2434 }
2435
2436 /* i915_gem_stolen.c */
2437 int i915_gem_init_stolen(struct drm_device *dev);
2438 int i915_gem_stolen_setup_compression(struct drm_device *dev, int size);
2439 void i915_gem_stolen_cleanup_compression(struct drm_device *dev);
2440 void i915_gem_cleanup_stolen(struct drm_device *dev);
2441 struct drm_i915_gem_object *
2442 i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
2443 struct drm_i915_gem_object *
2444 i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
2445 u32 stolen_offset,
2446 u32 gtt_offset,
2447 u32 size);
2448 void i915_gem_object_release_stolen(struct drm_i915_gem_object *obj);
2449
2450 /* i915_gem_tiling.c */
2451 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
2452 {
2453 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2454
2455 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
2456 obj->tiling_mode != I915_TILING_NONE;
2457 }
2458
2459 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
2460 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
2461 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
2462
2463 /* i915_gem_debug.c */
2464 #if WATCH_LISTS
2465 int i915_verify_lists(struct drm_device *dev);
2466 #else
2467 #define i915_verify_lists(dev) 0
2468 #endif
2469
2470 /* i915_debugfs.c */
2471 int i915_debugfs_init(struct drm_minor *minor);
2472 void i915_debugfs_cleanup(struct drm_minor *minor);
2473 #ifdef CONFIG_DEBUG_FS
2474 void intel_display_crc_init(struct drm_device *dev);
2475 #else
2476 static inline void intel_display_crc_init(struct drm_device *dev) {}
2477 #endif
2478
2479 /* i915_gpu_error.c */
2480 __printf(2, 3)
2481 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
2482 int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
2483 const struct i915_error_state_file_priv *error);
2484 int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
2485 size_t count, loff_t pos);
2486 static inline void i915_error_state_buf_release(
2487 struct drm_i915_error_state_buf *eb)
2488 {
2489 kfree(eb->buf);
2490 }
2491 void i915_capture_error_state(struct drm_device *dev, bool wedge,
2492 const char *error_msg);
2493 void i915_error_state_get(struct drm_device *dev,
2494 struct i915_error_state_file_priv *error_priv);
2495 void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
2496 void i915_destroy_error_state(struct drm_device *dev);
2497
2498 void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone);
2499 const char *i915_cache_level_str(int type);
2500
2501 /* i915_cmd_parser.c */
2502 int i915_cmd_parser_get_version(void);
2503 int i915_cmd_parser_init_ring(struct intel_engine_cs *ring);
2504 void i915_cmd_parser_fini_ring(struct intel_engine_cs *ring);
2505 bool i915_needs_cmd_parser(struct intel_engine_cs *ring);
2506 int i915_parse_cmds(struct intel_engine_cs *ring,
2507 struct drm_i915_gem_object *batch_obj,
2508 u32 batch_start_offset,
2509 bool is_master);
2510
2511 /* i915_suspend.c */
2512 extern int i915_save_state(struct drm_device *dev);
2513 extern int i915_restore_state(struct drm_device *dev);
2514
2515 /* i915_ums.c */
2516 void i915_save_display_reg(struct drm_device *dev);
2517 void i915_restore_display_reg(struct drm_device *dev);
2518
2519 /* i915_sysfs.c */
2520 void i915_setup_sysfs(struct drm_device *dev_priv);
2521 void i915_teardown_sysfs(struct drm_device *dev_priv);
2522
2523 /* intel_i2c.c */
2524 extern int intel_setup_gmbus(struct drm_device *dev);
2525 extern void intel_teardown_gmbus(struct drm_device *dev);
2526 static inline bool intel_gmbus_is_port_valid(unsigned port)
2527 {
2528 return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD);
2529 }
2530
2531 extern struct i2c_adapter *intel_gmbus_get_adapter(
2532 struct drm_i915_private *dev_priv, unsigned port);
2533 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
2534 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
2535 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
2536 {
2537 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
2538 }
2539 extern void intel_i2c_reset(struct drm_device *dev);
2540
2541 /* intel_opregion.c */
2542 struct intel_encoder;
2543 #ifdef CONFIG_ACPI
2544 extern int intel_opregion_setup(struct drm_device *dev);
2545 extern void intel_opregion_init(struct drm_device *dev);
2546 extern void intel_opregion_fini(struct drm_device *dev);
2547 extern void intel_opregion_asle_intr(struct drm_device *dev);
2548 extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
2549 bool enable);
2550 extern int intel_opregion_notify_adapter(struct drm_device *dev,
2551 pci_power_t state);
2552 #else
2553 static inline int intel_opregion_setup(struct drm_device *dev) { return 0; }
2554 static inline void intel_opregion_init(struct drm_device *dev) { return; }
2555 static inline void intel_opregion_fini(struct drm_device *dev) { return; }
2556 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
2557 static inline int
2558 intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
2559 {
2560 return 0;
2561 }
2562 static inline int
2563 intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state)
2564 {
2565 return 0;
2566 }
2567 #endif
2568
2569 /* intel_acpi.c */
2570 #ifdef CONFIG_ACPI
2571 extern void intel_register_dsm_handler(void);
2572 extern void intel_unregister_dsm_handler(void);
2573 #else
2574 static inline void intel_register_dsm_handler(void) { return; }
2575 static inline void intel_unregister_dsm_handler(void) { return; }
2576 #endif /* CONFIG_ACPI */
2577
2578 /* modesetting */
2579 extern void intel_modeset_init_hw(struct drm_device *dev);
2580 extern void intel_modeset_suspend_hw(struct drm_device *dev);
2581 extern void intel_modeset_init(struct drm_device *dev);
2582 extern void intel_modeset_gem_init(struct drm_device *dev);
2583 extern void intel_modeset_cleanup(struct drm_device *dev);
2584 extern void intel_connector_unregister(struct intel_connector *);
2585 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
2586 extern void intel_modeset_setup_hw_state(struct drm_device *dev,
2587 bool force_restore);
2588 extern void i915_redisable_vga(struct drm_device *dev);
2589 extern void i915_redisable_vga_power_on(struct drm_device *dev);
2590 extern bool intel_fbc_enabled(struct drm_device *dev);
2591 extern void intel_disable_fbc(struct drm_device *dev);
2592 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
2593 extern void intel_init_pch_refclk(struct drm_device *dev);
2594 extern void gen6_set_rps(struct drm_device *dev, u8 val);
2595 extern void valleyview_set_rps(struct drm_device *dev, u8 val);
2596 extern int valleyview_rps_max_freq(struct drm_i915_private *dev_priv);
2597 extern int valleyview_rps_min_freq(struct drm_i915_private *dev_priv);
2598 extern void intel_detect_pch(struct drm_device *dev);
2599 extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
2600 extern int intel_enable_rc6(const struct drm_device *dev);
2601
2602 extern bool i915_semaphore_is_enabled(struct drm_device *dev);
2603 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
2604 struct drm_file *file);
2605 int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data,
2606 struct drm_file *file);
2607
2608 /* overlay */
2609 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
2610 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
2611 struct intel_overlay_error_state *error);
2612
2613 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
2614 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
2615 struct drm_device *dev,
2616 struct intel_display_error_state *error);
2617
2618 /* On SNB platform, before reading ring registers forcewake bit
2619 * must be set to prevent GT core from power down and stale values being
2620 * returned.
2621 */
2622 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine);
2623 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine);
2624 void assert_force_wake_inactive(struct drm_i915_private *dev_priv);
2625
2626 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val);
2627 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val);
2628
2629 /* intel_sideband.c */
2630 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr);
2631 void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val);
2632 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
2633 u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
2634 void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2635 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
2636 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2637 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
2638 void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2639 u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
2640 void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2641 u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg);
2642 void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2643 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
2644 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
2645 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
2646 enum intel_sbi_destination destination);
2647 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
2648 enum intel_sbi_destination destination);
2649 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
2650 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2651
2652 int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val);
2653 int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val);
2654
2655 #define FORCEWAKE_RENDER (1 << 0)
2656 #define FORCEWAKE_MEDIA (1 << 1)
2657 #define FORCEWAKE_ALL (FORCEWAKE_RENDER | FORCEWAKE_MEDIA)
2658
2659
2660 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
2661 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
2662
2663 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
2664 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
2665 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
2666 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
2667
2668 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
2669 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
2670 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
2671 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
2672
2673 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
2674 * will be implemented using 2 32-bit writes in an arbitrary order with
2675 * an arbitrary delay between them. This can cause the hardware to
2676 * act upon the intermediate value, possibly leading to corruption and
2677 * machine death. You have been warned.
2678 */
2679 #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
2680 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
2681
2682 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
2683 u32 upper = I915_READ(upper_reg); \
2684 u32 lower = I915_READ(lower_reg); \
2685 u32 tmp = I915_READ(upper_reg); \
2686 if (upper != tmp) { \
2687 upper = tmp; \
2688 lower = I915_READ(lower_reg); \
2689 WARN_ON(I915_READ(upper_reg) != upper); \
2690 } \
2691 (u64)upper << 32 | lower; })
2692
2693 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
2694 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
2695
2696 /* "Broadcast RGB" property */
2697 #define INTEL_BROADCAST_RGB_AUTO 0
2698 #define INTEL_BROADCAST_RGB_FULL 1
2699 #define INTEL_BROADCAST_RGB_LIMITED 2
2700
2701 static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev)
2702 {
2703 if (HAS_PCH_SPLIT(dev))
2704 return CPU_VGACNTRL;
2705 else if (IS_VALLEYVIEW(dev))
2706 return VLV_VGACNTRL;
2707 else
2708 return VGACNTRL;
2709 }
2710
2711 static inline void __user *to_user_ptr(u64 address)
2712 {
2713 return (void __user *)(uintptr_t)address;
2714 }
2715
2716 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
2717 {
2718 unsigned long j = msecs_to_jiffies(m);
2719
2720 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
2721 }
2722
2723 static inline unsigned long
2724 timespec_to_jiffies_timeout(const struct timespec *value)
2725 {
2726 unsigned long j = timespec_to_jiffies(value);
2727
2728 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
2729 }
2730
2731 /*
2732 * If you need to wait X milliseconds between events A and B, but event B
2733 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
2734 * when event A happened, then just before event B you call this function and
2735 * pass the timestamp as the first argument, and X as the second argument.
2736 */
2737 static inline void
2738 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
2739 {
2740 unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
2741
2742 /*
2743 * Don't re-read the value of "jiffies" every time since it may change
2744 * behind our back and break the math.
2745 */
2746 tmp_jiffies = jiffies;
2747 target_jiffies = timestamp_jiffies +
2748 msecs_to_jiffies_timeout(to_wait_ms);
2749
2750 if (time_after(target_jiffies, tmp_jiffies)) {
2751 remaining_jiffies = target_jiffies - tmp_jiffies;
2752 while (remaining_jiffies)
2753 remaining_jiffies =
2754 schedule_timeout_uninterruptible(remaining_jiffies);
2755 }
2756 }
2757
2758 #endif
Linux kernel - Deliverables
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