1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
34 #include <uapi/drm/drm_fourcc.h>
36 #include <linux/io-mapping.h>
37 #include <linux/i2c.h>
38 #include <linux/i2c-algo-bit.h>
39 #include <linux/backlight.h>
40 #include <linux/hashtable.h>
41 #include <linux/intel-iommu.h>
42 #include <linux/kref.h>
43 #include <linux/pm_qos.h>
44 #include <linux/shmem_fs.h>
47 #include <drm/intel-gtt.h>
48 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
49 #include <drm/drm_gem.h>
50 #include <drm/drm_auth.h>
52 #include "i915_params.h"
55 #include "intel_bios.h"
56 #include "intel_dpll_mgr.h"
57 #include "intel_guc.h"
58 #include "intel_lrc.h"
59 #include "intel_ringbuffer.h"
62 #include "i915_gem_gtt.h"
63 #include "i915_gem_render_state.h"
64 #include "i915_gem_request.h"
66 #include "intel_gvt.h"
68 /* General customization:
71 #define DRIVER_NAME "i915"
72 #define DRIVER_DESC "Intel Graphics"
73 #define DRIVER_DATE "20160725"
76 /* Many gcc seem to no see through this and fall over :( */
78 #define WARN_ON(x) ({ \
79 bool __i915_warn_cond = (x); \
80 if (__builtin_constant_p(__i915_warn_cond)) \
81 BUILD_BUG_ON(__i915_warn_cond); \
82 WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
84 #define WARN_ON(x) WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
88 #define WARN_ON_ONCE(x) WARN_ONCE((x), "%s", "WARN_ON_ONCE(" __stringify(x) ")")
90 #define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
91 (long) (x), __func__);
93 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
94 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
95 * which may not necessarily be a user visible problem. This will either
96 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
97 * enable distros and users to tailor their preferred amount of i915 abrt
100 #define I915_STATE_WARN(condition, format...) ({ \
101 int __ret_warn_on = !!(condition); \
102 if (unlikely(__ret_warn_on)) \
103 if (!WARN(i915.verbose_state_checks, format)) \
105 unlikely(__ret_warn_on); \
108 #define I915_STATE_WARN_ON(x) \
109 I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
111 bool __i915_inject_load_failure(const char *func
, int line
);
112 #define i915_inject_load_failure() \
113 __i915_inject_load_failure(__func__, __LINE__)
115 static inline const char *yesno(bool v
)
117 return v
? "yes" : "no";
120 static inline const char *onoff(bool v
)
122 return v
? "on" : "off";
131 I915_MAX_PIPES
= _PIPE_EDP
133 #define pipe_name(p) ((p) + 'A')
145 static inline const char *transcoder_name(enum transcoder transcoder
)
147 switch (transcoder
) {
156 case TRANSCODER_DSI_A
:
158 case TRANSCODER_DSI_C
:
165 static inline bool transcoder_is_dsi(enum transcoder transcoder
)
167 return transcoder
== TRANSCODER_DSI_A
|| transcoder
== TRANSCODER_DSI_C
;
171 * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
172 * number of planes per CRTC. Not all platforms really have this many planes,
173 * which means some arrays of size I915_MAX_PLANES may have unused entries
174 * between the topmost sprite plane and the cursor plane.
183 #define plane_name(p) ((p) + 'A')
185 #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
195 #define port_name(p) ((p) + 'A')
197 #define I915_NUM_PHYS_VLV 2
209 enum intel_display_power_domain
{
213 POWER_DOMAIN_PIPE_A_PANEL_FITTER
,
214 POWER_DOMAIN_PIPE_B_PANEL_FITTER
,
215 POWER_DOMAIN_PIPE_C_PANEL_FITTER
,
216 POWER_DOMAIN_TRANSCODER_A
,
217 POWER_DOMAIN_TRANSCODER_B
,
218 POWER_DOMAIN_TRANSCODER_C
,
219 POWER_DOMAIN_TRANSCODER_EDP
,
220 POWER_DOMAIN_TRANSCODER_DSI_A
,
221 POWER_DOMAIN_TRANSCODER_DSI_C
,
222 POWER_DOMAIN_PORT_DDI_A_LANES
,
223 POWER_DOMAIN_PORT_DDI_B_LANES
,
224 POWER_DOMAIN_PORT_DDI_C_LANES
,
225 POWER_DOMAIN_PORT_DDI_D_LANES
,
226 POWER_DOMAIN_PORT_DDI_E_LANES
,
227 POWER_DOMAIN_PORT_DSI
,
228 POWER_DOMAIN_PORT_CRT
,
229 POWER_DOMAIN_PORT_OTHER
,
238 POWER_DOMAIN_MODESET
,
244 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
245 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
246 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
247 #define POWER_DOMAIN_TRANSCODER(tran) \
248 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
249 (tran) + POWER_DOMAIN_TRANSCODER_A)
253 HPD_TV
= HPD_NONE
, /* TV is known to be unreliable */
265 #define for_each_hpd_pin(__pin) \
266 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
268 struct i915_hotplug
{
269 struct work_struct hotplug_work
;
272 unsigned long last_jiffies
;
277 HPD_MARK_DISABLED
= 2
279 } stats
[HPD_NUM_PINS
];
281 struct delayed_work reenable_work
;
283 struct intel_digital_port
*irq_port
[I915_MAX_PORTS
];
286 struct work_struct dig_port_work
;
288 struct work_struct poll_init_work
;
292 * if we get a HPD irq from DP and a HPD irq from non-DP
293 * the non-DP HPD could block the workqueue on a mode config
294 * mutex getting, that userspace may have taken. However
295 * userspace is waiting on the DP workqueue to run which is
296 * blocked behind the non-DP one.
298 struct workqueue_struct
*dp_wq
;
301 #define I915_GEM_GPU_DOMAINS \
302 (I915_GEM_DOMAIN_RENDER | \
303 I915_GEM_DOMAIN_SAMPLER | \
304 I915_GEM_DOMAIN_COMMAND | \
305 I915_GEM_DOMAIN_INSTRUCTION | \
306 I915_GEM_DOMAIN_VERTEX)
308 #define for_each_pipe(__dev_priv, __p) \
309 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
310 #define for_each_pipe_masked(__dev_priv, __p, __mask) \
311 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \
312 for_each_if ((__mask) & (1 << (__p)))
313 #define for_each_plane(__dev_priv, __pipe, __p) \
315 (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
317 #define for_each_sprite(__dev_priv, __p, __s) \
319 (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \
322 #define for_each_port_masked(__port, __ports_mask) \
323 for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) \
324 for_each_if ((__ports_mask) & (1 << (__port)))
326 #define for_each_crtc(dev, crtc) \
327 list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head)
329 #define for_each_intel_plane(dev, intel_plane) \
330 list_for_each_entry(intel_plane, \
331 &(dev)->mode_config.plane_list, \
334 #define for_each_intel_plane_mask(dev, intel_plane, plane_mask) \
335 list_for_each_entry(intel_plane, \
336 &(dev)->mode_config.plane_list, \
338 for_each_if ((plane_mask) & \
339 (1 << drm_plane_index(&intel_plane->base)))
341 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
342 list_for_each_entry(intel_plane, \
343 &(dev)->mode_config.plane_list, \
345 for_each_if ((intel_plane)->pipe == (intel_crtc)->pipe)
347 #define for_each_intel_crtc(dev, intel_crtc) \
348 list_for_each_entry(intel_crtc, \
349 &(dev)->mode_config.crtc_list, \
352 #define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask) \
353 list_for_each_entry(intel_crtc, \
354 &(dev)->mode_config.crtc_list, \
356 for_each_if ((crtc_mask) & (1 << drm_crtc_index(&intel_crtc->base)))
358 #define for_each_intel_encoder(dev, intel_encoder) \
359 list_for_each_entry(intel_encoder, \
360 &(dev)->mode_config.encoder_list, \
363 #define for_each_intel_connector(dev, intel_connector) \
364 list_for_each_entry(intel_connector, \
365 &(dev)->mode_config.connector_list, \
368 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
369 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
370 for_each_if ((intel_encoder)->base.crtc == (__crtc))
372 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
373 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
374 for_each_if ((intel_connector)->base.encoder == (__encoder))
376 #define for_each_power_domain(domain, mask) \
377 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
378 for_each_if ((1 << (domain)) & (mask))
380 struct drm_i915_private
;
381 struct i915_mm_struct
;
382 struct i915_mmu_object
;
384 struct drm_i915_file_private
{
385 struct drm_i915_private
*dev_priv
;
386 struct drm_file
*file
;
390 struct list_head request_list
;
391 /* 20ms is a fairly arbitrary limit (greater than the average frame time)
392 * chosen to prevent the CPU getting more than a frame ahead of the GPU
393 * (when using lax throttling for the frontbuffer). We also use it to
394 * offer free GPU waitboosts for severely congested workloads.
396 #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
398 struct idr context_idr
;
400 struct intel_rps_client
{
401 struct list_head link
;
405 unsigned int bsd_engine
;
408 /* Used by dp and fdi links */
409 struct intel_link_m_n
{
417 void intel_link_compute_m_n(int bpp
, int nlanes
,
418 int pixel_clock
, int link_clock
,
419 struct intel_link_m_n
*m_n
);
421 /* Interface history:
424 * 1.2: Add Power Management
425 * 1.3: Add vblank support
426 * 1.4: Fix cmdbuffer path, add heap destroy
427 * 1.5: Add vblank pipe configuration
428 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
429 * - Support vertical blank on secondary display pipe
431 #define DRIVER_MAJOR 1
432 #define DRIVER_MINOR 6
433 #define DRIVER_PATCHLEVEL 0
435 struct opregion_header
;
436 struct opregion_acpi
;
437 struct opregion_swsci
;
438 struct opregion_asle
;
440 struct intel_opregion
{
441 struct opregion_header
*header
;
442 struct opregion_acpi
*acpi
;
443 struct opregion_swsci
*swsci
;
444 u32 swsci_gbda_sub_functions
;
445 u32 swsci_sbcb_sub_functions
;
446 struct opregion_asle
*asle
;
451 struct work_struct asle_work
;
453 #define OPREGION_SIZE (8*1024)
455 struct intel_overlay
;
456 struct intel_overlay_error_state
;
458 #define I915_FENCE_REG_NONE -1
459 #define I915_MAX_NUM_FENCES 32
460 /* 32 fences + sign bit for FENCE_REG_NONE */
461 #define I915_MAX_NUM_FENCE_BITS 6
463 struct drm_i915_fence_reg
{
464 struct list_head lru_list
;
465 struct drm_i915_gem_object
*obj
;
469 struct sdvo_device_mapping
{
478 struct intel_display_error_state
;
480 struct drm_i915_error_state
{
490 /* Generic register state */
498 u32 error
; /* gen6+ */
499 u32 err_int
; /* gen7 */
500 u32 fault_data0
; /* gen8, gen9 */
501 u32 fault_data1
; /* gen8, gen9 */
507 u32 extra_instdone
[I915_NUM_INSTDONE_REG
];
508 u64 fence
[I915_MAX_NUM_FENCES
];
509 struct intel_overlay_error_state
*overlay
;
510 struct intel_display_error_state
*display
;
511 struct drm_i915_error_object
*semaphore_obj
;
513 struct drm_i915_error_engine
{
515 /* Software tracked state */
519 enum intel_engine_hangcheck_action hangcheck_action
;
522 /* our own tracking of ring head and tail */
527 u32 semaphore_seqno
[I915_NUM_ENGINES
- 1];
546 u32 rc_psmi
; /* sleep state */
547 u32 semaphore_mboxes
[I915_NUM_ENGINES
- 1];
549 struct drm_i915_error_object
{
553 } *ringbuffer
, *batchbuffer
, *wa_batchbuffer
, *ctx
, *hws_page
;
555 struct drm_i915_error_object
*wa_ctx
;
557 struct drm_i915_error_request
{
563 struct drm_i915_error_waiter
{
564 char comm
[TASK_COMM_LEN
];
578 char comm
[TASK_COMM_LEN
];
579 } engine
[I915_NUM_ENGINES
];
581 struct drm_i915_error_buffer
{
584 u32 rseqno
[I915_NUM_ENGINES
], wseqno
;
588 s32 fence_reg
:I915_MAX_NUM_FENCE_BITS
;
596 } **active_bo
, **pinned_bo
;
598 u32
*active_bo_count
, *pinned_bo_count
;
602 struct intel_connector
;
603 struct intel_encoder
;
604 struct intel_crtc_state
;
605 struct intel_initial_plane_config
;
610 struct drm_i915_display_funcs
{
611 int (*get_display_clock_speed
)(struct drm_device
*dev
);
612 int (*get_fifo_size
)(struct drm_device
*dev
, int plane
);
613 int (*compute_pipe_wm
)(struct intel_crtc_state
*cstate
);
614 int (*compute_intermediate_wm
)(struct drm_device
*dev
,
615 struct intel_crtc
*intel_crtc
,
616 struct intel_crtc_state
*newstate
);
617 void (*initial_watermarks
)(struct intel_crtc_state
*cstate
);
618 void (*optimize_watermarks
)(struct intel_crtc_state
*cstate
);
619 int (*compute_global_watermarks
)(struct drm_atomic_state
*state
);
620 void (*update_wm
)(struct drm_crtc
*crtc
);
621 int (*modeset_calc_cdclk
)(struct drm_atomic_state
*state
);
622 void (*modeset_commit_cdclk
)(struct drm_atomic_state
*state
);
623 /* Returns the active state of the crtc, and if the crtc is active,
624 * fills out the pipe-config with the hw state. */
625 bool (*get_pipe_config
)(struct intel_crtc
*,
626 struct intel_crtc_state
*);
627 void (*get_initial_plane_config
)(struct intel_crtc
*,
628 struct intel_initial_plane_config
*);
629 int (*crtc_compute_clock
)(struct intel_crtc
*crtc
,
630 struct intel_crtc_state
*crtc_state
);
631 void (*crtc_enable
)(struct drm_crtc
*crtc
);
632 void (*crtc_disable
)(struct drm_crtc
*crtc
);
633 void (*audio_codec_enable
)(struct drm_connector
*connector
,
634 struct intel_encoder
*encoder
,
635 const struct drm_display_mode
*adjusted_mode
);
636 void (*audio_codec_disable
)(struct intel_encoder
*encoder
);
637 void (*fdi_link_train
)(struct drm_crtc
*crtc
);
638 void (*init_clock_gating
)(struct drm_device
*dev
);
639 int (*queue_flip
)(struct drm_device
*dev
, struct drm_crtc
*crtc
,
640 struct drm_framebuffer
*fb
,
641 struct drm_i915_gem_object
*obj
,
642 struct drm_i915_gem_request
*req
,
644 void (*hpd_irq_setup
)(struct drm_i915_private
*dev_priv
);
645 /* clock updates for mode set */
647 /* render clock increase/decrease */
648 /* display clock increase/decrease */
649 /* pll clock increase/decrease */
651 void (*load_csc_matrix
)(struct drm_crtc_state
*crtc_state
);
652 void (*load_luts
)(struct drm_crtc_state
*crtc_state
);
655 enum forcewake_domain_id
{
656 FW_DOMAIN_ID_RENDER
= 0,
657 FW_DOMAIN_ID_BLITTER
,
663 enum forcewake_domains
{
664 FORCEWAKE_RENDER
= (1 << FW_DOMAIN_ID_RENDER
),
665 FORCEWAKE_BLITTER
= (1 << FW_DOMAIN_ID_BLITTER
),
666 FORCEWAKE_MEDIA
= (1 << FW_DOMAIN_ID_MEDIA
),
667 FORCEWAKE_ALL
= (FORCEWAKE_RENDER
|
672 #define FW_REG_READ (1)
673 #define FW_REG_WRITE (2)
675 enum forcewake_domains
676 intel_uncore_forcewake_for_reg(struct drm_i915_private
*dev_priv
,
677 i915_reg_t reg
, unsigned int op
);
679 struct intel_uncore_funcs
{
680 void (*force_wake_get
)(struct drm_i915_private
*dev_priv
,
681 enum forcewake_domains domains
);
682 void (*force_wake_put
)(struct drm_i915_private
*dev_priv
,
683 enum forcewake_domains domains
);
685 uint8_t (*mmio_readb
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
, bool trace
);
686 uint16_t (*mmio_readw
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
, bool trace
);
687 uint32_t (*mmio_readl
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
, bool trace
);
688 uint64_t (*mmio_readq
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
, bool trace
);
690 void (*mmio_writeb
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
,
691 uint8_t val
, bool trace
);
692 void (*mmio_writew
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
,
693 uint16_t val
, bool trace
);
694 void (*mmio_writel
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
,
695 uint32_t val
, bool trace
);
696 void (*mmio_writeq
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
,
697 uint64_t val
, bool trace
);
700 struct intel_uncore
{
701 spinlock_t lock
; /** lock is also taken in irq contexts. */
703 struct intel_uncore_funcs funcs
;
706 enum forcewake_domains fw_domains
;
708 struct intel_uncore_forcewake_domain
{
709 struct drm_i915_private
*i915
;
710 enum forcewake_domain_id id
;
711 enum forcewake_domains mask
;
713 struct hrtimer timer
;
720 } fw_domain
[FW_DOMAIN_ID_COUNT
];
722 int unclaimed_mmio_check
;
725 /* Iterate over initialised fw domains */
726 #define for_each_fw_domain_masked(domain__, mask__, dev_priv__) \
727 for ((domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
728 (domain__) < &(dev_priv__)->uncore.fw_domain[FW_DOMAIN_ID_COUNT]; \
730 for_each_if ((mask__) & (domain__)->mask)
732 #define for_each_fw_domain(domain__, dev_priv__) \
733 for_each_fw_domain_masked(domain__, FORCEWAKE_ALL, dev_priv__)
735 #define CSR_VERSION(major, minor) ((major) << 16 | (minor))
736 #define CSR_VERSION_MAJOR(version) ((version) >> 16)
737 #define CSR_VERSION_MINOR(version) ((version) & 0xffff)
740 struct work_struct work
;
742 uint32_t *dmc_payload
;
743 uint32_t dmc_fw_size
;
746 i915_reg_t mmioaddr
[8];
747 uint32_t mmiodata
[8];
749 uint32_t allowed_dc_mask
;
752 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
753 func(is_mobile) sep \
756 func(is_i945gm) sep \
758 func(need_gfx_hws) sep \
760 func(is_pineview) sep \
761 func(is_broadwater) sep \
762 func(is_crestline) sep \
763 func(is_ivybridge) sep \
764 func(is_valleyview) sep \
765 func(is_cherryview) sep \
766 func(is_haswell) sep \
767 func(is_broadwell) sep \
768 func(is_skylake) sep \
769 func(is_broxton) sep \
770 func(is_kabylake) sep \
771 func(is_preliminary) sep \
773 func(has_pipe_cxsr) sep \
774 func(has_hotplug) sep \
775 func(cursor_needs_physical) sep \
776 func(has_overlay) sep \
777 func(overlay_needs_physical) sep \
778 func(supports_tv) sep \
780 func(has_snoop) sep \
782 func(has_fpga_dbg) sep \
785 #define DEFINE_FLAG(name) u8 name:1
786 #define SEP_SEMICOLON ;
788 struct intel_device_info
{
789 u32 display_mmio_offset
;
792 u8 num_sprites
[I915_MAX_PIPES
];
795 u8 ring_mask
; /* Rings supported by the HW */
796 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG
, SEP_SEMICOLON
);
797 /* Register offsets for the various display pipes and transcoders */
798 int pipe_offsets
[I915_MAX_TRANSCODERS
];
799 int trans_offsets
[I915_MAX_TRANSCODERS
];
800 int palette_offsets
[I915_MAX_PIPES
];
801 int cursor_offsets
[I915_MAX_PIPES
];
803 /* Slice/subslice/EU info */
806 u8 subslice_per_slice
;
810 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
813 u8 has_subslice_pg
:1;
817 u16 degamma_lut_size
;
825 enum i915_cache_level
{
827 I915_CACHE_LLC
, /* also used for snoopable memory on non-LLC */
828 I915_CACHE_L3_LLC
, /* gen7+, L3 sits between the domain specifc
829 caches, eg sampler/render caches, and the
830 large Last-Level-Cache. LLC is coherent with
831 the CPU, but L3 is only visible to the GPU. */
832 I915_CACHE_WT
, /* hsw:gt3e WriteThrough for scanouts */
835 struct i915_ctx_hang_stats
{
836 /* This context had batch pending when hang was declared */
837 unsigned batch_pending
;
839 /* This context had batch active when hang was declared */
840 unsigned batch_active
;
842 /* Time when this context was last blamed for a GPU reset */
843 unsigned long guilty_ts
;
845 /* If the contexts causes a second GPU hang within this time,
846 * it is permanently banned from submitting any more work.
848 unsigned long ban_period_seconds
;
850 /* This context is banned to submit more work */
854 /* This must match up with the value previously used for execbuf2.rsvd1. */
855 #define DEFAULT_CONTEXT_HANDLE 0
858 * struct i915_gem_context - as the name implies, represents a context.
859 * @ref: reference count.
860 * @user_handle: userspace tracking identity for this context.
861 * @remap_slice: l3 row remapping information.
862 * @flags: context specific flags:
863 * CONTEXT_NO_ZEROMAP: do not allow mapping things to page 0.
864 * @file_priv: filp associated with this context (NULL for global default
866 * @hang_stats: information about the role of this context in possible GPU
868 * @ppgtt: virtual memory space used by this context.
869 * @legacy_hw_ctx: render context backing object and whether it is correctly
870 * initialized (legacy ring submission mechanism only).
871 * @link: link in the global list of contexts.
873 * Contexts are memory images used by the hardware to store copies of their
876 struct i915_gem_context
{
878 struct drm_i915_private
*i915
;
879 struct drm_i915_file_private
*file_priv
;
880 struct i915_hw_ppgtt
*ppgtt
;
882 struct i915_ctx_hang_stats hang_stats
;
884 /* Unique identifier for this context, used by the hw for tracking */
886 #define CONTEXT_NO_ZEROMAP BIT(0)
887 #define CONTEXT_NO_ERROR_CAPTURE BIT(1)
893 struct intel_context
{
894 struct drm_i915_gem_object
*state
;
895 struct intel_ring
*ring
;
896 struct i915_vma
*lrc_vma
;
897 uint32_t *lrc_reg_state
;
901 } engine
[I915_NUM_ENGINES
];
904 struct atomic_notifier_head status_notifier
;
905 bool execlists_force_single_submission
;
907 struct list_head link
;
922 /* This is always the inner lock when overlapping with struct_mutex and
923 * it's the outer lock when overlapping with stolen_lock. */
926 unsigned int possible_framebuffer_bits
;
927 unsigned int busy_bits
;
928 unsigned int visible_pipes_mask
;
929 struct intel_crtc
*crtc
;
931 struct drm_mm_node compressed_fb
;
932 struct drm_mm_node
*compressed_llb
;
939 struct intel_fbc_state_cache
{
941 unsigned int mode_flags
;
942 uint32_t hsw_bdw_pixel_rate
;
946 unsigned int rotation
;
954 uint32_t pixel_format
;
957 unsigned int tiling_mode
;
961 struct intel_fbc_reg_params
{
965 unsigned int fence_y_offset
;
970 uint32_t pixel_format
;
978 struct intel_fbc_work
{
980 u32 scheduled_vblank
;
981 struct work_struct work
;
984 const char *no_fbc_reason
;
988 * HIGH_RR is the highest eDP panel refresh rate read from EDID
989 * LOW_RR is the lowest eDP panel refresh rate found from EDID
990 * parsing for same resolution.
992 enum drrs_refresh_rate_type
{
995 DRRS_MAX_RR
, /* RR count */
998 enum drrs_support_type
{
999 DRRS_NOT_SUPPORTED
= 0,
1000 STATIC_DRRS_SUPPORT
= 1,
1001 SEAMLESS_DRRS_SUPPORT
= 2
1007 struct delayed_work work
;
1008 struct intel_dp
*dp
;
1009 unsigned busy_frontbuffer_bits
;
1010 enum drrs_refresh_rate_type refresh_rate_type
;
1011 enum drrs_support_type type
;
1018 struct intel_dp
*enabled
;
1020 struct delayed_work work
;
1021 unsigned busy_frontbuffer_bits
;
1023 bool aux_frame_sync
;
1028 PCH_NONE
= 0, /* No PCH present */
1029 PCH_IBX
, /* Ibexpeak PCH */
1030 PCH_CPT
, /* Cougarpoint PCH */
1031 PCH_LPT
, /* Lynxpoint PCH */
1032 PCH_SPT
, /* Sunrisepoint PCH */
1033 PCH_KBP
, /* Kabypoint PCH */
1037 enum intel_sbi_destination
{
1042 #define QUIRK_PIPEA_FORCE (1<<0)
1043 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
1044 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
1045 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
1046 #define QUIRK_PIPEB_FORCE (1<<4)
1047 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
1050 struct intel_fbc_work
;
1052 struct intel_gmbus
{
1053 struct i2c_adapter adapter
;
1054 #define GMBUS_FORCE_BIT_RETRY (1U << 31)
1057 i915_reg_t gpio_reg
;
1058 struct i2c_algo_bit_data bit_algo
;
1059 struct drm_i915_private
*dev_priv
;
1062 struct i915_suspend_saved_registers
{
1065 u32 savePP_ON_DELAYS
;
1066 u32 savePP_OFF_DELAYS
;
1071 u32 saveFBC_CONTROL
;
1072 u32 saveCACHE_MODE_0
;
1073 u32 saveMI_ARB_STATE
;
1077 uint64_t saveFENCE
[I915_MAX_NUM_FENCES
];
1078 u32 savePCH_PORT_HOTPLUG
;
1082 struct vlv_s0ix_state
{
1089 u32 lra_limits
[GEN7_LRA_LIMITS_REG_NUM
];
1090 u32 media_max_req_count
;
1091 u32 gfx_max_req_count
;
1117 u32 rp_down_timeout
;
1123 /* Display 1 CZ domain */
1128 u32 gt_scratch
[GEN7_GT_SCRATCH_REG_NUM
];
1130 /* GT SA CZ domain */
1137 /* Display 2 CZ domain */
1141 u32 clock_gate_dis2
;
1144 struct intel_rps_ei
{
1150 struct intel_gen6_power_mgmt
{
1152 * work, interrupts_enabled and pm_iir are protected by
1153 * dev_priv->irq_lock
1155 struct work_struct work
;
1156 bool interrupts_enabled
;
1161 /* Frequencies are stored in potentially platform dependent multiples.
1162 * In other words, *_freq needs to be multiplied by X to be interesting.
1163 * Soft limits are those which are used for the dynamic reclocking done
1164 * by the driver (raise frequencies under heavy loads, and lower for
1165 * lighter loads). Hard limits are those imposed by the hardware.
1167 * A distinction is made for overclocking, which is never enabled by
1168 * default, and is considered to be above the hard limit if it's
1171 u8 cur_freq
; /* Current frequency (cached, may not == HW) */
1172 u8 min_freq_softlimit
; /* Minimum frequency permitted by the driver */
1173 u8 max_freq_softlimit
; /* Max frequency permitted by the driver */
1174 u8 max_freq
; /* Maximum frequency, RP0 if not overclocking */
1175 u8 min_freq
; /* AKA RPn. Minimum frequency */
1176 u8 boost_freq
; /* Frequency to request when wait boosting */
1177 u8 idle_freq
; /* Frequency to request when we are idle */
1178 u8 efficient_freq
; /* AKA RPe. Pre-determined balanced frequency */
1179 u8 rp1_freq
; /* "less than" RP0 power/freqency */
1180 u8 rp0_freq
; /* Non-overclocked max frequency. */
1181 u16 gpll_ref_freq
; /* vlv/chv GPLL reference frequency */
1183 u8 up_threshold
; /* Current %busy required to uplock */
1184 u8 down_threshold
; /* Current %busy required to downclock */
1187 enum { LOW_POWER
, BETWEEN
, HIGH_POWER
} power
;
1189 spinlock_t client_lock
;
1190 struct list_head clients
;
1194 struct delayed_work autoenable_work
;
1197 /* manual wa residency calculations */
1198 struct intel_rps_ei up_ei
, down_ei
;
1201 * Protects RPS/RC6 register access and PCU communication.
1202 * Must be taken after struct_mutex if nested. Note that
1203 * this lock may be held for long periods of time when
1204 * talking to hw - so only take it when talking to hw!
1206 struct mutex hw_lock
;
1209 /* defined intel_pm.c */
1210 extern spinlock_t mchdev_lock
;
1212 struct intel_ilk_power_mgmt
{
1220 unsigned long last_time1
;
1221 unsigned long chipset_power
;
1224 unsigned long gfx_power
;
1231 struct drm_i915_private
;
1232 struct i915_power_well
;
1234 struct i915_power_well_ops
{
1236 * Synchronize the well's hw state to match the current sw state, for
1237 * example enable/disable it based on the current refcount. Called
1238 * during driver init and resume time, possibly after first calling
1239 * the enable/disable handlers.
1241 void (*sync_hw
)(struct drm_i915_private
*dev_priv
,
1242 struct i915_power_well
*power_well
);
1244 * Enable the well and resources that depend on it (for example
1245 * interrupts located on the well). Called after the 0->1 refcount
1248 void (*enable
)(struct drm_i915_private
*dev_priv
,
1249 struct i915_power_well
*power_well
);
1251 * Disable the well and resources that depend on it. Called after
1252 * the 1->0 refcount transition.
1254 void (*disable
)(struct drm_i915_private
*dev_priv
,
1255 struct i915_power_well
*power_well
);
1256 /* Returns the hw enabled state. */
1257 bool (*is_enabled
)(struct drm_i915_private
*dev_priv
,
1258 struct i915_power_well
*power_well
);
1261 /* Power well structure for haswell */
1262 struct i915_power_well
{
1265 /* power well enable/disable usage count */
1267 /* cached hw enabled state */
1269 unsigned long domains
;
1271 const struct i915_power_well_ops
*ops
;
1274 struct i915_power_domains
{
1276 * Power wells needed for initialization at driver init and suspend
1277 * time are on. They are kept on until after the first modeset.
1281 int power_well_count
;
1284 int domain_use_count
[POWER_DOMAIN_NUM
];
1285 struct i915_power_well
*power_wells
;
1288 #define MAX_L3_SLICES 2
1289 struct intel_l3_parity
{
1290 u32
*remap_info
[MAX_L3_SLICES
];
1291 struct work_struct error_work
;
1295 struct i915_gem_mm
{
1296 /** Memory allocator for GTT stolen memory */
1297 struct drm_mm stolen
;
1298 /** Protects the usage of the GTT stolen memory allocator. This is
1299 * always the inner lock when overlapping with struct_mutex. */
1300 struct mutex stolen_lock
;
1302 /** List of all objects in gtt_space. Used to restore gtt
1303 * mappings on resume */
1304 struct list_head bound_list
;
1306 * List of objects which are not bound to the GTT (thus
1307 * are idle and not used by the GPU) but still have
1308 * (presumably uncached) pages still attached.
1310 struct list_head unbound_list
;
1312 /** Usable portion of the GTT for GEM */
1313 unsigned long stolen_base
; /* limited to low memory (32-bit) */
1315 /** PPGTT used for aliasing the PPGTT with the GTT */
1316 struct i915_hw_ppgtt
*aliasing_ppgtt
;
1318 struct notifier_block oom_notifier
;
1319 struct notifier_block vmap_notifier
;
1320 struct shrinker shrinker
;
1321 bool shrinker_no_lock_stealing
;
1323 /** LRU list of objects with fence regs on them. */
1324 struct list_head fence_list
;
1327 * Are we in a non-interruptible section of code like
1332 /* the indicator for dispatch video commands on two BSD rings */
1333 unsigned int bsd_engine_dispatch_index
;
1335 /** Bit 6 swizzling required for X tiling */
1336 uint32_t bit_6_swizzle_x
;
1337 /** Bit 6 swizzling required for Y tiling */
1338 uint32_t bit_6_swizzle_y
;
1340 /* accounting, useful for userland debugging */
1341 spinlock_t object_stat_lock
;
1342 size_t object_memory
;
1346 struct drm_i915_error_state_buf
{
1347 struct drm_i915_private
*i915
;
1356 struct i915_error_state_file_priv
{
1357 struct drm_device
*dev
;
1358 struct drm_i915_error_state
*error
;
1361 struct i915_gpu_error
{
1362 /* For hangcheck timer */
1363 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1364 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1365 /* Hang gpu twice in this window and your context gets banned */
1366 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1368 struct delayed_work hangcheck_work
;
1370 /* For reset and error_state handling. */
1372 /* Protected by the above dev->gpu_error.lock. */
1373 struct drm_i915_error_state
*first_error
;
1375 unsigned long missed_irq_rings
;
1378 * State variable controlling the reset flow and count
1380 * This is a counter which gets incremented when reset is triggered,
1381 * and again when reset has been handled. So odd values (lowest bit set)
1382 * means that reset is in progress and even values that
1383 * (reset_counter >> 1):th reset was successfully completed.
1385 * If reset is not completed succesfully, the I915_WEDGE bit is
1386 * set meaning that hardware is terminally sour and there is no
1387 * recovery. All waiters on the reset_queue will be woken when
1390 * This counter is used by the wait_seqno code to notice that reset
1391 * event happened and it needs to restart the entire ioctl (since most
1392 * likely the seqno it waited for won't ever signal anytime soon).
1394 * This is important for lock-free wait paths, where no contended lock
1395 * naturally enforces the correct ordering between the bail-out of the
1396 * waiter and the gpu reset work code.
1398 atomic_t reset_counter
;
1400 #define I915_RESET_IN_PROGRESS_FLAG 1
1401 #define I915_WEDGED (1 << 31)
1404 * Waitqueue to signal when a hang is detected. Used to for waiters
1405 * to release the struct_mutex for the reset to procede.
1407 wait_queue_head_t wait_queue
;
1410 * Waitqueue to signal when the reset has completed. Used by clients
1411 * that wait for dev_priv->mm.wedged to settle.
1413 wait_queue_head_t reset_queue
;
1415 /* For missed irq/seqno simulation. */
1416 unsigned long test_irq_rings
;
1419 enum modeset_restore
{
1420 MODESET_ON_LID_OPEN
,
1425 #define DP_AUX_A 0x40
1426 #define DP_AUX_B 0x10
1427 #define DP_AUX_C 0x20
1428 #define DP_AUX_D 0x30
1430 #define DDC_PIN_B 0x05
1431 #define DDC_PIN_C 0x04
1432 #define DDC_PIN_D 0x06
1434 struct ddi_vbt_port_info
{
1436 * This is an index in the HDMI/DVI DDI buffer translation table.
1437 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1438 * populate this field.
1440 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1441 uint8_t hdmi_level_shift
;
1443 uint8_t supports_dvi
:1;
1444 uint8_t supports_hdmi
:1;
1445 uint8_t supports_dp
:1;
1447 uint8_t alternate_aux_channel
;
1448 uint8_t alternate_ddc_pin
;
1450 uint8_t dp_boost_level
;
1451 uint8_t hdmi_boost_level
;
1454 enum psr_lines_to_wait
{
1455 PSR_0_LINES_TO_WAIT
= 0,
1457 PSR_4_LINES_TO_WAIT
,
1461 struct intel_vbt_data
{
1462 struct drm_display_mode
*lfp_lvds_vbt_mode
; /* if any */
1463 struct drm_display_mode
*sdvo_lvds_vbt_mode
; /* if any */
1466 unsigned int int_tv_support
:1;
1467 unsigned int lvds_dither
:1;
1468 unsigned int lvds_vbt
:1;
1469 unsigned int int_crt_support
:1;
1470 unsigned int lvds_use_ssc
:1;
1471 unsigned int display_clock_mode
:1;
1472 unsigned int fdi_rx_polarity_inverted
:1;
1473 unsigned int panel_type
:4;
1475 unsigned int bios_lvds_val
; /* initial [PCH_]LVDS reg val in VBIOS */
1477 enum drrs_support_type drrs_type
;
1488 struct edp_power_seq pps
;
1493 bool require_aux_wakeup
;
1495 enum psr_lines_to_wait lines_to_wait
;
1496 int tp1_wakeup_time
;
1497 int tp2_tp3_wakeup_time
;
1503 bool active_low_pwm
;
1504 u8 min_brightness
; /* min_brightness/255 of max */
1505 enum intel_backlight_type type
;
1511 struct mipi_config
*config
;
1512 struct mipi_pps_data
*pps
;
1516 const u8
*sequence
[MIPI_SEQ_MAX
];
1522 union child_device_config
*child_dev
;
1524 struct ddi_vbt_port_info ddi_port_info
[I915_MAX_PORTS
];
1525 struct sdvo_device_mapping sdvo_mappings
[2];
1528 enum intel_ddb_partitioning
{
1530 INTEL_DDB_PART_5_6
, /* IVB+ */
1533 struct intel_wm_level
{
1541 struct ilk_wm_values
{
1542 uint32_t wm_pipe
[3];
1544 uint32_t wm_lp_spr
[3];
1545 uint32_t wm_linetime
[3];
1547 enum intel_ddb_partitioning partitioning
;
1550 struct vlv_pipe_wm
{
1561 struct vlv_wm_values
{
1562 struct vlv_pipe_wm pipe
[3];
1563 struct vlv_sr_wm sr
;
1573 struct skl_ddb_entry
{
1574 uint16_t start
, end
; /* in number of blocks, 'end' is exclusive */
1577 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry
*entry
)
1579 return entry
->end
- entry
->start
;
1582 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry
*e1
,
1583 const struct skl_ddb_entry
*e2
)
1585 if (e1
->start
== e2
->start
&& e1
->end
== e2
->end
)
1591 struct skl_ddb_allocation
{
1592 struct skl_ddb_entry pipe
[I915_MAX_PIPES
];
1593 struct skl_ddb_entry plane
[I915_MAX_PIPES
][I915_MAX_PLANES
]; /* packed/uv */
1594 struct skl_ddb_entry y_plane
[I915_MAX_PIPES
][I915_MAX_PLANES
];
1597 struct skl_wm_values
{
1598 unsigned dirty_pipes
;
1599 struct skl_ddb_allocation ddb
;
1600 uint32_t wm_linetime
[I915_MAX_PIPES
];
1601 uint32_t plane
[I915_MAX_PIPES
][I915_MAX_PLANES
][8];
1602 uint32_t plane_trans
[I915_MAX_PIPES
][I915_MAX_PLANES
];
1605 struct skl_wm_level
{
1606 bool plane_en
[I915_MAX_PLANES
];
1607 uint16_t plane_res_b
[I915_MAX_PLANES
];
1608 uint8_t plane_res_l
[I915_MAX_PLANES
];
1612 * This struct helps tracking the state needed for runtime PM, which puts the
1613 * device in PCI D3 state. Notice that when this happens, nothing on the
1614 * graphics device works, even register access, so we don't get interrupts nor
1617 * Every piece of our code that needs to actually touch the hardware needs to
1618 * either call intel_runtime_pm_get or call intel_display_power_get with the
1619 * appropriate power domain.
1621 * Our driver uses the autosuspend delay feature, which means we'll only really
1622 * suspend if we stay with zero refcount for a certain amount of time. The
1623 * default value is currently very conservative (see intel_runtime_pm_enable), but
1624 * it can be changed with the standard runtime PM files from sysfs.
1626 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1627 * goes back to false exactly before we reenable the IRQs. We use this variable
1628 * to check if someone is trying to enable/disable IRQs while they're supposed
1629 * to be disabled. This shouldn't happen and we'll print some error messages in
1632 * For more, read the Documentation/power/runtime_pm.txt.
1634 struct i915_runtime_pm
{
1635 atomic_t wakeref_count
;
1636 atomic_t atomic_seq
;
1641 enum intel_pipe_crc_source
{
1642 INTEL_PIPE_CRC_SOURCE_NONE
,
1643 INTEL_PIPE_CRC_SOURCE_PLANE1
,
1644 INTEL_PIPE_CRC_SOURCE_PLANE2
,
1645 INTEL_PIPE_CRC_SOURCE_PF
,
1646 INTEL_PIPE_CRC_SOURCE_PIPE
,
1647 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1648 INTEL_PIPE_CRC_SOURCE_TV
,
1649 INTEL_PIPE_CRC_SOURCE_DP_B
,
1650 INTEL_PIPE_CRC_SOURCE_DP_C
,
1651 INTEL_PIPE_CRC_SOURCE_DP_D
,
1652 INTEL_PIPE_CRC_SOURCE_AUTO
,
1653 INTEL_PIPE_CRC_SOURCE_MAX
,
1656 struct intel_pipe_crc_entry
{
1661 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1662 struct intel_pipe_crc
{
1664 bool opened
; /* exclusive access to the result file */
1665 struct intel_pipe_crc_entry
*entries
;
1666 enum intel_pipe_crc_source source
;
1668 wait_queue_head_t wq
;
1671 struct i915_frontbuffer_tracking
{
1675 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1682 struct i915_wa_reg
{
1685 /* bitmask representing WA bits */
1690 * RING_MAX_NONPRIV_SLOTS is per-engine but at this point we are only
1691 * allowing it for RCS as we don't foresee any requirement of having
1692 * a whitelist for other engines. When it is really required for
1693 * other engines then the limit need to be increased.
1695 #define I915_MAX_WA_REGS (16 + RING_MAX_NONPRIV_SLOTS)
1697 struct i915_workarounds
{
1698 struct i915_wa_reg reg
[I915_MAX_WA_REGS
];
1700 u32 hw_whitelist_count
[I915_NUM_ENGINES
];
1703 struct i915_virtual_gpu
{
1707 /* used in computing the new watermarks state */
1708 struct intel_wm_config
{
1709 unsigned int num_pipes_active
;
1710 bool sprites_enabled
;
1711 bool sprites_scaled
;
1714 struct drm_i915_private
{
1715 struct drm_device drm
;
1717 struct kmem_cache
*objects
;
1718 struct kmem_cache
*vmas
;
1719 struct kmem_cache
*requests
;
1721 const struct intel_device_info info
;
1723 int relative_constants_mode
;
1727 struct intel_uncore uncore
;
1729 struct i915_virtual_gpu vgpu
;
1731 struct intel_gvt gvt
;
1733 struct intel_guc guc
;
1735 struct intel_csr csr
;
1737 struct intel_gmbus gmbus
[GMBUS_NUM_PINS
];
1739 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1740 * controller on different i2c buses. */
1741 struct mutex gmbus_mutex
;
1744 * Base address of the gmbus and gpio block.
1746 uint32_t gpio_mmio_base
;
1748 /* MMIO base address for MIPI regs */
1749 uint32_t mipi_mmio_base
;
1751 uint32_t psr_mmio_base
;
1753 wait_queue_head_t gmbus_wait_queue
;
1755 struct pci_dev
*bridge_dev
;
1756 struct i915_gem_context
*kernel_context
;
1757 struct intel_engine_cs engine
[I915_NUM_ENGINES
];
1758 struct drm_i915_gem_object
*semaphore_obj
;
1761 struct drm_dma_handle
*status_page_dmah
;
1762 struct resource mch_res
;
1764 /* protects the irq masks */
1765 spinlock_t irq_lock
;
1767 /* protects the mmio flip data */
1768 spinlock_t mmio_flip_lock
;
1770 bool display_irqs_enabled
;
1772 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1773 struct pm_qos_request pm_qos
;
1775 /* Sideband mailbox protection */
1776 struct mutex sb_lock
;
1778 /** Cached value of IMR to avoid reads in updating the bitfield */
1781 u32 de_irq_mask
[I915_MAX_PIPES
];
1786 u32 pipestat_irq_mask
[I915_MAX_PIPES
];
1788 struct i915_hotplug hotplug
;
1789 struct intel_fbc fbc
;
1790 struct i915_drrs drrs
;
1791 struct intel_opregion opregion
;
1792 struct intel_vbt_data vbt
;
1794 bool preserve_bios_swizzle
;
1797 struct intel_overlay
*overlay
;
1799 /* backlight registers and fields in struct intel_panel */
1800 struct mutex backlight_lock
;
1803 bool no_aux_handshake
;
1805 /* protects panel power sequencer state */
1806 struct mutex pps_mutex
;
1808 struct drm_i915_fence_reg fence_regs
[I915_MAX_NUM_FENCES
]; /* assume 965 */
1809 int num_fence_regs
; /* 8 on pre-965, 16 otherwise */
1811 unsigned int fsb_freq
, mem_freq
, is_ddr3
;
1812 unsigned int skl_preferred_vco_freq
;
1813 unsigned int cdclk_freq
, max_cdclk_freq
, atomic_cdclk_freq
;
1814 unsigned int max_dotclk_freq
;
1815 unsigned int rawclk_freq
;
1816 unsigned int hpll_freq
;
1817 unsigned int czclk_freq
;
1820 unsigned int vco
, ref
;
1824 * wq - Driver workqueue for GEM.
1826 * NOTE: Work items scheduled here are not allowed to grab any modeset
1827 * locks, for otherwise the flushing done in the pageflip code will
1828 * result in deadlocks.
1830 struct workqueue_struct
*wq
;
1832 /* Display functions */
1833 struct drm_i915_display_funcs display
;
1835 /* PCH chipset type */
1836 enum intel_pch pch_type
;
1837 unsigned short pch_id
;
1839 unsigned long quirks
;
1841 enum modeset_restore modeset_restore
;
1842 struct mutex modeset_restore_lock
;
1843 struct drm_atomic_state
*modeset_restore_state
;
1845 struct list_head vm_list
; /* Global list of all address spaces */
1846 struct i915_ggtt ggtt
; /* VM representing the global address space */
1848 struct i915_gem_mm mm
;
1849 DECLARE_HASHTABLE(mm_structs
, 7);
1850 struct mutex mm_lock
;
1852 /* The hw wants to have a stable context identifier for the lifetime
1853 * of the context (for OA, PASID, faults, etc). This is limited
1854 * in execlists to 21 bits.
1856 struct ida context_hw_ida
;
1857 #define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
1859 /* Kernel Modesetting */
1861 struct drm_crtc
*plane_to_crtc_mapping
[I915_MAX_PIPES
];
1862 struct drm_crtc
*pipe_to_crtc_mapping
[I915_MAX_PIPES
];
1863 wait_queue_head_t pending_flip_queue
;
1865 #ifdef CONFIG_DEBUG_FS
1866 struct intel_pipe_crc pipe_crc
[I915_MAX_PIPES
];
1869 /* dpll and cdclk state is protected by connection_mutex */
1870 int num_shared_dpll
;
1871 struct intel_shared_dpll shared_dplls
[I915_NUM_PLLS
];
1872 const struct intel_dpll_mgr
*dpll_mgr
;
1875 * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
1876 * Must be global rather than per dpll, because on some platforms
1877 * plls share registers.
1879 struct mutex dpll_lock
;
1881 unsigned int active_crtcs
;
1882 unsigned int min_pixclk
[I915_MAX_PIPES
];
1884 int dpio_phy_iosf_port
[I915_NUM_PHYS_VLV
];
1886 struct i915_workarounds workarounds
;
1888 struct i915_frontbuffer_tracking fb_tracking
;
1892 bool mchbar_need_disable
;
1894 struct intel_l3_parity l3_parity
;
1896 /* Cannot be determined by PCIID. You must always read a register. */
1899 /* gen6+ rps state */
1900 struct intel_gen6_power_mgmt rps
;
1902 /* ilk-only ips/rps state. Everything in here is protected by the global
1903 * mchdev_lock in intel_pm.c */
1904 struct intel_ilk_power_mgmt ips
;
1906 struct i915_power_domains power_domains
;
1908 struct i915_psr psr
;
1910 struct i915_gpu_error gpu_error
;
1912 struct drm_i915_gem_object
*vlv_pctx
;
1914 #ifdef CONFIG_DRM_FBDEV_EMULATION
1915 /* list of fbdev register on this device */
1916 struct intel_fbdev
*fbdev
;
1917 struct work_struct fbdev_suspend_work
;
1920 struct drm_property
*broadcast_rgb_property
;
1921 struct drm_property
*force_audio_property
;
1923 /* hda/i915 audio component */
1924 struct i915_audio_component
*audio_component
;
1925 bool audio_component_registered
;
1927 * av_mutex - mutex for audio/video sync
1930 struct mutex av_mutex
;
1932 uint32_t hw_context_size
;
1933 struct list_head context_list
;
1937 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
1938 u32 chv_phy_control
;
1940 * Shadows for CHV DPLL_MD regs to keep the state
1941 * checker somewhat working in the presence hardware
1942 * crappiness (can't read out DPLL_MD for pipes B & C).
1944 u32 chv_dpll_md
[I915_MAX_PIPES
];
1948 bool suspended_to_idle
;
1949 struct i915_suspend_saved_registers regfile
;
1950 struct vlv_s0ix_state vlv_s0ix_state
;
1954 * Raw watermark latency values:
1955 * in 0.1us units for WM0,
1956 * in 0.5us units for WM1+.
1959 uint16_t pri_latency
[5];
1961 uint16_t spr_latency
[5];
1963 uint16_t cur_latency
[5];
1965 * Raw watermark memory latency values
1966 * for SKL for all 8 levels
1969 uint16_t skl_latency
[8];
1972 * The skl_wm_values structure is a bit too big for stack
1973 * allocation, so we keep the staging struct where we store
1974 * intermediate results here instead.
1976 struct skl_wm_values skl_results
;
1978 /* current hardware state */
1980 struct ilk_wm_values hw
;
1981 struct skl_wm_values skl_hw
;
1982 struct vlv_wm_values vlv
;
1988 * Should be held around atomic WM register writing; also
1989 * protects * intel_crtc->wm.active and
1990 * cstate->wm.need_postvbl_update.
1992 struct mutex wm_mutex
;
1995 * Set during HW readout of watermarks/DDB. Some platforms
1996 * need to know when we're still using BIOS-provided values
1997 * (which we don't fully trust).
1999 bool distrust_bios_wm
;
2002 struct i915_runtime_pm pm
;
2004 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
2006 void (*cleanup_engine
)(struct intel_engine_cs
*engine
);
2007 void (*stop_engine
)(struct intel_engine_cs
*engine
);
2010 * Is the GPU currently considered idle, or busy executing
2011 * userspace requests? Whilst idle, we allow runtime power
2012 * management to power down the hardware and display clocks.
2013 * In order to reduce the effect on performance, there
2014 * is a slight delay before we do so.
2016 unsigned int active_engines
;
2020 * We leave the user IRQ off as much as possible,
2021 * but this means that requests will finish and never
2022 * be retired once the system goes idle. Set a timer to
2023 * fire periodically while the ring is running. When it
2024 * fires, go retire requests.
2026 struct delayed_work retire_work
;
2029 * When we detect an idle GPU, we want to turn on
2030 * powersaving features. So once we see that there
2031 * are no more requests outstanding and no more
2032 * arrive within a small period of time, we fire
2033 * off the idle_work.
2035 struct delayed_work idle_work
;
2038 /* perform PHY state sanity checks? */
2039 bool chv_phy_assert
[2];
2041 struct intel_encoder
*dig_port_map
[I915_MAX_PORTS
];
2044 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
2045 * will be rejected. Instead look for a better place.
2049 static inline struct drm_i915_private
*to_i915(const struct drm_device
*dev
)
2051 return container_of(dev
, struct drm_i915_private
, drm
);
2054 static inline struct drm_i915_private
*dev_to_i915(struct device
*dev
)
2056 return to_i915(dev_get_drvdata(dev
));
2059 static inline struct drm_i915_private
*guc_to_i915(struct intel_guc
*guc
)
2061 return container_of(guc
, struct drm_i915_private
, guc
);
2064 /* Simple iterator over all initialised engines */
2065 #define for_each_engine(engine__, dev_priv__) \
2066 for ((engine__) = &(dev_priv__)->engine[0]; \
2067 (engine__) < &(dev_priv__)->engine[I915_NUM_ENGINES]; \
2069 for_each_if (intel_engine_initialized(engine__))
2071 /* Iterator with engine_id */
2072 #define for_each_engine_id(engine__, dev_priv__, id__) \
2073 for ((engine__) = &(dev_priv__)->engine[0], (id__) = 0; \
2074 (engine__) < &(dev_priv__)->engine[I915_NUM_ENGINES]; \
2076 for_each_if (((id__) = (engine__)->id, \
2077 intel_engine_initialized(engine__)))
2079 /* Iterator over subset of engines selected by mask */
2080 #define for_each_engine_masked(engine__, dev_priv__, mask__) \
2081 for ((engine__) = &(dev_priv__)->engine[0]; \
2082 (engine__) < &(dev_priv__)->engine[I915_NUM_ENGINES]; \
2084 for_each_if (((mask__) & intel_engine_flag(engine__)) && \
2085 intel_engine_initialized(engine__))
2087 enum hdmi_force_audio
{
2088 HDMI_AUDIO_OFF_DVI
= -2, /* no aux data for HDMI-DVI converter */
2089 HDMI_AUDIO_OFF
, /* force turn off HDMI audio */
2090 HDMI_AUDIO_AUTO
, /* trust EDID */
2091 HDMI_AUDIO_ON
, /* force turn on HDMI audio */
2094 #define I915_GTT_OFFSET_NONE ((u32)-1)
2096 struct drm_i915_gem_object_ops
{
2098 #define I915_GEM_OBJECT_HAS_STRUCT_PAGE 0x1
2100 /* Interface between the GEM object and its backing storage.
2101 * get_pages() is called once prior to the use of the associated set
2102 * of pages before to binding them into the GTT, and put_pages() is
2103 * called after we no longer need them. As we expect there to be
2104 * associated cost with migrating pages between the backing storage
2105 * and making them available for the GPU (e.g. clflush), we may hold
2106 * onto the pages after they are no longer referenced by the GPU
2107 * in case they may be used again shortly (for example migrating the
2108 * pages to a different memory domain within the GTT). put_pages()
2109 * will therefore most likely be called when the object itself is
2110 * being released or under memory pressure (where we attempt to
2111 * reap pages for the shrinker).
2113 int (*get_pages
)(struct drm_i915_gem_object
*);
2114 void (*put_pages
)(struct drm_i915_gem_object
*);
2116 int (*dmabuf_export
)(struct drm_i915_gem_object
*);
2117 void (*release
)(struct drm_i915_gem_object
*);
2121 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2122 * considered to be the frontbuffer for the given plane interface-wise. This
2123 * doesn't mean that the hw necessarily already scans it out, but that any
2124 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
2126 * We have one bit per pipe and per scanout plane type.
2128 #define INTEL_MAX_SPRITE_BITS_PER_PIPE 5
2129 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2130 #define INTEL_FRONTBUFFER_BITS \
2131 (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES)
2132 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
2133 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2134 #define INTEL_FRONTBUFFER_CURSOR(pipe) \
2135 (1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2136 #define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \
2137 (1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2138 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2139 (1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2140 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2141 (0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2143 struct drm_i915_gem_object
{
2144 struct drm_gem_object base
;
2146 const struct drm_i915_gem_object_ops
*ops
;
2148 /** List of VMAs backed by this object */
2149 struct list_head vma_list
;
2151 /** Stolen memory for this object, instead of being backed by shmem. */
2152 struct drm_mm_node
*stolen
;
2153 struct list_head global_list
;
2155 /** Used in execbuf to temporarily hold a ref */
2156 struct list_head obj_exec_link
;
2158 struct list_head batch_pool_link
;
2161 * This is set if the object is on the active lists (has pending
2162 * rendering and so a non-zero seqno), and is not set if it i s on
2163 * inactive (ready to be unbound) list.
2165 unsigned int active
:I915_NUM_ENGINES
;
2168 * This is set if the object has been written to since last bound
2171 unsigned int dirty
:1;
2174 * Fence register bits (if any) for this object. Will be set
2175 * as needed when mapped into the GTT.
2176 * Protected by dev->struct_mutex.
2178 signed int fence_reg
:I915_MAX_NUM_FENCE_BITS
;
2181 * Advice: are the backing pages purgeable?
2183 unsigned int madv
:2;
2186 * Current tiling mode for the object.
2188 unsigned int tiling_mode
:2;
2190 * Whether the tiling parameters for the currently associated fence
2191 * register have changed. Note that for the purposes of tracking
2192 * tiling changes we also treat the unfenced register, the register
2193 * slot that the object occupies whilst it executes a fenced
2194 * command (such as BLT on gen2/3), as a "fence".
2196 unsigned int fence_dirty
:1;
2199 * Is the object at the current location in the gtt mappable and
2200 * fenceable? Used to avoid costly recalculations.
2202 unsigned int map_and_fenceable
:1;
2205 * Whether the current gtt mapping needs to be mappable (and isn't just
2206 * mappable by accident). Track pin and fault separate for a more
2207 * accurate mappable working set.
2209 unsigned int fault_mappable
:1;
2212 * Is the object to be mapped as read-only to the GPU
2213 * Only honoured if hardware has relevant pte bit
2215 unsigned long gt_ro
:1;
2216 unsigned int cache_level
:3;
2217 unsigned int cache_dirty
:1;
2219 unsigned int frontbuffer_bits
:INTEL_FRONTBUFFER_BITS
;
2221 unsigned int has_wc_mmap
;
2222 /** Count of VMA actually bound by this object */
2223 unsigned int bind_count
;
2224 unsigned int pin_display
;
2226 struct sg_table
*pages
;
2227 int pages_pin_count
;
2229 struct scatterlist
*sg
;
2234 /** Breadcrumb of last rendering to the buffer.
2235 * There can only be one writer, but we allow for multiple readers.
2236 * If there is a writer that necessarily implies that all other
2237 * read requests are complete - but we may only be lazily clearing
2238 * the read requests. A read request is naturally the most recent
2239 * request on a ring, so we may have two different write and read
2240 * requests on one ring where the write request is older than the
2241 * read request. This allows for the CPU to read from an active
2242 * buffer by only waiting for the write to complete.
2244 struct i915_gem_active last_read
[I915_NUM_ENGINES
];
2245 struct i915_gem_active last_write
;
2246 struct i915_gem_active last_fence
;
2248 /** Current tiling stride for the object, if it's tiled. */
2251 /** References from framebuffers, locks out tiling changes. */
2252 unsigned long framebuffer_references
;
2254 /** Record of address bit 17 of each page at last unbind. */
2255 unsigned long *bit_17
;
2258 /** for phy allocated objects */
2259 struct drm_dma_handle
*phys_handle
;
2261 struct i915_gem_userptr
{
2263 unsigned read_only
:1;
2264 unsigned workers
:4;
2265 #define I915_GEM_USERPTR_MAX_WORKERS 15
2267 struct i915_mm_struct
*mm
;
2268 struct i915_mmu_object
*mmu_object
;
2269 struct work_struct
*work
;
2274 static inline struct drm_i915_gem_object
*
2275 to_intel_bo(struct drm_gem_object
*gem
)
2277 /* Assert that to_intel_bo(NULL) == NULL */
2278 BUILD_BUG_ON(offsetof(struct drm_i915_gem_object
, base
));
2280 return container_of(gem
, struct drm_i915_gem_object
, base
);
2283 static inline struct drm_i915_gem_object
*
2284 i915_gem_object_lookup(struct drm_file
*file
, u32 handle
)
2286 return to_intel_bo(drm_gem_object_lookup(file
, handle
));
2290 extern struct drm_gem_object
*
2291 drm_gem_object_lookup(struct drm_file
*file
, u32 handle
);
2293 __attribute__((nonnull
))
2294 static inline struct drm_i915_gem_object
*
2295 i915_gem_object_get(struct drm_i915_gem_object
*obj
)
2297 drm_gem_object_reference(&obj
->base
);
2302 extern void drm_gem_object_reference(struct drm_gem_object
*);
2304 __attribute__((nonnull
))
2306 i915_gem_object_put(struct drm_i915_gem_object
*obj
)
2308 drm_gem_object_unreference(&obj
->base
);
2312 extern void drm_gem_object_unreference(struct drm_gem_object
*);
2314 __attribute__((nonnull
))
2316 i915_gem_object_put_unlocked(struct drm_i915_gem_object
*obj
)
2318 drm_gem_object_unreference_unlocked(&obj
->base
);
2322 extern void drm_gem_object_unreference_unlocked(struct drm_gem_object
*);
2325 i915_gem_object_has_struct_page(const struct drm_i915_gem_object
*obj
)
2327 return obj
->ops
->flags
& I915_GEM_OBJECT_HAS_STRUCT_PAGE
;
2331 * Optimised SGL iterator for GEM objects
2333 static __always_inline
struct sgt_iter
{
2334 struct scatterlist
*sgp
;
2341 } __sgt_iter(struct scatterlist
*sgl
, bool dma
) {
2342 struct sgt_iter s
= { .sgp
= sgl
};
2345 s
.max
= s
.curr
= s
.sgp
->offset
;
2346 s
.max
+= s
.sgp
->length
;
2348 s
.dma
= sg_dma_address(s
.sgp
);
2350 s
.pfn
= page_to_pfn(sg_page(s
.sgp
));
2357 * __sg_next - return the next scatterlist entry in a list
2358 * @sg: The current sg entry
2361 * If the entry is the last, return NULL; otherwise, step to the next
2362 * element in the array (@sg@+1). If that's a chain pointer, follow it;
2363 * otherwise just return the pointer to the current element.
2365 static inline struct scatterlist
*__sg_next(struct scatterlist
*sg
)
2367 #ifdef CONFIG_DEBUG_SG
2368 BUG_ON(sg
->sg_magic
!= SG_MAGIC
);
2370 return sg_is_last(sg
) ? NULL
:
2371 likely(!sg_is_chain(++sg
)) ? sg
:
2376 * for_each_sgt_dma - iterate over the DMA addresses of the given sg_table
2377 * @__dmap: DMA address (output)
2378 * @__iter: 'struct sgt_iter' (iterator state, internal)
2379 * @__sgt: sg_table to iterate over (input)
2381 #define for_each_sgt_dma(__dmap, __iter, __sgt) \
2382 for ((__iter) = __sgt_iter((__sgt)->sgl, true); \
2383 ((__dmap) = (__iter).dma + (__iter).curr); \
2384 (((__iter).curr += PAGE_SIZE) < (__iter).max) || \
2385 ((__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0))
2388 * for_each_sgt_page - iterate over the pages of the given sg_table
2389 * @__pp: page pointer (output)
2390 * @__iter: 'struct sgt_iter' (iterator state, internal)
2391 * @__sgt: sg_table to iterate over (input)
2393 #define for_each_sgt_page(__pp, __iter, __sgt) \
2394 for ((__iter) = __sgt_iter((__sgt)->sgl, false); \
2395 ((__pp) = (__iter).pfn == 0 ? NULL : \
2396 pfn_to_page((__iter).pfn + ((__iter).curr >> PAGE_SHIFT))); \
2397 (((__iter).curr += PAGE_SIZE) < (__iter).max) || \
2398 ((__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0))
2401 * A command that requires special handling by the command parser.
2403 struct drm_i915_cmd_descriptor
{
2405 * Flags describing how the command parser processes the command.
2407 * CMD_DESC_FIXED: The command has a fixed length if this is set,
2408 * a length mask if not set
2409 * CMD_DESC_SKIP: The command is allowed but does not follow the
2410 * standard length encoding for the opcode range in
2412 * CMD_DESC_REJECT: The command is never allowed
2413 * CMD_DESC_REGISTER: The command should be checked against the
2414 * register whitelist for the appropriate ring
2415 * CMD_DESC_MASTER: The command is allowed if the submitting process
2419 #define CMD_DESC_FIXED (1<<0)
2420 #define CMD_DESC_SKIP (1<<1)
2421 #define CMD_DESC_REJECT (1<<2)
2422 #define CMD_DESC_REGISTER (1<<3)
2423 #define CMD_DESC_BITMASK (1<<4)
2424 #define CMD_DESC_MASTER (1<<5)
2427 * The command's unique identification bits and the bitmask to get them.
2428 * This isn't strictly the opcode field as defined in the spec and may
2429 * also include type, subtype, and/or subop fields.
2437 * The command's length. The command is either fixed length (i.e. does
2438 * not include a length field) or has a length field mask. The flag
2439 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
2440 * a length mask. All command entries in a command table must include
2441 * length information.
2449 * Describes where to find a register address in the command to check
2450 * against the ring's register whitelist. Only valid if flags has the
2451 * CMD_DESC_REGISTER bit set.
2453 * A non-zero step value implies that the command may access multiple
2454 * registers in sequence (e.g. LRI), in that case step gives the
2455 * distance in dwords between individual offset fields.
2463 #define MAX_CMD_DESC_BITMASKS 3
2465 * Describes command checks where a particular dword is masked and
2466 * compared against an expected value. If the command does not match
2467 * the expected value, the parser rejects it. Only valid if flags has
2468 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
2471 * If the check specifies a non-zero condition_mask then the parser
2472 * only performs the check when the bits specified by condition_mask
2479 u32 condition_offset
;
2481 } bits
[MAX_CMD_DESC_BITMASKS
];
2485 * A table of commands requiring special handling by the command parser.
2487 * Each engine has an array of tables. Each table consists of an array of
2488 * command descriptors, which must be sorted with command opcodes in
2491 struct drm_i915_cmd_table
{
2492 const struct drm_i915_cmd_descriptor
*table
;
2496 /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
2497 #define __I915__(p) ({ \
2498 struct drm_i915_private *__p; \
2499 if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
2500 __p = (struct drm_i915_private *)p; \
2501 else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
2502 __p = to_i915((struct drm_device *)p); \
2507 #define INTEL_INFO(p) (&__I915__(p)->info)
2508 #define INTEL_GEN(p) (INTEL_INFO(p)->gen)
2509 #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id)
2511 #define REVID_FOREVER 0xff
2512 #define INTEL_REVID(p) (__I915__(p)->drm.pdev->revision)
2514 #define GEN_FOREVER (0)
2516 * Returns true if Gen is in inclusive range [Start, End].
2518 * Use GEN_FOREVER for unbound start and or end.
2520 #define IS_GEN(p, s, e) ({ \
2521 unsigned int __s = (s), __e = (e); \
2522 BUILD_BUG_ON(!__builtin_constant_p(s)); \
2523 BUILD_BUG_ON(!__builtin_constant_p(e)); \
2524 if ((__s) != GEN_FOREVER) \
2526 if ((__e) == GEN_FOREVER) \
2527 __e = BITS_PER_LONG - 1; \
2530 !!(INTEL_INFO(p)->gen_mask & GENMASK((__e), (__s))); \
2534 * Return true if revision is in range [since,until] inclusive.
2536 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
2538 #define IS_REVID(p, since, until) \
2539 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
2541 #define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577)
2542 #define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562)
2543 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
2544 #define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572)
2545 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
2546 #define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592)
2547 #define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772)
2548 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
2549 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
2550 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
2551 #define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42)
2552 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
2553 #define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001)
2554 #define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011)
2555 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
2556 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
2557 #define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046)
2558 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
2559 #define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \
2560 INTEL_DEVID(dev) == 0x0152 || \
2561 INTEL_DEVID(dev) == 0x015a)
2562 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
2563 #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_cherryview)
2564 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
2565 #define IS_BROADWELL(dev) (INTEL_INFO(dev)->is_broadwell)
2566 #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake)
2567 #define IS_BROXTON(dev) (INTEL_INFO(dev)->is_broxton)
2568 #define IS_KABYLAKE(dev) (INTEL_INFO(dev)->is_kabylake)
2569 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
2570 #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
2571 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
2572 #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
2573 ((INTEL_DEVID(dev) & 0xf) == 0x6 || \
2574 (INTEL_DEVID(dev) & 0xf) == 0xb || \
2575 (INTEL_DEVID(dev) & 0xf) == 0xe))
2576 /* ULX machines are also considered ULT. */
2577 #define IS_BDW_ULX(dev) (IS_BROADWELL(dev) && \
2578 (INTEL_DEVID(dev) & 0xf) == 0xe)
2579 #define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \
2580 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2581 #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
2582 (INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
2583 #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
2584 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2585 /* ULX machines are also considered ULT. */
2586 #define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \
2587 INTEL_DEVID(dev) == 0x0A1E)
2588 #define IS_SKL_ULT(dev) (INTEL_DEVID(dev) == 0x1906 || \
2589 INTEL_DEVID(dev) == 0x1913 || \
2590 INTEL_DEVID(dev) == 0x1916 || \
2591 INTEL_DEVID(dev) == 0x1921 || \
2592 INTEL_DEVID(dev) == 0x1926)
2593 #define IS_SKL_ULX(dev) (INTEL_DEVID(dev) == 0x190E || \
2594 INTEL_DEVID(dev) == 0x1915 || \
2595 INTEL_DEVID(dev) == 0x191E)
2596 #define IS_KBL_ULT(dev) (INTEL_DEVID(dev) == 0x5906 || \
2597 INTEL_DEVID(dev) == 0x5913 || \
2598 INTEL_DEVID(dev) == 0x5916 || \
2599 INTEL_DEVID(dev) == 0x5921 || \
2600 INTEL_DEVID(dev) == 0x5926)
2601 #define IS_KBL_ULX(dev) (INTEL_DEVID(dev) == 0x590E || \
2602 INTEL_DEVID(dev) == 0x5915 || \
2603 INTEL_DEVID(dev) == 0x591E)
2604 #define IS_SKL_GT3(dev) (IS_SKYLAKE(dev) && \
2605 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2606 #define IS_SKL_GT4(dev) (IS_SKYLAKE(dev) && \
2607 (INTEL_DEVID(dev) & 0x00F0) == 0x0030)
2609 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
2611 #define SKL_REVID_A0 0x0
2612 #define SKL_REVID_B0 0x1
2613 #define SKL_REVID_C0 0x2
2614 #define SKL_REVID_D0 0x3
2615 #define SKL_REVID_E0 0x4
2616 #define SKL_REVID_F0 0x5
2617 #define SKL_REVID_G0 0x6
2618 #define SKL_REVID_H0 0x7
2620 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
2622 #define BXT_REVID_A0 0x0
2623 #define BXT_REVID_A1 0x1
2624 #define BXT_REVID_B0 0x3
2625 #define BXT_REVID_C0 0x9
2627 #define IS_BXT_REVID(p, since, until) (IS_BROXTON(p) && IS_REVID(p, since, until))
2629 #define KBL_REVID_A0 0x0
2630 #define KBL_REVID_B0 0x1
2631 #define KBL_REVID_C0 0x2
2632 #define KBL_REVID_D0 0x3
2633 #define KBL_REVID_E0 0x4
2635 #define IS_KBL_REVID(p, since, until) \
2636 (IS_KABYLAKE(p) && IS_REVID(p, since, until))
2639 * The genX designation typically refers to the render engine, so render
2640 * capability related checks should use IS_GEN, while display and other checks
2641 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2644 #define IS_GEN2(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(1)))
2645 #define IS_GEN3(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(2)))
2646 #define IS_GEN4(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(3)))
2647 #define IS_GEN5(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(4)))
2648 #define IS_GEN6(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(5)))
2649 #define IS_GEN7(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(6)))
2650 #define IS_GEN8(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(7)))
2651 #define IS_GEN9(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(8)))
2653 #define ENGINE_MASK(id) BIT(id)
2654 #define RENDER_RING ENGINE_MASK(RCS)
2655 #define BSD_RING ENGINE_MASK(VCS)
2656 #define BLT_RING ENGINE_MASK(BCS)
2657 #define VEBOX_RING ENGINE_MASK(VECS)
2658 #define BSD2_RING ENGINE_MASK(VCS2)
2659 #define ALL_ENGINES (~0)
2661 #define HAS_ENGINE(dev_priv, id) \
2662 (!!(INTEL_INFO(dev_priv)->ring_mask & ENGINE_MASK(id)))
2664 #define HAS_BSD(dev_priv) HAS_ENGINE(dev_priv, VCS)
2665 #define HAS_BSD2(dev_priv) HAS_ENGINE(dev_priv, VCS2)
2666 #define HAS_BLT(dev_priv) HAS_ENGINE(dev_priv, BCS)
2667 #define HAS_VEBOX(dev_priv) HAS_ENGINE(dev_priv, VECS)
2669 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
2670 #define HAS_SNOOP(dev) (INTEL_INFO(dev)->has_snoop)
2671 #define HAS_EDRAM(dev) (!!(__I915__(dev)->edram_cap & EDRAM_ENABLED))
2672 #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
2674 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
2676 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
2677 #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8)
2678 #define USES_PPGTT(dev) (i915.enable_ppgtt)
2679 #define USES_FULL_PPGTT(dev) (i915.enable_ppgtt >= 2)
2680 #define USES_FULL_48BIT_PPGTT(dev) (i915.enable_ppgtt == 3)
2682 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
2683 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
2685 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2686 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
2688 /* WaRsDisableCoarsePowerGating:skl,bxt */
2689 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
2690 (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1) || \
2691 IS_SKL_GT3(dev_priv) || \
2692 IS_SKL_GT4(dev_priv))
2695 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2696 * even when in MSI mode. This results in spurious interrupt warnings if the
2697 * legacy irq no. is shared with another device. The kernel then disables that
2698 * interrupt source and so prevents the other device from working properly.
2700 #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2701 #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2703 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2704 * rows, which changed the alignment requirements and fence programming.
2706 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
2708 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
2709 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
2711 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
2712 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
2713 #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
2715 #define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev))
2717 #define HAS_DP_MST(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2718 INTEL_INFO(dev)->gen >= 9)
2720 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
2721 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
2722 #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2723 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \
2724 IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
2725 #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \
2726 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \
2727 IS_CHERRYVIEW(dev) || IS_SKYLAKE(dev) || \
2728 IS_KABYLAKE(dev) || IS_BROXTON(dev))
2729 #define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6)
2730 #define HAS_RC6p(dev) (IS_GEN6(dev) || IS_IVYBRIDGE(dev))
2732 #define HAS_CSR(dev) (IS_GEN9(dev))
2735 * For now, anything with a GuC requires uCode loading, and then supports
2736 * command submission once loaded. But these are logically independent
2737 * properties, so we have separate macros to test them.
2739 #define HAS_GUC(dev) (IS_GEN9(dev))
2740 #define HAS_GUC_UCODE(dev) (HAS_GUC(dev))
2741 #define HAS_GUC_SCHED(dev) (HAS_GUC(dev))
2743 #define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \
2744 INTEL_INFO(dev)->gen >= 8)
2746 #define HAS_CORE_RING_FREQ(dev) (INTEL_INFO(dev)->gen >= 6 && \
2747 !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && \
2750 #define HAS_POOLED_EU(dev) (INTEL_INFO(dev)->has_pooled_eu)
2752 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
2753 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2754 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2755 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2756 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2757 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2758 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2759 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2760 #define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA200
2761 #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
2762 #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
2763 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
2765 #define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
2766 #define HAS_PCH_KBP(dev) (INTEL_PCH_TYPE(dev) == PCH_KBP)
2767 #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
2768 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
2769 #define HAS_PCH_LPT_LP(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
2770 #define HAS_PCH_LPT_H(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
2771 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
2772 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
2773 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
2774 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
2776 #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || \
2777 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
2779 /* DPF == dynamic parity feature */
2780 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
2781 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
2783 #define GT_FREQUENCY_MULTIPLIER 50
2784 #define GEN9_FREQ_SCALER 3
2786 #include "i915_trace.h"
2788 static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private
*dev_priv
)
2790 #ifdef CONFIG_INTEL_IOMMU
2791 if (INTEL_GEN(dev_priv
) >= 6 && intel_iommu_gfx_mapped
)
2797 extern int i915_suspend_switcheroo(struct drm_device
*dev
, pm_message_t state
);
2798 extern int i915_resume_switcheroo(struct drm_device
*dev
);
2800 int intel_sanitize_enable_ppgtt(struct drm_i915_private
*dev_priv
,
2803 bool intel_sanitize_semaphores(struct drm_i915_private
*dev_priv
, int value
);
2807 __i915_printk(struct drm_i915_private
*dev_priv
, const char *level
,
2808 const char *fmt
, ...);
2810 #define i915_report_error(dev_priv, fmt, ...) \
2811 __i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__)
2813 #ifdef CONFIG_COMPAT
2814 extern long i915_compat_ioctl(struct file
*filp
, unsigned int cmd
,
2817 extern int intel_gpu_reset(struct drm_i915_private
*dev_priv
, u32 engine_mask
);
2818 extern bool intel_has_gpu_reset(struct drm_i915_private
*dev_priv
);
2819 extern int i915_reset(struct drm_i915_private
*dev_priv
);
2820 extern int intel_guc_reset(struct drm_i915_private
*dev_priv
);
2821 extern void intel_engine_init_hangcheck(struct intel_engine_cs
*engine
);
2822 extern unsigned long i915_chipset_val(struct drm_i915_private
*dev_priv
);
2823 extern unsigned long i915_mch_val(struct drm_i915_private
*dev_priv
);
2824 extern unsigned long i915_gfx_val(struct drm_i915_private
*dev_priv
);
2825 extern void i915_update_gfx_val(struct drm_i915_private
*dev_priv
);
2826 int vlv_force_gfx_clock(struct drm_i915_private
*dev_priv
, bool on
);
2828 /* intel_hotplug.c */
2829 void intel_hpd_irq_handler(struct drm_i915_private
*dev_priv
,
2830 u32 pin_mask
, u32 long_mask
);
2831 void intel_hpd_init(struct drm_i915_private
*dev_priv
);
2832 void intel_hpd_init_work(struct drm_i915_private
*dev_priv
);
2833 void intel_hpd_cancel_work(struct drm_i915_private
*dev_priv
);
2834 bool intel_hpd_pin_to_port(enum hpd_pin pin
, enum port
*port
);
2835 bool intel_hpd_disable(struct drm_i915_private
*dev_priv
, enum hpd_pin pin
);
2836 void intel_hpd_enable(struct drm_i915_private
*dev_priv
, enum hpd_pin pin
);
2839 static inline void i915_queue_hangcheck(struct drm_i915_private
*dev_priv
)
2841 unsigned long delay
;
2843 if (unlikely(!i915
.enable_hangcheck
))
2846 /* Don't continually defer the hangcheck so that it is always run at
2847 * least once after work has been scheduled on any ring. Otherwise,
2848 * we will ignore a hung ring if a second ring is kept busy.
2851 delay
= round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES
);
2852 queue_delayed_work(system_long_wq
,
2853 &dev_priv
->gpu_error
.hangcheck_work
, delay
);
2857 void i915_handle_error(struct drm_i915_private
*dev_priv
,
2859 const char *fmt
, ...);
2861 extern void intel_irq_init(struct drm_i915_private
*dev_priv
);
2862 int intel_irq_install(struct drm_i915_private
*dev_priv
);
2863 void intel_irq_uninstall(struct drm_i915_private
*dev_priv
);
2865 extern void intel_uncore_sanitize(struct drm_i915_private
*dev_priv
);
2866 extern void intel_uncore_early_sanitize(struct drm_i915_private
*dev_priv
,
2867 bool restore_forcewake
);
2868 extern void intel_uncore_init(struct drm_i915_private
*dev_priv
);
2869 extern bool intel_uncore_unclaimed_mmio(struct drm_i915_private
*dev_priv
);
2870 extern bool intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private
*dev_priv
);
2871 extern void intel_uncore_fini(struct drm_i915_private
*dev_priv
);
2872 extern void intel_uncore_forcewake_reset(struct drm_i915_private
*dev_priv
,
2874 const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id
);
2875 void intel_uncore_forcewake_get(struct drm_i915_private
*dev_priv
,
2876 enum forcewake_domains domains
);
2877 void intel_uncore_forcewake_put(struct drm_i915_private
*dev_priv
,
2878 enum forcewake_domains domains
);
2879 /* Like above but the caller must manage the uncore.lock itself.
2880 * Must be used with I915_READ_FW and friends.
2882 void intel_uncore_forcewake_get__locked(struct drm_i915_private
*dev_priv
,
2883 enum forcewake_domains domains
);
2884 void intel_uncore_forcewake_put__locked(struct drm_i915_private
*dev_priv
,
2885 enum forcewake_domains domains
);
2886 u64
intel_uncore_edram_size(struct drm_i915_private
*dev_priv
);
2888 void assert_forcewakes_inactive(struct drm_i915_private
*dev_priv
);
2890 int intel_wait_for_register(struct drm_i915_private
*dev_priv
,
2894 const unsigned long timeout_ms
);
2895 int intel_wait_for_register_fw(struct drm_i915_private
*dev_priv
,
2899 const unsigned long timeout_ms
);
2901 static inline bool intel_gvt_active(struct drm_i915_private
*dev_priv
)
2903 return dev_priv
->gvt
.initialized
;
2906 static inline bool intel_vgpu_active(struct drm_i915_private
*dev_priv
)
2908 return dev_priv
->vgpu
.active
;
2912 i915_enable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
2916 i915_disable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
2919 void valleyview_enable_display_irqs(struct drm_i915_private
*dev_priv
);
2920 void valleyview_disable_display_irqs(struct drm_i915_private
*dev_priv
);
2921 void i915_hotplug_interrupt_update(struct drm_i915_private
*dev_priv
,
2924 void ilk_update_display_irq(struct drm_i915_private
*dev_priv
,
2925 uint32_t interrupt_mask
,
2926 uint32_t enabled_irq_mask
);
2928 ilk_enable_display_irq(struct drm_i915_private
*dev_priv
, uint32_t bits
)
2930 ilk_update_display_irq(dev_priv
, bits
, bits
);
2933 ilk_disable_display_irq(struct drm_i915_private
*dev_priv
, uint32_t bits
)
2935 ilk_update_display_irq(dev_priv
, bits
, 0);
2937 void bdw_update_pipe_irq(struct drm_i915_private
*dev_priv
,
2939 uint32_t interrupt_mask
,
2940 uint32_t enabled_irq_mask
);
2941 static inline void bdw_enable_pipe_irq(struct drm_i915_private
*dev_priv
,
2942 enum pipe pipe
, uint32_t bits
)
2944 bdw_update_pipe_irq(dev_priv
, pipe
, bits
, bits
);
2946 static inline void bdw_disable_pipe_irq(struct drm_i915_private
*dev_priv
,
2947 enum pipe pipe
, uint32_t bits
)
2949 bdw_update_pipe_irq(dev_priv
, pipe
, bits
, 0);
2951 void ibx_display_interrupt_update(struct drm_i915_private
*dev_priv
,
2952 uint32_t interrupt_mask
,
2953 uint32_t enabled_irq_mask
);
2955 ibx_enable_display_interrupt(struct drm_i915_private
*dev_priv
, uint32_t bits
)
2957 ibx_display_interrupt_update(dev_priv
, bits
, bits
);
2960 ibx_disable_display_interrupt(struct drm_i915_private
*dev_priv
, uint32_t bits
)
2962 ibx_display_interrupt_update(dev_priv
, bits
, 0);
2966 int i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
2967 struct drm_file
*file_priv
);
2968 int i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
2969 struct drm_file
*file_priv
);
2970 int i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
2971 struct drm_file
*file_priv
);
2972 int i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
2973 struct drm_file
*file_priv
);
2974 int i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
2975 struct drm_file
*file_priv
);
2976 int i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
2977 struct drm_file
*file_priv
);
2978 int i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
2979 struct drm_file
*file_priv
);
2980 int i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
2981 struct drm_file
*file_priv
);
2982 int i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
2983 struct drm_file
*file_priv
);
2984 int i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
2985 struct drm_file
*file_priv
);
2986 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
2987 struct drm_file
*file
);
2988 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
2989 struct drm_file
*file
);
2990 int i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
2991 struct drm_file
*file_priv
);
2992 int i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
2993 struct drm_file
*file_priv
);
2994 int i915_gem_set_tiling(struct drm_device
*dev
, void *data
,
2995 struct drm_file
*file_priv
);
2996 int i915_gem_get_tiling(struct drm_device
*dev
, void *data
,
2997 struct drm_file
*file_priv
);
2998 void i915_gem_init_userptr(struct drm_i915_private
*dev_priv
);
2999 int i915_gem_userptr_ioctl(struct drm_device
*dev
, void *data
,
3000 struct drm_file
*file
);
3001 int i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
3002 struct drm_file
*file_priv
);
3003 int i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
,
3004 struct drm_file
*file_priv
);
3005 void i915_gem_load_init(struct drm_device
*dev
);
3006 void i915_gem_load_cleanup(struct drm_device
*dev
);
3007 void i915_gem_load_init_fences(struct drm_i915_private
*dev_priv
);
3008 int i915_gem_freeze_late(struct drm_i915_private
*dev_priv
);
3010 void *i915_gem_object_alloc(struct drm_device
*dev
);
3011 void i915_gem_object_free(struct drm_i915_gem_object
*obj
);
3012 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
3013 const struct drm_i915_gem_object_ops
*ops
);
3014 struct drm_i915_gem_object
*i915_gem_object_create(struct drm_device
*dev
,
3016 struct drm_i915_gem_object
*i915_gem_object_create_from_data(
3017 struct drm_device
*dev
, const void *data
, size_t size
);
3018 void i915_gem_close_object(struct drm_gem_object
*gem
, struct drm_file
*file
);
3019 void i915_gem_free_object(struct drm_gem_object
*obj
);
3022 i915_gem_object_ggtt_pin(struct drm_i915_gem_object
*obj
,
3023 const struct i915_ggtt_view
*view
,
3028 int i915_vma_bind(struct i915_vma
*vma
, enum i915_cache_level cache_level
,
3030 void __i915_vma_set_map_and_fenceable(struct i915_vma
*vma
);
3031 int __must_check
i915_vma_unbind(struct i915_vma
*vma
);
3032 void i915_vma_close(struct i915_vma
*vma
);
3033 void i915_vma_destroy(struct i915_vma
*vma
);
3035 int i915_gem_object_unbind(struct drm_i915_gem_object
*obj
);
3036 int i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
);
3037 void i915_gem_release_all_mmaps(struct drm_i915_private
*dev_priv
);
3038 void i915_gem_release_mmap(struct drm_i915_gem_object
*obj
);
3040 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object
*obj
,
3041 int *needs_clflush
);
3043 int __must_check
i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
);
3045 static inline int __sg_page_count(struct scatterlist
*sg
)
3047 return sg
->length
>> PAGE_SHIFT
;
3051 i915_gem_object_get_dirty_page(struct drm_i915_gem_object
*obj
, int n
);
3053 static inline dma_addr_t
3054 i915_gem_object_get_dma_address(struct drm_i915_gem_object
*obj
, int n
)
3056 if (n
< obj
->get_page
.last
) {
3057 obj
->get_page
.sg
= obj
->pages
->sgl
;
3058 obj
->get_page
.last
= 0;
3061 while (obj
->get_page
.last
+ __sg_page_count(obj
->get_page
.sg
) <= n
) {
3062 obj
->get_page
.last
+= __sg_page_count(obj
->get_page
.sg
++);
3063 if (unlikely(sg_is_chain(obj
->get_page
.sg
)))
3064 obj
->get_page
.sg
= sg_chain_ptr(obj
->get_page
.sg
);
3067 return sg_dma_address(obj
->get_page
.sg
) + ((n
- obj
->get_page
.last
) << PAGE_SHIFT
);
3070 static inline struct page
*
3071 i915_gem_object_get_page(struct drm_i915_gem_object
*obj
, int n
)
3073 if (WARN_ON(n
>= obj
->base
.size
>> PAGE_SHIFT
))
3076 if (n
< obj
->get_page
.last
) {
3077 obj
->get_page
.sg
= obj
->pages
->sgl
;
3078 obj
->get_page
.last
= 0;
3081 while (obj
->get_page
.last
+ __sg_page_count(obj
->get_page
.sg
) <= n
) {
3082 obj
->get_page
.last
+= __sg_page_count(obj
->get_page
.sg
++);
3083 if (unlikely(sg_is_chain(obj
->get_page
.sg
)))
3084 obj
->get_page
.sg
= sg_chain_ptr(obj
->get_page
.sg
);
3087 return nth_page(sg_page(obj
->get_page
.sg
), n
- obj
->get_page
.last
);
3090 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object
*obj
)
3092 BUG_ON(obj
->pages
== NULL
);
3093 obj
->pages_pin_count
++;
3096 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object
*obj
)
3098 BUG_ON(obj
->pages_pin_count
== 0);
3099 obj
->pages_pin_count
--;
3103 * i915_gem_object_pin_map - return a contiguous mapping of the entire object
3104 * @obj - the object to map into kernel address space
3106 * Calls i915_gem_object_pin_pages() to prevent reaping of the object's
3107 * pages and then returns a contiguous mapping of the backing storage into
3108 * the kernel address space.
3110 * The caller must hold the struct_mutex, and is responsible for calling
3111 * i915_gem_object_unpin_map() when the mapping is no longer required.
3113 * Returns the pointer through which to access the mapped object, or an
3114 * ERR_PTR() on error.
3116 void *__must_check
i915_gem_object_pin_map(struct drm_i915_gem_object
*obj
);
3119 * i915_gem_object_unpin_map - releases an earlier mapping
3120 * @obj - the object to unmap
3122 * After pinning the object and mapping its pages, once you are finished
3123 * with your access, call i915_gem_object_unpin_map() to release the pin
3124 * upon the mapping. Once the pin count reaches zero, that mapping may be
3127 * The caller must hold the struct_mutex.
3129 static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object
*obj
)
3131 lockdep_assert_held(&obj
->base
.dev
->struct_mutex
);
3132 i915_gem_object_unpin_pages(obj
);
3135 int __must_check
i915_mutex_lock_interruptible(struct drm_device
*dev
);
3136 int i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
3137 struct drm_i915_gem_request
*to
);
3138 void i915_vma_move_to_active(struct i915_vma
*vma
,
3139 struct drm_i915_gem_request
*req
,
3140 unsigned int flags
);
3141 int i915_gem_dumb_create(struct drm_file
*file_priv
,
3142 struct drm_device
*dev
,
3143 struct drm_mode_create_dumb
*args
);
3144 int i915_gem_mmap_gtt(struct drm_file
*file_priv
, struct drm_device
*dev
,
3145 uint32_t handle
, uint64_t *offset
);
3147 void i915_gem_track_fb(struct drm_i915_gem_object
*old
,
3148 struct drm_i915_gem_object
*new,
3149 unsigned frontbuffer_bits
);
3151 int __must_check
i915_gem_set_seqno(struct drm_device
*dev
, u32 seqno
);
3153 struct drm_i915_gem_request
*
3154 i915_gem_find_active_request(struct intel_engine_cs
*engine
);
3156 void i915_gem_retire_requests(struct drm_i915_private
*dev_priv
);
3158 static inline u32
i915_reset_counter(struct i915_gpu_error
*error
)
3160 return atomic_read(&error
->reset_counter
);
3163 static inline bool __i915_reset_in_progress(u32 reset
)
3165 return unlikely(reset
& I915_RESET_IN_PROGRESS_FLAG
);
3168 static inline bool __i915_reset_in_progress_or_wedged(u32 reset
)
3170 return unlikely(reset
& (I915_RESET_IN_PROGRESS_FLAG
| I915_WEDGED
));
3173 static inline bool __i915_terminally_wedged(u32 reset
)
3175 return unlikely(reset
& I915_WEDGED
);
3178 static inline bool i915_reset_in_progress(struct i915_gpu_error
*error
)
3180 return __i915_reset_in_progress(i915_reset_counter(error
));
3183 static inline bool i915_reset_in_progress_or_wedged(struct i915_gpu_error
*error
)
3185 return __i915_reset_in_progress_or_wedged(i915_reset_counter(error
));
3188 static inline bool i915_terminally_wedged(struct i915_gpu_error
*error
)
3190 return __i915_terminally_wedged(i915_reset_counter(error
));
3193 static inline u32
i915_reset_count(struct i915_gpu_error
*error
)
3195 return ((i915_reset_counter(error
) & ~I915_WEDGED
) + 1) / 2;
3198 void i915_gem_reset(struct drm_device
*dev
);
3199 bool i915_gem_clflush_object(struct drm_i915_gem_object
*obj
, bool force
);
3200 int __must_check
i915_gem_init(struct drm_device
*dev
);
3201 int __must_check
i915_gem_init_hw(struct drm_device
*dev
);
3202 void i915_gem_init_swizzling(struct drm_device
*dev
);
3203 void i915_gem_cleanup_engines(struct drm_device
*dev
);
3204 int __must_check
i915_gem_wait_for_idle(struct drm_i915_private
*dev_priv
);
3205 int __must_check
i915_gem_suspend(struct drm_device
*dev
);
3206 void i915_gem_resume(struct drm_device
*dev
);
3207 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
);
3209 i915_gem_object_wait_rendering(struct drm_i915_gem_object
*obj
,
3212 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
,
3215 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
);
3217 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
3219 const struct i915_ggtt_view
*view
);
3220 void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object
*obj
,
3221 const struct i915_ggtt_view
*view
);
3222 int i915_gem_object_attach_phys(struct drm_i915_gem_object
*obj
,
3224 int i915_gem_open(struct drm_device
*dev
, struct drm_file
*file
);
3225 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
);
3227 u64
i915_gem_get_ggtt_size(struct drm_i915_private
*dev_priv
, u64 size
,
3229 u64
i915_gem_get_ggtt_alignment(struct drm_i915_private
*dev_priv
, u64 size
,
3230 int tiling_mode
, bool fenced
);
3232 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
3233 enum i915_cache_level cache_level
);
3235 struct drm_gem_object
*i915_gem_prime_import(struct drm_device
*dev
,
3236 struct dma_buf
*dma_buf
);
3238 struct dma_buf
*i915_gem_prime_export(struct drm_device
*dev
,
3239 struct drm_gem_object
*gem_obj
, int flags
);
3241 u64
i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object
*o
,
3242 const struct i915_ggtt_view
*view
);
3243 u64
i915_gem_obj_offset(struct drm_i915_gem_object
*o
,
3244 struct i915_address_space
*vm
);
3246 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object
*o
)
3248 return i915_gem_obj_ggtt_offset_view(o
, &i915_ggtt_view_normal
);
3251 bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object
*o
,
3252 const struct i915_ggtt_view
*view
);
3253 bool i915_gem_obj_bound(struct drm_i915_gem_object
*o
,
3254 struct i915_address_space
*vm
);
3257 i915_gem_obj_to_vma(struct drm_i915_gem_object
*obj
,
3258 struct i915_address_space
*vm
);
3260 i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object
*obj
,
3261 const struct i915_ggtt_view
*view
);
3264 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object
*obj
,
3265 struct i915_address_space
*vm
);
3267 i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object
*obj
,
3268 const struct i915_ggtt_view
*view
);
3270 static inline struct i915_vma
*
3271 i915_gem_obj_to_ggtt(struct drm_i915_gem_object
*obj
)
3273 return i915_gem_obj_to_ggtt_view(obj
, &i915_ggtt_view_normal
);
3275 bool i915_gem_obj_is_pinned(struct drm_i915_gem_object
*obj
);
3277 /* Some GGTT VM helpers */
3278 static inline struct i915_hw_ppgtt
*
3279 i915_vm_to_ppgtt(struct i915_address_space
*vm
)
3281 return container_of(vm
, struct i915_hw_ppgtt
, base
);
3284 static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object
*obj
)
3286 return i915_gem_obj_ggtt_bound_view(obj
, &i915_ggtt_view_normal
);
3290 i915_gem_obj_ggtt_size(struct drm_i915_gem_object
*obj
);
3292 void i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object
*obj
,
3293 const struct i915_ggtt_view
*view
);
3295 i915_gem_object_ggtt_unpin(struct drm_i915_gem_object
*obj
)
3297 i915_gem_object_ggtt_unpin_view(obj
, &i915_ggtt_view_normal
);
3300 /* i915_gem_fence.c */
3301 int __must_check
i915_gem_object_get_fence(struct drm_i915_gem_object
*obj
);
3302 int __must_check
i915_gem_object_put_fence(struct drm_i915_gem_object
*obj
);
3304 bool i915_gem_object_pin_fence(struct drm_i915_gem_object
*obj
);
3305 void i915_gem_object_unpin_fence(struct drm_i915_gem_object
*obj
);
3307 void i915_gem_restore_fences(struct drm_device
*dev
);
3309 void i915_gem_detect_bit_6_swizzle(struct drm_device
*dev
);
3310 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
3311 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
3313 /* i915_gem_context.c */
3314 int __must_check
i915_gem_context_init(struct drm_device
*dev
);
3315 void i915_gem_context_lost(struct drm_i915_private
*dev_priv
);
3316 void i915_gem_context_fini(struct drm_device
*dev
);
3317 void i915_gem_context_reset(struct drm_device
*dev
);
3318 int i915_gem_context_open(struct drm_device
*dev
, struct drm_file
*file
);
3319 void i915_gem_context_close(struct drm_device
*dev
, struct drm_file
*file
);
3320 int i915_switch_context(struct drm_i915_gem_request
*req
);
3321 int i915_gem_switch_to_kernel_context(struct drm_i915_private
*dev_priv
);
3322 void i915_gem_context_free(struct kref
*ctx_ref
);
3323 struct drm_i915_gem_object
*
3324 i915_gem_alloc_context_obj(struct drm_device
*dev
, size_t size
);
3325 struct i915_gem_context
*
3326 i915_gem_context_create_gvt(struct drm_device
*dev
);
3328 static inline struct i915_gem_context
*
3329 i915_gem_context_lookup(struct drm_i915_file_private
*file_priv
, u32 id
)
3331 struct i915_gem_context
*ctx
;
3333 lockdep_assert_held(&file_priv
->dev_priv
->drm
.struct_mutex
);
3335 ctx
= idr_find(&file_priv
->context_idr
, id
);
3337 return ERR_PTR(-ENOENT
);
3342 static inline struct i915_gem_context
*
3343 i915_gem_context_get(struct i915_gem_context
*ctx
)
3345 kref_get(&ctx
->ref
);
3349 static inline void i915_gem_context_put(struct i915_gem_context
*ctx
)
3351 lockdep_assert_held(&ctx
->i915
->drm
.struct_mutex
);
3352 kref_put(&ctx
->ref
, i915_gem_context_free
);
3355 static inline bool i915_gem_context_is_default(const struct i915_gem_context
*c
)
3357 return c
->user_handle
== DEFAULT_CONTEXT_HANDLE
;
3360 int i915_gem_context_create_ioctl(struct drm_device
*dev
, void *data
,
3361 struct drm_file
*file
);
3362 int i915_gem_context_destroy_ioctl(struct drm_device
*dev
, void *data
,
3363 struct drm_file
*file
);
3364 int i915_gem_context_getparam_ioctl(struct drm_device
*dev
, void *data
,
3365 struct drm_file
*file_priv
);
3366 int i915_gem_context_setparam_ioctl(struct drm_device
*dev
, void *data
,
3367 struct drm_file
*file_priv
);
3368 int i915_gem_context_reset_stats_ioctl(struct drm_device
*dev
, void *data
,
3369 struct drm_file
*file
);
3371 /* i915_gem_evict.c */
3372 int __must_check
i915_gem_evict_something(struct i915_address_space
*vm
,
3373 u64 min_size
, u64 alignment
,
3374 unsigned cache_level
,
3377 int __must_check
i915_gem_evict_for_vma(struct i915_vma
*target
);
3378 int i915_gem_evict_vm(struct i915_address_space
*vm
, bool do_idle
);
3380 /* belongs in i915_gem_gtt.h */
3381 static inline void i915_gem_chipset_flush(struct drm_i915_private
*dev_priv
)
3383 if (INTEL_GEN(dev_priv
) < 6)
3384 intel_gtt_chipset_flush();
3387 /* i915_gem_stolen.c */
3388 int i915_gem_stolen_insert_node(struct drm_i915_private
*dev_priv
,
3389 struct drm_mm_node
*node
, u64 size
,
3390 unsigned alignment
);
3391 int i915_gem_stolen_insert_node_in_range(struct drm_i915_private
*dev_priv
,
3392 struct drm_mm_node
*node
, u64 size
,
3393 unsigned alignment
, u64 start
,
3395 void i915_gem_stolen_remove_node(struct drm_i915_private
*dev_priv
,
3396 struct drm_mm_node
*node
);
3397 int i915_gem_init_stolen(struct drm_device
*dev
);
3398 void i915_gem_cleanup_stolen(struct drm_device
*dev
);
3399 struct drm_i915_gem_object
*
3400 i915_gem_object_create_stolen(struct drm_device
*dev
, u32 size
);
3401 struct drm_i915_gem_object
*
3402 i915_gem_object_create_stolen_for_preallocated(struct drm_device
*dev
,
3407 /* i915_gem_shrinker.c */
3408 unsigned long i915_gem_shrink(struct drm_i915_private
*dev_priv
,
3409 unsigned long target
,
3411 #define I915_SHRINK_PURGEABLE 0x1
3412 #define I915_SHRINK_UNBOUND 0x2
3413 #define I915_SHRINK_BOUND 0x4
3414 #define I915_SHRINK_ACTIVE 0x8
3415 #define I915_SHRINK_VMAPS 0x10
3416 unsigned long i915_gem_shrink_all(struct drm_i915_private
*dev_priv
);
3417 void i915_gem_shrinker_init(struct drm_i915_private
*dev_priv
);
3418 void i915_gem_shrinker_cleanup(struct drm_i915_private
*dev_priv
);
3421 /* i915_gem_tiling.c */
3422 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object
*obj
)
3424 struct drm_i915_private
*dev_priv
= to_i915(obj
->base
.dev
);
3426 return dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_9_10_17
&&
3427 obj
->tiling_mode
!= I915_TILING_NONE
;
3430 /* i915_debugfs.c */
3431 #ifdef CONFIG_DEBUG_FS
3432 int i915_debugfs_register(struct drm_i915_private
*dev_priv
);
3433 void i915_debugfs_unregister(struct drm_i915_private
*dev_priv
);
3434 int i915_debugfs_connector_add(struct drm_connector
*connector
);
3435 void intel_display_crc_init(struct drm_device
*dev
);
3437 static inline int i915_debugfs_register(struct drm_i915_private
*dev_priv
) {return 0;}
3438 static inline void i915_debugfs_unregister(struct drm_i915_private
*dev_priv
) {}
3439 static inline int i915_debugfs_connector_add(struct drm_connector
*connector
)
3441 static inline void intel_display_crc_init(struct drm_device
*dev
) {}
3444 /* i915_gpu_error.c */
3446 void i915_error_printf(struct drm_i915_error_state_buf
*e
, const char *f
, ...);
3447 int i915_error_state_to_str(struct drm_i915_error_state_buf
*estr
,
3448 const struct i915_error_state_file_priv
*error
);
3449 int i915_error_state_buf_init(struct drm_i915_error_state_buf
*eb
,
3450 struct drm_i915_private
*i915
,
3451 size_t count
, loff_t pos
);
3452 static inline void i915_error_state_buf_release(
3453 struct drm_i915_error_state_buf
*eb
)
3457 void i915_capture_error_state(struct drm_i915_private
*dev_priv
,
3459 const char *error_msg
);
3460 void i915_error_state_get(struct drm_device
*dev
,
3461 struct i915_error_state_file_priv
*error_priv
);
3462 void i915_error_state_put(struct i915_error_state_file_priv
*error_priv
);
3463 void i915_destroy_error_state(struct drm_device
*dev
);
3465 void i915_get_extra_instdone(struct drm_i915_private
*dev_priv
, uint32_t *instdone
);
3466 const char *i915_cache_level_str(struct drm_i915_private
*i915
, int type
);
3468 /* i915_cmd_parser.c */
3469 int i915_cmd_parser_get_version(struct drm_i915_private
*dev_priv
);
3470 int intel_engine_init_cmd_parser(struct intel_engine_cs
*engine
);
3471 void intel_engine_cleanup_cmd_parser(struct intel_engine_cs
*engine
);
3472 bool intel_engine_needs_cmd_parser(struct intel_engine_cs
*engine
);
3473 int intel_engine_cmd_parser(struct intel_engine_cs
*engine
,
3474 struct drm_i915_gem_object
*batch_obj
,
3475 struct drm_i915_gem_object
*shadow_batch_obj
,
3476 u32 batch_start_offset
,
3480 /* i915_suspend.c */
3481 extern int i915_save_state(struct drm_device
*dev
);
3482 extern int i915_restore_state(struct drm_device
*dev
);
3485 void i915_setup_sysfs(struct drm_device
*dev_priv
);
3486 void i915_teardown_sysfs(struct drm_device
*dev_priv
);
3489 extern int intel_setup_gmbus(struct drm_device
*dev
);
3490 extern void intel_teardown_gmbus(struct drm_device
*dev
);
3491 extern bool intel_gmbus_is_valid_pin(struct drm_i915_private
*dev_priv
,
3494 extern struct i2c_adapter
*
3495 intel_gmbus_get_adapter(struct drm_i915_private
*dev_priv
, unsigned int pin
);
3496 extern void intel_gmbus_set_speed(struct i2c_adapter
*adapter
, int speed
);
3497 extern void intel_gmbus_force_bit(struct i2c_adapter
*adapter
, bool force_bit
);
3498 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter
*adapter
)
3500 return container_of(adapter
, struct intel_gmbus
, adapter
)->force_bit
;
3502 extern void intel_i2c_reset(struct drm_device
*dev
);
3505 int intel_bios_init(struct drm_i915_private
*dev_priv
);
3506 bool intel_bios_is_valid_vbt(const void *buf
, size_t size
);
3507 bool intel_bios_is_tv_present(struct drm_i915_private
*dev_priv
);
3508 bool intel_bios_is_lvds_present(struct drm_i915_private
*dev_priv
, u8
*i2c_pin
);
3509 bool intel_bios_is_port_present(struct drm_i915_private
*dev_priv
, enum port port
);
3510 bool intel_bios_is_port_edp(struct drm_i915_private
*dev_priv
, enum port port
);
3511 bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private
*dev_priv
, enum port port
);
3512 bool intel_bios_is_dsi_present(struct drm_i915_private
*dev_priv
, enum port
*port
);
3513 bool intel_bios_is_port_hpd_inverted(struct drm_i915_private
*dev_priv
,
3516 /* intel_opregion.c */
3518 extern int intel_opregion_setup(struct drm_i915_private
*dev_priv
);
3519 extern void intel_opregion_register(struct drm_i915_private
*dev_priv
);
3520 extern void intel_opregion_unregister(struct drm_i915_private
*dev_priv
);
3521 extern void intel_opregion_asle_intr(struct drm_i915_private
*dev_priv
);
3522 extern int intel_opregion_notify_encoder(struct intel_encoder
*intel_encoder
,
3524 extern int intel_opregion_notify_adapter(struct drm_i915_private
*dev_priv
,
3526 extern int intel_opregion_get_panel_type(struct drm_i915_private
*dev_priv
);
3528 static inline int intel_opregion_setup(struct drm_i915_private
*dev
) { return 0; }
3529 static inline void intel_opregion_register(struct drm_i915_private
*dev_priv
) { }
3530 static inline void intel_opregion_unregister(struct drm_i915_private
*dev_priv
) { }
3531 static inline void intel_opregion_asle_intr(struct drm_i915_private
*dev_priv
)
3535 intel_opregion_notify_encoder(struct intel_encoder
*intel_encoder
, bool enable
)
3540 intel_opregion_notify_adapter(struct drm_i915_private
*dev
, pci_power_t state
)
3544 static inline int intel_opregion_get_panel_type(struct drm_i915_private
*dev
)
3552 extern void intel_register_dsm_handler(void);
3553 extern void intel_unregister_dsm_handler(void);
3555 static inline void intel_register_dsm_handler(void) { return; }
3556 static inline void intel_unregister_dsm_handler(void) { return; }
3557 #endif /* CONFIG_ACPI */
3559 /* intel_device_info.c */
3560 static inline struct intel_device_info
*
3561 mkwrite_device_info(struct drm_i915_private
*dev_priv
)
3563 return (struct intel_device_info
*)&dev_priv
->info
;
3566 void intel_device_info_runtime_init(struct drm_i915_private
*dev_priv
);
3567 void intel_device_info_dump(struct drm_i915_private
*dev_priv
);
3570 extern void intel_modeset_init_hw(struct drm_device
*dev
);
3571 extern void intel_modeset_init(struct drm_device
*dev
);
3572 extern void intel_modeset_gem_init(struct drm_device
*dev
);
3573 extern void intel_modeset_cleanup(struct drm_device
*dev
);
3574 extern int intel_connector_register(struct drm_connector
*);
3575 extern void intel_connector_unregister(struct drm_connector
*);
3576 extern int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
);
3577 extern void intel_display_resume(struct drm_device
*dev
);
3578 extern void i915_redisable_vga(struct drm_device
*dev
);
3579 extern void i915_redisable_vga_power_on(struct drm_device
*dev
);
3580 extern bool ironlake_set_drps(struct drm_i915_private
*dev_priv
, u8 val
);
3581 extern void intel_init_pch_refclk(struct drm_device
*dev
);
3582 extern void intel_set_rps(struct drm_i915_private
*dev_priv
, u8 val
);
3583 extern void intel_set_memory_cxsr(struct drm_i915_private
*dev_priv
,
3586 int i915_reg_read_ioctl(struct drm_device
*dev
, void *data
,
3587 struct drm_file
*file
);
3590 extern struct intel_overlay_error_state
*
3591 intel_overlay_capture_error_state(struct drm_i915_private
*dev_priv
);
3592 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf
*e
,
3593 struct intel_overlay_error_state
*error
);
3595 extern struct intel_display_error_state
*
3596 intel_display_capture_error_state(struct drm_i915_private
*dev_priv
);
3597 extern void intel_display_print_error_state(struct drm_i915_error_state_buf
*e
,
3598 struct drm_device
*dev
,
3599 struct intel_display_error_state
*error
);
3601 int sandybridge_pcode_read(struct drm_i915_private
*dev_priv
, u32 mbox
, u32
*val
);
3602 int sandybridge_pcode_write(struct drm_i915_private
*dev_priv
, u32 mbox
, u32 val
);
3604 /* intel_sideband.c */
3605 u32
vlv_punit_read(struct drm_i915_private
*dev_priv
, u32 addr
);
3606 void vlv_punit_write(struct drm_i915_private
*dev_priv
, u32 addr
, u32 val
);
3607 u32
vlv_nc_read(struct drm_i915_private
*dev_priv
, u8 addr
);
3608 u32
vlv_iosf_sb_read(struct drm_i915_private
*dev_priv
, u8 port
, u32 reg
);
3609 void vlv_iosf_sb_write(struct drm_i915_private
*dev_priv
, u8 port
, u32 reg
, u32 val
);
3610 u32
vlv_cck_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3611 void vlv_cck_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3612 u32
vlv_ccu_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3613 void vlv_ccu_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3614 u32
vlv_bunit_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3615 void vlv_bunit_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3616 u32
vlv_dpio_read(struct drm_i915_private
*dev_priv
, enum pipe pipe
, int reg
);
3617 void vlv_dpio_write(struct drm_i915_private
*dev_priv
, enum pipe pipe
, int reg
, u32 val
);
3618 u32
intel_sbi_read(struct drm_i915_private
*dev_priv
, u16 reg
,
3619 enum intel_sbi_destination destination
);
3620 void intel_sbi_write(struct drm_i915_private
*dev_priv
, u16 reg
, u32 value
,
3621 enum intel_sbi_destination destination
);
3622 u32
vlv_flisdsi_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3623 void vlv_flisdsi_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3625 /* intel_dpio_phy.c */
3626 void chv_set_phy_signal_level(struct intel_encoder
*encoder
,
3627 u32 deemph_reg_value
, u32 margin_reg_value
,
3628 bool uniq_trans_scale
);
3629 void chv_data_lane_soft_reset(struct intel_encoder
*encoder
,
3631 void chv_phy_pre_pll_enable(struct intel_encoder
*encoder
);
3632 void chv_phy_pre_encoder_enable(struct intel_encoder
*encoder
);
3633 void chv_phy_release_cl2_override(struct intel_encoder
*encoder
);
3634 void chv_phy_post_pll_disable(struct intel_encoder
*encoder
);
3636 void vlv_set_phy_signal_level(struct intel_encoder
*encoder
,
3637 u32 demph_reg_value
, u32 preemph_reg_value
,
3638 u32 uniqtranscale_reg_value
, u32 tx3_demph
);
3639 void vlv_phy_pre_pll_enable(struct intel_encoder
*encoder
);
3640 void vlv_phy_pre_encoder_enable(struct intel_encoder
*encoder
);
3641 void vlv_phy_reset_lanes(struct intel_encoder
*encoder
);
3643 int intel_gpu_freq(struct drm_i915_private
*dev_priv
, int val
);
3644 int intel_freq_opcode(struct drm_i915_private
*dev_priv
, int val
);
3646 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3647 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3649 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3650 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3651 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3652 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
3654 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3655 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3656 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3657 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3659 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
3660 * will be implemented using 2 32-bit writes in an arbitrary order with
3661 * an arbitrary delay between them. This can cause the hardware to
3662 * act upon the intermediate value, possibly leading to corruption and
3663 * machine death. You have been warned.
3665 #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
3666 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3668 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
3669 u32 upper, lower, old_upper, loop = 0; \
3670 upper = I915_READ(upper_reg); \
3672 old_upper = upper; \
3673 lower = I915_READ(lower_reg); \
3674 upper = I915_READ(upper_reg); \
3675 } while (upper != old_upper && loop++ < 2); \
3676 (u64)upper << 32 | lower; })
3678 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3679 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
3681 #define __raw_read(x, s) \
3682 static inline uint##x##_t __raw_i915_read##x(struct drm_i915_private *dev_priv, \
3685 return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
3688 #define __raw_write(x, s) \
3689 static inline void __raw_i915_write##x(struct drm_i915_private *dev_priv, \
3690 i915_reg_t reg, uint##x##_t val) \
3692 write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
3707 /* These are untraced mmio-accessors that are only valid to be used inside
3708 * criticial sections inside IRQ handlers where forcewake is explicitly
3710 * Think twice, and think again, before using these.
3711 * Note: Should only be used between intel_uncore_forcewake_irqlock() and
3712 * intel_uncore_forcewake_irqunlock().
3714 #define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
3715 #define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
3716 #define I915_WRITE64_FW(reg__, val__) __raw_i915_write64(dev_priv, (reg__), (val__))
3717 #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
3719 /* "Broadcast RGB" property */
3720 #define INTEL_BROADCAST_RGB_AUTO 0
3721 #define INTEL_BROADCAST_RGB_FULL 1
3722 #define INTEL_BROADCAST_RGB_LIMITED 2
3724 static inline i915_reg_t
i915_vgacntrl_reg(struct drm_device
*dev
)
3726 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
))
3727 return VLV_VGACNTRL
;
3728 else if (INTEL_INFO(dev
)->gen
>= 5)
3729 return CPU_VGACNTRL
;
3734 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m
)
3736 unsigned long j
= msecs_to_jiffies(m
);
3738 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);
3741 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n
)
3743 return min_t(u64
, MAX_JIFFY_OFFSET
, nsecs_to_jiffies64(n
) + 1);
3746 static inline unsigned long
3747 timespec_to_jiffies_timeout(const struct timespec
*value
)
3749 unsigned long j
= timespec_to_jiffies(value
);
3751 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);
3755 * If you need to wait X milliseconds between events A and B, but event B
3756 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
3757 * when event A happened, then just before event B you call this function and
3758 * pass the timestamp as the first argument, and X as the second argument.
3761 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies
, int to_wait_ms
)
3763 unsigned long target_jiffies
, tmp_jiffies
, remaining_jiffies
;
3766 * Don't re-read the value of "jiffies" every time since it may change
3767 * behind our back and break the math.
3769 tmp_jiffies
= jiffies
;
3770 target_jiffies
= timestamp_jiffies
+
3771 msecs_to_jiffies_timeout(to_wait_ms
);
3773 if (time_after(target_jiffies
, tmp_jiffies
)) {
3774 remaining_jiffies
= target_jiffies
- tmp_jiffies
;
3775 while (remaining_jiffies
)
3777 schedule_timeout_uninterruptible(remaining_jiffies
);
3780 static inline bool __i915_request_irq_complete(struct drm_i915_gem_request
*req
)
3782 struct intel_engine_cs
*engine
= req
->engine
;
3784 /* Before we do the heavier coherent read of the seqno,
3785 * check the value (hopefully) in the CPU cacheline.
3787 if (i915_gem_request_completed(req
))
3790 /* Ensure our read of the seqno is coherent so that we
3791 * do not "miss an interrupt" (i.e. if this is the last
3792 * request and the seqno write from the GPU is not visible
3793 * by the time the interrupt fires, we will see that the
3794 * request is incomplete and go back to sleep awaiting
3795 * another interrupt that will never come.)
3797 * Strictly, we only need to do this once after an interrupt,
3798 * but it is easier and safer to do it every time the waiter
3801 if (engine
->irq_seqno_barrier
&&
3802 READ_ONCE(engine
->breadcrumbs
.irq_seqno_bh
) == current
&&
3803 cmpxchg_relaxed(&engine
->breadcrumbs
.irq_posted
, 1, 0)) {
3804 struct task_struct
*tsk
;
3806 /* The ordering of irq_posted versus applying the barrier
3807 * is crucial. The clearing of the current irq_posted must
3808 * be visible before we perform the barrier operation,
3809 * such that if a subsequent interrupt arrives, irq_posted
3810 * is reasserted and our task rewoken (which causes us to
3811 * do another __i915_request_irq_complete() immediately
3812 * and reapply the barrier). Conversely, if the clear
3813 * occurs after the barrier, then an interrupt that arrived
3814 * whilst we waited on the barrier would not trigger a
3815 * barrier on the next pass, and the read may not see the
3818 engine
->irq_seqno_barrier(engine
);
3820 /* If we consume the irq, but we are no longer the bottom-half,
3821 * the real bottom-half may not have serialised their own
3822 * seqno check with the irq-barrier (i.e. may have inspected
3823 * the seqno before we believe it coherent since they see
3824 * irq_posted == false but we are still running).
3827 tsk
= READ_ONCE(engine
->breadcrumbs
.irq_seqno_bh
);
3828 if (tsk
&& tsk
!= current
)
3829 /* Note that if the bottom-half is changed as we
3830 * are sending the wake-up, the new bottom-half will
3831 * be woken by whomever made the change. We only have
3832 * to worry about when we steal the irq-posted for
3835 wake_up_process(tsk
);
3838 if (i915_gem_request_completed(req
))
3842 /* We need to check whether any gpu reset happened in between
3843 * the request being submitted and now. If a reset has occurred,
3844 * the seqno will have been advance past ours and our request
3845 * is complete. If we are in the process of handling a reset,
3846 * the request is effectively complete as the rendering will
3847 * be discarded, but we need to return in order to drop the
3850 if (i915_reset_in_progress(&req
->i915
->gpu_error
))