drivers/gpu/drm/i915/i915_drv.h

   1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #ifndef _I915_DRV_H_
  31 #define _I915_DRV_H_
  32
  33 #include "i915_reg.h"
  34 #include "intel_bios.h"
  35 #include "i915_trace.h"
  36 #include "intel_ringbuffer.h"
  37 #include <linux/io-mapping.h>
  38 #include <linux/i2c.h>
  39 #include <drm/intel-gtt.h>
  40
  41 /* General customization:
  42  */
  43
  44 #define DRIVER_AUTHOR           "Tungsten Graphics, Inc."
  45
  46 #define DRIVER_NAME             "i915"
  47 #define DRIVER_DESC             "Intel Graphics"
  48 #define DRIVER_DATE             "20080730"
  49
  50 enum pipe {
  51         PIPE_A = 0,
  52         PIPE_B,
  53 };
  54
  55 enum plane {
  56         PLANE_A = 0,
  57         PLANE_B,
  58 };
  59
  60 #define I915_NUM_PIPE   2
  61
  62 #define I915_GEM_GPU_DOMAINS    (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
  63
  64 /* Interface history:
  65  *
  66  * 1.1: Original.
  67  * 1.2: Add Power Management
  68  * 1.3: Add vblank support
  69  * 1.4: Fix cmdbuffer path, add heap destroy
  70  * 1.5: Add vblank pipe configuration
  71  * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
  72  *      - Support vertical blank on secondary display pipe
  73  */
  74 #define DRIVER_MAJOR            1
  75 #define DRIVER_MINOR            6
  76 #define DRIVER_PATCHLEVEL       0
  77
  78 #define WATCH_COHERENCY 0
  79 #define WATCH_EXEC      0
  80 #define WATCH_RELOC     0
  81 #define WATCH_LISTS     0
  82 #define WATCH_PWRITE    0
  83
  84 #define I915_GEM_PHYS_CURSOR_0 1
  85 #define I915_GEM_PHYS_CURSOR_1 2
  86 #define I915_GEM_PHYS_OVERLAY_REGS 3
  87 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
  88
  89 struct drm_i915_gem_phys_object {
  90         int id;
  91         struct page **page_list;
  92         drm_dma_handle_t *handle;
  93         struct drm_gem_object *cur_obj;
  94 };
  95
  96 struct mem_block {
  97         struct mem_block *next;
  98         struct mem_block *prev;
  99         int start;
 100         int size;
 101         struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
 102 };
 103
 104 struct opregion_header;
 105 struct opregion_acpi;
 106 struct opregion_swsci;
 107 struct opregion_asle;
 108
 109 struct intel_opregion {
 110         struct opregion_header *header;
 111         struct opregion_acpi *acpi;
 112         struct opregion_swsci *swsci;
 113         struct opregion_asle *asle;
 114         void *vbt;
 115 };
 116 #define OPREGION_SIZE            (8*1024)
 117
 118 struct intel_overlay;
 119 struct intel_overlay_error_state;
 120
 121 struct drm_i915_master_private {
 122         drm_local_map_t *sarea;
 123         struct _drm_i915_sarea *sarea_priv;
 124 };
 125 #define I915_FENCE_REG_NONE -1
 126
 127 struct drm_i915_fence_reg {
 128         struct drm_gem_object *obj;
 129         struct list_head lru_list;
 130         bool gpu;
 131 };
 132
 133 struct sdvo_device_mapping {
 134         u8 initialized;
 135         u8 dvo_port;
 136         u8 slave_addr;
 137         u8 dvo_wiring;
 138         u8 i2c_pin;
 139         u8 i2c_speed;
 140         u8 ddc_pin;
 141 };
 142
 143 struct intel_display_error_state;
 144
 145 struct drm_i915_error_state {
 146         u32 eir;
 147         u32 pgtbl_er;
 148         u32 pipeastat;
 149         u32 pipebstat;
 150         u32 ipeir;
 151         u32 ipehr;
 152         u32 instdone;
 153         u32 acthd;
 154         u32 error; /* gen6+ */
 155         u32 bcs_acthd; /* gen6+ blt engine */
 156         u32 bcs_ipehr;
 157         u32 bcs_ipeir;
 158         u32 bcs_instdone;
 159         u32 bcs_seqno;
 160         u32 vcs_acthd; /* gen6+ bsd engine */
 161         u32 vcs_ipehr;
 162         u32 vcs_ipeir;
 163         u32 vcs_instdone;
 164         u32 vcs_seqno;
 165         u32 instpm;
 166         u32 instps;
 167         u32 instdone1;
 168         u32 seqno;
 169         u64 bbaddr;
 170         struct timeval time;
 171         struct drm_i915_error_object {
 172                 int page_count;
 173                 u32 gtt_offset;
 174                 u32 *pages[0];
 175         } *ringbuffer, *batchbuffer[2];
 176         struct drm_i915_error_buffer {
 177                 size_t size;
 178                 u32 name;
 179                 u32 seqno;
 180                 u32 gtt_offset;
 181                 u32 read_domains;
 182                 u32 write_domain;
 183                 u32 fence_reg;
 184                 s32 pinned:2;
 185                 u32 tiling:2;
 186                 u32 dirty:1;
 187                 u32 purgeable:1;
 188                 u32 ring:4;
 189         } *active_bo, *pinned_bo;
 190         u32 active_bo_count, pinned_bo_count;
 191         struct intel_overlay_error_state *overlay;
 192         struct intel_display_error_state *display;
 193 };
 194
 195 struct drm_i915_display_funcs {
 196         void (*dpms)(struct drm_crtc *crtc, int mode);
 197         bool (*fbc_enabled)(struct drm_device *dev);
 198         void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);
 199         void (*disable_fbc)(struct drm_device *dev);
 200         int (*get_display_clock_speed)(struct drm_device *dev);
 201         int (*get_fifo_size)(struct drm_device *dev, int plane);
 202         void (*update_wm)(struct drm_device *dev, int planea_clock,
 203                           int planeb_clock, int sr_hdisplay, int sr_htotal,
 204                           int pixel_size);
 205         /* clock updates for mode set */
 206         /* cursor updates */
 207         /* render clock increase/decrease */
 208         /* display clock increase/decrease */
 209         /* pll clock increase/decrease */
 210         /* clock gating init */
 211 };
 212
 213 struct intel_device_info {
 214         u8 gen;
 215         u8 is_mobile : 1;
 216         u8 is_i85x : 1;
 217         u8 is_i915g : 1;
 218         u8 is_i945gm : 1;
 219         u8 is_g33 : 1;
 220         u8 need_gfx_hws : 1;
 221         u8 is_g4x : 1;
 222         u8 is_pineview : 1;
 223         u8 is_broadwater : 1;
 224         u8 is_crestline : 1;
 225         u8 has_fbc : 1;
 226         u8 has_rc6 : 1;
 227         u8 has_pipe_cxsr : 1;
 228         u8 has_hotplug : 1;
 229         u8 cursor_needs_physical : 1;
 230         u8 has_overlay : 1;
 231         u8 overlay_needs_physical : 1;
 232         u8 supports_tv : 1;
 233         u8 has_bsd_ring : 1;
 234         u8 has_blt_ring : 1;
 235 };
 236
 237 enum no_fbc_reason {
 238         FBC_NO_OUTPUT, /* no outputs enabled to compress */
 239         FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */
 240         FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
 241         FBC_MODE_TOO_LARGE, /* mode too large for compression */
 242         FBC_BAD_PLANE, /* fbc not supported on plane */
 243         FBC_NOT_TILED, /* buffer not tiled */
 244         FBC_MULTIPLE_PIPES, /* more than one pipe active */
 245 };
 246
 247 enum intel_pch {
 248         PCH_IBX,        /* Ibexpeak PCH */
 249         PCH_CPT,        /* Cougarpoint PCH */
 250 };
 251
 252 #define QUIRK_PIPEA_FORCE (1<<0)
 253
 254 struct intel_fbdev;
 255
 256 typedef struct drm_i915_private {
 257         struct drm_device *dev;
 258
 259         const struct intel_device_info *info;
 260
 261         int has_gem;
 262
 263         void __iomem *regs;
 264
 265         struct intel_gmbus {
 266                 struct i2c_adapter adapter;
 267                 struct i2c_adapter *force_bit;
 268                 u32 reg0;
 269         } *gmbus;
 270
 271         struct pci_dev *bridge_dev;
 272         struct intel_ring_buffer render_ring;
 273         struct intel_ring_buffer bsd_ring;
 274         struct intel_ring_buffer blt_ring;
 275         uint32_t next_seqno;
 276
 277         drm_dma_handle_t *status_page_dmah;
 278         void *seqno_page;
 279         dma_addr_t dma_status_page;
 280         uint32_t counter;
 281         unsigned int seqno_gfx_addr;
 282         drm_local_map_t hws_map;
 283         struct drm_gem_object *seqno_obj;
 284         struct drm_gem_object *pwrctx;
 285         struct drm_gem_object *renderctx;
 286
 287         struct resource mch_res;
 288
 289         unsigned int cpp;
 290         int back_offset;
 291         int front_offset;
 292         int current_page;
 293         int page_flipping;
 294
 295         atomic_t irq_received;
 296         /** Protects user_irq_refcount and irq_mask_reg */
 297         spinlock_t user_irq_lock;
 298         u32 trace_irq_seqno;
 299         /** Cached value of IMR to avoid reads in updating the bitfield */
 300         u32 irq_mask_reg;
 301         u32 pipestat[2];
 302         /** splitted irq regs for graphics and display engine on Ironlake,
 303             irq_mask_reg is still used for display irq. */
 304         u32 gt_irq_mask_reg;
 305         u32 gt_irq_enable_reg;
 306         u32 de_irq_enable_reg;
 307         u32 pch_irq_mask_reg;
 308         u32 pch_irq_enable_reg;
 309
 310         u32 hotplug_supported_mask;
 311         struct work_struct hotplug_work;
 312
 313         int tex_lru_log_granularity;
 314         int allow_batchbuffer;
 315         struct mem_block *agp_heap;
 316         unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
 317         int vblank_pipe;
 318         int num_pipe;
 319
 320         /* For hangcheck timer */
 321 #define DRM_I915_HANGCHECK_PERIOD 250 /* in ms */
 322         struct timer_list hangcheck_timer;
 323         int hangcheck_count;
 324         uint32_t last_acthd;
 325         uint32_t last_instdone;
 326         uint32_t last_instdone1;
 327
 328         unsigned long cfb_size;
 329         unsigned long cfb_pitch;
 330         unsigned long cfb_offset;
 331         int cfb_fence;
 332         int cfb_plane;
 333         int cfb_y;
 334
 335         int irq_enabled;
 336
 337         struct intel_opregion opregion;
 338
 339         /* overlay */
 340         struct intel_overlay *overlay;
 341
 342         /* LVDS info */
 343         int backlight_level;  /* restore backlight to this value */
 344         struct drm_display_mode *panel_fixed_mode;
 345         struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
 346         struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
 347
 348         /* Feature bits from the VBIOS */
 349         unsigned int int_tv_support:1;
 350         unsigned int lvds_dither:1;
 351         unsigned int lvds_vbt:1;
 352         unsigned int int_crt_support:1;
 353         unsigned int lvds_use_ssc:1;
 354         int lvds_ssc_freq;
 355         struct {
 356                 int rate;
 357                 int lanes;
 358                 int preemphasis;
 359                 int vswing;
 360
 361                 bool initialized;
 362                 bool support;
 363                 int bpp;
 364                 struct edp_power_seq pps;
 365         } edp;
 366         bool no_aux_handshake;
 367
 368         struct notifier_block lid_notifier;
 369
 370         int crt_ddc_pin;
 371         struct drm_i915_fence_reg fence_regs[16]; /* assume 965 */
 372         int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
 373         int num_fence_regs; /* 8 on pre-965, 16 otherwise */
 374
 375         unsigned int fsb_freq, mem_freq, is_ddr3;
 376
 377         spinlock_t error_lock;
 378         struct drm_i915_error_state *first_error;
 379         struct work_struct error_work;
 380         struct completion error_completion;
 381         struct workqueue_struct *wq;
 382
 383         /* Display functions */
 384         struct drm_i915_display_funcs display;
 385
 386         /* PCH chipset type */
 387         enum intel_pch pch_type;
 388
 389         unsigned long quirks;
 390
 391         /* Register state */
 392         bool modeset_on_lid;
 393         u8 saveLBB;
 394         u32 saveDSPACNTR;
 395         u32 saveDSPBCNTR;
 396         u32 saveDSPARB;
 397         u32 saveHWS;
 398         u32 savePIPEACONF;
 399         u32 savePIPEBCONF;
 400         u32 savePIPEASRC;
 401         u32 savePIPEBSRC;
 402         u32 saveFPA0;
 403         u32 saveFPA1;
 404         u32 saveDPLL_A;
 405         u32 saveDPLL_A_MD;
 406         u32 saveHTOTAL_A;
 407         u32 saveHBLANK_A;
 408         u32 saveHSYNC_A;
 409         u32 saveVTOTAL_A;
 410         u32 saveVBLANK_A;
 411         u32 saveVSYNC_A;
 412         u32 saveBCLRPAT_A;
 413         u32 saveTRANSACONF;
 414         u32 saveTRANS_HTOTAL_A;
 415         u32 saveTRANS_HBLANK_A;
 416         u32 saveTRANS_HSYNC_A;
 417         u32 saveTRANS_VTOTAL_A;
 418         u32 saveTRANS_VBLANK_A;
 419         u32 saveTRANS_VSYNC_A;
 420         u32 savePIPEASTAT;
 421         u32 saveDSPASTRIDE;
 422         u32 saveDSPASIZE;
 423         u32 saveDSPAPOS;
 424         u32 saveDSPAADDR;
 425         u32 saveDSPASURF;
 426         u32 saveDSPATILEOFF;
 427         u32 savePFIT_PGM_RATIOS;
 428         u32 saveBLC_HIST_CTL;
 429         u32 saveBLC_PWM_CTL;
 430         u32 saveBLC_PWM_CTL2;
 431         u32 saveBLC_CPU_PWM_CTL;
 432         u32 saveBLC_CPU_PWM_CTL2;
 433         u32 saveFPB0;
 434         u32 saveFPB1;
 435         u32 saveDPLL_B;
 436         u32 saveDPLL_B_MD;
 437         u32 saveHTOTAL_B;
 438         u32 saveHBLANK_B;
 439         u32 saveHSYNC_B;
 440         u32 saveVTOTAL_B;
 441         u32 saveVBLANK_B;
 442         u32 saveVSYNC_B;
 443         u32 saveBCLRPAT_B;
 444         u32 saveTRANSBCONF;
 445         u32 saveTRANS_HTOTAL_B;
 446         u32 saveTRANS_HBLANK_B;
 447         u32 saveTRANS_HSYNC_B;
 448         u32 saveTRANS_VTOTAL_B;
 449         u32 saveTRANS_VBLANK_B;
 450         u32 saveTRANS_VSYNC_B;
 451         u32 savePIPEBSTAT;
 452         u32 saveDSPBSTRIDE;
 453         u32 saveDSPBSIZE;
 454         u32 saveDSPBPOS;
 455         u32 saveDSPBADDR;
 456         u32 saveDSPBSURF;
 457         u32 saveDSPBTILEOFF;
 458         u32 saveVGA0;
 459         u32 saveVGA1;
 460         u32 saveVGA_PD;
 461         u32 saveVGACNTRL;
 462         u32 saveADPA;
 463         u32 saveLVDS;
 464         u32 savePP_ON_DELAYS;
 465         u32 savePP_OFF_DELAYS;
 466         u32 saveDVOA;
 467         u32 saveDVOB;
 468         u32 saveDVOC;
 469         u32 savePP_ON;
 470         u32 savePP_OFF;
 471         u32 savePP_CONTROL;
 472         u32 savePP_DIVISOR;
 473         u32 savePFIT_CONTROL;
 474         u32 save_palette_a[256];
 475         u32 save_palette_b[256];
 476         u32 saveDPFC_CB_BASE;
 477         u32 saveFBC_CFB_BASE;
 478         u32 saveFBC_LL_BASE;
 479         u32 saveFBC_CONTROL;
 480         u32 saveFBC_CONTROL2;
 481         u32 saveIER;
 482         u32 saveIIR;
 483         u32 saveIMR;
 484         u32 saveDEIER;
 485         u32 saveDEIMR;
 486         u32 saveGTIER;
 487         u32 saveGTIMR;
 488         u32 saveFDI_RXA_IMR;
 489         u32 saveFDI_RXB_IMR;
 490         u32 saveCACHE_MODE_0;
 491         u32 saveMI_ARB_STATE;
 492         u32 saveSWF0[16];
 493         u32 saveSWF1[16];
 494         u32 saveSWF2[3];
 495         u8 saveMSR;
 496         u8 saveSR[8];
 497         u8 saveGR[25];
 498         u8 saveAR_INDEX;
 499         u8 saveAR[21];
 500         u8 saveDACMASK;
 501         u8 saveCR[37];
 502         uint64_t saveFENCE[16];
 503         u32 saveCURACNTR;
 504         u32 saveCURAPOS;
 505         u32 saveCURABASE;
 506         u32 saveCURBCNTR;
 507         u32 saveCURBPOS;
 508         u32 saveCURBBASE;
 509         u32 saveCURSIZE;
 510         u32 saveDP_B;
 511         u32 saveDP_C;
 512         u32 saveDP_D;
 513         u32 savePIPEA_GMCH_DATA_M;
 514         u32 savePIPEB_GMCH_DATA_M;
 515         u32 savePIPEA_GMCH_DATA_N;
 516         u32 savePIPEB_GMCH_DATA_N;
 517         u32 savePIPEA_DP_LINK_M;
 518         u32 savePIPEB_DP_LINK_M;
 519         u32 savePIPEA_DP_LINK_N;
 520         u32 savePIPEB_DP_LINK_N;
 521         u32 saveFDI_RXA_CTL;
 522         u32 saveFDI_TXA_CTL;
 523         u32 saveFDI_RXB_CTL;
 524         u32 saveFDI_TXB_CTL;
 525         u32 savePFA_CTL_1;
 526         u32 savePFB_CTL_1;
 527         u32 savePFA_WIN_SZ;
 528         u32 savePFB_WIN_SZ;
 529         u32 savePFA_WIN_POS;
 530         u32 savePFB_WIN_POS;
 531         u32 savePCH_DREF_CONTROL;
 532         u32 saveDISP_ARB_CTL;
 533         u32 savePIPEA_DATA_M1;
 534         u32 savePIPEA_DATA_N1;
 535         u32 savePIPEA_LINK_M1;
 536         u32 savePIPEA_LINK_N1;
 537         u32 savePIPEB_DATA_M1;
 538         u32 savePIPEB_DATA_N1;
 539         u32 savePIPEB_LINK_M1;
 540         u32 savePIPEB_LINK_N1;
 541         u32 saveMCHBAR_RENDER_STANDBY;
 542
 543         struct {
 544                 /** Bridge to intel-gtt-ko */
 545                 const struct intel_gtt *gtt;
 546                 /** Memory allocator for GTT stolen memory */
 547                 struct drm_mm stolen;
 548                 /** Memory allocator for GTT */
 549                 struct drm_mm gtt_space;
 550                 /** End of mappable part of GTT */
 551                 unsigned long gtt_mappable_end;
 552
 553                 struct io_mapping *gtt_mapping;
 554                 int gtt_mtrr;
 555
 556                 struct shrinker inactive_shrinker;
 557
 558                 /**
 559                  * List of objects currently involved in rendering.
 560                  *
 561                  * Includes buffers having the contents of their GPU caches
 562                  * flushed, not necessarily primitives.  last_rendering_seqno
 563                  * represents when the rendering involved will be completed.
 564                  *
 565                  * A reference is held on the buffer while on this list.
 566                  */
 567                 struct list_head active_list;
 568
 569                 /**
 570                  * List of objects which are not in the ringbuffer but which
 571                  * still have a write_domain which needs to be flushed before
 572                  * unbinding.
 573                  *
 574                  * last_rendering_seqno is 0 while an object is in this list.
 575                  *
 576                  * A reference is held on the buffer while on this list.
 577                  */
 578                 struct list_head flushing_list;
 579
 580                 /**
 581                  * LRU list of objects which are not in the ringbuffer and
 582                  * are ready to unbind, but are still in the GTT.
 583                  *
 584                  * last_rendering_seqno is 0 while an object is in this list.
 585                  *
 586                  * A reference is not held on the buffer while on this list,
 587                  * as merely being GTT-bound shouldn't prevent its being
 588                  * freed, and we'll pull it off the list in the free path.
 589                  */
 590                 struct list_head inactive_list;
 591
 592                 /**
 593                  * LRU list of objects which are not in the ringbuffer but
 594                  * are still pinned in the GTT.
 595                  */
 596                 struct list_head pinned_list;
 597
 598                 /** LRU list of objects with fence regs on them. */
 599                 struct list_head fence_list;
 600
 601                 /**
 602                  * List of objects currently pending being freed.
 603                  *
 604                  * These objects are no longer in use, but due to a signal
 605                  * we were prevented from freeing them at the appointed time.
 606                  */
 607                 struct list_head deferred_free_list;
 608
 609                 /**
 610                  * We leave the user IRQ off as much as possible,
 611                  * but this means that requests will finish and never
 612                  * be retired once the system goes idle. Set a timer to
 613                  * fire periodically while the ring is running. When it
 614                  * fires, go retire requests.
 615                  */
 616                 struct delayed_work retire_work;
 617
 618                 /**
 619                  * Flag if the X Server, and thus DRM, is not currently in
 620                  * control of the device.
 621                  *
 622                  * This is set between LeaveVT and EnterVT.  It needs to be
 623                  * replaced with a semaphore.  It also needs to be
 624                  * transitioned away from for kernel modesetting.
 625                  */
 626                 int suspended;
 627
 628                 /**
 629                  * Flag if the hardware appears to be wedged.
 630                  *
 631                  * This is set when attempts to idle the device timeout.
 632                  * It prevents command submission from occuring and makes
 633                  * every pending request fail
 634                  */
 635                 atomic_t wedged;
 636
 637                 /** Bit 6 swizzling required for X tiling */
 638                 uint32_t bit_6_swizzle_x;
 639                 /** Bit 6 swizzling required for Y tiling */
 640                 uint32_t bit_6_swizzle_y;
 641
 642                 /* storage for physical objects */
 643                 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
 644
 645                 /* accounting, useful for userland debugging */
 646                 size_t object_memory;
 647                 size_t pin_memory;
 648                 size_t gtt_memory;
 649                 size_t gtt_mappable_memory;
 650                 size_t mappable_gtt_used;
 651                 size_t mappable_gtt_total;
 652                 size_t gtt_total;
 653                 u32 object_count;
 654                 u32 pin_count;
 655                 u32 gtt_mappable_count;
 656                 u32 gtt_count;
 657         } mm;
 658         struct sdvo_device_mapping sdvo_mappings[2];
 659         /* indicate whether the LVDS_BORDER should be enabled or not */
 660         unsigned int lvds_border_bits;
 661         /* Panel fitter placement and size for Ironlake+ */
 662         u32 pch_pf_pos, pch_pf_size;
 663
 664         struct drm_crtc *plane_to_crtc_mapping[2];
 665         struct drm_crtc *pipe_to_crtc_mapping[2];
 666         wait_queue_head_t pending_flip_queue;
 667         bool flip_pending_is_done;
 668
 669         /* Reclocking support */
 670         bool render_reclock_avail;
 671         bool lvds_downclock_avail;
 672         /* indicates the reduced downclock for LVDS*/
 673         int lvds_downclock;
 674         struct work_struct idle_work;
 675         struct timer_list idle_timer;
 676         bool busy;
 677         u16 orig_clock;
 678         int child_dev_num;
 679         struct child_device_config *child_dev;
 680         struct drm_connector *int_lvds_connector;
 681
 682         bool mchbar_need_disable;
 683
 684         u8 cur_delay;
 685         u8 min_delay;
 686         u8 max_delay;
 687         u8 fmax;
 688         u8 fstart;
 689
 690         u64 last_count1;
 691         unsigned long last_time1;
 692         u64 last_count2;
 693         struct timespec last_time2;
 694         unsigned long gfx_power;
 695         int c_m;
 696         int r_t;
 697         u8 corr;
 698         spinlock_t *mchdev_lock;
 699
 700         enum no_fbc_reason no_fbc_reason;
 701
 702         struct drm_mm_node *compressed_fb;
 703         struct drm_mm_node *compressed_llb;
 704
 705         unsigned long last_gpu_reset;
 706
 707         /* list of fbdev register on this device */
 708         struct intel_fbdev *fbdev;
 709 } drm_i915_private_t;
 710
 711 /** driver private structure attached to each drm_gem_object */
 712 struct drm_i915_gem_object {
 713         struct drm_gem_object base;
 714
 715         /** Current space allocated to this object in the GTT, if any. */
 716         struct drm_mm_node *gtt_space;
 717
 718         /** This object's place on the active/flushing/inactive lists */
 719         struct list_head ring_list;
 720         struct list_head mm_list;
 721         /** This object's place on GPU write list */
 722         struct list_head gpu_write_list;
 723         /** This object's place on eviction list */
 724         struct list_head evict_list;
 725
 726         /**
 727          * This is set if the object is on the active or flushing lists
 728          * (has pending rendering), and is not set if it's on inactive (ready
 729          * to be unbound).
 730          */
 731         unsigned int active : 1;
 732
 733         /**
 734          * This is set if the object has been written to since last bound
 735          * to the GTT
 736          */
 737         unsigned int dirty : 1;
 738
 739         /**
 740          * Fence register bits (if any) for this object.  Will be set
 741          * as needed when mapped into the GTT.
 742          * Protected by dev->struct_mutex.
 743          *
 744          * Size: 4 bits for 16 fences + sign (for FENCE_REG_NONE)
 745          */
 746         signed int fence_reg : 5;
 747
 748         /**
 749          * Used for checking the object doesn't appear more than once
 750          * in an execbuffer object list.
 751          */
 752         unsigned int in_execbuffer : 1;
 753
 754         /**
 755          * Advice: are the backing pages purgeable?
 756          */
 757         unsigned int madv : 2;
 758
 759         /**
 760          * Current tiling mode for the object.
 761          */
 762         unsigned int tiling_mode : 2;
 763
 764         /** How many users have pinned this object in GTT space. The following
 765          * users can each hold at most one reference: pwrite/pread, pin_ioctl
 766          * (via user_pin_count), execbuffer (objects are not allowed multiple
 767          * times for the same batchbuffer), and the framebuffer code. When
 768          * switching/pageflipping, the framebuffer code has at most two buffers
 769          * pinned per crtc.
 770          *
 771          * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
 772          * bits with absolutely no headroom. So use 4 bits. */
 773         unsigned int pin_count : 4;
 774 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
 775
 776         /**
 777          * Is the object at the current location in the gtt mappable and
 778          * fenceable? Used to avoid costly recalculations.
 779          */
 780         unsigned int map_and_fenceable : 1;
 781
 782         /**
 783          * Whether the current gtt mapping needs to be mappable (and isn't just
 784          * mappable by accident). Track pin and fault separate for a more
 785          * accurate mappable working set.
 786          */
 787         unsigned int fault_mappable : 1;
 788         unsigned int pin_mappable : 1;
 789
 790         /** AGP memory structure for our GTT binding. */
 791         DRM_AGP_MEM *agp_mem;
 792
 793         struct page **pages;
 794
 795         /**
 796          * Current offset of the object in GTT space.
 797          *
 798          * This is the same as gtt_space->start
 799          */
 800         uint32_t gtt_offset;
 801
 802         /* Which ring is refering to is this object */
 803         struct intel_ring_buffer *ring;
 804
 805         /** Breadcrumb of last rendering to the buffer. */
 806         uint32_t last_rendering_seqno;
 807
 808         /** Current tiling stride for the object, if it's tiled. */
 809         uint32_t stride;
 810
 811         /** Record of address bit 17 of each page at last unbind. */
 812         unsigned long *bit_17;
 813
 814         /** AGP mapping type (AGP_USER_MEMORY or AGP_USER_CACHED_MEMORY */
 815         uint32_t agp_type;
 816
 817         /**
 818          * If present, while GEM_DOMAIN_CPU is in the read domain this array
 819          * flags which individual pages are valid.
 820          */
 821         uint8_t *page_cpu_valid;
 822
 823         /** User space pin count and filp owning the pin */
 824         uint32_t user_pin_count;
 825         struct drm_file *pin_filp;
 826
 827         /** for phy allocated objects */
 828         struct drm_i915_gem_phys_object *phys_obj;
 829
 830         /**
 831          * Number of crtcs where this object is currently the fb, but
 832          * will be page flipped away on the next vblank.  When it
 833          * reaches 0, dev_priv->pending_flip_queue will be woken up.
 834          */
 835         atomic_t pending_flip;
 836 };
 837
 838 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
 839
 840 /**
 841  * Request queue structure.
 842  *
 843  * The request queue allows us to note sequence numbers that have been emitted
 844  * and may be associated with active buffers to be retired.
 845  *
 846  * By keeping this list, we can avoid having to do questionable
 847  * sequence-number comparisons on buffer last_rendering_seqnos, and associate
 848  * an emission time with seqnos for tracking how far ahead of the GPU we are.
 849  */
 850 struct drm_i915_gem_request {
 851         /** On Which ring this request was generated */
 852         struct intel_ring_buffer *ring;
 853
 854         /** GEM sequence number associated with this request. */
 855         uint32_t seqno;
 856
 857         /** Time at which this request was emitted, in jiffies. */
 858         unsigned long emitted_jiffies;
 859
 860         /** global list entry for this request */
 861         struct list_head list;
 862
 863         struct drm_i915_file_private *file_priv;
 864         /** file_priv list entry for this request */
 865         struct list_head client_list;
 866 };
 867
 868 struct drm_i915_file_private {
 869         struct {
 870                 struct spinlock lock;
 871                 struct list_head request_list;
 872         } mm;
 873 };
 874
 875 enum intel_chip_family {
 876         CHIP_I8XX = 0x01,
 877         CHIP_I9XX = 0x02,
 878         CHIP_I915 = 0x04,
 879         CHIP_I965 = 0x08,
 880 };
 881
 882 #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
 883
 884 #define IS_I830(dev)            ((dev)->pci_device == 0x3577)
 885 #define IS_845G(dev)            ((dev)->pci_device == 0x2562)
 886 #define IS_I85X(dev)            (INTEL_INFO(dev)->is_i85x)
 887 #define IS_I865G(dev)           ((dev)->pci_device == 0x2572)
 888 #define IS_I915G(dev)           (INTEL_INFO(dev)->is_i915g)
 889 #define IS_I915GM(dev)          ((dev)->pci_device == 0x2592)
 890 #define IS_I945G(dev)           ((dev)->pci_device == 0x2772)
 891 #define IS_I945GM(dev)          (INTEL_INFO(dev)->is_i945gm)
 892 #define IS_BROADWATER(dev)      (INTEL_INFO(dev)->is_broadwater)
 893 #define IS_CRESTLINE(dev)       (INTEL_INFO(dev)->is_crestline)
 894 #define IS_GM45(dev)            ((dev)->pci_device == 0x2A42)
 895 #define IS_G4X(dev)             (INTEL_INFO(dev)->is_g4x)
 896 #define IS_PINEVIEW_G(dev)      ((dev)->pci_device == 0xa001)
 897 #define IS_PINEVIEW_M(dev)      ((dev)->pci_device == 0xa011)
 898 #define IS_PINEVIEW(dev)        (INTEL_INFO(dev)->is_pineview)
 899 #define IS_G33(dev)             (INTEL_INFO(dev)->is_g33)
 900 #define IS_IRONLAKE_D(dev)      ((dev)->pci_device == 0x0042)
 901 #define IS_IRONLAKE_M(dev)      ((dev)->pci_device == 0x0046)
 902 #define IS_MOBILE(dev)          (INTEL_INFO(dev)->is_mobile)
 903
 904 #define IS_GEN2(dev)    (INTEL_INFO(dev)->gen == 2)
 905 #define IS_GEN3(dev)    (INTEL_INFO(dev)->gen == 3)
 906 #define IS_GEN4(dev)    (INTEL_INFO(dev)->gen == 4)
 907 #define IS_GEN5(dev)    (INTEL_INFO(dev)->gen == 5)
 908 #define IS_GEN6(dev)    (INTEL_INFO(dev)->gen == 6)
 909
 910 #define HAS_BSD(dev)            (INTEL_INFO(dev)->has_bsd_ring)
 911 #define HAS_BLT(dev)            (INTEL_INFO(dev)->has_blt_ring)
 912 #define I915_NEED_GFX_HWS(dev)  (INTEL_INFO(dev)->need_gfx_hws)
 913
 914 #define HAS_OVERLAY(dev)                (INTEL_INFO(dev)->has_overlay)
 915 #define OVERLAY_NEEDS_PHYSICAL(dev)     (INTEL_INFO(dev)->overlay_needs_physical)
 916
 917 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
 918  * rows, which changed the alignment requirements and fence programming.
 919  */
 920 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
 921                                                       IS_I915GM(dev)))
 922 #define SUPPORTS_DIGITAL_OUTPUTS(dev)   (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
 923 #define SUPPORTS_INTEGRATED_HDMI(dev)   (IS_G4X(dev) || IS_GEN5(dev))
 924 #define SUPPORTS_INTEGRATED_DP(dev)     (IS_G4X(dev) || IS_GEN5(dev))
 925 #define SUPPORTS_EDP(dev)               (IS_IRONLAKE_M(dev))
 926 #define SUPPORTS_TV(dev)                (INTEL_INFO(dev)->supports_tv)
 927 #define I915_HAS_HOTPLUG(dev)            (INTEL_INFO(dev)->has_hotplug)
 928 /* dsparb controlled by hw only */
 929 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
 930
 931 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
 932 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
 933 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
 934 #define I915_HAS_RC6(dev) (INTEL_INFO(dev)->has_rc6)
 935
 936 #define HAS_PCH_SPLIT(dev) (IS_GEN5(dev) || IS_GEN6(dev))
 937 #define HAS_PIPE_CONTROL(dev) (IS_GEN5(dev) || IS_GEN6(dev))
 938
 939 #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
 940 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
 941 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
 942
 943 extern struct drm_ioctl_desc i915_ioctls[];
 944 extern int i915_max_ioctl;
 945 extern unsigned int i915_fbpercrtc;
 946 extern unsigned int i915_powersave;
 947 extern unsigned int i915_lvds_downclock;
 948
 949 extern int i915_suspend(struct drm_device *dev, pm_message_t state);
 950 extern int i915_resume(struct drm_device *dev);
 951 extern void i915_save_display(struct drm_device *dev);
 952 extern void i915_restore_display(struct drm_device *dev);
 953 extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
 954 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
 955
 956                                 /* i915_dma.c */
 957 extern void i915_kernel_lost_context(struct drm_device * dev);
 958 extern int i915_driver_load(struct drm_device *, unsigned long flags);
 959 extern int i915_driver_unload(struct drm_device *);
 960 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
 961 extern void i915_driver_lastclose(struct drm_device * dev);
 962 extern void i915_driver_preclose(struct drm_device *dev,
 963                                  struct drm_file *file_priv);
 964 extern void i915_driver_postclose(struct drm_device *dev,
 965                                   struct drm_file *file_priv);
 966 extern int i915_driver_device_is_agp(struct drm_device * dev);
 967 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
 968                               unsigned long arg);
 969 extern int i915_emit_box(struct drm_device *dev,
 970                          struct drm_clip_rect *boxes,
 971                          int i, int DR1, int DR4);
 972 extern int i915_reset(struct drm_device *dev, u8 flags);
 973 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
 974 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
 975 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
 976 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
 977
 978
 979 /* i915_irq.c */
 980 void i915_hangcheck_elapsed(unsigned long data);
 981 void i915_handle_error(struct drm_device *dev, bool wedged);
 982 extern int i915_irq_emit(struct drm_device *dev, void *data,
 983                          struct drm_file *file_priv);
 984 extern int i915_irq_wait(struct drm_device *dev, void *data,
 985                          struct drm_file *file_priv);
 986 void i915_trace_irq_get(struct drm_device *dev, u32 seqno);
 987 extern void i915_enable_interrupt (struct drm_device *dev);
 988
 989 extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
 990 extern void i915_driver_irq_preinstall(struct drm_device * dev);
 991 extern int i915_driver_irq_postinstall(struct drm_device *dev);
 992 extern void i915_driver_irq_uninstall(struct drm_device * dev);
 993 extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
 994                                 struct drm_file *file_priv);
 995 extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
 996                                 struct drm_file *file_priv);
 997 extern int i915_enable_vblank(struct drm_device *dev, int crtc);
 998 extern void i915_disable_vblank(struct drm_device *dev, int crtc);
 999 extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc);
1000 extern u32 gm45_get_vblank_counter(struct drm_device *dev, int crtc);
1001 extern int i915_vblank_swap(struct drm_device *dev, void *data,
1002                             struct drm_file *file_priv);
1003 extern void i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask);
1004 extern void i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask);
1005 extern void ironlake_enable_graphics_irq(drm_i915_private_t *dev_priv,
1006                 u32 mask);
1007 extern void ironlake_disable_graphics_irq(drm_i915_private_t *dev_priv,
1008                 u32 mask);
1009
1010 void
1011 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1012
1013 void
1014 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1015
1016 void intel_enable_asle (struct drm_device *dev);
1017
1018 #ifdef CONFIG_DEBUG_FS
1019 extern void i915_destroy_error_state(struct drm_device *dev);
1020 #else
1021 #define i915_destroy_error_state(x)
1022 #endif
1023
1024
1025 /* i915_mem.c */
1026 extern int i915_mem_alloc(struct drm_device *dev, void *data,
1027                           struct drm_file *file_priv);
1028 extern int i915_mem_free(struct drm_device *dev, void *data,
1029                          struct drm_file *file_priv);
1030 extern int i915_mem_init_heap(struct drm_device *dev, void *data,
1031                               struct drm_file *file_priv);
1032 extern int i915_mem_destroy_heap(struct drm_device *dev, void *data,
1033                                  struct drm_file *file_priv);
1034 extern void i915_mem_takedown(struct mem_block **heap);
1035 extern void i915_mem_release(struct drm_device * dev,
1036                              struct drm_file *file_priv, struct mem_block *heap);
1037 /* i915_gem.c */
1038 int i915_gem_check_is_wedged(struct drm_device *dev);
1039 int i915_gem_init_ioctl(struct drm_device *dev, void *data,
1040                         struct drm_file *file_priv);
1041 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
1042                           struct drm_file *file_priv);
1043 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
1044                          struct drm_file *file_priv);
1045 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1046                           struct drm_file *file_priv);
1047 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1048                         struct drm_file *file_priv);
1049 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1050                         struct drm_file *file_priv);
1051 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1052                               struct drm_file *file_priv);
1053 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1054                              struct drm_file *file_priv);
1055 int i915_gem_execbuffer(struct drm_device *dev, void *data,
1056                         struct drm_file *file_priv);
1057 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
1058                          struct drm_file *file_priv);
1059 int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
1060                        struct drm_file *file_priv);
1061 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
1062                          struct drm_file *file_priv);
1063 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
1064                         struct drm_file *file_priv);
1065 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
1066                             struct drm_file *file_priv);
1067 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
1068                            struct drm_file *file_priv);
1069 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
1070                            struct drm_file *file_priv);
1071 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
1072                            struct drm_file *file_priv);
1073 int i915_gem_set_tiling(struct drm_device *dev, void *data,
1074                         struct drm_file *file_priv);
1075 int i915_gem_get_tiling(struct drm_device *dev, void *data,
1076                         struct drm_file *file_priv);
1077 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
1078                                 struct drm_file *file_priv);
1079 void i915_gem_load(struct drm_device *dev);
1080 int i915_gem_init_object(struct drm_gem_object *obj);
1081 struct drm_gem_object * i915_gem_alloc_object(struct drm_device *dev,
1082                                               size_t size);
1083 void i915_gem_free_object(struct drm_gem_object *obj);
1084 int i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment,
1085                         bool map_and_fenceable);
1086 void i915_gem_object_unpin(struct drm_gem_object *obj);
1087 int i915_gem_object_unbind(struct drm_gem_object *obj);
1088 void i915_gem_release_mmap(struct drm_gem_object *obj);
1089 void i915_gem_lastclose(struct drm_device *dev);
1090
1091 /**
1092  * Returns true if seq1 is later than seq2.
1093  */
1094 static inline bool
1095 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1096 {
1097         return (int32_t)(seq1 - seq2) >= 0;
1098 }
1099
1100 int i915_gem_object_get_fence_reg(struct drm_gem_object *obj,
1101                                   bool interruptible);
1102 int i915_gem_object_put_fence_reg(struct drm_gem_object *obj,
1103                                   bool interruptible);
1104 void i915_gem_retire_requests(struct drm_device *dev);
1105 void i915_gem_reset(struct drm_device *dev);
1106 void i915_gem_clflush_object(struct drm_gem_object *obj);
1107 int i915_gem_object_set_domain(struct drm_gem_object *obj,
1108                                uint32_t read_domains,
1109                                uint32_t write_domain);
1110 int i915_gem_object_flush_gpu(struct drm_i915_gem_object *obj,
1111                               bool interruptible);
1112 int i915_gem_init_ringbuffer(struct drm_device *dev);
1113 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
1114 int i915_gem_do_init(struct drm_device *dev, unsigned long start,
1115                      unsigned long mappable_end, unsigned long end);
1116 int i915_gpu_idle(struct drm_device *dev);
1117 int i915_gem_idle(struct drm_device *dev);
1118 int i915_add_request(struct drm_device *dev,
1119                      struct drm_file *file_priv,
1120                      struct drm_i915_gem_request *request,
1121                      struct intel_ring_buffer *ring);
1122 int i915_do_wait_request(struct drm_device *dev,
1123                          uint32_t seqno,
1124                          bool interruptible,
1125                          struct intel_ring_buffer *ring);
1126 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
1127 int i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj,
1128                                       int write);
1129 int i915_gem_object_set_to_display_plane(struct drm_gem_object *obj,
1130                                          bool pipelined);
1131 int i915_gem_attach_phys_object(struct drm_device *dev,
1132                                 struct drm_gem_object *obj,
1133                                 int id,
1134                                 int align);
1135 void i915_gem_detach_phys_object(struct drm_device *dev,
1136                                  struct drm_gem_object *obj);
1137 void i915_gem_free_all_phys_object(struct drm_device *dev);
1138 void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv);
1139
1140 /* i915_gem_evict.c */
1141 int i915_gem_evict_something(struct drm_device *dev, int min_size,
1142                              unsigned alignment, bool mappable);
1143 int i915_gem_evict_everything(struct drm_device *dev, bool purgeable_only);
1144 int i915_gem_evict_inactive(struct drm_device *dev, bool purgeable_only);
1145
1146 /* i915_gem_tiling.c */
1147 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
1148 void i915_gem_object_do_bit_17_swizzle(struct drm_gem_object *obj);
1149 void i915_gem_object_save_bit_17_swizzle(struct drm_gem_object *obj);
1150
1151 /* i915_gem_debug.c */
1152 void i915_gem_dump_object(struct drm_gem_object *obj, int len,
1153                           const char *where, uint32_t mark);
1154 #if WATCH_LISTS
1155 int i915_verify_lists(struct drm_device *dev);
1156 #else
1157 #define i915_verify_lists(dev) 0
1158 #endif
1159 void i915_gem_object_check_coherency(struct drm_gem_object *obj, int handle);
1160 void i915_gem_dump_object(struct drm_gem_object *obj, int len,
1161                           const char *where, uint32_t mark);
1162
1163 /* i915_debugfs.c */
1164 int i915_debugfs_init(struct drm_minor *minor);
1165 void i915_debugfs_cleanup(struct drm_minor *minor);
1166
1167 /* i915_suspend.c */
1168 extern int i915_save_state(struct drm_device *dev);
1169 extern int i915_restore_state(struct drm_device *dev);
1170
1171 /* i915_suspend.c */
1172 extern int i915_save_state(struct drm_device *dev);
1173 extern int i915_restore_state(struct drm_device *dev);
1174
1175 /* intel_i2c.c */
1176 extern int intel_setup_gmbus(struct drm_device *dev);
1177 extern void intel_teardown_gmbus(struct drm_device *dev);
1178 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
1179 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
1180 extern inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
1181 {
1182         return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
1183 }
1184 extern void intel_i2c_reset(struct drm_device *dev);
1185
1186 /* intel_opregion.c */
1187 extern int intel_opregion_setup(struct drm_device *dev);
1188 #ifdef CONFIG_ACPI
1189 extern void intel_opregion_init(struct drm_device *dev);
1190 extern void intel_opregion_fini(struct drm_device *dev);
1191 extern void intel_opregion_asle_intr(struct drm_device *dev);
1192 extern void intel_opregion_gse_intr(struct drm_device *dev);
1193 extern void intel_opregion_enable_asle(struct drm_device *dev);
1194 #else
1195 static inline void intel_opregion_init(struct drm_device *dev) { return; }
1196 static inline void intel_opregion_fini(struct drm_device *dev) { return; }
1197 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
1198 static inline void intel_opregion_gse_intr(struct drm_device *dev) { return; }
1199 static inline void intel_opregion_enable_asle(struct drm_device *dev) { return; }
1200 #endif
1201
1202 /* intel_acpi.c */
1203 #ifdef CONFIG_ACPI
1204 extern void intel_register_dsm_handler(void);
1205 extern void intel_unregister_dsm_handler(void);
1206 #else
1207 static inline void intel_register_dsm_handler(void) { return; }
1208 static inline void intel_unregister_dsm_handler(void) { return; }
1209 #endif /* CONFIG_ACPI */
1210
1211 /* modesetting */
1212 extern void intel_modeset_init(struct drm_device *dev);
1213 extern void intel_modeset_cleanup(struct drm_device *dev);
1214 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
1215 extern void i8xx_disable_fbc(struct drm_device *dev);
1216 extern void g4x_disable_fbc(struct drm_device *dev);
1217 extern void ironlake_disable_fbc(struct drm_device *dev);
1218 extern void intel_disable_fbc(struct drm_device *dev);
1219 extern void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval);
1220 extern bool intel_fbc_enabled(struct drm_device *dev);
1221 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
1222 extern void intel_detect_pch (struct drm_device *dev);
1223 extern int intel_trans_dp_port_sel (struct drm_crtc *crtc);
1224
1225 /* overlay */
1226 #ifdef CONFIG_DEBUG_FS
1227 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
1228 extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error);
1229
1230 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
1231 extern void intel_display_print_error_state(struct seq_file *m,
1232                                             struct drm_device *dev,
1233                                             struct intel_display_error_state *error);
1234 #endif
1235
1236 /**
1237  * Lock test for when it's just for synchronization of ring access.
1238  *
1239  * In that case, we don't need to do it when GEM is initialized as nobody else
1240  * has access to the ring.
1241  */
1242 #define RING_LOCK_TEST_WITH_RETURN(dev, file_priv) do {                 \
1243         if (((drm_i915_private_t *)dev->dev_private)->render_ring.gem_object \
1244                         == NULL)                                        \
1245                 LOCK_TEST_WITH_RETURN(dev, file_priv);                  \
1246 } while (0)
1247
1248
1249 #define __i915_read(x, y) \
1250 static inline u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
1251         u##x val = read##y(dev_priv->regs + reg); \
1252         trace_i915_reg_rw('R', reg, val, sizeof(val)); \
1253         return val; \
1254 }
1255 __i915_read(8, b)
1256 __i915_read(16, w)
1257 __i915_read(32, l)
1258 __i915_read(64, q)
1259 #undef __i915_read
1260
1261 #define __i915_write(x, y) \
1262 static inline void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
1263         trace_i915_reg_rw('W', reg, val, sizeof(val)); \
1264         write##y(val, dev_priv->regs + reg); \
1265 }
1266 __i915_write(8, b)
1267 __i915_write(16, w)
1268 __i915_write(32, l)
1269 __i915_write(64, q)
1270 #undef __i915_write
1271
1272 #define I915_READ8(reg)         i915_read8(dev_priv, (reg))
1273 #define I915_WRITE8(reg, val)   i915_write8(dev_priv, (reg), (val))
1274
1275 #define I915_READ16(reg)        i915_read16(dev_priv, (reg))
1276 #define I915_WRITE16(reg, val)  i915_write16(dev_priv, (reg), (val))
1277 #define I915_READ16_NOTRACE(reg)        readw(dev_priv->regs + (reg))
1278 #define I915_WRITE16_NOTRACE(reg, val)  writew(val, dev_priv->regs + (reg))
1279
1280 #define I915_READ(reg)          i915_read32(dev_priv, (reg))
1281 #define I915_WRITE(reg, val)    i915_write32(dev_priv, (reg), (val))
1282 #define I915_READ_NOTRACE(reg)          readl(dev_priv->regs + (reg))
1283 #define I915_WRITE_NOTRACE(reg, val)    writel(val, dev_priv->regs + (reg))
1284
1285 #define I915_WRITE64(reg, val)  i915_write64(dev_priv, (reg), (val))
1286 #define I915_READ64(reg)        i915_read64(dev_priv, (reg))
1287
1288 #define POSTING_READ(reg)       (void)I915_READ_NOTRACE(reg)
1289 #define POSTING_READ16(reg)     (void)I915_READ16_NOTRACE(reg)
1290
1291
1292 /* On SNB platform, before reading ring registers forcewake bit
1293  * must be set to prevent GT core from power down and stale values being
1294  * returned.
1295  */
1296 static inline u32 i915_safe_read(struct drm_i915_private *dev_priv, u32 reg)
1297 {
1298         if (IS_GEN6(dev_priv->dev)) {
1299                 I915_WRITE_NOTRACE(FORCEWAKE, 1);
1300                 POSTING_READ(FORCEWAKE);
1301                 /* XXX How long do we really need to wait here?
1302                  * Will different registers/engines require different periods?
1303                  */
1304                 udelay(100);
1305         }
1306         return I915_READ(reg);
1307 }
1308
1309 static inline void
1310 i915_write(struct drm_i915_private *dev_priv, u32 reg, u64 val, int len)
1311 {
1312        /* Trace down the write operation before the real write */
1313        trace_i915_reg_rw('W', reg, val, len);
1314        switch (len) {
1315        case 8:
1316                writeq(val, dev_priv->regs + reg);
1317                break;
1318        case 4:
1319                writel(val, dev_priv->regs + reg);
1320                break;
1321        case 2:
1322                writew(val, dev_priv->regs + reg);
1323                break;
1324        case 1:
1325                writeb(val, dev_priv->regs + reg);
1326                break;
1327        }
1328 }
1329
1330 #define BEGIN_LP_RING(n) \
1331         intel_ring_begin(&dev_priv->render_ring, (n))
1332
1333 #define OUT_RING(x) \
1334         intel_ring_emit(&dev_priv->render_ring, x)
1335
1336 #define ADVANCE_LP_RING() \
1337         intel_ring_advance(&dev_priv->render_ring)
1338
1339 /**
1340  * Reads a dword out of the status page, which is written to from the command
1341  * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
1342  * MI_STORE_DATA_IMM.
1343  *
1344  * The following dwords have a reserved meaning:
1345  * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
1346  * 0x04: ring 0 head pointer
1347  * 0x05: ring 1 head pointer (915-class)
1348  * 0x06: ring 2 head pointer (915-class)
1349  * 0x10-0x1b: Context status DWords (GM45)
1350  * 0x1f: Last written status offset. (GM45)
1351  *
1352  * The area from dword 0x20 to 0x3ff is available for driver usage.
1353  */
1354 #define READ_HWSP(dev_priv, reg)  (((volatile u32 *)\
1355                         (dev_priv->render_ring.status_page.page_addr))[reg])
1356 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
1357 #define I915_GEM_HWS_INDEX              0x20
1358 #define I915_BREADCRUMB_INDEX           0x21
1359
1360 #endif