drivers/gpu/drm/i915/i915_drv.h

   1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #ifndef _I915_DRV_H_
  31 #define _I915_DRV_H_
  32
  33 #include <uapi/drm/i915_drm.h>
  34
  35 #include "i915_reg.h"
  36 #include "intel_bios.h"
  37 #include "intel_ringbuffer.h"
  38 #include "intel_lrc.h"
  39 #include "i915_gem_gtt.h"
  40 #include "i915_gem_render_state.h"
  41 #include <linux/io-mapping.h>
  42 #include <linux/i2c.h>
  43 #include <linux/i2c-algo-bit.h>
  44 #include <drm/intel-gtt.h>
  45 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
  46 #include <drm/drm_gem.h>
  47 #include <linux/backlight.h>
  48 #include <linux/hashtable.h>
  49 #include <linux/intel-iommu.h>
  50 #include <linux/kref.h>
  51 #include <linux/pm_qos.h>
  52
  53 /* General customization:
  54  */
  55
  56 #define DRIVER_NAME             "i915"
  57 #define DRIVER_DESC             "Intel Graphics"
  58 #define DRIVER_DATE             "20141107"
  59
  60 #undef WARN_ON
  61 #define WARN_ON(x)              WARN(x, "WARN_ON(" #x ")")
  62
  63 enum pipe {
  64         INVALID_PIPE = -1,
  65         PIPE_A = 0,
  66         PIPE_B,
  67         PIPE_C,
  68         _PIPE_EDP,
  69         I915_MAX_PIPES = _PIPE_EDP
  70 };
  71 #define pipe_name(p) ((p) + 'A')
  72
  73 enum transcoder {
  74         TRANSCODER_A = 0,
  75         TRANSCODER_B,
  76         TRANSCODER_C,
  77         TRANSCODER_EDP,
  78         I915_MAX_TRANSCODERS
  79 };
  80 #define transcoder_name(t) ((t) + 'A')
  81
  82 /*
  83  * This is the maximum (across all platforms) number of planes (primary +
  84  * sprites) that can be active at the same time on one pipe.
  85  *
  86  * This value doesn't count the cursor plane.
  87  */
  88 #define I915_MAX_PLANES 3
  89
  90 enum plane {
  91         PLANE_A = 0,
  92         PLANE_B,
  93         PLANE_C,
  94 };
  95 #define plane_name(p) ((p) + 'A')
  96
  97 #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
  98
  99 enum port {
 100         PORT_A = 0,
 101         PORT_B,
 102         PORT_C,
 103         PORT_D,
 104         PORT_E,
 105         I915_MAX_PORTS
 106 };
 107 #define port_name(p) ((p) + 'A')
 108
 109 #define I915_NUM_PHYS_VLV 2
 110
 111 enum dpio_channel {
 112         DPIO_CH0,
 113         DPIO_CH1
 114 };
 115
 116 enum dpio_phy {
 117         DPIO_PHY0,
 118         DPIO_PHY1
 119 };
 120
 121 enum intel_display_power_domain {
 122         POWER_DOMAIN_PIPE_A,
 123         POWER_DOMAIN_PIPE_B,
 124         POWER_DOMAIN_PIPE_C,
 125         POWER_DOMAIN_PIPE_A_PANEL_FITTER,
 126         POWER_DOMAIN_PIPE_B_PANEL_FITTER,
 127         POWER_DOMAIN_PIPE_C_PANEL_FITTER,
 128         POWER_DOMAIN_TRANSCODER_A,
 129         POWER_DOMAIN_TRANSCODER_B,
 130         POWER_DOMAIN_TRANSCODER_C,
 131         POWER_DOMAIN_TRANSCODER_EDP,
 132         POWER_DOMAIN_PORT_DDI_A_2_LANES,
 133         POWER_DOMAIN_PORT_DDI_A_4_LANES,
 134         POWER_DOMAIN_PORT_DDI_B_2_LANES,
 135         POWER_DOMAIN_PORT_DDI_B_4_LANES,
 136         POWER_DOMAIN_PORT_DDI_C_2_LANES,
 137         POWER_DOMAIN_PORT_DDI_C_4_LANES,
 138         POWER_DOMAIN_PORT_DDI_D_2_LANES,
 139         POWER_DOMAIN_PORT_DDI_D_4_LANES,
 140         POWER_DOMAIN_PORT_DSI,
 141         POWER_DOMAIN_PORT_CRT,
 142         POWER_DOMAIN_PORT_OTHER,
 143         POWER_DOMAIN_VGA,
 144         POWER_DOMAIN_AUDIO,
 145         POWER_DOMAIN_PLLS,
 146         POWER_DOMAIN_INIT,
 147
 148         POWER_DOMAIN_NUM,
 149 };
 150
 151 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
 152 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
 153                 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
 154 #define POWER_DOMAIN_TRANSCODER(tran) \
 155         ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
 156          (tran) + POWER_DOMAIN_TRANSCODER_A)
 157
 158 enum hpd_pin {
 159         HPD_NONE = 0,
 160         HPD_PORT_A = HPD_NONE, /* PORT_A is internal */
 161         HPD_TV = HPD_NONE,     /* TV is known to be unreliable */
 162         HPD_CRT,
 163         HPD_SDVO_B,
 164         HPD_SDVO_C,
 165         HPD_PORT_B,
 166         HPD_PORT_C,
 167         HPD_PORT_D,
 168         HPD_NUM_PINS
 169 };
 170
 171 #define I915_GEM_GPU_DOMAINS \
 172         (I915_GEM_DOMAIN_RENDER | \
 173          I915_GEM_DOMAIN_SAMPLER | \
 174          I915_GEM_DOMAIN_COMMAND | \
 175          I915_GEM_DOMAIN_INSTRUCTION | \
 176          I915_GEM_DOMAIN_VERTEX)
 177
 178 #define for_each_pipe(__dev_priv, __p) \
 179         for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
 180 #define for_each_plane(pipe, p) \
 181         for ((p) = 0; (p) < INTEL_INFO(dev)->num_sprites[(pipe)] + 1; (p)++)
 182 #define for_each_sprite(p, s) for ((s) = 0; (s) < INTEL_INFO(dev)->num_sprites[(p)]; (s)++)
 183
 184 #define for_each_crtc(dev, crtc) \
 185         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
 186
 187 #define for_each_intel_crtc(dev, intel_crtc) \
 188         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)
 189
 190 #define for_each_intel_encoder(dev, intel_encoder)              \
 191         list_for_each_entry(intel_encoder,                      \
 192                             &(dev)->mode_config.encoder_list,   \
 193                             base.head)
 194
 195 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
 196         list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
 197                 if ((intel_encoder)->base.crtc == (__crtc))
 198
 199 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
 200         list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
 201                 if ((intel_connector)->base.encoder == (__encoder))
 202
 203 #define for_each_power_domain(domain, mask)                             \
 204         for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++)     \
 205                 if ((1 << (domain)) & (mask))
 206
 207 struct drm_i915_private;
 208 struct i915_mm_struct;
 209 struct i915_mmu_object;
 210
 211 enum intel_dpll_id {
 212         DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
 213         /* real shared dpll ids must be >= 0 */
 214         DPLL_ID_PCH_PLL_A = 0,
 215         DPLL_ID_PCH_PLL_B = 1,
 216         DPLL_ID_WRPLL1 = 0,
 217         DPLL_ID_WRPLL2 = 1,
 218 };
 219 #define I915_NUM_PLLS 2
 220
 221 struct intel_dpll_hw_state {
 222         /* i9xx, pch plls */
 223         uint32_t dpll;
 224         uint32_t dpll_md;
 225         uint32_t fp0;
 226         uint32_t fp1;
 227
 228         /* hsw, bdw */
 229         uint32_t wrpll;
 230 };
 231
 232 struct intel_shared_dpll_config {
 233         unsigned crtc_mask; /* mask of CRTCs sharing this PLL */
 234         struct intel_dpll_hw_state hw_state;
 235 };
 236
 237 struct intel_shared_dpll {
 238         struct intel_shared_dpll_config config;
 239         struct intel_shared_dpll_config *new_config;
 240
 241         int active; /* count of number of active CRTCs (i.e. DPMS on) */
 242         bool on; /* is the PLL actually active? Disabled during modeset */
 243         const char *name;
 244         /* should match the index in the dev_priv->shared_dplls array */
 245         enum intel_dpll_id id;
 246         /* The mode_set hook is optional and should be used together with the
 247          * intel_prepare_shared_dpll function. */
 248         void (*mode_set)(struct drm_i915_private *dev_priv,
 249                          struct intel_shared_dpll *pll);
 250         void (*enable)(struct drm_i915_private *dev_priv,
 251                        struct intel_shared_dpll *pll);
 252         void (*disable)(struct drm_i915_private *dev_priv,
 253                         struct intel_shared_dpll *pll);
 254         bool (*get_hw_state)(struct drm_i915_private *dev_priv,
 255                              struct intel_shared_dpll *pll,
 256                              struct intel_dpll_hw_state *hw_state);
 257 };
 258
 259 /* Used by dp and fdi links */
 260 struct intel_link_m_n {
 261         uint32_t        tu;
 262         uint32_t        gmch_m;
 263         uint32_t        gmch_n;
 264         uint32_t        link_m;
 265         uint32_t        link_n;
 266 };
 267
 268 void intel_link_compute_m_n(int bpp, int nlanes,
 269                             int pixel_clock, int link_clock,
 270                             struct intel_link_m_n *m_n);
 271
 272 /* Interface history:
 273  *
 274  * 1.1: Original.
 275  * 1.2: Add Power Management
 276  * 1.3: Add vblank support
 277  * 1.4: Fix cmdbuffer path, add heap destroy
 278  * 1.5: Add vblank pipe configuration
 279  * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
 280  *      - Support vertical blank on secondary display pipe
 281  */
 282 #define DRIVER_MAJOR            1
 283 #define DRIVER_MINOR            6
 284 #define DRIVER_PATCHLEVEL       0
 285
 286 #define WATCH_LISTS     0
 287
 288 struct opregion_header;
 289 struct opregion_acpi;
 290 struct opregion_swsci;
 291 struct opregion_asle;
 292
 293 struct intel_opregion {
 294         struct opregion_header __iomem *header;
 295         struct opregion_acpi __iomem *acpi;
 296         struct opregion_swsci __iomem *swsci;
 297         u32 swsci_gbda_sub_functions;
 298         u32 swsci_sbcb_sub_functions;
 299         struct opregion_asle __iomem *asle;
 300         void __iomem *vbt;
 301         u32 __iomem *lid_state;
 302         struct work_struct asle_work;
 303 };
 304 #define OPREGION_SIZE            (8*1024)
 305
 306 struct intel_overlay;
 307 struct intel_overlay_error_state;
 308
 309 struct drm_local_map;
 310
 311 struct drm_i915_master_private {
 312         struct drm_local_map *sarea;
 313         struct _drm_i915_sarea *sarea_priv;
 314 };
 315 #define I915_FENCE_REG_NONE -1
 316 #define I915_MAX_NUM_FENCES 32
 317 /* 32 fences + sign bit for FENCE_REG_NONE */
 318 #define I915_MAX_NUM_FENCE_BITS 6
 319
 320 struct drm_i915_fence_reg {
 321         struct list_head lru_list;
 322         struct drm_i915_gem_object *obj;
 323         int pin_count;
 324 };
 325
 326 struct sdvo_device_mapping {
 327         u8 initialized;
 328         u8 dvo_port;
 329         u8 slave_addr;
 330         u8 dvo_wiring;
 331         u8 i2c_pin;
 332         u8 ddc_pin;
 333 };
 334
 335 struct intel_display_error_state;
 336
 337 struct drm_i915_error_state {
 338         struct kref ref;
 339         struct timeval time;
 340
 341         char error_msg[128];
 342         u32 reset_count;
 343         u32 suspend_count;
 344
 345         /* Generic register state */
 346         u32 eir;
 347         u32 pgtbl_er;
 348         u32 ier;
 349         u32 gtier[4];
 350         u32 ccid;
 351         u32 derrmr;
 352         u32 forcewake;
 353         u32 error; /* gen6+ */
 354         u32 err_int; /* gen7 */
 355         u32 done_reg;
 356         u32 gac_eco;
 357         u32 gam_ecochk;
 358         u32 gab_ctl;
 359         u32 gfx_mode;
 360         u32 extra_instdone[I915_NUM_INSTDONE_REG];
 361         u64 fence[I915_MAX_NUM_FENCES];
 362         struct intel_overlay_error_state *overlay;
 363         struct intel_display_error_state *display;
 364         struct drm_i915_error_object *semaphore_obj;
 365
 366         struct drm_i915_error_ring {
 367                 bool valid;
 368                 /* Software tracked state */
 369                 bool waiting;
 370                 int hangcheck_score;
 371                 enum intel_ring_hangcheck_action hangcheck_action;
 372                 int num_requests;
 373
 374                 /* our own tracking of ring head and tail */
 375                 u32 cpu_ring_head;
 376                 u32 cpu_ring_tail;
 377
 378                 u32 semaphore_seqno[I915_NUM_RINGS - 1];
 379
 380                 /* Register state */
 381                 u32 tail;
 382                 u32 head;
 383                 u32 ctl;
 384                 u32 hws;
 385                 u32 ipeir;
 386                 u32 ipehr;
 387                 u32 instdone;
 388                 u32 bbstate;
 389                 u32 instpm;
 390                 u32 instps;
 391                 u32 seqno;
 392                 u64 bbaddr;
 393                 u64 acthd;
 394                 u32 fault_reg;
 395                 u64 faddr;
 396                 u32 rc_psmi; /* sleep state */
 397                 u32 semaphore_mboxes[I915_NUM_RINGS - 1];
 398
 399                 struct drm_i915_error_object {
 400                         int page_count;
 401                         u32 gtt_offset;
 402                         u32 *pages[0];
 403                 } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
 404
 405                 struct drm_i915_error_request {
 406                         long jiffies;
 407                         u32 seqno;
 408                         u32 tail;
 409                 } *requests;
 410
 411                 struct {
 412                         u32 gfx_mode;
 413                         union {
 414                                 u64 pdp[4];
 415                                 u32 pp_dir_base;
 416                         };
 417                 } vm_info;
 418
 419                 pid_t pid;
 420                 char comm[TASK_COMM_LEN];
 421         } ring[I915_NUM_RINGS];
 422
 423         struct drm_i915_error_buffer {
 424                 u32 size;
 425                 u32 name;
 426                 u32 rseqno, wseqno;
 427                 u32 gtt_offset;
 428                 u32 read_domains;
 429                 u32 write_domain;
 430                 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
 431                 s32 pinned:2;
 432                 u32 tiling:2;
 433                 u32 dirty:1;
 434                 u32 purgeable:1;
 435                 u32 userptr:1;
 436                 s32 ring:4;
 437                 u32 cache_level:3;
 438         } **active_bo, **pinned_bo;
 439
 440         u32 *active_bo_count, *pinned_bo_count;
 441         u32 vm_count;
 442 };
 443
 444 struct intel_connector;
 445 struct intel_encoder;
 446 struct intel_crtc_config;
 447 struct intel_plane_config;
 448 struct intel_crtc;
 449 struct intel_limit;
 450 struct dpll;
 451
 452 struct drm_i915_display_funcs {
 453         bool (*fbc_enabled)(struct drm_device *dev);
 454         void (*enable_fbc)(struct drm_crtc *crtc);
 455         void (*disable_fbc)(struct drm_device *dev);
 456         int (*get_display_clock_speed)(struct drm_device *dev);
 457         int (*get_fifo_size)(struct drm_device *dev, int plane);
 458         /**
 459          * find_dpll() - Find the best values for the PLL
 460          * @limit: limits for the PLL
 461          * @crtc: current CRTC
 462          * @target: target frequency in kHz
 463          * @refclk: reference clock frequency in kHz
 464          * @match_clock: if provided, @best_clock P divider must
 465          *               match the P divider from @match_clock
 466          *               used for LVDS downclocking
 467          * @best_clock: best PLL values found
 468          *
 469          * Returns true on success, false on failure.
 470          */
 471         bool (*find_dpll)(const struct intel_limit *limit,
 472                           struct intel_crtc *crtc,
 473                           int target, int refclk,
 474                           struct dpll *match_clock,
 475                           struct dpll *best_clock);
 476         void (*update_wm)(struct drm_crtc *crtc);
 477         void (*update_sprite_wm)(struct drm_plane *plane,
 478                                  struct drm_crtc *crtc,
 479                                  uint32_t sprite_width, uint32_t sprite_height,
 480                                  int pixel_size, bool enable, bool scaled);
 481         void (*modeset_global_resources)(struct drm_device *dev);
 482         /* Returns the active state of the crtc, and if the crtc is active,
 483          * fills out the pipe-config with the hw state. */
 484         bool (*get_pipe_config)(struct intel_crtc *,
 485                                 struct intel_crtc_config *);
 486         void (*get_plane_config)(struct intel_crtc *,
 487                                  struct intel_plane_config *);
 488         int (*crtc_compute_clock)(struct intel_crtc *crtc);
 489         void (*crtc_enable)(struct drm_crtc *crtc);
 490         void (*crtc_disable)(struct drm_crtc *crtc);
 491         void (*off)(struct drm_crtc *crtc);
 492         void (*audio_codec_enable)(struct drm_connector *connector,
 493                                    struct intel_encoder *encoder,
 494                                    struct drm_display_mode *mode);
 495         void (*audio_codec_disable)(struct intel_encoder *encoder);
 496         void (*fdi_link_train)(struct drm_crtc *crtc);
 497         void (*init_clock_gating)(struct drm_device *dev);
 498         int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
 499                           struct drm_framebuffer *fb,
 500                           struct drm_i915_gem_object *obj,
 501                           struct intel_engine_cs *ring,
 502                           uint32_t flags);
 503         void (*update_primary_plane)(struct drm_crtc *crtc,
 504                                      struct drm_framebuffer *fb,
 505                                      int x, int y);
 506         void (*hpd_irq_setup)(struct drm_device *dev);
 507         /* clock updates for mode set */
 508         /* cursor updates */
 509         /* render clock increase/decrease */
 510         /* display clock increase/decrease */
 511         /* pll clock increase/decrease */
 512
 513         int (*setup_backlight)(struct intel_connector *connector);
 514         uint32_t (*get_backlight)(struct intel_connector *connector);
 515         void (*set_backlight)(struct intel_connector *connector,
 516                               uint32_t level);
 517         void (*disable_backlight)(struct intel_connector *connector);
 518         void (*enable_backlight)(struct intel_connector *connector);
 519 };
 520
 521 struct intel_uncore_funcs {
 522         void (*force_wake_get)(struct drm_i915_private *dev_priv,
 523                                                         int fw_engine);
 524         void (*force_wake_put)(struct drm_i915_private *dev_priv,
 525                                                         int fw_engine);
 526
 527         uint8_t  (*mmio_readb)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
 528         uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
 529         uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
 530         uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
 531
 532         void (*mmio_writeb)(struct drm_i915_private *dev_priv, off_t offset,
 533                                 uint8_t val, bool trace);
 534         void (*mmio_writew)(struct drm_i915_private *dev_priv, off_t offset,
 535                                 uint16_t val, bool trace);
 536         void (*mmio_writel)(struct drm_i915_private *dev_priv, off_t offset,
 537                                 uint32_t val, bool trace);
 538         void (*mmio_writeq)(struct drm_i915_private *dev_priv, off_t offset,
 539                                 uint64_t val, bool trace);
 540 };
 541
 542 struct intel_uncore {
 543         spinlock_t lock; /** lock is also taken in irq contexts. */
 544
 545         struct intel_uncore_funcs funcs;
 546
 547         unsigned fifo_count;
 548         unsigned forcewake_count;
 549
 550         unsigned fw_rendercount;
 551         unsigned fw_mediacount;
 552         unsigned fw_blittercount;
 553
 554         struct timer_list force_wake_timer;
 555 };
 556
 557 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
 558         func(is_mobile) sep \
 559         func(is_i85x) sep \
 560         func(is_i915g) sep \
 561         func(is_i945gm) sep \
 562         func(is_g33) sep \
 563         func(need_gfx_hws) sep \
 564         func(is_g4x) sep \
 565         func(is_pineview) sep \
 566         func(is_broadwater) sep \
 567         func(is_crestline) sep \
 568         func(is_ivybridge) sep \
 569         func(is_valleyview) sep \
 570         func(is_haswell) sep \
 571         func(is_skylake) sep \
 572         func(is_preliminary) sep \
 573         func(has_fbc) sep \
 574         func(has_pipe_cxsr) sep \
 575         func(has_hotplug) sep \
 576         func(cursor_needs_physical) sep \
 577         func(has_overlay) sep \
 578         func(overlay_needs_physical) sep \
 579         func(supports_tv) sep \
 580         func(has_llc) sep \
 581         func(has_ddi) sep \
 582         func(has_fpga_dbg)
 583
 584 #define DEFINE_FLAG(name) u8 name:1
 585 #define SEP_SEMICOLON ;
 586
 587 struct intel_device_info {
 588         u32 display_mmio_offset;
 589         u16 device_id;
 590         u8 num_pipes:3;
 591         u8 num_sprites[I915_MAX_PIPES];
 592         u8 gen;
 593         u8 ring_mask; /* Rings supported by the HW */
 594         DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
 595         /* Register offsets for the various display pipes and transcoders */
 596         int pipe_offsets[I915_MAX_TRANSCODERS];
 597         int trans_offsets[I915_MAX_TRANSCODERS];
 598         int palette_offsets[I915_MAX_PIPES];
 599         int cursor_offsets[I915_MAX_PIPES];
 600 };
 601
 602 #undef DEFINE_FLAG
 603 #undef SEP_SEMICOLON
 604
 605 enum i915_cache_level {
 606         I915_CACHE_NONE = 0,
 607         I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
 608         I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
 609                               caches, eg sampler/render caches, and the
 610                               large Last-Level-Cache. LLC is coherent with
 611                               the CPU, but L3 is only visible to the GPU. */
 612         I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
 613 };
 614
 615 struct i915_ctx_hang_stats {
 616         /* This context had batch pending when hang was declared */
 617         unsigned batch_pending;
 618
 619         /* This context had batch active when hang was declared */
 620         unsigned batch_active;
 621
 622         /* Time when this context was last blamed for a GPU reset */
 623         unsigned long guilty_ts;
 624
 625         /* This context is banned to submit more work */
 626         bool banned;
 627 };
 628
 629 /* This must match up with the value previously used for execbuf2.rsvd1. */
 630 #define DEFAULT_CONTEXT_HANDLE 0
 631 /**
 632  * struct intel_context - as the name implies, represents a context.
 633  * @ref: reference count.
 634  * @user_handle: userspace tracking identity for this context.
 635  * @remap_slice: l3 row remapping information.
 636  * @file_priv: filp associated with this context (NULL for global default
 637  *             context).
 638  * @hang_stats: information about the role of this context in possible GPU
 639  *              hangs.
 640  * @vm: virtual memory space used by this context.
 641  * @legacy_hw_ctx: render context backing object and whether it is correctly
 642  *                initialized (legacy ring submission mechanism only).
 643  * @link: link in the global list of contexts.
 644  *
 645  * Contexts are memory images used by the hardware to store copies of their
 646  * internal state.
 647  */
 648 struct intel_context {
 649         struct kref ref;
 650         int user_handle;
 651         uint8_t remap_slice;
 652         struct drm_i915_file_private *file_priv;
 653         struct i915_ctx_hang_stats hang_stats;
 654         struct i915_hw_ppgtt *ppgtt;
 655
 656         /* Legacy ring buffer submission */
 657         struct {
 658                 struct drm_i915_gem_object *rcs_state;
 659                 bool initialized;
 660         } legacy_hw_ctx;
 661
 662         /* Execlists */
 663         bool rcs_initialized;
 664         struct {
 665                 struct drm_i915_gem_object *state;
 666                 struct intel_ringbuffer *ringbuf;
 667         } engine[I915_NUM_RINGS];
 668
 669         struct list_head link;
 670 };
 671
 672 struct i915_fbc {
 673         unsigned long size;
 674         unsigned threshold;
 675         unsigned int fb_id;
 676         enum plane plane;
 677         int y;
 678
 679         struct drm_mm_node compressed_fb;
 680         struct drm_mm_node *compressed_llb;
 681
 682         bool false_color;
 683
 684         /* Tracks whether the HW is actually enabled, not whether the feature is
 685          * possible. */
 686         bool enabled;
 687
 688         /* On gen8 some rings cannont perform fbc clean operation so for now
 689          * we are doing this on SW with mmio.
 690          * This variable works in the opposite information direction
 691          * of ring->fbc_dirty telling software on frontbuffer tracking
 692          * to perform the cache clean on sw side.
 693          */
 694         bool need_sw_cache_clean;
 695
 696         struct intel_fbc_work {
 697                 struct delayed_work work;
 698                 struct drm_crtc *crtc;
 699                 struct drm_framebuffer *fb;
 700         } *fbc_work;
 701
 702         enum no_fbc_reason {
 703                 FBC_OK, /* FBC is enabled */
 704                 FBC_UNSUPPORTED, /* FBC is not supported by this chipset */
 705                 FBC_NO_OUTPUT, /* no outputs enabled to compress */
 706                 FBC_STOLEN_TOO_SMALL, /* not enough space for buffers */
 707                 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
 708                 FBC_MODE_TOO_LARGE, /* mode too large for compression */
 709                 FBC_BAD_PLANE, /* fbc not supported on plane */
 710                 FBC_NOT_TILED, /* buffer not tiled */
 711                 FBC_MULTIPLE_PIPES, /* more than one pipe active */
 712                 FBC_MODULE_PARAM,
 713                 FBC_CHIP_DEFAULT, /* disabled by default on this chip */
 714         } no_fbc_reason;
 715 };
 716
 717 struct i915_drrs {
 718         struct intel_connector *connector;
 719 };
 720
 721 struct intel_dp;
 722 struct i915_psr {
 723         struct mutex lock;
 724         bool sink_support;
 725         bool source_ok;
 726         struct intel_dp *enabled;
 727         bool active;
 728         struct delayed_work work;
 729         unsigned busy_frontbuffer_bits;
 730 };
 731
 732 enum intel_pch {
 733         PCH_NONE = 0,   /* No PCH present */
 734         PCH_IBX,        /* Ibexpeak PCH */
 735         PCH_CPT,        /* Cougarpoint PCH */
 736         PCH_LPT,        /* Lynxpoint PCH */
 737         PCH_SPT,        /* Sunrisepoint PCH */
 738         PCH_NOP,
 739 };
 740
 741 enum intel_sbi_destination {
 742         SBI_ICLK,
 743         SBI_MPHY,
 744 };
 745
 746 #define QUIRK_PIPEA_FORCE (1<<0)
 747 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
 748 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
 749 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
 750 #define QUIRK_PIPEB_FORCE (1<<4)
 751
 752 struct intel_fbdev;
 753 struct intel_fbc_work;
 754
 755 struct intel_gmbus {
 756         struct i2c_adapter adapter;
 757         u32 force_bit;
 758         u32 reg0;
 759         u32 gpio_reg;
 760         struct i2c_algo_bit_data bit_algo;
 761         struct drm_i915_private *dev_priv;
 762 };
 763
 764 struct i915_suspend_saved_registers {
 765         u8 saveLBB;
 766         u32 saveDSPACNTR;
 767         u32 saveDSPBCNTR;
 768         u32 saveDSPARB;
 769         u32 savePIPEACONF;
 770         u32 savePIPEBCONF;
 771         u32 savePIPEASRC;
 772         u32 savePIPEBSRC;
 773         u32 saveFPA0;
 774         u32 saveFPA1;
 775         u32 saveDPLL_A;
 776         u32 saveDPLL_A_MD;
 777         u32 saveHTOTAL_A;
 778         u32 saveHBLANK_A;
 779         u32 saveHSYNC_A;
 780         u32 saveVTOTAL_A;
 781         u32 saveVBLANK_A;
 782         u32 saveVSYNC_A;
 783         u32 saveBCLRPAT_A;
 784         u32 saveTRANSACONF;
 785         u32 saveTRANS_HTOTAL_A;
 786         u32 saveTRANS_HBLANK_A;
 787         u32 saveTRANS_HSYNC_A;
 788         u32 saveTRANS_VTOTAL_A;
 789         u32 saveTRANS_VBLANK_A;
 790         u32 saveTRANS_VSYNC_A;
 791         u32 savePIPEASTAT;
 792         u32 saveDSPASTRIDE;
 793         u32 saveDSPASIZE;
 794         u32 saveDSPAPOS;
 795         u32 saveDSPAADDR;
 796         u32 saveDSPASURF;
 797         u32 saveDSPATILEOFF;
 798         u32 savePFIT_PGM_RATIOS;
 799         u32 saveBLC_HIST_CTL;
 800         u32 saveBLC_PWM_CTL;
 801         u32 saveBLC_PWM_CTL2;
 802         u32 saveBLC_HIST_CTL_B;
 803         u32 saveBLC_CPU_PWM_CTL;
 804         u32 saveBLC_CPU_PWM_CTL2;
 805         u32 saveFPB0;
 806         u32 saveFPB1;
 807         u32 saveDPLL_B;
 808         u32 saveDPLL_B_MD;
 809         u32 saveHTOTAL_B;
 810         u32 saveHBLANK_B;
 811         u32 saveHSYNC_B;
 812         u32 saveVTOTAL_B;
 813         u32 saveVBLANK_B;
 814         u32 saveVSYNC_B;
 815         u32 saveBCLRPAT_B;
 816         u32 saveTRANSBCONF;
 817         u32 saveTRANS_HTOTAL_B;
 818         u32 saveTRANS_HBLANK_B;
 819         u32 saveTRANS_HSYNC_B;
 820         u32 saveTRANS_VTOTAL_B;
 821         u32 saveTRANS_VBLANK_B;
 822         u32 saveTRANS_VSYNC_B;
 823         u32 savePIPEBSTAT;
 824         u32 saveDSPBSTRIDE;
 825         u32 saveDSPBSIZE;
 826         u32 saveDSPBPOS;
 827         u32 saveDSPBADDR;
 828         u32 saveDSPBSURF;
 829         u32 saveDSPBTILEOFF;
 830         u32 saveVGA0;
 831         u32 saveVGA1;
 832         u32 saveVGA_PD;
 833         u32 saveVGACNTRL;
 834         u32 saveADPA;
 835         u32 saveLVDS;
 836         u32 savePP_ON_DELAYS;
 837         u32 savePP_OFF_DELAYS;
 838         u32 saveDVOA;
 839         u32 saveDVOB;
 840         u32 saveDVOC;
 841         u32 savePP_ON;
 842         u32 savePP_OFF;
 843         u32 savePP_CONTROL;
 844         u32 savePP_DIVISOR;
 845         u32 savePFIT_CONTROL;
 846         u32 save_palette_a[256];
 847         u32 save_palette_b[256];
 848         u32 saveFBC_CONTROL;
 849         u32 saveIER;
 850         u32 saveIIR;
 851         u32 saveIMR;
 852         u32 saveDEIER;
 853         u32 saveDEIMR;
 854         u32 saveGTIER;
 855         u32 saveGTIMR;
 856         u32 saveFDI_RXA_IMR;
 857         u32 saveFDI_RXB_IMR;
 858         u32 saveCACHE_MODE_0;
 859         u32 saveMI_ARB_STATE;
 860         u32 saveSWF0[16];
 861         u32 saveSWF1[16];
 862         u32 saveSWF2[3];
 863         u8 saveMSR;
 864         u8 saveSR[8];
 865         u8 saveGR[25];
 866         u8 saveAR_INDEX;
 867         u8 saveAR[21];
 868         u8 saveDACMASK;
 869         u8 saveCR[37];
 870         uint64_t saveFENCE[I915_MAX_NUM_FENCES];
 871         u32 saveCURACNTR;
 872         u32 saveCURAPOS;
 873         u32 saveCURABASE;
 874         u32 saveCURBCNTR;
 875         u32 saveCURBPOS;
 876         u32 saveCURBBASE;
 877         u32 saveCURSIZE;
 878         u32 saveDP_B;
 879         u32 saveDP_C;
 880         u32 saveDP_D;
 881         u32 savePIPEA_GMCH_DATA_M;
 882         u32 savePIPEB_GMCH_DATA_M;
 883         u32 savePIPEA_GMCH_DATA_N;
 884         u32 savePIPEB_GMCH_DATA_N;
 885         u32 savePIPEA_DP_LINK_M;
 886         u32 savePIPEB_DP_LINK_M;
 887         u32 savePIPEA_DP_LINK_N;
 888         u32 savePIPEB_DP_LINK_N;
 889         u32 saveFDI_RXA_CTL;
 890         u32 saveFDI_TXA_CTL;
 891         u32 saveFDI_RXB_CTL;
 892         u32 saveFDI_TXB_CTL;
 893         u32 savePFA_CTL_1;
 894         u32 savePFB_CTL_1;
 895         u32 savePFA_WIN_SZ;
 896         u32 savePFB_WIN_SZ;
 897         u32 savePFA_WIN_POS;
 898         u32 savePFB_WIN_POS;
 899         u32 savePCH_DREF_CONTROL;
 900         u32 saveDISP_ARB_CTL;
 901         u32 savePIPEA_DATA_M1;
 902         u32 savePIPEA_DATA_N1;
 903         u32 savePIPEA_LINK_M1;
 904         u32 savePIPEA_LINK_N1;
 905         u32 savePIPEB_DATA_M1;
 906         u32 savePIPEB_DATA_N1;
 907         u32 savePIPEB_LINK_M1;
 908         u32 savePIPEB_LINK_N1;
 909         u32 saveMCHBAR_RENDER_STANDBY;
 910         u32 savePCH_PORT_HOTPLUG;
 911 };
 912
 913 struct vlv_s0ix_state {
 914         /* GAM */
 915         u32 wr_watermark;
 916         u32 gfx_prio_ctrl;
 917         u32 arb_mode;
 918         u32 gfx_pend_tlb0;
 919         u32 gfx_pend_tlb1;
 920         u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
 921         u32 media_max_req_count;
 922         u32 gfx_max_req_count;
 923         u32 render_hwsp;
 924         u32 ecochk;
 925         u32 bsd_hwsp;
 926         u32 blt_hwsp;
 927         u32 tlb_rd_addr;
 928
 929         /* MBC */
 930         u32 g3dctl;
 931         u32 gsckgctl;
 932         u32 mbctl;
 933
 934         /* GCP */
 935         u32 ucgctl1;
 936         u32 ucgctl3;
 937         u32 rcgctl1;
 938         u32 rcgctl2;
 939         u32 rstctl;
 940         u32 misccpctl;
 941
 942         /* GPM */
 943         u32 gfxpause;
 944         u32 rpdeuhwtc;
 945         u32 rpdeuc;
 946         u32 ecobus;
 947         u32 pwrdwnupctl;
 948         u32 rp_down_timeout;
 949         u32 rp_deucsw;
 950         u32 rcubmabdtmr;
 951         u32 rcedata;
 952         u32 spare2gh;
 953
 954         /* Display 1 CZ domain */
 955         u32 gt_imr;
 956         u32 gt_ier;
 957         u32 pm_imr;
 958         u32 pm_ier;
 959         u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
 960
 961         /* GT SA CZ domain */
 962         u32 tilectl;
 963         u32 gt_fifoctl;
 964         u32 gtlc_wake_ctrl;
 965         u32 gtlc_survive;
 966         u32 pmwgicz;
 967
 968         /* Display 2 CZ domain */
 969         u32 gu_ctl0;
 970         u32 gu_ctl1;
 971         u32 clock_gate_dis2;
 972 };
 973
 974 struct intel_rps_ei {
 975         u32 cz_clock;
 976         u32 render_c0;
 977         u32 media_c0;
 978 };
 979
 980 struct intel_gen6_power_mgmt {
 981         /* work and pm_iir are protected by dev_priv->irq_lock */
 982         struct work_struct work;
 983         u32 pm_iir;
 984
 985         /* Frequencies are stored in potentially platform dependent multiples.
 986          * In other words, *_freq needs to be multiplied by X to be interesting.
 987          * Soft limits are those which are used for the dynamic reclocking done
 988          * by the driver (raise frequencies under heavy loads, and lower for
 989          * lighter loads). Hard limits are those imposed by the hardware.
 990          *
 991          * A distinction is made for overclocking, which is never enabled by
 992          * default, and is considered to be above the hard limit if it's
 993          * possible at all.
 994          */
 995         u8 cur_freq;            /* Current frequency (cached, may not == HW) */
 996         u8 min_freq_softlimit;  /* Minimum frequency permitted by the driver */
 997         u8 max_freq_softlimit;  /* Max frequency permitted by the driver */
 998         u8 max_freq;            /* Maximum frequency, RP0 if not overclocking */
 999         u8 min_freq;            /* AKA RPn. Minimum frequency */
1000         u8 efficient_freq;      /* AKA RPe. Pre-determined balanced frequency */
1001         u8 rp1_freq;            /* "less than" RP0 power/freqency */
1002         u8 rp0_freq;            /* Non-overclocked max frequency. */
1003         u32 cz_freq;
1004
1005         u32 ei_interrupt_count;
1006
1007         int last_adj;
1008         enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
1009
1010         bool enabled;
1011         struct delayed_work delayed_resume_work;
1012
1013         /* manual wa residency calculations */
1014         struct intel_rps_ei up_ei, down_ei;
1015
1016         /*
1017          * Protects RPS/RC6 register access and PCU communication.
1018          * Must be taken after struct_mutex if nested.
1019          */
1020         struct mutex hw_lock;
1021 };
1022
1023 /* defined intel_pm.c */
1024 extern spinlock_t mchdev_lock;
1025
1026 struct intel_ilk_power_mgmt {
1027         u8 cur_delay;
1028         u8 min_delay;
1029         u8 max_delay;
1030         u8 fmax;
1031         u8 fstart;
1032
1033         u64 last_count1;
1034         unsigned long last_time1;
1035         unsigned long chipset_power;
1036         u64 last_count2;
1037         u64 last_time2;
1038         unsigned long gfx_power;
1039         u8 corr;
1040
1041         int c_m;
1042         int r_t;
1043
1044         struct drm_i915_gem_object *pwrctx;
1045         struct drm_i915_gem_object *renderctx;
1046 };
1047
1048 struct drm_i915_private;
1049 struct i915_power_well;
1050
1051 struct i915_power_well_ops {
1052         /*
1053          * Synchronize the well's hw state to match the current sw state, for
1054          * example enable/disable it based on the current refcount. Called
1055          * during driver init and resume time, possibly after first calling
1056          * the enable/disable handlers.
1057          */
1058         void (*sync_hw)(struct drm_i915_private *dev_priv,
1059                         struct i915_power_well *power_well);
1060         /*
1061          * Enable the well and resources that depend on it (for example
1062          * interrupts located on the well). Called after the 0->1 refcount
1063          * transition.
1064          */
1065         void (*enable)(struct drm_i915_private *dev_priv,
1066                        struct i915_power_well *power_well);
1067         /*
1068          * Disable the well and resources that depend on it. Called after
1069          * the 1->0 refcount transition.
1070          */
1071         void (*disable)(struct drm_i915_private *dev_priv,
1072                         struct i915_power_well *power_well);
1073         /* Returns the hw enabled state. */
1074         bool (*is_enabled)(struct drm_i915_private *dev_priv,
1075                            struct i915_power_well *power_well);
1076 };
1077
1078 /* Power well structure for haswell */
1079 struct i915_power_well {
1080         const char *name;
1081         bool always_on;
1082         /* power well enable/disable usage count */
1083         int count;
1084         /* cached hw enabled state */
1085         bool hw_enabled;
1086         unsigned long domains;
1087         unsigned long data;
1088         const struct i915_power_well_ops *ops;
1089 };
1090
1091 struct i915_power_domains {
1092         /*
1093          * Power wells needed for initialization at driver init and suspend
1094          * time are on. They are kept on until after the first modeset.
1095          */
1096         bool init_power_on;
1097         bool initializing;
1098         int power_well_count;
1099
1100         struct mutex lock;
1101         int domain_use_count[POWER_DOMAIN_NUM];
1102         struct i915_power_well *power_wells;
1103 };
1104
1105 struct i915_dri1_state {
1106         unsigned allow_batchbuffer : 1;
1107         u32 __iomem *gfx_hws_cpu_addr;
1108
1109         unsigned int cpp;
1110         int back_offset;
1111         int front_offset;
1112         int current_page;
1113         int page_flipping;
1114
1115         uint32_t counter;
1116 };
1117
1118 struct i915_ums_state {
1119         /**
1120          * Flag if the X Server, and thus DRM, is not currently in
1121          * control of the device.
1122          *
1123          * This is set between LeaveVT and EnterVT.  It needs to be
1124          * replaced with a semaphore.  It also needs to be
1125          * transitioned away from for kernel modesetting.
1126          */
1127         int mm_suspended;
1128 };
1129
1130 #define MAX_L3_SLICES 2
1131 struct intel_l3_parity {
1132         u32 *remap_info[MAX_L3_SLICES];
1133         struct work_struct error_work;
1134         int which_slice;
1135 };
1136
1137 struct i915_gem_mm {
1138         /** Memory allocator for GTT stolen memory */
1139         struct drm_mm stolen;
1140         /** List of all objects in gtt_space. Used to restore gtt
1141          * mappings on resume */
1142         struct list_head bound_list;
1143         /**
1144          * List of objects which are not bound to the GTT (thus
1145          * are idle and not used by the GPU) but still have
1146          * (presumably uncached) pages still attached.
1147          */
1148         struct list_head unbound_list;
1149
1150         /** Usable portion of the GTT for GEM */
1151         unsigned long stolen_base; /* limited to low memory (32-bit) */
1152
1153         /** PPGTT used for aliasing the PPGTT with the GTT */
1154         struct i915_hw_ppgtt *aliasing_ppgtt;
1155
1156         struct notifier_block oom_notifier;
1157         struct shrinker shrinker;
1158         bool shrinker_no_lock_stealing;
1159
1160         /** LRU list of objects with fence regs on them. */
1161         struct list_head fence_list;
1162
1163         /**
1164          * We leave the user IRQ off as much as possible,
1165          * but this means that requests will finish and never
1166          * be retired once the system goes idle. Set a timer to
1167          * fire periodically while the ring is running. When it
1168          * fires, go retire requests.
1169          */
1170         struct delayed_work retire_work;
1171
1172         /**
1173          * When we detect an idle GPU, we want to turn on
1174          * powersaving features. So once we see that there
1175          * are no more requests outstanding and no more
1176          * arrive within a small period of time, we fire
1177          * off the idle_work.
1178          */
1179         struct delayed_work idle_work;
1180
1181         /**
1182          * Are we in a non-interruptible section of code like
1183          * modesetting?
1184          */
1185         bool interruptible;
1186
1187         /**
1188          * Is the GPU currently considered idle, or busy executing userspace
1189          * requests?  Whilst idle, we attempt to power down the hardware and
1190          * display clocks. In order to reduce the effect on performance, there
1191          * is a slight delay before we do so.
1192          */
1193         bool busy;
1194
1195         /* the indicator for dispatch video commands on two BSD rings */
1196         int bsd_ring_dispatch_index;
1197
1198         /** Bit 6 swizzling required for X tiling */
1199         uint32_t bit_6_swizzle_x;
1200         /** Bit 6 swizzling required for Y tiling */
1201         uint32_t bit_6_swizzle_y;
1202
1203         /* accounting, useful for userland debugging */
1204         spinlock_t object_stat_lock;
1205         size_t object_memory;
1206         u32 object_count;
1207 };
1208
1209 struct drm_i915_error_state_buf {
1210         struct drm_i915_private *i915;
1211         unsigned bytes;
1212         unsigned size;
1213         int err;
1214         u8 *buf;
1215         loff_t start;
1216         loff_t pos;
1217 };
1218
1219 struct i915_error_state_file_priv {
1220         struct drm_device *dev;
1221         struct drm_i915_error_state *error;
1222 };
1223
1224 struct i915_gpu_error {
1225         /* For hangcheck timer */
1226 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1227 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1228         /* Hang gpu twice in this window and your context gets banned */
1229 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1230
1231         struct timer_list hangcheck_timer;
1232
1233         /* For reset and error_state handling. */
1234         spinlock_t lock;
1235         /* Protected by the above dev->gpu_error.lock. */
1236         struct drm_i915_error_state *first_error;
1237         struct work_struct work;
1238
1239
1240         unsigned long missed_irq_rings;
1241
1242         /**
1243          * State variable controlling the reset flow and count
1244          *
1245          * This is a counter which gets incremented when reset is triggered,
1246          * and again when reset has been handled. So odd values (lowest bit set)
1247          * means that reset is in progress and even values that
1248          * (reset_counter >> 1):th reset was successfully completed.
1249          *
1250          * If reset is not completed succesfully, the I915_WEDGE bit is
1251          * set meaning that hardware is terminally sour and there is no
1252          * recovery. All waiters on the reset_queue will be woken when
1253          * that happens.
1254          *
1255          * This counter is used by the wait_seqno code to notice that reset
1256          * event happened and it needs to restart the entire ioctl (since most
1257          * likely the seqno it waited for won't ever signal anytime soon).
1258          *
1259          * This is important for lock-free wait paths, where no contended lock
1260          * naturally enforces the correct ordering between the bail-out of the
1261          * waiter and the gpu reset work code.
1262          */
1263         atomic_t reset_counter;
1264
1265 #define I915_RESET_IN_PROGRESS_FLAG     1
1266 #define I915_WEDGED                     (1 << 31)
1267
1268         /**
1269          * Waitqueue to signal when the reset has completed. Used by clients
1270          * that wait for dev_priv->mm.wedged to settle.
1271          */
1272         wait_queue_head_t reset_queue;
1273
1274         /* Userspace knobs for gpu hang simulation;
1275          * combines both a ring mask, and extra flags
1276          */
1277         u32 stop_rings;
1278 #define I915_STOP_RING_ALLOW_BAN       (1 << 31)
1279 #define I915_STOP_RING_ALLOW_WARN      (1 << 30)
1280
1281         /* For missed irq/seqno simulation. */
1282         unsigned int test_irq_rings;
1283
1284         /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset   */
1285         bool reload_in_reset;
1286 };
1287
1288 enum modeset_restore {
1289         MODESET_ON_LID_OPEN,
1290         MODESET_DONE,
1291         MODESET_SUSPENDED,
1292 };
1293
1294 struct ddi_vbt_port_info {
1295         /*
1296          * This is an index in the HDMI/DVI DDI buffer translation table.
1297          * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1298          * populate this field.
1299          */
1300 #define HDMI_LEVEL_SHIFT_UNKNOWN        0xff
1301         uint8_t hdmi_level_shift;
1302
1303         uint8_t supports_dvi:1;
1304         uint8_t supports_hdmi:1;
1305         uint8_t supports_dp:1;
1306 };
1307
1308 enum drrs_support_type {
1309         DRRS_NOT_SUPPORTED = 0,
1310         STATIC_DRRS_SUPPORT = 1,
1311         SEAMLESS_DRRS_SUPPORT = 2
1312 };
1313
1314 struct intel_vbt_data {
1315         struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1316         struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1317
1318         /* Feature bits */
1319         unsigned int int_tv_support:1;
1320         unsigned int lvds_dither:1;
1321         unsigned int lvds_vbt:1;
1322         unsigned int int_crt_support:1;
1323         unsigned int lvds_use_ssc:1;
1324         unsigned int display_clock_mode:1;
1325         unsigned int fdi_rx_polarity_inverted:1;
1326         unsigned int has_mipi:1;
1327         int lvds_ssc_freq;
1328         unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1329
1330         enum drrs_support_type drrs_type;
1331
1332         /* eDP */
1333         int edp_rate;
1334         int edp_lanes;
1335         int edp_preemphasis;
1336         int edp_vswing;
1337         bool edp_initialized;
1338         bool edp_support;
1339         int edp_bpp;
1340         struct edp_power_seq edp_pps;
1341
1342         struct {
1343                 u16 pwm_freq_hz;
1344                 bool present;
1345                 bool active_low_pwm;
1346                 u8 min_brightness;      /* min_brightness/255 of max */
1347         } backlight;
1348
1349         /* MIPI DSI */
1350         struct {
1351                 u16 port;
1352                 u16 panel_id;
1353                 struct mipi_config *config;
1354                 struct mipi_pps_data *pps;
1355                 u8 seq_version;
1356                 u32 size;
1357                 u8 *data;
1358                 u8 *sequence[MIPI_SEQ_MAX];
1359         } dsi;
1360
1361         int crt_ddc_pin;
1362
1363         int child_dev_num;
1364         union child_device_config *child_dev;
1365
1366         struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1367 };
1368
1369 enum intel_ddb_partitioning {
1370         INTEL_DDB_PART_1_2,
1371         INTEL_DDB_PART_5_6, /* IVB+ */
1372 };
1373
1374 struct intel_wm_level {
1375         bool enable;
1376         uint32_t pri_val;
1377         uint32_t spr_val;
1378         uint32_t cur_val;
1379         uint32_t fbc_val;
1380 };
1381
1382 struct ilk_wm_values {
1383         uint32_t wm_pipe[3];
1384         uint32_t wm_lp[3];
1385         uint32_t wm_lp_spr[3];
1386         uint32_t wm_linetime[3];
1387         bool enable_fbc_wm;
1388         enum intel_ddb_partitioning partitioning;
1389 };
1390
1391 struct skl_ddb_entry {
1392         uint16_t start, end;    /* in number of blocks, 'end' is exclusive */
1393 };
1394
1395 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
1396 {
1397         return entry->end - entry->start;
1398 }
1399
1400 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
1401                                        const struct skl_ddb_entry *e2)
1402 {
1403         if (e1->start == e2->start && e1->end == e2->end)
1404                 return true;
1405
1406         return false;
1407 }
1408
1409 struct skl_ddb_allocation {
1410         struct skl_ddb_entry pipe[I915_MAX_PIPES];
1411         struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES];
1412         struct skl_ddb_entry cursor[I915_MAX_PIPES];
1413 };
1414
1415 struct skl_wm_values {
1416         bool dirty[I915_MAX_PIPES];
1417         struct skl_ddb_allocation ddb;
1418         uint32_t wm_linetime[I915_MAX_PIPES];
1419         uint32_t plane[I915_MAX_PIPES][I915_MAX_PLANES][8];
1420         uint32_t cursor[I915_MAX_PIPES][8];
1421         uint32_t plane_trans[I915_MAX_PIPES][I915_MAX_PLANES];
1422         uint32_t cursor_trans[I915_MAX_PIPES];
1423 };
1424
1425 struct skl_wm_level {
1426         bool plane_en[I915_MAX_PLANES];
1427         bool cursor_en;
1428         uint16_t plane_res_b[I915_MAX_PLANES];
1429         uint8_t plane_res_l[I915_MAX_PLANES];
1430         uint16_t cursor_res_b;
1431         uint8_t cursor_res_l;
1432 };
1433
1434 /*
1435  * This struct helps tracking the state needed for runtime PM, which puts the
1436  * device in PCI D3 state. Notice that when this happens, nothing on the
1437  * graphics device works, even register access, so we don't get interrupts nor
1438  * anything else.
1439  *
1440  * Every piece of our code that needs to actually touch the hardware needs to
1441  * either call intel_runtime_pm_get or call intel_display_power_get with the
1442  * appropriate power domain.
1443  *
1444  * Our driver uses the autosuspend delay feature, which means we'll only really
1445  * suspend if we stay with zero refcount for a certain amount of time. The
1446  * default value is currently very conservative (see intel_runtime_pm_enable), but
1447  * it can be changed with the standard runtime PM files from sysfs.
1448  *
1449  * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1450  * goes back to false exactly before we reenable the IRQs. We use this variable
1451  * to check if someone is trying to enable/disable IRQs while they're supposed
1452  * to be disabled. This shouldn't happen and we'll print some error messages in
1453  * case it happens.
1454  *
1455  * For more, read the Documentation/power/runtime_pm.txt.
1456  */
1457 struct i915_runtime_pm {
1458         bool suspended;
1459         bool irqs_enabled;
1460 };
1461
1462 enum intel_pipe_crc_source {
1463         INTEL_PIPE_CRC_SOURCE_NONE,
1464         INTEL_PIPE_CRC_SOURCE_PLANE1,
1465         INTEL_PIPE_CRC_SOURCE_PLANE2,
1466         INTEL_PIPE_CRC_SOURCE_PF,
1467         INTEL_PIPE_CRC_SOURCE_PIPE,
1468         /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1469         INTEL_PIPE_CRC_SOURCE_TV,
1470         INTEL_PIPE_CRC_SOURCE_DP_B,
1471         INTEL_PIPE_CRC_SOURCE_DP_C,
1472         INTEL_PIPE_CRC_SOURCE_DP_D,
1473         INTEL_PIPE_CRC_SOURCE_AUTO,
1474         INTEL_PIPE_CRC_SOURCE_MAX,
1475 };
1476
1477 struct intel_pipe_crc_entry {
1478         uint32_t frame;
1479         uint32_t crc[5];
1480 };
1481
1482 #define INTEL_PIPE_CRC_ENTRIES_NR       128
1483 struct intel_pipe_crc {
1484         spinlock_t lock;
1485         bool opened;            /* exclusive access to the result file */
1486         struct intel_pipe_crc_entry *entries;
1487         enum intel_pipe_crc_source source;
1488         int head, tail;
1489         wait_queue_head_t wq;
1490 };
1491
1492 struct i915_frontbuffer_tracking {
1493         struct mutex lock;
1494
1495         /*
1496          * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1497          * scheduled flips.
1498          */
1499         unsigned busy_bits;
1500         unsigned flip_bits;
1501 };
1502
1503 struct i915_wa_reg {
1504         u32 addr;
1505         u32 value;
1506         /* bitmask representing WA bits */
1507         u32 mask;
1508 };
1509
1510 #define I915_MAX_WA_REGS 16
1511
1512 struct i915_workarounds {
1513         struct i915_wa_reg reg[I915_MAX_WA_REGS];
1514         u32 count;
1515 };
1516
1517 struct drm_i915_private {
1518         struct drm_device *dev;
1519         struct kmem_cache *slab;
1520
1521         const struct intel_device_info info;
1522
1523         int relative_constants_mode;
1524
1525         void __iomem *regs;
1526
1527         struct intel_uncore uncore;
1528
1529         struct intel_gmbus gmbus[GMBUS_NUM_PORTS];
1530
1531
1532         /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1533          * controller on different i2c buses. */
1534         struct mutex gmbus_mutex;
1535
1536         /**
1537          * Base address of the gmbus and gpio block.
1538          */
1539         uint32_t gpio_mmio_base;
1540
1541         /* MMIO base address for MIPI regs */
1542         uint32_t mipi_mmio_base;
1543
1544         wait_queue_head_t gmbus_wait_queue;
1545
1546         struct pci_dev *bridge_dev;
1547         struct intel_engine_cs ring[I915_NUM_RINGS];
1548         struct drm_i915_gem_object *semaphore_obj;
1549         uint32_t last_seqno, next_seqno;
1550
1551         struct drm_dma_handle *status_page_dmah;
1552         struct resource mch_res;
1553
1554         /* protects the irq masks */
1555         spinlock_t irq_lock;
1556
1557         /* protects the mmio flip data */
1558         spinlock_t mmio_flip_lock;
1559
1560         bool display_irqs_enabled;
1561
1562         /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1563         struct pm_qos_request pm_qos;
1564
1565         /* DPIO indirect register protection */
1566         struct mutex dpio_lock;
1567
1568         /** Cached value of IMR to avoid reads in updating the bitfield */
1569         union {
1570                 u32 irq_mask;
1571                 u32 de_irq_mask[I915_MAX_PIPES];
1572         };
1573         u32 gt_irq_mask;
1574         u32 pm_irq_mask;
1575         u32 pm_rps_events;
1576         u32 pipestat_irq_mask[I915_MAX_PIPES];
1577
1578         struct work_struct hotplug_work;
1579         struct {
1580                 unsigned long hpd_last_jiffies;
1581                 int hpd_cnt;
1582                 enum {
1583                         HPD_ENABLED = 0,
1584                         HPD_DISABLED = 1,
1585                         HPD_MARK_DISABLED = 2
1586                 } hpd_mark;
1587         } hpd_stats[HPD_NUM_PINS];
1588         u32 hpd_event_bits;
1589         struct delayed_work hotplug_reenable_work;
1590
1591         struct i915_fbc fbc;
1592         struct i915_drrs drrs;
1593         struct intel_opregion opregion;
1594         struct intel_vbt_data vbt;
1595
1596         bool preserve_bios_swizzle;
1597
1598         /* overlay */
1599         struct intel_overlay *overlay;
1600
1601         /* backlight registers and fields in struct intel_panel */
1602         struct mutex backlight_lock;
1603
1604         /* LVDS info */
1605         bool no_aux_handshake;
1606
1607         /* protects panel power sequencer state */
1608         struct mutex pps_mutex;
1609
1610         struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
1611         int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
1612         int num_fence_regs; /* 8 on pre-965, 16 otherwise */
1613
1614         unsigned int fsb_freq, mem_freq, is_ddr3;
1615         unsigned int vlv_cdclk_freq;
1616         unsigned int hpll_freq;
1617
1618         /**
1619          * wq - Driver workqueue for GEM.
1620          *
1621          * NOTE: Work items scheduled here are not allowed to grab any modeset
1622          * locks, for otherwise the flushing done in the pageflip code will
1623          * result in deadlocks.
1624          */
1625         struct workqueue_struct *wq;
1626
1627         /* Display functions */
1628         struct drm_i915_display_funcs display;
1629
1630         /* PCH chipset type */
1631         enum intel_pch pch_type;
1632         unsigned short pch_id;
1633
1634         unsigned long quirks;
1635
1636         enum modeset_restore modeset_restore;
1637         struct mutex modeset_restore_lock;
1638
1639         struct list_head vm_list; /* Global list of all address spaces */
1640         struct i915_gtt gtt; /* VM representing the global address space */
1641
1642         struct i915_gem_mm mm;
1643         DECLARE_HASHTABLE(mm_structs, 7);
1644         struct mutex mm_lock;
1645
1646         /* Kernel Modesetting */
1647
1648         struct sdvo_device_mapping sdvo_mappings[2];
1649
1650         struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
1651         struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1652         wait_queue_head_t pending_flip_queue;
1653
1654 #ifdef CONFIG_DEBUG_FS
1655         struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1656 #endif
1657
1658         int num_shared_dpll;
1659         struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1660         int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1661
1662         struct i915_workarounds workarounds;
1663
1664         /* Reclocking support */
1665         bool render_reclock_avail;
1666         bool lvds_downclock_avail;
1667         /* indicates the reduced downclock for LVDS*/
1668         int lvds_downclock;
1669
1670         struct i915_frontbuffer_tracking fb_tracking;
1671
1672         u16 orig_clock;
1673
1674         bool mchbar_need_disable;
1675
1676         struct intel_l3_parity l3_parity;
1677
1678         /* Cannot be determined by PCIID. You must always read a register. */
1679         size_t ellc_size;
1680
1681         /* gen6+ rps state */
1682         struct intel_gen6_power_mgmt rps;
1683
1684         /* ilk-only ips/rps state. Everything in here is protected by the global
1685          * mchdev_lock in intel_pm.c */
1686         struct intel_ilk_power_mgmt ips;
1687
1688         struct i915_power_domains power_domains;
1689
1690         struct i915_psr psr;
1691
1692         struct i915_gpu_error gpu_error;
1693
1694         struct drm_i915_gem_object *vlv_pctx;
1695
1696 #ifdef CONFIG_DRM_I915_FBDEV
1697         /* list of fbdev register on this device */
1698         struct intel_fbdev *fbdev;
1699         struct work_struct fbdev_suspend_work;
1700 #endif
1701
1702         struct drm_property *broadcast_rgb_property;
1703         struct drm_property *force_audio_property;
1704
1705         uint32_t hw_context_size;
1706         struct list_head context_list;
1707
1708         u32 fdi_rx_config;
1709
1710         u32 suspend_count;
1711         struct i915_suspend_saved_registers regfile;
1712         struct vlv_s0ix_state vlv_s0ix_state;
1713
1714         struct {
1715                 /*
1716                  * Raw watermark latency values:
1717                  * in 0.1us units for WM0,
1718                  * in 0.5us units for WM1+.
1719                  */
1720                 /* primary */
1721                 uint16_t pri_latency[5];
1722                 /* sprite */
1723                 uint16_t spr_latency[5];
1724                 /* cursor */
1725                 uint16_t cur_latency[5];
1726                 /*
1727                  * Raw watermark memory latency values
1728                  * for SKL for all 8 levels
1729                  * in 1us units.
1730                  */
1731                 uint16_t skl_latency[8];
1732
1733                 /*
1734                  * The skl_wm_values structure is a bit too big for stack
1735                  * allocation, so we keep the staging struct where we store
1736                  * intermediate results here instead.
1737                  */
1738                 struct skl_wm_values skl_results;
1739
1740                 /* current hardware state */
1741                 union {
1742                         struct ilk_wm_values hw;
1743                         struct skl_wm_values skl_hw;
1744                 };
1745         } wm;
1746
1747         struct i915_runtime_pm pm;
1748
1749         struct intel_digital_port *hpd_irq_port[I915_MAX_PORTS];
1750         u32 long_hpd_port_mask;
1751         u32 short_hpd_port_mask;
1752         struct work_struct dig_port_work;
1753
1754         /*
1755          * if we get a HPD irq from DP and a HPD irq from non-DP
1756          * the non-DP HPD could block the workqueue on a mode config
1757          * mutex getting, that userspace may have taken. However
1758          * userspace is waiting on the DP workqueue to run which is
1759          * blocked behind the non-DP one.
1760          */
1761         struct workqueue_struct *dp_wq;
1762
1763         uint32_t bios_vgacntr;
1764
1765         /* Old dri1 support infrastructure, beware the dragons ya fools entering
1766          * here! */
1767         struct i915_dri1_state dri1;
1768         /* Old ums support infrastructure, same warning applies. */
1769         struct i915_ums_state ums;
1770
1771         /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
1772         struct {
1773                 int (*do_execbuf)(struct drm_device *dev, struct drm_file *file,
1774                                   struct intel_engine_cs *ring,
1775                                   struct intel_context *ctx,
1776                                   struct drm_i915_gem_execbuffer2 *args,
1777                                   struct list_head *vmas,
1778                                   struct drm_i915_gem_object *batch_obj,
1779                                   u64 exec_start, u32 flags);
1780                 int (*init_rings)(struct drm_device *dev);
1781                 void (*cleanup_ring)(struct intel_engine_cs *ring);
1782                 void (*stop_ring)(struct intel_engine_cs *ring);
1783         } gt;
1784
1785         /*
1786          * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
1787          * will be rejected. Instead look for a better place.
1788          */
1789 };
1790
1791 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
1792 {
1793         return dev->dev_private;
1794 }
1795
1796 /* Iterate over initialised rings */
1797 #define for_each_ring(ring__, dev_priv__, i__) \
1798         for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
1799                 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
1800
1801 enum hdmi_force_audio {
1802         HDMI_AUDIO_OFF_DVI = -2,        /* no aux data for HDMI-DVI converter */
1803         HDMI_AUDIO_OFF,                 /* force turn off HDMI audio */
1804         HDMI_AUDIO_AUTO,                /* trust EDID */
1805         HDMI_AUDIO_ON,                  /* force turn on HDMI audio */
1806 };
1807
1808 #define I915_GTT_OFFSET_NONE ((u32)-1)
1809
1810 struct drm_i915_gem_object_ops {
1811         /* Interface between the GEM object and its backing storage.
1812          * get_pages() is called once prior to the use of the associated set
1813          * of pages before to binding them into the GTT, and put_pages() is
1814          * called after we no longer need them. As we expect there to be
1815          * associated cost with migrating pages between the backing storage
1816          * and making them available for the GPU (e.g. clflush), we may hold
1817          * onto the pages after they are no longer referenced by the GPU
1818          * in case they may be used again shortly (for example migrating the
1819          * pages to a different memory domain within the GTT). put_pages()
1820          * will therefore most likely be called when the object itself is
1821          * being released or under memory pressure (where we attempt to
1822          * reap pages for the shrinker).
1823          */
1824         int (*get_pages)(struct drm_i915_gem_object *);
1825         void (*put_pages)(struct drm_i915_gem_object *);
1826         int (*dmabuf_export)(struct drm_i915_gem_object *);
1827         void (*release)(struct drm_i915_gem_object *);
1828 };
1829
1830 /*
1831  * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
1832  * considered to be the frontbuffer for the given plane interface-vise. This
1833  * doesn't mean that the hw necessarily already scans it out, but that any
1834  * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
1835  *
1836  * We have one bit per pipe and per scanout plane type.
1837  */
1838 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 4
1839 #define INTEL_FRONTBUFFER_BITS \
1840         (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES)
1841 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
1842         (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
1843 #define INTEL_FRONTBUFFER_CURSOR(pipe) \
1844         (1 << (1 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1845 #define INTEL_FRONTBUFFER_SPRITE(pipe) \
1846         (1 << (2 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1847 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
1848         (1 << (3 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1849 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
1850         (0xf << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
1851
1852 struct drm_i915_gem_object {
1853         struct drm_gem_object base;
1854
1855         const struct drm_i915_gem_object_ops *ops;
1856
1857         /** List of VMAs backed by this object */
1858         struct list_head vma_list;
1859
1860         /** Stolen memory for this object, instead of being backed by shmem. */
1861         struct drm_mm_node *stolen;
1862         struct list_head global_list;
1863
1864         struct list_head ring_list;
1865         /** Used in execbuf to temporarily hold a ref */
1866         struct list_head obj_exec_link;
1867
1868         /**
1869          * This is set if the object is on the active lists (has pending
1870          * rendering and so a non-zero seqno), and is not set if it i s on
1871          * inactive (ready to be unbound) list.
1872          */
1873         unsigned int active:1;
1874
1875         /**
1876          * This is set if the object has been written to since last bound
1877          * to the GTT
1878          */
1879         unsigned int dirty:1;
1880
1881         /**
1882          * Fence register bits (if any) for this object.  Will be set
1883          * as needed when mapped into the GTT.
1884          * Protected by dev->struct_mutex.
1885          */
1886         signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
1887
1888         /**
1889          * Advice: are the backing pages purgeable?
1890          */
1891         unsigned int madv:2;
1892
1893         /**
1894          * Current tiling mode for the object.
1895          */
1896         unsigned int tiling_mode:2;
1897         /**
1898          * Whether the tiling parameters for the currently associated fence
1899          * register have changed. Note that for the purposes of tracking
1900          * tiling changes we also treat the unfenced register, the register
1901          * slot that the object occupies whilst it executes a fenced
1902          * command (such as BLT on gen2/3), as a "fence".
1903          */
1904         unsigned int fence_dirty:1;
1905
1906         /**
1907          * Is the object at the current location in the gtt mappable and
1908          * fenceable? Used to avoid costly recalculations.
1909          */
1910         unsigned int map_and_fenceable:1;
1911
1912         /**
1913          * Whether the current gtt mapping needs to be mappable (and isn't just
1914          * mappable by accident). Track pin and fault separate for a more
1915          * accurate mappable working set.
1916          */
1917         unsigned int fault_mappable:1;
1918         unsigned int pin_mappable:1;
1919         unsigned int pin_display:1;
1920
1921         /*
1922          * Is the object to be mapped as read-only to the GPU
1923          * Only honoured if hardware has relevant pte bit
1924          */
1925         unsigned long gt_ro:1;
1926         unsigned int cache_level:3;
1927
1928         unsigned int has_dma_mapping:1;
1929
1930         unsigned int frontbuffer_bits:INTEL_FRONTBUFFER_BITS;
1931
1932         struct sg_table *pages;
1933         int pages_pin_count;
1934
1935         /* prime dma-buf support */
1936         void *dma_buf_vmapping;
1937         int vmapping_count;
1938
1939         struct intel_engine_cs *ring;
1940
1941         /** Breadcrumb of last rendering to the buffer. */
1942         uint32_t last_read_seqno;
1943         uint32_t last_write_seqno;
1944         /** Breadcrumb of last fenced GPU access to the buffer. */
1945         uint32_t last_fenced_seqno;
1946
1947         /** Current tiling stride for the object, if it's tiled. */
1948         uint32_t stride;
1949
1950         /** References from framebuffers, locks out tiling changes. */
1951         unsigned long framebuffer_references;
1952
1953         /** Record of address bit 17 of each page at last unbind. */
1954         unsigned long *bit_17;
1955
1956         /** User space pin count and filp owning the pin */
1957         unsigned long user_pin_count;
1958         struct drm_file *pin_filp;
1959
1960         /** for phy allocated objects */
1961         struct drm_dma_handle *phys_handle;
1962
1963         union {
1964                 struct i915_gem_userptr {
1965                         uintptr_t ptr;
1966                         unsigned read_only :1;
1967                         unsigned workers :4;
1968 #define I915_GEM_USERPTR_MAX_WORKERS 15
1969
1970                         struct i915_mm_struct *mm;
1971                         struct i915_mmu_object *mmu_object;
1972                         struct work_struct *work;
1973                 } userptr;
1974         };
1975 };
1976 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
1977
1978 void i915_gem_track_fb(struct drm_i915_gem_object *old,
1979                        struct drm_i915_gem_object *new,
1980                        unsigned frontbuffer_bits);
1981
1982 /**
1983  * Request queue structure.
1984  *
1985  * The request queue allows us to note sequence numbers that have been emitted
1986  * and may be associated with active buffers to be retired.
1987  *
1988  * By keeping this list, we can avoid having to do questionable
1989  * sequence-number comparisons on buffer last_rendering_seqnos, and associate
1990  * an emission time with seqnos for tracking how far ahead of the GPU we are.
1991  */
1992 struct drm_i915_gem_request {
1993         /** On Which ring this request was generated */
1994         struct intel_engine_cs *ring;
1995
1996         /** GEM sequence number associated with this request. */
1997         uint32_t seqno;
1998
1999         /** Position in the ringbuffer of the start of the request */
2000         u32 head;
2001
2002         /** Position in the ringbuffer of the end of the request */
2003         u32 tail;
2004
2005         /** Context related to this request */
2006         struct intel_context *ctx;
2007
2008         /** Batch buffer related to this request if any */
2009         struct drm_i915_gem_object *batch_obj;
2010
2011         /** Time at which this request was emitted, in jiffies. */
2012         unsigned long emitted_jiffies;
2013
2014         /** global list entry for this request */
2015         struct list_head list;
2016
2017         struct drm_i915_file_private *file_priv;
2018         /** file_priv list entry for this request */
2019         struct list_head client_list;
2020 };
2021
2022 struct drm_i915_file_private {
2023         struct drm_i915_private *dev_priv;
2024         struct drm_file *file;
2025
2026         struct {
2027                 spinlock_t lock;
2028                 struct list_head request_list;
2029                 struct delayed_work idle_work;
2030         } mm;
2031         struct idr context_idr;
2032
2033         atomic_t rps_wait_boost;
2034         struct  intel_engine_cs *bsd_ring;
2035 };
2036
2037 /*
2038  * A command that requires special handling by the command parser.
2039  */
2040 struct drm_i915_cmd_descriptor {
2041         /*
2042          * Flags describing how the command parser processes the command.
2043          *
2044          * CMD_DESC_FIXED: The command has a fixed length if this is set,
2045          *                 a length mask if not set
2046          * CMD_DESC_SKIP: The command is allowed but does not follow the
2047          *                standard length encoding for the opcode range in
2048          *                which it falls
2049          * CMD_DESC_REJECT: The command is never allowed
2050          * CMD_DESC_REGISTER: The command should be checked against the
2051          *                    register whitelist for the appropriate ring
2052          * CMD_DESC_MASTER: The command is allowed if the submitting process
2053          *                  is the DRM master
2054          */
2055         u32 flags;
2056 #define CMD_DESC_FIXED    (1<<0)
2057 #define CMD_DESC_SKIP     (1<<1)
2058 #define CMD_DESC_REJECT   (1<<2)
2059 #define CMD_DESC_REGISTER (1<<3)
2060 #define CMD_DESC_BITMASK  (1<<4)
2061 #define CMD_DESC_MASTER   (1<<5)
2062
2063         /*
2064          * The command's unique identification bits and the bitmask to get them.
2065          * This isn't strictly the opcode field as defined in the spec and may
2066          * also include type, subtype, and/or subop fields.
2067          */
2068         struct {
2069                 u32 value;
2070                 u32 mask;
2071         } cmd;
2072
2073         /*
2074          * The command's length. The command is either fixed length (i.e. does
2075          * not include a length field) or has a length field mask. The flag
2076          * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
2077          * a length mask. All command entries in a command table must include
2078          * length information.
2079          */
2080         union {
2081                 u32 fixed;
2082                 u32 mask;
2083         } length;
2084
2085         /*
2086          * Describes where to find a register address in the command to check
2087          * against the ring's register whitelist. Only valid if flags has the
2088          * CMD_DESC_REGISTER bit set.
2089          */
2090         struct {
2091                 u32 offset;
2092                 u32 mask;
2093         } reg;
2094
2095 #define MAX_CMD_DESC_BITMASKS 3
2096         /*
2097          * Describes command checks where a particular dword is masked and
2098          * compared against an expected value. If the command does not match
2099          * the expected value, the parser rejects it. Only valid if flags has
2100          * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
2101          * are valid.
2102          *
2103          * If the check specifies a non-zero condition_mask then the parser
2104          * only performs the check when the bits specified by condition_mask
2105          * are non-zero.
2106          */
2107         struct {
2108                 u32 offset;
2109                 u32 mask;
2110                 u32 expected;
2111                 u32 condition_offset;
2112                 u32 condition_mask;
2113         } bits[MAX_CMD_DESC_BITMASKS];
2114 };
2115
2116 /*
2117  * A table of commands requiring special handling by the command parser.
2118  *
2119  * Each ring has an array of tables. Each table consists of an array of command
2120  * descriptors, which must be sorted with command opcodes in ascending order.
2121  */
2122 struct drm_i915_cmd_table {
2123         const struct drm_i915_cmd_descriptor *table;
2124         int count;
2125 };
2126
2127 /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
2128 #define __I915__(p) ({ \
2129         struct drm_i915_private *__p; \
2130         if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
2131                 __p = (struct drm_i915_private *)p; \
2132         else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
2133                 __p = to_i915((struct drm_device *)p); \
2134         else \
2135                 BUILD_BUG(); \
2136         __p; \
2137 })
2138 #define INTEL_INFO(p)   (&__I915__(p)->info)
2139 #define INTEL_DEVID(p)  (INTEL_INFO(p)->device_id)
2140
2141 #define IS_I830(dev)            (INTEL_DEVID(dev) == 0x3577)
2142 #define IS_845G(dev)            (INTEL_DEVID(dev) == 0x2562)
2143 #define IS_I85X(dev)            (INTEL_INFO(dev)->is_i85x)
2144 #define IS_I865G(dev)           (INTEL_DEVID(dev) == 0x2572)
2145 #define IS_I915G(dev)           (INTEL_INFO(dev)->is_i915g)
2146 #define IS_I915GM(dev)          (INTEL_DEVID(dev) == 0x2592)
2147 #define IS_I945G(dev)           (INTEL_DEVID(dev) == 0x2772)
2148 #define IS_I945GM(dev)          (INTEL_INFO(dev)->is_i945gm)
2149 #define IS_BROADWATER(dev)      (INTEL_INFO(dev)->is_broadwater)
2150 #define IS_CRESTLINE(dev)       (INTEL_INFO(dev)->is_crestline)
2151 #define IS_GM45(dev)            (INTEL_DEVID(dev) == 0x2A42)
2152 #define IS_G4X(dev)             (INTEL_INFO(dev)->is_g4x)
2153 #define IS_PINEVIEW_G(dev)      (INTEL_DEVID(dev) == 0xa001)
2154 #define IS_PINEVIEW_M(dev)      (INTEL_DEVID(dev) == 0xa011)
2155 #define IS_PINEVIEW(dev)        (INTEL_INFO(dev)->is_pineview)
2156 #define IS_G33(dev)             (INTEL_INFO(dev)->is_g33)
2157 #define IS_IRONLAKE_M(dev)      (INTEL_DEVID(dev) == 0x0046)
2158 #define IS_IVYBRIDGE(dev)       (INTEL_INFO(dev)->is_ivybridge)
2159 #define IS_IVB_GT1(dev)         (INTEL_DEVID(dev) == 0x0156 || \
2160                                  INTEL_DEVID(dev) == 0x0152 || \
2161                                  INTEL_DEVID(dev) == 0x015a)
2162 #define IS_SNB_GT1(dev)         (INTEL_DEVID(dev) == 0x0102 || \
2163                                  INTEL_DEVID(dev) == 0x0106 || \
2164                                  INTEL_DEVID(dev) == 0x010A)
2165 #define IS_VALLEYVIEW(dev)      (INTEL_INFO(dev)->is_valleyview)
2166 #define IS_CHERRYVIEW(dev)      (INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
2167 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
2168 #define IS_BROADWELL(dev)       (!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
2169 #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake)
2170 #define IS_MOBILE(dev)          (INTEL_INFO(dev)->is_mobile)
2171 #define IS_HSW_EARLY_SDV(dev)   (IS_HASWELL(dev) && \
2172                                  (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
2173 #define IS_BDW_ULT(dev)         (IS_BROADWELL(dev) && \
2174                                  ((INTEL_DEVID(dev) & 0xf) == 0x2  || \
2175                                  (INTEL_DEVID(dev) & 0xf) == 0x6 || \
2176                                  (INTEL_DEVID(dev) & 0xf) == 0xe))
2177 #define IS_BDW_GT3(dev)         (IS_BROADWELL(dev) && \
2178                                  (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2179 #define IS_HSW_ULT(dev)         (IS_HASWELL(dev) && \
2180                                  (INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
2181 #define IS_HSW_GT3(dev)         (IS_HASWELL(dev) && \
2182                                  (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2183 /* ULX machines are also considered ULT. */
2184 #define IS_HSW_ULX(dev)         (INTEL_DEVID(dev) == 0x0A0E || \
2185                                  INTEL_DEVID(dev) == 0x0A1E)
2186 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
2187
2188 /*
2189  * The genX designation typically refers to the render engine, so render
2190  * capability related checks should use IS_GEN, while display and other checks
2191  * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2192  * chips, etc.).
2193  */
2194 #define IS_GEN2(dev)    (INTEL_INFO(dev)->gen == 2)
2195 #define IS_GEN3(dev)    (INTEL_INFO(dev)->gen == 3)
2196 #define IS_GEN4(dev)    (INTEL_INFO(dev)->gen == 4)
2197 #define IS_GEN5(dev)    (INTEL_INFO(dev)->gen == 5)
2198 #define IS_GEN6(dev)    (INTEL_INFO(dev)->gen == 6)
2199 #define IS_GEN7(dev)    (INTEL_INFO(dev)->gen == 7)
2200 #define IS_GEN8(dev)    (INTEL_INFO(dev)->gen == 8)
2201 #define IS_GEN9(dev)    (INTEL_INFO(dev)->gen == 9)
2202
2203 #define RENDER_RING             (1<<RCS)
2204 #define BSD_RING                (1<<VCS)
2205 #define BLT_RING                (1<<BCS)
2206 #define VEBOX_RING              (1<<VECS)
2207 #define BSD2_RING               (1<<VCS2)
2208 #define HAS_BSD(dev)            (INTEL_INFO(dev)->ring_mask & BSD_RING)
2209 #define HAS_BSD2(dev)           (INTEL_INFO(dev)->ring_mask & BSD2_RING)
2210 #define HAS_BLT(dev)            (INTEL_INFO(dev)->ring_mask & BLT_RING)
2211 #define HAS_VEBOX(dev)          (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
2212 #define HAS_LLC(dev)            (INTEL_INFO(dev)->has_llc)
2213 #define HAS_WT(dev)             ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
2214                                  __I915__(dev)->ellc_size)
2215 #define I915_NEED_GFX_HWS(dev)  (INTEL_INFO(dev)->need_gfx_hws)
2216
2217 #define HAS_HW_CONTEXTS(dev)    (INTEL_INFO(dev)->gen >= 6)
2218 #define HAS_LOGICAL_RING_CONTEXTS(dev)  (INTEL_INFO(dev)->gen >= 8)
2219 #define USES_PPGTT(dev)         (i915.enable_ppgtt)
2220 #define USES_FULL_PPGTT(dev)    (i915.enable_ppgtt == 2)
2221
2222 #define HAS_OVERLAY(dev)                (INTEL_INFO(dev)->has_overlay)
2223 #define OVERLAY_NEEDS_PHYSICAL(dev)     (INTEL_INFO(dev)->overlay_needs_physical)
2224
2225 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2226 #define HAS_BROKEN_CS_TLB(dev)          (IS_I830(dev) || IS_845G(dev))
2227 /*
2228  * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2229  * even when in MSI mode. This results in spurious interrupt warnings if the
2230  * legacy irq no. is shared with another device. The kernel then disables that
2231  * interrupt source and so prevents the other device from working properly.
2232  */
2233 #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2234 #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2235
2236 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2237  * rows, which changed the alignment requirements and fence programming.
2238  */
2239 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
2240                                                       IS_I915GM(dev)))
2241 #define SUPPORTS_DIGITAL_OUTPUTS(dev)   (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
2242 #define SUPPORTS_INTEGRATED_HDMI(dev)   (IS_G4X(dev) || IS_GEN5(dev))
2243 #define SUPPORTS_INTEGRATED_DP(dev)     (IS_G4X(dev) || IS_GEN5(dev))
2244 #define SUPPORTS_TV(dev)                (INTEL_INFO(dev)->supports_tv)
2245 #define I915_HAS_HOTPLUG(dev)            (INTEL_INFO(dev)->has_hotplug)
2246
2247 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
2248 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
2249 #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
2250
2251 #define HAS_IPS(dev)            (IS_HSW_ULT(dev) || IS_BROADWELL(dev))
2252
2253 #define HAS_DDI(dev)            (INTEL_INFO(dev)->has_ddi)
2254 #define HAS_FPGA_DBG_UNCLAIMED(dev)     (INTEL_INFO(dev)->has_fpga_dbg)
2255 #define HAS_PSR(dev)            (IS_HASWELL(dev) || IS_BROADWELL(dev))
2256 #define HAS_RUNTIME_PM(dev)     (IS_GEN6(dev) || IS_HASWELL(dev) || \
2257                                  IS_BROADWELL(dev) || IS_VALLEYVIEW(dev))
2258 #define HAS_RC6(dev)            (INTEL_INFO(dev)->gen >= 6)
2259 #define HAS_RC6p(dev)           (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
2260
2261 #define INTEL_PCH_DEVICE_ID_MASK                0xff00
2262 #define INTEL_PCH_IBX_DEVICE_ID_TYPE            0x3b00
2263 #define INTEL_PCH_CPT_DEVICE_ID_TYPE            0x1c00
2264 #define INTEL_PCH_PPT_DEVICE_ID_TYPE            0x1e00
2265 #define INTEL_PCH_LPT_DEVICE_ID_TYPE            0x8c00
2266 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE         0x9c00
2267 #define INTEL_PCH_SPT_DEVICE_ID_TYPE            0xA100
2268 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE         0x9D00
2269
2270 #define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
2271 #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
2272 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
2273 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
2274 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
2275 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
2276 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
2277
2278 #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev))
2279
2280 /* DPF == dynamic parity feature */
2281 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
2282 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
2283
2284 #define GT_FREQUENCY_MULTIPLIER 50
2285
2286 #include "i915_trace.h"
2287
2288 extern const struct drm_ioctl_desc i915_ioctls[];
2289 extern int i915_max_ioctl;
2290
2291 extern int i915_suspend_legacy(struct drm_device *dev, pm_message_t state);
2292 extern int i915_resume_legacy(struct drm_device *dev);
2293 extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
2294 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
2295
2296 /* i915_params.c */
2297 struct i915_params {
2298         int modeset;
2299         int panel_ignore_lid;
2300         unsigned int powersave;
2301         int semaphores;
2302         unsigned int lvds_downclock;
2303         int lvds_channel_mode;
2304         int panel_use_ssc;
2305         int vbt_sdvo_panel_type;
2306         int enable_rc6;
2307         int enable_fbc;
2308         int enable_ppgtt;
2309         int enable_execlists;
2310         int enable_psr;
2311         unsigned int preliminary_hw_support;
2312         int disable_power_well;
2313         int enable_ips;
2314         int invert_brightness;
2315         int enable_cmd_parser;
2316         /* leave bools at the end to not create holes */
2317         bool enable_hangcheck;
2318         bool fastboot;
2319         bool prefault_disable;
2320         bool reset;
2321         bool disable_display;
2322         bool disable_vtd_wa;
2323         int use_mmio_flip;
2324         bool mmio_debug;
2325 };
2326 extern struct i915_params i915 __read_mostly;
2327
2328                                 /* i915_dma.c */
2329 void i915_update_dri1_breadcrumb(struct drm_device *dev);
2330 extern void i915_kernel_lost_context(struct drm_device * dev);
2331 extern int i915_driver_load(struct drm_device *, unsigned long flags);
2332 extern int i915_driver_unload(struct drm_device *);
2333 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file);
2334 extern void i915_driver_lastclose(struct drm_device * dev);
2335 extern void i915_driver_preclose(struct drm_device *dev,
2336                                  struct drm_file *file);
2337 extern void i915_driver_postclose(struct drm_device *dev,
2338                                   struct drm_file *file);
2339 extern int i915_driver_device_is_agp(struct drm_device * dev);
2340 #ifdef CONFIG_COMPAT
2341 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
2342                               unsigned long arg);
2343 #endif
2344 extern int i915_emit_box(struct drm_device *dev,
2345                          struct drm_clip_rect *box,
2346                          int DR1, int DR4);
2347 extern int intel_gpu_reset(struct drm_device *dev);
2348 extern int i915_reset(struct drm_device *dev);
2349 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
2350 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
2351 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
2352 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
2353 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
2354 void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
2355
2356 /* i915_irq.c */
2357 void i915_queue_hangcheck(struct drm_device *dev);
2358 __printf(3, 4)
2359 void i915_handle_error(struct drm_device *dev, bool wedged,
2360                        const char *fmt, ...);
2361
2362 extern void intel_irq_init(struct drm_i915_private *dev_priv);
2363 extern void intel_hpd_init(struct drm_i915_private *dev_priv);
2364 int intel_irq_install(struct drm_i915_private *dev_priv);
2365 void intel_irq_uninstall(struct drm_i915_private *dev_priv);
2366
2367 extern void intel_uncore_sanitize(struct drm_device *dev);
2368 extern void intel_uncore_early_sanitize(struct drm_device *dev,
2369                                         bool restore_forcewake);
2370 extern void intel_uncore_init(struct drm_device *dev);
2371 extern void intel_uncore_check_errors(struct drm_device *dev);
2372 extern void intel_uncore_fini(struct drm_device *dev);
2373 extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore);
2374
2375 void
2376 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2377                      u32 status_mask);
2378
2379 void
2380 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2381                       u32 status_mask);
2382
2383 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
2384 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
2385 void
2386 ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask);
2387 void
2388 ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask);
2389 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
2390                                   uint32_t interrupt_mask,
2391                                   uint32_t enabled_irq_mask);
2392 #define ibx_enable_display_interrupt(dev_priv, bits) \
2393         ibx_display_interrupt_update((dev_priv), (bits), (bits))
2394 #define ibx_disable_display_interrupt(dev_priv, bits) \
2395         ibx_display_interrupt_update((dev_priv), (bits), 0)
2396
2397 /* i915_gem.c */
2398 int i915_gem_init_ioctl(struct drm_device *dev, void *data,
2399                         struct drm_file *file_priv);
2400 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
2401                           struct drm_file *file_priv);
2402 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
2403                          struct drm_file *file_priv);
2404 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2405                           struct drm_file *file_priv);
2406 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
2407                         struct drm_file *file_priv);
2408 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2409                         struct drm_file *file_priv);
2410 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2411                               struct drm_file *file_priv);
2412 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
2413                              struct drm_file *file_priv);
2414 void i915_gem_execbuffer_move_to_active(struct list_head *vmas,
2415                                         struct intel_engine_cs *ring);
2416 void i915_gem_execbuffer_retire_commands(struct drm_device *dev,
2417                                          struct drm_file *file,
2418                                          struct intel_engine_cs *ring,
2419                                          struct drm_i915_gem_object *obj);
2420 int i915_gem_ringbuffer_submission(struct drm_device *dev,
2421                                    struct drm_file *file,
2422                                    struct intel_engine_cs *ring,
2423                                    struct intel_context *ctx,
2424                                    struct drm_i915_gem_execbuffer2 *args,
2425                                    struct list_head *vmas,
2426                                    struct drm_i915_gem_object *batch_obj,
2427                                    u64 exec_start, u32 flags);
2428 int i915_gem_execbuffer(struct drm_device *dev, void *data,
2429                         struct drm_file *file_priv);
2430 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
2431                          struct drm_file *file_priv);
2432 int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
2433                        struct drm_file *file_priv);
2434 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
2435                          struct drm_file *file_priv);
2436 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
2437                         struct drm_file *file_priv);
2438 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
2439                                struct drm_file *file);
2440 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
2441                                struct drm_file *file);
2442 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
2443                             struct drm_file *file_priv);
2444 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
2445                            struct drm_file *file_priv);
2446 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
2447                            struct drm_file *file_priv);
2448 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
2449                            struct drm_file *file_priv);
2450 int i915_gem_set_tiling(struct drm_device *dev, void *data,
2451                         struct drm_file *file_priv);
2452 int i915_gem_get_tiling(struct drm_device *dev, void *data,
2453                         struct drm_file *file_priv);
2454 int i915_gem_init_userptr(struct drm_device *dev);
2455 int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
2456                            struct drm_file *file);
2457 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
2458                                 struct drm_file *file_priv);
2459 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
2460                         struct drm_file *file_priv);
2461 void i915_gem_load(struct drm_device *dev);
2462 unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv,
2463                               long target,
2464                               unsigned flags);
2465 #define I915_SHRINK_PURGEABLE 0x1
2466 #define I915_SHRINK_UNBOUND 0x2
2467 #define I915_SHRINK_BOUND 0x4
2468 void *i915_gem_object_alloc(struct drm_device *dev);
2469 void i915_gem_object_free(struct drm_i915_gem_object *obj);
2470 void i915_gem_object_init(struct drm_i915_gem_object *obj,
2471                          const struct drm_i915_gem_object_ops *ops);
2472 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
2473                                                   size_t size);
2474 void i915_init_vm(struct drm_i915_private *dev_priv,
2475                   struct i915_address_space *vm);
2476 void i915_gem_free_object(struct drm_gem_object *obj);
2477 void i915_gem_vma_destroy(struct i915_vma *vma);
2478
2479 #define PIN_MAPPABLE 0x1
2480 #define PIN_NONBLOCK 0x2
2481 #define PIN_GLOBAL 0x4
2482 #define PIN_OFFSET_BIAS 0x8
2483 #define PIN_OFFSET_MASK (~4095)
2484 int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
2485                                      struct i915_address_space *vm,
2486                                      uint32_t alignment,
2487                                      uint64_t flags);
2488 int __must_check i915_vma_unbind(struct i915_vma *vma);
2489 int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
2490 void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv);
2491 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
2492 void i915_gem_lastclose(struct drm_device *dev);
2493
2494 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
2495                                     int *needs_clflush);
2496
2497 int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
2498 static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
2499 {
2500         struct sg_page_iter sg_iter;
2501
2502         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, n)
2503                 return sg_page_iter_page(&sg_iter);
2504
2505         return NULL;
2506 }
2507 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
2508 {
2509         BUG_ON(obj->pages == NULL);
2510         obj->pages_pin_count++;
2511 }
2512 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
2513 {
2514         BUG_ON(obj->pages_pin_count == 0);
2515         obj->pages_pin_count--;
2516 }
2517
2518 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
2519 int i915_gem_object_sync(struct drm_i915_gem_object *obj,
2520                          struct intel_engine_cs *to);
2521 void i915_vma_move_to_active(struct i915_vma *vma,
2522                              struct intel_engine_cs *ring);
2523 int i915_gem_dumb_create(struct drm_file *file_priv,
2524                          struct drm_device *dev,
2525                          struct drm_mode_create_dumb *args);
2526 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
2527                       uint32_t handle, uint64_t *offset);
2528 /**
2529  * Returns true if seq1 is later than seq2.
2530  */
2531 static inline bool
2532 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
2533 {
2534         return (int32_t)(seq1 - seq2) >= 0;
2535 }
2536
2537 int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
2538 int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
2539 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
2540 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
2541
2542 bool i915_gem_object_pin_fence(struct drm_i915_gem_object *obj);
2543 void i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj);
2544
2545 struct drm_i915_gem_request *
2546 i915_gem_find_active_request(struct intel_engine_cs *ring);
2547
2548 bool i915_gem_retire_requests(struct drm_device *dev);
2549 void i915_gem_retire_requests_ring(struct intel_engine_cs *ring);
2550 int __must_check i915_gem_check_wedge(struct i915_gpu_error *error,
2551                                       bool interruptible);
2552 int __must_check i915_gem_check_olr(struct intel_engine_cs *ring, u32 seqno);
2553
2554 static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
2555 {
2556         return unlikely(atomic_read(&error->reset_counter)
2557                         & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED));
2558 }
2559
2560 static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
2561 {
2562         return atomic_read(&error->reset_counter) & I915_WEDGED;
2563 }
2564
2565 static inline u32 i915_reset_count(struct i915_gpu_error *error)
2566 {
2567         return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2;
2568 }
2569
2570 static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv)
2571 {
2572         return dev_priv->gpu_error.stop_rings == 0 ||
2573                 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_BAN;
2574 }
2575
2576 static inline bool i915_stop_ring_allow_warn(struct drm_i915_private *dev_priv)
2577 {
2578         return dev_priv->gpu_error.stop_rings == 0 ||
2579                 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_WARN;
2580 }
2581
2582 void i915_gem_reset(struct drm_device *dev);
2583 bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
2584 int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
2585 int __must_check i915_gem_init(struct drm_device *dev);
2586 int i915_gem_init_rings(struct drm_device *dev);
2587 int __must_check i915_gem_init_hw(struct drm_device *dev);
2588 int i915_gem_l3_remap(struct intel_engine_cs *ring, int slice);
2589 void i915_gem_init_swizzling(struct drm_device *dev);
2590 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
2591 int __must_check i915_gpu_idle(struct drm_device *dev);
2592 int __must_check i915_gem_suspend(struct drm_device *dev);
2593 int __i915_add_request(struct intel_engine_cs *ring,
2594                        struct drm_file *file,
2595                        struct drm_i915_gem_object *batch_obj,
2596                        u32 *seqno);
2597 #define i915_add_request(ring, seqno) \
2598         __i915_add_request(ring, NULL, NULL, seqno)
2599 int __i915_wait_seqno(struct intel_engine_cs *ring, u32 seqno,
2600                         unsigned reset_counter,
2601                         bool interruptible,
2602                         s64 *timeout,
2603                         struct drm_i915_file_private *file_priv);
2604 int __must_check i915_wait_seqno(struct intel_engine_cs *ring,
2605                                  uint32_t seqno);
2606 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
2607 int __must_check
2608 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
2609                                   bool write);
2610 int __must_check
2611 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
2612 int __must_check
2613 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
2614                                      u32 alignment,
2615                                      struct intel_engine_cs *pipelined);
2616 void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj);
2617 int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
2618                                 int align);
2619 int i915_gem_open(struct drm_device *dev, struct drm_file *file);
2620 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
2621
2622 uint32_t
2623 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
2624 uint32_t
2625 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
2626                             int tiling_mode, bool fenced);
2627
2628 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
2629                                     enum i915_cache_level cache_level);
2630
2631 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
2632                                 struct dma_buf *dma_buf);
2633
2634 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
2635                                 struct drm_gem_object *gem_obj, int flags);
2636
2637 void i915_gem_restore_fences(struct drm_device *dev);
2638
2639 unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o,
2640                                   struct i915_address_space *vm);
2641 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o);
2642 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
2643                         struct i915_address_space *vm);
2644 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
2645                                 struct i915_address_space *vm);
2646 struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
2647                                      struct i915_address_space *vm);
2648 struct i915_vma *
2649 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
2650                                   struct i915_address_space *vm);
2651
2652 struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj);
2653 static inline bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj) {
2654         struct i915_vma *vma;
2655         list_for_each_entry(vma, &obj->vma_list, vma_link)
2656                 if (vma->pin_count > 0)
2657                         return true;
2658         return false;
2659 }
2660
2661 /* Some GGTT VM helpers */
2662 #define i915_obj_to_ggtt(obj) \
2663         (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
2664 static inline bool i915_is_ggtt(struct i915_address_space *vm)
2665 {
2666         struct i915_address_space *ggtt =
2667                 &((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base;
2668         return vm == ggtt;
2669 }
2670
2671 static inline struct i915_hw_ppgtt *
2672 i915_vm_to_ppgtt(struct i915_address_space *vm)
2673 {
2674         WARN_ON(i915_is_ggtt(vm));
2675
2676         return container_of(vm, struct i915_hw_ppgtt, base);
2677 }
2678
2679
2680 static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj)
2681 {
2682         return i915_gem_obj_bound(obj, i915_obj_to_ggtt(obj));
2683 }
2684
2685 static inline unsigned long
2686 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *obj)
2687 {
2688         return i915_gem_obj_offset(obj, i915_obj_to_ggtt(obj));
2689 }
2690
2691 static inline unsigned long
2692 i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj)
2693 {
2694         return i915_gem_obj_size(obj, i915_obj_to_ggtt(obj));
2695 }
2696
2697 static inline int __must_check
2698 i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj,
2699                       uint32_t alignment,
2700                       unsigned flags)
2701 {
2702         return i915_gem_object_pin(obj, i915_obj_to_ggtt(obj),
2703                                    alignment, flags | PIN_GLOBAL);
2704 }
2705
2706 static inline int
2707 i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj)
2708 {
2709         return i915_vma_unbind(i915_gem_obj_to_ggtt(obj));
2710 }
2711
2712 void i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj);
2713
2714 /* i915_gem_context.c */
2715 int __must_check i915_gem_context_init(struct drm_device *dev);
2716 void i915_gem_context_fini(struct drm_device *dev);
2717 void i915_gem_context_reset(struct drm_device *dev);
2718 int i915_gem_context_open(struct drm_device *dev, struct drm_file *file);
2719 int i915_gem_context_enable(struct drm_i915_private *dev_priv);
2720 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
2721 int i915_switch_context(struct intel_engine_cs *ring,
2722                         struct intel_context *to);
2723 struct intel_context *
2724 i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id);
2725 void i915_gem_context_free(struct kref *ctx_ref);
2726 struct drm_i915_gem_object *
2727 i915_gem_alloc_context_obj(struct drm_device *dev, size_t size);
2728 static inline void i915_gem_context_reference(struct intel_context *ctx)
2729 {
2730         kref_get(&ctx->ref);
2731 }
2732
2733 static inline void i915_gem_context_unreference(struct intel_context *ctx)
2734 {
2735         kref_put(&ctx->ref, i915_gem_context_free);
2736 }
2737
2738 static inline bool i915_gem_context_is_default(const struct intel_context *c)
2739 {
2740         return c->user_handle == DEFAULT_CONTEXT_HANDLE;
2741 }
2742
2743 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
2744                                   struct drm_file *file);
2745 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
2746                                    struct drm_file *file);
2747
2748 /* i915_gem_evict.c */
2749 int __must_check i915_gem_evict_something(struct drm_device *dev,
2750                                           struct i915_address_space *vm,
2751                                           int min_size,
2752                                           unsigned alignment,
2753                                           unsigned cache_level,
2754                                           unsigned long start,
2755                                           unsigned long end,
2756                                           unsigned flags);
2757 int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
2758 int i915_gem_evict_everything(struct drm_device *dev);
2759
2760 /* belongs in i915_gem_gtt.h */
2761 static inline void i915_gem_chipset_flush(struct drm_device *dev)
2762 {
2763         if (INTEL_INFO(dev)->gen < 6)
2764                 intel_gtt_chipset_flush();
2765 }
2766
2767 /* i915_gem_stolen.c */
2768 int i915_gem_init_stolen(struct drm_device *dev);
2769 int i915_gem_stolen_setup_compression(struct drm_device *dev, int size, int fb_cpp);
2770 void i915_gem_stolen_cleanup_compression(struct drm_device *dev);
2771 void i915_gem_cleanup_stolen(struct drm_device *dev);
2772 struct drm_i915_gem_object *
2773 i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
2774 struct drm_i915_gem_object *
2775 i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
2776                                                u32 stolen_offset,
2777                                                u32 gtt_offset,
2778                                                u32 size);
2779
2780 /* i915_gem_tiling.c */
2781 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
2782 {
2783         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2784
2785         return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
2786                 obj->tiling_mode != I915_TILING_NONE;
2787 }
2788
2789 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
2790 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
2791 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
2792
2793 /* i915_gem_debug.c */
2794 #if WATCH_LISTS
2795 int i915_verify_lists(struct drm_device *dev);
2796 #else
2797 #define i915_verify_lists(dev) 0
2798 #endif
2799
2800 /* i915_debugfs.c */
2801 int i915_debugfs_init(struct drm_minor *minor);
2802 void i915_debugfs_cleanup(struct drm_minor *minor);
2803 #ifdef CONFIG_DEBUG_FS
2804 void intel_display_crc_init(struct drm_device *dev);
2805 #else
2806 static inline void intel_display_crc_init(struct drm_device *dev) {}
2807 #endif
2808
2809 /* i915_gpu_error.c */
2810 __printf(2, 3)
2811 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
2812 int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
2813                             const struct i915_error_state_file_priv *error);
2814 int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
2815                               struct drm_i915_private *i915,
2816                               size_t count, loff_t pos);
2817 static inline void i915_error_state_buf_release(
2818         struct drm_i915_error_state_buf *eb)
2819 {
2820         kfree(eb->buf);
2821 }
2822 void i915_capture_error_state(struct drm_device *dev, bool wedge,
2823                               const char *error_msg);
2824 void i915_error_state_get(struct drm_device *dev,
2825                           struct i915_error_state_file_priv *error_priv);
2826 void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
2827 void i915_destroy_error_state(struct drm_device *dev);
2828
2829 void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone);
2830 const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
2831
2832 /* i915_cmd_parser.c */
2833 int i915_cmd_parser_get_version(void);
2834 int i915_cmd_parser_init_ring(struct intel_engine_cs *ring);
2835 void i915_cmd_parser_fini_ring(struct intel_engine_cs *ring);
2836 bool i915_needs_cmd_parser(struct intel_engine_cs *ring);
2837 int i915_parse_cmds(struct intel_engine_cs *ring,
2838                     struct drm_i915_gem_object *batch_obj,
2839                     u32 batch_start_offset,
2840                     bool is_master);
2841
2842 /* i915_suspend.c */
2843 extern int i915_save_state(struct drm_device *dev);
2844 extern int i915_restore_state(struct drm_device *dev);
2845
2846 /* i915_ums.c */
2847 void i915_save_display_reg(struct drm_device *dev);
2848 void i915_restore_display_reg(struct drm_device *dev);
2849
2850 /* i915_sysfs.c */
2851 void i915_setup_sysfs(struct drm_device *dev_priv);
2852 void i915_teardown_sysfs(struct drm_device *dev_priv);
2853
2854 /* intel_i2c.c */
2855 extern int intel_setup_gmbus(struct drm_device *dev);
2856 extern void intel_teardown_gmbus(struct drm_device *dev);
2857 static inline bool intel_gmbus_is_port_valid(unsigned port)
2858 {
2859         return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD);
2860 }
2861
2862 extern struct i2c_adapter *intel_gmbus_get_adapter(
2863                 struct drm_i915_private *dev_priv, unsigned port);
2864 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
2865 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
2866 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
2867 {
2868         return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
2869 }
2870 extern void intel_i2c_reset(struct drm_device *dev);
2871
2872 /* intel_opregion.c */
2873 #ifdef CONFIG_ACPI
2874 extern int intel_opregion_setup(struct drm_device *dev);
2875 extern void intel_opregion_init(struct drm_device *dev);
2876 extern void intel_opregion_fini(struct drm_device *dev);
2877 extern void intel_opregion_asle_intr(struct drm_device *dev);
2878 extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
2879                                          bool enable);
2880 extern int intel_opregion_notify_adapter(struct drm_device *dev,
2881                                          pci_power_t state);
2882 #else
2883 static inline int intel_opregion_setup(struct drm_device *dev) { return 0; }
2884 static inline void intel_opregion_init(struct drm_device *dev) { return; }
2885 static inline void intel_opregion_fini(struct drm_device *dev) { return; }
2886 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
2887 static inline int
2888 intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
2889 {
2890         return 0;
2891 }
2892 static inline int
2893 intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state)
2894 {
2895         return 0;
2896 }
2897 #endif
2898
2899 /* intel_acpi.c */
2900 #ifdef CONFIG_ACPI
2901 extern void intel_register_dsm_handler(void);
2902 extern void intel_unregister_dsm_handler(void);
2903 #else
2904 static inline void intel_register_dsm_handler(void) { return; }
2905 static inline void intel_unregister_dsm_handler(void) { return; }
2906 #endif /* CONFIG_ACPI */
2907
2908 /* modesetting */
2909 extern void intel_modeset_init_hw(struct drm_device *dev);
2910 extern void intel_modeset_init(struct drm_device *dev);
2911 extern void intel_modeset_gem_init(struct drm_device *dev);
2912 extern void intel_modeset_cleanup(struct drm_device *dev);
2913 extern void intel_connector_unregister(struct intel_connector *);
2914 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
2915 extern void intel_modeset_setup_hw_state(struct drm_device *dev,
2916                                          bool force_restore);
2917 extern void i915_redisable_vga(struct drm_device *dev);
2918 extern void i915_redisable_vga_power_on(struct drm_device *dev);
2919 extern bool intel_fbc_enabled(struct drm_device *dev);
2920 extern void bdw_fbc_sw_flush(struct drm_device *dev, u32 value);
2921 extern void intel_disable_fbc(struct drm_device *dev);
2922 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
2923 extern void intel_init_pch_refclk(struct drm_device *dev);
2924 extern void gen6_set_rps(struct drm_device *dev, u8 val);
2925 extern void valleyview_set_rps(struct drm_device *dev, u8 val);
2926 extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
2927                                   bool enable);
2928 extern void intel_detect_pch(struct drm_device *dev);
2929 extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
2930 extern int intel_enable_rc6(const struct drm_device *dev);
2931
2932 extern bool i915_semaphore_is_enabled(struct drm_device *dev);
2933 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
2934                         struct drm_file *file);
2935 int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data,
2936                                struct drm_file *file);
2937
2938 void intel_notify_mmio_flip(struct intel_engine_cs *ring);
2939
2940 /* overlay */
2941 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
2942 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
2943                                             struct intel_overlay_error_state *error);
2944
2945 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
2946 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
2947                                             struct drm_device *dev,
2948                                             struct intel_display_error_state *error);
2949
2950 /* On SNB platform, before reading ring registers forcewake bit
2951  * must be set to prevent GT core from power down and stale values being
2952  * returned.
2953  */
2954 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine);
2955 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine);
2956 void assert_force_wake_inactive(struct drm_i915_private *dev_priv);
2957
2958 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val);
2959 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val);
2960
2961 /* intel_sideband.c */
2962 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr);
2963 void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val);
2964 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
2965 u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
2966 void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2967 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
2968 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2969 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
2970 void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2971 u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
2972 void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2973 u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg);
2974 void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2975 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
2976 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
2977 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
2978                    enum intel_sbi_destination destination);
2979 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
2980                      enum intel_sbi_destination destination);
2981 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
2982 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2983
2984 int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val);
2985 int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val);
2986
2987 #define FORCEWAKE_RENDER        (1 << 0)
2988 #define FORCEWAKE_MEDIA         (1 << 1)
2989 #define FORCEWAKE_BLITTER       (1 << 2)
2990 #define FORCEWAKE_ALL           (FORCEWAKE_RENDER | FORCEWAKE_MEDIA | \
2991                                         FORCEWAKE_BLITTER)
2992
2993
2994 #define I915_READ8(reg)         dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
2995 #define I915_WRITE8(reg, val)   dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
2996
2997 #define I915_READ16(reg)        dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
2998 #define I915_WRITE16(reg, val)  dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
2999 #define I915_READ16_NOTRACE(reg)        dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3000 #define I915_WRITE16_NOTRACE(reg, val)  dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
3001
3002 #define I915_READ(reg)          dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3003 #define I915_WRITE(reg, val)    dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3004 #define I915_READ_NOTRACE(reg)          dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3005 #define I915_WRITE_NOTRACE(reg, val)    dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3006
3007 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
3008  * will be implemented using 2 32-bit writes in an arbitrary order with
3009  * an arbitrary delay between them. This can cause the hardware to
3010  * act upon the intermediate value, possibly leading to corruption and
3011  * machine death. You have been warned.
3012  */
3013 #define I915_WRITE64(reg, val)  dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
3014 #define I915_READ64(reg)        dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3015
3016 #define I915_READ64_2x32(lower_reg, upper_reg) ({                       \
3017                 u32 upper = I915_READ(upper_reg);                       \
3018                 u32 lower = I915_READ(lower_reg);                       \
3019                 u32 tmp = I915_READ(upper_reg);                         \
3020                 if (upper != tmp) {                                     \
3021                         upper = tmp;                                    \
3022                         lower = I915_READ(lower_reg);                   \
3023                         WARN_ON(I915_READ(upper_reg) != upper);         \
3024                 }                                                       \
3025                 (u64)upper << 32 | lower; })
3026
3027 #define POSTING_READ(reg)       (void)I915_READ_NOTRACE(reg)
3028 #define POSTING_READ16(reg)     (void)I915_READ16_NOTRACE(reg)
3029
3030 /* "Broadcast RGB" property */
3031 #define INTEL_BROADCAST_RGB_AUTO 0
3032 #define INTEL_BROADCAST_RGB_FULL 1
3033 #define INTEL_BROADCAST_RGB_LIMITED 2
3034
3035 static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev)
3036 {
3037         if (IS_VALLEYVIEW(dev))
3038                 return VLV_VGACNTRL;
3039         else if (INTEL_INFO(dev)->gen >= 5)
3040                 return CPU_VGACNTRL;
3041         else
3042                 return VGACNTRL;
3043 }
3044
3045 static inline void __user *to_user_ptr(u64 address)
3046 {
3047         return (void __user *)(uintptr_t)address;
3048 }
3049
3050 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
3051 {
3052         unsigned long j = msecs_to_jiffies(m);
3053
3054         return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3055 }
3056
3057 static inline unsigned long
3058 timespec_to_jiffies_timeout(const struct timespec *value)
3059 {
3060         unsigned long j = timespec_to_jiffies(value);
3061
3062         return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3063 }
3064
3065 /*
3066  * If you need to wait X milliseconds between events A and B, but event B
3067  * doesn't happen exactly after event A, you record the timestamp (jiffies) of
3068  * when event A happened, then just before event B you call this function and
3069  * pass the timestamp as the first argument, and X as the second argument.
3070  */
3071 static inline void
3072 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
3073 {
3074         unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
3075
3076         /*
3077          * Don't re-read the value of "jiffies" every time since it may change
3078          * behind our back and break the math.
3079          */
3080         tmp_jiffies = jiffies;
3081         target_jiffies = timestamp_jiffies +
3082                          msecs_to_jiffies_timeout(to_wait_ms);
3083
3084         if (time_after(target_jiffies, tmp_jiffies)) {
3085                 remaining_jiffies = target_jiffies - tmp_jiffies;
3086                 while (remaining_jiffies)
3087                         remaining_jiffies =
3088                             schedule_timeout_uninterruptible(remaining_jiffies);
3089         }
3090 }
3091
3092 #endif