2 * Copyright © 2008-2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/drm_vma_manager.h>
30 #include <drm/i915_drm.h>
32 #include "i915_vgpu.h"
33 #include "i915_trace.h"
34 #include "intel_drv.h"
35 #include <linux/shmem_fs.h>
36 #include <linux/slab.h>
37 #include <linux/swap.h>
38 #include <linux/pci.h>
39 #include <linux/dma-buf.h>
41 #define RQ_BUG_ON(expr)
43 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
);
44 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
);
46 i915_gem_object_retire__write(struct drm_i915_gem_object
*obj
);
48 i915_gem_object_retire__read(struct drm_i915_gem_object
*obj
, int ring
);
49 static void i915_gem_write_fence(struct drm_device
*dev
, int reg
,
50 struct drm_i915_gem_object
*obj
);
51 static void i915_gem_object_update_fence(struct drm_i915_gem_object
*obj
,
52 struct drm_i915_fence_reg
*fence
,
55 static bool cpu_cache_is_coherent(struct drm_device
*dev
,
56 enum i915_cache_level level
)
58 return HAS_LLC(dev
) || level
!= I915_CACHE_NONE
;
61 static bool cpu_write_needs_clflush(struct drm_i915_gem_object
*obj
)
63 if (!cpu_cache_is_coherent(obj
->base
.dev
, obj
->cache_level
))
66 return obj
->pin_display
;
69 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object
*obj
)
72 i915_gem_release_mmap(obj
);
74 /* As we do not have an associated fence register, we will force
75 * a tiling change if we ever need to acquire one.
77 obj
->fence_dirty
= false;
78 obj
->fence_reg
= I915_FENCE_REG_NONE
;
81 /* some bookkeeping */
82 static void i915_gem_info_add_obj(struct drm_i915_private
*dev_priv
,
85 spin_lock(&dev_priv
->mm
.object_stat_lock
);
86 dev_priv
->mm
.object_count
++;
87 dev_priv
->mm
.object_memory
+= size
;
88 spin_unlock(&dev_priv
->mm
.object_stat_lock
);
91 static void i915_gem_info_remove_obj(struct drm_i915_private
*dev_priv
,
94 spin_lock(&dev_priv
->mm
.object_stat_lock
);
95 dev_priv
->mm
.object_count
--;
96 dev_priv
->mm
.object_memory
-= size
;
97 spin_unlock(&dev_priv
->mm
.object_stat_lock
);
101 i915_gem_wait_for_error(struct i915_gpu_error
*error
)
105 #define EXIT_COND (!i915_reset_in_progress(error) || \
106 i915_terminally_wedged(error))
111 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
112 * userspace. If it takes that long something really bad is going on and
113 * we should simply try to bail out and fail as gracefully as possible.
115 ret
= wait_event_interruptible_timeout(error
->reset_queue
,
119 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
121 } else if (ret
< 0) {
129 int i915_mutex_lock_interruptible(struct drm_device
*dev
)
131 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
134 ret
= i915_gem_wait_for_error(&dev_priv
->gpu_error
);
138 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
142 WARN_ON(i915_verify_lists(dev
));
147 i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
148 struct drm_file
*file
)
150 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
151 struct drm_i915_gem_get_aperture
*args
= data
;
152 struct drm_i915_gem_object
*obj
;
156 mutex_lock(&dev
->struct_mutex
);
157 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
)
158 if (i915_gem_obj_is_pinned(obj
))
159 pinned
+= i915_gem_obj_ggtt_size(obj
);
160 mutex_unlock(&dev
->struct_mutex
);
162 args
->aper_size
= dev_priv
->gtt
.base
.total
;
163 args
->aper_available_size
= args
->aper_size
- pinned
;
169 i915_gem_object_get_pages_phys(struct drm_i915_gem_object
*obj
)
171 struct address_space
*mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
172 char *vaddr
= obj
->phys_handle
->vaddr
;
174 struct scatterlist
*sg
;
177 if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj
)))
180 for (i
= 0; i
< obj
->base
.size
/ PAGE_SIZE
; i
++) {
184 page
= shmem_read_mapping_page(mapping
, i
);
186 return PTR_ERR(page
);
188 src
= kmap_atomic(page
);
189 memcpy(vaddr
, src
, PAGE_SIZE
);
190 drm_clflush_virt_range(vaddr
, PAGE_SIZE
);
193 page_cache_release(page
);
197 i915_gem_chipset_flush(obj
->base
.dev
);
199 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
203 if (sg_alloc_table(st
, 1, GFP_KERNEL
)) {
210 sg
->length
= obj
->base
.size
;
212 sg_dma_address(sg
) = obj
->phys_handle
->busaddr
;
213 sg_dma_len(sg
) = obj
->base
.size
;
216 obj
->has_dma_mapping
= true;
221 i915_gem_object_put_pages_phys(struct drm_i915_gem_object
*obj
)
225 BUG_ON(obj
->madv
== __I915_MADV_PURGED
);
227 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
229 /* In the event of a disaster, abandon all caches and
232 WARN_ON(ret
!= -EIO
);
233 obj
->base
.read_domains
= obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
236 if (obj
->madv
== I915_MADV_DONTNEED
)
240 struct address_space
*mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
241 char *vaddr
= obj
->phys_handle
->vaddr
;
244 for (i
= 0; i
< obj
->base
.size
/ PAGE_SIZE
; i
++) {
248 page
= shmem_read_mapping_page(mapping
, i
);
252 dst
= kmap_atomic(page
);
253 drm_clflush_virt_range(vaddr
, PAGE_SIZE
);
254 memcpy(dst
, vaddr
, PAGE_SIZE
);
257 set_page_dirty(page
);
258 if (obj
->madv
== I915_MADV_WILLNEED
)
259 mark_page_accessed(page
);
260 page_cache_release(page
);
266 sg_free_table(obj
->pages
);
269 obj
->has_dma_mapping
= false;
273 i915_gem_object_release_phys(struct drm_i915_gem_object
*obj
)
275 drm_pci_free(obj
->base
.dev
, obj
->phys_handle
);
278 static const struct drm_i915_gem_object_ops i915_gem_phys_ops
= {
279 .get_pages
= i915_gem_object_get_pages_phys
,
280 .put_pages
= i915_gem_object_put_pages_phys
,
281 .release
= i915_gem_object_release_phys
,
285 drop_pages(struct drm_i915_gem_object
*obj
)
287 struct i915_vma
*vma
, *next
;
290 drm_gem_object_reference(&obj
->base
);
291 list_for_each_entry_safe(vma
, next
, &obj
->vma_list
, vma_link
)
292 if (i915_vma_unbind(vma
))
295 ret
= i915_gem_object_put_pages(obj
);
296 drm_gem_object_unreference(&obj
->base
);
302 i915_gem_object_attach_phys(struct drm_i915_gem_object
*obj
,
305 drm_dma_handle_t
*phys
;
308 if (obj
->phys_handle
) {
309 if ((unsigned long)obj
->phys_handle
->vaddr
& (align
-1))
315 if (obj
->madv
!= I915_MADV_WILLNEED
)
318 if (obj
->base
.filp
== NULL
)
321 ret
= drop_pages(obj
);
325 /* create a new object */
326 phys
= drm_pci_alloc(obj
->base
.dev
, obj
->base
.size
, align
);
330 obj
->phys_handle
= phys
;
331 obj
->ops
= &i915_gem_phys_ops
;
333 return i915_gem_object_get_pages(obj
);
337 i915_gem_phys_pwrite(struct drm_i915_gem_object
*obj
,
338 struct drm_i915_gem_pwrite
*args
,
339 struct drm_file
*file_priv
)
341 struct drm_device
*dev
= obj
->base
.dev
;
342 void *vaddr
= obj
->phys_handle
->vaddr
+ args
->offset
;
343 char __user
*user_data
= to_user_ptr(args
->data_ptr
);
346 /* We manually control the domain here and pretend that it
347 * remains coherent i.e. in the GTT domain, like shmem_pwrite.
349 ret
= i915_gem_object_wait_rendering(obj
, false);
353 intel_fb_obj_invalidate(obj
, ORIGIN_CPU
);
354 if (__copy_from_user_inatomic_nocache(vaddr
, user_data
, args
->size
)) {
355 unsigned long unwritten
;
357 /* The physical object once assigned is fixed for the lifetime
358 * of the obj, so we can safely drop the lock and continue
361 mutex_unlock(&dev
->struct_mutex
);
362 unwritten
= copy_from_user(vaddr
, user_data
, args
->size
);
363 mutex_lock(&dev
->struct_mutex
);
370 drm_clflush_virt_range(vaddr
, args
->size
);
371 i915_gem_chipset_flush(dev
);
374 intel_fb_obj_flush(obj
, false);
378 void *i915_gem_object_alloc(struct drm_device
*dev
)
380 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
381 return kmem_cache_zalloc(dev_priv
->objects
, GFP_KERNEL
);
384 void i915_gem_object_free(struct drm_i915_gem_object
*obj
)
386 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
387 kmem_cache_free(dev_priv
->objects
, obj
);
391 i915_gem_create(struct drm_file
*file
,
392 struct drm_device
*dev
,
396 struct drm_i915_gem_object
*obj
;
400 size
= roundup(size
, PAGE_SIZE
);
404 /* Allocate the new object */
405 obj
= i915_gem_alloc_object(dev
, size
);
409 ret
= drm_gem_handle_create(file
, &obj
->base
, &handle
);
410 /* drop reference from allocate - handle holds it now */
411 drm_gem_object_unreference_unlocked(&obj
->base
);
420 i915_gem_dumb_create(struct drm_file
*file
,
421 struct drm_device
*dev
,
422 struct drm_mode_create_dumb
*args
)
424 /* have to work out size/pitch and return them */
425 args
->pitch
= ALIGN(args
->width
* DIV_ROUND_UP(args
->bpp
, 8), 64);
426 args
->size
= args
->pitch
* args
->height
;
427 return i915_gem_create(file
, dev
,
428 args
->size
, &args
->handle
);
432 * Creates a new mm object and returns a handle to it.
435 i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
436 struct drm_file
*file
)
438 struct drm_i915_gem_create
*args
= data
;
440 return i915_gem_create(file
, dev
,
441 args
->size
, &args
->handle
);
445 __copy_to_user_swizzled(char __user
*cpu_vaddr
,
446 const char *gpu_vaddr
, int gpu_offset
,
449 int ret
, cpu_offset
= 0;
452 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
453 int this_length
= min(cacheline_end
- gpu_offset
, length
);
454 int swizzled_gpu_offset
= gpu_offset
^ 64;
456 ret
= __copy_to_user(cpu_vaddr
+ cpu_offset
,
457 gpu_vaddr
+ swizzled_gpu_offset
,
462 cpu_offset
+= this_length
;
463 gpu_offset
+= this_length
;
464 length
-= this_length
;
471 __copy_from_user_swizzled(char *gpu_vaddr
, int gpu_offset
,
472 const char __user
*cpu_vaddr
,
475 int ret
, cpu_offset
= 0;
478 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
479 int this_length
= min(cacheline_end
- gpu_offset
, length
);
480 int swizzled_gpu_offset
= gpu_offset
^ 64;
482 ret
= __copy_from_user(gpu_vaddr
+ swizzled_gpu_offset
,
483 cpu_vaddr
+ cpu_offset
,
488 cpu_offset
+= this_length
;
489 gpu_offset
+= this_length
;
490 length
-= this_length
;
497 * Pins the specified object's pages and synchronizes the object with
498 * GPU accesses. Sets needs_clflush to non-zero if the caller should
499 * flush the object from the CPU cache.
501 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object
*obj
,
511 if (!(obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
)) {
512 /* If we're not in the cpu read domain, set ourself into the gtt
513 * read domain and manually flush cachelines (if required). This
514 * optimizes for the case when the gpu will dirty the data
515 * anyway again before the next pread happens. */
516 *needs_clflush
= !cpu_cache_is_coherent(obj
->base
.dev
,
518 ret
= i915_gem_object_wait_rendering(obj
, true);
523 ret
= i915_gem_object_get_pages(obj
);
527 i915_gem_object_pin_pages(obj
);
532 /* Per-page copy function for the shmem pread fastpath.
533 * Flushes invalid cachelines before reading the target if
534 * needs_clflush is set. */
536 shmem_pread_fast(struct page
*page
, int shmem_page_offset
, int page_length
,
537 char __user
*user_data
,
538 bool page_do_bit17_swizzling
, bool needs_clflush
)
543 if (unlikely(page_do_bit17_swizzling
))
546 vaddr
= kmap_atomic(page
);
548 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
550 ret
= __copy_to_user_inatomic(user_data
,
551 vaddr
+ shmem_page_offset
,
553 kunmap_atomic(vaddr
);
555 return ret
? -EFAULT
: 0;
559 shmem_clflush_swizzled_range(char *addr
, unsigned long length
,
562 if (unlikely(swizzled
)) {
563 unsigned long start
= (unsigned long) addr
;
564 unsigned long end
= (unsigned long) addr
+ length
;
566 /* For swizzling simply ensure that we always flush both
567 * channels. Lame, but simple and it works. Swizzled
568 * pwrite/pread is far from a hotpath - current userspace
569 * doesn't use it at all. */
570 start
= round_down(start
, 128);
571 end
= round_up(end
, 128);
573 drm_clflush_virt_range((void *)start
, end
- start
);
575 drm_clflush_virt_range(addr
, length
);
580 /* Only difference to the fast-path function is that this can handle bit17
581 * and uses non-atomic copy and kmap functions. */
583 shmem_pread_slow(struct page
*page
, int shmem_page_offset
, int page_length
,
584 char __user
*user_data
,
585 bool page_do_bit17_swizzling
, bool needs_clflush
)
592 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
594 page_do_bit17_swizzling
);
596 if (page_do_bit17_swizzling
)
597 ret
= __copy_to_user_swizzled(user_data
,
598 vaddr
, shmem_page_offset
,
601 ret
= __copy_to_user(user_data
,
602 vaddr
+ shmem_page_offset
,
606 return ret
? - EFAULT
: 0;
610 i915_gem_shmem_pread(struct drm_device
*dev
,
611 struct drm_i915_gem_object
*obj
,
612 struct drm_i915_gem_pread
*args
,
613 struct drm_file
*file
)
615 char __user
*user_data
;
618 int shmem_page_offset
, page_length
, ret
= 0;
619 int obj_do_bit17_swizzling
, page_do_bit17_swizzling
;
621 int needs_clflush
= 0;
622 struct sg_page_iter sg_iter
;
624 user_data
= to_user_ptr(args
->data_ptr
);
627 obj_do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
629 ret
= i915_gem_obj_prepare_shmem_read(obj
, &needs_clflush
);
633 offset
= args
->offset
;
635 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
,
636 offset
>> PAGE_SHIFT
) {
637 struct page
*page
= sg_page_iter_page(&sg_iter
);
642 /* Operation in this page
644 * shmem_page_offset = offset within page in shmem file
645 * page_length = bytes to copy for this page
647 shmem_page_offset
= offset_in_page(offset
);
648 page_length
= remain
;
649 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
650 page_length
= PAGE_SIZE
- shmem_page_offset
;
652 page_do_bit17_swizzling
= obj_do_bit17_swizzling
&&
653 (page_to_phys(page
) & (1 << 17)) != 0;
655 ret
= shmem_pread_fast(page
, shmem_page_offset
, page_length
,
656 user_data
, page_do_bit17_swizzling
,
661 mutex_unlock(&dev
->struct_mutex
);
663 if (likely(!i915
.prefault_disable
) && !prefaulted
) {
664 ret
= fault_in_multipages_writeable(user_data
, remain
);
665 /* Userspace is tricking us, but we've already clobbered
666 * its pages with the prefault and promised to write the
667 * data up to the first fault. Hence ignore any errors
668 * and just continue. */
673 ret
= shmem_pread_slow(page
, shmem_page_offset
, page_length
,
674 user_data
, page_do_bit17_swizzling
,
677 mutex_lock(&dev
->struct_mutex
);
683 remain
-= page_length
;
684 user_data
+= page_length
;
685 offset
+= page_length
;
689 i915_gem_object_unpin_pages(obj
);
695 * Reads data from the object referenced by handle.
697 * On error, the contents of *data are undefined.
700 i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
701 struct drm_file
*file
)
703 struct drm_i915_gem_pread
*args
= data
;
704 struct drm_i915_gem_object
*obj
;
710 if (!access_ok(VERIFY_WRITE
,
711 to_user_ptr(args
->data_ptr
),
715 ret
= i915_mutex_lock_interruptible(dev
);
719 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
720 if (&obj
->base
== NULL
) {
725 /* Bounds check source. */
726 if (args
->offset
> obj
->base
.size
||
727 args
->size
> obj
->base
.size
- args
->offset
) {
732 /* prime objects have no backing filp to GEM pread/pwrite
735 if (!obj
->base
.filp
) {
740 trace_i915_gem_object_pread(obj
, args
->offset
, args
->size
);
742 ret
= i915_gem_shmem_pread(dev
, obj
, args
, file
);
745 drm_gem_object_unreference(&obj
->base
);
747 mutex_unlock(&dev
->struct_mutex
);
751 /* This is the fast write path which cannot handle
752 * page faults in the source data
756 fast_user_write(struct io_mapping
*mapping
,
757 loff_t page_base
, int page_offset
,
758 char __user
*user_data
,
761 void __iomem
*vaddr_atomic
;
763 unsigned long unwritten
;
765 vaddr_atomic
= io_mapping_map_atomic_wc(mapping
, page_base
);
766 /* We can use the cpu mem copy function because this is X86. */
767 vaddr
= (void __force
*)vaddr_atomic
+ page_offset
;
768 unwritten
= __copy_from_user_inatomic_nocache(vaddr
,
770 io_mapping_unmap_atomic(vaddr_atomic
);
775 * This is the fast pwrite path, where we copy the data directly from the
776 * user into the GTT, uncached.
779 i915_gem_gtt_pwrite_fast(struct drm_device
*dev
,
780 struct drm_i915_gem_object
*obj
,
781 struct drm_i915_gem_pwrite
*args
,
782 struct drm_file
*file
)
784 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
786 loff_t offset
, page_base
;
787 char __user
*user_data
;
788 int page_offset
, page_length
, ret
;
790 ret
= i915_gem_obj_ggtt_pin(obj
, 0, PIN_MAPPABLE
| PIN_NONBLOCK
);
794 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
798 ret
= i915_gem_object_put_fence(obj
);
802 user_data
= to_user_ptr(args
->data_ptr
);
805 offset
= i915_gem_obj_ggtt_offset(obj
) + args
->offset
;
807 intel_fb_obj_invalidate(obj
, ORIGIN_GTT
);
810 /* Operation in this page
812 * page_base = page offset within aperture
813 * page_offset = offset within page
814 * page_length = bytes to copy for this page
816 page_base
= offset
& PAGE_MASK
;
817 page_offset
= offset_in_page(offset
);
818 page_length
= remain
;
819 if ((page_offset
+ remain
) > PAGE_SIZE
)
820 page_length
= PAGE_SIZE
- page_offset
;
822 /* If we get a fault while copying data, then (presumably) our
823 * source page isn't available. Return the error and we'll
824 * retry in the slow path.
826 if (fast_user_write(dev_priv
->gtt
.mappable
, page_base
,
827 page_offset
, user_data
, page_length
)) {
832 remain
-= page_length
;
833 user_data
+= page_length
;
834 offset
+= page_length
;
838 intel_fb_obj_flush(obj
, false);
840 i915_gem_object_ggtt_unpin(obj
);
845 /* Per-page copy function for the shmem pwrite fastpath.
846 * Flushes invalid cachelines before writing to the target if
847 * needs_clflush_before is set and flushes out any written cachelines after
848 * writing if needs_clflush is set. */
850 shmem_pwrite_fast(struct page
*page
, int shmem_page_offset
, int page_length
,
851 char __user
*user_data
,
852 bool page_do_bit17_swizzling
,
853 bool needs_clflush_before
,
854 bool needs_clflush_after
)
859 if (unlikely(page_do_bit17_swizzling
))
862 vaddr
= kmap_atomic(page
);
863 if (needs_clflush_before
)
864 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
866 ret
= __copy_from_user_inatomic(vaddr
+ shmem_page_offset
,
867 user_data
, page_length
);
868 if (needs_clflush_after
)
869 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
871 kunmap_atomic(vaddr
);
873 return ret
? -EFAULT
: 0;
876 /* Only difference to the fast-path function is that this can handle bit17
877 * and uses non-atomic copy and kmap functions. */
879 shmem_pwrite_slow(struct page
*page
, int shmem_page_offset
, int page_length
,
880 char __user
*user_data
,
881 bool page_do_bit17_swizzling
,
882 bool needs_clflush_before
,
883 bool needs_clflush_after
)
889 if (unlikely(needs_clflush_before
|| page_do_bit17_swizzling
))
890 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
892 page_do_bit17_swizzling
);
893 if (page_do_bit17_swizzling
)
894 ret
= __copy_from_user_swizzled(vaddr
, shmem_page_offset
,
898 ret
= __copy_from_user(vaddr
+ shmem_page_offset
,
901 if (needs_clflush_after
)
902 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
904 page_do_bit17_swizzling
);
907 return ret
? -EFAULT
: 0;
911 i915_gem_shmem_pwrite(struct drm_device
*dev
,
912 struct drm_i915_gem_object
*obj
,
913 struct drm_i915_gem_pwrite
*args
,
914 struct drm_file
*file
)
918 char __user
*user_data
;
919 int shmem_page_offset
, page_length
, ret
= 0;
920 int obj_do_bit17_swizzling
, page_do_bit17_swizzling
;
921 int hit_slowpath
= 0;
922 int needs_clflush_after
= 0;
923 int needs_clflush_before
= 0;
924 struct sg_page_iter sg_iter
;
926 user_data
= to_user_ptr(args
->data_ptr
);
929 obj_do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
931 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
932 /* If we're not in the cpu write domain, set ourself into the gtt
933 * write domain and manually flush cachelines (if required). This
934 * optimizes for the case when the gpu will use the data
935 * right away and we therefore have to clflush anyway. */
936 needs_clflush_after
= cpu_write_needs_clflush(obj
);
937 ret
= i915_gem_object_wait_rendering(obj
, false);
941 /* Same trick applies to invalidate partially written cachelines read
943 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) == 0)
944 needs_clflush_before
=
945 !cpu_cache_is_coherent(dev
, obj
->cache_level
);
947 ret
= i915_gem_object_get_pages(obj
);
951 intel_fb_obj_invalidate(obj
, ORIGIN_CPU
);
953 i915_gem_object_pin_pages(obj
);
955 offset
= args
->offset
;
958 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
,
959 offset
>> PAGE_SHIFT
) {
960 struct page
*page
= sg_page_iter_page(&sg_iter
);
961 int partial_cacheline_write
;
966 /* Operation in this page
968 * shmem_page_offset = offset within page in shmem file
969 * page_length = bytes to copy for this page
971 shmem_page_offset
= offset_in_page(offset
);
973 page_length
= remain
;
974 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
975 page_length
= PAGE_SIZE
- shmem_page_offset
;
977 /* If we don't overwrite a cacheline completely we need to be
978 * careful to have up-to-date data by first clflushing. Don't
979 * overcomplicate things and flush the entire patch. */
980 partial_cacheline_write
= needs_clflush_before
&&
981 ((shmem_page_offset
| page_length
)
982 & (boot_cpu_data
.x86_clflush_size
- 1));
984 page_do_bit17_swizzling
= obj_do_bit17_swizzling
&&
985 (page_to_phys(page
) & (1 << 17)) != 0;
987 ret
= shmem_pwrite_fast(page
, shmem_page_offset
, page_length
,
988 user_data
, page_do_bit17_swizzling
,
989 partial_cacheline_write
,
990 needs_clflush_after
);
995 mutex_unlock(&dev
->struct_mutex
);
996 ret
= shmem_pwrite_slow(page
, shmem_page_offset
, page_length
,
997 user_data
, page_do_bit17_swizzling
,
998 partial_cacheline_write
,
999 needs_clflush_after
);
1001 mutex_lock(&dev
->struct_mutex
);
1007 remain
-= page_length
;
1008 user_data
+= page_length
;
1009 offset
+= page_length
;
1013 i915_gem_object_unpin_pages(obj
);
1017 * Fixup: Flush cpu caches in case we didn't flush the dirty
1018 * cachelines in-line while writing and the object moved
1019 * out of the cpu write domain while we've dropped the lock.
1021 if (!needs_clflush_after
&&
1022 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
1023 if (i915_gem_clflush_object(obj
, obj
->pin_display
))
1024 i915_gem_chipset_flush(dev
);
1028 if (needs_clflush_after
)
1029 i915_gem_chipset_flush(dev
);
1031 intel_fb_obj_flush(obj
, false);
1036 * Writes data to the object referenced by handle.
1038 * On error, the contents of the buffer that were to be modified are undefined.
1041 i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
1042 struct drm_file
*file
)
1044 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1045 struct drm_i915_gem_pwrite
*args
= data
;
1046 struct drm_i915_gem_object
*obj
;
1049 if (args
->size
== 0)
1052 if (!access_ok(VERIFY_READ
,
1053 to_user_ptr(args
->data_ptr
),
1057 if (likely(!i915
.prefault_disable
)) {
1058 ret
= fault_in_multipages_readable(to_user_ptr(args
->data_ptr
),
1064 intel_runtime_pm_get(dev_priv
);
1066 ret
= i915_mutex_lock_interruptible(dev
);
1070 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1071 if (&obj
->base
== NULL
) {
1076 /* Bounds check destination. */
1077 if (args
->offset
> obj
->base
.size
||
1078 args
->size
> obj
->base
.size
- args
->offset
) {
1083 /* prime objects have no backing filp to GEM pread/pwrite
1086 if (!obj
->base
.filp
) {
1091 trace_i915_gem_object_pwrite(obj
, args
->offset
, args
->size
);
1094 /* We can only do the GTT pwrite on untiled buffers, as otherwise
1095 * it would end up going through the fenced access, and we'll get
1096 * different detiling behavior between reading and writing.
1097 * pread/pwrite currently are reading and writing from the CPU
1098 * perspective, requiring manual detiling by the client.
1100 if (obj
->tiling_mode
== I915_TILING_NONE
&&
1101 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
&&
1102 cpu_write_needs_clflush(obj
)) {
1103 ret
= i915_gem_gtt_pwrite_fast(dev
, obj
, args
, file
);
1104 /* Note that the gtt paths might fail with non-page-backed user
1105 * pointers (e.g. gtt mappings when moving data between
1106 * textures). Fallback to the shmem path in that case. */
1109 if (ret
== -EFAULT
|| ret
== -ENOSPC
) {
1110 if (obj
->phys_handle
)
1111 ret
= i915_gem_phys_pwrite(obj
, args
, file
);
1113 ret
= i915_gem_shmem_pwrite(dev
, obj
, args
, file
);
1117 drm_gem_object_unreference(&obj
->base
);
1119 mutex_unlock(&dev
->struct_mutex
);
1121 intel_runtime_pm_put(dev_priv
);
1127 i915_gem_check_wedge(struct i915_gpu_error
*error
,
1130 if (i915_reset_in_progress(error
)) {
1131 /* Non-interruptible callers can't handle -EAGAIN, hence return
1132 * -EIO unconditionally for these. */
1136 /* Recovery complete, but the reset failed ... */
1137 if (i915_terminally_wedged(error
))
1141 * Check if GPU Reset is in progress - we need intel_ring_begin
1142 * to work properly to reinit the hw state while the gpu is
1143 * still marked as reset-in-progress. Handle this with a flag.
1145 if (!error
->reload_in_reset
)
1153 * Compare arbitrary request against outstanding lazy request. Emit on match.
1156 i915_gem_check_olr(struct drm_i915_gem_request
*req
)
1158 WARN_ON(!mutex_is_locked(&req
->ring
->dev
->struct_mutex
));
1160 if (req
== req
->ring
->outstanding_lazy_request
)
1161 i915_add_request(req
);
1166 static void fake_irq(unsigned long data
)
1168 wake_up_process((struct task_struct
*)data
);
1171 static bool missed_irq(struct drm_i915_private
*dev_priv
,
1172 struct intel_engine_cs
*ring
)
1174 return test_bit(ring
->id
, &dev_priv
->gpu_error
.missed_irq_rings
);
1177 static int __i915_spin_request(struct drm_i915_gem_request
*req
)
1179 unsigned long timeout
;
1181 if (i915_gem_request_get_ring(req
)->irq_refcount
)
1184 timeout
= jiffies
+ 1;
1185 while (!need_resched()) {
1186 if (i915_gem_request_completed(req
, true))
1189 if (time_after_eq(jiffies
, timeout
))
1192 cpu_relax_lowlatency();
1194 if (i915_gem_request_completed(req
, false))
1201 * __i915_wait_request - wait until execution of request has finished
1203 * @reset_counter: reset sequence associated with the given request
1204 * @interruptible: do an interruptible wait (normally yes)
1205 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
1207 * Note: It is of utmost importance that the passed in seqno and reset_counter
1208 * values have been read by the caller in an smp safe manner. Where read-side
1209 * locks are involved, it is sufficient to read the reset_counter before
1210 * unlocking the lock that protects the seqno. For lockless tricks, the
1211 * reset_counter _must_ be read before, and an appropriate smp_rmb must be
1214 * Returns 0 if the request was found within the alloted time. Else returns the
1215 * errno with remaining time filled in timeout argument.
1217 int __i915_wait_request(struct drm_i915_gem_request
*req
,
1218 unsigned reset_counter
,
1221 struct intel_rps_client
*rps
)
1223 struct intel_engine_cs
*ring
= i915_gem_request_get_ring(req
);
1224 struct drm_device
*dev
= ring
->dev
;
1225 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1226 const bool irq_test_in_progress
=
1227 ACCESS_ONCE(dev_priv
->gpu_error
.test_irq_rings
) & intel_ring_flag(ring
);
1229 unsigned long timeout_expire
;
1233 WARN(!intel_irqs_enabled(dev_priv
), "IRQs disabled");
1235 if (list_empty(&req
->list
))
1238 if (i915_gem_request_completed(req
, true))
1241 timeout_expire
= timeout
?
1242 jiffies
+ nsecs_to_jiffies_timeout((u64
)*timeout
) : 0;
1244 if (INTEL_INFO(dev_priv
)->gen
>= 6)
1245 gen6_rps_boost(dev_priv
, rps
, req
->emitted_jiffies
);
1247 /* Record current time in case interrupted by signal, or wedged */
1248 trace_i915_gem_request_wait_begin(req
);
1249 before
= ktime_get_raw_ns();
1251 /* Optimistic spin for the next jiffie before touching IRQs */
1252 ret
= __i915_spin_request(req
);
1256 if (!irq_test_in_progress
&& WARN_ON(!ring
->irq_get(ring
))) {
1262 struct timer_list timer
;
1264 prepare_to_wait(&ring
->irq_queue
, &wait
,
1265 interruptible
? TASK_INTERRUPTIBLE
: TASK_UNINTERRUPTIBLE
);
1267 /* We need to check whether any gpu reset happened in between
1268 * the caller grabbing the seqno and now ... */
1269 if (reset_counter
!= atomic_read(&dev_priv
->gpu_error
.reset_counter
)) {
1270 /* ... but upgrade the -EAGAIN to an -EIO if the gpu
1271 * is truely gone. */
1272 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, interruptible
);
1278 if (i915_gem_request_completed(req
, false)) {
1283 if (interruptible
&& signal_pending(current
)) {
1288 if (timeout
&& time_after_eq(jiffies
, timeout_expire
)) {
1293 timer
.function
= NULL
;
1294 if (timeout
|| missed_irq(dev_priv
, ring
)) {
1295 unsigned long expire
;
1297 setup_timer_on_stack(&timer
, fake_irq
, (unsigned long)current
);
1298 expire
= missed_irq(dev_priv
, ring
) ? jiffies
+ 1 : timeout_expire
;
1299 mod_timer(&timer
, expire
);
1304 if (timer
.function
) {
1305 del_singleshot_timer_sync(&timer
);
1306 destroy_timer_on_stack(&timer
);
1309 if (!irq_test_in_progress
)
1310 ring
->irq_put(ring
);
1312 finish_wait(&ring
->irq_queue
, &wait
);
1315 now
= ktime_get_raw_ns();
1316 trace_i915_gem_request_wait_end(req
);
1319 s64 tres
= *timeout
- (now
- before
);
1321 *timeout
= tres
< 0 ? 0 : tres
;
1324 * Apparently ktime isn't accurate enough and occasionally has a
1325 * bit of mismatch in the jiffies<->nsecs<->ktime loop. So patch
1326 * things up to make the test happy. We allow up to 1 jiffy.
1328 * This is a regrssion from the timespec->ktime conversion.
1330 if (ret
== -ETIME
&& *timeout
< jiffies_to_usecs(1)*1000)
1338 i915_gem_request_remove_from_client(struct drm_i915_gem_request
*request
)
1340 struct drm_i915_file_private
*file_priv
= request
->file_priv
;
1345 spin_lock(&file_priv
->mm
.lock
);
1346 list_del(&request
->client_list
);
1347 request
->file_priv
= NULL
;
1348 spin_unlock(&file_priv
->mm
.lock
);
1351 static void i915_gem_request_retire(struct drm_i915_gem_request
*request
)
1353 trace_i915_gem_request_retire(request
);
1355 /* We know the GPU must have read the request to have
1356 * sent us the seqno + interrupt, so use the position
1357 * of tail of the request to update the last known position
1360 * Note this requires that we are always called in request
1363 request
->ringbuf
->last_retired_head
= request
->postfix
;
1365 list_del_init(&request
->list
);
1366 i915_gem_request_remove_from_client(request
);
1368 put_pid(request
->pid
);
1370 i915_gem_request_unreference(request
);
1374 __i915_gem_request_retire__upto(struct drm_i915_gem_request
*req
)
1376 struct intel_engine_cs
*engine
= req
->ring
;
1377 struct drm_i915_gem_request
*tmp
;
1379 lockdep_assert_held(&engine
->dev
->struct_mutex
);
1381 if (list_empty(&req
->list
))
1385 tmp
= list_first_entry(&engine
->request_list
,
1386 typeof(*tmp
), list
);
1388 i915_gem_request_retire(tmp
);
1389 } while (tmp
!= req
);
1391 WARN_ON(i915_verify_lists(engine
->dev
));
1395 * Waits for a request to be signaled, and cleans up the
1396 * request and object lists appropriately for that event.
1399 i915_wait_request(struct drm_i915_gem_request
*req
)
1401 struct drm_device
*dev
;
1402 struct drm_i915_private
*dev_priv
;
1406 BUG_ON(req
== NULL
);
1408 dev
= req
->ring
->dev
;
1409 dev_priv
= dev
->dev_private
;
1410 interruptible
= dev_priv
->mm
.interruptible
;
1412 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
1414 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, interruptible
);
1418 ret
= i915_gem_check_olr(req
);
1422 ret
= __i915_wait_request(req
,
1423 atomic_read(&dev_priv
->gpu_error
.reset_counter
),
1424 interruptible
, NULL
, NULL
);
1428 __i915_gem_request_retire__upto(req
);
1433 * Ensures that all rendering to the object has completed and the object is
1434 * safe to unbind from the GTT or access from the CPU.
1437 i915_gem_object_wait_rendering(struct drm_i915_gem_object
*obj
,
1446 if (obj
->last_write_req
!= NULL
) {
1447 ret
= i915_wait_request(obj
->last_write_req
);
1451 i
= obj
->last_write_req
->ring
->id
;
1452 if (obj
->last_read_req
[i
] == obj
->last_write_req
)
1453 i915_gem_object_retire__read(obj
, i
);
1455 i915_gem_object_retire__write(obj
);
1458 for (i
= 0; i
< I915_NUM_RINGS
; i
++) {
1459 if (obj
->last_read_req
[i
] == NULL
)
1462 ret
= i915_wait_request(obj
->last_read_req
[i
]);
1466 i915_gem_object_retire__read(obj
, i
);
1468 RQ_BUG_ON(obj
->active
);
1475 i915_gem_object_retire_request(struct drm_i915_gem_object
*obj
,
1476 struct drm_i915_gem_request
*req
)
1478 int ring
= req
->ring
->id
;
1480 if (obj
->last_read_req
[ring
] == req
)
1481 i915_gem_object_retire__read(obj
, ring
);
1482 else if (obj
->last_write_req
== req
)
1483 i915_gem_object_retire__write(obj
);
1485 __i915_gem_request_retire__upto(req
);
1488 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1489 * as the object state may change during this call.
1491 static __must_check
int
1492 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object
*obj
,
1493 struct intel_rps_client
*rps
,
1496 struct drm_device
*dev
= obj
->base
.dev
;
1497 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1498 struct drm_i915_gem_request
*requests
[I915_NUM_RINGS
];
1499 unsigned reset_counter
;
1502 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
1503 BUG_ON(!dev_priv
->mm
.interruptible
);
1508 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, true);
1512 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
1515 struct drm_i915_gem_request
*req
;
1517 req
= obj
->last_write_req
;
1521 ret
= i915_gem_check_olr(req
);
1525 requests
[n
++] = i915_gem_request_reference(req
);
1527 for (i
= 0; i
< I915_NUM_RINGS
; i
++) {
1528 struct drm_i915_gem_request
*req
;
1530 req
= obj
->last_read_req
[i
];
1534 ret
= i915_gem_check_olr(req
);
1538 requests
[n
++] = i915_gem_request_reference(req
);
1542 mutex_unlock(&dev
->struct_mutex
);
1543 for (i
= 0; ret
== 0 && i
< n
; i
++)
1544 ret
= __i915_wait_request(requests
[i
], reset_counter
, true,
1546 mutex_lock(&dev
->struct_mutex
);
1549 for (i
= 0; i
< n
; i
++) {
1551 i915_gem_object_retire_request(obj
, requests
[i
]);
1552 i915_gem_request_unreference(requests
[i
]);
1558 static struct intel_rps_client
*to_rps_client(struct drm_file
*file
)
1560 struct drm_i915_file_private
*fpriv
= file
->driver_priv
;
1565 * Called when user space prepares to use an object with the CPU, either
1566 * through the mmap ioctl's mapping or a GTT mapping.
1569 i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
1570 struct drm_file
*file
)
1572 struct drm_i915_gem_set_domain
*args
= data
;
1573 struct drm_i915_gem_object
*obj
;
1574 uint32_t read_domains
= args
->read_domains
;
1575 uint32_t write_domain
= args
->write_domain
;
1578 /* Only handle setting domains to types used by the CPU. */
1579 if (write_domain
& I915_GEM_GPU_DOMAINS
)
1582 if (read_domains
& I915_GEM_GPU_DOMAINS
)
1585 /* Having something in the write domain implies it's in the read
1586 * domain, and only that read domain. Enforce that in the request.
1588 if (write_domain
!= 0 && read_domains
!= write_domain
)
1591 ret
= i915_mutex_lock_interruptible(dev
);
1595 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1596 if (&obj
->base
== NULL
) {
1601 /* Try to flush the object off the GPU without holding the lock.
1602 * We will repeat the flush holding the lock in the normal manner
1603 * to catch cases where we are gazumped.
1605 ret
= i915_gem_object_wait_rendering__nonblocking(obj
,
1606 to_rps_client(file
),
1611 if (read_domains
& I915_GEM_DOMAIN_GTT
)
1612 ret
= i915_gem_object_set_to_gtt_domain(obj
, write_domain
!= 0);
1614 ret
= i915_gem_object_set_to_cpu_domain(obj
, write_domain
!= 0);
1617 drm_gem_object_unreference(&obj
->base
);
1619 mutex_unlock(&dev
->struct_mutex
);
1624 * Called when user space has done writes to this buffer
1627 i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1628 struct drm_file
*file
)
1630 struct drm_i915_gem_sw_finish
*args
= data
;
1631 struct drm_i915_gem_object
*obj
;
1634 ret
= i915_mutex_lock_interruptible(dev
);
1638 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1639 if (&obj
->base
== NULL
) {
1644 /* Pinned buffers may be scanout, so flush the cache */
1645 if (obj
->pin_display
)
1646 i915_gem_object_flush_cpu_write_domain(obj
);
1648 drm_gem_object_unreference(&obj
->base
);
1650 mutex_unlock(&dev
->struct_mutex
);
1655 * Maps the contents of an object, returning the address it is mapped
1658 * While the mapping holds a reference on the contents of the object, it doesn't
1659 * imply a ref on the object itself.
1663 * DRM driver writers who look a this function as an example for how to do GEM
1664 * mmap support, please don't implement mmap support like here. The modern way
1665 * to implement DRM mmap support is with an mmap offset ioctl (like
1666 * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly.
1667 * That way debug tooling like valgrind will understand what's going on, hiding
1668 * the mmap call in a driver private ioctl will break that. The i915 driver only
1669 * does cpu mmaps this way because we didn't know better.
1672 i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1673 struct drm_file
*file
)
1675 struct drm_i915_gem_mmap
*args
= data
;
1676 struct drm_gem_object
*obj
;
1679 if (args
->flags
& ~(I915_MMAP_WC
))
1682 if (args
->flags
& I915_MMAP_WC
&& !cpu_has_pat
)
1685 obj
= drm_gem_object_lookup(dev
, file
, args
->handle
);
1689 /* prime objects have no backing filp to GEM mmap
1693 drm_gem_object_unreference_unlocked(obj
);
1697 addr
= vm_mmap(obj
->filp
, 0, args
->size
,
1698 PROT_READ
| PROT_WRITE
, MAP_SHARED
,
1700 if (args
->flags
& I915_MMAP_WC
) {
1701 struct mm_struct
*mm
= current
->mm
;
1702 struct vm_area_struct
*vma
;
1704 down_write(&mm
->mmap_sem
);
1705 vma
= find_vma(mm
, addr
);
1708 pgprot_writecombine(vm_get_page_prot(vma
->vm_flags
));
1711 up_write(&mm
->mmap_sem
);
1713 drm_gem_object_unreference_unlocked(obj
);
1714 if (IS_ERR((void *)addr
))
1717 args
->addr_ptr
= (uint64_t) addr
;
1723 * i915_gem_fault - fault a page into the GTT
1724 * vma: VMA in question
1727 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1728 * from userspace. The fault handler takes care of binding the object to
1729 * the GTT (if needed), allocating and programming a fence register (again,
1730 * only if needed based on whether the old reg is still valid or the object
1731 * is tiled) and inserting a new PTE into the faulting process.
1733 * Note that the faulting process may involve evicting existing objects
1734 * from the GTT and/or fence registers to make room. So performance may
1735 * suffer if the GTT working set is large or there are few fence registers
1738 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
)
1740 struct drm_i915_gem_object
*obj
= to_intel_bo(vma
->vm_private_data
);
1741 struct drm_device
*dev
= obj
->base
.dev
;
1742 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1743 struct i915_ggtt_view view
= i915_ggtt_view_normal
;
1744 pgoff_t page_offset
;
1747 bool write
= !!(vmf
->flags
& FAULT_FLAG_WRITE
);
1749 intel_runtime_pm_get(dev_priv
);
1751 /* We don't use vmf->pgoff since that has the fake offset */
1752 page_offset
= ((unsigned long)vmf
->virtual_address
- vma
->vm_start
) >>
1755 ret
= i915_mutex_lock_interruptible(dev
);
1759 trace_i915_gem_object_fault(obj
, page_offset
, true, write
);
1761 /* Try to flush the object off the GPU first without holding the lock.
1762 * Upon reacquiring the lock, we will perform our sanity checks and then
1763 * repeat the flush holding the lock in the normal manner to catch cases
1764 * where we are gazumped.
1766 ret
= i915_gem_object_wait_rendering__nonblocking(obj
, NULL
, !write
);
1770 /* Access to snoopable pages through the GTT is incoherent. */
1771 if (obj
->cache_level
!= I915_CACHE_NONE
&& !HAS_LLC(dev
)) {
1776 /* Use a partial view if the object is bigger than the aperture. */
1777 if (obj
->base
.size
>= dev_priv
->gtt
.mappable_end
&&
1778 obj
->tiling_mode
== I915_TILING_NONE
) {
1779 static const unsigned int chunk_size
= 256; // 1 MiB
1781 memset(&view
, 0, sizeof(view
));
1782 view
.type
= I915_GGTT_VIEW_PARTIAL
;
1783 view
.params
.partial
.offset
= rounddown(page_offset
, chunk_size
);
1784 view
.params
.partial
.size
=
1787 (vma
->vm_end
- vma
->vm_start
)/PAGE_SIZE
-
1788 view
.params
.partial
.offset
);
1791 /* Now pin it into the GTT if needed */
1792 ret
= i915_gem_object_ggtt_pin(obj
, &view
, 0, PIN_MAPPABLE
);
1796 ret
= i915_gem_object_set_to_gtt_domain(obj
, write
);
1800 ret
= i915_gem_object_get_fence(obj
);
1804 /* Finally, remap it using the new GTT offset */
1805 pfn
= dev_priv
->gtt
.mappable_base
+
1806 i915_gem_obj_ggtt_offset_view(obj
, &view
);
1809 if (unlikely(view
.type
== I915_GGTT_VIEW_PARTIAL
)) {
1810 /* Overriding existing pages in partial view does not cause
1811 * us any trouble as TLBs are still valid because the fault
1812 * is due to userspace losing part of the mapping or never
1813 * having accessed it before (at this partials' range).
1815 unsigned long base
= vma
->vm_start
+
1816 (view
.params
.partial
.offset
<< PAGE_SHIFT
);
1819 for (i
= 0; i
< view
.params
.partial
.size
; i
++) {
1820 ret
= vm_insert_pfn(vma
, base
+ i
* PAGE_SIZE
, pfn
+ i
);
1825 obj
->fault_mappable
= true;
1827 if (!obj
->fault_mappable
) {
1828 unsigned long size
= min_t(unsigned long,
1829 vma
->vm_end
- vma
->vm_start
,
1833 for (i
= 0; i
< size
>> PAGE_SHIFT
; i
++) {
1834 ret
= vm_insert_pfn(vma
,
1835 (unsigned long)vma
->vm_start
+ i
* PAGE_SIZE
,
1841 obj
->fault_mappable
= true;
1843 ret
= vm_insert_pfn(vma
,
1844 (unsigned long)vmf
->virtual_address
,
1848 i915_gem_object_ggtt_unpin_view(obj
, &view
);
1850 mutex_unlock(&dev
->struct_mutex
);
1855 * We eat errors when the gpu is terminally wedged to avoid
1856 * userspace unduly crashing (gl has no provisions for mmaps to
1857 * fail). But any other -EIO isn't ours (e.g. swap in failure)
1858 * and so needs to be reported.
1860 if (!i915_terminally_wedged(&dev_priv
->gpu_error
)) {
1861 ret
= VM_FAULT_SIGBUS
;
1866 * EAGAIN means the gpu is hung and we'll wait for the error
1867 * handler to reset everything when re-faulting in
1868 * i915_mutex_lock_interruptible.
1875 * EBUSY is ok: this just means that another thread
1876 * already did the job.
1878 ret
= VM_FAULT_NOPAGE
;
1885 ret
= VM_FAULT_SIGBUS
;
1888 WARN_ONCE(ret
, "unhandled error in i915_gem_fault: %i\n", ret
);
1889 ret
= VM_FAULT_SIGBUS
;
1893 intel_runtime_pm_put(dev_priv
);
1898 * i915_gem_release_mmap - remove physical page mappings
1899 * @obj: obj in question
1901 * Preserve the reservation of the mmapping with the DRM core code, but
1902 * relinquish ownership of the pages back to the system.
1904 * It is vital that we remove the page mapping if we have mapped a tiled
1905 * object through the GTT and then lose the fence register due to
1906 * resource pressure. Similarly if the object has been moved out of the
1907 * aperture, than pages mapped into userspace must be revoked. Removing the
1908 * mapping will then trigger a page fault on the next user access, allowing
1909 * fixup by i915_gem_fault().
1912 i915_gem_release_mmap(struct drm_i915_gem_object
*obj
)
1914 if (!obj
->fault_mappable
)
1917 drm_vma_node_unmap(&obj
->base
.vma_node
,
1918 obj
->base
.dev
->anon_inode
->i_mapping
);
1919 obj
->fault_mappable
= false;
1923 i915_gem_release_all_mmaps(struct drm_i915_private
*dev_priv
)
1925 struct drm_i915_gem_object
*obj
;
1927 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
)
1928 i915_gem_release_mmap(obj
);
1932 i915_gem_get_gtt_size(struct drm_device
*dev
, uint32_t size
, int tiling_mode
)
1936 if (INTEL_INFO(dev
)->gen
>= 4 ||
1937 tiling_mode
== I915_TILING_NONE
)
1940 /* Previous chips need a power-of-two fence region when tiling */
1941 if (INTEL_INFO(dev
)->gen
== 3)
1942 gtt_size
= 1024*1024;
1944 gtt_size
= 512*1024;
1946 while (gtt_size
< size
)
1953 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1954 * @obj: object to check
1956 * Return the required GTT alignment for an object, taking into account
1957 * potential fence register mapping.
1960 i915_gem_get_gtt_alignment(struct drm_device
*dev
, uint32_t size
,
1961 int tiling_mode
, bool fenced
)
1964 * Minimum alignment is 4k (GTT page size), but might be greater
1965 * if a fence register is needed for the object.
1967 if (INTEL_INFO(dev
)->gen
>= 4 || (!fenced
&& IS_G33(dev
)) ||
1968 tiling_mode
== I915_TILING_NONE
)
1972 * Previous chips need to be aligned to the size of the smallest
1973 * fence register that can contain the object.
1975 return i915_gem_get_gtt_size(dev
, size
, tiling_mode
);
1978 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object
*obj
)
1980 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
1983 if (drm_vma_node_has_offset(&obj
->base
.vma_node
))
1986 dev_priv
->mm
.shrinker_no_lock_stealing
= true;
1988 ret
= drm_gem_create_mmap_offset(&obj
->base
);
1992 /* Badly fragmented mmap space? The only way we can recover
1993 * space is by destroying unwanted objects. We can't randomly release
1994 * mmap_offsets as userspace expects them to be persistent for the
1995 * lifetime of the objects. The closest we can is to release the
1996 * offsets on purgeable objects by truncating it and marking it purged,
1997 * which prevents userspace from ever using that object again.
1999 i915_gem_shrink(dev_priv
,
2000 obj
->base
.size
>> PAGE_SHIFT
,
2002 I915_SHRINK_UNBOUND
|
2003 I915_SHRINK_PURGEABLE
);
2004 ret
= drm_gem_create_mmap_offset(&obj
->base
);
2008 i915_gem_shrink_all(dev_priv
);
2009 ret
= drm_gem_create_mmap_offset(&obj
->base
);
2011 dev_priv
->mm
.shrinker_no_lock_stealing
= false;
2016 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object
*obj
)
2018 drm_gem_free_mmap_offset(&obj
->base
);
2022 i915_gem_mmap_gtt(struct drm_file
*file
,
2023 struct drm_device
*dev
,
2027 struct drm_i915_gem_object
*obj
;
2030 ret
= i915_mutex_lock_interruptible(dev
);
2034 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, handle
));
2035 if (&obj
->base
== NULL
) {
2040 if (obj
->madv
!= I915_MADV_WILLNEED
) {
2041 DRM_DEBUG("Attempting to mmap a purgeable buffer\n");
2046 ret
= i915_gem_object_create_mmap_offset(obj
);
2050 *offset
= drm_vma_node_offset_addr(&obj
->base
.vma_node
);
2053 drm_gem_object_unreference(&obj
->base
);
2055 mutex_unlock(&dev
->struct_mutex
);
2060 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
2062 * @data: GTT mapping ioctl data
2063 * @file: GEM object info
2065 * Simply returns the fake offset to userspace so it can mmap it.
2066 * The mmap call will end up in drm_gem_mmap(), which will set things
2067 * up so we can get faults in the handler above.
2069 * The fault handler will take care of binding the object into the GTT
2070 * (since it may have been evicted to make room for something), allocating
2071 * a fence register, and mapping the appropriate aperture address into
2075 i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
2076 struct drm_file
*file
)
2078 struct drm_i915_gem_mmap_gtt
*args
= data
;
2080 return i915_gem_mmap_gtt(file
, dev
, args
->handle
, &args
->offset
);
2083 /* Immediately discard the backing storage */
2085 i915_gem_object_truncate(struct drm_i915_gem_object
*obj
)
2087 i915_gem_object_free_mmap_offset(obj
);
2089 if (obj
->base
.filp
== NULL
)
2092 /* Our goal here is to return as much of the memory as
2093 * is possible back to the system as we are called from OOM.
2094 * To do this we must instruct the shmfs to drop all of its
2095 * backing pages, *now*.
2097 shmem_truncate_range(file_inode(obj
->base
.filp
), 0, (loff_t
)-1);
2098 obj
->madv
= __I915_MADV_PURGED
;
2101 /* Try to discard unwanted pages */
2103 i915_gem_object_invalidate(struct drm_i915_gem_object
*obj
)
2105 struct address_space
*mapping
;
2107 switch (obj
->madv
) {
2108 case I915_MADV_DONTNEED
:
2109 i915_gem_object_truncate(obj
);
2110 case __I915_MADV_PURGED
:
2114 if (obj
->base
.filp
== NULL
)
2117 mapping
= file_inode(obj
->base
.filp
)->i_mapping
,
2118 invalidate_mapping_pages(mapping
, 0, (loff_t
)-1);
2122 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object
*obj
)
2124 struct sg_page_iter sg_iter
;
2127 BUG_ON(obj
->madv
== __I915_MADV_PURGED
);
2129 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
2131 /* In the event of a disaster, abandon all caches and
2132 * hope for the best.
2134 WARN_ON(ret
!= -EIO
);
2135 i915_gem_clflush_object(obj
, true);
2136 obj
->base
.read_domains
= obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
2139 if (i915_gem_object_needs_bit17_swizzle(obj
))
2140 i915_gem_object_save_bit_17_swizzle(obj
);
2142 if (obj
->madv
== I915_MADV_DONTNEED
)
2145 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
, 0) {
2146 struct page
*page
= sg_page_iter_page(&sg_iter
);
2149 set_page_dirty(page
);
2151 if (obj
->madv
== I915_MADV_WILLNEED
)
2152 mark_page_accessed(page
);
2154 page_cache_release(page
);
2158 sg_free_table(obj
->pages
);
2163 i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
)
2165 const struct drm_i915_gem_object_ops
*ops
= obj
->ops
;
2167 if (obj
->pages
== NULL
)
2170 if (obj
->pages_pin_count
)
2173 BUG_ON(i915_gem_obj_bound_any(obj
));
2175 /* ->put_pages might need to allocate memory for the bit17 swizzle
2176 * array, hence protect them from being reaped by removing them from gtt
2178 list_del(&obj
->global_list
);
2180 ops
->put_pages(obj
);
2183 i915_gem_object_invalidate(obj
);
2189 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object
*obj
)
2191 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2193 struct address_space
*mapping
;
2194 struct sg_table
*st
;
2195 struct scatterlist
*sg
;
2196 struct sg_page_iter sg_iter
;
2198 unsigned long last_pfn
= 0; /* suppress gcc warning */
2201 /* Assert that the object is not currently in any GPU domain. As it
2202 * wasn't in the GTT, there shouldn't be any way it could have been in
2205 BUG_ON(obj
->base
.read_domains
& I915_GEM_GPU_DOMAINS
);
2206 BUG_ON(obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
);
2208 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
2212 page_count
= obj
->base
.size
/ PAGE_SIZE
;
2213 if (sg_alloc_table(st
, page_count
, GFP_KERNEL
)) {
2218 /* Get the list of pages out of our struct file. They'll be pinned
2219 * at this point until we release them.
2221 * Fail silently without starting the shrinker
2223 mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
2224 gfp
= mapping_gfp_mask(mapping
);
2225 gfp
|= __GFP_NORETRY
| __GFP_NOWARN
| __GFP_NO_KSWAPD
;
2226 gfp
&= ~(__GFP_IO
| __GFP_WAIT
);
2229 for (i
= 0; i
< page_count
; i
++) {
2230 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
2232 i915_gem_shrink(dev_priv
,
2235 I915_SHRINK_UNBOUND
|
2236 I915_SHRINK_PURGEABLE
);
2237 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
2240 /* We've tried hard to allocate the memory by reaping
2241 * our own buffer, now let the real VM do its job and
2242 * go down in flames if truly OOM.
2244 i915_gem_shrink_all(dev_priv
);
2245 page
= shmem_read_mapping_page(mapping
, i
);
2249 #ifdef CONFIG_SWIOTLB
2250 if (swiotlb_nr_tbl()) {
2252 sg_set_page(sg
, page
, PAGE_SIZE
, 0);
2257 if (!i
|| page_to_pfn(page
) != last_pfn
+ 1) {
2261 sg_set_page(sg
, page
, PAGE_SIZE
, 0);
2263 sg
->length
+= PAGE_SIZE
;
2265 last_pfn
= page_to_pfn(page
);
2267 /* Check that the i965g/gm workaround works. */
2268 WARN_ON((gfp
& __GFP_DMA32
) && (last_pfn
>= 0x00100000UL
));
2270 #ifdef CONFIG_SWIOTLB
2271 if (!swiotlb_nr_tbl())
2276 if (i915_gem_object_needs_bit17_swizzle(obj
))
2277 i915_gem_object_do_bit_17_swizzle(obj
);
2279 if (obj
->tiling_mode
!= I915_TILING_NONE
&&
2280 dev_priv
->quirks
& QUIRK_PIN_SWIZZLED_PAGES
)
2281 i915_gem_object_pin_pages(obj
);
2287 for_each_sg_page(st
->sgl
, &sg_iter
, st
->nents
, 0)
2288 page_cache_release(sg_page_iter_page(&sg_iter
));
2292 /* shmemfs first checks if there is enough memory to allocate the page
2293 * and reports ENOSPC should there be insufficient, along with the usual
2294 * ENOMEM for a genuine allocation failure.
2296 * We use ENOSPC in our driver to mean that we have run out of aperture
2297 * space and so want to translate the error from shmemfs back to our
2298 * usual understanding of ENOMEM.
2300 if (PTR_ERR(page
) == -ENOSPC
)
2303 return PTR_ERR(page
);
2306 /* Ensure that the associated pages are gathered from the backing storage
2307 * and pinned into our object. i915_gem_object_get_pages() may be called
2308 * multiple times before they are released by a single call to
2309 * i915_gem_object_put_pages() - once the pages are no longer referenced
2310 * either as a result of memory pressure (reaping pages under the shrinker)
2311 * or as the object is itself released.
2314 i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
)
2316 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2317 const struct drm_i915_gem_object_ops
*ops
= obj
->ops
;
2323 if (obj
->madv
!= I915_MADV_WILLNEED
) {
2324 DRM_DEBUG("Attempting to obtain a purgeable object\n");
2328 BUG_ON(obj
->pages_pin_count
);
2330 ret
= ops
->get_pages(obj
);
2334 list_add_tail(&obj
->global_list
, &dev_priv
->mm
.unbound_list
);
2336 obj
->get_page
.sg
= obj
->pages
->sgl
;
2337 obj
->get_page
.last
= 0;
2342 void i915_vma_move_to_active(struct i915_vma
*vma
,
2343 struct drm_i915_gem_request
*req
)
2345 struct drm_i915_gem_object
*obj
= vma
->obj
;
2346 struct intel_engine_cs
*ring
;
2348 ring
= i915_gem_request_get_ring(req
);
2350 /* Add a reference if we're newly entering the active list. */
2351 if (obj
->active
== 0)
2352 drm_gem_object_reference(&obj
->base
);
2353 obj
->active
|= intel_ring_flag(ring
);
2355 list_move_tail(&obj
->ring_list
[ring
->id
], &ring
->active_list
);
2356 i915_gem_request_assign(&obj
->last_read_req
[ring
->id
], req
);
2358 list_move_tail(&vma
->mm_list
, &vma
->vm
->active_list
);
2362 i915_gem_object_retire__write(struct drm_i915_gem_object
*obj
)
2364 RQ_BUG_ON(obj
->last_write_req
== NULL
);
2365 RQ_BUG_ON(!(obj
->active
& intel_ring_flag(obj
->last_write_req
->ring
)));
2367 i915_gem_request_assign(&obj
->last_write_req
, NULL
);
2368 intel_fb_obj_flush(obj
, true);
2372 i915_gem_object_retire__read(struct drm_i915_gem_object
*obj
, int ring
)
2374 struct i915_vma
*vma
;
2376 RQ_BUG_ON(obj
->last_read_req
[ring
] == NULL
);
2377 RQ_BUG_ON(!(obj
->active
& (1 << ring
)));
2379 list_del_init(&obj
->ring_list
[ring
]);
2380 i915_gem_request_assign(&obj
->last_read_req
[ring
], NULL
);
2382 if (obj
->last_write_req
&& obj
->last_write_req
->ring
->id
== ring
)
2383 i915_gem_object_retire__write(obj
);
2385 obj
->active
&= ~(1 << ring
);
2389 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
) {
2390 if (!list_empty(&vma
->mm_list
))
2391 list_move_tail(&vma
->mm_list
, &vma
->vm
->inactive_list
);
2394 i915_gem_request_assign(&obj
->last_fenced_req
, NULL
);
2395 drm_gem_object_unreference(&obj
->base
);
2399 i915_gem_init_seqno(struct drm_device
*dev
, u32 seqno
)
2401 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2402 struct intel_engine_cs
*ring
;
2405 /* Carefully retire all requests without writing to the rings */
2406 for_each_ring(ring
, dev_priv
, i
) {
2407 ret
= intel_ring_idle(ring
);
2411 i915_gem_retire_requests(dev
);
2413 /* Finally reset hw state */
2414 for_each_ring(ring
, dev_priv
, i
) {
2415 intel_ring_init_seqno(ring
, seqno
);
2417 for (j
= 0; j
< ARRAY_SIZE(ring
->semaphore
.sync_seqno
); j
++)
2418 ring
->semaphore
.sync_seqno
[j
] = 0;
2424 int i915_gem_set_seqno(struct drm_device
*dev
, u32 seqno
)
2426 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2432 /* HWS page needs to be set less than what we
2433 * will inject to ring
2435 ret
= i915_gem_init_seqno(dev
, seqno
- 1);
2439 /* Carefully set the last_seqno value so that wrap
2440 * detection still works
2442 dev_priv
->next_seqno
= seqno
;
2443 dev_priv
->last_seqno
= seqno
- 1;
2444 if (dev_priv
->last_seqno
== 0)
2445 dev_priv
->last_seqno
--;
2451 i915_gem_get_seqno(struct drm_device
*dev
, u32
*seqno
)
2453 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2455 /* reserve 0 for non-seqno */
2456 if (dev_priv
->next_seqno
== 0) {
2457 int ret
= i915_gem_init_seqno(dev
, 0);
2461 dev_priv
->next_seqno
= 1;
2464 *seqno
= dev_priv
->last_seqno
= dev_priv
->next_seqno
++;
2469 * NB: This function is not allowed to fail. Doing so would mean the the
2470 * request is not being tracked for completion but the work itself is
2471 * going to happen on the hardware. This would be a Bad Thing(tm).
2473 void __i915_add_request(struct drm_i915_gem_request
*request
,
2474 struct drm_file
*file
,
2475 struct drm_i915_gem_object
*obj
,
2478 struct intel_engine_cs
*ring
;
2479 struct drm_i915_private
*dev_priv
;
2480 struct intel_ringbuffer
*ringbuf
;
2484 if (WARN_ON(request
== NULL
))
2487 ring
= request
->ring
;
2488 dev_priv
= ring
->dev
->dev_private
;
2489 ringbuf
= request
->ringbuf
;
2491 WARN_ON(request
!= ring
->outstanding_lazy_request
);
2494 * To ensure that this call will not fail, space for its emissions
2495 * should already have been reserved in the ring buffer. Let the ring
2496 * know that it is time to use that space up.
2498 intel_ring_reserved_space_use(ringbuf
);
2500 request_start
= intel_ring_get_tail(ringbuf
);
2502 * Emit any outstanding flushes - execbuf can fail to emit the flush
2503 * after having emitted the batchbuffer command. Hence we need to fix
2504 * things up similar to emitting the lazy request. The difference here
2505 * is that the flush _must_ happen before the next request, no matter
2509 if (i915
.enable_execlists
)
2510 ret
= logical_ring_flush_all_caches(request
);
2512 ret
= intel_ring_flush_all_caches(request
);
2513 /* Not allowed to fail! */
2514 WARN(ret
, "*_ring_flush_all_caches failed: %d!\n", ret
);
2517 /* Record the position of the start of the request so that
2518 * should we detect the updated seqno part-way through the
2519 * GPU processing the request, we never over-estimate the
2520 * position of the head.
2522 request
->postfix
= intel_ring_get_tail(ringbuf
);
2524 if (i915
.enable_execlists
)
2525 ret
= ring
->emit_request(request
);
2527 ret
= ring
->add_request(request
);
2529 request
->tail
= intel_ring_get_tail(ringbuf
);
2531 /* Not allowed to fail! */
2532 WARN(ret
, "emit|add_request failed: %d!\n", ret
);
2534 request
->head
= request_start
;
2536 /* Whilst this request exists, batch_obj will be on the
2537 * active_list, and so will hold the active reference. Only when this
2538 * request is retired will the the batch_obj be moved onto the
2539 * inactive_list and lose its active reference. Hence we do not need
2540 * to explicitly hold another reference here.
2542 request
->batch_obj
= obj
;
2544 request
->emitted_jiffies
= jiffies
;
2545 list_add_tail(&request
->list
, &ring
->request_list
);
2546 request
->file_priv
= NULL
;
2549 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
2551 spin_lock(&file_priv
->mm
.lock
);
2552 request
->file_priv
= file_priv
;
2553 list_add_tail(&request
->client_list
,
2554 &file_priv
->mm
.request_list
);
2555 spin_unlock(&file_priv
->mm
.lock
);
2557 request
->pid
= get_pid(task_pid(current
));
2560 trace_i915_gem_request_add(request
);
2561 ring
->outstanding_lazy_request
= NULL
;
2563 i915_queue_hangcheck(ring
->dev
);
2565 queue_delayed_work(dev_priv
->wq
,
2566 &dev_priv
->mm
.retire_work
,
2567 round_jiffies_up_relative(HZ
));
2568 intel_mark_busy(dev_priv
->dev
);
2570 /* Sanity check that the reserved size was large enough. */
2571 intel_ring_reserved_space_end(ringbuf
);
2574 static bool i915_context_is_banned(struct drm_i915_private
*dev_priv
,
2575 const struct intel_context
*ctx
)
2577 unsigned long elapsed
;
2579 elapsed
= get_seconds() - ctx
->hang_stats
.guilty_ts
;
2581 if (ctx
->hang_stats
.banned
)
2584 if (ctx
->hang_stats
.ban_period_seconds
&&
2585 elapsed
<= ctx
->hang_stats
.ban_period_seconds
) {
2586 if (!i915_gem_context_is_default(ctx
)) {
2587 DRM_DEBUG("context hanging too fast, banning!\n");
2589 } else if (i915_stop_ring_allow_ban(dev_priv
)) {
2590 if (i915_stop_ring_allow_warn(dev_priv
))
2591 DRM_ERROR("gpu hanging too fast, banning!\n");
2599 static void i915_set_reset_status(struct drm_i915_private
*dev_priv
,
2600 struct intel_context
*ctx
,
2603 struct i915_ctx_hang_stats
*hs
;
2608 hs
= &ctx
->hang_stats
;
2611 hs
->banned
= i915_context_is_banned(dev_priv
, ctx
);
2613 hs
->guilty_ts
= get_seconds();
2615 hs
->batch_pending
++;
2619 void i915_gem_request_free(struct kref
*req_ref
)
2621 struct drm_i915_gem_request
*req
= container_of(req_ref
,
2623 struct intel_context
*ctx
= req
->ctx
;
2626 if (i915
.enable_execlists
) {
2627 struct intel_engine_cs
*ring
= req
->ring
;
2629 if (ctx
!= ring
->default_context
)
2630 intel_lr_context_unpin(ring
, ctx
);
2633 i915_gem_context_unreference(ctx
);
2636 kmem_cache_free(req
->i915
->requests
, req
);
2639 int i915_gem_request_alloc(struct intel_engine_cs
*ring
,
2640 struct intel_context
*ctx
,
2641 struct drm_i915_gem_request
**req_out
)
2643 struct drm_i915_private
*dev_priv
= to_i915(ring
->dev
);
2644 struct drm_i915_gem_request
*req
;
2650 if ((*req_out
= ring
->outstanding_lazy_request
) != NULL
)
2653 req
= kmem_cache_zalloc(dev_priv
->requests
, GFP_KERNEL
);
2657 ret
= i915_gem_get_seqno(ring
->dev
, &req
->seqno
);
2661 kref_init(&req
->ref
);
2662 req
->i915
= dev_priv
;
2665 i915_gem_context_reference(req
->ctx
);
2667 if (i915
.enable_execlists
)
2668 ret
= intel_logical_ring_alloc_request_extras(req
);
2670 ret
= intel_ring_alloc_request_extras(req
);
2672 i915_gem_context_unreference(req
->ctx
);
2677 * Reserve space in the ring buffer for all the commands required to
2678 * eventually emit this request. This is to guarantee that the
2679 * i915_add_request() call can't fail. Note that the reserve may need
2680 * to be redone if the request is not actually submitted straight
2681 * away, e.g. because a GPU scheduler has deferred it.
2683 if (i915
.enable_execlists
)
2684 ret
= intel_logical_ring_reserve_space(req
);
2686 ret
= intel_ring_reserve_space(req
);
2689 * At this point, the request is fully allocated even if not
2690 * fully prepared. Thus it can be cleaned up using the proper
2693 i915_gem_request_cancel(req
);
2697 *req_out
= ring
->outstanding_lazy_request
= req
;
2701 kmem_cache_free(dev_priv
->requests
, req
);
2705 void i915_gem_request_cancel(struct drm_i915_gem_request
*req
)
2707 intel_ring_reserved_space_cancel(req
->ringbuf
);
2709 i915_gem_request_unreference(req
);
2712 struct drm_i915_gem_request
*
2713 i915_gem_find_active_request(struct intel_engine_cs
*ring
)
2715 struct drm_i915_gem_request
*request
;
2717 list_for_each_entry(request
, &ring
->request_list
, list
) {
2718 if (i915_gem_request_completed(request
, false))
2727 static void i915_gem_reset_ring_status(struct drm_i915_private
*dev_priv
,
2728 struct intel_engine_cs
*ring
)
2730 struct drm_i915_gem_request
*request
;
2733 request
= i915_gem_find_active_request(ring
);
2735 if (request
== NULL
)
2738 ring_hung
= ring
->hangcheck
.score
>= HANGCHECK_SCORE_RING_HUNG
;
2740 i915_set_reset_status(dev_priv
, request
->ctx
, ring_hung
);
2742 list_for_each_entry_continue(request
, &ring
->request_list
, list
)
2743 i915_set_reset_status(dev_priv
, request
->ctx
, false);
2746 static void i915_gem_reset_ring_cleanup(struct drm_i915_private
*dev_priv
,
2747 struct intel_engine_cs
*ring
)
2749 while (!list_empty(&ring
->active_list
)) {
2750 struct drm_i915_gem_object
*obj
;
2752 obj
= list_first_entry(&ring
->active_list
,
2753 struct drm_i915_gem_object
,
2754 ring_list
[ring
->id
]);
2756 i915_gem_object_retire__read(obj
, ring
->id
);
2760 * Clear the execlists queue up before freeing the requests, as those
2761 * are the ones that keep the context and ringbuffer backing objects
2764 while (!list_empty(&ring
->execlist_queue
)) {
2765 struct drm_i915_gem_request
*submit_req
;
2767 submit_req
= list_first_entry(&ring
->execlist_queue
,
2768 struct drm_i915_gem_request
,
2770 list_del(&submit_req
->execlist_link
);
2772 if (submit_req
->ctx
!= ring
->default_context
)
2773 intel_lr_context_unpin(ring
, submit_req
->ctx
);
2775 i915_gem_request_unreference(submit_req
);
2779 * We must free the requests after all the corresponding objects have
2780 * been moved off active lists. Which is the same order as the normal
2781 * retire_requests function does. This is important if object hold
2782 * implicit references on things like e.g. ppgtt address spaces through
2785 while (!list_empty(&ring
->request_list
)) {
2786 struct drm_i915_gem_request
*request
;
2788 request
= list_first_entry(&ring
->request_list
,
2789 struct drm_i915_gem_request
,
2792 i915_gem_request_retire(request
);
2795 /* This may not have been flushed before the reset, so clean it now */
2796 i915_gem_request_assign(&ring
->outstanding_lazy_request
, NULL
);
2799 void i915_gem_restore_fences(struct drm_device
*dev
)
2801 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2804 for (i
= 0; i
< dev_priv
->num_fence_regs
; i
++) {
2805 struct drm_i915_fence_reg
*reg
= &dev_priv
->fence_regs
[i
];
2808 * Commit delayed tiling changes if we have an object still
2809 * attached to the fence, otherwise just clear the fence.
2812 i915_gem_object_update_fence(reg
->obj
, reg
,
2813 reg
->obj
->tiling_mode
);
2815 i915_gem_write_fence(dev
, i
, NULL
);
2820 void i915_gem_reset(struct drm_device
*dev
)
2822 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2823 struct intel_engine_cs
*ring
;
2827 * Before we free the objects from the requests, we need to inspect
2828 * them for finding the guilty party. As the requests only borrow
2829 * their reference to the objects, the inspection must be done first.
2831 for_each_ring(ring
, dev_priv
, i
)
2832 i915_gem_reset_ring_status(dev_priv
, ring
);
2834 for_each_ring(ring
, dev_priv
, i
)
2835 i915_gem_reset_ring_cleanup(dev_priv
, ring
);
2837 i915_gem_context_reset(dev
);
2839 i915_gem_restore_fences(dev
);
2841 WARN_ON(i915_verify_lists(dev
));
2845 * This function clears the request list as sequence numbers are passed.
2848 i915_gem_retire_requests_ring(struct intel_engine_cs
*ring
)
2850 WARN_ON(i915_verify_lists(ring
->dev
));
2852 /* Retire requests first as we use it above for the early return.
2853 * If we retire requests last, we may use a later seqno and so clear
2854 * the requests lists without clearing the active list, leading to
2857 while (!list_empty(&ring
->request_list
)) {
2858 struct drm_i915_gem_request
*request
;
2860 request
= list_first_entry(&ring
->request_list
,
2861 struct drm_i915_gem_request
,
2864 if (!i915_gem_request_completed(request
, true))
2867 i915_gem_request_retire(request
);
2870 /* Move any buffers on the active list that are no longer referenced
2871 * by the ringbuffer to the flushing/inactive lists as appropriate,
2872 * before we free the context associated with the requests.
2874 while (!list_empty(&ring
->active_list
)) {
2875 struct drm_i915_gem_object
*obj
;
2877 obj
= list_first_entry(&ring
->active_list
,
2878 struct drm_i915_gem_object
,
2879 ring_list
[ring
->id
]);
2881 if (!list_empty(&obj
->last_read_req
[ring
->id
]->list
))
2884 i915_gem_object_retire__read(obj
, ring
->id
);
2887 if (unlikely(ring
->trace_irq_req
&&
2888 i915_gem_request_completed(ring
->trace_irq_req
, true))) {
2889 ring
->irq_put(ring
);
2890 i915_gem_request_assign(&ring
->trace_irq_req
, NULL
);
2893 WARN_ON(i915_verify_lists(ring
->dev
));
2897 i915_gem_retire_requests(struct drm_device
*dev
)
2899 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2900 struct intel_engine_cs
*ring
;
2904 for_each_ring(ring
, dev_priv
, i
) {
2905 i915_gem_retire_requests_ring(ring
);
2906 idle
&= list_empty(&ring
->request_list
);
2907 if (i915
.enable_execlists
) {
2908 unsigned long flags
;
2910 spin_lock_irqsave(&ring
->execlist_lock
, flags
);
2911 idle
&= list_empty(&ring
->execlist_queue
);
2912 spin_unlock_irqrestore(&ring
->execlist_lock
, flags
);
2914 intel_execlists_retire_requests(ring
);
2919 mod_delayed_work(dev_priv
->wq
,
2920 &dev_priv
->mm
.idle_work
,
2921 msecs_to_jiffies(100));
2927 i915_gem_retire_work_handler(struct work_struct
*work
)
2929 struct drm_i915_private
*dev_priv
=
2930 container_of(work
, typeof(*dev_priv
), mm
.retire_work
.work
);
2931 struct drm_device
*dev
= dev_priv
->dev
;
2934 /* Come back later if the device is busy... */
2936 if (mutex_trylock(&dev
->struct_mutex
)) {
2937 idle
= i915_gem_retire_requests(dev
);
2938 mutex_unlock(&dev
->struct_mutex
);
2941 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
,
2942 round_jiffies_up_relative(HZ
));
2946 i915_gem_idle_work_handler(struct work_struct
*work
)
2948 struct drm_i915_private
*dev_priv
=
2949 container_of(work
, typeof(*dev_priv
), mm
.idle_work
.work
);
2950 struct drm_device
*dev
= dev_priv
->dev
;
2951 struct intel_engine_cs
*ring
;
2954 for_each_ring(ring
, dev_priv
, i
)
2955 if (!list_empty(&ring
->request_list
))
2958 intel_mark_idle(dev
);
2960 if (mutex_trylock(&dev
->struct_mutex
)) {
2961 struct intel_engine_cs
*ring
;
2964 for_each_ring(ring
, dev_priv
, i
)
2965 i915_gem_batch_pool_fini(&ring
->batch_pool
);
2967 mutex_unlock(&dev
->struct_mutex
);
2972 * Ensures that an object will eventually get non-busy by flushing any required
2973 * write domains, emitting any outstanding lazy request and retiring and
2974 * completed requests.
2977 i915_gem_object_flush_active(struct drm_i915_gem_object
*obj
)
2984 for (i
= 0; i
< I915_NUM_RINGS
; i
++) {
2985 struct drm_i915_gem_request
*req
;
2987 req
= obj
->last_read_req
[i
];
2991 if (list_empty(&req
->list
))
2994 ret
= i915_gem_check_olr(req
);
2998 if (i915_gem_request_completed(req
, true)) {
2999 __i915_gem_request_retire__upto(req
);
3001 i915_gem_object_retire__read(obj
, i
);
3009 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
3010 * @DRM_IOCTL_ARGS: standard ioctl arguments
3012 * Returns 0 if successful, else an error is returned with the remaining time in
3013 * the timeout parameter.
3014 * -ETIME: object is still busy after timeout
3015 * -ERESTARTSYS: signal interrupted the wait
3016 * -ENONENT: object doesn't exist
3017 * Also possible, but rare:
3018 * -EAGAIN: GPU wedged
3020 * -ENODEV: Internal IRQ fail
3021 * -E?: The add request failed
3023 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
3024 * non-zero timeout parameter the wait ioctl will wait for the given number of
3025 * nanoseconds on an object becoming unbusy. Since the wait itself does so
3026 * without holding struct_mutex the object may become re-busied before this
3027 * function completes. A similar but shorter * race condition exists in the busy
3031 i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
, struct drm_file
*file
)
3033 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3034 struct drm_i915_gem_wait
*args
= data
;
3035 struct drm_i915_gem_object
*obj
;
3036 struct drm_i915_gem_request
*req
[I915_NUM_RINGS
];
3037 unsigned reset_counter
;
3041 if (args
->flags
!= 0)
3044 ret
= i915_mutex_lock_interruptible(dev
);
3048 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->bo_handle
));
3049 if (&obj
->base
== NULL
) {
3050 mutex_unlock(&dev
->struct_mutex
);
3054 /* Need to make sure the object gets inactive eventually. */
3055 ret
= i915_gem_object_flush_active(obj
);
3062 /* Do this after OLR check to make sure we make forward progress polling
3063 * on this IOCTL with a timeout == 0 (like busy ioctl)
3065 if (args
->timeout_ns
== 0) {
3070 drm_gem_object_unreference(&obj
->base
);
3071 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
3073 for (i
= 0; i
< I915_NUM_RINGS
; i
++) {
3074 if (obj
->last_read_req
[i
] == NULL
)
3077 req
[n
++] = i915_gem_request_reference(obj
->last_read_req
[i
]);
3080 mutex_unlock(&dev
->struct_mutex
);
3082 for (i
= 0; i
< n
; i
++) {
3084 ret
= __i915_wait_request(req
[i
], reset_counter
, true,
3085 args
->timeout_ns
> 0 ? &args
->timeout_ns
: NULL
,
3087 i915_gem_request_unreference__unlocked(req
[i
]);
3092 drm_gem_object_unreference(&obj
->base
);
3093 mutex_unlock(&dev
->struct_mutex
);
3098 __i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
3099 struct intel_engine_cs
*to
,
3100 struct drm_i915_gem_request
*from_req
,
3101 struct drm_i915_gem_request
**to_req
)
3103 struct intel_engine_cs
*from
;
3106 from
= i915_gem_request_get_ring(from_req
);
3110 if (i915_gem_request_completed(from_req
, true))
3113 ret
= i915_gem_check_olr(from_req
);
3117 if (!i915_semaphore_is_enabled(obj
->base
.dev
)) {
3118 struct drm_i915_private
*i915
= to_i915(obj
->base
.dev
);
3119 ret
= __i915_wait_request(from_req
,
3120 atomic_read(&i915
->gpu_error
.reset_counter
),
3121 i915
->mm
.interruptible
,
3123 &i915
->rps
.semaphores
);
3127 i915_gem_object_retire_request(obj
, from_req
);
3129 int idx
= intel_ring_sync_index(from
, to
);
3130 u32 seqno
= i915_gem_request_get_seqno(from_req
);
3134 if (seqno
<= from
->semaphore
.sync_seqno
[idx
])
3137 if (*to_req
== NULL
) {
3138 ret
= i915_gem_request_alloc(to
, to
->default_context
, to_req
);
3143 trace_i915_gem_ring_sync_to(*to_req
, from
, from_req
);
3144 ret
= to
->semaphore
.sync_to(*to_req
, from
, seqno
);
3148 /* We use last_read_req because sync_to()
3149 * might have just caused seqno wrap under
3152 from
->semaphore
.sync_seqno
[idx
] =
3153 i915_gem_request_get_seqno(obj
->last_read_req
[from
->id
]);
3160 * i915_gem_object_sync - sync an object to a ring.
3162 * @obj: object which may be in use on another ring.
3163 * @to: ring we wish to use the object on. May be NULL.
3164 * @to_req: request we wish to use the object for. See below.
3165 * This will be allocated and returned if a request is
3166 * required but not passed in.
3168 * This code is meant to abstract object synchronization with the GPU.
3169 * Calling with NULL implies synchronizing the object with the CPU
3170 * rather than a particular GPU ring. Conceptually we serialise writes
3171 * between engines inside the GPU. We only allow one engine to write
3172 * into a buffer at any time, but multiple readers. To ensure each has
3173 * a coherent view of memory, we must:
3175 * - If there is an outstanding write request to the object, the new
3176 * request must wait for it to complete (either CPU or in hw, requests
3177 * on the same ring will be naturally ordered).
3179 * - If we are a write request (pending_write_domain is set), the new
3180 * request must wait for outstanding read requests to complete.
3182 * For CPU synchronisation (NULL to) no request is required. For syncing with
3183 * rings to_req must be non-NULL. However, a request does not have to be
3184 * pre-allocated. If *to_req is NULL and sync commands will be emitted then a
3185 * request will be allocated automatically and returned through *to_req. Note
3186 * that it is not guaranteed that commands will be emitted (because the system
3187 * might already be idle). Hence there is no need to create a request that
3188 * might never have any work submitted. Note further that if a request is
3189 * returned in *to_req, it is the responsibility of the caller to submit
3190 * that request (after potentially adding more work to it).
3192 * Returns 0 if successful, else propagates up the lower layer error.
3195 i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
3196 struct intel_engine_cs
*to
,
3197 struct drm_i915_gem_request
**to_req
)
3199 const bool readonly
= obj
->base
.pending_write_domain
== 0;
3200 struct drm_i915_gem_request
*req
[I915_NUM_RINGS
];
3207 return i915_gem_object_wait_rendering(obj
, readonly
);
3211 if (obj
->last_write_req
)
3212 req
[n
++] = obj
->last_write_req
;
3214 for (i
= 0; i
< I915_NUM_RINGS
; i
++)
3215 if (obj
->last_read_req
[i
])
3216 req
[n
++] = obj
->last_read_req
[i
];
3218 for (i
= 0; i
< n
; i
++) {
3219 ret
= __i915_gem_object_sync(obj
, to
, req
[i
], to_req
);
3227 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object
*obj
)
3229 u32 old_write_domain
, old_read_domains
;
3231 /* Force a pagefault for domain tracking on next user access */
3232 i915_gem_release_mmap(obj
);
3234 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
) == 0)
3237 /* Wait for any direct GTT access to complete */
3240 old_read_domains
= obj
->base
.read_domains
;
3241 old_write_domain
= obj
->base
.write_domain
;
3243 obj
->base
.read_domains
&= ~I915_GEM_DOMAIN_GTT
;
3244 obj
->base
.write_domain
&= ~I915_GEM_DOMAIN_GTT
;
3246 trace_i915_gem_object_change_domain(obj
,
3251 int i915_vma_unbind(struct i915_vma
*vma
)
3253 struct drm_i915_gem_object
*obj
= vma
->obj
;
3254 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
3257 if (list_empty(&vma
->vma_link
))
3260 if (!drm_mm_node_allocated(&vma
->node
)) {
3261 i915_gem_vma_destroy(vma
);
3268 BUG_ON(obj
->pages
== NULL
);
3270 ret
= i915_gem_object_wait_rendering(obj
, false);
3273 /* Continue on if we fail due to EIO, the GPU is hung so we
3274 * should be safe and we need to cleanup or else we might
3275 * cause memory corruption through use-after-free.
3278 if (i915_is_ggtt(vma
->vm
) &&
3279 vma
->ggtt_view
.type
== I915_GGTT_VIEW_NORMAL
) {
3280 i915_gem_object_finish_gtt(obj
);
3282 /* release the fence reg _after_ flushing */
3283 ret
= i915_gem_object_put_fence(obj
);
3288 trace_i915_vma_unbind(vma
);
3290 vma
->vm
->unbind_vma(vma
);
3293 list_del_init(&vma
->mm_list
);
3294 if (i915_is_ggtt(vma
->vm
)) {
3295 if (vma
->ggtt_view
.type
== I915_GGTT_VIEW_NORMAL
) {
3296 obj
->map_and_fenceable
= false;
3297 } else if (vma
->ggtt_view
.pages
) {
3298 sg_free_table(vma
->ggtt_view
.pages
);
3299 kfree(vma
->ggtt_view
.pages
);
3300 vma
->ggtt_view
.pages
= NULL
;
3304 drm_mm_remove_node(&vma
->node
);
3305 i915_gem_vma_destroy(vma
);
3307 /* Since the unbound list is global, only move to that list if
3308 * no more VMAs exist. */
3309 if (list_empty(&obj
->vma_list
)) {
3310 i915_gem_gtt_finish_object(obj
);
3311 list_move_tail(&obj
->global_list
, &dev_priv
->mm
.unbound_list
);
3314 /* And finally now the object is completely decoupled from this vma,
3315 * we can drop its hold on the backing storage and allow it to be
3316 * reaped by the shrinker.
3318 i915_gem_object_unpin_pages(obj
);
3323 int i915_gpu_idle(struct drm_device
*dev
)
3325 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3326 struct intel_engine_cs
*ring
;
3329 /* Flush everything onto the inactive list. */
3330 for_each_ring(ring
, dev_priv
, i
) {
3331 if (!i915
.enable_execlists
) {
3332 struct drm_i915_gem_request
*req
;
3334 ret
= i915_gem_request_alloc(ring
, ring
->default_context
, &req
);
3338 ret
= i915_switch_context(req
);
3340 i915_gem_request_cancel(req
);
3344 i915_add_request_no_flush(req
);
3347 WARN_ON(ring
->outstanding_lazy_request
);
3349 ret
= intel_ring_idle(ring
);
3354 WARN_ON(i915_verify_lists(dev
));
3358 static void i965_write_fence_reg(struct drm_device
*dev
, int reg
,
3359 struct drm_i915_gem_object
*obj
)
3361 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3363 int fence_pitch_shift
;
3365 if (INTEL_INFO(dev
)->gen
>= 6) {
3366 fence_reg
= FENCE_REG_SANDYBRIDGE_0
;
3367 fence_pitch_shift
= SANDYBRIDGE_FENCE_PITCH_SHIFT
;
3369 fence_reg
= FENCE_REG_965_0
;
3370 fence_pitch_shift
= I965_FENCE_PITCH_SHIFT
;
3373 fence_reg
+= reg
* 8;
3375 /* To w/a incoherency with non-atomic 64-bit register updates,
3376 * we split the 64-bit update into two 32-bit writes. In order
3377 * for a partial fence not to be evaluated between writes, we
3378 * precede the update with write to turn off the fence register,
3379 * and only enable the fence as the last step.
3381 * For extra levels of paranoia, we make sure each step lands
3382 * before applying the next step.
3384 I915_WRITE(fence_reg
, 0);
3385 POSTING_READ(fence_reg
);
3388 u32 size
= i915_gem_obj_ggtt_size(obj
);
3391 /* Adjust fence size to match tiled area */
3392 if (obj
->tiling_mode
!= I915_TILING_NONE
) {
3393 uint32_t row_size
= obj
->stride
*
3394 (obj
->tiling_mode
== I915_TILING_Y
? 32 : 8);
3395 size
= (size
/ row_size
) * row_size
;
3398 val
= (uint64_t)((i915_gem_obj_ggtt_offset(obj
) + size
- 4096) &
3400 val
|= i915_gem_obj_ggtt_offset(obj
) & 0xfffff000;
3401 val
|= (uint64_t)((obj
->stride
/ 128) - 1) << fence_pitch_shift
;
3402 if (obj
->tiling_mode
== I915_TILING_Y
)
3403 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
3404 val
|= I965_FENCE_REG_VALID
;
3406 I915_WRITE(fence_reg
+ 4, val
>> 32);
3407 POSTING_READ(fence_reg
+ 4);
3409 I915_WRITE(fence_reg
+ 0, val
);
3410 POSTING_READ(fence_reg
);
3412 I915_WRITE(fence_reg
+ 4, 0);
3413 POSTING_READ(fence_reg
+ 4);
3417 static void i915_write_fence_reg(struct drm_device
*dev
, int reg
,
3418 struct drm_i915_gem_object
*obj
)
3420 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3424 u32 size
= i915_gem_obj_ggtt_size(obj
);
3428 WARN((i915_gem_obj_ggtt_offset(obj
) & ~I915_FENCE_START_MASK
) ||
3429 (size
& -size
) != size
||
3430 (i915_gem_obj_ggtt_offset(obj
) & (size
- 1)),
3431 "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
3432 i915_gem_obj_ggtt_offset(obj
), obj
->map_and_fenceable
, size
);
3434 if (obj
->tiling_mode
== I915_TILING_Y
&& HAS_128_BYTE_Y_TILING(dev
))
3439 /* Note: pitch better be a power of two tile widths */
3440 pitch_val
= obj
->stride
/ tile_width
;
3441 pitch_val
= ffs(pitch_val
) - 1;
3443 val
= i915_gem_obj_ggtt_offset(obj
);
3444 if (obj
->tiling_mode
== I915_TILING_Y
)
3445 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
3446 val
|= I915_FENCE_SIZE_BITS(size
);
3447 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
3448 val
|= I830_FENCE_REG_VALID
;
3453 reg
= FENCE_REG_830_0
+ reg
* 4;
3455 reg
= FENCE_REG_945_8
+ (reg
- 8) * 4;
3457 I915_WRITE(reg
, val
);
3461 static void i830_write_fence_reg(struct drm_device
*dev
, int reg
,
3462 struct drm_i915_gem_object
*obj
)
3464 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3468 u32 size
= i915_gem_obj_ggtt_size(obj
);
3471 WARN((i915_gem_obj_ggtt_offset(obj
) & ~I830_FENCE_START_MASK
) ||
3472 (size
& -size
) != size
||
3473 (i915_gem_obj_ggtt_offset(obj
) & (size
- 1)),
3474 "object 0x%08lx not 512K or pot-size 0x%08x aligned\n",
3475 i915_gem_obj_ggtt_offset(obj
), size
);
3477 pitch_val
= obj
->stride
/ 128;
3478 pitch_val
= ffs(pitch_val
) - 1;
3480 val
= i915_gem_obj_ggtt_offset(obj
);
3481 if (obj
->tiling_mode
== I915_TILING_Y
)
3482 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
3483 val
|= I830_FENCE_SIZE_BITS(size
);
3484 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
3485 val
|= I830_FENCE_REG_VALID
;
3489 I915_WRITE(FENCE_REG_830_0
+ reg
* 4, val
);
3490 POSTING_READ(FENCE_REG_830_0
+ reg
* 4);
3493 inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object
*obj
)
3495 return obj
&& obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
;
3498 static void i915_gem_write_fence(struct drm_device
*dev
, int reg
,
3499 struct drm_i915_gem_object
*obj
)
3501 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3503 /* Ensure that all CPU reads are completed before installing a fence
3504 * and all writes before removing the fence.
3506 if (i915_gem_object_needs_mb(dev_priv
->fence_regs
[reg
].obj
))
3509 WARN(obj
&& (!obj
->stride
|| !obj
->tiling_mode
),
3510 "bogus fence setup with stride: 0x%x, tiling mode: %i\n",
3511 obj
->stride
, obj
->tiling_mode
);
3514 i830_write_fence_reg(dev
, reg
, obj
);
3515 else if (IS_GEN3(dev
))
3516 i915_write_fence_reg(dev
, reg
, obj
);
3517 else if (INTEL_INFO(dev
)->gen
>= 4)
3518 i965_write_fence_reg(dev
, reg
, obj
);
3520 /* And similarly be paranoid that no direct access to this region
3521 * is reordered to before the fence is installed.
3523 if (i915_gem_object_needs_mb(obj
))
3527 static inline int fence_number(struct drm_i915_private
*dev_priv
,
3528 struct drm_i915_fence_reg
*fence
)
3530 return fence
- dev_priv
->fence_regs
;
3533 static void i915_gem_object_update_fence(struct drm_i915_gem_object
*obj
,
3534 struct drm_i915_fence_reg
*fence
,
3537 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
3538 int reg
= fence_number(dev_priv
, fence
);
3540 i915_gem_write_fence(obj
->base
.dev
, reg
, enable
? obj
: NULL
);
3543 obj
->fence_reg
= reg
;
3545 list_move_tail(&fence
->lru_list
, &dev_priv
->mm
.fence_list
);
3547 obj
->fence_reg
= I915_FENCE_REG_NONE
;
3549 list_del_init(&fence
->lru_list
);
3551 obj
->fence_dirty
= false;
3555 i915_gem_object_wait_fence(struct drm_i915_gem_object
*obj
)
3557 if (obj
->last_fenced_req
) {
3558 int ret
= i915_wait_request(obj
->last_fenced_req
);
3562 i915_gem_request_assign(&obj
->last_fenced_req
, NULL
);
3569 i915_gem_object_put_fence(struct drm_i915_gem_object
*obj
)
3571 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
3572 struct drm_i915_fence_reg
*fence
;
3575 ret
= i915_gem_object_wait_fence(obj
);
3579 if (obj
->fence_reg
== I915_FENCE_REG_NONE
)
3582 fence
= &dev_priv
->fence_regs
[obj
->fence_reg
];
3584 if (WARN_ON(fence
->pin_count
))
3587 i915_gem_object_fence_lost(obj
);
3588 i915_gem_object_update_fence(obj
, fence
, false);
3593 static struct drm_i915_fence_reg
*
3594 i915_find_fence_reg(struct drm_device
*dev
)
3596 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3597 struct drm_i915_fence_reg
*reg
, *avail
;
3600 /* First try to find a free reg */
3602 for (i
= dev_priv
->fence_reg_start
; i
< dev_priv
->num_fence_regs
; i
++) {
3603 reg
= &dev_priv
->fence_regs
[i
];
3607 if (!reg
->pin_count
)
3614 /* None available, try to steal one or wait for a user to finish */
3615 list_for_each_entry(reg
, &dev_priv
->mm
.fence_list
, lru_list
) {
3623 /* Wait for completion of pending flips which consume fences */
3624 if (intel_has_pending_fb_unpin(dev
))
3625 return ERR_PTR(-EAGAIN
);
3627 return ERR_PTR(-EDEADLK
);
3631 * i915_gem_object_get_fence - set up fencing for an object
3632 * @obj: object to map through a fence reg
3634 * When mapping objects through the GTT, userspace wants to be able to write
3635 * to them without having to worry about swizzling if the object is tiled.
3636 * This function walks the fence regs looking for a free one for @obj,
3637 * stealing one if it can't find any.
3639 * It then sets up the reg based on the object's properties: address, pitch
3640 * and tiling format.
3642 * For an untiled surface, this removes any existing fence.
3645 i915_gem_object_get_fence(struct drm_i915_gem_object
*obj
)
3647 struct drm_device
*dev
= obj
->base
.dev
;
3648 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3649 bool enable
= obj
->tiling_mode
!= I915_TILING_NONE
;
3650 struct drm_i915_fence_reg
*reg
;
3653 /* Have we updated the tiling parameters upon the object and so
3654 * will need to serialise the write to the associated fence register?
3656 if (obj
->fence_dirty
) {
3657 ret
= i915_gem_object_wait_fence(obj
);
3662 /* Just update our place in the LRU if our fence is getting reused. */
3663 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
3664 reg
= &dev_priv
->fence_regs
[obj
->fence_reg
];
3665 if (!obj
->fence_dirty
) {
3666 list_move_tail(®
->lru_list
,
3667 &dev_priv
->mm
.fence_list
);
3670 } else if (enable
) {
3671 if (WARN_ON(!obj
->map_and_fenceable
))
3674 reg
= i915_find_fence_reg(dev
);
3676 return PTR_ERR(reg
);
3679 struct drm_i915_gem_object
*old
= reg
->obj
;
3681 ret
= i915_gem_object_wait_fence(old
);
3685 i915_gem_object_fence_lost(old
);
3690 i915_gem_object_update_fence(obj
, reg
, enable
);
3695 static bool i915_gem_valid_gtt_space(struct i915_vma
*vma
,
3696 unsigned long cache_level
)
3698 struct drm_mm_node
*gtt_space
= &vma
->node
;
3699 struct drm_mm_node
*other
;
3702 * On some machines we have to be careful when putting differing types
3703 * of snoopable memory together to avoid the prefetcher crossing memory
3704 * domains and dying. During vm initialisation, we decide whether or not
3705 * these constraints apply and set the drm_mm.color_adjust
3708 if (vma
->vm
->mm
.color_adjust
== NULL
)
3711 if (!drm_mm_node_allocated(gtt_space
))
3714 if (list_empty(>t_space
->node_list
))
3717 other
= list_entry(gtt_space
->node_list
.prev
, struct drm_mm_node
, node_list
);
3718 if (other
->allocated
&& !other
->hole_follows
&& other
->color
!= cache_level
)
3721 other
= list_entry(gtt_space
->node_list
.next
, struct drm_mm_node
, node_list
);
3722 if (other
->allocated
&& !gtt_space
->hole_follows
&& other
->color
!= cache_level
)
3729 * Finds free space in the GTT aperture and binds the object or a view of it
3732 static struct i915_vma
*
3733 i915_gem_object_bind_to_vm(struct drm_i915_gem_object
*obj
,
3734 struct i915_address_space
*vm
,
3735 const struct i915_ggtt_view
*ggtt_view
,
3739 struct drm_device
*dev
= obj
->base
.dev
;
3740 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3741 u32 size
, fence_size
, fence_alignment
, unfenced_alignment
;
3742 unsigned long start
=
3743 flags
& PIN_OFFSET_BIAS
? flags
& PIN_OFFSET_MASK
: 0;
3745 flags
& PIN_MAPPABLE
? dev_priv
->gtt
.mappable_end
: vm
->total
;
3746 struct i915_vma
*vma
;
3749 if (i915_is_ggtt(vm
)) {
3752 if (WARN_ON(!ggtt_view
))
3753 return ERR_PTR(-EINVAL
);
3755 view_size
= i915_ggtt_view_size(obj
, ggtt_view
);
3757 fence_size
= i915_gem_get_gtt_size(dev
,
3760 fence_alignment
= i915_gem_get_gtt_alignment(dev
,
3764 unfenced_alignment
= i915_gem_get_gtt_alignment(dev
,
3768 size
= flags
& PIN_MAPPABLE
? fence_size
: view_size
;
3770 fence_size
= i915_gem_get_gtt_size(dev
,
3773 fence_alignment
= i915_gem_get_gtt_alignment(dev
,
3777 unfenced_alignment
=
3778 i915_gem_get_gtt_alignment(dev
,
3782 size
= flags
& PIN_MAPPABLE
? fence_size
: obj
->base
.size
;
3786 alignment
= flags
& PIN_MAPPABLE
? fence_alignment
:
3788 if (flags
& PIN_MAPPABLE
&& alignment
& (fence_alignment
- 1)) {
3789 DRM_DEBUG("Invalid object (view type=%u) alignment requested %u\n",
3790 ggtt_view
? ggtt_view
->type
: 0,
3792 return ERR_PTR(-EINVAL
);
3795 /* If binding the object/GGTT view requires more space than the entire
3796 * aperture has, reject it early before evicting everything in a vain
3797 * attempt to find space.
3800 DRM_DEBUG("Attempting to bind an object (view type=%u) larger than the aperture: size=%u > %s aperture=%lu\n",
3801 ggtt_view
? ggtt_view
->type
: 0,
3803 flags
& PIN_MAPPABLE
? "mappable" : "total",
3805 return ERR_PTR(-E2BIG
);
3808 ret
= i915_gem_object_get_pages(obj
);
3810 return ERR_PTR(ret
);
3812 i915_gem_object_pin_pages(obj
);
3814 vma
= ggtt_view
? i915_gem_obj_lookup_or_create_ggtt_vma(obj
, ggtt_view
) :
3815 i915_gem_obj_lookup_or_create_vma(obj
, vm
);
3821 ret
= drm_mm_insert_node_in_range_generic(&vm
->mm
, &vma
->node
,
3825 DRM_MM_SEARCH_DEFAULT
,
3826 DRM_MM_CREATE_DEFAULT
);
3828 ret
= i915_gem_evict_something(dev
, vm
, size
, alignment
,
3837 if (WARN_ON(!i915_gem_valid_gtt_space(vma
, obj
->cache_level
))) {
3839 goto err_remove_node
;
3842 ret
= i915_gem_gtt_prepare_object(obj
);
3844 goto err_remove_node
;
3846 trace_i915_vma_bind(vma
, flags
);
3847 ret
= i915_vma_bind(vma
, obj
->cache_level
, flags
);
3849 goto err_finish_gtt
;
3851 list_move_tail(&obj
->global_list
, &dev_priv
->mm
.bound_list
);
3852 list_add_tail(&vma
->mm_list
, &vm
->inactive_list
);
3857 i915_gem_gtt_finish_object(obj
);
3859 drm_mm_remove_node(&vma
->node
);
3861 i915_gem_vma_destroy(vma
);
3864 i915_gem_object_unpin_pages(obj
);
3869 i915_gem_clflush_object(struct drm_i915_gem_object
*obj
,
3872 /* If we don't have a page list set up, then we're not pinned
3873 * to GPU, and we can ignore the cache flush because it'll happen
3874 * again at bind time.
3876 if (obj
->pages
== NULL
)
3880 * Stolen memory is always coherent with the GPU as it is explicitly
3881 * marked as wc by the system, or the system is cache-coherent.
3883 if (obj
->stolen
|| obj
->phys_handle
)
3886 /* If the GPU is snooping the contents of the CPU cache,
3887 * we do not need to manually clear the CPU cache lines. However,
3888 * the caches are only snooped when the render cache is
3889 * flushed/invalidated. As we always have to emit invalidations
3890 * and flushes when moving into and out of the RENDER domain, correct
3891 * snooping behaviour occurs naturally as the result of our domain
3894 if (!force
&& cpu_cache_is_coherent(obj
->base
.dev
, obj
->cache_level
)) {
3895 obj
->cache_dirty
= true;
3899 trace_i915_gem_object_clflush(obj
);
3900 drm_clflush_sg(obj
->pages
);
3901 obj
->cache_dirty
= false;
3906 /** Flushes the GTT write domain for the object if it's dirty. */
3908 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
)
3910 uint32_t old_write_domain
;
3912 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_GTT
)
3915 /* No actual flushing is required for the GTT write domain. Writes
3916 * to it immediately go to main memory as far as we know, so there's
3917 * no chipset flush. It also doesn't land in render cache.
3919 * However, we do have to enforce the order so that all writes through
3920 * the GTT land before any writes to the device, such as updates to
3925 old_write_domain
= obj
->base
.write_domain
;
3926 obj
->base
.write_domain
= 0;
3928 intel_fb_obj_flush(obj
, false);
3930 trace_i915_gem_object_change_domain(obj
,
3931 obj
->base
.read_domains
,
3935 /** Flushes the CPU write domain for the object if it's dirty. */
3937 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
)
3939 uint32_t old_write_domain
;
3941 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
)
3944 if (i915_gem_clflush_object(obj
, obj
->pin_display
))
3945 i915_gem_chipset_flush(obj
->base
.dev
);
3947 old_write_domain
= obj
->base
.write_domain
;
3948 obj
->base
.write_domain
= 0;
3950 intel_fb_obj_flush(obj
, false);
3952 trace_i915_gem_object_change_domain(obj
,
3953 obj
->base
.read_domains
,
3958 * Moves a single object to the GTT read, and possibly write domain.
3960 * This function returns when the move is complete, including waiting on
3964 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
, bool write
)
3966 uint32_t old_write_domain
, old_read_domains
;
3967 struct i915_vma
*vma
;
3970 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_GTT
)
3973 ret
= i915_gem_object_wait_rendering(obj
, !write
);
3977 /* Flush and acquire obj->pages so that we are coherent through
3978 * direct access in memory with previous cached writes through
3979 * shmemfs and that our cache domain tracking remains valid.
3980 * For example, if the obj->filp was moved to swap without us
3981 * being notified and releasing the pages, we would mistakenly
3982 * continue to assume that the obj remained out of the CPU cached
3985 ret
= i915_gem_object_get_pages(obj
);
3989 i915_gem_object_flush_cpu_write_domain(obj
);
3991 /* Serialise direct access to this object with the barriers for
3992 * coherent writes from the GPU, by effectively invalidating the
3993 * GTT domain upon first access.
3995 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
) == 0)
3998 old_write_domain
= obj
->base
.write_domain
;
3999 old_read_domains
= obj
->base
.read_domains
;
4001 /* It should now be out of any other write domains, and we can update
4002 * the domain values for our changes.
4004 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
4005 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
4007 obj
->base
.read_domains
= I915_GEM_DOMAIN_GTT
;
4008 obj
->base
.write_domain
= I915_GEM_DOMAIN_GTT
;
4013 intel_fb_obj_invalidate(obj
, ORIGIN_GTT
);
4015 trace_i915_gem_object_change_domain(obj
,
4019 /* And bump the LRU for this access */
4020 vma
= i915_gem_obj_to_ggtt(obj
);
4021 if (vma
&& drm_mm_node_allocated(&vma
->node
) && !obj
->active
)
4022 list_move_tail(&vma
->mm_list
,
4023 &to_i915(obj
->base
.dev
)->gtt
.base
.inactive_list
);
4028 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
4029 enum i915_cache_level cache_level
)
4031 struct drm_device
*dev
= obj
->base
.dev
;
4032 struct i915_vma
*vma
, *next
;
4035 if (obj
->cache_level
== cache_level
)
4038 if (i915_gem_obj_is_pinned(obj
)) {
4039 DRM_DEBUG("can not change the cache level of pinned objects\n");
4043 list_for_each_entry_safe(vma
, next
, &obj
->vma_list
, vma_link
) {
4044 if (!i915_gem_valid_gtt_space(vma
, cache_level
)) {
4045 ret
= i915_vma_unbind(vma
);
4051 if (i915_gem_obj_bound_any(obj
)) {
4052 ret
= i915_gem_object_wait_rendering(obj
, false);
4056 i915_gem_object_finish_gtt(obj
);
4058 /* Before SandyBridge, you could not use tiling or fence
4059 * registers with snooped memory, so relinquish any fences
4060 * currently pointing to our region in the aperture.
4062 if (INTEL_INFO(dev
)->gen
< 6) {
4063 ret
= i915_gem_object_put_fence(obj
);
4068 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
4069 if (drm_mm_node_allocated(&vma
->node
)) {
4070 ret
= i915_vma_bind(vma
, cache_level
,
4077 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
4078 vma
->node
.color
= cache_level
;
4079 obj
->cache_level
= cache_level
;
4081 if (obj
->cache_dirty
&&
4082 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
&&
4083 cpu_write_needs_clflush(obj
)) {
4084 if (i915_gem_clflush_object(obj
, true))
4085 i915_gem_chipset_flush(obj
->base
.dev
);
4091 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
4092 struct drm_file
*file
)
4094 struct drm_i915_gem_caching
*args
= data
;
4095 struct drm_i915_gem_object
*obj
;
4097 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
4098 if (&obj
->base
== NULL
)
4101 switch (obj
->cache_level
) {
4102 case I915_CACHE_LLC
:
4103 case I915_CACHE_L3_LLC
:
4104 args
->caching
= I915_CACHING_CACHED
;
4108 args
->caching
= I915_CACHING_DISPLAY
;
4112 args
->caching
= I915_CACHING_NONE
;
4116 drm_gem_object_unreference_unlocked(&obj
->base
);
4120 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
4121 struct drm_file
*file
)
4123 struct drm_i915_gem_caching
*args
= data
;
4124 struct drm_i915_gem_object
*obj
;
4125 enum i915_cache_level level
;
4128 switch (args
->caching
) {
4129 case I915_CACHING_NONE
:
4130 level
= I915_CACHE_NONE
;
4132 case I915_CACHING_CACHED
:
4133 level
= I915_CACHE_LLC
;
4135 case I915_CACHING_DISPLAY
:
4136 level
= HAS_WT(dev
) ? I915_CACHE_WT
: I915_CACHE_NONE
;
4142 ret
= i915_mutex_lock_interruptible(dev
);
4146 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
4147 if (&obj
->base
== NULL
) {
4152 ret
= i915_gem_object_set_cache_level(obj
, level
);
4154 drm_gem_object_unreference(&obj
->base
);
4156 mutex_unlock(&dev
->struct_mutex
);
4161 * Prepare buffer for display plane (scanout, cursors, etc).
4162 * Can be called from an uninterruptible phase (modesetting) and allows
4163 * any flushes to be pipelined (for pageflips).
4166 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
4168 struct intel_engine_cs
*pipelined
,
4169 struct drm_i915_gem_request
**pipelined_request
,
4170 const struct i915_ggtt_view
*view
)
4172 u32 old_read_domains
, old_write_domain
;
4175 ret
= i915_gem_object_sync(obj
, pipelined
, pipelined_request
);
4179 /* Mark the pin_display early so that we account for the
4180 * display coherency whilst setting up the cache domains.
4184 /* The display engine is not coherent with the LLC cache on gen6. As
4185 * a result, we make sure that the pinning that is about to occur is
4186 * done with uncached PTEs. This is lowest common denominator for all
4189 * However for gen6+, we could do better by using the GFDT bit instead
4190 * of uncaching, which would allow us to flush all the LLC-cached data
4191 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
4193 ret
= i915_gem_object_set_cache_level(obj
,
4194 HAS_WT(obj
->base
.dev
) ? I915_CACHE_WT
: I915_CACHE_NONE
);
4196 goto err_unpin_display
;
4198 /* As the user may map the buffer once pinned in the display plane
4199 * (e.g. libkms for the bootup splash), we have to ensure that we
4200 * always use map_and_fenceable for all scanout buffers.
4202 ret
= i915_gem_object_ggtt_pin(obj
, view
, alignment
,
4203 view
->type
== I915_GGTT_VIEW_NORMAL
?
4206 goto err_unpin_display
;
4208 i915_gem_object_flush_cpu_write_domain(obj
);
4210 old_write_domain
= obj
->base
.write_domain
;
4211 old_read_domains
= obj
->base
.read_domains
;
4213 /* It should now be out of any other write domains, and we can update
4214 * the domain values for our changes.
4216 obj
->base
.write_domain
= 0;
4217 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
4219 trace_i915_gem_object_change_domain(obj
,
4231 i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object
*obj
,
4232 const struct i915_ggtt_view
*view
)
4234 if (WARN_ON(obj
->pin_display
== 0))
4237 i915_gem_object_ggtt_unpin_view(obj
, view
);
4243 * Moves a single object to the CPU read, and possibly write domain.
4245 * This function returns when the move is complete, including waiting on
4249 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
)
4251 uint32_t old_write_domain
, old_read_domains
;
4254 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_CPU
)
4257 ret
= i915_gem_object_wait_rendering(obj
, !write
);
4261 i915_gem_object_flush_gtt_write_domain(obj
);
4263 old_write_domain
= obj
->base
.write_domain
;
4264 old_read_domains
= obj
->base
.read_domains
;
4266 /* Flush the CPU cache if it's still invalid. */
4267 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) == 0) {
4268 i915_gem_clflush_object(obj
, false);
4270 obj
->base
.read_domains
|= I915_GEM_DOMAIN_CPU
;
4273 /* It should now be out of any other write domains, and we can update
4274 * the domain values for our changes.
4276 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
4278 /* If we're writing through the CPU, then the GPU read domains will
4279 * need to be invalidated at next use.
4282 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
4283 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
4287 intel_fb_obj_invalidate(obj
, ORIGIN_CPU
);
4289 trace_i915_gem_object_change_domain(obj
,
4296 /* Throttle our rendering by waiting until the ring has completed our requests
4297 * emitted over 20 msec ago.
4299 * Note that if we were to use the current jiffies each time around the loop,
4300 * we wouldn't escape the function with any frames outstanding if the time to
4301 * render a frame was over 20ms.
4303 * This should get us reasonable parallelism between CPU and GPU but also
4304 * relatively low latency when blocking on a particular request to finish.
4307 i915_gem_ring_throttle(struct drm_device
*dev
, struct drm_file
*file
)
4309 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4310 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
4311 unsigned long recent_enough
= jiffies
- DRM_I915_THROTTLE_JIFFIES
;
4312 struct drm_i915_gem_request
*request
, *target
= NULL
;
4313 unsigned reset_counter
;
4316 ret
= i915_gem_wait_for_error(&dev_priv
->gpu_error
);
4320 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, false);
4324 spin_lock(&file_priv
->mm
.lock
);
4325 list_for_each_entry(request
, &file_priv
->mm
.request_list
, client_list
) {
4326 if (time_after_eq(request
->emitted_jiffies
, recent_enough
))
4331 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
4333 i915_gem_request_reference(target
);
4334 spin_unlock(&file_priv
->mm
.lock
);
4339 ret
= __i915_wait_request(target
, reset_counter
, true, NULL
, NULL
);
4341 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, 0);
4343 i915_gem_request_unreference__unlocked(target
);
4349 i915_vma_misplaced(struct i915_vma
*vma
, uint32_t alignment
, uint64_t flags
)
4351 struct drm_i915_gem_object
*obj
= vma
->obj
;
4354 vma
->node
.start
& (alignment
- 1))
4357 if (flags
& PIN_MAPPABLE
&& !obj
->map_and_fenceable
)
4360 if (flags
& PIN_OFFSET_BIAS
&&
4361 vma
->node
.start
< (flags
& PIN_OFFSET_MASK
))
4368 i915_gem_object_do_pin(struct drm_i915_gem_object
*obj
,
4369 struct i915_address_space
*vm
,
4370 const struct i915_ggtt_view
*ggtt_view
,
4374 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
4375 struct i915_vma
*vma
;
4379 if (WARN_ON(vm
== &dev_priv
->mm
.aliasing_ppgtt
->base
))
4382 if (WARN_ON(flags
& (PIN_GLOBAL
| PIN_MAPPABLE
) && !i915_is_ggtt(vm
)))
4385 if (WARN_ON((flags
& (PIN_MAPPABLE
| PIN_GLOBAL
)) == PIN_MAPPABLE
))
4388 if (WARN_ON(i915_is_ggtt(vm
) != !!ggtt_view
))
4391 vma
= ggtt_view
? i915_gem_obj_to_ggtt_view(obj
, ggtt_view
) :
4392 i915_gem_obj_to_vma(obj
, vm
);
4395 return PTR_ERR(vma
);
4398 if (WARN_ON(vma
->pin_count
== DRM_I915_GEM_OBJECT_MAX_PIN_COUNT
))
4401 if (i915_vma_misplaced(vma
, alignment
, flags
)) {
4402 unsigned long offset
;
4403 offset
= ggtt_view
? i915_gem_obj_ggtt_offset_view(obj
, ggtt_view
) :
4404 i915_gem_obj_offset(obj
, vm
);
4405 WARN(vma
->pin_count
,
4406 "bo is already pinned in %s with incorrect alignment:"
4407 " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d,"
4408 " obj->map_and_fenceable=%d\n",
4409 ggtt_view
? "ggtt" : "ppgtt",
4412 !!(flags
& PIN_MAPPABLE
),
4413 obj
->map_and_fenceable
);
4414 ret
= i915_vma_unbind(vma
);
4422 bound
= vma
? vma
->bound
: 0;
4423 if (vma
== NULL
|| !drm_mm_node_allocated(&vma
->node
)) {
4424 vma
= i915_gem_object_bind_to_vm(obj
, vm
, ggtt_view
, alignment
,
4427 return PTR_ERR(vma
);
4429 ret
= i915_vma_bind(vma
, obj
->cache_level
, flags
);
4434 if (ggtt_view
&& ggtt_view
->type
== I915_GGTT_VIEW_NORMAL
&&
4435 (bound
^ vma
->bound
) & GLOBAL_BIND
) {
4436 bool mappable
, fenceable
;
4437 u32 fence_size
, fence_alignment
;
4439 fence_size
= i915_gem_get_gtt_size(obj
->base
.dev
,
4442 fence_alignment
= i915_gem_get_gtt_alignment(obj
->base
.dev
,
4447 fenceable
= (vma
->node
.size
== fence_size
&&
4448 (vma
->node
.start
& (fence_alignment
- 1)) == 0);
4450 mappable
= (vma
->node
.start
+ fence_size
<=
4451 dev_priv
->gtt
.mappable_end
);
4453 obj
->map_and_fenceable
= mappable
&& fenceable
;
4455 WARN_ON(flags
& PIN_MAPPABLE
&& !obj
->map_and_fenceable
);
4463 i915_gem_object_pin(struct drm_i915_gem_object
*obj
,
4464 struct i915_address_space
*vm
,
4468 return i915_gem_object_do_pin(obj
, vm
,
4469 i915_is_ggtt(vm
) ? &i915_ggtt_view_normal
: NULL
,
4474 i915_gem_object_ggtt_pin(struct drm_i915_gem_object
*obj
,
4475 const struct i915_ggtt_view
*view
,
4479 if (WARN_ONCE(!view
, "no view specified"))
4482 return i915_gem_object_do_pin(obj
, i915_obj_to_ggtt(obj
), view
,
4483 alignment
, flags
| PIN_GLOBAL
);
4487 i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object
*obj
,
4488 const struct i915_ggtt_view
*view
)
4490 struct i915_vma
*vma
= i915_gem_obj_to_ggtt_view(obj
, view
);
4493 WARN_ON(vma
->pin_count
== 0);
4494 WARN_ON(!i915_gem_obj_ggtt_bound_view(obj
, view
));
4500 i915_gem_object_pin_fence(struct drm_i915_gem_object
*obj
)
4502 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
4503 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
4504 struct i915_vma
*ggtt_vma
= i915_gem_obj_to_ggtt(obj
);
4506 WARN_ON(!ggtt_vma
||
4507 dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
>
4508 ggtt_vma
->pin_count
);
4509 dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
++;
4516 i915_gem_object_unpin_fence(struct drm_i915_gem_object
*obj
)
4518 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
4519 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
4520 WARN_ON(dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
<= 0);
4521 dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
--;
4526 i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
4527 struct drm_file
*file
)
4529 struct drm_i915_gem_busy
*args
= data
;
4530 struct drm_i915_gem_object
*obj
;
4533 ret
= i915_mutex_lock_interruptible(dev
);
4537 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
4538 if (&obj
->base
== NULL
) {
4543 /* Count all active objects as busy, even if they are currently not used
4544 * by the gpu. Users of this interface expect objects to eventually
4545 * become non-busy without any further actions, therefore emit any
4546 * necessary flushes here.
4548 ret
= i915_gem_object_flush_active(obj
);
4552 BUILD_BUG_ON(I915_NUM_RINGS
> 16);
4553 args
->busy
= obj
->active
<< 16;
4554 if (obj
->last_write_req
)
4555 args
->busy
|= obj
->last_write_req
->ring
->id
;
4558 drm_gem_object_unreference(&obj
->base
);
4560 mutex_unlock(&dev
->struct_mutex
);
4565 i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
4566 struct drm_file
*file_priv
)
4568 return i915_gem_ring_throttle(dev
, file_priv
);
4572 i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
4573 struct drm_file
*file_priv
)
4575 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4576 struct drm_i915_gem_madvise
*args
= data
;
4577 struct drm_i915_gem_object
*obj
;
4580 switch (args
->madv
) {
4581 case I915_MADV_DONTNEED
:
4582 case I915_MADV_WILLNEED
:
4588 ret
= i915_mutex_lock_interruptible(dev
);
4592 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file_priv
, args
->handle
));
4593 if (&obj
->base
== NULL
) {
4598 if (i915_gem_obj_is_pinned(obj
)) {
4604 obj
->tiling_mode
!= I915_TILING_NONE
&&
4605 dev_priv
->quirks
& QUIRK_PIN_SWIZZLED_PAGES
) {
4606 if (obj
->madv
== I915_MADV_WILLNEED
)
4607 i915_gem_object_unpin_pages(obj
);
4608 if (args
->madv
== I915_MADV_WILLNEED
)
4609 i915_gem_object_pin_pages(obj
);
4612 if (obj
->madv
!= __I915_MADV_PURGED
)
4613 obj
->madv
= args
->madv
;
4615 /* if the object is no longer attached, discard its backing storage */
4616 if (obj
->madv
== I915_MADV_DONTNEED
&& obj
->pages
== NULL
)
4617 i915_gem_object_truncate(obj
);
4619 args
->retained
= obj
->madv
!= __I915_MADV_PURGED
;
4622 drm_gem_object_unreference(&obj
->base
);
4624 mutex_unlock(&dev
->struct_mutex
);
4628 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
4629 const struct drm_i915_gem_object_ops
*ops
)
4633 INIT_LIST_HEAD(&obj
->global_list
);
4634 for (i
= 0; i
< I915_NUM_RINGS
; i
++)
4635 INIT_LIST_HEAD(&obj
->ring_list
[i
]);
4636 INIT_LIST_HEAD(&obj
->obj_exec_link
);
4637 INIT_LIST_HEAD(&obj
->vma_list
);
4638 INIT_LIST_HEAD(&obj
->batch_pool_link
);
4642 obj
->fence_reg
= I915_FENCE_REG_NONE
;
4643 obj
->madv
= I915_MADV_WILLNEED
;
4645 i915_gem_info_add_obj(obj
->base
.dev
->dev_private
, obj
->base
.size
);
4648 static const struct drm_i915_gem_object_ops i915_gem_object_ops
= {
4649 .get_pages
= i915_gem_object_get_pages_gtt
,
4650 .put_pages
= i915_gem_object_put_pages_gtt
,
4653 struct drm_i915_gem_object
*i915_gem_alloc_object(struct drm_device
*dev
,
4656 struct drm_i915_gem_object
*obj
;
4657 struct address_space
*mapping
;
4660 obj
= i915_gem_object_alloc(dev
);
4664 if (drm_gem_object_init(dev
, &obj
->base
, size
) != 0) {
4665 i915_gem_object_free(obj
);
4669 mask
= GFP_HIGHUSER
| __GFP_RECLAIMABLE
;
4670 if (IS_CRESTLINE(dev
) || IS_BROADWATER(dev
)) {
4671 /* 965gm cannot relocate objects above 4GiB. */
4672 mask
&= ~__GFP_HIGHMEM
;
4673 mask
|= __GFP_DMA32
;
4676 mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
4677 mapping_set_gfp_mask(mapping
, mask
);
4679 i915_gem_object_init(obj
, &i915_gem_object_ops
);
4681 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
4682 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
4685 /* On some devices, we can have the GPU use the LLC (the CPU
4686 * cache) for about a 10% performance improvement
4687 * compared to uncached. Graphics requests other than
4688 * display scanout are coherent with the CPU in
4689 * accessing this cache. This means in this mode we
4690 * don't need to clflush on the CPU side, and on the
4691 * GPU side we only need to flush internal caches to
4692 * get data visible to the CPU.
4694 * However, we maintain the display planes as UC, and so
4695 * need to rebind when first used as such.
4697 obj
->cache_level
= I915_CACHE_LLC
;
4699 obj
->cache_level
= I915_CACHE_NONE
;
4701 trace_i915_gem_object_create(obj
);
4706 static bool discard_backing_storage(struct drm_i915_gem_object
*obj
)
4708 /* If we are the last user of the backing storage (be it shmemfs
4709 * pages or stolen etc), we know that the pages are going to be
4710 * immediately released. In this case, we can then skip copying
4711 * back the contents from the GPU.
4714 if (obj
->madv
!= I915_MADV_WILLNEED
)
4717 if (obj
->base
.filp
== NULL
)
4720 /* At first glance, this looks racy, but then again so would be
4721 * userspace racing mmap against close. However, the first external
4722 * reference to the filp can only be obtained through the
4723 * i915_gem_mmap_ioctl() which safeguards us against the user
4724 * acquiring such a reference whilst we are in the middle of
4725 * freeing the object.
4727 return atomic_long_read(&obj
->base
.filp
->f_count
) == 1;
4730 void i915_gem_free_object(struct drm_gem_object
*gem_obj
)
4732 struct drm_i915_gem_object
*obj
= to_intel_bo(gem_obj
);
4733 struct drm_device
*dev
= obj
->base
.dev
;
4734 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4735 struct i915_vma
*vma
, *next
;
4737 intel_runtime_pm_get(dev_priv
);
4739 trace_i915_gem_object_destroy(obj
);
4741 list_for_each_entry_safe(vma
, next
, &obj
->vma_list
, vma_link
) {
4745 ret
= i915_vma_unbind(vma
);
4746 if (WARN_ON(ret
== -ERESTARTSYS
)) {
4747 bool was_interruptible
;
4749 was_interruptible
= dev_priv
->mm
.interruptible
;
4750 dev_priv
->mm
.interruptible
= false;
4752 WARN_ON(i915_vma_unbind(vma
));
4754 dev_priv
->mm
.interruptible
= was_interruptible
;
4758 /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
4759 * before progressing. */
4761 i915_gem_object_unpin_pages(obj
);
4763 WARN_ON(obj
->frontbuffer_bits
);
4765 if (obj
->pages
&& obj
->madv
== I915_MADV_WILLNEED
&&
4766 dev_priv
->quirks
& QUIRK_PIN_SWIZZLED_PAGES
&&
4767 obj
->tiling_mode
!= I915_TILING_NONE
)
4768 i915_gem_object_unpin_pages(obj
);
4770 if (WARN_ON(obj
->pages_pin_count
))
4771 obj
->pages_pin_count
= 0;
4772 if (discard_backing_storage(obj
))
4773 obj
->madv
= I915_MADV_DONTNEED
;
4774 i915_gem_object_put_pages(obj
);
4775 i915_gem_object_free_mmap_offset(obj
);
4779 if (obj
->base
.import_attach
)
4780 drm_prime_gem_destroy(&obj
->base
, NULL
);
4782 if (obj
->ops
->release
)
4783 obj
->ops
->release(obj
);
4785 drm_gem_object_release(&obj
->base
);
4786 i915_gem_info_remove_obj(dev_priv
, obj
->base
.size
);
4789 i915_gem_object_free(obj
);
4791 intel_runtime_pm_put(dev_priv
);
4794 struct i915_vma
*i915_gem_obj_to_vma(struct drm_i915_gem_object
*obj
,
4795 struct i915_address_space
*vm
)
4797 struct i915_vma
*vma
;
4798 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
) {
4799 if (i915_is_ggtt(vma
->vm
) &&
4800 vma
->ggtt_view
.type
!= I915_GGTT_VIEW_NORMAL
)
4808 struct i915_vma
*i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object
*obj
,
4809 const struct i915_ggtt_view
*view
)
4811 struct i915_address_space
*ggtt
= i915_obj_to_ggtt(obj
);
4812 struct i915_vma
*vma
;
4814 if (WARN_ONCE(!view
, "no view specified"))
4815 return ERR_PTR(-EINVAL
);
4817 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
4818 if (vma
->vm
== ggtt
&&
4819 i915_ggtt_view_equal(&vma
->ggtt_view
, view
))
4824 void i915_gem_vma_destroy(struct i915_vma
*vma
)
4826 struct i915_address_space
*vm
= NULL
;
4827 WARN_ON(vma
->node
.allocated
);
4829 /* Keep the vma as a placeholder in the execbuffer reservation lists */
4830 if (!list_empty(&vma
->exec_list
))
4835 if (!i915_is_ggtt(vm
))
4836 i915_ppgtt_put(i915_vm_to_ppgtt(vm
));
4838 list_del(&vma
->vma_link
);
4840 kmem_cache_free(to_i915(vma
->obj
->base
.dev
)->vmas
, vma
);
4844 i915_gem_stop_ringbuffers(struct drm_device
*dev
)
4846 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4847 struct intel_engine_cs
*ring
;
4850 for_each_ring(ring
, dev_priv
, i
)
4851 dev_priv
->gt
.stop_ring(ring
);
4855 i915_gem_suspend(struct drm_device
*dev
)
4857 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4860 mutex_lock(&dev
->struct_mutex
);
4861 ret
= i915_gpu_idle(dev
);
4865 i915_gem_retire_requests(dev
);
4867 i915_gem_stop_ringbuffers(dev
);
4868 mutex_unlock(&dev
->struct_mutex
);
4870 cancel_delayed_work_sync(&dev_priv
->gpu_error
.hangcheck_work
);
4871 cancel_delayed_work_sync(&dev_priv
->mm
.retire_work
);
4872 flush_delayed_work(&dev_priv
->mm
.idle_work
);
4874 /* Assert that we sucessfully flushed all the work and
4875 * reset the GPU back to its idle, low power state.
4877 WARN_ON(dev_priv
->mm
.busy
);
4882 mutex_unlock(&dev
->struct_mutex
);
4886 int i915_gem_l3_remap(struct drm_i915_gem_request
*req
, int slice
)
4888 struct intel_engine_cs
*ring
= req
->ring
;
4889 struct drm_device
*dev
= ring
->dev
;
4890 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4891 u32 reg_base
= GEN7_L3LOG_BASE
+ (slice
* 0x200);
4892 u32
*remap_info
= dev_priv
->l3_parity
.remap_info
[slice
];
4895 if (!HAS_L3_DPF(dev
) || !remap_info
)
4898 ret
= intel_ring_begin(req
, GEN7_L3LOG_SIZE
/ 4 * 3);
4903 * Note: We do not worry about the concurrent register cacheline hang
4904 * here because no other code should access these registers other than
4905 * at initialization time.
4907 for (i
= 0; i
< GEN7_L3LOG_SIZE
; i
+= 4) {
4908 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
4909 intel_ring_emit(ring
, reg_base
+ i
);
4910 intel_ring_emit(ring
, remap_info
[i
/4]);
4913 intel_ring_advance(ring
);
4918 void i915_gem_init_swizzling(struct drm_device
*dev
)
4920 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4922 if (INTEL_INFO(dev
)->gen
< 5 ||
4923 dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_NONE
)
4926 I915_WRITE(DISP_ARB_CTL
, I915_READ(DISP_ARB_CTL
) |
4927 DISP_TILE_SURFACE_SWIZZLING
);
4932 I915_WRITE(TILECTL
, I915_READ(TILECTL
) | TILECTL_SWZCTL
);
4934 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB
));
4935 else if (IS_GEN7(dev
))
4936 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB
));
4937 else if (IS_GEN8(dev
))
4938 I915_WRITE(GAMTARBMODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW
));
4944 intel_enable_blt(struct drm_device
*dev
)
4949 /* The blitter was dysfunctional on early prototypes */
4950 if (IS_GEN6(dev
) && dev
->pdev
->revision
< 8) {
4951 DRM_INFO("BLT not supported on this pre-production hardware;"
4952 " graphics performance will be degraded.\n");
4959 static void init_unused_ring(struct drm_device
*dev
, u32 base
)
4961 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4963 I915_WRITE(RING_CTL(base
), 0);
4964 I915_WRITE(RING_HEAD(base
), 0);
4965 I915_WRITE(RING_TAIL(base
), 0);
4966 I915_WRITE(RING_START(base
), 0);
4969 static void init_unused_rings(struct drm_device
*dev
)
4972 init_unused_ring(dev
, PRB1_BASE
);
4973 init_unused_ring(dev
, SRB0_BASE
);
4974 init_unused_ring(dev
, SRB1_BASE
);
4975 init_unused_ring(dev
, SRB2_BASE
);
4976 init_unused_ring(dev
, SRB3_BASE
);
4977 } else if (IS_GEN2(dev
)) {
4978 init_unused_ring(dev
, SRB0_BASE
);
4979 init_unused_ring(dev
, SRB1_BASE
);
4980 } else if (IS_GEN3(dev
)) {
4981 init_unused_ring(dev
, PRB1_BASE
);
4982 init_unused_ring(dev
, PRB2_BASE
);
4986 int i915_gem_init_rings(struct drm_device
*dev
)
4988 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4991 ret
= intel_init_render_ring_buffer(dev
);
4996 ret
= intel_init_bsd_ring_buffer(dev
);
4998 goto cleanup_render_ring
;
5001 if (intel_enable_blt(dev
)) {
5002 ret
= intel_init_blt_ring_buffer(dev
);
5004 goto cleanup_bsd_ring
;
5007 if (HAS_VEBOX(dev
)) {
5008 ret
= intel_init_vebox_ring_buffer(dev
);
5010 goto cleanup_blt_ring
;
5013 if (HAS_BSD2(dev
)) {
5014 ret
= intel_init_bsd2_ring_buffer(dev
);
5016 goto cleanup_vebox_ring
;
5019 ret
= i915_gem_set_seqno(dev
, ((u32
)~0 - 0x1000));
5021 goto cleanup_bsd2_ring
;
5026 intel_cleanup_ring_buffer(&dev_priv
->ring
[VCS2
]);
5028 intel_cleanup_ring_buffer(&dev_priv
->ring
[VECS
]);
5030 intel_cleanup_ring_buffer(&dev_priv
->ring
[BCS
]);
5032 intel_cleanup_ring_buffer(&dev_priv
->ring
[VCS
]);
5033 cleanup_render_ring
:
5034 intel_cleanup_ring_buffer(&dev_priv
->ring
[RCS
]);
5040 i915_gem_init_hw(struct drm_device
*dev
)
5042 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5043 struct intel_engine_cs
*ring
;
5046 if (INTEL_INFO(dev
)->gen
< 6 && !intel_enable_gtt())
5049 /* Double layer security blanket, see i915_gem_init() */
5050 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
5052 if (dev_priv
->ellc_size
)
5053 I915_WRITE(HSW_IDICR
, I915_READ(HSW_IDICR
) | IDIHASHMSK(0xf));
5055 if (IS_HASWELL(dev
))
5056 I915_WRITE(MI_PREDICATE_RESULT_2
, IS_HSW_GT3(dev
) ?
5057 LOWER_SLICE_ENABLED
: LOWER_SLICE_DISABLED
);
5059 if (HAS_PCH_NOP(dev
)) {
5060 if (IS_IVYBRIDGE(dev
)) {
5061 u32 temp
= I915_READ(GEN7_MSG_CTL
);
5062 temp
&= ~(WAIT_FOR_PCH_FLR_ACK
| WAIT_FOR_PCH_RESET_ACK
);
5063 I915_WRITE(GEN7_MSG_CTL
, temp
);
5064 } else if (INTEL_INFO(dev
)->gen
>= 7) {
5065 u32 temp
= I915_READ(HSW_NDE_RSTWRN_OPT
);
5066 temp
&= ~RESET_PCH_HANDSHAKE_ENABLE
;
5067 I915_WRITE(HSW_NDE_RSTWRN_OPT
, temp
);
5071 i915_gem_init_swizzling(dev
);
5074 * At least 830 can leave some of the unused rings
5075 * "active" (ie. head != tail) after resume which
5076 * will prevent c3 entry. Makes sure all unused rings
5079 init_unused_rings(dev
);
5081 BUG_ON(!dev_priv
->ring
[RCS
].default_context
);
5083 ret
= i915_ppgtt_init_hw(dev
);
5085 DRM_ERROR("PPGTT enable HW failed %d\n", ret
);
5089 /* Need to do basic initialisation of all rings first: */
5090 for_each_ring(ring
, dev_priv
, i
) {
5091 ret
= ring
->init_hw(ring
);
5096 /* Now it is safe to go back round and do everything else: */
5097 for_each_ring(ring
, dev_priv
, i
) {
5098 struct drm_i915_gem_request
*req
;
5100 WARN_ON(!ring
->default_context
);
5102 ret
= i915_gem_request_alloc(ring
, ring
->default_context
, &req
);
5104 i915_gem_cleanup_ringbuffer(dev
);
5108 if (ring
->id
== RCS
) {
5109 for (j
= 0; j
< NUM_L3_SLICES(dev
); j
++)
5110 i915_gem_l3_remap(req
, j
);
5113 ret
= i915_ppgtt_init_ring(req
);
5114 if (ret
&& ret
!= -EIO
) {
5115 DRM_ERROR("PPGTT enable ring #%d failed %d\n", i
, ret
);
5116 i915_gem_request_cancel(req
);
5117 i915_gem_cleanup_ringbuffer(dev
);
5121 ret
= i915_gem_context_enable(req
);
5122 if (ret
&& ret
!= -EIO
) {
5123 DRM_ERROR("Context enable ring #%d failed %d\n", i
, ret
);
5124 i915_gem_request_cancel(req
);
5125 i915_gem_cleanup_ringbuffer(dev
);
5129 i915_add_request_no_flush(req
);
5133 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
5137 int i915_gem_init(struct drm_device
*dev
)
5139 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5142 i915
.enable_execlists
= intel_sanitize_enable_execlists(dev
,
5143 i915
.enable_execlists
);
5145 mutex_lock(&dev
->struct_mutex
);
5147 if (IS_VALLEYVIEW(dev
)) {
5148 /* VLVA0 (potential hack), BIOS isn't actually waking us */
5149 I915_WRITE(VLV_GTLC_WAKE_CTRL
, VLV_GTLC_ALLOWWAKEREQ
);
5150 if (wait_for((I915_READ(VLV_GTLC_PW_STATUS
) &
5151 VLV_GTLC_ALLOWWAKEACK
), 10))
5152 DRM_DEBUG_DRIVER("allow wake ack timed out\n");
5155 if (!i915
.enable_execlists
) {
5156 dev_priv
->gt
.execbuf_submit
= i915_gem_ringbuffer_submission
;
5157 dev_priv
->gt
.init_rings
= i915_gem_init_rings
;
5158 dev_priv
->gt
.cleanup_ring
= intel_cleanup_ring_buffer
;
5159 dev_priv
->gt
.stop_ring
= intel_stop_ring_buffer
;
5161 dev_priv
->gt
.execbuf_submit
= intel_execlists_submission
;
5162 dev_priv
->gt
.init_rings
= intel_logical_rings_init
;
5163 dev_priv
->gt
.cleanup_ring
= intel_logical_ring_cleanup
;
5164 dev_priv
->gt
.stop_ring
= intel_logical_ring_stop
;
5167 /* This is just a security blanket to placate dragons.
5168 * On some systems, we very sporadically observe that the first TLBs
5169 * used by the CS may be stale, despite us poking the TLB reset. If
5170 * we hold the forcewake during initialisation these problems
5171 * just magically go away.
5173 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
5175 ret
= i915_gem_init_userptr(dev
);
5179 i915_gem_init_global_gtt(dev
);
5181 ret
= i915_gem_context_init(dev
);
5185 ret
= dev_priv
->gt
.init_rings(dev
);
5189 ret
= i915_gem_init_hw(dev
);
5191 /* Allow ring initialisation to fail by marking the GPU as
5192 * wedged. But we only want to do this where the GPU is angry,
5193 * for all other failure, such as an allocation failure, bail.
5195 DRM_ERROR("Failed to initialize GPU, declaring it wedged\n");
5196 atomic_set_mask(I915_WEDGED
, &dev_priv
->gpu_error
.reset_counter
);
5201 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
5202 mutex_unlock(&dev
->struct_mutex
);
5208 i915_gem_cleanup_ringbuffer(struct drm_device
*dev
)
5210 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5211 struct intel_engine_cs
*ring
;
5214 for_each_ring(ring
, dev_priv
, i
)
5215 dev_priv
->gt
.cleanup_ring(ring
);
5219 init_ring_lists(struct intel_engine_cs
*ring
)
5221 INIT_LIST_HEAD(&ring
->active_list
);
5222 INIT_LIST_HEAD(&ring
->request_list
);
5225 void i915_init_vm(struct drm_i915_private
*dev_priv
,
5226 struct i915_address_space
*vm
)
5228 if (!i915_is_ggtt(vm
))
5229 drm_mm_init(&vm
->mm
, vm
->start
, vm
->total
);
5230 vm
->dev
= dev_priv
->dev
;
5231 INIT_LIST_HEAD(&vm
->active_list
);
5232 INIT_LIST_HEAD(&vm
->inactive_list
);
5233 INIT_LIST_HEAD(&vm
->global_link
);
5234 list_add_tail(&vm
->global_link
, &dev_priv
->vm_list
);
5238 i915_gem_load(struct drm_device
*dev
)
5240 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5244 kmem_cache_create("i915_gem_object",
5245 sizeof(struct drm_i915_gem_object
), 0,
5249 kmem_cache_create("i915_gem_vma",
5250 sizeof(struct i915_vma
), 0,
5253 dev_priv
->requests
=
5254 kmem_cache_create("i915_gem_request",
5255 sizeof(struct drm_i915_gem_request
), 0,
5259 INIT_LIST_HEAD(&dev_priv
->vm_list
);
5260 i915_init_vm(dev_priv
, &dev_priv
->gtt
.base
);
5262 INIT_LIST_HEAD(&dev_priv
->context_list
);
5263 INIT_LIST_HEAD(&dev_priv
->mm
.unbound_list
);
5264 INIT_LIST_HEAD(&dev_priv
->mm
.bound_list
);
5265 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
5266 for (i
= 0; i
< I915_NUM_RINGS
; i
++)
5267 init_ring_lists(&dev_priv
->ring
[i
]);
5268 for (i
= 0; i
< I915_MAX_NUM_FENCES
; i
++)
5269 INIT_LIST_HEAD(&dev_priv
->fence_regs
[i
].lru_list
);
5270 INIT_DELAYED_WORK(&dev_priv
->mm
.retire_work
,
5271 i915_gem_retire_work_handler
);
5272 INIT_DELAYED_WORK(&dev_priv
->mm
.idle_work
,
5273 i915_gem_idle_work_handler
);
5274 init_waitqueue_head(&dev_priv
->gpu_error
.reset_queue
);
5276 dev_priv
->relative_constants_mode
= I915_EXEC_CONSTANTS_REL_GENERAL
;
5278 if (INTEL_INFO(dev
)->gen
>= 7 && !IS_VALLEYVIEW(dev
))
5279 dev_priv
->num_fence_regs
= 32;
5280 else if (INTEL_INFO(dev
)->gen
>= 4 || IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
5281 dev_priv
->num_fence_regs
= 16;
5283 dev_priv
->num_fence_regs
= 8;
5285 if (intel_vgpu_active(dev
))
5286 dev_priv
->num_fence_regs
=
5287 I915_READ(vgtif_reg(avail_rs
.fence_num
));
5289 /* Initialize fence registers to zero */
5290 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
5291 i915_gem_restore_fences(dev
);
5293 i915_gem_detect_bit_6_swizzle(dev
);
5294 init_waitqueue_head(&dev_priv
->pending_flip_queue
);
5296 dev_priv
->mm
.interruptible
= true;
5298 i915_gem_shrinker_init(dev_priv
);
5300 mutex_init(&dev_priv
->fb_tracking
.lock
);
5303 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
)
5305 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
5307 /* Clean up our request list when the client is going away, so that
5308 * later retire_requests won't dereference our soon-to-be-gone
5311 spin_lock(&file_priv
->mm
.lock
);
5312 while (!list_empty(&file_priv
->mm
.request_list
)) {
5313 struct drm_i915_gem_request
*request
;
5315 request
= list_first_entry(&file_priv
->mm
.request_list
,
5316 struct drm_i915_gem_request
,
5318 list_del(&request
->client_list
);
5319 request
->file_priv
= NULL
;
5321 spin_unlock(&file_priv
->mm
.lock
);
5323 if (!list_empty(&file_priv
->rps
.link
)) {
5324 spin_lock(&to_i915(dev
)->rps
.client_lock
);
5325 list_del(&file_priv
->rps
.link
);
5326 spin_unlock(&to_i915(dev
)->rps
.client_lock
);
5330 int i915_gem_open(struct drm_device
*dev
, struct drm_file
*file
)
5332 struct drm_i915_file_private
*file_priv
;
5335 DRM_DEBUG_DRIVER("\n");
5337 file_priv
= kzalloc(sizeof(*file_priv
), GFP_KERNEL
);
5341 file
->driver_priv
= file_priv
;
5342 file_priv
->dev_priv
= dev
->dev_private
;
5343 file_priv
->file
= file
;
5344 INIT_LIST_HEAD(&file_priv
->rps
.link
);
5346 spin_lock_init(&file_priv
->mm
.lock
);
5347 INIT_LIST_HEAD(&file_priv
->mm
.request_list
);
5349 ret
= i915_gem_context_open(dev
, file
);
5357 * i915_gem_track_fb - update frontbuffer tracking
5358 * old: current GEM buffer for the frontbuffer slots
5359 * new: new GEM buffer for the frontbuffer slots
5360 * frontbuffer_bits: bitmask of frontbuffer slots
5362 * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them
5363 * from @old and setting them in @new. Both @old and @new can be NULL.
5365 void i915_gem_track_fb(struct drm_i915_gem_object
*old
,
5366 struct drm_i915_gem_object
*new,
5367 unsigned frontbuffer_bits
)
5370 WARN_ON(!mutex_is_locked(&old
->base
.dev
->struct_mutex
));
5371 WARN_ON(!(old
->frontbuffer_bits
& frontbuffer_bits
));
5372 old
->frontbuffer_bits
&= ~frontbuffer_bits
;
5376 WARN_ON(!mutex_is_locked(&new->base
.dev
->struct_mutex
));
5377 WARN_ON(new->frontbuffer_bits
& frontbuffer_bits
);
5378 new->frontbuffer_bits
|= frontbuffer_bits
;
5382 /* All the new VM stuff */
5384 i915_gem_obj_offset(struct drm_i915_gem_object
*o
,
5385 struct i915_address_space
*vm
)
5387 struct drm_i915_private
*dev_priv
= o
->base
.dev
->dev_private
;
5388 struct i915_vma
*vma
;
5390 WARN_ON(vm
== &dev_priv
->mm
.aliasing_ppgtt
->base
);
5392 list_for_each_entry(vma
, &o
->vma_list
, vma_link
) {
5393 if (i915_is_ggtt(vma
->vm
) &&
5394 vma
->ggtt_view
.type
!= I915_GGTT_VIEW_NORMAL
)
5397 return vma
->node
.start
;
5400 WARN(1, "%s vma for this object not found.\n",
5401 i915_is_ggtt(vm
) ? "global" : "ppgtt");
5406 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object
*o
,
5407 const struct i915_ggtt_view
*view
)
5409 struct i915_address_space
*ggtt
= i915_obj_to_ggtt(o
);
5410 struct i915_vma
*vma
;
5412 list_for_each_entry(vma
, &o
->vma_list
, vma_link
)
5413 if (vma
->vm
== ggtt
&&
5414 i915_ggtt_view_equal(&vma
->ggtt_view
, view
))
5415 return vma
->node
.start
;
5417 WARN(1, "global vma for this object not found. (view=%u)\n", view
->type
);
5421 bool i915_gem_obj_bound(struct drm_i915_gem_object
*o
,
5422 struct i915_address_space
*vm
)
5424 struct i915_vma
*vma
;
5426 list_for_each_entry(vma
, &o
->vma_list
, vma_link
) {
5427 if (i915_is_ggtt(vma
->vm
) &&
5428 vma
->ggtt_view
.type
!= I915_GGTT_VIEW_NORMAL
)
5430 if (vma
->vm
== vm
&& drm_mm_node_allocated(&vma
->node
))
5437 bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object
*o
,
5438 const struct i915_ggtt_view
*view
)
5440 struct i915_address_space
*ggtt
= i915_obj_to_ggtt(o
);
5441 struct i915_vma
*vma
;
5443 list_for_each_entry(vma
, &o
->vma_list
, vma_link
)
5444 if (vma
->vm
== ggtt
&&
5445 i915_ggtt_view_equal(&vma
->ggtt_view
, view
) &&
5446 drm_mm_node_allocated(&vma
->node
))
5452 bool i915_gem_obj_bound_any(struct drm_i915_gem_object
*o
)
5454 struct i915_vma
*vma
;
5456 list_for_each_entry(vma
, &o
->vma_list
, vma_link
)
5457 if (drm_mm_node_allocated(&vma
->node
))
5463 unsigned long i915_gem_obj_size(struct drm_i915_gem_object
*o
,
5464 struct i915_address_space
*vm
)
5466 struct drm_i915_private
*dev_priv
= o
->base
.dev
->dev_private
;
5467 struct i915_vma
*vma
;
5469 WARN_ON(vm
== &dev_priv
->mm
.aliasing_ppgtt
->base
);
5471 BUG_ON(list_empty(&o
->vma_list
));
5473 list_for_each_entry(vma
, &o
->vma_list
, vma_link
) {
5474 if (i915_is_ggtt(vma
->vm
) &&
5475 vma
->ggtt_view
.type
!= I915_GGTT_VIEW_NORMAL
)
5478 return vma
->node
.size
;
5483 bool i915_gem_obj_is_pinned(struct drm_i915_gem_object
*obj
)
5485 struct i915_vma
*vma
;
5486 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
5487 if (vma
->pin_count
> 0)