2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/shmem_fs.h>
35 #include <linux/slab.h>
36 #include <linux/swap.h>
37 #include <linux/pci.h>
38 #include <linux/dma-buf.h>
40 static __must_check
int i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object
*obj
);
41 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
);
42 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
);
43 static __must_check
int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object
*obj
,
45 bool map_and_fenceable
);
46 static int i915_gem_phys_pwrite(struct drm_device
*dev
,
47 struct drm_i915_gem_object
*obj
,
48 struct drm_i915_gem_pwrite
*args
,
49 struct drm_file
*file
);
51 static void i915_gem_write_fence(struct drm_device
*dev
, int reg
,
52 struct drm_i915_gem_object
*obj
);
53 static void i915_gem_object_update_fence(struct drm_i915_gem_object
*obj
,
54 struct drm_i915_fence_reg
*fence
,
57 static int i915_gem_inactive_shrink(struct shrinker
*shrinker
,
58 struct shrink_control
*sc
);
59 static void i915_gem_object_truncate(struct drm_i915_gem_object
*obj
);
61 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object
*obj
)
64 i915_gem_release_mmap(obj
);
66 /* As we do not have an associated fence register, we will force
67 * a tiling change if we ever need to acquire one.
69 obj
->fence_dirty
= false;
70 obj
->fence_reg
= I915_FENCE_REG_NONE
;
73 /* some bookkeeping */
74 static void i915_gem_info_add_obj(struct drm_i915_private
*dev_priv
,
77 dev_priv
->mm
.object_count
++;
78 dev_priv
->mm
.object_memory
+= size
;
81 static void i915_gem_info_remove_obj(struct drm_i915_private
*dev_priv
,
84 dev_priv
->mm
.object_count
--;
85 dev_priv
->mm
.object_memory
-= size
;
89 i915_gem_wait_for_error(struct drm_device
*dev
)
91 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
92 struct completion
*x
= &dev_priv
->error_completion
;
96 if (!atomic_read(&dev_priv
->mm
.wedged
))
100 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
101 * userspace. If it takes that long something really bad is going on and
102 * we should simply try to bail out and fail as gracefully as possible.
104 ret
= wait_for_completion_interruptible_timeout(x
, 10*HZ
);
106 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
108 } else if (ret
< 0) {
112 if (atomic_read(&dev_priv
->mm
.wedged
)) {
113 /* GPU is hung, bump the completion count to account for
114 * the token we just consumed so that we never hit zero and
115 * end up waiting upon a subsequent completion event that
118 spin_lock_irqsave(&x
->wait
.lock
, flags
);
120 spin_unlock_irqrestore(&x
->wait
.lock
, flags
);
125 int i915_mutex_lock_interruptible(struct drm_device
*dev
)
129 ret
= i915_gem_wait_for_error(dev
);
133 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
137 WARN_ON(i915_verify_lists(dev
));
142 i915_gem_object_is_inactive(struct drm_i915_gem_object
*obj
)
148 i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
149 struct drm_file
*file
)
151 struct drm_i915_gem_init
*args
= data
;
153 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
156 if (args
->gtt_start
>= args
->gtt_end
||
157 (args
->gtt_end
| args
->gtt_start
) & (PAGE_SIZE
- 1))
160 /* GEM with user mode setting was never supported on ilk and later. */
161 if (INTEL_INFO(dev
)->gen
>= 5)
164 mutex_lock(&dev
->struct_mutex
);
165 i915_gem_init_global_gtt(dev
, args
->gtt_start
,
166 args
->gtt_end
, args
->gtt_end
);
167 mutex_unlock(&dev
->struct_mutex
);
173 i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
174 struct drm_file
*file
)
176 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
177 struct drm_i915_gem_get_aperture
*args
= data
;
178 struct drm_i915_gem_object
*obj
;
182 mutex_lock(&dev
->struct_mutex
);
183 list_for_each_entry(obj
, &dev_priv
->mm
.gtt_list
, gtt_list
)
185 pinned
+= obj
->gtt_space
->size
;
186 mutex_unlock(&dev
->struct_mutex
);
188 args
->aper_size
= dev_priv
->mm
.gtt_total
;
189 args
->aper_available_size
= args
->aper_size
- pinned
;
195 i915_gem_create(struct drm_file
*file
,
196 struct drm_device
*dev
,
200 struct drm_i915_gem_object
*obj
;
204 size
= roundup(size
, PAGE_SIZE
);
208 /* Allocate the new object */
209 obj
= i915_gem_alloc_object(dev
, size
);
213 ret
= drm_gem_handle_create(file
, &obj
->base
, &handle
);
215 drm_gem_object_release(&obj
->base
);
216 i915_gem_info_remove_obj(dev
->dev_private
, obj
->base
.size
);
221 /* drop reference from allocate - handle holds it now */
222 drm_gem_object_unreference(&obj
->base
);
223 trace_i915_gem_object_create(obj
);
230 i915_gem_dumb_create(struct drm_file
*file
,
231 struct drm_device
*dev
,
232 struct drm_mode_create_dumb
*args
)
234 /* have to work out size/pitch and return them */
235 args
->pitch
= ALIGN(args
->width
* ((args
->bpp
+ 7) / 8), 64);
236 args
->size
= args
->pitch
* args
->height
;
237 return i915_gem_create(file
, dev
,
238 args
->size
, &args
->handle
);
241 int i915_gem_dumb_destroy(struct drm_file
*file
,
242 struct drm_device
*dev
,
245 return drm_gem_handle_delete(file
, handle
);
249 * Creates a new mm object and returns a handle to it.
252 i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
253 struct drm_file
*file
)
255 struct drm_i915_gem_create
*args
= data
;
257 return i915_gem_create(file
, dev
,
258 args
->size
, &args
->handle
);
261 static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object
*obj
)
263 drm_i915_private_t
*dev_priv
= obj
->base
.dev
->dev_private
;
265 return dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_9_10_17
&&
266 obj
->tiling_mode
!= I915_TILING_NONE
;
270 __copy_to_user_swizzled(char __user
*cpu_vaddr
,
271 const char *gpu_vaddr
, int gpu_offset
,
274 int ret
, cpu_offset
= 0;
277 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
278 int this_length
= min(cacheline_end
- gpu_offset
, length
);
279 int swizzled_gpu_offset
= gpu_offset
^ 64;
281 ret
= __copy_to_user(cpu_vaddr
+ cpu_offset
,
282 gpu_vaddr
+ swizzled_gpu_offset
,
287 cpu_offset
+= this_length
;
288 gpu_offset
+= this_length
;
289 length
-= this_length
;
296 __copy_from_user_swizzled(char *gpu_vaddr
, int gpu_offset
,
297 const char __user
*cpu_vaddr
,
300 int ret
, cpu_offset
= 0;
303 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
304 int this_length
= min(cacheline_end
- gpu_offset
, length
);
305 int swizzled_gpu_offset
= gpu_offset
^ 64;
307 ret
= __copy_from_user(gpu_vaddr
+ swizzled_gpu_offset
,
308 cpu_vaddr
+ cpu_offset
,
313 cpu_offset
+= this_length
;
314 gpu_offset
+= this_length
;
315 length
-= this_length
;
321 /* Per-page copy function for the shmem pread fastpath.
322 * Flushes invalid cachelines before reading the target if
323 * needs_clflush is set. */
325 shmem_pread_fast(struct page
*page
, int shmem_page_offset
, int page_length
,
326 char __user
*user_data
,
327 bool page_do_bit17_swizzling
, bool needs_clflush
)
332 if (unlikely(page_do_bit17_swizzling
))
335 vaddr
= kmap_atomic(page
);
337 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
339 ret
= __copy_to_user_inatomic(user_data
,
340 vaddr
+ shmem_page_offset
,
342 kunmap_atomic(vaddr
);
348 shmem_clflush_swizzled_range(char *addr
, unsigned long length
,
351 if (unlikely(swizzled
)) {
352 unsigned long start
= (unsigned long) addr
;
353 unsigned long end
= (unsigned long) addr
+ length
;
355 /* For swizzling simply ensure that we always flush both
356 * channels. Lame, but simple and it works. Swizzled
357 * pwrite/pread is far from a hotpath - current userspace
358 * doesn't use it at all. */
359 start
= round_down(start
, 128);
360 end
= round_up(end
, 128);
362 drm_clflush_virt_range((void *)start
, end
- start
);
364 drm_clflush_virt_range(addr
, length
);
369 /* Only difference to the fast-path function is that this can handle bit17
370 * and uses non-atomic copy and kmap functions. */
372 shmem_pread_slow(struct page
*page
, int shmem_page_offset
, int page_length
,
373 char __user
*user_data
,
374 bool page_do_bit17_swizzling
, bool needs_clflush
)
381 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
383 page_do_bit17_swizzling
);
385 if (page_do_bit17_swizzling
)
386 ret
= __copy_to_user_swizzled(user_data
,
387 vaddr
, shmem_page_offset
,
390 ret
= __copy_to_user(user_data
,
391 vaddr
+ shmem_page_offset
,
399 i915_gem_shmem_pread(struct drm_device
*dev
,
400 struct drm_i915_gem_object
*obj
,
401 struct drm_i915_gem_pread
*args
,
402 struct drm_file
*file
)
404 struct address_space
*mapping
= obj
->base
.filp
->f_path
.dentry
->d_inode
->i_mapping
;
405 char __user
*user_data
;
408 int shmem_page_offset
, page_length
, ret
= 0;
409 int obj_do_bit17_swizzling
, page_do_bit17_swizzling
;
410 int hit_slowpath
= 0;
412 int needs_clflush
= 0;
415 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
418 obj_do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
420 if (!(obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
)) {
421 /* If we're not in the cpu read domain, set ourself into the gtt
422 * read domain and manually flush cachelines (if required). This
423 * optimizes for the case when the gpu will dirty the data
424 * anyway again before the next pread happens. */
425 if (obj
->cache_level
== I915_CACHE_NONE
)
427 ret
= i915_gem_object_set_to_gtt_domain(obj
, false);
432 offset
= args
->offset
;
437 /* Operation in this page
439 * shmem_page_offset = offset within page in shmem file
440 * page_length = bytes to copy for this page
442 shmem_page_offset
= offset_in_page(offset
);
443 page_length
= remain
;
444 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
445 page_length
= PAGE_SIZE
- shmem_page_offset
;
448 page
= obj
->pages
[offset
>> PAGE_SHIFT
];
451 page
= shmem_read_mapping_page(mapping
, offset
>> PAGE_SHIFT
);
459 page_do_bit17_swizzling
= obj_do_bit17_swizzling
&&
460 (page_to_phys(page
) & (1 << 17)) != 0;
462 ret
= shmem_pread_fast(page
, shmem_page_offset
, page_length
,
463 user_data
, page_do_bit17_swizzling
,
469 page_cache_get(page
);
470 mutex_unlock(&dev
->struct_mutex
);
473 ret
= fault_in_multipages_writeable(user_data
, remain
);
474 /* Userspace is tricking us, but we've already clobbered
475 * its pages with the prefault and promised to write the
476 * data up to the first fault. Hence ignore any errors
477 * and just continue. */
482 ret
= shmem_pread_slow(page
, shmem_page_offset
, page_length
,
483 user_data
, page_do_bit17_swizzling
,
486 mutex_lock(&dev
->struct_mutex
);
487 page_cache_release(page
);
489 mark_page_accessed(page
);
491 page_cache_release(page
);
498 remain
-= page_length
;
499 user_data
+= page_length
;
500 offset
+= page_length
;
505 /* Fixup: Kill any reinstated backing storage pages */
506 if (obj
->madv
== __I915_MADV_PURGED
)
507 i915_gem_object_truncate(obj
);
514 * Reads data from the object referenced by handle.
516 * On error, the contents of *data are undefined.
519 i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
520 struct drm_file
*file
)
522 struct drm_i915_gem_pread
*args
= data
;
523 struct drm_i915_gem_object
*obj
;
529 if (!access_ok(VERIFY_WRITE
,
530 (char __user
*)(uintptr_t)args
->data_ptr
,
534 ret
= i915_mutex_lock_interruptible(dev
);
538 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
539 if (&obj
->base
== NULL
) {
544 /* Bounds check source. */
545 if (args
->offset
> obj
->base
.size
||
546 args
->size
> obj
->base
.size
- args
->offset
) {
551 /* prime objects have no backing filp to GEM pread/pwrite
554 if (!obj
->base
.filp
) {
559 trace_i915_gem_object_pread(obj
, args
->offset
, args
->size
);
561 ret
= i915_gem_shmem_pread(dev
, obj
, args
, file
);
564 drm_gem_object_unreference(&obj
->base
);
566 mutex_unlock(&dev
->struct_mutex
);
570 /* This is the fast write path which cannot handle
571 * page faults in the source data
575 fast_user_write(struct io_mapping
*mapping
,
576 loff_t page_base
, int page_offset
,
577 char __user
*user_data
,
580 void __iomem
*vaddr_atomic
;
582 unsigned long unwritten
;
584 vaddr_atomic
= io_mapping_map_atomic_wc(mapping
, page_base
);
585 /* We can use the cpu mem copy function because this is X86. */
586 vaddr
= (void __force
*)vaddr_atomic
+ page_offset
;
587 unwritten
= __copy_from_user_inatomic_nocache(vaddr
,
589 io_mapping_unmap_atomic(vaddr_atomic
);
594 * This is the fast pwrite path, where we copy the data directly from the
595 * user into the GTT, uncached.
598 i915_gem_gtt_pwrite_fast(struct drm_device
*dev
,
599 struct drm_i915_gem_object
*obj
,
600 struct drm_i915_gem_pwrite
*args
,
601 struct drm_file
*file
)
603 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
605 loff_t offset
, page_base
;
606 char __user
*user_data
;
607 int page_offset
, page_length
, ret
;
609 ret
= i915_gem_object_pin(obj
, 0, true);
613 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
617 ret
= i915_gem_object_put_fence(obj
);
621 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
624 offset
= obj
->gtt_offset
+ args
->offset
;
627 /* Operation in this page
629 * page_base = page offset within aperture
630 * page_offset = offset within page
631 * page_length = bytes to copy for this page
633 page_base
= offset
& PAGE_MASK
;
634 page_offset
= offset_in_page(offset
);
635 page_length
= remain
;
636 if ((page_offset
+ remain
) > PAGE_SIZE
)
637 page_length
= PAGE_SIZE
- page_offset
;
639 /* If we get a fault while copying data, then (presumably) our
640 * source page isn't available. Return the error and we'll
641 * retry in the slow path.
643 if (fast_user_write(dev_priv
->mm
.gtt_mapping
, page_base
,
644 page_offset
, user_data
, page_length
)) {
649 remain
-= page_length
;
650 user_data
+= page_length
;
651 offset
+= page_length
;
655 i915_gem_object_unpin(obj
);
660 /* Per-page copy function for the shmem pwrite fastpath.
661 * Flushes invalid cachelines before writing to the target if
662 * needs_clflush_before is set and flushes out any written cachelines after
663 * writing if needs_clflush is set. */
665 shmem_pwrite_fast(struct page
*page
, int shmem_page_offset
, int page_length
,
666 char __user
*user_data
,
667 bool page_do_bit17_swizzling
,
668 bool needs_clflush_before
,
669 bool needs_clflush_after
)
674 if (unlikely(page_do_bit17_swizzling
))
677 vaddr
= kmap_atomic(page
);
678 if (needs_clflush_before
)
679 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
681 ret
= __copy_from_user_inatomic_nocache(vaddr
+ shmem_page_offset
,
684 if (needs_clflush_after
)
685 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
687 kunmap_atomic(vaddr
);
692 /* Only difference to the fast-path function is that this can handle bit17
693 * and uses non-atomic copy and kmap functions. */
695 shmem_pwrite_slow(struct page
*page
, int shmem_page_offset
, int page_length
,
696 char __user
*user_data
,
697 bool page_do_bit17_swizzling
,
698 bool needs_clflush_before
,
699 bool needs_clflush_after
)
705 if (unlikely(needs_clflush_before
|| page_do_bit17_swizzling
))
706 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
708 page_do_bit17_swizzling
);
709 if (page_do_bit17_swizzling
)
710 ret
= __copy_from_user_swizzled(vaddr
, shmem_page_offset
,
714 ret
= __copy_from_user(vaddr
+ shmem_page_offset
,
717 if (needs_clflush_after
)
718 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
720 page_do_bit17_swizzling
);
727 i915_gem_shmem_pwrite(struct drm_device
*dev
,
728 struct drm_i915_gem_object
*obj
,
729 struct drm_i915_gem_pwrite
*args
,
730 struct drm_file
*file
)
732 struct address_space
*mapping
= obj
->base
.filp
->f_path
.dentry
->d_inode
->i_mapping
;
735 char __user
*user_data
;
736 int shmem_page_offset
, page_length
, ret
= 0;
737 int obj_do_bit17_swizzling
, page_do_bit17_swizzling
;
738 int hit_slowpath
= 0;
739 int needs_clflush_after
= 0;
740 int needs_clflush_before
= 0;
743 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
746 obj_do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
748 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
749 /* If we're not in the cpu write domain, set ourself into the gtt
750 * write domain and manually flush cachelines (if required). This
751 * optimizes for the case when the gpu will use the data
752 * right away and we therefore have to clflush anyway. */
753 if (obj
->cache_level
== I915_CACHE_NONE
)
754 needs_clflush_after
= 1;
755 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
759 /* Same trick applies for invalidate partially written cachelines before
761 if (!(obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
)
762 && obj
->cache_level
== I915_CACHE_NONE
)
763 needs_clflush_before
= 1;
765 offset
= args
->offset
;
770 int partial_cacheline_write
;
772 /* Operation in this page
774 * shmem_page_offset = offset within page in shmem file
775 * page_length = bytes to copy for this page
777 shmem_page_offset
= offset_in_page(offset
);
779 page_length
= remain
;
780 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
781 page_length
= PAGE_SIZE
- shmem_page_offset
;
783 /* If we don't overwrite a cacheline completely we need to be
784 * careful to have up-to-date data by first clflushing. Don't
785 * overcomplicate things and flush the entire patch. */
786 partial_cacheline_write
= needs_clflush_before
&&
787 ((shmem_page_offset
| page_length
)
788 & (boot_cpu_data
.x86_clflush_size
- 1));
791 page
= obj
->pages
[offset
>> PAGE_SHIFT
];
794 page
= shmem_read_mapping_page(mapping
, offset
>> PAGE_SHIFT
);
802 page_do_bit17_swizzling
= obj_do_bit17_swizzling
&&
803 (page_to_phys(page
) & (1 << 17)) != 0;
805 ret
= shmem_pwrite_fast(page
, shmem_page_offset
, page_length
,
806 user_data
, page_do_bit17_swizzling
,
807 partial_cacheline_write
,
808 needs_clflush_after
);
813 page_cache_get(page
);
814 mutex_unlock(&dev
->struct_mutex
);
816 ret
= shmem_pwrite_slow(page
, shmem_page_offset
, page_length
,
817 user_data
, page_do_bit17_swizzling
,
818 partial_cacheline_write
,
819 needs_clflush_after
);
821 mutex_lock(&dev
->struct_mutex
);
822 page_cache_release(page
);
824 set_page_dirty(page
);
825 mark_page_accessed(page
);
827 page_cache_release(page
);
834 remain
-= page_length
;
835 user_data
+= page_length
;
836 offset
+= page_length
;
841 /* Fixup: Kill any reinstated backing storage pages */
842 if (obj
->madv
== __I915_MADV_PURGED
)
843 i915_gem_object_truncate(obj
);
844 /* and flush dirty cachelines in case the object isn't in the cpu write
846 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
847 i915_gem_clflush_object(obj
);
848 intel_gtt_chipset_flush();
852 if (needs_clflush_after
)
853 intel_gtt_chipset_flush();
859 * Writes data to the object referenced by handle.
861 * On error, the contents of the buffer that were to be modified are undefined.
864 i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
865 struct drm_file
*file
)
867 struct drm_i915_gem_pwrite
*args
= data
;
868 struct drm_i915_gem_object
*obj
;
874 if (!access_ok(VERIFY_READ
,
875 (char __user
*)(uintptr_t)args
->data_ptr
,
879 ret
= fault_in_multipages_readable((char __user
*)(uintptr_t)args
->data_ptr
,
884 ret
= i915_mutex_lock_interruptible(dev
);
888 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
889 if (&obj
->base
== NULL
) {
894 /* Bounds check destination. */
895 if (args
->offset
> obj
->base
.size
||
896 args
->size
> obj
->base
.size
- args
->offset
) {
901 /* prime objects have no backing filp to GEM pread/pwrite
904 if (!obj
->base
.filp
) {
909 trace_i915_gem_object_pwrite(obj
, args
->offset
, args
->size
);
912 /* We can only do the GTT pwrite on untiled buffers, as otherwise
913 * it would end up going through the fenced access, and we'll get
914 * different detiling behavior between reading and writing.
915 * pread/pwrite currently are reading and writing from the CPU
916 * perspective, requiring manual detiling by the client.
919 ret
= i915_gem_phys_pwrite(dev
, obj
, args
, file
);
923 if (obj
->gtt_space
&&
924 obj
->cache_level
== I915_CACHE_NONE
&&
925 obj
->tiling_mode
== I915_TILING_NONE
&&
926 obj
->map_and_fenceable
&&
927 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
928 ret
= i915_gem_gtt_pwrite_fast(dev
, obj
, args
, file
);
929 /* Note that the gtt paths might fail with non-page-backed user
930 * pointers (e.g. gtt mappings when moving data between
931 * textures). Fallback to the shmem path in that case. */
935 ret
= i915_gem_shmem_pwrite(dev
, obj
, args
, file
);
938 drm_gem_object_unreference(&obj
->base
);
940 mutex_unlock(&dev
->struct_mutex
);
945 * Called when user space prepares to use an object with the CPU, either
946 * through the mmap ioctl's mapping or a GTT mapping.
949 i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
950 struct drm_file
*file
)
952 struct drm_i915_gem_set_domain
*args
= data
;
953 struct drm_i915_gem_object
*obj
;
954 uint32_t read_domains
= args
->read_domains
;
955 uint32_t write_domain
= args
->write_domain
;
958 /* Only handle setting domains to types used by the CPU. */
959 if (write_domain
& I915_GEM_GPU_DOMAINS
)
962 if (read_domains
& I915_GEM_GPU_DOMAINS
)
965 /* Having something in the write domain implies it's in the read
966 * domain, and only that read domain. Enforce that in the request.
968 if (write_domain
!= 0 && read_domains
!= write_domain
)
971 ret
= i915_mutex_lock_interruptible(dev
);
975 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
976 if (&obj
->base
== NULL
) {
981 if (read_domains
& I915_GEM_DOMAIN_GTT
) {
982 ret
= i915_gem_object_set_to_gtt_domain(obj
, write_domain
!= 0);
984 /* Silently promote "you're not bound, there was nothing to do"
985 * to success, since the client was just asking us to
986 * make sure everything was done.
991 ret
= i915_gem_object_set_to_cpu_domain(obj
, write_domain
!= 0);
994 drm_gem_object_unreference(&obj
->base
);
996 mutex_unlock(&dev
->struct_mutex
);
1001 * Called when user space has done writes to this buffer
1004 i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1005 struct drm_file
*file
)
1007 struct drm_i915_gem_sw_finish
*args
= data
;
1008 struct drm_i915_gem_object
*obj
;
1011 ret
= i915_mutex_lock_interruptible(dev
);
1015 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1016 if (&obj
->base
== NULL
) {
1021 /* Pinned buffers may be scanout, so flush the cache */
1023 i915_gem_object_flush_cpu_write_domain(obj
);
1025 drm_gem_object_unreference(&obj
->base
);
1027 mutex_unlock(&dev
->struct_mutex
);
1032 * Maps the contents of an object, returning the address it is mapped
1035 * While the mapping holds a reference on the contents of the object, it doesn't
1036 * imply a ref on the object itself.
1039 i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1040 struct drm_file
*file
)
1042 struct drm_i915_gem_mmap
*args
= data
;
1043 struct drm_gem_object
*obj
;
1046 obj
= drm_gem_object_lookup(dev
, file
, args
->handle
);
1050 /* prime objects have no backing filp to GEM mmap
1054 drm_gem_object_unreference_unlocked(obj
);
1058 addr
= vm_mmap(obj
->filp
, 0, args
->size
,
1059 PROT_READ
| PROT_WRITE
, MAP_SHARED
,
1061 drm_gem_object_unreference_unlocked(obj
);
1062 if (IS_ERR((void *)addr
))
1065 args
->addr_ptr
= (uint64_t) addr
;
1071 * i915_gem_fault - fault a page into the GTT
1072 * vma: VMA in question
1075 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1076 * from userspace. The fault handler takes care of binding the object to
1077 * the GTT (if needed), allocating and programming a fence register (again,
1078 * only if needed based on whether the old reg is still valid or the object
1079 * is tiled) and inserting a new PTE into the faulting process.
1081 * Note that the faulting process may involve evicting existing objects
1082 * from the GTT and/or fence registers to make room. So performance may
1083 * suffer if the GTT working set is large or there are few fence registers
1086 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
)
1088 struct drm_i915_gem_object
*obj
= to_intel_bo(vma
->vm_private_data
);
1089 struct drm_device
*dev
= obj
->base
.dev
;
1090 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1091 pgoff_t page_offset
;
1094 bool write
= !!(vmf
->flags
& FAULT_FLAG_WRITE
);
1096 /* We don't use vmf->pgoff since that has the fake offset */
1097 page_offset
= ((unsigned long)vmf
->virtual_address
- vma
->vm_start
) >>
1100 ret
= i915_mutex_lock_interruptible(dev
);
1104 trace_i915_gem_object_fault(obj
, page_offset
, true, write
);
1106 /* Now bind it into the GTT if needed */
1107 if (!obj
->map_and_fenceable
) {
1108 ret
= i915_gem_object_unbind(obj
);
1112 if (!obj
->gtt_space
) {
1113 ret
= i915_gem_object_bind_to_gtt(obj
, 0, true);
1117 ret
= i915_gem_object_set_to_gtt_domain(obj
, write
);
1122 if (!obj
->has_global_gtt_mapping
)
1123 i915_gem_gtt_bind_object(obj
, obj
->cache_level
);
1125 ret
= i915_gem_object_get_fence(obj
);
1129 if (i915_gem_object_is_inactive(obj
))
1130 list_move_tail(&obj
->mm_list
, &dev_priv
->mm
.inactive_list
);
1132 obj
->fault_mappable
= true;
1134 pfn
= ((dev_priv
->mm
.gtt_base_addr
+ obj
->gtt_offset
) >> PAGE_SHIFT
) +
1137 /* Finally, remap it using the new GTT offset */
1138 ret
= vm_insert_pfn(vma
, (unsigned long)vmf
->virtual_address
, pfn
);
1140 mutex_unlock(&dev
->struct_mutex
);
1144 /* If this -EIO is due to a gpu hang, give the reset code a
1145 * chance to clean up the mess. Otherwise return the proper
1147 if (!atomic_read(&dev_priv
->mm
.wedged
))
1148 return VM_FAULT_SIGBUS
;
1150 /* Give the error handler a chance to run and move the
1151 * objects off the GPU active list. Next time we service the
1152 * fault, we should be able to transition the page into the
1153 * GTT without touching the GPU (and so avoid further
1154 * EIO/EGAIN). If the GPU is wedged, then there is no issue
1155 * with coherency, just lost writes.
1161 return VM_FAULT_NOPAGE
;
1163 return VM_FAULT_OOM
;
1165 return VM_FAULT_SIGBUS
;
1170 * i915_gem_release_mmap - remove physical page mappings
1171 * @obj: obj in question
1173 * Preserve the reservation of the mmapping with the DRM core code, but
1174 * relinquish ownership of the pages back to the system.
1176 * It is vital that we remove the page mapping if we have mapped a tiled
1177 * object through the GTT and then lose the fence register due to
1178 * resource pressure. Similarly if the object has been moved out of the
1179 * aperture, than pages mapped into userspace must be revoked. Removing the
1180 * mapping will then trigger a page fault on the next user access, allowing
1181 * fixup by i915_gem_fault().
1184 i915_gem_release_mmap(struct drm_i915_gem_object
*obj
)
1186 if (!obj
->fault_mappable
)
1189 if (obj
->base
.dev
->dev_mapping
)
1190 unmap_mapping_range(obj
->base
.dev
->dev_mapping
,
1191 (loff_t
)obj
->base
.map_list
.hash
.key
<<PAGE_SHIFT
,
1194 obj
->fault_mappable
= false;
1198 i915_gem_get_gtt_size(struct drm_device
*dev
, uint32_t size
, int tiling_mode
)
1202 if (INTEL_INFO(dev
)->gen
>= 4 ||
1203 tiling_mode
== I915_TILING_NONE
)
1206 /* Previous chips need a power-of-two fence region when tiling */
1207 if (INTEL_INFO(dev
)->gen
== 3)
1208 gtt_size
= 1024*1024;
1210 gtt_size
= 512*1024;
1212 while (gtt_size
< size
)
1219 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1220 * @obj: object to check
1222 * Return the required GTT alignment for an object, taking into account
1223 * potential fence register mapping.
1226 i915_gem_get_gtt_alignment(struct drm_device
*dev
,
1231 * Minimum alignment is 4k (GTT page size), but might be greater
1232 * if a fence register is needed for the object.
1234 if (INTEL_INFO(dev
)->gen
>= 4 ||
1235 tiling_mode
== I915_TILING_NONE
)
1239 * Previous chips need to be aligned to the size of the smallest
1240 * fence register that can contain the object.
1242 return i915_gem_get_gtt_size(dev
, size
, tiling_mode
);
1246 * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an
1249 * @size: size of the object
1250 * @tiling_mode: tiling mode of the object
1252 * Return the required GTT alignment for an object, only taking into account
1253 * unfenced tiled surface requirements.
1256 i915_gem_get_unfenced_gtt_alignment(struct drm_device
*dev
,
1261 * Minimum alignment is 4k (GTT page size) for sane hw.
1263 if (INTEL_INFO(dev
)->gen
>= 4 || IS_G33(dev
) ||
1264 tiling_mode
== I915_TILING_NONE
)
1267 /* Previous hardware however needs to be aligned to a power-of-two
1268 * tile height. The simplest method for determining this is to reuse
1269 * the power-of-tile object size.
1271 return i915_gem_get_gtt_size(dev
, size
, tiling_mode
);
1275 i915_gem_mmap_gtt(struct drm_file
*file
,
1276 struct drm_device
*dev
,
1280 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1281 struct drm_i915_gem_object
*obj
;
1284 ret
= i915_mutex_lock_interruptible(dev
);
1288 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, handle
));
1289 if (&obj
->base
== NULL
) {
1294 if (obj
->base
.size
> dev_priv
->mm
.gtt_mappable_end
) {
1299 if (obj
->madv
!= I915_MADV_WILLNEED
) {
1300 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1305 if (!obj
->base
.map_list
.map
) {
1306 ret
= drm_gem_create_mmap_offset(&obj
->base
);
1311 *offset
= (u64
)obj
->base
.map_list
.hash
.key
<< PAGE_SHIFT
;
1314 drm_gem_object_unreference(&obj
->base
);
1316 mutex_unlock(&dev
->struct_mutex
);
1321 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1323 * @data: GTT mapping ioctl data
1324 * @file: GEM object info
1326 * Simply returns the fake offset to userspace so it can mmap it.
1327 * The mmap call will end up in drm_gem_mmap(), which will set things
1328 * up so we can get faults in the handler above.
1330 * The fault handler will take care of binding the object into the GTT
1331 * (since it may have been evicted to make room for something), allocating
1332 * a fence register, and mapping the appropriate aperture address into
1336 i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
1337 struct drm_file
*file
)
1339 struct drm_i915_gem_mmap_gtt
*args
= data
;
1341 return i915_gem_mmap_gtt(file
, dev
, args
->handle
, &args
->offset
);
1345 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object
*obj
,
1349 struct address_space
*mapping
;
1350 struct inode
*inode
;
1353 if (obj
->pages
|| obj
->sg_table
)
1356 /* Get the list of pages out of our struct file. They'll be pinned
1357 * at this point until we release them.
1359 page_count
= obj
->base
.size
/ PAGE_SIZE
;
1360 BUG_ON(obj
->pages
!= NULL
);
1361 obj
->pages
= drm_malloc_ab(page_count
, sizeof(struct page
*));
1362 if (obj
->pages
== NULL
)
1365 inode
= obj
->base
.filp
->f_path
.dentry
->d_inode
;
1366 mapping
= inode
->i_mapping
;
1367 gfpmask
|= mapping_gfp_mask(mapping
);
1369 for (i
= 0; i
< page_count
; i
++) {
1370 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfpmask
);
1374 obj
->pages
[i
] = page
;
1377 if (i915_gem_object_needs_bit17_swizzle(obj
))
1378 i915_gem_object_do_bit_17_swizzle(obj
);
1384 page_cache_release(obj
->pages
[i
]);
1386 drm_free_large(obj
->pages
);
1388 return PTR_ERR(page
);
1392 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object
*obj
)
1394 int page_count
= obj
->base
.size
/ PAGE_SIZE
;
1400 BUG_ON(obj
->madv
== __I915_MADV_PURGED
);
1402 if (i915_gem_object_needs_bit17_swizzle(obj
))
1403 i915_gem_object_save_bit_17_swizzle(obj
);
1405 if (obj
->madv
== I915_MADV_DONTNEED
)
1408 for (i
= 0; i
< page_count
; i
++) {
1410 set_page_dirty(obj
->pages
[i
]);
1412 if (obj
->madv
== I915_MADV_WILLNEED
)
1413 mark_page_accessed(obj
->pages
[i
]);
1415 page_cache_release(obj
->pages
[i
]);
1419 drm_free_large(obj
->pages
);
1424 i915_gem_object_move_to_active(struct drm_i915_gem_object
*obj
,
1425 struct intel_ring_buffer
*ring
,
1428 struct drm_device
*dev
= obj
->base
.dev
;
1429 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1431 BUG_ON(ring
== NULL
);
1434 /* Add a reference if we're newly entering the active list. */
1436 drm_gem_object_reference(&obj
->base
);
1440 /* Move from whatever list we were on to the tail of execution. */
1441 list_move_tail(&obj
->mm_list
, &dev_priv
->mm
.active_list
);
1442 list_move_tail(&obj
->ring_list
, &ring
->active_list
);
1444 obj
->last_rendering_seqno
= seqno
;
1446 if (obj
->fenced_gpu_access
) {
1447 obj
->last_fenced_seqno
= seqno
;
1449 /* Bump MRU to take account of the delayed flush */
1450 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
1451 struct drm_i915_fence_reg
*reg
;
1453 reg
= &dev_priv
->fence_regs
[obj
->fence_reg
];
1454 list_move_tail(®
->lru_list
,
1455 &dev_priv
->mm
.fence_list
);
1461 i915_gem_object_move_off_active(struct drm_i915_gem_object
*obj
)
1463 list_del_init(&obj
->ring_list
);
1464 obj
->last_rendering_seqno
= 0;
1465 obj
->last_fenced_seqno
= 0;
1469 i915_gem_object_move_to_flushing(struct drm_i915_gem_object
*obj
)
1471 struct drm_device
*dev
= obj
->base
.dev
;
1472 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1474 BUG_ON(!obj
->active
);
1475 list_move_tail(&obj
->mm_list
, &dev_priv
->mm
.flushing_list
);
1477 i915_gem_object_move_off_active(obj
);
1481 i915_gem_object_move_to_inactive(struct drm_i915_gem_object
*obj
)
1483 struct drm_device
*dev
= obj
->base
.dev
;
1484 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1486 list_move_tail(&obj
->mm_list
, &dev_priv
->mm
.inactive_list
);
1488 BUG_ON(!list_empty(&obj
->gpu_write_list
));
1489 BUG_ON(!obj
->active
);
1492 i915_gem_object_move_off_active(obj
);
1493 obj
->fenced_gpu_access
= false;
1496 obj
->pending_gpu_write
= false;
1497 drm_gem_object_unreference(&obj
->base
);
1499 WARN_ON(i915_verify_lists(dev
));
1502 /* Immediately discard the backing storage */
1504 i915_gem_object_truncate(struct drm_i915_gem_object
*obj
)
1506 struct inode
*inode
;
1508 /* Our goal here is to return as much of the memory as
1509 * is possible back to the system as we are called from OOM.
1510 * To do this we must instruct the shmfs to drop all of its
1511 * backing pages, *now*.
1513 inode
= obj
->base
.filp
->f_path
.dentry
->d_inode
;
1514 shmem_truncate_range(inode
, 0, (loff_t
)-1);
1516 if (obj
->base
.map_list
.map
)
1517 drm_gem_free_mmap_offset(&obj
->base
);
1519 obj
->madv
= __I915_MADV_PURGED
;
1523 i915_gem_object_is_purgeable(struct drm_i915_gem_object
*obj
)
1525 return obj
->madv
== I915_MADV_DONTNEED
;
1529 i915_gem_process_flushing_list(struct intel_ring_buffer
*ring
,
1530 uint32_t flush_domains
)
1532 struct drm_i915_gem_object
*obj
, *next
;
1534 list_for_each_entry_safe(obj
, next
,
1535 &ring
->gpu_write_list
,
1537 if (obj
->base
.write_domain
& flush_domains
) {
1538 uint32_t old_write_domain
= obj
->base
.write_domain
;
1540 obj
->base
.write_domain
= 0;
1541 list_del_init(&obj
->gpu_write_list
);
1542 i915_gem_object_move_to_active(obj
, ring
,
1543 i915_gem_next_request_seqno(ring
));
1545 trace_i915_gem_object_change_domain(obj
,
1546 obj
->base
.read_domains
,
1553 i915_gem_get_seqno(struct drm_device
*dev
)
1555 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1556 u32 seqno
= dev_priv
->next_seqno
;
1558 /* reserve 0 for non-seqno */
1559 if (++dev_priv
->next_seqno
== 0)
1560 dev_priv
->next_seqno
= 1;
1566 i915_gem_next_request_seqno(struct intel_ring_buffer
*ring
)
1568 if (ring
->outstanding_lazy_request
== 0)
1569 ring
->outstanding_lazy_request
= i915_gem_get_seqno(ring
->dev
);
1571 return ring
->outstanding_lazy_request
;
1575 i915_add_request(struct intel_ring_buffer
*ring
,
1576 struct drm_file
*file
,
1577 struct drm_i915_gem_request
*request
)
1579 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
1581 u32 request_ring_position
;
1586 * Emit any outstanding flushes - execbuf can fail to emit the flush
1587 * after having emitted the batchbuffer command. Hence we need to fix
1588 * things up similar to emitting the lazy request. The difference here
1589 * is that the flush _must_ happen before the next request, no matter
1592 if (ring
->gpu_caches_dirty
) {
1593 ret
= i915_gem_flush_ring(ring
, 0, I915_GEM_GPU_DOMAINS
);
1597 ring
->gpu_caches_dirty
= false;
1600 BUG_ON(request
== NULL
);
1601 seqno
= i915_gem_next_request_seqno(ring
);
1603 /* Record the position of the start of the request so that
1604 * should we detect the updated seqno part-way through the
1605 * GPU processing the request, we never over-estimate the
1606 * position of the head.
1608 request_ring_position
= intel_ring_get_tail(ring
);
1610 ret
= ring
->add_request(ring
, &seqno
);
1614 trace_i915_gem_request_add(ring
, seqno
);
1616 request
->seqno
= seqno
;
1617 request
->ring
= ring
;
1618 request
->tail
= request_ring_position
;
1619 request
->emitted_jiffies
= jiffies
;
1620 was_empty
= list_empty(&ring
->request_list
);
1621 list_add_tail(&request
->list
, &ring
->request_list
);
1624 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
1626 spin_lock(&file_priv
->mm
.lock
);
1627 request
->file_priv
= file_priv
;
1628 list_add_tail(&request
->client_list
,
1629 &file_priv
->mm
.request_list
);
1630 spin_unlock(&file_priv
->mm
.lock
);
1633 ring
->outstanding_lazy_request
= 0;
1635 if (!dev_priv
->mm
.suspended
) {
1636 if (i915_enable_hangcheck
) {
1637 mod_timer(&dev_priv
->hangcheck_timer
,
1639 msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD
));
1642 queue_delayed_work(dev_priv
->wq
,
1643 &dev_priv
->mm
.retire_work
, HZ
);
1646 WARN_ON(!list_empty(&ring
->gpu_write_list
));
1652 i915_gem_request_remove_from_client(struct drm_i915_gem_request
*request
)
1654 struct drm_i915_file_private
*file_priv
= request
->file_priv
;
1659 spin_lock(&file_priv
->mm
.lock
);
1660 if (request
->file_priv
) {
1661 list_del(&request
->client_list
);
1662 request
->file_priv
= NULL
;
1664 spin_unlock(&file_priv
->mm
.lock
);
1667 static void i915_gem_reset_ring_lists(struct drm_i915_private
*dev_priv
,
1668 struct intel_ring_buffer
*ring
)
1670 while (!list_empty(&ring
->request_list
)) {
1671 struct drm_i915_gem_request
*request
;
1673 request
= list_first_entry(&ring
->request_list
,
1674 struct drm_i915_gem_request
,
1677 list_del(&request
->list
);
1678 i915_gem_request_remove_from_client(request
);
1682 while (!list_empty(&ring
->active_list
)) {
1683 struct drm_i915_gem_object
*obj
;
1685 obj
= list_first_entry(&ring
->active_list
,
1686 struct drm_i915_gem_object
,
1689 obj
->base
.write_domain
= 0;
1690 list_del_init(&obj
->gpu_write_list
);
1691 i915_gem_object_move_to_inactive(obj
);
1695 static void i915_gem_reset_fences(struct drm_device
*dev
)
1697 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1700 for (i
= 0; i
< dev_priv
->num_fence_regs
; i
++) {
1701 struct drm_i915_fence_reg
*reg
= &dev_priv
->fence_regs
[i
];
1703 i915_gem_write_fence(dev
, i
, NULL
);
1706 i915_gem_object_fence_lost(reg
->obj
);
1710 INIT_LIST_HEAD(®
->lru_list
);
1713 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
1716 void i915_gem_reset(struct drm_device
*dev
)
1718 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1719 struct drm_i915_gem_object
*obj
;
1720 struct intel_ring_buffer
*ring
;
1723 for_each_ring(ring
, dev_priv
, i
)
1724 i915_gem_reset_ring_lists(dev_priv
, ring
);
1726 /* Remove anything from the flushing lists. The GPU cache is likely
1727 * to be lost on reset along with the data, so simply move the
1728 * lost bo to the inactive list.
1730 while (!list_empty(&dev_priv
->mm
.flushing_list
)) {
1731 obj
= list_first_entry(&dev_priv
->mm
.flushing_list
,
1732 struct drm_i915_gem_object
,
1735 obj
->base
.write_domain
= 0;
1736 list_del_init(&obj
->gpu_write_list
);
1737 i915_gem_object_move_to_inactive(obj
);
1740 /* Move everything out of the GPU domains to ensure we do any
1741 * necessary invalidation upon reuse.
1743 list_for_each_entry(obj
,
1744 &dev_priv
->mm
.inactive_list
,
1747 obj
->base
.read_domains
&= ~I915_GEM_GPU_DOMAINS
;
1750 /* The fence registers are invalidated so clear them out */
1751 i915_gem_reset_fences(dev
);
1755 * This function clears the request list as sequence numbers are passed.
1758 i915_gem_retire_requests_ring(struct intel_ring_buffer
*ring
)
1763 if (list_empty(&ring
->request_list
))
1766 WARN_ON(i915_verify_lists(ring
->dev
));
1768 seqno
= ring
->get_seqno(ring
);
1770 for (i
= 0; i
< ARRAY_SIZE(ring
->sync_seqno
); i
++)
1771 if (seqno
>= ring
->sync_seqno
[i
])
1772 ring
->sync_seqno
[i
] = 0;
1774 while (!list_empty(&ring
->request_list
)) {
1775 struct drm_i915_gem_request
*request
;
1777 request
= list_first_entry(&ring
->request_list
,
1778 struct drm_i915_gem_request
,
1781 if (!i915_seqno_passed(seqno
, request
->seqno
))
1784 trace_i915_gem_request_retire(ring
, request
->seqno
);
1785 /* We know the GPU must have read the request to have
1786 * sent us the seqno + interrupt, so use the position
1787 * of tail of the request to update the last known position
1790 ring
->last_retired_head
= request
->tail
;
1792 list_del(&request
->list
);
1793 i915_gem_request_remove_from_client(request
);
1797 /* Move any buffers on the active list that are no longer referenced
1798 * by the ringbuffer to the flushing/inactive lists as appropriate.
1800 while (!list_empty(&ring
->active_list
)) {
1801 struct drm_i915_gem_object
*obj
;
1803 obj
= list_first_entry(&ring
->active_list
,
1804 struct drm_i915_gem_object
,
1807 if (!i915_seqno_passed(seqno
, obj
->last_rendering_seqno
))
1810 if (obj
->base
.write_domain
!= 0)
1811 i915_gem_object_move_to_flushing(obj
);
1813 i915_gem_object_move_to_inactive(obj
);
1816 if (unlikely(ring
->trace_irq_seqno
&&
1817 i915_seqno_passed(seqno
, ring
->trace_irq_seqno
))) {
1818 ring
->irq_put(ring
);
1819 ring
->trace_irq_seqno
= 0;
1822 WARN_ON(i915_verify_lists(ring
->dev
));
1826 i915_gem_retire_requests(struct drm_device
*dev
)
1828 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1829 struct intel_ring_buffer
*ring
;
1832 for_each_ring(ring
, dev_priv
, i
)
1833 i915_gem_retire_requests_ring(ring
);
1837 i915_gem_retire_work_handler(struct work_struct
*work
)
1839 drm_i915_private_t
*dev_priv
;
1840 struct drm_device
*dev
;
1841 struct intel_ring_buffer
*ring
;
1845 dev_priv
= container_of(work
, drm_i915_private_t
,
1846 mm
.retire_work
.work
);
1847 dev
= dev_priv
->dev
;
1849 /* Come back later if the device is busy... */
1850 if (!mutex_trylock(&dev
->struct_mutex
)) {
1851 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, HZ
);
1855 i915_gem_retire_requests(dev
);
1857 /* Send a periodic flush down the ring so we don't hold onto GEM
1858 * objects indefinitely.
1861 for_each_ring(ring
, dev_priv
, i
) {
1862 if (ring
->gpu_caches_dirty
) {
1863 struct drm_i915_gem_request
*request
;
1865 request
= kzalloc(sizeof(*request
), GFP_KERNEL
);
1866 if (request
== NULL
||
1867 i915_add_request(ring
, NULL
, request
))
1871 idle
&= list_empty(&ring
->request_list
);
1874 if (!dev_priv
->mm
.suspended
&& !idle
)
1875 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, HZ
);
1877 mutex_unlock(&dev
->struct_mutex
);
1881 i915_gem_check_wedge(struct drm_i915_private
*dev_priv
,
1884 if (atomic_read(&dev_priv
->mm
.wedged
)) {
1885 struct completion
*x
= &dev_priv
->error_completion
;
1886 bool recovery_complete
;
1887 unsigned long flags
;
1889 /* Give the error handler a chance to run. */
1890 spin_lock_irqsave(&x
->wait
.lock
, flags
);
1891 recovery_complete
= x
->done
> 0;
1892 spin_unlock_irqrestore(&x
->wait
.lock
, flags
);
1894 /* Non-interruptible callers can't handle -EAGAIN, hence return
1895 * -EIO unconditionally for these. */
1899 /* Recovery complete, but still wedged means reset failure. */
1900 if (recovery_complete
)
1910 * Compare seqno against outstanding lazy request. Emit a request if they are
1914 i915_gem_check_olr(struct intel_ring_buffer
*ring
, u32 seqno
)
1918 BUG_ON(!mutex_is_locked(&ring
->dev
->struct_mutex
));
1920 if (seqno
== ring
->outstanding_lazy_request
) {
1921 struct drm_i915_gem_request
*request
;
1923 request
= kzalloc(sizeof(*request
), GFP_KERNEL
);
1924 if (request
== NULL
)
1927 ret
= i915_add_request(ring
, NULL
, request
);
1933 BUG_ON(seqno
!= request
->seqno
);
1940 * __wait_seqno - wait until execution of seqno has finished
1941 * @ring: the ring expected to report seqno
1943 * @interruptible: do an interruptible wait (normally yes)
1944 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
1946 * Returns 0 if the seqno was found within the alloted time. Else returns the
1947 * errno with remaining time filled in timeout argument.
1949 static int __wait_seqno(struct intel_ring_buffer
*ring
, u32 seqno
,
1950 bool interruptible
, struct timespec
*timeout
)
1952 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
1953 struct timespec before
, now
, wait_time
={1,0};
1954 unsigned long timeout_jiffies
;
1956 bool wait_forever
= true;
1959 if (i915_seqno_passed(ring
->get_seqno(ring
), seqno
))
1962 trace_i915_gem_request_wait_begin(ring
, seqno
);
1964 if (timeout
!= NULL
) {
1965 wait_time
= *timeout
;
1966 wait_forever
= false;
1969 timeout_jiffies
= timespec_to_jiffies(&wait_time
);
1971 if (WARN_ON(!ring
->irq_get(ring
)))
1974 /* Record current time in case interrupted by signal, or wedged * */
1975 getrawmonotonic(&before
);
1978 (i915_seqno_passed(ring->get_seqno(ring), seqno) || \
1979 atomic_read(&dev_priv->mm.wedged))
1982 end
= wait_event_interruptible_timeout(ring
->irq_queue
,
1986 end
= wait_event_timeout(ring
->irq_queue
, EXIT_COND
,
1989 ret
= i915_gem_check_wedge(dev_priv
, interruptible
);
1992 } while (end
== 0 && wait_forever
);
1994 getrawmonotonic(&now
);
1996 ring
->irq_put(ring
);
1997 trace_i915_gem_request_wait_end(ring
, seqno
);
2001 struct timespec sleep_time
= timespec_sub(now
, before
);
2002 *timeout
= timespec_sub(*timeout
, sleep_time
);
2006 case -EAGAIN
: /* Wedged */
2007 case -ERESTARTSYS
: /* Signal */
2009 case 0: /* Timeout */
2011 set_normalized_timespec(timeout
, 0, 0);
2013 default: /* Completed */
2014 WARN_ON(end
< 0); /* We're not aware of other errors */
2020 * Waits for a sequence number to be signaled, and cleans up the
2021 * request and object lists appropriately for that event.
2024 i915_wait_seqno(struct intel_ring_buffer
*ring
, uint32_t seqno
)
2026 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
2031 ret
= i915_gem_check_wedge(dev_priv
, dev_priv
->mm
.interruptible
);
2035 ret
= i915_gem_check_olr(ring
, seqno
);
2039 ret
= __wait_seqno(ring
, seqno
, dev_priv
->mm
.interruptible
, NULL
);
2045 * Ensures that all rendering to the object has completed and the object is
2046 * safe to unbind from the GTT or access from the CPU.
2049 i915_gem_object_wait_rendering(struct drm_i915_gem_object
*obj
)
2053 /* This function only exists to support waiting for existing rendering,
2054 * not for emitting required flushes.
2056 BUG_ON((obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
) != 0);
2058 /* If there is rendering queued on the buffer being evicted, wait for
2062 ret
= i915_wait_seqno(obj
->ring
, obj
->last_rendering_seqno
);
2065 i915_gem_retire_requests_ring(obj
->ring
);
2072 * Ensures that an object will eventually get non-busy by flushing any required
2073 * write domains, emitting any outstanding lazy request and retiring and
2074 * completed requests.
2077 i915_gem_object_flush_active(struct drm_i915_gem_object
*obj
)
2082 ret
= i915_gem_object_flush_gpu_write_domain(obj
);
2086 ret
= i915_gem_check_olr(obj
->ring
,
2087 obj
->last_rendering_seqno
);
2090 i915_gem_retire_requests_ring(obj
->ring
);
2097 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2098 * @DRM_IOCTL_ARGS: standard ioctl arguments
2100 * Returns 0 if successful, else an error is returned with the remaining time in
2101 * the timeout parameter.
2102 * -ETIME: object is still busy after timeout
2103 * -ERESTARTSYS: signal interrupted the wait
2104 * -ENONENT: object doesn't exist
2105 * Also possible, but rare:
2106 * -EAGAIN: GPU wedged
2108 * -ENODEV: Internal IRQ fail
2109 * -E?: The add request failed
2111 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2112 * non-zero timeout parameter the wait ioctl will wait for the given number of
2113 * nanoseconds on an object becoming unbusy. Since the wait itself does so
2114 * without holding struct_mutex the object may become re-busied before this
2115 * function completes. A similar but shorter * race condition exists in the busy
2119 i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
, struct drm_file
*file
)
2121 struct drm_i915_gem_wait
*args
= data
;
2122 struct drm_i915_gem_object
*obj
;
2123 struct intel_ring_buffer
*ring
= NULL
;
2124 struct timespec timeout_stack
, *timeout
= NULL
;
2128 if (args
->timeout_ns
>= 0) {
2129 timeout_stack
= ns_to_timespec(args
->timeout_ns
);
2130 timeout
= &timeout_stack
;
2133 ret
= i915_mutex_lock_interruptible(dev
);
2137 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->bo_handle
));
2138 if (&obj
->base
== NULL
) {
2139 mutex_unlock(&dev
->struct_mutex
);
2143 /* Need to make sure the object gets inactive eventually. */
2144 ret
= i915_gem_object_flush_active(obj
);
2149 seqno
= obj
->last_rendering_seqno
;
2156 /* Do this after OLR check to make sure we make forward progress polling
2157 * on this IOCTL with a 0 timeout (like busy ioctl)
2159 if (!args
->timeout_ns
) {
2164 drm_gem_object_unreference(&obj
->base
);
2165 mutex_unlock(&dev
->struct_mutex
);
2167 ret
= __wait_seqno(ring
, seqno
, true, timeout
);
2169 WARN_ON(!timespec_valid(timeout
));
2170 args
->timeout_ns
= timespec_to_ns(timeout
);
2175 drm_gem_object_unreference(&obj
->base
);
2176 mutex_unlock(&dev
->struct_mutex
);
2181 * i915_gem_object_sync - sync an object to a ring.
2183 * @obj: object which may be in use on another ring.
2184 * @to: ring we wish to use the object on. May be NULL.
2186 * This code is meant to abstract object synchronization with the GPU.
2187 * Calling with NULL implies synchronizing the object with the CPU
2188 * rather than a particular GPU ring.
2190 * Returns 0 if successful, else propagates up the lower layer error.
2193 i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
2194 struct intel_ring_buffer
*to
)
2196 struct intel_ring_buffer
*from
= obj
->ring
;
2200 if (from
== NULL
|| to
== from
)
2203 if (to
== NULL
|| !i915_semaphore_is_enabled(obj
->base
.dev
))
2204 return i915_gem_object_wait_rendering(obj
);
2206 idx
= intel_ring_sync_index(from
, to
);
2208 seqno
= obj
->last_rendering_seqno
;
2209 if (seqno
<= from
->sync_seqno
[idx
])
2212 ret
= i915_gem_check_olr(obj
->ring
, seqno
);
2216 ret
= to
->sync_to(to
, from
, seqno
);
2218 from
->sync_seqno
[idx
] = seqno
;
2223 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object
*obj
)
2225 u32 old_write_domain
, old_read_domains
;
2227 /* Act a barrier for all accesses through the GTT */
2230 /* Force a pagefault for domain tracking on next user access */
2231 i915_gem_release_mmap(obj
);
2233 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
) == 0)
2236 old_read_domains
= obj
->base
.read_domains
;
2237 old_write_domain
= obj
->base
.write_domain
;
2239 obj
->base
.read_domains
&= ~I915_GEM_DOMAIN_GTT
;
2240 obj
->base
.write_domain
&= ~I915_GEM_DOMAIN_GTT
;
2242 trace_i915_gem_object_change_domain(obj
,
2248 * Unbinds an object from the GTT aperture.
2251 i915_gem_object_unbind(struct drm_i915_gem_object
*obj
)
2253 drm_i915_private_t
*dev_priv
= obj
->base
.dev
->dev_private
;
2256 if (obj
->gtt_space
== NULL
)
2262 ret
= i915_gem_object_finish_gpu(obj
);
2265 /* Continue on if we fail due to EIO, the GPU is hung so we
2266 * should be safe and we need to cleanup or else we might
2267 * cause memory corruption through use-after-free.
2270 i915_gem_object_finish_gtt(obj
);
2272 /* Move the object to the CPU domain to ensure that
2273 * any possible CPU writes while it's not in the GTT
2274 * are flushed when we go to remap it.
2277 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
2278 if (ret
== -ERESTARTSYS
)
2281 /* In the event of a disaster, abandon all caches and
2282 * hope for the best.
2284 i915_gem_clflush_object(obj
);
2285 obj
->base
.read_domains
= obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
2288 /* release the fence reg _after_ flushing */
2289 ret
= i915_gem_object_put_fence(obj
);
2293 trace_i915_gem_object_unbind(obj
);
2295 if (obj
->has_global_gtt_mapping
)
2296 i915_gem_gtt_unbind_object(obj
);
2297 if (obj
->has_aliasing_ppgtt_mapping
) {
2298 i915_ppgtt_unbind_object(dev_priv
->mm
.aliasing_ppgtt
, obj
);
2299 obj
->has_aliasing_ppgtt_mapping
= 0;
2301 i915_gem_gtt_finish_object(obj
);
2303 i915_gem_object_put_pages_gtt(obj
);
2305 list_del_init(&obj
->gtt_list
);
2306 list_del_init(&obj
->mm_list
);
2307 /* Avoid an unnecessary call to unbind on rebind. */
2308 obj
->map_and_fenceable
= true;
2310 drm_mm_put_block(obj
->gtt_space
);
2311 obj
->gtt_space
= NULL
;
2312 obj
->gtt_offset
= 0;
2314 if (i915_gem_object_is_purgeable(obj
))
2315 i915_gem_object_truncate(obj
);
2321 i915_gem_flush_ring(struct intel_ring_buffer
*ring
,
2322 uint32_t invalidate_domains
,
2323 uint32_t flush_domains
)
2327 if (((invalidate_domains
| flush_domains
) & I915_GEM_GPU_DOMAINS
) == 0)
2330 trace_i915_gem_ring_flush(ring
, invalidate_domains
, flush_domains
);
2332 ret
= ring
->flush(ring
, invalidate_domains
, flush_domains
);
2336 if (flush_domains
& I915_GEM_GPU_DOMAINS
)
2337 i915_gem_process_flushing_list(ring
, flush_domains
);
2342 static int i915_ring_idle(struct intel_ring_buffer
*ring
)
2346 if (list_empty(&ring
->gpu_write_list
) && list_empty(&ring
->active_list
))
2349 if (!list_empty(&ring
->gpu_write_list
)) {
2350 ret
= i915_gem_flush_ring(ring
,
2351 I915_GEM_GPU_DOMAINS
, I915_GEM_GPU_DOMAINS
);
2356 return i915_wait_seqno(ring
, i915_gem_next_request_seqno(ring
));
2359 int i915_gpu_idle(struct drm_device
*dev
)
2361 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2362 struct intel_ring_buffer
*ring
;
2365 /* Flush everything onto the inactive list. */
2366 for_each_ring(ring
, dev_priv
, i
) {
2367 ret
= i915_ring_idle(ring
);
2371 /* Is the device fubar? */
2372 if (WARN_ON(!list_empty(&ring
->gpu_write_list
)))
2375 ret
= i915_switch_context(ring
, NULL
, DEFAULT_CONTEXT_ID
);
2383 static void sandybridge_write_fence_reg(struct drm_device
*dev
, int reg
,
2384 struct drm_i915_gem_object
*obj
)
2386 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2390 u32 size
= obj
->gtt_space
->size
;
2392 val
= (uint64_t)((obj
->gtt_offset
+ size
- 4096) &
2394 val
|= obj
->gtt_offset
& 0xfffff000;
2395 val
|= (uint64_t)((obj
->stride
/ 128) - 1) <<
2396 SANDYBRIDGE_FENCE_PITCH_SHIFT
;
2398 if (obj
->tiling_mode
== I915_TILING_Y
)
2399 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
2400 val
|= I965_FENCE_REG_VALID
;
2404 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0
+ reg
* 8, val
);
2405 POSTING_READ(FENCE_REG_SANDYBRIDGE_0
+ reg
* 8);
2408 static void i965_write_fence_reg(struct drm_device
*dev
, int reg
,
2409 struct drm_i915_gem_object
*obj
)
2411 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2415 u32 size
= obj
->gtt_space
->size
;
2417 val
= (uint64_t)((obj
->gtt_offset
+ size
- 4096) &
2419 val
|= obj
->gtt_offset
& 0xfffff000;
2420 val
|= ((obj
->stride
/ 128) - 1) << I965_FENCE_PITCH_SHIFT
;
2421 if (obj
->tiling_mode
== I915_TILING_Y
)
2422 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
2423 val
|= I965_FENCE_REG_VALID
;
2427 I915_WRITE64(FENCE_REG_965_0
+ reg
* 8, val
);
2428 POSTING_READ(FENCE_REG_965_0
+ reg
* 8);
2431 static void i915_write_fence_reg(struct drm_device
*dev
, int reg
,
2432 struct drm_i915_gem_object
*obj
)
2434 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2438 u32 size
= obj
->gtt_space
->size
;
2442 WARN((obj
->gtt_offset
& ~I915_FENCE_START_MASK
) ||
2443 (size
& -size
) != size
||
2444 (obj
->gtt_offset
& (size
- 1)),
2445 "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2446 obj
->gtt_offset
, obj
->map_and_fenceable
, size
);
2448 if (obj
->tiling_mode
== I915_TILING_Y
&& HAS_128_BYTE_Y_TILING(dev
))
2453 /* Note: pitch better be a power of two tile widths */
2454 pitch_val
= obj
->stride
/ tile_width
;
2455 pitch_val
= ffs(pitch_val
) - 1;
2457 val
= obj
->gtt_offset
;
2458 if (obj
->tiling_mode
== I915_TILING_Y
)
2459 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2460 val
|= I915_FENCE_SIZE_BITS(size
);
2461 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2462 val
|= I830_FENCE_REG_VALID
;
2467 reg
= FENCE_REG_830_0
+ reg
* 4;
2469 reg
= FENCE_REG_945_8
+ (reg
- 8) * 4;
2471 I915_WRITE(reg
, val
);
2475 static void i830_write_fence_reg(struct drm_device
*dev
, int reg
,
2476 struct drm_i915_gem_object
*obj
)
2478 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2482 u32 size
= obj
->gtt_space
->size
;
2485 WARN((obj
->gtt_offset
& ~I830_FENCE_START_MASK
) ||
2486 (size
& -size
) != size
||
2487 (obj
->gtt_offset
& (size
- 1)),
2488 "object 0x%08x not 512K or pot-size 0x%08x aligned\n",
2489 obj
->gtt_offset
, size
);
2491 pitch_val
= obj
->stride
/ 128;
2492 pitch_val
= ffs(pitch_val
) - 1;
2494 val
= obj
->gtt_offset
;
2495 if (obj
->tiling_mode
== I915_TILING_Y
)
2496 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2497 val
|= I830_FENCE_SIZE_BITS(size
);
2498 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2499 val
|= I830_FENCE_REG_VALID
;
2503 I915_WRITE(FENCE_REG_830_0
+ reg
* 4, val
);
2504 POSTING_READ(FENCE_REG_830_0
+ reg
* 4);
2507 static void i915_gem_write_fence(struct drm_device
*dev
, int reg
,
2508 struct drm_i915_gem_object
*obj
)
2510 switch (INTEL_INFO(dev
)->gen
) {
2512 case 6: sandybridge_write_fence_reg(dev
, reg
, obj
); break;
2514 case 4: i965_write_fence_reg(dev
, reg
, obj
); break;
2515 case 3: i915_write_fence_reg(dev
, reg
, obj
); break;
2516 case 2: i830_write_fence_reg(dev
, reg
, obj
); break;
2521 static inline int fence_number(struct drm_i915_private
*dev_priv
,
2522 struct drm_i915_fence_reg
*fence
)
2524 return fence
- dev_priv
->fence_regs
;
2527 static void i915_gem_object_update_fence(struct drm_i915_gem_object
*obj
,
2528 struct drm_i915_fence_reg
*fence
,
2531 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2532 int reg
= fence_number(dev_priv
, fence
);
2534 i915_gem_write_fence(obj
->base
.dev
, reg
, enable
? obj
: NULL
);
2537 obj
->fence_reg
= reg
;
2539 list_move_tail(&fence
->lru_list
, &dev_priv
->mm
.fence_list
);
2541 obj
->fence_reg
= I915_FENCE_REG_NONE
;
2543 list_del_init(&fence
->lru_list
);
2548 i915_gem_object_flush_fence(struct drm_i915_gem_object
*obj
)
2552 if (obj
->fenced_gpu_access
) {
2553 if (obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
) {
2554 ret
= i915_gem_flush_ring(obj
->ring
,
2555 0, obj
->base
.write_domain
);
2560 obj
->fenced_gpu_access
= false;
2563 if (obj
->last_fenced_seqno
) {
2564 ret
= i915_wait_seqno(obj
->ring
, obj
->last_fenced_seqno
);
2568 obj
->last_fenced_seqno
= 0;
2571 /* Ensure that all CPU reads are completed before installing a fence
2572 * and all writes before removing the fence.
2574 if (obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
)
2581 i915_gem_object_put_fence(struct drm_i915_gem_object
*obj
)
2583 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2586 ret
= i915_gem_object_flush_fence(obj
);
2590 if (obj
->fence_reg
== I915_FENCE_REG_NONE
)
2593 i915_gem_object_update_fence(obj
,
2594 &dev_priv
->fence_regs
[obj
->fence_reg
],
2596 i915_gem_object_fence_lost(obj
);
2601 static struct drm_i915_fence_reg
*
2602 i915_find_fence_reg(struct drm_device
*dev
)
2604 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2605 struct drm_i915_fence_reg
*reg
, *avail
;
2608 /* First try to find a free reg */
2610 for (i
= dev_priv
->fence_reg_start
; i
< dev_priv
->num_fence_regs
; i
++) {
2611 reg
= &dev_priv
->fence_regs
[i
];
2615 if (!reg
->pin_count
)
2622 /* None available, try to steal one or wait for a user to finish */
2623 list_for_each_entry(reg
, &dev_priv
->mm
.fence_list
, lru_list
) {
2634 * i915_gem_object_get_fence - set up fencing for an object
2635 * @obj: object to map through a fence reg
2637 * When mapping objects through the GTT, userspace wants to be able to write
2638 * to them without having to worry about swizzling if the object is tiled.
2639 * This function walks the fence regs looking for a free one for @obj,
2640 * stealing one if it can't find any.
2642 * It then sets up the reg based on the object's properties: address, pitch
2643 * and tiling format.
2645 * For an untiled surface, this removes any existing fence.
2648 i915_gem_object_get_fence(struct drm_i915_gem_object
*obj
)
2650 struct drm_device
*dev
= obj
->base
.dev
;
2651 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2652 bool enable
= obj
->tiling_mode
!= I915_TILING_NONE
;
2653 struct drm_i915_fence_reg
*reg
;
2656 /* Have we updated the tiling parameters upon the object and so
2657 * will need to serialise the write to the associated fence register?
2659 if (obj
->fence_dirty
) {
2660 ret
= i915_gem_object_flush_fence(obj
);
2665 /* Just update our place in the LRU if our fence is getting reused. */
2666 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
2667 reg
= &dev_priv
->fence_regs
[obj
->fence_reg
];
2668 if (!obj
->fence_dirty
) {
2669 list_move_tail(®
->lru_list
,
2670 &dev_priv
->mm
.fence_list
);
2673 } else if (enable
) {
2674 reg
= i915_find_fence_reg(dev
);
2679 struct drm_i915_gem_object
*old
= reg
->obj
;
2681 ret
= i915_gem_object_flush_fence(old
);
2685 i915_gem_object_fence_lost(old
);
2690 i915_gem_object_update_fence(obj
, reg
, enable
);
2691 obj
->fence_dirty
= false;
2697 * Finds free space in the GTT aperture and binds the object there.
2700 i915_gem_object_bind_to_gtt(struct drm_i915_gem_object
*obj
,
2702 bool map_and_fenceable
)
2704 struct drm_device
*dev
= obj
->base
.dev
;
2705 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2706 struct drm_mm_node
*free_space
;
2707 gfp_t gfpmask
= __GFP_NORETRY
| __GFP_NOWARN
;
2708 u32 size
, fence_size
, fence_alignment
, unfenced_alignment
;
2709 bool mappable
, fenceable
;
2712 if (obj
->madv
!= I915_MADV_WILLNEED
) {
2713 DRM_ERROR("Attempting to bind a purgeable object\n");
2717 fence_size
= i915_gem_get_gtt_size(dev
,
2720 fence_alignment
= i915_gem_get_gtt_alignment(dev
,
2723 unfenced_alignment
=
2724 i915_gem_get_unfenced_gtt_alignment(dev
,
2729 alignment
= map_and_fenceable
? fence_alignment
:
2731 if (map_and_fenceable
&& alignment
& (fence_alignment
- 1)) {
2732 DRM_ERROR("Invalid object alignment requested %u\n", alignment
);
2736 size
= map_and_fenceable
? fence_size
: obj
->base
.size
;
2738 /* If the object is bigger than the entire aperture, reject it early
2739 * before evicting everything in a vain attempt to find space.
2741 if (obj
->base
.size
>
2742 (map_and_fenceable
? dev_priv
->mm
.gtt_mappable_end
: dev_priv
->mm
.gtt_total
)) {
2743 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2748 if (map_and_fenceable
)
2750 drm_mm_search_free_in_range(&dev_priv
->mm
.gtt_space
,
2752 0, dev_priv
->mm
.gtt_mappable_end
,
2755 free_space
= drm_mm_search_free(&dev_priv
->mm
.gtt_space
,
2756 size
, alignment
, 0);
2758 if (free_space
!= NULL
) {
2759 if (map_and_fenceable
)
2761 drm_mm_get_block_range_generic(free_space
,
2763 0, dev_priv
->mm
.gtt_mappable_end
,
2767 drm_mm_get_block(free_space
, size
, alignment
);
2769 if (obj
->gtt_space
== NULL
) {
2770 /* If the gtt is empty and we're still having trouble
2771 * fitting our object in, we're out of memory.
2773 ret
= i915_gem_evict_something(dev
, size
, alignment
,
2781 ret
= i915_gem_object_get_pages_gtt(obj
, gfpmask
);
2783 drm_mm_put_block(obj
->gtt_space
);
2784 obj
->gtt_space
= NULL
;
2786 if (ret
== -ENOMEM
) {
2787 /* first try to reclaim some memory by clearing the GTT */
2788 ret
= i915_gem_evict_everything(dev
, false);
2790 /* now try to shrink everyone else */
2805 ret
= i915_gem_gtt_prepare_object(obj
);
2807 i915_gem_object_put_pages_gtt(obj
);
2808 drm_mm_put_block(obj
->gtt_space
);
2809 obj
->gtt_space
= NULL
;
2811 if (i915_gem_evict_everything(dev
, false))
2817 if (!dev_priv
->mm
.aliasing_ppgtt
)
2818 i915_gem_gtt_bind_object(obj
, obj
->cache_level
);
2820 list_add_tail(&obj
->gtt_list
, &dev_priv
->mm
.gtt_list
);
2821 list_add_tail(&obj
->mm_list
, &dev_priv
->mm
.inactive_list
);
2823 /* Assert that the object is not currently in any GPU domain. As it
2824 * wasn't in the GTT, there shouldn't be any way it could have been in
2827 BUG_ON(obj
->base
.read_domains
& I915_GEM_GPU_DOMAINS
);
2828 BUG_ON(obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
);
2830 obj
->gtt_offset
= obj
->gtt_space
->start
;
2833 obj
->gtt_space
->size
== fence_size
&&
2834 (obj
->gtt_space
->start
& (fence_alignment
- 1)) == 0;
2837 obj
->gtt_offset
+ obj
->base
.size
<= dev_priv
->mm
.gtt_mappable_end
;
2839 obj
->map_and_fenceable
= mappable
&& fenceable
;
2841 trace_i915_gem_object_bind(obj
, map_and_fenceable
);
2846 i915_gem_clflush_object(struct drm_i915_gem_object
*obj
)
2848 /* If we don't have a page list set up, then we're not pinned
2849 * to GPU, and we can ignore the cache flush because it'll happen
2850 * again at bind time.
2852 if (obj
->pages
== NULL
)
2855 /* If the GPU is snooping the contents of the CPU cache,
2856 * we do not need to manually clear the CPU cache lines. However,
2857 * the caches are only snooped when the render cache is
2858 * flushed/invalidated. As we always have to emit invalidations
2859 * and flushes when moving into and out of the RENDER domain, correct
2860 * snooping behaviour occurs naturally as the result of our domain
2863 if (obj
->cache_level
!= I915_CACHE_NONE
)
2866 trace_i915_gem_object_clflush(obj
);
2868 drm_clflush_pages(obj
->pages
, obj
->base
.size
/ PAGE_SIZE
);
2871 /** Flushes any GPU write domain for the object if it's dirty. */
2873 i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object
*obj
)
2875 if ((obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
) == 0)
2878 /* Queue the GPU write cache flushing we need. */
2879 return i915_gem_flush_ring(obj
->ring
, 0, obj
->base
.write_domain
);
2882 /** Flushes the GTT write domain for the object if it's dirty. */
2884 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
)
2886 uint32_t old_write_domain
;
2888 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_GTT
)
2891 /* No actual flushing is required for the GTT write domain. Writes
2892 * to it immediately go to main memory as far as we know, so there's
2893 * no chipset flush. It also doesn't land in render cache.
2895 * However, we do have to enforce the order so that all writes through
2896 * the GTT land before any writes to the device, such as updates to
2901 old_write_domain
= obj
->base
.write_domain
;
2902 obj
->base
.write_domain
= 0;
2904 trace_i915_gem_object_change_domain(obj
,
2905 obj
->base
.read_domains
,
2909 /** Flushes the CPU write domain for the object if it's dirty. */
2911 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
)
2913 uint32_t old_write_domain
;
2915 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
)
2918 i915_gem_clflush_object(obj
);
2919 intel_gtt_chipset_flush();
2920 old_write_domain
= obj
->base
.write_domain
;
2921 obj
->base
.write_domain
= 0;
2923 trace_i915_gem_object_change_domain(obj
,
2924 obj
->base
.read_domains
,
2929 * Moves a single object to the GTT read, and possibly write domain.
2931 * This function returns when the move is complete, including waiting on
2935 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
, bool write
)
2937 drm_i915_private_t
*dev_priv
= obj
->base
.dev
->dev_private
;
2938 uint32_t old_write_domain
, old_read_domains
;
2941 /* Not valid to be called on unbound objects. */
2942 if (obj
->gtt_space
== NULL
)
2945 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_GTT
)
2948 ret
= i915_gem_object_flush_gpu_write_domain(obj
);
2952 if (obj
->pending_gpu_write
|| write
) {
2953 ret
= i915_gem_object_wait_rendering(obj
);
2958 i915_gem_object_flush_cpu_write_domain(obj
);
2960 old_write_domain
= obj
->base
.write_domain
;
2961 old_read_domains
= obj
->base
.read_domains
;
2963 /* It should now be out of any other write domains, and we can update
2964 * the domain values for our changes.
2966 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
2967 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
2969 obj
->base
.read_domains
= I915_GEM_DOMAIN_GTT
;
2970 obj
->base
.write_domain
= I915_GEM_DOMAIN_GTT
;
2974 trace_i915_gem_object_change_domain(obj
,
2978 /* And bump the LRU for this access */
2979 if (i915_gem_object_is_inactive(obj
))
2980 list_move_tail(&obj
->mm_list
, &dev_priv
->mm
.inactive_list
);
2985 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
2986 enum i915_cache_level cache_level
)
2988 struct drm_device
*dev
= obj
->base
.dev
;
2989 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2992 if (obj
->cache_level
== cache_level
)
2995 if (obj
->pin_count
) {
2996 DRM_DEBUG("can not change the cache level of pinned objects\n");
3000 if (obj
->gtt_space
) {
3001 ret
= i915_gem_object_finish_gpu(obj
);
3005 i915_gem_object_finish_gtt(obj
);
3007 /* Before SandyBridge, you could not use tiling or fence
3008 * registers with snooped memory, so relinquish any fences
3009 * currently pointing to our region in the aperture.
3011 if (INTEL_INFO(obj
->base
.dev
)->gen
< 6) {
3012 ret
= i915_gem_object_put_fence(obj
);
3017 if (obj
->has_global_gtt_mapping
)
3018 i915_gem_gtt_bind_object(obj
, cache_level
);
3019 if (obj
->has_aliasing_ppgtt_mapping
)
3020 i915_ppgtt_bind_object(dev_priv
->mm
.aliasing_ppgtt
,
3024 if (cache_level
== I915_CACHE_NONE
) {
3025 u32 old_read_domains
, old_write_domain
;
3027 /* If we're coming from LLC cached, then we haven't
3028 * actually been tracking whether the data is in the
3029 * CPU cache or not, since we only allow one bit set
3030 * in obj->write_domain and have been skipping the clflushes.
3031 * Just set it to the CPU cache for now.
3033 WARN_ON(obj
->base
.write_domain
& ~I915_GEM_DOMAIN_CPU
);
3034 WARN_ON(obj
->base
.read_domains
& ~I915_GEM_DOMAIN_CPU
);
3036 old_read_domains
= obj
->base
.read_domains
;
3037 old_write_domain
= obj
->base
.write_domain
;
3039 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
3040 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
3042 trace_i915_gem_object_change_domain(obj
,
3047 obj
->cache_level
= cache_level
;
3052 * Prepare buffer for display plane (scanout, cursors, etc).
3053 * Can be called from an uninterruptible phase (modesetting) and allows
3054 * any flushes to be pipelined (for pageflips).
3057 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
3059 struct intel_ring_buffer
*pipelined
)
3061 u32 old_read_domains
, old_write_domain
;
3064 ret
= i915_gem_object_flush_gpu_write_domain(obj
);
3068 if (pipelined
!= obj
->ring
) {
3069 ret
= i915_gem_object_sync(obj
, pipelined
);
3074 /* The display engine is not coherent with the LLC cache on gen6. As
3075 * a result, we make sure that the pinning that is about to occur is
3076 * done with uncached PTEs. This is lowest common denominator for all
3079 * However for gen6+, we could do better by using the GFDT bit instead
3080 * of uncaching, which would allow us to flush all the LLC-cached data
3081 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3083 ret
= i915_gem_object_set_cache_level(obj
, I915_CACHE_NONE
);
3087 /* As the user may map the buffer once pinned in the display plane
3088 * (e.g. libkms for the bootup splash), we have to ensure that we
3089 * always use map_and_fenceable for all scanout buffers.
3091 ret
= i915_gem_object_pin(obj
, alignment
, true);
3095 i915_gem_object_flush_cpu_write_domain(obj
);
3097 old_write_domain
= obj
->base
.write_domain
;
3098 old_read_domains
= obj
->base
.read_domains
;
3100 /* It should now be out of any other write domains, and we can update
3101 * the domain values for our changes.
3103 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
3104 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
3106 trace_i915_gem_object_change_domain(obj
,
3114 i915_gem_object_finish_gpu(struct drm_i915_gem_object
*obj
)
3118 if ((obj
->base
.read_domains
& I915_GEM_GPU_DOMAINS
) == 0)
3121 if (obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
) {
3122 ret
= i915_gem_flush_ring(obj
->ring
, 0, obj
->base
.write_domain
);
3127 ret
= i915_gem_object_wait_rendering(obj
);
3131 /* Ensure that we invalidate the GPU's caches and TLBs. */
3132 obj
->base
.read_domains
&= ~I915_GEM_GPU_DOMAINS
;
3137 * Moves a single object to the CPU read, and possibly write domain.
3139 * This function returns when the move is complete, including waiting on
3143 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
)
3145 uint32_t old_write_domain
, old_read_domains
;
3148 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_CPU
)
3151 ret
= i915_gem_object_flush_gpu_write_domain(obj
);
3155 if (write
|| obj
->pending_gpu_write
) {
3156 ret
= i915_gem_object_wait_rendering(obj
);
3161 i915_gem_object_flush_gtt_write_domain(obj
);
3163 old_write_domain
= obj
->base
.write_domain
;
3164 old_read_domains
= obj
->base
.read_domains
;
3166 /* Flush the CPU cache if it's still invalid. */
3167 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) == 0) {
3168 i915_gem_clflush_object(obj
);
3170 obj
->base
.read_domains
|= I915_GEM_DOMAIN_CPU
;
3173 /* It should now be out of any other write domains, and we can update
3174 * the domain values for our changes.
3176 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
3178 /* If we're writing through the CPU, then the GPU read domains will
3179 * need to be invalidated at next use.
3182 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
3183 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
3186 trace_i915_gem_object_change_domain(obj
,
3193 /* Throttle our rendering by waiting until the ring has completed our requests
3194 * emitted over 20 msec ago.
3196 * Note that if we were to use the current jiffies each time around the loop,
3197 * we wouldn't escape the function with any frames outstanding if the time to
3198 * render a frame was over 20ms.
3200 * This should get us reasonable parallelism between CPU and GPU but also
3201 * relatively low latency when blocking on a particular request to finish.
3204 i915_gem_ring_throttle(struct drm_device
*dev
, struct drm_file
*file
)
3206 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3207 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
3208 unsigned long recent_enough
= jiffies
- msecs_to_jiffies(20);
3209 struct drm_i915_gem_request
*request
;
3210 struct intel_ring_buffer
*ring
= NULL
;
3214 if (atomic_read(&dev_priv
->mm
.wedged
))
3217 spin_lock(&file_priv
->mm
.lock
);
3218 list_for_each_entry(request
, &file_priv
->mm
.request_list
, client_list
) {
3219 if (time_after_eq(request
->emitted_jiffies
, recent_enough
))
3222 ring
= request
->ring
;
3223 seqno
= request
->seqno
;
3225 spin_unlock(&file_priv
->mm
.lock
);
3230 ret
= __wait_seqno(ring
, seqno
, true, NULL
);
3232 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, 0);
3238 i915_gem_object_pin(struct drm_i915_gem_object
*obj
,
3240 bool map_and_fenceable
)
3244 BUG_ON(obj
->pin_count
== DRM_I915_GEM_OBJECT_MAX_PIN_COUNT
);
3246 if (obj
->gtt_space
!= NULL
) {
3247 if ((alignment
&& obj
->gtt_offset
& (alignment
- 1)) ||
3248 (map_and_fenceable
&& !obj
->map_and_fenceable
)) {
3249 WARN(obj
->pin_count
,
3250 "bo is already pinned with incorrect alignment:"
3251 " offset=%x, req.alignment=%x, req.map_and_fenceable=%d,"
3252 " obj->map_and_fenceable=%d\n",
3253 obj
->gtt_offset
, alignment
,
3255 obj
->map_and_fenceable
);
3256 ret
= i915_gem_object_unbind(obj
);
3262 if (obj
->gtt_space
== NULL
) {
3263 ret
= i915_gem_object_bind_to_gtt(obj
, alignment
,
3269 if (!obj
->has_global_gtt_mapping
&& map_and_fenceable
)
3270 i915_gem_gtt_bind_object(obj
, obj
->cache_level
);
3273 obj
->pin_mappable
|= map_and_fenceable
;
3279 i915_gem_object_unpin(struct drm_i915_gem_object
*obj
)
3281 BUG_ON(obj
->pin_count
== 0);
3282 BUG_ON(obj
->gtt_space
== NULL
);
3284 if (--obj
->pin_count
== 0)
3285 obj
->pin_mappable
= false;
3289 i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
3290 struct drm_file
*file
)
3292 struct drm_i915_gem_pin
*args
= data
;
3293 struct drm_i915_gem_object
*obj
;
3296 ret
= i915_mutex_lock_interruptible(dev
);
3300 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3301 if (&obj
->base
== NULL
) {
3306 if (obj
->madv
!= I915_MADV_WILLNEED
) {
3307 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3312 if (obj
->pin_filp
!= NULL
&& obj
->pin_filp
!= file
) {
3313 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3319 obj
->user_pin_count
++;
3320 obj
->pin_filp
= file
;
3321 if (obj
->user_pin_count
== 1) {
3322 ret
= i915_gem_object_pin(obj
, args
->alignment
, true);
3327 /* XXX - flush the CPU caches for pinned objects
3328 * as the X server doesn't manage domains yet
3330 i915_gem_object_flush_cpu_write_domain(obj
);
3331 args
->offset
= obj
->gtt_offset
;
3333 drm_gem_object_unreference(&obj
->base
);
3335 mutex_unlock(&dev
->struct_mutex
);
3340 i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
3341 struct drm_file
*file
)
3343 struct drm_i915_gem_pin
*args
= data
;
3344 struct drm_i915_gem_object
*obj
;
3347 ret
= i915_mutex_lock_interruptible(dev
);
3351 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3352 if (&obj
->base
== NULL
) {
3357 if (obj
->pin_filp
!= file
) {
3358 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3363 obj
->user_pin_count
--;
3364 if (obj
->user_pin_count
== 0) {
3365 obj
->pin_filp
= NULL
;
3366 i915_gem_object_unpin(obj
);
3370 drm_gem_object_unreference(&obj
->base
);
3372 mutex_unlock(&dev
->struct_mutex
);
3377 i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
3378 struct drm_file
*file
)
3380 struct drm_i915_gem_busy
*args
= data
;
3381 struct drm_i915_gem_object
*obj
;
3384 ret
= i915_mutex_lock_interruptible(dev
);
3388 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3389 if (&obj
->base
== NULL
) {
3394 /* Count all active objects as busy, even if they are currently not used
3395 * by the gpu. Users of this interface expect objects to eventually
3396 * become non-busy without any further actions, therefore emit any
3397 * necessary flushes here.
3399 ret
= i915_gem_object_flush_active(obj
);
3401 args
->busy
= obj
->active
;
3403 drm_gem_object_unreference(&obj
->base
);
3405 mutex_unlock(&dev
->struct_mutex
);
3410 i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
3411 struct drm_file
*file_priv
)
3413 return i915_gem_ring_throttle(dev
, file_priv
);
3417 i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
3418 struct drm_file
*file_priv
)
3420 struct drm_i915_gem_madvise
*args
= data
;
3421 struct drm_i915_gem_object
*obj
;
3424 switch (args
->madv
) {
3425 case I915_MADV_DONTNEED
:
3426 case I915_MADV_WILLNEED
:
3432 ret
= i915_mutex_lock_interruptible(dev
);
3436 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file_priv
, args
->handle
));
3437 if (&obj
->base
== NULL
) {
3442 if (obj
->pin_count
) {
3447 if (obj
->madv
!= __I915_MADV_PURGED
)
3448 obj
->madv
= args
->madv
;
3450 /* if the object is no longer bound, discard its backing storage */
3451 if (i915_gem_object_is_purgeable(obj
) &&
3452 obj
->gtt_space
== NULL
)
3453 i915_gem_object_truncate(obj
);
3455 args
->retained
= obj
->madv
!= __I915_MADV_PURGED
;
3458 drm_gem_object_unreference(&obj
->base
);
3460 mutex_unlock(&dev
->struct_mutex
);
3464 struct drm_i915_gem_object
*i915_gem_alloc_object(struct drm_device
*dev
,
3467 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3468 struct drm_i915_gem_object
*obj
;
3469 struct address_space
*mapping
;
3472 obj
= kzalloc(sizeof(*obj
), GFP_KERNEL
);
3476 if (drm_gem_object_init(dev
, &obj
->base
, size
) != 0) {
3481 mask
= GFP_HIGHUSER
| __GFP_RECLAIMABLE
;
3482 if (IS_CRESTLINE(dev
) || IS_BROADWATER(dev
)) {
3483 /* 965gm cannot relocate objects above 4GiB. */
3484 mask
&= ~__GFP_HIGHMEM
;
3485 mask
|= __GFP_DMA32
;
3488 mapping
= obj
->base
.filp
->f_path
.dentry
->d_inode
->i_mapping
;
3489 mapping_set_gfp_mask(mapping
, mask
);
3491 i915_gem_info_add_obj(dev_priv
, size
);
3493 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
3494 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
3497 /* On some devices, we can have the GPU use the LLC (the CPU
3498 * cache) for about a 10% performance improvement
3499 * compared to uncached. Graphics requests other than
3500 * display scanout are coherent with the CPU in
3501 * accessing this cache. This means in this mode we
3502 * don't need to clflush on the CPU side, and on the
3503 * GPU side we only need to flush internal caches to
3504 * get data visible to the CPU.
3506 * However, we maintain the display planes as UC, and so
3507 * need to rebind when first used as such.
3509 obj
->cache_level
= I915_CACHE_LLC
;
3511 obj
->cache_level
= I915_CACHE_NONE
;
3513 obj
->base
.driver_private
= NULL
;
3514 obj
->fence_reg
= I915_FENCE_REG_NONE
;
3515 INIT_LIST_HEAD(&obj
->mm_list
);
3516 INIT_LIST_HEAD(&obj
->gtt_list
);
3517 INIT_LIST_HEAD(&obj
->ring_list
);
3518 INIT_LIST_HEAD(&obj
->exec_list
);
3519 INIT_LIST_HEAD(&obj
->gpu_write_list
);
3520 obj
->madv
= I915_MADV_WILLNEED
;
3521 /* Avoid an unnecessary call to unbind on the first bind. */
3522 obj
->map_and_fenceable
= true;
3527 int i915_gem_init_object(struct drm_gem_object
*obj
)
3534 void i915_gem_free_object(struct drm_gem_object
*gem_obj
)
3536 struct drm_i915_gem_object
*obj
= to_intel_bo(gem_obj
);
3537 struct drm_device
*dev
= obj
->base
.dev
;
3538 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3540 trace_i915_gem_object_destroy(obj
);
3542 if (gem_obj
->import_attach
)
3543 drm_prime_gem_destroy(gem_obj
, obj
->sg_table
);
3546 i915_gem_detach_phys_object(dev
, obj
);
3549 if (WARN_ON(i915_gem_object_unbind(obj
) == -ERESTARTSYS
)) {
3550 bool was_interruptible
;
3552 was_interruptible
= dev_priv
->mm
.interruptible
;
3553 dev_priv
->mm
.interruptible
= false;
3555 WARN_ON(i915_gem_object_unbind(obj
));
3557 dev_priv
->mm
.interruptible
= was_interruptible
;
3560 if (obj
->base
.map_list
.map
)
3561 drm_gem_free_mmap_offset(&obj
->base
);
3563 drm_gem_object_release(&obj
->base
);
3564 i915_gem_info_remove_obj(dev_priv
, obj
->base
.size
);
3571 i915_gem_idle(struct drm_device
*dev
)
3573 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3576 mutex_lock(&dev
->struct_mutex
);
3578 if (dev_priv
->mm
.suspended
) {
3579 mutex_unlock(&dev
->struct_mutex
);
3583 ret
= i915_gpu_idle(dev
);
3585 mutex_unlock(&dev
->struct_mutex
);
3588 i915_gem_retire_requests(dev
);
3590 /* Under UMS, be paranoid and evict. */
3591 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
3592 i915_gem_evict_everything(dev
, false);
3594 i915_gem_reset_fences(dev
);
3596 /* Hack! Don't let anybody do execbuf while we don't control the chip.
3597 * We need to replace this with a semaphore, or something.
3598 * And not confound mm.suspended!
3600 dev_priv
->mm
.suspended
= 1;
3601 del_timer_sync(&dev_priv
->hangcheck_timer
);
3603 i915_kernel_lost_context(dev
);
3604 i915_gem_cleanup_ringbuffer(dev
);
3606 mutex_unlock(&dev
->struct_mutex
);
3608 /* Cancel the retire work handler, which should be idle now. */
3609 cancel_delayed_work_sync(&dev_priv
->mm
.retire_work
);
3614 void i915_gem_l3_remap(struct drm_device
*dev
)
3616 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3620 if (!IS_IVYBRIDGE(dev
))
3623 if (!dev_priv
->mm
.l3_remap_info
)
3626 misccpctl
= I915_READ(GEN7_MISCCPCTL
);
3627 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
& ~GEN7_DOP_CLOCK_GATE_ENABLE
);
3628 POSTING_READ(GEN7_MISCCPCTL
);
3630 for (i
= 0; i
< GEN7_L3LOG_SIZE
; i
+= 4) {
3631 u32 remap
= I915_READ(GEN7_L3LOG_BASE
+ i
);
3632 if (remap
&& remap
!= dev_priv
->mm
.l3_remap_info
[i
/4])
3633 DRM_DEBUG("0x%x was already programmed to %x\n",
3634 GEN7_L3LOG_BASE
+ i
, remap
);
3635 if (remap
&& !dev_priv
->mm
.l3_remap_info
[i
/4])
3636 DRM_DEBUG_DRIVER("Clearing remapped register\n");
3637 I915_WRITE(GEN7_L3LOG_BASE
+ i
, dev_priv
->mm
.l3_remap_info
[i
/4]);
3640 /* Make sure all the writes land before disabling dop clock gating */
3641 POSTING_READ(GEN7_L3LOG_BASE
);
3643 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
);
3646 void i915_gem_init_swizzling(struct drm_device
*dev
)
3648 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3650 if (INTEL_INFO(dev
)->gen
< 5 ||
3651 dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_NONE
)
3654 I915_WRITE(DISP_ARB_CTL
, I915_READ(DISP_ARB_CTL
) |
3655 DISP_TILE_SURFACE_SWIZZLING
);
3660 I915_WRITE(TILECTL
, I915_READ(TILECTL
) | TILECTL_SWZCTL
);
3662 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB
));
3664 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB
));
3667 void i915_gem_init_ppgtt(struct drm_device
*dev
)
3669 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3671 struct intel_ring_buffer
*ring
;
3672 struct i915_hw_ppgtt
*ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
3673 uint32_t __iomem
*pd_addr
;
3677 if (!dev_priv
->mm
.aliasing_ppgtt
)
3681 pd_addr
= dev_priv
->mm
.gtt
->gtt
+ ppgtt
->pd_offset
/sizeof(uint32_t);
3682 for (i
= 0; i
< ppgtt
->num_pd_entries
; i
++) {
3685 if (dev_priv
->mm
.gtt
->needs_dmar
)
3686 pt_addr
= ppgtt
->pt_dma_addr
[i
];
3688 pt_addr
= page_to_phys(ppgtt
->pt_pages
[i
]);
3690 pd_entry
= GEN6_PDE_ADDR_ENCODE(pt_addr
);
3691 pd_entry
|= GEN6_PDE_VALID
;
3693 writel(pd_entry
, pd_addr
+ i
);
3697 pd_offset
= ppgtt
->pd_offset
;
3698 pd_offset
/= 64; /* in cachelines, */
3701 if (INTEL_INFO(dev
)->gen
== 6) {
3702 uint32_t ecochk
, gab_ctl
, ecobits
;
3704 ecobits
= I915_READ(GAC_ECO_BITS
);
3705 I915_WRITE(GAC_ECO_BITS
, ecobits
| ECOBITS_PPGTT_CACHE64B
);
3707 gab_ctl
= I915_READ(GAB_CTL
);
3708 I915_WRITE(GAB_CTL
, gab_ctl
| GAB_CTL_CONT_AFTER_PAGEFAULT
);
3710 ecochk
= I915_READ(GAM_ECOCHK
);
3711 I915_WRITE(GAM_ECOCHK
, ecochk
| ECOCHK_SNB_BIT
|
3712 ECOCHK_PPGTT_CACHE64B
);
3713 I915_WRITE(GFX_MODE
, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE
));
3714 } else if (INTEL_INFO(dev
)->gen
>= 7) {
3715 I915_WRITE(GAM_ECOCHK
, ECOCHK_PPGTT_CACHE64B
);
3716 /* GFX_MODE is per-ring on gen7+ */
3719 for_each_ring(ring
, dev_priv
, i
) {
3720 if (INTEL_INFO(dev
)->gen
>= 7)
3721 I915_WRITE(RING_MODE_GEN7(ring
),
3722 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE
));
3724 I915_WRITE(RING_PP_DIR_DCLV(ring
), PP_DIR_DCLV_2G
);
3725 I915_WRITE(RING_PP_DIR_BASE(ring
), pd_offset
);
3730 i915_gem_init_hw(struct drm_device
*dev
)
3732 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3735 if (!intel_enable_gtt())
3738 i915_gem_l3_remap(dev
);
3740 i915_gem_init_swizzling(dev
);
3742 ret
= intel_init_render_ring_buffer(dev
);
3747 ret
= intel_init_bsd_ring_buffer(dev
);
3749 goto cleanup_render_ring
;
3753 ret
= intel_init_blt_ring_buffer(dev
);
3755 goto cleanup_bsd_ring
;
3758 dev_priv
->next_seqno
= 1;
3761 * XXX: There was some w/a described somewhere suggesting loading
3762 * contexts before PPGTT.
3764 i915_gem_context_init(dev
);
3765 i915_gem_init_ppgtt(dev
);
3770 intel_cleanup_ring_buffer(&dev_priv
->ring
[VCS
]);
3771 cleanup_render_ring
:
3772 intel_cleanup_ring_buffer(&dev_priv
->ring
[RCS
]);
3777 intel_enable_ppgtt(struct drm_device
*dev
)
3779 if (i915_enable_ppgtt
>= 0)
3780 return i915_enable_ppgtt
;
3782 #ifdef CONFIG_INTEL_IOMMU
3783 /* Disable ppgtt on SNB if VT-d is on. */
3784 if (INTEL_INFO(dev
)->gen
== 6 && intel_iommu_gfx_mapped
)
3791 int i915_gem_init(struct drm_device
*dev
)
3793 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3794 unsigned long gtt_size
, mappable_size
;
3797 gtt_size
= dev_priv
->mm
.gtt
->gtt_total_entries
<< PAGE_SHIFT
;
3798 mappable_size
= dev_priv
->mm
.gtt
->gtt_mappable_entries
<< PAGE_SHIFT
;
3800 mutex_lock(&dev
->struct_mutex
);
3801 if (intel_enable_ppgtt(dev
) && HAS_ALIASING_PPGTT(dev
)) {
3802 /* PPGTT pdes are stolen from global gtt ptes, so shrink the
3803 * aperture accordingly when using aliasing ppgtt. */
3804 gtt_size
-= I915_PPGTT_PD_ENTRIES
*PAGE_SIZE
;
3806 i915_gem_init_global_gtt(dev
, 0, mappable_size
, gtt_size
);
3808 ret
= i915_gem_init_aliasing_ppgtt(dev
);
3810 mutex_unlock(&dev
->struct_mutex
);
3814 /* Let GEM Manage all of the aperture.
3816 * However, leave one page at the end still bound to the scratch
3817 * page. There are a number of places where the hardware
3818 * apparently prefetches past the end of the object, and we've
3819 * seen multiple hangs with the GPU head pointer stuck in a
3820 * batchbuffer bound at the last page of the aperture. One page
3821 * should be enough to keep any prefetching inside of the
3824 i915_gem_init_global_gtt(dev
, 0, mappable_size
,
3828 ret
= i915_gem_init_hw(dev
);
3829 mutex_unlock(&dev
->struct_mutex
);
3831 i915_gem_cleanup_aliasing_ppgtt(dev
);
3835 /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */
3836 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
3837 dev_priv
->dri1
.allow_batchbuffer
= 1;
3842 i915_gem_cleanup_ringbuffer(struct drm_device
*dev
)
3844 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3845 struct intel_ring_buffer
*ring
;
3848 for_each_ring(ring
, dev_priv
, i
)
3849 intel_cleanup_ring_buffer(ring
);
3853 i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
3854 struct drm_file
*file_priv
)
3856 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3859 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
3862 if (atomic_read(&dev_priv
->mm
.wedged
)) {
3863 DRM_ERROR("Reenabling wedged hardware, good luck\n");
3864 atomic_set(&dev_priv
->mm
.wedged
, 0);
3867 mutex_lock(&dev
->struct_mutex
);
3868 dev_priv
->mm
.suspended
= 0;
3870 ret
= i915_gem_init_hw(dev
);
3872 mutex_unlock(&dev
->struct_mutex
);
3876 BUG_ON(!list_empty(&dev_priv
->mm
.active_list
));
3877 BUG_ON(!list_empty(&dev_priv
->mm
.flushing_list
));
3878 BUG_ON(!list_empty(&dev_priv
->mm
.inactive_list
));
3879 mutex_unlock(&dev
->struct_mutex
);
3881 ret
= drm_irq_install(dev
);
3883 goto cleanup_ringbuffer
;
3888 mutex_lock(&dev
->struct_mutex
);
3889 i915_gem_cleanup_ringbuffer(dev
);
3890 dev_priv
->mm
.suspended
= 1;
3891 mutex_unlock(&dev
->struct_mutex
);
3897 i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
3898 struct drm_file
*file_priv
)
3900 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
3903 drm_irq_uninstall(dev
);
3904 return i915_gem_idle(dev
);
3908 i915_gem_lastclose(struct drm_device
*dev
)
3912 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
3915 ret
= i915_gem_idle(dev
);
3917 DRM_ERROR("failed to idle hardware: %d\n", ret
);
3921 init_ring_lists(struct intel_ring_buffer
*ring
)
3923 INIT_LIST_HEAD(&ring
->active_list
);
3924 INIT_LIST_HEAD(&ring
->request_list
);
3925 INIT_LIST_HEAD(&ring
->gpu_write_list
);
3929 i915_gem_load(struct drm_device
*dev
)
3932 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3934 INIT_LIST_HEAD(&dev_priv
->mm
.active_list
);
3935 INIT_LIST_HEAD(&dev_priv
->mm
.flushing_list
);
3936 INIT_LIST_HEAD(&dev_priv
->mm
.inactive_list
);
3937 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
3938 INIT_LIST_HEAD(&dev_priv
->mm
.gtt_list
);
3939 for (i
= 0; i
< I915_NUM_RINGS
; i
++)
3940 init_ring_lists(&dev_priv
->ring
[i
]);
3941 for (i
= 0; i
< I915_MAX_NUM_FENCES
; i
++)
3942 INIT_LIST_HEAD(&dev_priv
->fence_regs
[i
].lru_list
);
3943 INIT_DELAYED_WORK(&dev_priv
->mm
.retire_work
,
3944 i915_gem_retire_work_handler
);
3945 init_completion(&dev_priv
->error_completion
);
3947 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
3949 I915_WRITE(MI_ARB_STATE
,
3950 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE
));
3953 dev_priv
->relative_constants_mode
= I915_EXEC_CONSTANTS_REL_GENERAL
;
3955 /* Old X drivers will take 0-2 for front, back, depth buffers */
3956 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
3957 dev_priv
->fence_reg_start
= 3;
3959 if (INTEL_INFO(dev
)->gen
>= 4 || IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
3960 dev_priv
->num_fence_regs
= 16;
3962 dev_priv
->num_fence_regs
= 8;
3964 /* Initialize fence registers to zero */
3965 i915_gem_reset_fences(dev
);
3967 i915_gem_detect_bit_6_swizzle(dev
);
3968 init_waitqueue_head(&dev_priv
->pending_flip_queue
);
3970 dev_priv
->mm
.interruptible
= true;
3972 dev_priv
->mm
.inactive_shrinker
.shrink
= i915_gem_inactive_shrink
;
3973 dev_priv
->mm
.inactive_shrinker
.seeks
= DEFAULT_SEEKS
;
3974 register_shrinker(&dev_priv
->mm
.inactive_shrinker
);
3978 * Create a physically contiguous memory object for this object
3979 * e.g. for cursor + overlay regs
3981 static int i915_gem_init_phys_object(struct drm_device
*dev
,
3982 int id
, int size
, int align
)
3984 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3985 struct drm_i915_gem_phys_object
*phys_obj
;
3988 if (dev_priv
->mm
.phys_objs
[id
- 1] || !size
)
3991 phys_obj
= kzalloc(sizeof(struct drm_i915_gem_phys_object
), GFP_KERNEL
);
3997 phys_obj
->handle
= drm_pci_alloc(dev
, size
, align
);
3998 if (!phys_obj
->handle
) {
4003 set_memory_wc((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
4006 dev_priv
->mm
.phys_objs
[id
- 1] = phys_obj
;
4014 static void i915_gem_free_phys_object(struct drm_device
*dev
, int id
)
4016 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4017 struct drm_i915_gem_phys_object
*phys_obj
;
4019 if (!dev_priv
->mm
.phys_objs
[id
- 1])
4022 phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
4023 if (phys_obj
->cur_obj
) {
4024 i915_gem_detach_phys_object(dev
, phys_obj
->cur_obj
);
4028 set_memory_wb((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
4030 drm_pci_free(dev
, phys_obj
->handle
);
4032 dev_priv
->mm
.phys_objs
[id
- 1] = NULL
;
4035 void i915_gem_free_all_phys_object(struct drm_device
*dev
)
4039 for (i
= I915_GEM_PHYS_CURSOR_0
; i
<= I915_MAX_PHYS_OBJECT
; i
++)
4040 i915_gem_free_phys_object(dev
, i
);
4043 void i915_gem_detach_phys_object(struct drm_device
*dev
,
4044 struct drm_i915_gem_object
*obj
)
4046 struct address_space
*mapping
= obj
->base
.filp
->f_path
.dentry
->d_inode
->i_mapping
;
4053 vaddr
= obj
->phys_obj
->handle
->vaddr
;
4055 page_count
= obj
->base
.size
/ PAGE_SIZE
;
4056 for (i
= 0; i
< page_count
; i
++) {
4057 struct page
*page
= shmem_read_mapping_page(mapping
, i
);
4058 if (!IS_ERR(page
)) {
4059 char *dst
= kmap_atomic(page
);
4060 memcpy(dst
, vaddr
+ i
*PAGE_SIZE
, PAGE_SIZE
);
4063 drm_clflush_pages(&page
, 1);
4065 set_page_dirty(page
);
4066 mark_page_accessed(page
);
4067 page_cache_release(page
);
4070 intel_gtt_chipset_flush();
4072 obj
->phys_obj
->cur_obj
= NULL
;
4073 obj
->phys_obj
= NULL
;
4077 i915_gem_attach_phys_object(struct drm_device
*dev
,
4078 struct drm_i915_gem_object
*obj
,
4082 struct address_space
*mapping
= obj
->base
.filp
->f_path
.dentry
->d_inode
->i_mapping
;
4083 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4088 if (id
> I915_MAX_PHYS_OBJECT
)
4091 if (obj
->phys_obj
) {
4092 if (obj
->phys_obj
->id
== id
)
4094 i915_gem_detach_phys_object(dev
, obj
);
4097 /* create a new object */
4098 if (!dev_priv
->mm
.phys_objs
[id
- 1]) {
4099 ret
= i915_gem_init_phys_object(dev
, id
,
4100 obj
->base
.size
, align
);
4102 DRM_ERROR("failed to init phys object %d size: %zu\n",
4103 id
, obj
->base
.size
);
4108 /* bind to the object */
4109 obj
->phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
4110 obj
->phys_obj
->cur_obj
= obj
;
4112 page_count
= obj
->base
.size
/ PAGE_SIZE
;
4114 for (i
= 0; i
< page_count
; i
++) {
4118 page
= shmem_read_mapping_page(mapping
, i
);
4120 return PTR_ERR(page
);
4122 src
= kmap_atomic(page
);
4123 dst
= obj
->phys_obj
->handle
->vaddr
+ (i
* PAGE_SIZE
);
4124 memcpy(dst
, src
, PAGE_SIZE
);
4127 mark_page_accessed(page
);
4128 page_cache_release(page
);
4135 i915_gem_phys_pwrite(struct drm_device
*dev
,
4136 struct drm_i915_gem_object
*obj
,
4137 struct drm_i915_gem_pwrite
*args
,
4138 struct drm_file
*file_priv
)
4140 void *vaddr
= obj
->phys_obj
->handle
->vaddr
+ args
->offset
;
4141 char __user
*user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
4143 if (__copy_from_user_inatomic_nocache(vaddr
, user_data
, args
->size
)) {
4144 unsigned long unwritten
;
4146 /* The physical object once assigned is fixed for the lifetime
4147 * of the obj, so we can safely drop the lock and continue
4150 mutex_unlock(&dev
->struct_mutex
);
4151 unwritten
= copy_from_user(vaddr
, user_data
, args
->size
);
4152 mutex_lock(&dev
->struct_mutex
);
4157 intel_gtt_chipset_flush();
4161 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
)
4163 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
4165 /* Clean up our request list when the client is going away, so that
4166 * later retire_requests won't dereference our soon-to-be-gone
4169 spin_lock(&file_priv
->mm
.lock
);
4170 while (!list_empty(&file_priv
->mm
.request_list
)) {
4171 struct drm_i915_gem_request
*request
;
4173 request
= list_first_entry(&file_priv
->mm
.request_list
,
4174 struct drm_i915_gem_request
,
4176 list_del(&request
->client_list
);
4177 request
->file_priv
= NULL
;
4179 spin_unlock(&file_priv
->mm
.lock
);
4183 i915_gpu_is_active(struct drm_device
*dev
)
4185 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4188 lists_empty
= list_empty(&dev_priv
->mm
.flushing_list
) &&
4189 list_empty(&dev_priv
->mm
.active_list
);
4191 return !lists_empty
;
4195 i915_gem_inactive_shrink(struct shrinker
*shrinker
, struct shrink_control
*sc
)
4197 struct drm_i915_private
*dev_priv
=
4198 container_of(shrinker
,
4199 struct drm_i915_private
,
4200 mm
.inactive_shrinker
);
4201 struct drm_device
*dev
= dev_priv
->dev
;
4202 struct drm_i915_gem_object
*obj
, *next
;
4203 int nr_to_scan
= sc
->nr_to_scan
;
4206 if (!mutex_trylock(&dev
->struct_mutex
))
4209 /* "fast-path" to count number of available objects */
4210 if (nr_to_scan
== 0) {
4212 list_for_each_entry(obj
,
4213 &dev_priv
->mm
.inactive_list
,
4216 mutex_unlock(&dev
->struct_mutex
);
4217 return cnt
/ 100 * sysctl_vfs_cache_pressure
;
4221 /* first scan for clean buffers */
4222 i915_gem_retire_requests(dev
);
4224 list_for_each_entry_safe(obj
, next
,
4225 &dev_priv
->mm
.inactive_list
,
4227 if (i915_gem_object_is_purgeable(obj
)) {
4228 if (i915_gem_object_unbind(obj
) == 0 &&
4234 /* second pass, evict/count anything still on the inactive list */
4236 list_for_each_entry_safe(obj
, next
,
4237 &dev_priv
->mm
.inactive_list
,
4240 i915_gem_object_unbind(obj
) == 0)
4246 if (nr_to_scan
&& i915_gpu_is_active(dev
)) {
4248 * We are desperate for pages, so as a last resort, wait
4249 * for the GPU to finish and discard whatever we can.
4250 * This has a dramatic impact to reduce the number of
4251 * OOM-killer events whilst running the GPU aggressively.
4253 if (i915_gpu_idle(dev
) == 0)
4256 mutex_unlock(&dev
->struct_mutex
);
4257 return cnt
/ 100 * sysctl_vfs_cache_pressure
;