2 * Copyright © 2008-2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/drm_vma_manager.h>
30 #include <drm/i915_drm.h>
32 #include "i915_vgpu.h"
33 #include "i915_trace.h"
34 #include "intel_drv.h"
35 #include <linux/shmem_fs.h>
36 #include <linux/slab.h>
37 #include <linux/swap.h>
38 #include <linux/pci.h>
39 #include <linux/dma-buf.h>
41 #define RQ_BUG_ON(expr)
43 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
);
44 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
);
46 i915_gem_object_retire__write(struct drm_i915_gem_object
*obj
);
48 i915_gem_object_retire__read(struct drm_i915_gem_object
*obj
, int ring
);
49 static void i915_gem_write_fence(struct drm_device
*dev
, int reg
,
50 struct drm_i915_gem_object
*obj
);
51 static void i915_gem_object_update_fence(struct drm_i915_gem_object
*obj
,
52 struct drm_i915_fence_reg
*fence
,
55 static bool cpu_cache_is_coherent(struct drm_device
*dev
,
56 enum i915_cache_level level
)
58 return HAS_LLC(dev
) || level
!= I915_CACHE_NONE
;
61 static bool cpu_write_needs_clflush(struct drm_i915_gem_object
*obj
)
63 if (!cpu_cache_is_coherent(obj
->base
.dev
, obj
->cache_level
))
66 return obj
->pin_display
;
69 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object
*obj
)
72 i915_gem_release_mmap(obj
);
74 /* As we do not have an associated fence register, we will force
75 * a tiling change if we ever need to acquire one.
77 obj
->fence_dirty
= false;
78 obj
->fence_reg
= I915_FENCE_REG_NONE
;
81 /* some bookkeeping */
82 static void i915_gem_info_add_obj(struct drm_i915_private
*dev_priv
,
85 spin_lock(&dev_priv
->mm
.object_stat_lock
);
86 dev_priv
->mm
.object_count
++;
87 dev_priv
->mm
.object_memory
+= size
;
88 spin_unlock(&dev_priv
->mm
.object_stat_lock
);
91 static void i915_gem_info_remove_obj(struct drm_i915_private
*dev_priv
,
94 spin_lock(&dev_priv
->mm
.object_stat_lock
);
95 dev_priv
->mm
.object_count
--;
96 dev_priv
->mm
.object_memory
-= size
;
97 spin_unlock(&dev_priv
->mm
.object_stat_lock
);
101 i915_gem_wait_for_error(struct i915_gpu_error
*error
)
105 #define EXIT_COND (!i915_reset_in_progress(error) || \
106 i915_terminally_wedged(error))
111 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
112 * userspace. If it takes that long something really bad is going on and
113 * we should simply try to bail out and fail as gracefully as possible.
115 ret
= wait_event_interruptible_timeout(error
->reset_queue
,
119 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
121 } else if (ret
< 0) {
129 int i915_mutex_lock_interruptible(struct drm_device
*dev
)
131 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
134 ret
= i915_gem_wait_for_error(&dev_priv
->gpu_error
);
138 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
142 WARN_ON(i915_verify_lists(dev
));
147 i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
148 struct drm_file
*file
)
150 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
151 struct drm_i915_gem_get_aperture
*args
= data
;
152 struct drm_i915_gem_object
*obj
;
156 mutex_lock(&dev
->struct_mutex
);
157 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
)
158 if (i915_gem_obj_is_pinned(obj
))
159 pinned
+= i915_gem_obj_ggtt_size(obj
);
160 mutex_unlock(&dev
->struct_mutex
);
162 args
->aper_size
= dev_priv
->gtt
.base
.total
;
163 args
->aper_available_size
= args
->aper_size
- pinned
;
169 i915_gem_object_get_pages_phys(struct drm_i915_gem_object
*obj
)
171 struct address_space
*mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
172 char *vaddr
= obj
->phys_handle
->vaddr
;
174 struct scatterlist
*sg
;
177 if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj
)))
180 for (i
= 0; i
< obj
->base
.size
/ PAGE_SIZE
; i
++) {
184 page
= shmem_read_mapping_page(mapping
, i
);
186 return PTR_ERR(page
);
188 src
= kmap_atomic(page
);
189 memcpy(vaddr
, src
, PAGE_SIZE
);
190 drm_clflush_virt_range(vaddr
, PAGE_SIZE
);
193 page_cache_release(page
);
197 i915_gem_chipset_flush(obj
->base
.dev
);
199 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
203 if (sg_alloc_table(st
, 1, GFP_KERNEL
)) {
210 sg
->length
= obj
->base
.size
;
212 sg_dma_address(sg
) = obj
->phys_handle
->busaddr
;
213 sg_dma_len(sg
) = obj
->base
.size
;
216 obj
->has_dma_mapping
= true;
221 i915_gem_object_put_pages_phys(struct drm_i915_gem_object
*obj
)
225 BUG_ON(obj
->madv
== __I915_MADV_PURGED
);
227 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
229 /* In the event of a disaster, abandon all caches and
232 WARN_ON(ret
!= -EIO
);
233 obj
->base
.read_domains
= obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
236 if (obj
->madv
== I915_MADV_DONTNEED
)
240 struct address_space
*mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
241 char *vaddr
= obj
->phys_handle
->vaddr
;
244 for (i
= 0; i
< obj
->base
.size
/ PAGE_SIZE
; i
++) {
248 page
= shmem_read_mapping_page(mapping
, i
);
252 dst
= kmap_atomic(page
);
253 drm_clflush_virt_range(vaddr
, PAGE_SIZE
);
254 memcpy(dst
, vaddr
, PAGE_SIZE
);
257 set_page_dirty(page
);
258 if (obj
->madv
== I915_MADV_WILLNEED
)
259 mark_page_accessed(page
);
260 page_cache_release(page
);
266 sg_free_table(obj
->pages
);
269 obj
->has_dma_mapping
= false;
273 i915_gem_object_release_phys(struct drm_i915_gem_object
*obj
)
275 drm_pci_free(obj
->base
.dev
, obj
->phys_handle
);
278 static const struct drm_i915_gem_object_ops i915_gem_phys_ops
= {
279 .get_pages
= i915_gem_object_get_pages_phys
,
280 .put_pages
= i915_gem_object_put_pages_phys
,
281 .release
= i915_gem_object_release_phys
,
285 drop_pages(struct drm_i915_gem_object
*obj
)
287 struct i915_vma
*vma
, *next
;
290 drm_gem_object_reference(&obj
->base
);
291 list_for_each_entry_safe(vma
, next
, &obj
->vma_list
, vma_link
)
292 if (i915_vma_unbind(vma
))
295 ret
= i915_gem_object_put_pages(obj
);
296 drm_gem_object_unreference(&obj
->base
);
302 i915_gem_object_attach_phys(struct drm_i915_gem_object
*obj
,
305 drm_dma_handle_t
*phys
;
308 if (obj
->phys_handle
) {
309 if ((unsigned long)obj
->phys_handle
->vaddr
& (align
-1))
315 if (obj
->madv
!= I915_MADV_WILLNEED
)
318 if (obj
->base
.filp
== NULL
)
321 ret
= drop_pages(obj
);
325 /* create a new object */
326 phys
= drm_pci_alloc(obj
->base
.dev
, obj
->base
.size
, align
);
330 obj
->phys_handle
= phys
;
331 obj
->ops
= &i915_gem_phys_ops
;
333 return i915_gem_object_get_pages(obj
);
337 i915_gem_phys_pwrite(struct drm_i915_gem_object
*obj
,
338 struct drm_i915_gem_pwrite
*args
,
339 struct drm_file
*file_priv
)
341 struct drm_device
*dev
= obj
->base
.dev
;
342 void *vaddr
= obj
->phys_handle
->vaddr
+ args
->offset
;
343 char __user
*user_data
= to_user_ptr(args
->data_ptr
);
346 /* We manually control the domain here and pretend that it
347 * remains coherent i.e. in the GTT domain, like shmem_pwrite.
349 ret
= i915_gem_object_wait_rendering(obj
, false);
353 intel_fb_obj_invalidate(obj
, ORIGIN_CPU
);
354 if (__copy_from_user_inatomic_nocache(vaddr
, user_data
, args
->size
)) {
355 unsigned long unwritten
;
357 /* The physical object once assigned is fixed for the lifetime
358 * of the obj, so we can safely drop the lock and continue
361 mutex_unlock(&dev
->struct_mutex
);
362 unwritten
= copy_from_user(vaddr
, user_data
, args
->size
);
363 mutex_lock(&dev
->struct_mutex
);
370 drm_clflush_virt_range(vaddr
, args
->size
);
371 i915_gem_chipset_flush(dev
);
374 intel_fb_obj_flush(obj
, false);
378 void *i915_gem_object_alloc(struct drm_device
*dev
)
380 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
381 return kmem_cache_zalloc(dev_priv
->objects
, GFP_KERNEL
);
384 void i915_gem_object_free(struct drm_i915_gem_object
*obj
)
386 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
387 kmem_cache_free(dev_priv
->objects
, obj
);
391 i915_gem_create(struct drm_file
*file
,
392 struct drm_device
*dev
,
396 struct drm_i915_gem_object
*obj
;
400 size
= roundup(size
, PAGE_SIZE
);
404 /* Allocate the new object */
405 obj
= i915_gem_alloc_object(dev
, size
);
409 ret
= drm_gem_handle_create(file
, &obj
->base
, &handle
);
410 /* drop reference from allocate - handle holds it now */
411 drm_gem_object_unreference_unlocked(&obj
->base
);
420 i915_gem_dumb_create(struct drm_file
*file
,
421 struct drm_device
*dev
,
422 struct drm_mode_create_dumb
*args
)
424 /* have to work out size/pitch and return them */
425 args
->pitch
= ALIGN(args
->width
* DIV_ROUND_UP(args
->bpp
, 8), 64);
426 args
->size
= args
->pitch
* args
->height
;
427 return i915_gem_create(file
, dev
,
428 args
->size
, &args
->handle
);
432 * Creates a new mm object and returns a handle to it.
435 i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
436 struct drm_file
*file
)
438 struct drm_i915_gem_create
*args
= data
;
440 return i915_gem_create(file
, dev
,
441 args
->size
, &args
->handle
);
445 __copy_to_user_swizzled(char __user
*cpu_vaddr
,
446 const char *gpu_vaddr
, int gpu_offset
,
449 int ret
, cpu_offset
= 0;
452 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
453 int this_length
= min(cacheline_end
- gpu_offset
, length
);
454 int swizzled_gpu_offset
= gpu_offset
^ 64;
456 ret
= __copy_to_user(cpu_vaddr
+ cpu_offset
,
457 gpu_vaddr
+ swizzled_gpu_offset
,
462 cpu_offset
+= this_length
;
463 gpu_offset
+= this_length
;
464 length
-= this_length
;
471 __copy_from_user_swizzled(char *gpu_vaddr
, int gpu_offset
,
472 const char __user
*cpu_vaddr
,
475 int ret
, cpu_offset
= 0;
478 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
479 int this_length
= min(cacheline_end
- gpu_offset
, length
);
480 int swizzled_gpu_offset
= gpu_offset
^ 64;
482 ret
= __copy_from_user(gpu_vaddr
+ swizzled_gpu_offset
,
483 cpu_vaddr
+ cpu_offset
,
488 cpu_offset
+= this_length
;
489 gpu_offset
+= this_length
;
490 length
-= this_length
;
497 * Pins the specified object's pages and synchronizes the object with
498 * GPU accesses. Sets needs_clflush to non-zero if the caller should
499 * flush the object from the CPU cache.
501 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object
*obj
,
511 if (!(obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
)) {
512 /* If we're not in the cpu read domain, set ourself into the gtt
513 * read domain and manually flush cachelines (if required). This
514 * optimizes for the case when the gpu will dirty the data
515 * anyway again before the next pread happens. */
516 *needs_clflush
= !cpu_cache_is_coherent(obj
->base
.dev
,
518 ret
= i915_gem_object_wait_rendering(obj
, true);
523 ret
= i915_gem_object_get_pages(obj
);
527 i915_gem_object_pin_pages(obj
);
532 /* Per-page copy function for the shmem pread fastpath.
533 * Flushes invalid cachelines before reading the target if
534 * needs_clflush is set. */
536 shmem_pread_fast(struct page
*page
, int shmem_page_offset
, int page_length
,
537 char __user
*user_data
,
538 bool page_do_bit17_swizzling
, bool needs_clflush
)
543 if (unlikely(page_do_bit17_swizzling
))
546 vaddr
= kmap_atomic(page
);
548 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
550 ret
= __copy_to_user_inatomic(user_data
,
551 vaddr
+ shmem_page_offset
,
553 kunmap_atomic(vaddr
);
555 return ret
? -EFAULT
: 0;
559 shmem_clflush_swizzled_range(char *addr
, unsigned long length
,
562 if (unlikely(swizzled
)) {
563 unsigned long start
= (unsigned long) addr
;
564 unsigned long end
= (unsigned long) addr
+ length
;
566 /* For swizzling simply ensure that we always flush both
567 * channels. Lame, but simple and it works. Swizzled
568 * pwrite/pread is far from a hotpath - current userspace
569 * doesn't use it at all. */
570 start
= round_down(start
, 128);
571 end
= round_up(end
, 128);
573 drm_clflush_virt_range((void *)start
, end
- start
);
575 drm_clflush_virt_range(addr
, length
);
580 /* Only difference to the fast-path function is that this can handle bit17
581 * and uses non-atomic copy and kmap functions. */
583 shmem_pread_slow(struct page
*page
, int shmem_page_offset
, int page_length
,
584 char __user
*user_data
,
585 bool page_do_bit17_swizzling
, bool needs_clflush
)
592 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
594 page_do_bit17_swizzling
);
596 if (page_do_bit17_swizzling
)
597 ret
= __copy_to_user_swizzled(user_data
,
598 vaddr
, shmem_page_offset
,
601 ret
= __copy_to_user(user_data
,
602 vaddr
+ shmem_page_offset
,
606 return ret
? - EFAULT
: 0;
610 i915_gem_shmem_pread(struct drm_device
*dev
,
611 struct drm_i915_gem_object
*obj
,
612 struct drm_i915_gem_pread
*args
,
613 struct drm_file
*file
)
615 char __user
*user_data
;
618 int shmem_page_offset
, page_length
, ret
= 0;
619 int obj_do_bit17_swizzling
, page_do_bit17_swizzling
;
621 int needs_clflush
= 0;
622 struct sg_page_iter sg_iter
;
624 user_data
= to_user_ptr(args
->data_ptr
);
627 obj_do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
629 ret
= i915_gem_obj_prepare_shmem_read(obj
, &needs_clflush
);
633 offset
= args
->offset
;
635 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
,
636 offset
>> PAGE_SHIFT
) {
637 struct page
*page
= sg_page_iter_page(&sg_iter
);
642 /* Operation in this page
644 * shmem_page_offset = offset within page in shmem file
645 * page_length = bytes to copy for this page
647 shmem_page_offset
= offset_in_page(offset
);
648 page_length
= remain
;
649 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
650 page_length
= PAGE_SIZE
- shmem_page_offset
;
652 page_do_bit17_swizzling
= obj_do_bit17_swizzling
&&
653 (page_to_phys(page
) & (1 << 17)) != 0;
655 ret
= shmem_pread_fast(page
, shmem_page_offset
, page_length
,
656 user_data
, page_do_bit17_swizzling
,
661 mutex_unlock(&dev
->struct_mutex
);
663 if (likely(!i915
.prefault_disable
) && !prefaulted
) {
664 ret
= fault_in_multipages_writeable(user_data
, remain
);
665 /* Userspace is tricking us, but we've already clobbered
666 * its pages with the prefault and promised to write the
667 * data up to the first fault. Hence ignore any errors
668 * and just continue. */
673 ret
= shmem_pread_slow(page
, shmem_page_offset
, page_length
,
674 user_data
, page_do_bit17_swizzling
,
677 mutex_lock(&dev
->struct_mutex
);
683 remain
-= page_length
;
684 user_data
+= page_length
;
685 offset
+= page_length
;
689 i915_gem_object_unpin_pages(obj
);
695 * Reads data from the object referenced by handle.
697 * On error, the contents of *data are undefined.
700 i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
701 struct drm_file
*file
)
703 struct drm_i915_gem_pread
*args
= data
;
704 struct drm_i915_gem_object
*obj
;
710 if (!access_ok(VERIFY_WRITE
,
711 to_user_ptr(args
->data_ptr
),
715 ret
= i915_mutex_lock_interruptible(dev
);
719 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
720 if (&obj
->base
== NULL
) {
725 /* Bounds check source. */
726 if (args
->offset
> obj
->base
.size
||
727 args
->size
> obj
->base
.size
- args
->offset
) {
732 /* prime objects have no backing filp to GEM pread/pwrite
735 if (!obj
->base
.filp
) {
740 trace_i915_gem_object_pread(obj
, args
->offset
, args
->size
);
742 ret
= i915_gem_shmem_pread(dev
, obj
, args
, file
);
745 drm_gem_object_unreference(&obj
->base
);
747 mutex_unlock(&dev
->struct_mutex
);
751 /* This is the fast write path which cannot handle
752 * page faults in the source data
756 fast_user_write(struct io_mapping
*mapping
,
757 loff_t page_base
, int page_offset
,
758 char __user
*user_data
,
761 void __iomem
*vaddr_atomic
;
763 unsigned long unwritten
;
765 vaddr_atomic
= io_mapping_map_atomic_wc(mapping
, page_base
);
766 /* We can use the cpu mem copy function because this is X86. */
767 vaddr
= (void __force
*)vaddr_atomic
+ page_offset
;
768 unwritten
= __copy_from_user_inatomic_nocache(vaddr
,
770 io_mapping_unmap_atomic(vaddr_atomic
);
775 * This is the fast pwrite path, where we copy the data directly from the
776 * user into the GTT, uncached.
779 i915_gem_gtt_pwrite_fast(struct drm_device
*dev
,
780 struct drm_i915_gem_object
*obj
,
781 struct drm_i915_gem_pwrite
*args
,
782 struct drm_file
*file
)
784 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
786 loff_t offset
, page_base
;
787 char __user
*user_data
;
788 int page_offset
, page_length
, ret
;
790 ret
= i915_gem_obj_ggtt_pin(obj
, 0, PIN_MAPPABLE
| PIN_NONBLOCK
);
794 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
798 ret
= i915_gem_object_put_fence(obj
);
802 user_data
= to_user_ptr(args
->data_ptr
);
805 offset
= i915_gem_obj_ggtt_offset(obj
) + args
->offset
;
807 intel_fb_obj_invalidate(obj
, ORIGIN_GTT
);
810 /* Operation in this page
812 * page_base = page offset within aperture
813 * page_offset = offset within page
814 * page_length = bytes to copy for this page
816 page_base
= offset
& PAGE_MASK
;
817 page_offset
= offset_in_page(offset
);
818 page_length
= remain
;
819 if ((page_offset
+ remain
) > PAGE_SIZE
)
820 page_length
= PAGE_SIZE
- page_offset
;
822 /* If we get a fault while copying data, then (presumably) our
823 * source page isn't available. Return the error and we'll
824 * retry in the slow path.
826 if (fast_user_write(dev_priv
->gtt
.mappable
, page_base
,
827 page_offset
, user_data
, page_length
)) {
832 remain
-= page_length
;
833 user_data
+= page_length
;
834 offset
+= page_length
;
838 intel_fb_obj_flush(obj
, false);
840 i915_gem_object_ggtt_unpin(obj
);
845 /* Per-page copy function for the shmem pwrite fastpath.
846 * Flushes invalid cachelines before writing to the target if
847 * needs_clflush_before is set and flushes out any written cachelines after
848 * writing if needs_clflush is set. */
850 shmem_pwrite_fast(struct page
*page
, int shmem_page_offset
, int page_length
,
851 char __user
*user_data
,
852 bool page_do_bit17_swizzling
,
853 bool needs_clflush_before
,
854 bool needs_clflush_after
)
859 if (unlikely(page_do_bit17_swizzling
))
862 vaddr
= kmap_atomic(page
);
863 if (needs_clflush_before
)
864 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
866 ret
= __copy_from_user_inatomic(vaddr
+ shmem_page_offset
,
867 user_data
, page_length
);
868 if (needs_clflush_after
)
869 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
871 kunmap_atomic(vaddr
);
873 return ret
? -EFAULT
: 0;
876 /* Only difference to the fast-path function is that this can handle bit17
877 * and uses non-atomic copy and kmap functions. */
879 shmem_pwrite_slow(struct page
*page
, int shmem_page_offset
, int page_length
,
880 char __user
*user_data
,
881 bool page_do_bit17_swizzling
,
882 bool needs_clflush_before
,
883 bool needs_clflush_after
)
889 if (unlikely(needs_clflush_before
|| page_do_bit17_swizzling
))
890 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
892 page_do_bit17_swizzling
);
893 if (page_do_bit17_swizzling
)
894 ret
= __copy_from_user_swizzled(vaddr
, shmem_page_offset
,
898 ret
= __copy_from_user(vaddr
+ shmem_page_offset
,
901 if (needs_clflush_after
)
902 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
904 page_do_bit17_swizzling
);
907 return ret
? -EFAULT
: 0;
911 i915_gem_shmem_pwrite(struct drm_device
*dev
,
912 struct drm_i915_gem_object
*obj
,
913 struct drm_i915_gem_pwrite
*args
,
914 struct drm_file
*file
)
918 char __user
*user_data
;
919 int shmem_page_offset
, page_length
, ret
= 0;
920 int obj_do_bit17_swizzling
, page_do_bit17_swizzling
;
921 int hit_slowpath
= 0;
922 int needs_clflush_after
= 0;
923 int needs_clflush_before
= 0;
924 struct sg_page_iter sg_iter
;
926 user_data
= to_user_ptr(args
->data_ptr
);
929 obj_do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
931 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
932 /* If we're not in the cpu write domain, set ourself into the gtt
933 * write domain and manually flush cachelines (if required). This
934 * optimizes for the case when the gpu will use the data
935 * right away and we therefore have to clflush anyway. */
936 needs_clflush_after
= cpu_write_needs_clflush(obj
);
937 ret
= i915_gem_object_wait_rendering(obj
, false);
941 /* Same trick applies to invalidate partially written cachelines read
943 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) == 0)
944 needs_clflush_before
=
945 !cpu_cache_is_coherent(dev
, obj
->cache_level
);
947 ret
= i915_gem_object_get_pages(obj
);
951 intel_fb_obj_invalidate(obj
, ORIGIN_CPU
);
953 i915_gem_object_pin_pages(obj
);
955 offset
= args
->offset
;
958 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
,
959 offset
>> PAGE_SHIFT
) {
960 struct page
*page
= sg_page_iter_page(&sg_iter
);
961 int partial_cacheline_write
;
966 /* Operation in this page
968 * shmem_page_offset = offset within page in shmem file
969 * page_length = bytes to copy for this page
971 shmem_page_offset
= offset_in_page(offset
);
973 page_length
= remain
;
974 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
975 page_length
= PAGE_SIZE
- shmem_page_offset
;
977 /* If we don't overwrite a cacheline completely we need to be
978 * careful to have up-to-date data by first clflushing. Don't
979 * overcomplicate things and flush the entire patch. */
980 partial_cacheline_write
= needs_clflush_before
&&
981 ((shmem_page_offset
| page_length
)
982 & (boot_cpu_data
.x86_clflush_size
- 1));
984 page_do_bit17_swizzling
= obj_do_bit17_swizzling
&&
985 (page_to_phys(page
) & (1 << 17)) != 0;
987 ret
= shmem_pwrite_fast(page
, shmem_page_offset
, page_length
,
988 user_data
, page_do_bit17_swizzling
,
989 partial_cacheline_write
,
990 needs_clflush_after
);
995 mutex_unlock(&dev
->struct_mutex
);
996 ret
= shmem_pwrite_slow(page
, shmem_page_offset
, page_length
,
997 user_data
, page_do_bit17_swizzling
,
998 partial_cacheline_write
,
999 needs_clflush_after
);
1001 mutex_lock(&dev
->struct_mutex
);
1007 remain
-= page_length
;
1008 user_data
+= page_length
;
1009 offset
+= page_length
;
1013 i915_gem_object_unpin_pages(obj
);
1017 * Fixup: Flush cpu caches in case we didn't flush the dirty
1018 * cachelines in-line while writing and the object moved
1019 * out of the cpu write domain while we've dropped the lock.
1021 if (!needs_clflush_after
&&
1022 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
1023 if (i915_gem_clflush_object(obj
, obj
->pin_display
))
1024 i915_gem_chipset_flush(dev
);
1028 if (needs_clflush_after
)
1029 i915_gem_chipset_flush(dev
);
1031 intel_fb_obj_flush(obj
, false);
1036 * Writes data to the object referenced by handle.
1038 * On error, the contents of the buffer that were to be modified are undefined.
1041 i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
1042 struct drm_file
*file
)
1044 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1045 struct drm_i915_gem_pwrite
*args
= data
;
1046 struct drm_i915_gem_object
*obj
;
1049 if (args
->size
== 0)
1052 if (!access_ok(VERIFY_READ
,
1053 to_user_ptr(args
->data_ptr
),
1057 if (likely(!i915
.prefault_disable
)) {
1058 ret
= fault_in_multipages_readable(to_user_ptr(args
->data_ptr
),
1064 intel_runtime_pm_get(dev_priv
);
1066 ret
= i915_mutex_lock_interruptible(dev
);
1070 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1071 if (&obj
->base
== NULL
) {
1076 /* Bounds check destination. */
1077 if (args
->offset
> obj
->base
.size
||
1078 args
->size
> obj
->base
.size
- args
->offset
) {
1083 /* prime objects have no backing filp to GEM pread/pwrite
1086 if (!obj
->base
.filp
) {
1091 trace_i915_gem_object_pwrite(obj
, args
->offset
, args
->size
);
1094 /* We can only do the GTT pwrite on untiled buffers, as otherwise
1095 * it would end up going through the fenced access, and we'll get
1096 * different detiling behavior between reading and writing.
1097 * pread/pwrite currently are reading and writing from the CPU
1098 * perspective, requiring manual detiling by the client.
1100 if (obj
->tiling_mode
== I915_TILING_NONE
&&
1101 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
&&
1102 cpu_write_needs_clflush(obj
)) {
1103 ret
= i915_gem_gtt_pwrite_fast(dev
, obj
, args
, file
);
1104 /* Note that the gtt paths might fail with non-page-backed user
1105 * pointers (e.g. gtt mappings when moving data between
1106 * textures). Fallback to the shmem path in that case. */
1109 if (ret
== -EFAULT
|| ret
== -ENOSPC
) {
1110 if (obj
->phys_handle
)
1111 ret
= i915_gem_phys_pwrite(obj
, args
, file
);
1113 ret
= i915_gem_shmem_pwrite(dev
, obj
, args
, file
);
1117 drm_gem_object_unreference(&obj
->base
);
1119 mutex_unlock(&dev
->struct_mutex
);
1121 intel_runtime_pm_put(dev_priv
);
1127 i915_gem_check_wedge(struct i915_gpu_error
*error
,
1130 if (i915_reset_in_progress(error
)) {
1131 /* Non-interruptible callers can't handle -EAGAIN, hence return
1132 * -EIO unconditionally for these. */
1136 /* Recovery complete, but the reset failed ... */
1137 if (i915_terminally_wedged(error
))
1141 * Check if GPU Reset is in progress - we need intel_ring_begin
1142 * to work properly to reinit the hw state while the gpu is
1143 * still marked as reset-in-progress. Handle this with a flag.
1145 if (!error
->reload_in_reset
)
1153 * Compare arbitrary request against outstanding lazy request. Emit on match.
1156 i915_gem_check_olr(struct drm_i915_gem_request
*req
)
1158 WARN_ON(!mutex_is_locked(&req
->ring
->dev
->struct_mutex
));
1163 static void fake_irq(unsigned long data
)
1165 wake_up_process((struct task_struct
*)data
);
1168 static bool missed_irq(struct drm_i915_private
*dev_priv
,
1169 struct intel_engine_cs
*ring
)
1171 return test_bit(ring
->id
, &dev_priv
->gpu_error
.missed_irq_rings
);
1174 static int __i915_spin_request(struct drm_i915_gem_request
*req
)
1176 unsigned long timeout
;
1178 if (i915_gem_request_get_ring(req
)->irq_refcount
)
1181 timeout
= jiffies
+ 1;
1182 while (!need_resched()) {
1183 if (i915_gem_request_completed(req
, true))
1186 if (time_after_eq(jiffies
, timeout
))
1189 cpu_relax_lowlatency();
1191 if (i915_gem_request_completed(req
, false))
1198 * __i915_wait_request - wait until execution of request has finished
1200 * @reset_counter: reset sequence associated with the given request
1201 * @interruptible: do an interruptible wait (normally yes)
1202 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
1204 * Note: It is of utmost importance that the passed in seqno and reset_counter
1205 * values have been read by the caller in an smp safe manner. Where read-side
1206 * locks are involved, it is sufficient to read the reset_counter before
1207 * unlocking the lock that protects the seqno. For lockless tricks, the
1208 * reset_counter _must_ be read before, and an appropriate smp_rmb must be
1211 * Returns 0 if the request was found within the alloted time. Else returns the
1212 * errno with remaining time filled in timeout argument.
1214 int __i915_wait_request(struct drm_i915_gem_request
*req
,
1215 unsigned reset_counter
,
1218 struct intel_rps_client
*rps
)
1220 struct intel_engine_cs
*ring
= i915_gem_request_get_ring(req
);
1221 struct drm_device
*dev
= ring
->dev
;
1222 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1223 const bool irq_test_in_progress
=
1224 ACCESS_ONCE(dev_priv
->gpu_error
.test_irq_rings
) & intel_ring_flag(ring
);
1226 unsigned long timeout_expire
;
1230 WARN(!intel_irqs_enabled(dev_priv
), "IRQs disabled");
1232 if (list_empty(&req
->list
))
1235 if (i915_gem_request_completed(req
, true))
1238 timeout_expire
= timeout
?
1239 jiffies
+ nsecs_to_jiffies_timeout((u64
)*timeout
) : 0;
1241 if (INTEL_INFO(dev_priv
)->gen
>= 6)
1242 gen6_rps_boost(dev_priv
, rps
, req
->emitted_jiffies
);
1244 /* Record current time in case interrupted by signal, or wedged */
1245 trace_i915_gem_request_wait_begin(req
);
1246 before
= ktime_get_raw_ns();
1248 /* Optimistic spin for the next jiffie before touching IRQs */
1249 ret
= __i915_spin_request(req
);
1253 if (!irq_test_in_progress
&& WARN_ON(!ring
->irq_get(ring
))) {
1259 struct timer_list timer
;
1261 prepare_to_wait(&ring
->irq_queue
, &wait
,
1262 interruptible
? TASK_INTERRUPTIBLE
: TASK_UNINTERRUPTIBLE
);
1264 /* We need to check whether any gpu reset happened in between
1265 * the caller grabbing the seqno and now ... */
1266 if (reset_counter
!= atomic_read(&dev_priv
->gpu_error
.reset_counter
)) {
1267 /* ... but upgrade the -EAGAIN to an -EIO if the gpu
1268 * is truely gone. */
1269 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, interruptible
);
1275 if (i915_gem_request_completed(req
, false)) {
1280 if (interruptible
&& signal_pending(current
)) {
1285 if (timeout
&& time_after_eq(jiffies
, timeout_expire
)) {
1290 timer
.function
= NULL
;
1291 if (timeout
|| missed_irq(dev_priv
, ring
)) {
1292 unsigned long expire
;
1294 setup_timer_on_stack(&timer
, fake_irq
, (unsigned long)current
);
1295 expire
= missed_irq(dev_priv
, ring
) ? jiffies
+ 1 : timeout_expire
;
1296 mod_timer(&timer
, expire
);
1301 if (timer
.function
) {
1302 del_singleshot_timer_sync(&timer
);
1303 destroy_timer_on_stack(&timer
);
1306 if (!irq_test_in_progress
)
1307 ring
->irq_put(ring
);
1309 finish_wait(&ring
->irq_queue
, &wait
);
1312 now
= ktime_get_raw_ns();
1313 trace_i915_gem_request_wait_end(req
);
1316 s64 tres
= *timeout
- (now
- before
);
1318 *timeout
= tres
< 0 ? 0 : tres
;
1321 * Apparently ktime isn't accurate enough and occasionally has a
1322 * bit of mismatch in the jiffies<->nsecs<->ktime loop. So patch
1323 * things up to make the test happy. We allow up to 1 jiffy.
1325 * This is a regrssion from the timespec->ktime conversion.
1327 if (ret
== -ETIME
&& *timeout
< jiffies_to_usecs(1)*1000)
1334 int i915_gem_request_add_to_client(struct drm_i915_gem_request
*req
,
1335 struct drm_file
*file
)
1337 struct drm_i915_private
*dev_private
;
1338 struct drm_i915_file_private
*file_priv
;
1340 WARN_ON(!req
|| !file
|| req
->file_priv
);
1348 dev_private
= req
->ring
->dev
->dev_private
;
1349 file_priv
= file
->driver_priv
;
1351 spin_lock(&file_priv
->mm
.lock
);
1352 req
->file_priv
= file_priv
;
1353 list_add_tail(&req
->client_list
, &file_priv
->mm
.request_list
);
1354 spin_unlock(&file_priv
->mm
.lock
);
1356 req
->pid
= get_pid(task_pid(current
));
1362 i915_gem_request_remove_from_client(struct drm_i915_gem_request
*request
)
1364 struct drm_i915_file_private
*file_priv
= request
->file_priv
;
1369 spin_lock(&file_priv
->mm
.lock
);
1370 list_del(&request
->client_list
);
1371 request
->file_priv
= NULL
;
1372 spin_unlock(&file_priv
->mm
.lock
);
1374 put_pid(request
->pid
);
1375 request
->pid
= NULL
;
1378 static void i915_gem_request_retire(struct drm_i915_gem_request
*request
)
1380 trace_i915_gem_request_retire(request
);
1382 /* We know the GPU must have read the request to have
1383 * sent us the seqno + interrupt, so use the position
1384 * of tail of the request to update the last known position
1387 * Note this requires that we are always called in request
1390 request
->ringbuf
->last_retired_head
= request
->postfix
;
1392 list_del_init(&request
->list
);
1393 i915_gem_request_remove_from_client(request
);
1395 i915_gem_request_unreference(request
);
1399 __i915_gem_request_retire__upto(struct drm_i915_gem_request
*req
)
1401 struct intel_engine_cs
*engine
= req
->ring
;
1402 struct drm_i915_gem_request
*tmp
;
1404 lockdep_assert_held(&engine
->dev
->struct_mutex
);
1406 if (list_empty(&req
->list
))
1410 tmp
= list_first_entry(&engine
->request_list
,
1411 typeof(*tmp
), list
);
1413 i915_gem_request_retire(tmp
);
1414 } while (tmp
!= req
);
1416 WARN_ON(i915_verify_lists(engine
->dev
));
1420 * Waits for a request to be signaled, and cleans up the
1421 * request and object lists appropriately for that event.
1424 i915_wait_request(struct drm_i915_gem_request
*req
)
1426 struct drm_device
*dev
;
1427 struct drm_i915_private
*dev_priv
;
1431 BUG_ON(req
== NULL
);
1433 dev
= req
->ring
->dev
;
1434 dev_priv
= dev
->dev_private
;
1435 interruptible
= dev_priv
->mm
.interruptible
;
1437 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
1439 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, interruptible
);
1443 ret
= i915_gem_check_olr(req
);
1447 ret
= __i915_wait_request(req
,
1448 atomic_read(&dev_priv
->gpu_error
.reset_counter
),
1449 interruptible
, NULL
, NULL
);
1453 __i915_gem_request_retire__upto(req
);
1458 * Ensures that all rendering to the object has completed and the object is
1459 * safe to unbind from the GTT or access from the CPU.
1462 i915_gem_object_wait_rendering(struct drm_i915_gem_object
*obj
,
1471 if (obj
->last_write_req
!= NULL
) {
1472 ret
= i915_wait_request(obj
->last_write_req
);
1476 i
= obj
->last_write_req
->ring
->id
;
1477 if (obj
->last_read_req
[i
] == obj
->last_write_req
)
1478 i915_gem_object_retire__read(obj
, i
);
1480 i915_gem_object_retire__write(obj
);
1483 for (i
= 0; i
< I915_NUM_RINGS
; i
++) {
1484 if (obj
->last_read_req
[i
] == NULL
)
1487 ret
= i915_wait_request(obj
->last_read_req
[i
]);
1491 i915_gem_object_retire__read(obj
, i
);
1493 RQ_BUG_ON(obj
->active
);
1500 i915_gem_object_retire_request(struct drm_i915_gem_object
*obj
,
1501 struct drm_i915_gem_request
*req
)
1503 int ring
= req
->ring
->id
;
1505 if (obj
->last_read_req
[ring
] == req
)
1506 i915_gem_object_retire__read(obj
, ring
);
1507 else if (obj
->last_write_req
== req
)
1508 i915_gem_object_retire__write(obj
);
1510 __i915_gem_request_retire__upto(req
);
1513 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1514 * as the object state may change during this call.
1516 static __must_check
int
1517 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object
*obj
,
1518 struct intel_rps_client
*rps
,
1521 struct drm_device
*dev
= obj
->base
.dev
;
1522 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1523 struct drm_i915_gem_request
*requests
[I915_NUM_RINGS
];
1524 unsigned reset_counter
;
1527 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
1528 BUG_ON(!dev_priv
->mm
.interruptible
);
1533 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, true);
1537 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
1540 struct drm_i915_gem_request
*req
;
1542 req
= obj
->last_write_req
;
1546 ret
= i915_gem_check_olr(req
);
1550 requests
[n
++] = i915_gem_request_reference(req
);
1552 for (i
= 0; i
< I915_NUM_RINGS
; i
++) {
1553 struct drm_i915_gem_request
*req
;
1555 req
= obj
->last_read_req
[i
];
1559 ret
= i915_gem_check_olr(req
);
1563 requests
[n
++] = i915_gem_request_reference(req
);
1567 mutex_unlock(&dev
->struct_mutex
);
1568 for (i
= 0; ret
== 0 && i
< n
; i
++)
1569 ret
= __i915_wait_request(requests
[i
], reset_counter
, true,
1571 mutex_lock(&dev
->struct_mutex
);
1574 for (i
= 0; i
< n
; i
++) {
1576 i915_gem_object_retire_request(obj
, requests
[i
]);
1577 i915_gem_request_unreference(requests
[i
]);
1583 static struct intel_rps_client
*to_rps_client(struct drm_file
*file
)
1585 struct drm_i915_file_private
*fpriv
= file
->driver_priv
;
1590 * Called when user space prepares to use an object with the CPU, either
1591 * through the mmap ioctl's mapping or a GTT mapping.
1594 i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
1595 struct drm_file
*file
)
1597 struct drm_i915_gem_set_domain
*args
= data
;
1598 struct drm_i915_gem_object
*obj
;
1599 uint32_t read_domains
= args
->read_domains
;
1600 uint32_t write_domain
= args
->write_domain
;
1603 /* Only handle setting domains to types used by the CPU. */
1604 if (write_domain
& I915_GEM_GPU_DOMAINS
)
1607 if (read_domains
& I915_GEM_GPU_DOMAINS
)
1610 /* Having something in the write domain implies it's in the read
1611 * domain, and only that read domain. Enforce that in the request.
1613 if (write_domain
!= 0 && read_domains
!= write_domain
)
1616 ret
= i915_mutex_lock_interruptible(dev
);
1620 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1621 if (&obj
->base
== NULL
) {
1626 /* Try to flush the object off the GPU without holding the lock.
1627 * We will repeat the flush holding the lock in the normal manner
1628 * to catch cases where we are gazumped.
1630 ret
= i915_gem_object_wait_rendering__nonblocking(obj
,
1631 to_rps_client(file
),
1636 if (read_domains
& I915_GEM_DOMAIN_GTT
)
1637 ret
= i915_gem_object_set_to_gtt_domain(obj
, write_domain
!= 0);
1639 ret
= i915_gem_object_set_to_cpu_domain(obj
, write_domain
!= 0);
1642 drm_gem_object_unreference(&obj
->base
);
1644 mutex_unlock(&dev
->struct_mutex
);
1649 * Called when user space has done writes to this buffer
1652 i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1653 struct drm_file
*file
)
1655 struct drm_i915_gem_sw_finish
*args
= data
;
1656 struct drm_i915_gem_object
*obj
;
1659 ret
= i915_mutex_lock_interruptible(dev
);
1663 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1664 if (&obj
->base
== NULL
) {
1669 /* Pinned buffers may be scanout, so flush the cache */
1670 if (obj
->pin_display
)
1671 i915_gem_object_flush_cpu_write_domain(obj
);
1673 drm_gem_object_unreference(&obj
->base
);
1675 mutex_unlock(&dev
->struct_mutex
);
1680 * Maps the contents of an object, returning the address it is mapped
1683 * While the mapping holds a reference on the contents of the object, it doesn't
1684 * imply a ref on the object itself.
1688 * DRM driver writers who look a this function as an example for how to do GEM
1689 * mmap support, please don't implement mmap support like here. The modern way
1690 * to implement DRM mmap support is with an mmap offset ioctl (like
1691 * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly.
1692 * That way debug tooling like valgrind will understand what's going on, hiding
1693 * the mmap call in a driver private ioctl will break that. The i915 driver only
1694 * does cpu mmaps this way because we didn't know better.
1697 i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1698 struct drm_file
*file
)
1700 struct drm_i915_gem_mmap
*args
= data
;
1701 struct drm_gem_object
*obj
;
1704 if (args
->flags
& ~(I915_MMAP_WC
))
1707 if (args
->flags
& I915_MMAP_WC
&& !cpu_has_pat
)
1710 obj
= drm_gem_object_lookup(dev
, file
, args
->handle
);
1714 /* prime objects have no backing filp to GEM mmap
1718 drm_gem_object_unreference_unlocked(obj
);
1722 addr
= vm_mmap(obj
->filp
, 0, args
->size
,
1723 PROT_READ
| PROT_WRITE
, MAP_SHARED
,
1725 if (args
->flags
& I915_MMAP_WC
) {
1726 struct mm_struct
*mm
= current
->mm
;
1727 struct vm_area_struct
*vma
;
1729 down_write(&mm
->mmap_sem
);
1730 vma
= find_vma(mm
, addr
);
1733 pgprot_writecombine(vm_get_page_prot(vma
->vm_flags
));
1736 up_write(&mm
->mmap_sem
);
1738 drm_gem_object_unreference_unlocked(obj
);
1739 if (IS_ERR((void *)addr
))
1742 args
->addr_ptr
= (uint64_t) addr
;
1748 * i915_gem_fault - fault a page into the GTT
1749 * vma: VMA in question
1752 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1753 * from userspace. The fault handler takes care of binding the object to
1754 * the GTT (if needed), allocating and programming a fence register (again,
1755 * only if needed based on whether the old reg is still valid or the object
1756 * is tiled) and inserting a new PTE into the faulting process.
1758 * Note that the faulting process may involve evicting existing objects
1759 * from the GTT and/or fence registers to make room. So performance may
1760 * suffer if the GTT working set is large or there are few fence registers
1763 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
)
1765 struct drm_i915_gem_object
*obj
= to_intel_bo(vma
->vm_private_data
);
1766 struct drm_device
*dev
= obj
->base
.dev
;
1767 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1768 struct i915_ggtt_view view
= i915_ggtt_view_normal
;
1769 pgoff_t page_offset
;
1772 bool write
= !!(vmf
->flags
& FAULT_FLAG_WRITE
);
1774 intel_runtime_pm_get(dev_priv
);
1776 /* We don't use vmf->pgoff since that has the fake offset */
1777 page_offset
= ((unsigned long)vmf
->virtual_address
- vma
->vm_start
) >>
1780 ret
= i915_mutex_lock_interruptible(dev
);
1784 trace_i915_gem_object_fault(obj
, page_offset
, true, write
);
1786 /* Try to flush the object off the GPU first without holding the lock.
1787 * Upon reacquiring the lock, we will perform our sanity checks and then
1788 * repeat the flush holding the lock in the normal manner to catch cases
1789 * where we are gazumped.
1791 ret
= i915_gem_object_wait_rendering__nonblocking(obj
, NULL
, !write
);
1795 /* Access to snoopable pages through the GTT is incoherent. */
1796 if (obj
->cache_level
!= I915_CACHE_NONE
&& !HAS_LLC(dev
)) {
1801 /* Use a partial view if the object is bigger than the aperture. */
1802 if (obj
->base
.size
>= dev_priv
->gtt
.mappable_end
&&
1803 obj
->tiling_mode
== I915_TILING_NONE
) {
1804 static const unsigned int chunk_size
= 256; // 1 MiB
1806 memset(&view
, 0, sizeof(view
));
1807 view
.type
= I915_GGTT_VIEW_PARTIAL
;
1808 view
.params
.partial
.offset
= rounddown(page_offset
, chunk_size
);
1809 view
.params
.partial
.size
=
1812 (vma
->vm_end
- vma
->vm_start
)/PAGE_SIZE
-
1813 view
.params
.partial
.offset
);
1816 /* Now pin it into the GTT if needed */
1817 ret
= i915_gem_object_ggtt_pin(obj
, &view
, 0, PIN_MAPPABLE
);
1821 ret
= i915_gem_object_set_to_gtt_domain(obj
, write
);
1825 ret
= i915_gem_object_get_fence(obj
);
1829 /* Finally, remap it using the new GTT offset */
1830 pfn
= dev_priv
->gtt
.mappable_base
+
1831 i915_gem_obj_ggtt_offset_view(obj
, &view
);
1834 if (unlikely(view
.type
== I915_GGTT_VIEW_PARTIAL
)) {
1835 /* Overriding existing pages in partial view does not cause
1836 * us any trouble as TLBs are still valid because the fault
1837 * is due to userspace losing part of the mapping or never
1838 * having accessed it before (at this partials' range).
1840 unsigned long base
= vma
->vm_start
+
1841 (view
.params
.partial
.offset
<< PAGE_SHIFT
);
1844 for (i
= 0; i
< view
.params
.partial
.size
; i
++) {
1845 ret
= vm_insert_pfn(vma
, base
+ i
* PAGE_SIZE
, pfn
+ i
);
1850 obj
->fault_mappable
= true;
1852 if (!obj
->fault_mappable
) {
1853 unsigned long size
= min_t(unsigned long,
1854 vma
->vm_end
- vma
->vm_start
,
1858 for (i
= 0; i
< size
>> PAGE_SHIFT
; i
++) {
1859 ret
= vm_insert_pfn(vma
,
1860 (unsigned long)vma
->vm_start
+ i
* PAGE_SIZE
,
1866 obj
->fault_mappable
= true;
1868 ret
= vm_insert_pfn(vma
,
1869 (unsigned long)vmf
->virtual_address
,
1873 i915_gem_object_ggtt_unpin_view(obj
, &view
);
1875 mutex_unlock(&dev
->struct_mutex
);
1880 * We eat errors when the gpu is terminally wedged to avoid
1881 * userspace unduly crashing (gl has no provisions for mmaps to
1882 * fail). But any other -EIO isn't ours (e.g. swap in failure)
1883 * and so needs to be reported.
1885 if (!i915_terminally_wedged(&dev_priv
->gpu_error
)) {
1886 ret
= VM_FAULT_SIGBUS
;
1891 * EAGAIN means the gpu is hung and we'll wait for the error
1892 * handler to reset everything when re-faulting in
1893 * i915_mutex_lock_interruptible.
1900 * EBUSY is ok: this just means that another thread
1901 * already did the job.
1903 ret
= VM_FAULT_NOPAGE
;
1910 ret
= VM_FAULT_SIGBUS
;
1913 WARN_ONCE(ret
, "unhandled error in i915_gem_fault: %i\n", ret
);
1914 ret
= VM_FAULT_SIGBUS
;
1918 intel_runtime_pm_put(dev_priv
);
1923 * i915_gem_release_mmap - remove physical page mappings
1924 * @obj: obj in question
1926 * Preserve the reservation of the mmapping with the DRM core code, but
1927 * relinquish ownership of the pages back to the system.
1929 * It is vital that we remove the page mapping if we have mapped a tiled
1930 * object through the GTT and then lose the fence register due to
1931 * resource pressure. Similarly if the object has been moved out of the
1932 * aperture, than pages mapped into userspace must be revoked. Removing the
1933 * mapping will then trigger a page fault on the next user access, allowing
1934 * fixup by i915_gem_fault().
1937 i915_gem_release_mmap(struct drm_i915_gem_object
*obj
)
1939 if (!obj
->fault_mappable
)
1942 drm_vma_node_unmap(&obj
->base
.vma_node
,
1943 obj
->base
.dev
->anon_inode
->i_mapping
);
1944 obj
->fault_mappable
= false;
1948 i915_gem_release_all_mmaps(struct drm_i915_private
*dev_priv
)
1950 struct drm_i915_gem_object
*obj
;
1952 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
)
1953 i915_gem_release_mmap(obj
);
1957 i915_gem_get_gtt_size(struct drm_device
*dev
, uint32_t size
, int tiling_mode
)
1961 if (INTEL_INFO(dev
)->gen
>= 4 ||
1962 tiling_mode
== I915_TILING_NONE
)
1965 /* Previous chips need a power-of-two fence region when tiling */
1966 if (INTEL_INFO(dev
)->gen
== 3)
1967 gtt_size
= 1024*1024;
1969 gtt_size
= 512*1024;
1971 while (gtt_size
< size
)
1978 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1979 * @obj: object to check
1981 * Return the required GTT alignment for an object, taking into account
1982 * potential fence register mapping.
1985 i915_gem_get_gtt_alignment(struct drm_device
*dev
, uint32_t size
,
1986 int tiling_mode
, bool fenced
)
1989 * Minimum alignment is 4k (GTT page size), but might be greater
1990 * if a fence register is needed for the object.
1992 if (INTEL_INFO(dev
)->gen
>= 4 || (!fenced
&& IS_G33(dev
)) ||
1993 tiling_mode
== I915_TILING_NONE
)
1997 * Previous chips need to be aligned to the size of the smallest
1998 * fence register that can contain the object.
2000 return i915_gem_get_gtt_size(dev
, size
, tiling_mode
);
2003 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object
*obj
)
2005 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2008 if (drm_vma_node_has_offset(&obj
->base
.vma_node
))
2011 dev_priv
->mm
.shrinker_no_lock_stealing
= true;
2013 ret
= drm_gem_create_mmap_offset(&obj
->base
);
2017 /* Badly fragmented mmap space? The only way we can recover
2018 * space is by destroying unwanted objects. We can't randomly release
2019 * mmap_offsets as userspace expects them to be persistent for the
2020 * lifetime of the objects. The closest we can is to release the
2021 * offsets on purgeable objects by truncating it and marking it purged,
2022 * which prevents userspace from ever using that object again.
2024 i915_gem_shrink(dev_priv
,
2025 obj
->base
.size
>> PAGE_SHIFT
,
2027 I915_SHRINK_UNBOUND
|
2028 I915_SHRINK_PURGEABLE
);
2029 ret
= drm_gem_create_mmap_offset(&obj
->base
);
2033 i915_gem_shrink_all(dev_priv
);
2034 ret
= drm_gem_create_mmap_offset(&obj
->base
);
2036 dev_priv
->mm
.shrinker_no_lock_stealing
= false;
2041 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object
*obj
)
2043 drm_gem_free_mmap_offset(&obj
->base
);
2047 i915_gem_mmap_gtt(struct drm_file
*file
,
2048 struct drm_device
*dev
,
2052 struct drm_i915_gem_object
*obj
;
2055 ret
= i915_mutex_lock_interruptible(dev
);
2059 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, handle
));
2060 if (&obj
->base
== NULL
) {
2065 if (obj
->madv
!= I915_MADV_WILLNEED
) {
2066 DRM_DEBUG("Attempting to mmap a purgeable buffer\n");
2071 ret
= i915_gem_object_create_mmap_offset(obj
);
2075 *offset
= drm_vma_node_offset_addr(&obj
->base
.vma_node
);
2078 drm_gem_object_unreference(&obj
->base
);
2080 mutex_unlock(&dev
->struct_mutex
);
2085 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
2087 * @data: GTT mapping ioctl data
2088 * @file: GEM object info
2090 * Simply returns the fake offset to userspace so it can mmap it.
2091 * The mmap call will end up in drm_gem_mmap(), which will set things
2092 * up so we can get faults in the handler above.
2094 * The fault handler will take care of binding the object into the GTT
2095 * (since it may have been evicted to make room for something), allocating
2096 * a fence register, and mapping the appropriate aperture address into
2100 i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
2101 struct drm_file
*file
)
2103 struct drm_i915_gem_mmap_gtt
*args
= data
;
2105 return i915_gem_mmap_gtt(file
, dev
, args
->handle
, &args
->offset
);
2108 /* Immediately discard the backing storage */
2110 i915_gem_object_truncate(struct drm_i915_gem_object
*obj
)
2112 i915_gem_object_free_mmap_offset(obj
);
2114 if (obj
->base
.filp
== NULL
)
2117 /* Our goal here is to return as much of the memory as
2118 * is possible back to the system as we are called from OOM.
2119 * To do this we must instruct the shmfs to drop all of its
2120 * backing pages, *now*.
2122 shmem_truncate_range(file_inode(obj
->base
.filp
), 0, (loff_t
)-1);
2123 obj
->madv
= __I915_MADV_PURGED
;
2126 /* Try to discard unwanted pages */
2128 i915_gem_object_invalidate(struct drm_i915_gem_object
*obj
)
2130 struct address_space
*mapping
;
2132 switch (obj
->madv
) {
2133 case I915_MADV_DONTNEED
:
2134 i915_gem_object_truncate(obj
);
2135 case __I915_MADV_PURGED
:
2139 if (obj
->base
.filp
== NULL
)
2142 mapping
= file_inode(obj
->base
.filp
)->i_mapping
,
2143 invalidate_mapping_pages(mapping
, 0, (loff_t
)-1);
2147 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object
*obj
)
2149 struct sg_page_iter sg_iter
;
2152 BUG_ON(obj
->madv
== __I915_MADV_PURGED
);
2154 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
2156 /* In the event of a disaster, abandon all caches and
2157 * hope for the best.
2159 WARN_ON(ret
!= -EIO
);
2160 i915_gem_clflush_object(obj
, true);
2161 obj
->base
.read_domains
= obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
2164 if (i915_gem_object_needs_bit17_swizzle(obj
))
2165 i915_gem_object_save_bit_17_swizzle(obj
);
2167 if (obj
->madv
== I915_MADV_DONTNEED
)
2170 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
, 0) {
2171 struct page
*page
= sg_page_iter_page(&sg_iter
);
2174 set_page_dirty(page
);
2176 if (obj
->madv
== I915_MADV_WILLNEED
)
2177 mark_page_accessed(page
);
2179 page_cache_release(page
);
2183 sg_free_table(obj
->pages
);
2188 i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
)
2190 const struct drm_i915_gem_object_ops
*ops
= obj
->ops
;
2192 if (obj
->pages
== NULL
)
2195 if (obj
->pages_pin_count
)
2198 BUG_ON(i915_gem_obj_bound_any(obj
));
2200 /* ->put_pages might need to allocate memory for the bit17 swizzle
2201 * array, hence protect them from being reaped by removing them from gtt
2203 list_del(&obj
->global_list
);
2205 ops
->put_pages(obj
);
2208 i915_gem_object_invalidate(obj
);
2214 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object
*obj
)
2216 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2218 struct address_space
*mapping
;
2219 struct sg_table
*st
;
2220 struct scatterlist
*sg
;
2221 struct sg_page_iter sg_iter
;
2223 unsigned long last_pfn
= 0; /* suppress gcc warning */
2226 /* Assert that the object is not currently in any GPU domain. As it
2227 * wasn't in the GTT, there shouldn't be any way it could have been in
2230 BUG_ON(obj
->base
.read_domains
& I915_GEM_GPU_DOMAINS
);
2231 BUG_ON(obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
);
2233 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
2237 page_count
= obj
->base
.size
/ PAGE_SIZE
;
2238 if (sg_alloc_table(st
, page_count
, GFP_KERNEL
)) {
2243 /* Get the list of pages out of our struct file. They'll be pinned
2244 * at this point until we release them.
2246 * Fail silently without starting the shrinker
2248 mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
2249 gfp
= mapping_gfp_mask(mapping
);
2250 gfp
|= __GFP_NORETRY
| __GFP_NOWARN
| __GFP_NO_KSWAPD
;
2251 gfp
&= ~(__GFP_IO
| __GFP_WAIT
);
2254 for (i
= 0; i
< page_count
; i
++) {
2255 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
2257 i915_gem_shrink(dev_priv
,
2260 I915_SHRINK_UNBOUND
|
2261 I915_SHRINK_PURGEABLE
);
2262 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
2265 /* We've tried hard to allocate the memory by reaping
2266 * our own buffer, now let the real VM do its job and
2267 * go down in flames if truly OOM.
2269 i915_gem_shrink_all(dev_priv
);
2270 page
= shmem_read_mapping_page(mapping
, i
);
2274 #ifdef CONFIG_SWIOTLB
2275 if (swiotlb_nr_tbl()) {
2277 sg_set_page(sg
, page
, PAGE_SIZE
, 0);
2282 if (!i
|| page_to_pfn(page
) != last_pfn
+ 1) {
2286 sg_set_page(sg
, page
, PAGE_SIZE
, 0);
2288 sg
->length
+= PAGE_SIZE
;
2290 last_pfn
= page_to_pfn(page
);
2292 /* Check that the i965g/gm workaround works. */
2293 WARN_ON((gfp
& __GFP_DMA32
) && (last_pfn
>= 0x00100000UL
));
2295 #ifdef CONFIG_SWIOTLB
2296 if (!swiotlb_nr_tbl())
2301 if (i915_gem_object_needs_bit17_swizzle(obj
))
2302 i915_gem_object_do_bit_17_swizzle(obj
);
2304 if (obj
->tiling_mode
!= I915_TILING_NONE
&&
2305 dev_priv
->quirks
& QUIRK_PIN_SWIZZLED_PAGES
)
2306 i915_gem_object_pin_pages(obj
);
2312 for_each_sg_page(st
->sgl
, &sg_iter
, st
->nents
, 0)
2313 page_cache_release(sg_page_iter_page(&sg_iter
));
2317 /* shmemfs first checks if there is enough memory to allocate the page
2318 * and reports ENOSPC should there be insufficient, along with the usual
2319 * ENOMEM for a genuine allocation failure.
2321 * We use ENOSPC in our driver to mean that we have run out of aperture
2322 * space and so want to translate the error from shmemfs back to our
2323 * usual understanding of ENOMEM.
2325 if (PTR_ERR(page
) == -ENOSPC
)
2328 return PTR_ERR(page
);
2331 /* Ensure that the associated pages are gathered from the backing storage
2332 * and pinned into our object. i915_gem_object_get_pages() may be called
2333 * multiple times before they are released by a single call to
2334 * i915_gem_object_put_pages() - once the pages are no longer referenced
2335 * either as a result of memory pressure (reaping pages under the shrinker)
2336 * or as the object is itself released.
2339 i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
)
2341 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2342 const struct drm_i915_gem_object_ops
*ops
= obj
->ops
;
2348 if (obj
->madv
!= I915_MADV_WILLNEED
) {
2349 DRM_DEBUG("Attempting to obtain a purgeable object\n");
2353 BUG_ON(obj
->pages_pin_count
);
2355 ret
= ops
->get_pages(obj
);
2359 list_add_tail(&obj
->global_list
, &dev_priv
->mm
.unbound_list
);
2361 obj
->get_page
.sg
= obj
->pages
->sgl
;
2362 obj
->get_page
.last
= 0;
2367 void i915_vma_move_to_active(struct i915_vma
*vma
,
2368 struct drm_i915_gem_request
*req
)
2370 struct drm_i915_gem_object
*obj
= vma
->obj
;
2371 struct intel_engine_cs
*ring
;
2373 ring
= i915_gem_request_get_ring(req
);
2375 /* Add a reference if we're newly entering the active list. */
2376 if (obj
->active
== 0)
2377 drm_gem_object_reference(&obj
->base
);
2378 obj
->active
|= intel_ring_flag(ring
);
2380 list_move_tail(&obj
->ring_list
[ring
->id
], &ring
->active_list
);
2381 i915_gem_request_assign(&obj
->last_read_req
[ring
->id
], req
);
2383 list_move_tail(&vma
->mm_list
, &vma
->vm
->active_list
);
2387 i915_gem_object_retire__write(struct drm_i915_gem_object
*obj
)
2389 RQ_BUG_ON(obj
->last_write_req
== NULL
);
2390 RQ_BUG_ON(!(obj
->active
& intel_ring_flag(obj
->last_write_req
->ring
)));
2392 i915_gem_request_assign(&obj
->last_write_req
, NULL
);
2393 intel_fb_obj_flush(obj
, true);
2397 i915_gem_object_retire__read(struct drm_i915_gem_object
*obj
, int ring
)
2399 struct i915_vma
*vma
;
2401 RQ_BUG_ON(obj
->last_read_req
[ring
] == NULL
);
2402 RQ_BUG_ON(!(obj
->active
& (1 << ring
)));
2404 list_del_init(&obj
->ring_list
[ring
]);
2405 i915_gem_request_assign(&obj
->last_read_req
[ring
], NULL
);
2407 if (obj
->last_write_req
&& obj
->last_write_req
->ring
->id
== ring
)
2408 i915_gem_object_retire__write(obj
);
2410 obj
->active
&= ~(1 << ring
);
2414 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
) {
2415 if (!list_empty(&vma
->mm_list
))
2416 list_move_tail(&vma
->mm_list
, &vma
->vm
->inactive_list
);
2419 i915_gem_request_assign(&obj
->last_fenced_req
, NULL
);
2420 drm_gem_object_unreference(&obj
->base
);
2424 i915_gem_init_seqno(struct drm_device
*dev
, u32 seqno
)
2426 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2427 struct intel_engine_cs
*ring
;
2430 /* Carefully retire all requests without writing to the rings */
2431 for_each_ring(ring
, dev_priv
, i
) {
2432 ret
= intel_ring_idle(ring
);
2436 i915_gem_retire_requests(dev
);
2438 /* Finally reset hw state */
2439 for_each_ring(ring
, dev_priv
, i
) {
2440 intel_ring_init_seqno(ring
, seqno
);
2442 for (j
= 0; j
< ARRAY_SIZE(ring
->semaphore
.sync_seqno
); j
++)
2443 ring
->semaphore
.sync_seqno
[j
] = 0;
2449 int i915_gem_set_seqno(struct drm_device
*dev
, u32 seqno
)
2451 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2457 /* HWS page needs to be set less than what we
2458 * will inject to ring
2460 ret
= i915_gem_init_seqno(dev
, seqno
- 1);
2464 /* Carefully set the last_seqno value so that wrap
2465 * detection still works
2467 dev_priv
->next_seqno
= seqno
;
2468 dev_priv
->last_seqno
= seqno
- 1;
2469 if (dev_priv
->last_seqno
== 0)
2470 dev_priv
->last_seqno
--;
2476 i915_gem_get_seqno(struct drm_device
*dev
, u32
*seqno
)
2478 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2480 /* reserve 0 for non-seqno */
2481 if (dev_priv
->next_seqno
== 0) {
2482 int ret
= i915_gem_init_seqno(dev
, 0);
2486 dev_priv
->next_seqno
= 1;
2489 *seqno
= dev_priv
->last_seqno
= dev_priv
->next_seqno
++;
2494 * NB: This function is not allowed to fail. Doing so would mean the the
2495 * request is not being tracked for completion but the work itself is
2496 * going to happen on the hardware. This would be a Bad Thing(tm).
2498 void __i915_add_request(struct drm_i915_gem_request
*request
,
2499 struct drm_i915_gem_object
*obj
,
2502 struct intel_engine_cs
*ring
;
2503 struct drm_i915_private
*dev_priv
;
2504 struct intel_ringbuffer
*ringbuf
;
2508 if (WARN_ON(request
== NULL
))
2511 ring
= request
->ring
;
2512 dev_priv
= ring
->dev
->dev_private
;
2513 ringbuf
= request
->ringbuf
;
2516 * To ensure that this call will not fail, space for its emissions
2517 * should already have been reserved in the ring buffer. Let the ring
2518 * know that it is time to use that space up.
2520 intel_ring_reserved_space_use(ringbuf
);
2522 request_start
= intel_ring_get_tail(ringbuf
);
2524 * Emit any outstanding flushes - execbuf can fail to emit the flush
2525 * after having emitted the batchbuffer command. Hence we need to fix
2526 * things up similar to emitting the lazy request. The difference here
2527 * is that the flush _must_ happen before the next request, no matter
2531 if (i915
.enable_execlists
)
2532 ret
= logical_ring_flush_all_caches(request
);
2534 ret
= intel_ring_flush_all_caches(request
);
2535 /* Not allowed to fail! */
2536 WARN(ret
, "*_ring_flush_all_caches failed: %d!\n", ret
);
2539 /* Record the position of the start of the request so that
2540 * should we detect the updated seqno part-way through the
2541 * GPU processing the request, we never over-estimate the
2542 * position of the head.
2544 request
->postfix
= intel_ring_get_tail(ringbuf
);
2546 if (i915
.enable_execlists
)
2547 ret
= ring
->emit_request(request
);
2549 ret
= ring
->add_request(request
);
2551 request
->tail
= intel_ring_get_tail(ringbuf
);
2553 /* Not allowed to fail! */
2554 WARN(ret
, "emit|add_request failed: %d!\n", ret
);
2556 request
->head
= request_start
;
2558 /* Whilst this request exists, batch_obj will be on the
2559 * active_list, and so will hold the active reference. Only when this
2560 * request is retired will the the batch_obj be moved onto the
2561 * inactive_list and lose its active reference. Hence we do not need
2562 * to explicitly hold another reference here.
2564 request
->batch_obj
= obj
;
2566 request
->emitted_jiffies
= jiffies
;
2567 list_add_tail(&request
->list
, &ring
->request_list
);
2569 trace_i915_gem_request_add(request
);
2571 i915_queue_hangcheck(ring
->dev
);
2573 queue_delayed_work(dev_priv
->wq
,
2574 &dev_priv
->mm
.retire_work
,
2575 round_jiffies_up_relative(HZ
));
2576 intel_mark_busy(dev_priv
->dev
);
2578 /* Sanity check that the reserved size was large enough. */
2579 intel_ring_reserved_space_end(ringbuf
);
2582 static bool i915_context_is_banned(struct drm_i915_private
*dev_priv
,
2583 const struct intel_context
*ctx
)
2585 unsigned long elapsed
;
2587 elapsed
= get_seconds() - ctx
->hang_stats
.guilty_ts
;
2589 if (ctx
->hang_stats
.banned
)
2592 if (ctx
->hang_stats
.ban_period_seconds
&&
2593 elapsed
<= ctx
->hang_stats
.ban_period_seconds
) {
2594 if (!i915_gem_context_is_default(ctx
)) {
2595 DRM_DEBUG("context hanging too fast, banning!\n");
2597 } else if (i915_stop_ring_allow_ban(dev_priv
)) {
2598 if (i915_stop_ring_allow_warn(dev_priv
))
2599 DRM_ERROR("gpu hanging too fast, banning!\n");
2607 static void i915_set_reset_status(struct drm_i915_private
*dev_priv
,
2608 struct intel_context
*ctx
,
2611 struct i915_ctx_hang_stats
*hs
;
2616 hs
= &ctx
->hang_stats
;
2619 hs
->banned
= i915_context_is_banned(dev_priv
, ctx
);
2621 hs
->guilty_ts
= get_seconds();
2623 hs
->batch_pending
++;
2627 void i915_gem_request_free(struct kref
*req_ref
)
2629 struct drm_i915_gem_request
*req
= container_of(req_ref
,
2631 struct intel_context
*ctx
= req
->ctx
;
2634 i915_gem_request_remove_from_client(req
);
2637 if (i915
.enable_execlists
) {
2638 struct intel_engine_cs
*ring
= req
->ring
;
2640 if (ctx
!= ring
->default_context
)
2641 intel_lr_context_unpin(ring
, ctx
);
2644 i915_gem_context_unreference(ctx
);
2647 kmem_cache_free(req
->i915
->requests
, req
);
2650 int i915_gem_request_alloc(struct intel_engine_cs
*ring
,
2651 struct intel_context
*ctx
,
2652 struct drm_i915_gem_request
**req_out
)
2654 struct drm_i915_private
*dev_priv
= to_i915(ring
->dev
);
2655 struct drm_i915_gem_request
*req
;
2663 req
= kmem_cache_zalloc(dev_priv
->requests
, GFP_KERNEL
);
2667 ret
= i915_gem_get_seqno(ring
->dev
, &req
->seqno
);
2671 kref_init(&req
->ref
);
2672 req
->i915
= dev_priv
;
2675 i915_gem_context_reference(req
->ctx
);
2677 if (i915
.enable_execlists
)
2678 ret
= intel_logical_ring_alloc_request_extras(req
);
2680 ret
= intel_ring_alloc_request_extras(req
);
2682 i915_gem_context_unreference(req
->ctx
);
2687 * Reserve space in the ring buffer for all the commands required to
2688 * eventually emit this request. This is to guarantee that the
2689 * i915_add_request() call can't fail. Note that the reserve may need
2690 * to be redone if the request is not actually submitted straight
2691 * away, e.g. because a GPU scheduler has deferred it.
2693 if (i915
.enable_execlists
)
2694 ret
= intel_logical_ring_reserve_space(req
);
2696 ret
= intel_ring_reserve_space(req
);
2699 * At this point, the request is fully allocated even if not
2700 * fully prepared. Thus it can be cleaned up using the proper
2703 i915_gem_request_cancel(req
);
2711 kmem_cache_free(dev_priv
->requests
, req
);
2715 void i915_gem_request_cancel(struct drm_i915_gem_request
*req
)
2717 intel_ring_reserved_space_cancel(req
->ringbuf
);
2719 i915_gem_request_unreference(req
);
2722 struct drm_i915_gem_request
*
2723 i915_gem_find_active_request(struct intel_engine_cs
*ring
)
2725 struct drm_i915_gem_request
*request
;
2727 list_for_each_entry(request
, &ring
->request_list
, list
) {
2728 if (i915_gem_request_completed(request
, false))
2737 static void i915_gem_reset_ring_status(struct drm_i915_private
*dev_priv
,
2738 struct intel_engine_cs
*ring
)
2740 struct drm_i915_gem_request
*request
;
2743 request
= i915_gem_find_active_request(ring
);
2745 if (request
== NULL
)
2748 ring_hung
= ring
->hangcheck
.score
>= HANGCHECK_SCORE_RING_HUNG
;
2750 i915_set_reset_status(dev_priv
, request
->ctx
, ring_hung
);
2752 list_for_each_entry_continue(request
, &ring
->request_list
, list
)
2753 i915_set_reset_status(dev_priv
, request
->ctx
, false);
2756 static void i915_gem_reset_ring_cleanup(struct drm_i915_private
*dev_priv
,
2757 struct intel_engine_cs
*ring
)
2759 while (!list_empty(&ring
->active_list
)) {
2760 struct drm_i915_gem_object
*obj
;
2762 obj
= list_first_entry(&ring
->active_list
,
2763 struct drm_i915_gem_object
,
2764 ring_list
[ring
->id
]);
2766 i915_gem_object_retire__read(obj
, ring
->id
);
2770 * Clear the execlists queue up before freeing the requests, as those
2771 * are the ones that keep the context and ringbuffer backing objects
2774 while (!list_empty(&ring
->execlist_queue
)) {
2775 struct drm_i915_gem_request
*submit_req
;
2777 submit_req
= list_first_entry(&ring
->execlist_queue
,
2778 struct drm_i915_gem_request
,
2780 list_del(&submit_req
->execlist_link
);
2782 if (submit_req
->ctx
!= ring
->default_context
)
2783 intel_lr_context_unpin(ring
, submit_req
->ctx
);
2785 i915_gem_request_unreference(submit_req
);
2789 * We must free the requests after all the corresponding objects have
2790 * been moved off active lists. Which is the same order as the normal
2791 * retire_requests function does. This is important if object hold
2792 * implicit references on things like e.g. ppgtt address spaces through
2795 while (!list_empty(&ring
->request_list
)) {
2796 struct drm_i915_gem_request
*request
;
2798 request
= list_first_entry(&ring
->request_list
,
2799 struct drm_i915_gem_request
,
2802 i915_gem_request_retire(request
);
2806 void i915_gem_restore_fences(struct drm_device
*dev
)
2808 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2811 for (i
= 0; i
< dev_priv
->num_fence_regs
; i
++) {
2812 struct drm_i915_fence_reg
*reg
= &dev_priv
->fence_regs
[i
];
2815 * Commit delayed tiling changes if we have an object still
2816 * attached to the fence, otherwise just clear the fence.
2819 i915_gem_object_update_fence(reg
->obj
, reg
,
2820 reg
->obj
->tiling_mode
);
2822 i915_gem_write_fence(dev
, i
, NULL
);
2827 void i915_gem_reset(struct drm_device
*dev
)
2829 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2830 struct intel_engine_cs
*ring
;
2834 * Before we free the objects from the requests, we need to inspect
2835 * them for finding the guilty party. As the requests only borrow
2836 * their reference to the objects, the inspection must be done first.
2838 for_each_ring(ring
, dev_priv
, i
)
2839 i915_gem_reset_ring_status(dev_priv
, ring
);
2841 for_each_ring(ring
, dev_priv
, i
)
2842 i915_gem_reset_ring_cleanup(dev_priv
, ring
);
2844 i915_gem_context_reset(dev
);
2846 i915_gem_restore_fences(dev
);
2848 WARN_ON(i915_verify_lists(dev
));
2852 * This function clears the request list as sequence numbers are passed.
2855 i915_gem_retire_requests_ring(struct intel_engine_cs
*ring
)
2857 WARN_ON(i915_verify_lists(ring
->dev
));
2859 /* Retire requests first as we use it above for the early return.
2860 * If we retire requests last, we may use a later seqno and so clear
2861 * the requests lists without clearing the active list, leading to
2864 while (!list_empty(&ring
->request_list
)) {
2865 struct drm_i915_gem_request
*request
;
2867 request
= list_first_entry(&ring
->request_list
,
2868 struct drm_i915_gem_request
,
2871 if (!i915_gem_request_completed(request
, true))
2874 i915_gem_request_retire(request
);
2877 /* Move any buffers on the active list that are no longer referenced
2878 * by the ringbuffer to the flushing/inactive lists as appropriate,
2879 * before we free the context associated with the requests.
2881 while (!list_empty(&ring
->active_list
)) {
2882 struct drm_i915_gem_object
*obj
;
2884 obj
= list_first_entry(&ring
->active_list
,
2885 struct drm_i915_gem_object
,
2886 ring_list
[ring
->id
]);
2888 if (!list_empty(&obj
->last_read_req
[ring
->id
]->list
))
2891 i915_gem_object_retire__read(obj
, ring
->id
);
2894 if (unlikely(ring
->trace_irq_req
&&
2895 i915_gem_request_completed(ring
->trace_irq_req
, true))) {
2896 ring
->irq_put(ring
);
2897 i915_gem_request_assign(&ring
->trace_irq_req
, NULL
);
2900 WARN_ON(i915_verify_lists(ring
->dev
));
2904 i915_gem_retire_requests(struct drm_device
*dev
)
2906 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2907 struct intel_engine_cs
*ring
;
2911 for_each_ring(ring
, dev_priv
, i
) {
2912 i915_gem_retire_requests_ring(ring
);
2913 idle
&= list_empty(&ring
->request_list
);
2914 if (i915
.enable_execlists
) {
2915 unsigned long flags
;
2917 spin_lock_irqsave(&ring
->execlist_lock
, flags
);
2918 idle
&= list_empty(&ring
->execlist_queue
);
2919 spin_unlock_irqrestore(&ring
->execlist_lock
, flags
);
2921 intel_execlists_retire_requests(ring
);
2926 mod_delayed_work(dev_priv
->wq
,
2927 &dev_priv
->mm
.idle_work
,
2928 msecs_to_jiffies(100));
2934 i915_gem_retire_work_handler(struct work_struct
*work
)
2936 struct drm_i915_private
*dev_priv
=
2937 container_of(work
, typeof(*dev_priv
), mm
.retire_work
.work
);
2938 struct drm_device
*dev
= dev_priv
->dev
;
2941 /* Come back later if the device is busy... */
2943 if (mutex_trylock(&dev
->struct_mutex
)) {
2944 idle
= i915_gem_retire_requests(dev
);
2945 mutex_unlock(&dev
->struct_mutex
);
2948 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
,
2949 round_jiffies_up_relative(HZ
));
2953 i915_gem_idle_work_handler(struct work_struct
*work
)
2955 struct drm_i915_private
*dev_priv
=
2956 container_of(work
, typeof(*dev_priv
), mm
.idle_work
.work
);
2957 struct drm_device
*dev
= dev_priv
->dev
;
2958 struct intel_engine_cs
*ring
;
2961 for_each_ring(ring
, dev_priv
, i
)
2962 if (!list_empty(&ring
->request_list
))
2965 intel_mark_idle(dev
);
2967 if (mutex_trylock(&dev
->struct_mutex
)) {
2968 struct intel_engine_cs
*ring
;
2971 for_each_ring(ring
, dev_priv
, i
)
2972 i915_gem_batch_pool_fini(&ring
->batch_pool
);
2974 mutex_unlock(&dev
->struct_mutex
);
2979 * Ensures that an object will eventually get non-busy by flushing any required
2980 * write domains, emitting any outstanding lazy request and retiring and
2981 * completed requests.
2984 i915_gem_object_flush_active(struct drm_i915_gem_object
*obj
)
2991 for (i
= 0; i
< I915_NUM_RINGS
; i
++) {
2992 struct drm_i915_gem_request
*req
;
2994 req
= obj
->last_read_req
[i
];
2998 if (list_empty(&req
->list
))
3001 ret
= i915_gem_check_olr(req
);
3005 if (i915_gem_request_completed(req
, true)) {
3006 __i915_gem_request_retire__upto(req
);
3008 i915_gem_object_retire__read(obj
, i
);
3016 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
3017 * @DRM_IOCTL_ARGS: standard ioctl arguments
3019 * Returns 0 if successful, else an error is returned with the remaining time in
3020 * the timeout parameter.
3021 * -ETIME: object is still busy after timeout
3022 * -ERESTARTSYS: signal interrupted the wait
3023 * -ENONENT: object doesn't exist
3024 * Also possible, but rare:
3025 * -EAGAIN: GPU wedged
3027 * -ENODEV: Internal IRQ fail
3028 * -E?: The add request failed
3030 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
3031 * non-zero timeout parameter the wait ioctl will wait for the given number of
3032 * nanoseconds on an object becoming unbusy. Since the wait itself does so
3033 * without holding struct_mutex the object may become re-busied before this
3034 * function completes. A similar but shorter * race condition exists in the busy
3038 i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
, struct drm_file
*file
)
3040 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3041 struct drm_i915_gem_wait
*args
= data
;
3042 struct drm_i915_gem_object
*obj
;
3043 struct drm_i915_gem_request
*req
[I915_NUM_RINGS
];
3044 unsigned reset_counter
;
3048 if (args
->flags
!= 0)
3051 ret
= i915_mutex_lock_interruptible(dev
);
3055 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->bo_handle
));
3056 if (&obj
->base
== NULL
) {
3057 mutex_unlock(&dev
->struct_mutex
);
3061 /* Need to make sure the object gets inactive eventually. */
3062 ret
= i915_gem_object_flush_active(obj
);
3069 /* Do this after OLR check to make sure we make forward progress polling
3070 * on this IOCTL with a timeout == 0 (like busy ioctl)
3072 if (args
->timeout_ns
== 0) {
3077 drm_gem_object_unreference(&obj
->base
);
3078 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
3080 for (i
= 0; i
< I915_NUM_RINGS
; i
++) {
3081 if (obj
->last_read_req
[i
] == NULL
)
3084 req
[n
++] = i915_gem_request_reference(obj
->last_read_req
[i
]);
3087 mutex_unlock(&dev
->struct_mutex
);
3089 for (i
= 0; i
< n
; i
++) {
3091 ret
= __i915_wait_request(req
[i
], reset_counter
, true,
3092 args
->timeout_ns
> 0 ? &args
->timeout_ns
: NULL
,
3094 i915_gem_request_unreference__unlocked(req
[i
]);
3099 drm_gem_object_unreference(&obj
->base
);
3100 mutex_unlock(&dev
->struct_mutex
);
3105 __i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
3106 struct intel_engine_cs
*to
,
3107 struct drm_i915_gem_request
*from_req
,
3108 struct drm_i915_gem_request
**to_req
)
3110 struct intel_engine_cs
*from
;
3113 from
= i915_gem_request_get_ring(from_req
);
3117 if (i915_gem_request_completed(from_req
, true))
3120 ret
= i915_gem_check_olr(from_req
);
3124 if (!i915_semaphore_is_enabled(obj
->base
.dev
)) {
3125 struct drm_i915_private
*i915
= to_i915(obj
->base
.dev
);
3126 ret
= __i915_wait_request(from_req
,
3127 atomic_read(&i915
->gpu_error
.reset_counter
),
3128 i915
->mm
.interruptible
,
3130 &i915
->rps
.semaphores
);
3134 i915_gem_object_retire_request(obj
, from_req
);
3136 int idx
= intel_ring_sync_index(from
, to
);
3137 u32 seqno
= i915_gem_request_get_seqno(from_req
);
3141 if (seqno
<= from
->semaphore
.sync_seqno
[idx
])
3144 if (*to_req
== NULL
) {
3145 ret
= i915_gem_request_alloc(to
, to
->default_context
, to_req
);
3150 trace_i915_gem_ring_sync_to(*to_req
, from
, from_req
);
3151 ret
= to
->semaphore
.sync_to(*to_req
, from
, seqno
);
3155 /* We use last_read_req because sync_to()
3156 * might have just caused seqno wrap under
3159 from
->semaphore
.sync_seqno
[idx
] =
3160 i915_gem_request_get_seqno(obj
->last_read_req
[from
->id
]);
3167 * i915_gem_object_sync - sync an object to a ring.
3169 * @obj: object which may be in use on another ring.
3170 * @to: ring we wish to use the object on. May be NULL.
3171 * @to_req: request we wish to use the object for. See below.
3172 * This will be allocated and returned if a request is
3173 * required but not passed in.
3175 * This code is meant to abstract object synchronization with the GPU.
3176 * Calling with NULL implies synchronizing the object with the CPU
3177 * rather than a particular GPU ring. Conceptually we serialise writes
3178 * between engines inside the GPU. We only allow one engine to write
3179 * into a buffer at any time, but multiple readers. To ensure each has
3180 * a coherent view of memory, we must:
3182 * - If there is an outstanding write request to the object, the new
3183 * request must wait for it to complete (either CPU or in hw, requests
3184 * on the same ring will be naturally ordered).
3186 * - If we are a write request (pending_write_domain is set), the new
3187 * request must wait for outstanding read requests to complete.
3189 * For CPU synchronisation (NULL to) no request is required. For syncing with
3190 * rings to_req must be non-NULL. However, a request does not have to be
3191 * pre-allocated. If *to_req is NULL and sync commands will be emitted then a
3192 * request will be allocated automatically and returned through *to_req. Note
3193 * that it is not guaranteed that commands will be emitted (because the system
3194 * might already be idle). Hence there is no need to create a request that
3195 * might never have any work submitted. Note further that if a request is
3196 * returned in *to_req, it is the responsibility of the caller to submit
3197 * that request (after potentially adding more work to it).
3199 * Returns 0 if successful, else propagates up the lower layer error.
3202 i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
3203 struct intel_engine_cs
*to
,
3204 struct drm_i915_gem_request
**to_req
)
3206 const bool readonly
= obj
->base
.pending_write_domain
== 0;
3207 struct drm_i915_gem_request
*req
[I915_NUM_RINGS
];
3214 return i915_gem_object_wait_rendering(obj
, readonly
);
3218 if (obj
->last_write_req
)
3219 req
[n
++] = obj
->last_write_req
;
3221 for (i
= 0; i
< I915_NUM_RINGS
; i
++)
3222 if (obj
->last_read_req
[i
])
3223 req
[n
++] = obj
->last_read_req
[i
];
3225 for (i
= 0; i
< n
; i
++) {
3226 ret
= __i915_gem_object_sync(obj
, to
, req
[i
], to_req
);
3234 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object
*obj
)
3236 u32 old_write_domain
, old_read_domains
;
3238 /* Force a pagefault for domain tracking on next user access */
3239 i915_gem_release_mmap(obj
);
3241 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
) == 0)
3244 /* Wait for any direct GTT access to complete */
3247 old_read_domains
= obj
->base
.read_domains
;
3248 old_write_domain
= obj
->base
.write_domain
;
3250 obj
->base
.read_domains
&= ~I915_GEM_DOMAIN_GTT
;
3251 obj
->base
.write_domain
&= ~I915_GEM_DOMAIN_GTT
;
3253 trace_i915_gem_object_change_domain(obj
,
3258 int i915_vma_unbind(struct i915_vma
*vma
)
3260 struct drm_i915_gem_object
*obj
= vma
->obj
;
3261 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
3264 if (list_empty(&vma
->vma_link
))
3267 if (!drm_mm_node_allocated(&vma
->node
)) {
3268 i915_gem_vma_destroy(vma
);
3275 BUG_ON(obj
->pages
== NULL
);
3277 ret
= i915_gem_object_wait_rendering(obj
, false);
3280 /* Continue on if we fail due to EIO, the GPU is hung so we
3281 * should be safe and we need to cleanup or else we might
3282 * cause memory corruption through use-after-free.
3285 if (i915_is_ggtt(vma
->vm
) &&
3286 vma
->ggtt_view
.type
== I915_GGTT_VIEW_NORMAL
) {
3287 i915_gem_object_finish_gtt(obj
);
3289 /* release the fence reg _after_ flushing */
3290 ret
= i915_gem_object_put_fence(obj
);
3295 trace_i915_vma_unbind(vma
);
3297 vma
->vm
->unbind_vma(vma
);
3300 list_del_init(&vma
->mm_list
);
3301 if (i915_is_ggtt(vma
->vm
)) {
3302 if (vma
->ggtt_view
.type
== I915_GGTT_VIEW_NORMAL
) {
3303 obj
->map_and_fenceable
= false;
3304 } else if (vma
->ggtt_view
.pages
) {
3305 sg_free_table(vma
->ggtt_view
.pages
);
3306 kfree(vma
->ggtt_view
.pages
);
3307 vma
->ggtt_view
.pages
= NULL
;
3311 drm_mm_remove_node(&vma
->node
);
3312 i915_gem_vma_destroy(vma
);
3314 /* Since the unbound list is global, only move to that list if
3315 * no more VMAs exist. */
3316 if (list_empty(&obj
->vma_list
)) {
3317 i915_gem_gtt_finish_object(obj
);
3318 list_move_tail(&obj
->global_list
, &dev_priv
->mm
.unbound_list
);
3321 /* And finally now the object is completely decoupled from this vma,
3322 * we can drop its hold on the backing storage and allow it to be
3323 * reaped by the shrinker.
3325 i915_gem_object_unpin_pages(obj
);
3330 int i915_gpu_idle(struct drm_device
*dev
)
3332 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3333 struct intel_engine_cs
*ring
;
3336 /* Flush everything onto the inactive list. */
3337 for_each_ring(ring
, dev_priv
, i
) {
3338 if (!i915
.enable_execlists
) {
3339 struct drm_i915_gem_request
*req
;
3341 ret
= i915_gem_request_alloc(ring
, ring
->default_context
, &req
);
3345 ret
= i915_switch_context(req
);
3347 i915_gem_request_cancel(req
);
3351 i915_add_request_no_flush(req
);
3354 ret
= intel_ring_idle(ring
);
3359 WARN_ON(i915_verify_lists(dev
));
3363 static void i965_write_fence_reg(struct drm_device
*dev
, int reg
,
3364 struct drm_i915_gem_object
*obj
)
3366 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3368 int fence_pitch_shift
;
3370 if (INTEL_INFO(dev
)->gen
>= 6) {
3371 fence_reg
= FENCE_REG_SANDYBRIDGE_0
;
3372 fence_pitch_shift
= SANDYBRIDGE_FENCE_PITCH_SHIFT
;
3374 fence_reg
= FENCE_REG_965_0
;
3375 fence_pitch_shift
= I965_FENCE_PITCH_SHIFT
;
3378 fence_reg
+= reg
* 8;
3380 /* To w/a incoherency with non-atomic 64-bit register updates,
3381 * we split the 64-bit update into two 32-bit writes. In order
3382 * for a partial fence not to be evaluated between writes, we
3383 * precede the update with write to turn off the fence register,
3384 * and only enable the fence as the last step.
3386 * For extra levels of paranoia, we make sure each step lands
3387 * before applying the next step.
3389 I915_WRITE(fence_reg
, 0);
3390 POSTING_READ(fence_reg
);
3393 u32 size
= i915_gem_obj_ggtt_size(obj
);
3396 /* Adjust fence size to match tiled area */
3397 if (obj
->tiling_mode
!= I915_TILING_NONE
) {
3398 uint32_t row_size
= obj
->stride
*
3399 (obj
->tiling_mode
== I915_TILING_Y
? 32 : 8);
3400 size
= (size
/ row_size
) * row_size
;
3403 val
= (uint64_t)((i915_gem_obj_ggtt_offset(obj
) + size
- 4096) &
3405 val
|= i915_gem_obj_ggtt_offset(obj
) & 0xfffff000;
3406 val
|= (uint64_t)((obj
->stride
/ 128) - 1) << fence_pitch_shift
;
3407 if (obj
->tiling_mode
== I915_TILING_Y
)
3408 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
3409 val
|= I965_FENCE_REG_VALID
;
3411 I915_WRITE(fence_reg
+ 4, val
>> 32);
3412 POSTING_READ(fence_reg
+ 4);
3414 I915_WRITE(fence_reg
+ 0, val
);
3415 POSTING_READ(fence_reg
);
3417 I915_WRITE(fence_reg
+ 4, 0);
3418 POSTING_READ(fence_reg
+ 4);
3422 static void i915_write_fence_reg(struct drm_device
*dev
, int reg
,
3423 struct drm_i915_gem_object
*obj
)
3425 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3429 u32 size
= i915_gem_obj_ggtt_size(obj
);
3433 WARN((i915_gem_obj_ggtt_offset(obj
) & ~I915_FENCE_START_MASK
) ||
3434 (size
& -size
) != size
||
3435 (i915_gem_obj_ggtt_offset(obj
) & (size
- 1)),
3436 "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
3437 i915_gem_obj_ggtt_offset(obj
), obj
->map_and_fenceable
, size
);
3439 if (obj
->tiling_mode
== I915_TILING_Y
&& HAS_128_BYTE_Y_TILING(dev
))
3444 /* Note: pitch better be a power of two tile widths */
3445 pitch_val
= obj
->stride
/ tile_width
;
3446 pitch_val
= ffs(pitch_val
) - 1;
3448 val
= i915_gem_obj_ggtt_offset(obj
);
3449 if (obj
->tiling_mode
== I915_TILING_Y
)
3450 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
3451 val
|= I915_FENCE_SIZE_BITS(size
);
3452 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
3453 val
|= I830_FENCE_REG_VALID
;
3458 reg
= FENCE_REG_830_0
+ reg
* 4;
3460 reg
= FENCE_REG_945_8
+ (reg
- 8) * 4;
3462 I915_WRITE(reg
, val
);
3466 static void i830_write_fence_reg(struct drm_device
*dev
, int reg
,
3467 struct drm_i915_gem_object
*obj
)
3469 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3473 u32 size
= i915_gem_obj_ggtt_size(obj
);
3476 WARN((i915_gem_obj_ggtt_offset(obj
) & ~I830_FENCE_START_MASK
) ||
3477 (size
& -size
) != size
||
3478 (i915_gem_obj_ggtt_offset(obj
) & (size
- 1)),
3479 "object 0x%08lx not 512K or pot-size 0x%08x aligned\n",
3480 i915_gem_obj_ggtt_offset(obj
), size
);
3482 pitch_val
= obj
->stride
/ 128;
3483 pitch_val
= ffs(pitch_val
) - 1;
3485 val
= i915_gem_obj_ggtt_offset(obj
);
3486 if (obj
->tiling_mode
== I915_TILING_Y
)
3487 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
3488 val
|= I830_FENCE_SIZE_BITS(size
);
3489 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
3490 val
|= I830_FENCE_REG_VALID
;
3494 I915_WRITE(FENCE_REG_830_0
+ reg
* 4, val
);
3495 POSTING_READ(FENCE_REG_830_0
+ reg
* 4);
3498 inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object
*obj
)
3500 return obj
&& obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
;
3503 static void i915_gem_write_fence(struct drm_device
*dev
, int reg
,
3504 struct drm_i915_gem_object
*obj
)
3506 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3508 /* Ensure that all CPU reads are completed before installing a fence
3509 * and all writes before removing the fence.
3511 if (i915_gem_object_needs_mb(dev_priv
->fence_regs
[reg
].obj
))
3514 WARN(obj
&& (!obj
->stride
|| !obj
->tiling_mode
),
3515 "bogus fence setup with stride: 0x%x, tiling mode: %i\n",
3516 obj
->stride
, obj
->tiling_mode
);
3519 i830_write_fence_reg(dev
, reg
, obj
);
3520 else if (IS_GEN3(dev
))
3521 i915_write_fence_reg(dev
, reg
, obj
);
3522 else if (INTEL_INFO(dev
)->gen
>= 4)
3523 i965_write_fence_reg(dev
, reg
, obj
);
3525 /* And similarly be paranoid that no direct access to this region
3526 * is reordered to before the fence is installed.
3528 if (i915_gem_object_needs_mb(obj
))
3532 static inline int fence_number(struct drm_i915_private
*dev_priv
,
3533 struct drm_i915_fence_reg
*fence
)
3535 return fence
- dev_priv
->fence_regs
;
3538 static void i915_gem_object_update_fence(struct drm_i915_gem_object
*obj
,
3539 struct drm_i915_fence_reg
*fence
,
3542 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
3543 int reg
= fence_number(dev_priv
, fence
);
3545 i915_gem_write_fence(obj
->base
.dev
, reg
, enable
? obj
: NULL
);
3548 obj
->fence_reg
= reg
;
3550 list_move_tail(&fence
->lru_list
, &dev_priv
->mm
.fence_list
);
3552 obj
->fence_reg
= I915_FENCE_REG_NONE
;
3554 list_del_init(&fence
->lru_list
);
3556 obj
->fence_dirty
= false;
3560 i915_gem_object_wait_fence(struct drm_i915_gem_object
*obj
)
3562 if (obj
->last_fenced_req
) {
3563 int ret
= i915_wait_request(obj
->last_fenced_req
);
3567 i915_gem_request_assign(&obj
->last_fenced_req
, NULL
);
3574 i915_gem_object_put_fence(struct drm_i915_gem_object
*obj
)
3576 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
3577 struct drm_i915_fence_reg
*fence
;
3580 ret
= i915_gem_object_wait_fence(obj
);
3584 if (obj
->fence_reg
== I915_FENCE_REG_NONE
)
3587 fence
= &dev_priv
->fence_regs
[obj
->fence_reg
];
3589 if (WARN_ON(fence
->pin_count
))
3592 i915_gem_object_fence_lost(obj
);
3593 i915_gem_object_update_fence(obj
, fence
, false);
3598 static struct drm_i915_fence_reg
*
3599 i915_find_fence_reg(struct drm_device
*dev
)
3601 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3602 struct drm_i915_fence_reg
*reg
, *avail
;
3605 /* First try to find a free reg */
3607 for (i
= dev_priv
->fence_reg_start
; i
< dev_priv
->num_fence_regs
; i
++) {
3608 reg
= &dev_priv
->fence_regs
[i
];
3612 if (!reg
->pin_count
)
3619 /* None available, try to steal one or wait for a user to finish */
3620 list_for_each_entry(reg
, &dev_priv
->mm
.fence_list
, lru_list
) {
3628 /* Wait for completion of pending flips which consume fences */
3629 if (intel_has_pending_fb_unpin(dev
))
3630 return ERR_PTR(-EAGAIN
);
3632 return ERR_PTR(-EDEADLK
);
3636 * i915_gem_object_get_fence - set up fencing for an object
3637 * @obj: object to map through a fence reg
3639 * When mapping objects through the GTT, userspace wants to be able to write
3640 * to them without having to worry about swizzling if the object is tiled.
3641 * This function walks the fence regs looking for a free one for @obj,
3642 * stealing one if it can't find any.
3644 * It then sets up the reg based on the object's properties: address, pitch
3645 * and tiling format.
3647 * For an untiled surface, this removes any existing fence.
3650 i915_gem_object_get_fence(struct drm_i915_gem_object
*obj
)
3652 struct drm_device
*dev
= obj
->base
.dev
;
3653 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3654 bool enable
= obj
->tiling_mode
!= I915_TILING_NONE
;
3655 struct drm_i915_fence_reg
*reg
;
3658 /* Have we updated the tiling parameters upon the object and so
3659 * will need to serialise the write to the associated fence register?
3661 if (obj
->fence_dirty
) {
3662 ret
= i915_gem_object_wait_fence(obj
);
3667 /* Just update our place in the LRU if our fence is getting reused. */
3668 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
3669 reg
= &dev_priv
->fence_regs
[obj
->fence_reg
];
3670 if (!obj
->fence_dirty
) {
3671 list_move_tail(®
->lru_list
,
3672 &dev_priv
->mm
.fence_list
);
3675 } else if (enable
) {
3676 if (WARN_ON(!obj
->map_and_fenceable
))
3679 reg
= i915_find_fence_reg(dev
);
3681 return PTR_ERR(reg
);
3684 struct drm_i915_gem_object
*old
= reg
->obj
;
3686 ret
= i915_gem_object_wait_fence(old
);
3690 i915_gem_object_fence_lost(old
);
3695 i915_gem_object_update_fence(obj
, reg
, enable
);
3700 static bool i915_gem_valid_gtt_space(struct i915_vma
*vma
,
3701 unsigned long cache_level
)
3703 struct drm_mm_node
*gtt_space
= &vma
->node
;
3704 struct drm_mm_node
*other
;
3707 * On some machines we have to be careful when putting differing types
3708 * of snoopable memory together to avoid the prefetcher crossing memory
3709 * domains and dying. During vm initialisation, we decide whether or not
3710 * these constraints apply and set the drm_mm.color_adjust
3713 if (vma
->vm
->mm
.color_adjust
== NULL
)
3716 if (!drm_mm_node_allocated(gtt_space
))
3719 if (list_empty(>t_space
->node_list
))
3722 other
= list_entry(gtt_space
->node_list
.prev
, struct drm_mm_node
, node_list
);
3723 if (other
->allocated
&& !other
->hole_follows
&& other
->color
!= cache_level
)
3726 other
= list_entry(gtt_space
->node_list
.next
, struct drm_mm_node
, node_list
);
3727 if (other
->allocated
&& !gtt_space
->hole_follows
&& other
->color
!= cache_level
)
3734 * Finds free space in the GTT aperture and binds the object or a view of it
3737 static struct i915_vma
*
3738 i915_gem_object_bind_to_vm(struct drm_i915_gem_object
*obj
,
3739 struct i915_address_space
*vm
,
3740 const struct i915_ggtt_view
*ggtt_view
,
3744 struct drm_device
*dev
= obj
->base
.dev
;
3745 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3746 u32 size
, fence_size
, fence_alignment
, unfenced_alignment
;
3747 unsigned long start
=
3748 flags
& PIN_OFFSET_BIAS
? flags
& PIN_OFFSET_MASK
: 0;
3750 flags
& PIN_MAPPABLE
? dev_priv
->gtt
.mappable_end
: vm
->total
;
3751 struct i915_vma
*vma
;
3754 if (i915_is_ggtt(vm
)) {
3757 if (WARN_ON(!ggtt_view
))
3758 return ERR_PTR(-EINVAL
);
3760 view_size
= i915_ggtt_view_size(obj
, ggtt_view
);
3762 fence_size
= i915_gem_get_gtt_size(dev
,
3765 fence_alignment
= i915_gem_get_gtt_alignment(dev
,
3769 unfenced_alignment
= i915_gem_get_gtt_alignment(dev
,
3773 size
= flags
& PIN_MAPPABLE
? fence_size
: view_size
;
3775 fence_size
= i915_gem_get_gtt_size(dev
,
3778 fence_alignment
= i915_gem_get_gtt_alignment(dev
,
3782 unfenced_alignment
=
3783 i915_gem_get_gtt_alignment(dev
,
3787 size
= flags
& PIN_MAPPABLE
? fence_size
: obj
->base
.size
;
3791 alignment
= flags
& PIN_MAPPABLE
? fence_alignment
:
3793 if (flags
& PIN_MAPPABLE
&& alignment
& (fence_alignment
- 1)) {
3794 DRM_DEBUG("Invalid object (view type=%u) alignment requested %u\n",
3795 ggtt_view
? ggtt_view
->type
: 0,
3797 return ERR_PTR(-EINVAL
);
3800 /* If binding the object/GGTT view requires more space than the entire
3801 * aperture has, reject it early before evicting everything in a vain
3802 * attempt to find space.
3805 DRM_DEBUG("Attempting to bind an object (view type=%u) larger than the aperture: size=%u > %s aperture=%lu\n",
3806 ggtt_view
? ggtt_view
->type
: 0,
3808 flags
& PIN_MAPPABLE
? "mappable" : "total",
3810 return ERR_PTR(-E2BIG
);
3813 ret
= i915_gem_object_get_pages(obj
);
3815 return ERR_PTR(ret
);
3817 i915_gem_object_pin_pages(obj
);
3819 vma
= ggtt_view
? i915_gem_obj_lookup_or_create_ggtt_vma(obj
, ggtt_view
) :
3820 i915_gem_obj_lookup_or_create_vma(obj
, vm
);
3826 ret
= drm_mm_insert_node_in_range_generic(&vm
->mm
, &vma
->node
,
3830 DRM_MM_SEARCH_DEFAULT
,
3831 DRM_MM_CREATE_DEFAULT
);
3833 ret
= i915_gem_evict_something(dev
, vm
, size
, alignment
,
3842 if (WARN_ON(!i915_gem_valid_gtt_space(vma
, obj
->cache_level
))) {
3844 goto err_remove_node
;
3847 ret
= i915_gem_gtt_prepare_object(obj
);
3849 goto err_remove_node
;
3851 trace_i915_vma_bind(vma
, flags
);
3852 ret
= i915_vma_bind(vma
, obj
->cache_level
, flags
);
3854 goto err_finish_gtt
;
3856 list_move_tail(&obj
->global_list
, &dev_priv
->mm
.bound_list
);
3857 list_add_tail(&vma
->mm_list
, &vm
->inactive_list
);
3862 i915_gem_gtt_finish_object(obj
);
3864 drm_mm_remove_node(&vma
->node
);
3866 i915_gem_vma_destroy(vma
);
3869 i915_gem_object_unpin_pages(obj
);
3874 i915_gem_clflush_object(struct drm_i915_gem_object
*obj
,
3877 /* If we don't have a page list set up, then we're not pinned
3878 * to GPU, and we can ignore the cache flush because it'll happen
3879 * again at bind time.
3881 if (obj
->pages
== NULL
)
3885 * Stolen memory is always coherent with the GPU as it is explicitly
3886 * marked as wc by the system, or the system is cache-coherent.
3888 if (obj
->stolen
|| obj
->phys_handle
)
3891 /* If the GPU is snooping the contents of the CPU cache,
3892 * we do not need to manually clear the CPU cache lines. However,
3893 * the caches are only snooped when the render cache is
3894 * flushed/invalidated. As we always have to emit invalidations
3895 * and flushes when moving into and out of the RENDER domain, correct
3896 * snooping behaviour occurs naturally as the result of our domain
3899 if (!force
&& cpu_cache_is_coherent(obj
->base
.dev
, obj
->cache_level
)) {
3900 obj
->cache_dirty
= true;
3904 trace_i915_gem_object_clflush(obj
);
3905 drm_clflush_sg(obj
->pages
);
3906 obj
->cache_dirty
= false;
3911 /** Flushes the GTT write domain for the object if it's dirty. */
3913 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
)
3915 uint32_t old_write_domain
;
3917 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_GTT
)
3920 /* No actual flushing is required for the GTT write domain. Writes
3921 * to it immediately go to main memory as far as we know, so there's
3922 * no chipset flush. It also doesn't land in render cache.
3924 * However, we do have to enforce the order so that all writes through
3925 * the GTT land before any writes to the device, such as updates to
3930 old_write_domain
= obj
->base
.write_domain
;
3931 obj
->base
.write_domain
= 0;
3933 intel_fb_obj_flush(obj
, false);
3935 trace_i915_gem_object_change_domain(obj
,
3936 obj
->base
.read_domains
,
3940 /** Flushes the CPU write domain for the object if it's dirty. */
3942 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
)
3944 uint32_t old_write_domain
;
3946 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
)
3949 if (i915_gem_clflush_object(obj
, obj
->pin_display
))
3950 i915_gem_chipset_flush(obj
->base
.dev
);
3952 old_write_domain
= obj
->base
.write_domain
;
3953 obj
->base
.write_domain
= 0;
3955 intel_fb_obj_flush(obj
, false);
3957 trace_i915_gem_object_change_domain(obj
,
3958 obj
->base
.read_domains
,
3963 * Moves a single object to the GTT read, and possibly write domain.
3965 * This function returns when the move is complete, including waiting on
3969 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
, bool write
)
3971 uint32_t old_write_domain
, old_read_domains
;
3972 struct i915_vma
*vma
;
3975 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_GTT
)
3978 ret
= i915_gem_object_wait_rendering(obj
, !write
);
3982 /* Flush and acquire obj->pages so that we are coherent through
3983 * direct access in memory with previous cached writes through
3984 * shmemfs and that our cache domain tracking remains valid.
3985 * For example, if the obj->filp was moved to swap without us
3986 * being notified and releasing the pages, we would mistakenly
3987 * continue to assume that the obj remained out of the CPU cached
3990 ret
= i915_gem_object_get_pages(obj
);
3994 i915_gem_object_flush_cpu_write_domain(obj
);
3996 /* Serialise direct access to this object with the barriers for
3997 * coherent writes from the GPU, by effectively invalidating the
3998 * GTT domain upon first access.
4000 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
) == 0)
4003 old_write_domain
= obj
->base
.write_domain
;
4004 old_read_domains
= obj
->base
.read_domains
;
4006 /* It should now be out of any other write domains, and we can update
4007 * the domain values for our changes.
4009 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
4010 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
4012 obj
->base
.read_domains
= I915_GEM_DOMAIN_GTT
;
4013 obj
->base
.write_domain
= I915_GEM_DOMAIN_GTT
;
4018 intel_fb_obj_invalidate(obj
, ORIGIN_GTT
);
4020 trace_i915_gem_object_change_domain(obj
,
4024 /* And bump the LRU for this access */
4025 vma
= i915_gem_obj_to_ggtt(obj
);
4026 if (vma
&& drm_mm_node_allocated(&vma
->node
) && !obj
->active
)
4027 list_move_tail(&vma
->mm_list
,
4028 &to_i915(obj
->base
.dev
)->gtt
.base
.inactive_list
);
4033 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
4034 enum i915_cache_level cache_level
)
4036 struct drm_device
*dev
= obj
->base
.dev
;
4037 struct i915_vma
*vma
, *next
;
4040 if (obj
->cache_level
== cache_level
)
4043 if (i915_gem_obj_is_pinned(obj
)) {
4044 DRM_DEBUG("can not change the cache level of pinned objects\n");
4048 list_for_each_entry_safe(vma
, next
, &obj
->vma_list
, vma_link
) {
4049 if (!i915_gem_valid_gtt_space(vma
, cache_level
)) {
4050 ret
= i915_vma_unbind(vma
);
4056 if (i915_gem_obj_bound_any(obj
)) {
4057 ret
= i915_gem_object_wait_rendering(obj
, false);
4061 i915_gem_object_finish_gtt(obj
);
4063 /* Before SandyBridge, you could not use tiling or fence
4064 * registers with snooped memory, so relinquish any fences
4065 * currently pointing to our region in the aperture.
4067 if (INTEL_INFO(dev
)->gen
< 6) {
4068 ret
= i915_gem_object_put_fence(obj
);
4073 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
4074 if (drm_mm_node_allocated(&vma
->node
)) {
4075 ret
= i915_vma_bind(vma
, cache_level
,
4082 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
4083 vma
->node
.color
= cache_level
;
4084 obj
->cache_level
= cache_level
;
4086 if (obj
->cache_dirty
&&
4087 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
&&
4088 cpu_write_needs_clflush(obj
)) {
4089 if (i915_gem_clflush_object(obj
, true))
4090 i915_gem_chipset_flush(obj
->base
.dev
);
4096 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
4097 struct drm_file
*file
)
4099 struct drm_i915_gem_caching
*args
= data
;
4100 struct drm_i915_gem_object
*obj
;
4102 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
4103 if (&obj
->base
== NULL
)
4106 switch (obj
->cache_level
) {
4107 case I915_CACHE_LLC
:
4108 case I915_CACHE_L3_LLC
:
4109 args
->caching
= I915_CACHING_CACHED
;
4113 args
->caching
= I915_CACHING_DISPLAY
;
4117 args
->caching
= I915_CACHING_NONE
;
4121 drm_gem_object_unreference_unlocked(&obj
->base
);
4125 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
4126 struct drm_file
*file
)
4128 struct drm_i915_gem_caching
*args
= data
;
4129 struct drm_i915_gem_object
*obj
;
4130 enum i915_cache_level level
;
4133 switch (args
->caching
) {
4134 case I915_CACHING_NONE
:
4135 level
= I915_CACHE_NONE
;
4137 case I915_CACHING_CACHED
:
4138 level
= I915_CACHE_LLC
;
4140 case I915_CACHING_DISPLAY
:
4141 level
= HAS_WT(dev
) ? I915_CACHE_WT
: I915_CACHE_NONE
;
4147 ret
= i915_mutex_lock_interruptible(dev
);
4151 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
4152 if (&obj
->base
== NULL
) {
4157 ret
= i915_gem_object_set_cache_level(obj
, level
);
4159 drm_gem_object_unreference(&obj
->base
);
4161 mutex_unlock(&dev
->struct_mutex
);
4166 * Prepare buffer for display plane (scanout, cursors, etc).
4167 * Can be called from an uninterruptible phase (modesetting) and allows
4168 * any flushes to be pipelined (for pageflips).
4171 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
4173 struct intel_engine_cs
*pipelined
,
4174 struct drm_i915_gem_request
**pipelined_request
,
4175 const struct i915_ggtt_view
*view
)
4177 u32 old_read_domains
, old_write_domain
;
4180 ret
= i915_gem_object_sync(obj
, pipelined
, pipelined_request
);
4184 /* Mark the pin_display early so that we account for the
4185 * display coherency whilst setting up the cache domains.
4189 /* The display engine is not coherent with the LLC cache on gen6. As
4190 * a result, we make sure that the pinning that is about to occur is
4191 * done with uncached PTEs. This is lowest common denominator for all
4194 * However for gen6+, we could do better by using the GFDT bit instead
4195 * of uncaching, which would allow us to flush all the LLC-cached data
4196 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
4198 ret
= i915_gem_object_set_cache_level(obj
,
4199 HAS_WT(obj
->base
.dev
) ? I915_CACHE_WT
: I915_CACHE_NONE
);
4201 goto err_unpin_display
;
4203 /* As the user may map the buffer once pinned in the display plane
4204 * (e.g. libkms for the bootup splash), we have to ensure that we
4205 * always use map_and_fenceable for all scanout buffers.
4207 ret
= i915_gem_object_ggtt_pin(obj
, view
, alignment
,
4208 view
->type
== I915_GGTT_VIEW_NORMAL
?
4211 goto err_unpin_display
;
4213 i915_gem_object_flush_cpu_write_domain(obj
);
4215 old_write_domain
= obj
->base
.write_domain
;
4216 old_read_domains
= obj
->base
.read_domains
;
4218 /* It should now be out of any other write domains, and we can update
4219 * the domain values for our changes.
4221 obj
->base
.write_domain
= 0;
4222 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
4224 trace_i915_gem_object_change_domain(obj
,
4236 i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object
*obj
,
4237 const struct i915_ggtt_view
*view
)
4239 if (WARN_ON(obj
->pin_display
== 0))
4242 i915_gem_object_ggtt_unpin_view(obj
, view
);
4248 * Moves a single object to the CPU read, and possibly write domain.
4250 * This function returns when the move is complete, including waiting on
4254 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
)
4256 uint32_t old_write_domain
, old_read_domains
;
4259 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_CPU
)
4262 ret
= i915_gem_object_wait_rendering(obj
, !write
);
4266 i915_gem_object_flush_gtt_write_domain(obj
);
4268 old_write_domain
= obj
->base
.write_domain
;
4269 old_read_domains
= obj
->base
.read_domains
;
4271 /* Flush the CPU cache if it's still invalid. */
4272 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) == 0) {
4273 i915_gem_clflush_object(obj
, false);
4275 obj
->base
.read_domains
|= I915_GEM_DOMAIN_CPU
;
4278 /* It should now be out of any other write domains, and we can update
4279 * the domain values for our changes.
4281 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
4283 /* If we're writing through the CPU, then the GPU read domains will
4284 * need to be invalidated at next use.
4287 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
4288 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
4292 intel_fb_obj_invalidate(obj
, ORIGIN_CPU
);
4294 trace_i915_gem_object_change_domain(obj
,
4301 /* Throttle our rendering by waiting until the ring has completed our requests
4302 * emitted over 20 msec ago.
4304 * Note that if we were to use the current jiffies each time around the loop,
4305 * we wouldn't escape the function with any frames outstanding if the time to
4306 * render a frame was over 20ms.
4308 * This should get us reasonable parallelism between CPU and GPU but also
4309 * relatively low latency when blocking on a particular request to finish.
4312 i915_gem_ring_throttle(struct drm_device
*dev
, struct drm_file
*file
)
4314 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4315 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
4316 unsigned long recent_enough
= jiffies
- DRM_I915_THROTTLE_JIFFIES
;
4317 struct drm_i915_gem_request
*request
, *target
= NULL
;
4318 unsigned reset_counter
;
4321 ret
= i915_gem_wait_for_error(&dev_priv
->gpu_error
);
4325 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, false);
4329 spin_lock(&file_priv
->mm
.lock
);
4330 list_for_each_entry(request
, &file_priv
->mm
.request_list
, client_list
) {
4331 if (time_after_eq(request
->emitted_jiffies
, recent_enough
))
4335 * Note that the request might not have been submitted yet.
4336 * In which case emitted_jiffies will be zero.
4338 if (!request
->emitted_jiffies
)
4343 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
4345 i915_gem_request_reference(target
);
4346 spin_unlock(&file_priv
->mm
.lock
);
4351 ret
= __i915_wait_request(target
, reset_counter
, true, NULL
, NULL
);
4353 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, 0);
4355 i915_gem_request_unreference__unlocked(target
);
4361 i915_vma_misplaced(struct i915_vma
*vma
, uint32_t alignment
, uint64_t flags
)
4363 struct drm_i915_gem_object
*obj
= vma
->obj
;
4366 vma
->node
.start
& (alignment
- 1))
4369 if (flags
& PIN_MAPPABLE
&& !obj
->map_and_fenceable
)
4372 if (flags
& PIN_OFFSET_BIAS
&&
4373 vma
->node
.start
< (flags
& PIN_OFFSET_MASK
))
4380 i915_gem_object_do_pin(struct drm_i915_gem_object
*obj
,
4381 struct i915_address_space
*vm
,
4382 const struct i915_ggtt_view
*ggtt_view
,
4386 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
4387 struct i915_vma
*vma
;
4391 if (WARN_ON(vm
== &dev_priv
->mm
.aliasing_ppgtt
->base
))
4394 if (WARN_ON(flags
& (PIN_GLOBAL
| PIN_MAPPABLE
) && !i915_is_ggtt(vm
)))
4397 if (WARN_ON((flags
& (PIN_MAPPABLE
| PIN_GLOBAL
)) == PIN_MAPPABLE
))
4400 if (WARN_ON(i915_is_ggtt(vm
) != !!ggtt_view
))
4403 vma
= ggtt_view
? i915_gem_obj_to_ggtt_view(obj
, ggtt_view
) :
4404 i915_gem_obj_to_vma(obj
, vm
);
4407 return PTR_ERR(vma
);
4410 if (WARN_ON(vma
->pin_count
== DRM_I915_GEM_OBJECT_MAX_PIN_COUNT
))
4413 if (i915_vma_misplaced(vma
, alignment
, flags
)) {
4414 unsigned long offset
;
4415 offset
= ggtt_view
? i915_gem_obj_ggtt_offset_view(obj
, ggtt_view
) :
4416 i915_gem_obj_offset(obj
, vm
);
4417 WARN(vma
->pin_count
,
4418 "bo is already pinned in %s with incorrect alignment:"
4419 " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d,"
4420 " obj->map_and_fenceable=%d\n",
4421 ggtt_view
? "ggtt" : "ppgtt",
4424 !!(flags
& PIN_MAPPABLE
),
4425 obj
->map_and_fenceable
);
4426 ret
= i915_vma_unbind(vma
);
4434 bound
= vma
? vma
->bound
: 0;
4435 if (vma
== NULL
|| !drm_mm_node_allocated(&vma
->node
)) {
4436 vma
= i915_gem_object_bind_to_vm(obj
, vm
, ggtt_view
, alignment
,
4439 return PTR_ERR(vma
);
4441 ret
= i915_vma_bind(vma
, obj
->cache_level
, flags
);
4446 if (ggtt_view
&& ggtt_view
->type
== I915_GGTT_VIEW_NORMAL
&&
4447 (bound
^ vma
->bound
) & GLOBAL_BIND
) {
4448 bool mappable
, fenceable
;
4449 u32 fence_size
, fence_alignment
;
4451 fence_size
= i915_gem_get_gtt_size(obj
->base
.dev
,
4454 fence_alignment
= i915_gem_get_gtt_alignment(obj
->base
.dev
,
4459 fenceable
= (vma
->node
.size
== fence_size
&&
4460 (vma
->node
.start
& (fence_alignment
- 1)) == 0);
4462 mappable
= (vma
->node
.start
+ fence_size
<=
4463 dev_priv
->gtt
.mappable_end
);
4465 obj
->map_and_fenceable
= mappable
&& fenceable
;
4467 WARN_ON(flags
& PIN_MAPPABLE
&& !obj
->map_and_fenceable
);
4475 i915_gem_object_pin(struct drm_i915_gem_object
*obj
,
4476 struct i915_address_space
*vm
,
4480 return i915_gem_object_do_pin(obj
, vm
,
4481 i915_is_ggtt(vm
) ? &i915_ggtt_view_normal
: NULL
,
4486 i915_gem_object_ggtt_pin(struct drm_i915_gem_object
*obj
,
4487 const struct i915_ggtt_view
*view
,
4491 if (WARN_ONCE(!view
, "no view specified"))
4494 return i915_gem_object_do_pin(obj
, i915_obj_to_ggtt(obj
), view
,
4495 alignment
, flags
| PIN_GLOBAL
);
4499 i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object
*obj
,
4500 const struct i915_ggtt_view
*view
)
4502 struct i915_vma
*vma
= i915_gem_obj_to_ggtt_view(obj
, view
);
4505 WARN_ON(vma
->pin_count
== 0);
4506 WARN_ON(!i915_gem_obj_ggtt_bound_view(obj
, view
));
4512 i915_gem_object_pin_fence(struct drm_i915_gem_object
*obj
)
4514 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
4515 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
4516 struct i915_vma
*ggtt_vma
= i915_gem_obj_to_ggtt(obj
);
4518 WARN_ON(!ggtt_vma
||
4519 dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
>
4520 ggtt_vma
->pin_count
);
4521 dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
++;
4528 i915_gem_object_unpin_fence(struct drm_i915_gem_object
*obj
)
4530 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
4531 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
4532 WARN_ON(dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
<= 0);
4533 dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
--;
4538 i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
4539 struct drm_file
*file
)
4541 struct drm_i915_gem_busy
*args
= data
;
4542 struct drm_i915_gem_object
*obj
;
4545 ret
= i915_mutex_lock_interruptible(dev
);
4549 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
4550 if (&obj
->base
== NULL
) {
4555 /* Count all active objects as busy, even if they are currently not used
4556 * by the gpu. Users of this interface expect objects to eventually
4557 * become non-busy without any further actions, therefore emit any
4558 * necessary flushes here.
4560 ret
= i915_gem_object_flush_active(obj
);
4564 BUILD_BUG_ON(I915_NUM_RINGS
> 16);
4565 args
->busy
= obj
->active
<< 16;
4566 if (obj
->last_write_req
)
4567 args
->busy
|= obj
->last_write_req
->ring
->id
;
4570 drm_gem_object_unreference(&obj
->base
);
4572 mutex_unlock(&dev
->struct_mutex
);
4577 i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
4578 struct drm_file
*file_priv
)
4580 return i915_gem_ring_throttle(dev
, file_priv
);
4584 i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
4585 struct drm_file
*file_priv
)
4587 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4588 struct drm_i915_gem_madvise
*args
= data
;
4589 struct drm_i915_gem_object
*obj
;
4592 switch (args
->madv
) {
4593 case I915_MADV_DONTNEED
:
4594 case I915_MADV_WILLNEED
:
4600 ret
= i915_mutex_lock_interruptible(dev
);
4604 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file_priv
, args
->handle
));
4605 if (&obj
->base
== NULL
) {
4610 if (i915_gem_obj_is_pinned(obj
)) {
4616 obj
->tiling_mode
!= I915_TILING_NONE
&&
4617 dev_priv
->quirks
& QUIRK_PIN_SWIZZLED_PAGES
) {
4618 if (obj
->madv
== I915_MADV_WILLNEED
)
4619 i915_gem_object_unpin_pages(obj
);
4620 if (args
->madv
== I915_MADV_WILLNEED
)
4621 i915_gem_object_pin_pages(obj
);
4624 if (obj
->madv
!= __I915_MADV_PURGED
)
4625 obj
->madv
= args
->madv
;
4627 /* if the object is no longer attached, discard its backing storage */
4628 if (obj
->madv
== I915_MADV_DONTNEED
&& obj
->pages
== NULL
)
4629 i915_gem_object_truncate(obj
);
4631 args
->retained
= obj
->madv
!= __I915_MADV_PURGED
;
4634 drm_gem_object_unreference(&obj
->base
);
4636 mutex_unlock(&dev
->struct_mutex
);
4640 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
4641 const struct drm_i915_gem_object_ops
*ops
)
4645 INIT_LIST_HEAD(&obj
->global_list
);
4646 for (i
= 0; i
< I915_NUM_RINGS
; i
++)
4647 INIT_LIST_HEAD(&obj
->ring_list
[i
]);
4648 INIT_LIST_HEAD(&obj
->obj_exec_link
);
4649 INIT_LIST_HEAD(&obj
->vma_list
);
4650 INIT_LIST_HEAD(&obj
->batch_pool_link
);
4654 obj
->fence_reg
= I915_FENCE_REG_NONE
;
4655 obj
->madv
= I915_MADV_WILLNEED
;
4657 i915_gem_info_add_obj(obj
->base
.dev
->dev_private
, obj
->base
.size
);
4660 static const struct drm_i915_gem_object_ops i915_gem_object_ops
= {
4661 .get_pages
= i915_gem_object_get_pages_gtt
,
4662 .put_pages
= i915_gem_object_put_pages_gtt
,
4665 struct drm_i915_gem_object
*i915_gem_alloc_object(struct drm_device
*dev
,
4668 struct drm_i915_gem_object
*obj
;
4669 struct address_space
*mapping
;
4672 obj
= i915_gem_object_alloc(dev
);
4676 if (drm_gem_object_init(dev
, &obj
->base
, size
) != 0) {
4677 i915_gem_object_free(obj
);
4681 mask
= GFP_HIGHUSER
| __GFP_RECLAIMABLE
;
4682 if (IS_CRESTLINE(dev
) || IS_BROADWATER(dev
)) {
4683 /* 965gm cannot relocate objects above 4GiB. */
4684 mask
&= ~__GFP_HIGHMEM
;
4685 mask
|= __GFP_DMA32
;
4688 mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
4689 mapping_set_gfp_mask(mapping
, mask
);
4691 i915_gem_object_init(obj
, &i915_gem_object_ops
);
4693 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
4694 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
4697 /* On some devices, we can have the GPU use the LLC (the CPU
4698 * cache) for about a 10% performance improvement
4699 * compared to uncached. Graphics requests other than
4700 * display scanout are coherent with the CPU in
4701 * accessing this cache. This means in this mode we
4702 * don't need to clflush on the CPU side, and on the
4703 * GPU side we only need to flush internal caches to
4704 * get data visible to the CPU.
4706 * However, we maintain the display planes as UC, and so
4707 * need to rebind when first used as such.
4709 obj
->cache_level
= I915_CACHE_LLC
;
4711 obj
->cache_level
= I915_CACHE_NONE
;
4713 trace_i915_gem_object_create(obj
);
4718 static bool discard_backing_storage(struct drm_i915_gem_object
*obj
)
4720 /* If we are the last user of the backing storage (be it shmemfs
4721 * pages or stolen etc), we know that the pages are going to be
4722 * immediately released. In this case, we can then skip copying
4723 * back the contents from the GPU.
4726 if (obj
->madv
!= I915_MADV_WILLNEED
)
4729 if (obj
->base
.filp
== NULL
)
4732 /* At first glance, this looks racy, but then again so would be
4733 * userspace racing mmap against close. However, the first external
4734 * reference to the filp can only be obtained through the
4735 * i915_gem_mmap_ioctl() which safeguards us against the user
4736 * acquiring such a reference whilst we are in the middle of
4737 * freeing the object.
4739 return atomic_long_read(&obj
->base
.filp
->f_count
) == 1;
4742 void i915_gem_free_object(struct drm_gem_object
*gem_obj
)
4744 struct drm_i915_gem_object
*obj
= to_intel_bo(gem_obj
);
4745 struct drm_device
*dev
= obj
->base
.dev
;
4746 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4747 struct i915_vma
*vma
, *next
;
4749 intel_runtime_pm_get(dev_priv
);
4751 trace_i915_gem_object_destroy(obj
);
4753 list_for_each_entry_safe(vma
, next
, &obj
->vma_list
, vma_link
) {
4757 ret
= i915_vma_unbind(vma
);
4758 if (WARN_ON(ret
== -ERESTARTSYS
)) {
4759 bool was_interruptible
;
4761 was_interruptible
= dev_priv
->mm
.interruptible
;
4762 dev_priv
->mm
.interruptible
= false;
4764 WARN_ON(i915_vma_unbind(vma
));
4766 dev_priv
->mm
.interruptible
= was_interruptible
;
4770 /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
4771 * before progressing. */
4773 i915_gem_object_unpin_pages(obj
);
4775 WARN_ON(obj
->frontbuffer_bits
);
4777 if (obj
->pages
&& obj
->madv
== I915_MADV_WILLNEED
&&
4778 dev_priv
->quirks
& QUIRK_PIN_SWIZZLED_PAGES
&&
4779 obj
->tiling_mode
!= I915_TILING_NONE
)
4780 i915_gem_object_unpin_pages(obj
);
4782 if (WARN_ON(obj
->pages_pin_count
))
4783 obj
->pages_pin_count
= 0;
4784 if (discard_backing_storage(obj
))
4785 obj
->madv
= I915_MADV_DONTNEED
;
4786 i915_gem_object_put_pages(obj
);
4787 i915_gem_object_free_mmap_offset(obj
);
4791 if (obj
->base
.import_attach
)
4792 drm_prime_gem_destroy(&obj
->base
, NULL
);
4794 if (obj
->ops
->release
)
4795 obj
->ops
->release(obj
);
4797 drm_gem_object_release(&obj
->base
);
4798 i915_gem_info_remove_obj(dev_priv
, obj
->base
.size
);
4801 i915_gem_object_free(obj
);
4803 intel_runtime_pm_put(dev_priv
);
4806 struct i915_vma
*i915_gem_obj_to_vma(struct drm_i915_gem_object
*obj
,
4807 struct i915_address_space
*vm
)
4809 struct i915_vma
*vma
;
4810 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
) {
4811 if (i915_is_ggtt(vma
->vm
) &&
4812 vma
->ggtt_view
.type
!= I915_GGTT_VIEW_NORMAL
)
4820 struct i915_vma
*i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object
*obj
,
4821 const struct i915_ggtt_view
*view
)
4823 struct i915_address_space
*ggtt
= i915_obj_to_ggtt(obj
);
4824 struct i915_vma
*vma
;
4826 if (WARN_ONCE(!view
, "no view specified"))
4827 return ERR_PTR(-EINVAL
);
4829 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
4830 if (vma
->vm
== ggtt
&&
4831 i915_ggtt_view_equal(&vma
->ggtt_view
, view
))
4836 void i915_gem_vma_destroy(struct i915_vma
*vma
)
4838 struct i915_address_space
*vm
= NULL
;
4839 WARN_ON(vma
->node
.allocated
);
4841 /* Keep the vma as a placeholder in the execbuffer reservation lists */
4842 if (!list_empty(&vma
->exec_list
))
4847 if (!i915_is_ggtt(vm
))
4848 i915_ppgtt_put(i915_vm_to_ppgtt(vm
));
4850 list_del(&vma
->vma_link
);
4852 kmem_cache_free(to_i915(vma
->obj
->base
.dev
)->vmas
, vma
);
4856 i915_gem_stop_ringbuffers(struct drm_device
*dev
)
4858 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4859 struct intel_engine_cs
*ring
;
4862 for_each_ring(ring
, dev_priv
, i
)
4863 dev_priv
->gt
.stop_ring(ring
);
4867 i915_gem_suspend(struct drm_device
*dev
)
4869 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4872 mutex_lock(&dev
->struct_mutex
);
4873 ret
= i915_gpu_idle(dev
);
4877 i915_gem_retire_requests(dev
);
4879 i915_gem_stop_ringbuffers(dev
);
4880 mutex_unlock(&dev
->struct_mutex
);
4882 cancel_delayed_work_sync(&dev_priv
->gpu_error
.hangcheck_work
);
4883 cancel_delayed_work_sync(&dev_priv
->mm
.retire_work
);
4884 flush_delayed_work(&dev_priv
->mm
.idle_work
);
4886 /* Assert that we sucessfully flushed all the work and
4887 * reset the GPU back to its idle, low power state.
4889 WARN_ON(dev_priv
->mm
.busy
);
4894 mutex_unlock(&dev
->struct_mutex
);
4898 int i915_gem_l3_remap(struct drm_i915_gem_request
*req
, int slice
)
4900 struct intel_engine_cs
*ring
= req
->ring
;
4901 struct drm_device
*dev
= ring
->dev
;
4902 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4903 u32 reg_base
= GEN7_L3LOG_BASE
+ (slice
* 0x200);
4904 u32
*remap_info
= dev_priv
->l3_parity
.remap_info
[slice
];
4907 if (!HAS_L3_DPF(dev
) || !remap_info
)
4910 ret
= intel_ring_begin(req
, GEN7_L3LOG_SIZE
/ 4 * 3);
4915 * Note: We do not worry about the concurrent register cacheline hang
4916 * here because no other code should access these registers other than
4917 * at initialization time.
4919 for (i
= 0; i
< GEN7_L3LOG_SIZE
; i
+= 4) {
4920 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
4921 intel_ring_emit(ring
, reg_base
+ i
);
4922 intel_ring_emit(ring
, remap_info
[i
/4]);
4925 intel_ring_advance(ring
);
4930 void i915_gem_init_swizzling(struct drm_device
*dev
)
4932 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4934 if (INTEL_INFO(dev
)->gen
< 5 ||
4935 dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_NONE
)
4938 I915_WRITE(DISP_ARB_CTL
, I915_READ(DISP_ARB_CTL
) |
4939 DISP_TILE_SURFACE_SWIZZLING
);
4944 I915_WRITE(TILECTL
, I915_READ(TILECTL
) | TILECTL_SWZCTL
);
4946 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB
));
4947 else if (IS_GEN7(dev
))
4948 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB
));
4949 else if (IS_GEN8(dev
))
4950 I915_WRITE(GAMTARBMODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW
));
4956 intel_enable_blt(struct drm_device
*dev
)
4961 /* The blitter was dysfunctional on early prototypes */
4962 if (IS_GEN6(dev
) && dev
->pdev
->revision
< 8) {
4963 DRM_INFO("BLT not supported on this pre-production hardware;"
4964 " graphics performance will be degraded.\n");
4971 static void init_unused_ring(struct drm_device
*dev
, u32 base
)
4973 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4975 I915_WRITE(RING_CTL(base
), 0);
4976 I915_WRITE(RING_HEAD(base
), 0);
4977 I915_WRITE(RING_TAIL(base
), 0);
4978 I915_WRITE(RING_START(base
), 0);
4981 static void init_unused_rings(struct drm_device
*dev
)
4984 init_unused_ring(dev
, PRB1_BASE
);
4985 init_unused_ring(dev
, SRB0_BASE
);
4986 init_unused_ring(dev
, SRB1_BASE
);
4987 init_unused_ring(dev
, SRB2_BASE
);
4988 init_unused_ring(dev
, SRB3_BASE
);
4989 } else if (IS_GEN2(dev
)) {
4990 init_unused_ring(dev
, SRB0_BASE
);
4991 init_unused_ring(dev
, SRB1_BASE
);
4992 } else if (IS_GEN3(dev
)) {
4993 init_unused_ring(dev
, PRB1_BASE
);
4994 init_unused_ring(dev
, PRB2_BASE
);
4998 int i915_gem_init_rings(struct drm_device
*dev
)
5000 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5003 ret
= intel_init_render_ring_buffer(dev
);
5008 ret
= intel_init_bsd_ring_buffer(dev
);
5010 goto cleanup_render_ring
;
5013 if (intel_enable_blt(dev
)) {
5014 ret
= intel_init_blt_ring_buffer(dev
);
5016 goto cleanup_bsd_ring
;
5019 if (HAS_VEBOX(dev
)) {
5020 ret
= intel_init_vebox_ring_buffer(dev
);
5022 goto cleanup_blt_ring
;
5025 if (HAS_BSD2(dev
)) {
5026 ret
= intel_init_bsd2_ring_buffer(dev
);
5028 goto cleanup_vebox_ring
;
5031 ret
= i915_gem_set_seqno(dev
, ((u32
)~0 - 0x1000));
5033 goto cleanup_bsd2_ring
;
5038 intel_cleanup_ring_buffer(&dev_priv
->ring
[VCS2
]);
5040 intel_cleanup_ring_buffer(&dev_priv
->ring
[VECS
]);
5042 intel_cleanup_ring_buffer(&dev_priv
->ring
[BCS
]);
5044 intel_cleanup_ring_buffer(&dev_priv
->ring
[VCS
]);
5045 cleanup_render_ring
:
5046 intel_cleanup_ring_buffer(&dev_priv
->ring
[RCS
]);
5052 i915_gem_init_hw(struct drm_device
*dev
)
5054 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5055 struct intel_engine_cs
*ring
;
5058 if (INTEL_INFO(dev
)->gen
< 6 && !intel_enable_gtt())
5061 /* Double layer security blanket, see i915_gem_init() */
5062 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
5064 if (dev_priv
->ellc_size
)
5065 I915_WRITE(HSW_IDICR
, I915_READ(HSW_IDICR
) | IDIHASHMSK(0xf));
5067 if (IS_HASWELL(dev
))
5068 I915_WRITE(MI_PREDICATE_RESULT_2
, IS_HSW_GT3(dev
) ?
5069 LOWER_SLICE_ENABLED
: LOWER_SLICE_DISABLED
);
5071 if (HAS_PCH_NOP(dev
)) {
5072 if (IS_IVYBRIDGE(dev
)) {
5073 u32 temp
= I915_READ(GEN7_MSG_CTL
);
5074 temp
&= ~(WAIT_FOR_PCH_FLR_ACK
| WAIT_FOR_PCH_RESET_ACK
);
5075 I915_WRITE(GEN7_MSG_CTL
, temp
);
5076 } else if (INTEL_INFO(dev
)->gen
>= 7) {
5077 u32 temp
= I915_READ(HSW_NDE_RSTWRN_OPT
);
5078 temp
&= ~RESET_PCH_HANDSHAKE_ENABLE
;
5079 I915_WRITE(HSW_NDE_RSTWRN_OPT
, temp
);
5083 i915_gem_init_swizzling(dev
);
5086 * At least 830 can leave some of the unused rings
5087 * "active" (ie. head != tail) after resume which
5088 * will prevent c3 entry. Makes sure all unused rings
5091 init_unused_rings(dev
);
5093 BUG_ON(!dev_priv
->ring
[RCS
].default_context
);
5095 ret
= i915_ppgtt_init_hw(dev
);
5097 DRM_ERROR("PPGTT enable HW failed %d\n", ret
);
5101 /* Need to do basic initialisation of all rings first: */
5102 for_each_ring(ring
, dev_priv
, i
) {
5103 ret
= ring
->init_hw(ring
);
5108 /* Now it is safe to go back round and do everything else: */
5109 for_each_ring(ring
, dev_priv
, i
) {
5110 struct drm_i915_gem_request
*req
;
5112 WARN_ON(!ring
->default_context
);
5114 ret
= i915_gem_request_alloc(ring
, ring
->default_context
, &req
);
5116 i915_gem_cleanup_ringbuffer(dev
);
5120 if (ring
->id
== RCS
) {
5121 for (j
= 0; j
< NUM_L3_SLICES(dev
); j
++)
5122 i915_gem_l3_remap(req
, j
);
5125 ret
= i915_ppgtt_init_ring(req
);
5126 if (ret
&& ret
!= -EIO
) {
5127 DRM_ERROR("PPGTT enable ring #%d failed %d\n", i
, ret
);
5128 i915_gem_request_cancel(req
);
5129 i915_gem_cleanup_ringbuffer(dev
);
5133 ret
= i915_gem_context_enable(req
);
5134 if (ret
&& ret
!= -EIO
) {
5135 DRM_ERROR("Context enable ring #%d failed %d\n", i
, ret
);
5136 i915_gem_request_cancel(req
);
5137 i915_gem_cleanup_ringbuffer(dev
);
5141 i915_add_request_no_flush(req
);
5145 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
5149 int i915_gem_init(struct drm_device
*dev
)
5151 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5154 i915
.enable_execlists
= intel_sanitize_enable_execlists(dev
,
5155 i915
.enable_execlists
);
5157 mutex_lock(&dev
->struct_mutex
);
5159 if (IS_VALLEYVIEW(dev
)) {
5160 /* VLVA0 (potential hack), BIOS isn't actually waking us */
5161 I915_WRITE(VLV_GTLC_WAKE_CTRL
, VLV_GTLC_ALLOWWAKEREQ
);
5162 if (wait_for((I915_READ(VLV_GTLC_PW_STATUS
) &
5163 VLV_GTLC_ALLOWWAKEACK
), 10))
5164 DRM_DEBUG_DRIVER("allow wake ack timed out\n");
5167 if (!i915
.enable_execlists
) {
5168 dev_priv
->gt
.execbuf_submit
= i915_gem_ringbuffer_submission
;
5169 dev_priv
->gt
.init_rings
= i915_gem_init_rings
;
5170 dev_priv
->gt
.cleanup_ring
= intel_cleanup_ring_buffer
;
5171 dev_priv
->gt
.stop_ring
= intel_stop_ring_buffer
;
5173 dev_priv
->gt
.execbuf_submit
= intel_execlists_submission
;
5174 dev_priv
->gt
.init_rings
= intel_logical_rings_init
;
5175 dev_priv
->gt
.cleanup_ring
= intel_logical_ring_cleanup
;
5176 dev_priv
->gt
.stop_ring
= intel_logical_ring_stop
;
5179 /* This is just a security blanket to placate dragons.
5180 * On some systems, we very sporadically observe that the first TLBs
5181 * used by the CS may be stale, despite us poking the TLB reset. If
5182 * we hold the forcewake during initialisation these problems
5183 * just magically go away.
5185 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
5187 ret
= i915_gem_init_userptr(dev
);
5191 i915_gem_init_global_gtt(dev
);
5193 ret
= i915_gem_context_init(dev
);
5197 ret
= dev_priv
->gt
.init_rings(dev
);
5201 ret
= i915_gem_init_hw(dev
);
5203 /* Allow ring initialisation to fail by marking the GPU as
5204 * wedged. But we only want to do this where the GPU is angry,
5205 * for all other failure, such as an allocation failure, bail.
5207 DRM_ERROR("Failed to initialize GPU, declaring it wedged\n");
5208 atomic_set_mask(I915_WEDGED
, &dev_priv
->gpu_error
.reset_counter
);
5213 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
5214 mutex_unlock(&dev
->struct_mutex
);
5220 i915_gem_cleanup_ringbuffer(struct drm_device
*dev
)
5222 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5223 struct intel_engine_cs
*ring
;
5226 for_each_ring(ring
, dev_priv
, i
)
5227 dev_priv
->gt
.cleanup_ring(ring
);
5231 init_ring_lists(struct intel_engine_cs
*ring
)
5233 INIT_LIST_HEAD(&ring
->active_list
);
5234 INIT_LIST_HEAD(&ring
->request_list
);
5237 void i915_init_vm(struct drm_i915_private
*dev_priv
,
5238 struct i915_address_space
*vm
)
5240 if (!i915_is_ggtt(vm
))
5241 drm_mm_init(&vm
->mm
, vm
->start
, vm
->total
);
5242 vm
->dev
= dev_priv
->dev
;
5243 INIT_LIST_HEAD(&vm
->active_list
);
5244 INIT_LIST_HEAD(&vm
->inactive_list
);
5245 INIT_LIST_HEAD(&vm
->global_link
);
5246 list_add_tail(&vm
->global_link
, &dev_priv
->vm_list
);
5250 i915_gem_load(struct drm_device
*dev
)
5252 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5256 kmem_cache_create("i915_gem_object",
5257 sizeof(struct drm_i915_gem_object
), 0,
5261 kmem_cache_create("i915_gem_vma",
5262 sizeof(struct i915_vma
), 0,
5265 dev_priv
->requests
=
5266 kmem_cache_create("i915_gem_request",
5267 sizeof(struct drm_i915_gem_request
), 0,
5271 INIT_LIST_HEAD(&dev_priv
->vm_list
);
5272 i915_init_vm(dev_priv
, &dev_priv
->gtt
.base
);
5274 INIT_LIST_HEAD(&dev_priv
->context_list
);
5275 INIT_LIST_HEAD(&dev_priv
->mm
.unbound_list
);
5276 INIT_LIST_HEAD(&dev_priv
->mm
.bound_list
);
5277 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
5278 for (i
= 0; i
< I915_NUM_RINGS
; i
++)
5279 init_ring_lists(&dev_priv
->ring
[i
]);
5280 for (i
= 0; i
< I915_MAX_NUM_FENCES
; i
++)
5281 INIT_LIST_HEAD(&dev_priv
->fence_regs
[i
].lru_list
);
5282 INIT_DELAYED_WORK(&dev_priv
->mm
.retire_work
,
5283 i915_gem_retire_work_handler
);
5284 INIT_DELAYED_WORK(&dev_priv
->mm
.idle_work
,
5285 i915_gem_idle_work_handler
);
5286 init_waitqueue_head(&dev_priv
->gpu_error
.reset_queue
);
5288 dev_priv
->relative_constants_mode
= I915_EXEC_CONSTANTS_REL_GENERAL
;
5290 if (INTEL_INFO(dev
)->gen
>= 7 && !IS_VALLEYVIEW(dev
))
5291 dev_priv
->num_fence_regs
= 32;
5292 else if (INTEL_INFO(dev
)->gen
>= 4 || IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
5293 dev_priv
->num_fence_regs
= 16;
5295 dev_priv
->num_fence_regs
= 8;
5297 if (intel_vgpu_active(dev
))
5298 dev_priv
->num_fence_regs
=
5299 I915_READ(vgtif_reg(avail_rs
.fence_num
));
5301 /* Initialize fence registers to zero */
5302 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
5303 i915_gem_restore_fences(dev
);
5305 i915_gem_detect_bit_6_swizzle(dev
);
5306 init_waitqueue_head(&dev_priv
->pending_flip_queue
);
5308 dev_priv
->mm
.interruptible
= true;
5310 i915_gem_shrinker_init(dev_priv
);
5312 mutex_init(&dev_priv
->fb_tracking
.lock
);
5315 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
)
5317 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
5319 /* Clean up our request list when the client is going away, so that
5320 * later retire_requests won't dereference our soon-to-be-gone
5323 spin_lock(&file_priv
->mm
.lock
);
5324 while (!list_empty(&file_priv
->mm
.request_list
)) {
5325 struct drm_i915_gem_request
*request
;
5327 request
= list_first_entry(&file_priv
->mm
.request_list
,
5328 struct drm_i915_gem_request
,
5330 list_del(&request
->client_list
);
5331 request
->file_priv
= NULL
;
5333 spin_unlock(&file_priv
->mm
.lock
);
5335 if (!list_empty(&file_priv
->rps
.link
)) {
5336 spin_lock(&to_i915(dev
)->rps
.client_lock
);
5337 list_del(&file_priv
->rps
.link
);
5338 spin_unlock(&to_i915(dev
)->rps
.client_lock
);
5342 int i915_gem_open(struct drm_device
*dev
, struct drm_file
*file
)
5344 struct drm_i915_file_private
*file_priv
;
5347 DRM_DEBUG_DRIVER("\n");
5349 file_priv
= kzalloc(sizeof(*file_priv
), GFP_KERNEL
);
5353 file
->driver_priv
= file_priv
;
5354 file_priv
->dev_priv
= dev
->dev_private
;
5355 file_priv
->file
= file
;
5356 INIT_LIST_HEAD(&file_priv
->rps
.link
);
5358 spin_lock_init(&file_priv
->mm
.lock
);
5359 INIT_LIST_HEAD(&file_priv
->mm
.request_list
);
5361 ret
= i915_gem_context_open(dev
, file
);
5369 * i915_gem_track_fb - update frontbuffer tracking
5370 * old: current GEM buffer for the frontbuffer slots
5371 * new: new GEM buffer for the frontbuffer slots
5372 * frontbuffer_bits: bitmask of frontbuffer slots
5374 * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them
5375 * from @old and setting them in @new. Both @old and @new can be NULL.
5377 void i915_gem_track_fb(struct drm_i915_gem_object
*old
,
5378 struct drm_i915_gem_object
*new,
5379 unsigned frontbuffer_bits
)
5382 WARN_ON(!mutex_is_locked(&old
->base
.dev
->struct_mutex
));
5383 WARN_ON(!(old
->frontbuffer_bits
& frontbuffer_bits
));
5384 old
->frontbuffer_bits
&= ~frontbuffer_bits
;
5388 WARN_ON(!mutex_is_locked(&new->base
.dev
->struct_mutex
));
5389 WARN_ON(new->frontbuffer_bits
& frontbuffer_bits
);
5390 new->frontbuffer_bits
|= frontbuffer_bits
;
5394 /* All the new VM stuff */
5396 i915_gem_obj_offset(struct drm_i915_gem_object
*o
,
5397 struct i915_address_space
*vm
)
5399 struct drm_i915_private
*dev_priv
= o
->base
.dev
->dev_private
;
5400 struct i915_vma
*vma
;
5402 WARN_ON(vm
== &dev_priv
->mm
.aliasing_ppgtt
->base
);
5404 list_for_each_entry(vma
, &o
->vma_list
, vma_link
) {
5405 if (i915_is_ggtt(vma
->vm
) &&
5406 vma
->ggtt_view
.type
!= I915_GGTT_VIEW_NORMAL
)
5409 return vma
->node
.start
;
5412 WARN(1, "%s vma for this object not found.\n",
5413 i915_is_ggtt(vm
) ? "global" : "ppgtt");
5418 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object
*o
,
5419 const struct i915_ggtt_view
*view
)
5421 struct i915_address_space
*ggtt
= i915_obj_to_ggtt(o
);
5422 struct i915_vma
*vma
;
5424 list_for_each_entry(vma
, &o
->vma_list
, vma_link
)
5425 if (vma
->vm
== ggtt
&&
5426 i915_ggtt_view_equal(&vma
->ggtt_view
, view
))
5427 return vma
->node
.start
;
5429 WARN(1, "global vma for this object not found. (view=%u)\n", view
->type
);
5433 bool i915_gem_obj_bound(struct drm_i915_gem_object
*o
,
5434 struct i915_address_space
*vm
)
5436 struct i915_vma
*vma
;
5438 list_for_each_entry(vma
, &o
->vma_list
, vma_link
) {
5439 if (i915_is_ggtt(vma
->vm
) &&
5440 vma
->ggtt_view
.type
!= I915_GGTT_VIEW_NORMAL
)
5442 if (vma
->vm
== vm
&& drm_mm_node_allocated(&vma
->node
))
5449 bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object
*o
,
5450 const struct i915_ggtt_view
*view
)
5452 struct i915_address_space
*ggtt
= i915_obj_to_ggtt(o
);
5453 struct i915_vma
*vma
;
5455 list_for_each_entry(vma
, &o
->vma_list
, vma_link
)
5456 if (vma
->vm
== ggtt
&&
5457 i915_ggtt_view_equal(&vma
->ggtt_view
, view
) &&
5458 drm_mm_node_allocated(&vma
->node
))
5464 bool i915_gem_obj_bound_any(struct drm_i915_gem_object
*o
)
5466 struct i915_vma
*vma
;
5468 list_for_each_entry(vma
, &o
->vma_list
, vma_link
)
5469 if (drm_mm_node_allocated(&vma
->node
))
5475 unsigned long i915_gem_obj_size(struct drm_i915_gem_object
*o
,
5476 struct i915_address_space
*vm
)
5478 struct drm_i915_private
*dev_priv
= o
->base
.dev
->dev_private
;
5479 struct i915_vma
*vma
;
5481 WARN_ON(vm
== &dev_priv
->mm
.aliasing_ppgtt
->base
);
5483 BUG_ON(list_empty(&o
->vma_list
));
5485 list_for_each_entry(vma
, &o
->vma_list
, vma_link
) {
5486 if (i915_is_ggtt(vma
->vm
) &&
5487 vma
->ggtt_view
.type
!= I915_GGTT_VIEW_NORMAL
)
5490 return vma
->node
.size
;
5495 bool i915_gem_obj_is_pinned(struct drm_i915_gem_object
*obj
)
5497 struct i915_vma
*vma
;
5498 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
5499 if (vma
->pin_count
> 0)