2 * Copyright © 2008-2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/drm_vma_manager.h>
30 #include <drm/i915_drm.h>
32 #include "i915_vgpu.h"
33 #include "i915_trace.h"
34 #include "intel_drv.h"
35 #include <linux/shmem_fs.h>
36 #include <linux/slab.h>
37 #include <linux/swap.h>
38 #include <linux/pci.h>
39 #include <linux/dma-buf.h>
41 #define RQ_BUG_ON(expr)
43 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
);
44 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
);
46 i915_gem_object_retire__write(struct drm_i915_gem_object
*obj
);
48 i915_gem_object_retire__read(struct drm_i915_gem_object
*obj
, int ring
);
50 static bool cpu_cache_is_coherent(struct drm_device
*dev
,
51 enum i915_cache_level level
)
53 return HAS_LLC(dev
) || level
!= I915_CACHE_NONE
;
56 static bool cpu_write_needs_clflush(struct drm_i915_gem_object
*obj
)
58 if (!cpu_cache_is_coherent(obj
->base
.dev
, obj
->cache_level
))
61 return obj
->pin_display
;
64 /* some bookkeeping */
65 static void i915_gem_info_add_obj(struct drm_i915_private
*dev_priv
,
68 spin_lock(&dev_priv
->mm
.object_stat_lock
);
69 dev_priv
->mm
.object_count
++;
70 dev_priv
->mm
.object_memory
+= size
;
71 spin_unlock(&dev_priv
->mm
.object_stat_lock
);
74 static void i915_gem_info_remove_obj(struct drm_i915_private
*dev_priv
,
77 spin_lock(&dev_priv
->mm
.object_stat_lock
);
78 dev_priv
->mm
.object_count
--;
79 dev_priv
->mm
.object_memory
-= size
;
80 spin_unlock(&dev_priv
->mm
.object_stat_lock
);
84 i915_gem_wait_for_error(struct i915_gpu_error
*error
)
88 #define EXIT_COND (!i915_reset_in_progress(error) || \
89 i915_terminally_wedged(error))
94 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
95 * userspace. If it takes that long something really bad is going on and
96 * we should simply try to bail out and fail as gracefully as possible.
98 ret
= wait_event_interruptible_timeout(error
->reset_queue
,
102 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
104 } else if (ret
< 0) {
112 int i915_mutex_lock_interruptible(struct drm_device
*dev
)
114 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
117 ret
= i915_gem_wait_for_error(&dev_priv
->gpu_error
);
121 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
125 WARN_ON(i915_verify_lists(dev
));
130 i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
131 struct drm_file
*file
)
133 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
134 struct drm_i915_gem_get_aperture
*args
= data
;
135 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
136 struct i915_vma
*vma
;
140 mutex_lock(&dev
->struct_mutex
);
141 list_for_each_entry(vma
, &ggtt
->base
.active_list
, vm_link
)
143 pinned
+= vma
->node
.size
;
144 list_for_each_entry(vma
, &ggtt
->base
.inactive_list
, vm_link
)
146 pinned
+= vma
->node
.size
;
147 mutex_unlock(&dev
->struct_mutex
);
149 args
->aper_size
= dev_priv
->ggtt
.base
.total
;
150 args
->aper_available_size
= args
->aper_size
- pinned
;
156 i915_gem_object_get_pages_phys(struct drm_i915_gem_object
*obj
)
158 struct address_space
*mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
159 char *vaddr
= obj
->phys_handle
->vaddr
;
161 struct scatterlist
*sg
;
164 if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj
)))
167 for (i
= 0; i
< obj
->base
.size
/ PAGE_SIZE
; i
++) {
171 page
= shmem_read_mapping_page(mapping
, i
);
173 return PTR_ERR(page
);
175 src
= kmap_atomic(page
);
176 memcpy(vaddr
, src
, PAGE_SIZE
);
177 drm_clflush_virt_range(vaddr
, PAGE_SIZE
);
180 page_cache_release(page
);
184 i915_gem_chipset_flush(obj
->base
.dev
);
186 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
190 if (sg_alloc_table(st
, 1, GFP_KERNEL
)) {
197 sg
->length
= obj
->base
.size
;
199 sg_dma_address(sg
) = obj
->phys_handle
->busaddr
;
200 sg_dma_len(sg
) = obj
->base
.size
;
207 i915_gem_object_put_pages_phys(struct drm_i915_gem_object
*obj
)
211 BUG_ON(obj
->madv
== __I915_MADV_PURGED
);
213 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
215 /* In the event of a disaster, abandon all caches and
218 WARN_ON(ret
!= -EIO
);
219 obj
->base
.read_domains
= obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
222 if (obj
->madv
== I915_MADV_DONTNEED
)
226 struct address_space
*mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
227 char *vaddr
= obj
->phys_handle
->vaddr
;
230 for (i
= 0; i
< obj
->base
.size
/ PAGE_SIZE
; i
++) {
234 page
= shmem_read_mapping_page(mapping
, i
);
238 dst
= kmap_atomic(page
);
239 drm_clflush_virt_range(vaddr
, PAGE_SIZE
);
240 memcpy(dst
, vaddr
, PAGE_SIZE
);
243 set_page_dirty(page
);
244 if (obj
->madv
== I915_MADV_WILLNEED
)
245 mark_page_accessed(page
);
246 page_cache_release(page
);
252 sg_free_table(obj
->pages
);
257 i915_gem_object_release_phys(struct drm_i915_gem_object
*obj
)
259 drm_pci_free(obj
->base
.dev
, obj
->phys_handle
);
262 static const struct drm_i915_gem_object_ops i915_gem_phys_ops
= {
263 .get_pages
= i915_gem_object_get_pages_phys
,
264 .put_pages
= i915_gem_object_put_pages_phys
,
265 .release
= i915_gem_object_release_phys
,
269 drop_pages(struct drm_i915_gem_object
*obj
)
271 struct i915_vma
*vma
, *next
;
274 drm_gem_object_reference(&obj
->base
);
275 list_for_each_entry_safe(vma
, next
, &obj
->vma_list
, obj_link
)
276 if (i915_vma_unbind(vma
))
279 ret
= i915_gem_object_put_pages(obj
);
280 drm_gem_object_unreference(&obj
->base
);
286 i915_gem_object_attach_phys(struct drm_i915_gem_object
*obj
,
289 drm_dma_handle_t
*phys
;
292 if (obj
->phys_handle
) {
293 if ((unsigned long)obj
->phys_handle
->vaddr
& (align
-1))
299 if (obj
->madv
!= I915_MADV_WILLNEED
)
302 if (obj
->base
.filp
== NULL
)
305 ret
= drop_pages(obj
);
309 /* create a new object */
310 phys
= drm_pci_alloc(obj
->base
.dev
, obj
->base
.size
, align
);
314 obj
->phys_handle
= phys
;
315 obj
->ops
= &i915_gem_phys_ops
;
317 return i915_gem_object_get_pages(obj
);
321 i915_gem_phys_pwrite(struct drm_i915_gem_object
*obj
,
322 struct drm_i915_gem_pwrite
*args
,
323 struct drm_file
*file_priv
)
325 struct drm_device
*dev
= obj
->base
.dev
;
326 void *vaddr
= obj
->phys_handle
->vaddr
+ args
->offset
;
327 char __user
*user_data
= to_user_ptr(args
->data_ptr
);
330 /* We manually control the domain here and pretend that it
331 * remains coherent i.e. in the GTT domain, like shmem_pwrite.
333 ret
= i915_gem_object_wait_rendering(obj
, false);
337 intel_fb_obj_invalidate(obj
, ORIGIN_CPU
);
338 if (__copy_from_user_inatomic_nocache(vaddr
, user_data
, args
->size
)) {
339 unsigned long unwritten
;
341 /* The physical object once assigned is fixed for the lifetime
342 * of the obj, so we can safely drop the lock and continue
345 mutex_unlock(&dev
->struct_mutex
);
346 unwritten
= copy_from_user(vaddr
, user_data
, args
->size
);
347 mutex_lock(&dev
->struct_mutex
);
354 drm_clflush_virt_range(vaddr
, args
->size
);
355 i915_gem_chipset_flush(dev
);
358 intel_fb_obj_flush(obj
, false, ORIGIN_CPU
);
362 void *i915_gem_object_alloc(struct drm_device
*dev
)
364 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
365 return kmem_cache_zalloc(dev_priv
->objects
, GFP_KERNEL
);
368 void i915_gem_object_free(struct drm_i915_gem_object
*obj
)
370 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
371 kmem_cache_free(dev_priv
->objects
, obj
);
375 i915_gem_create(struct drm_file
*file
,
376 struct drm_device
*dev
,
380 struct drm_i915_gem_object
*obj
;
384 size
= roundup(size
, PAGE_SIZE
);
388 /* Allocate the new object */
389 obj
= i915_gem_alloc_object(dev
, size
);
393 ret
= drm_gem_handle_create(file
, &obj
->base
, &handle
);
394 /* drop reference from allocate - handle holds it now */
395 drm_gem_object_unreference_unlocked(&obj
->base
);
404 i915_gem_dumb_create(struct drm_file
*file
,
405 struct drm_device
*dev
,
406 struct drm_mode_create_dumb
*args
)
408 /* have to work out size/pitch and return them */
409 args
->pitch
= ALIGN(args
->width
* DIV_ROUND_UP(args
->bpp
, 8), 64);
410 args
->size
= args
->pitch
* args
->height
;
411 return i915_gem_create(file
, dev
,
412 args
->size
, &args
->handle
);
416 * Creates a new mm object and returns a handle to it.
419 i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
420 struct drm_file
*file
)
422 struct drm_i915_gem_create
*args
= data
;
424 return i915_gem_create(file
, dev
,
425 args
->size
, &args
->handle
);
429 __copy_to_user_swizzled(char __user
*cpu_vaddr
,
430 const char *gpu_vaddr
, int gpu_offset
,
433 int ret
, cpu_offset
= 0;
436 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
437 int this_length
= min(cacheline_end
- gpu_offset
, length
);
438 int swizzled_gpu_offset
= gpu_offset
^ 64;
440 ret
= __copy_to_user(cpu_vaddr
+ cpu_offset
,
441 gpu_vaddr
+ swizzled_gpu_offset
,
446 cpu_offset
+= this_length
;
447 gpu_offset
+= this_length
;
448 length
-= this_length
;
455 __copy_from_user_swizzled(char *gpu_vaddr
, int gpu_offset
,
456 const char __user
*cpu_vaddr
,
459 int ret
, cpu_offset
= 0;
462 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
463 int this_length
= min(cacheline_end
- gpu_offset
, length
);
464 int swizzled_gpu_offset
= gpu_offset
^ 64;
466 ret
= __copy_from_user(gpu_vaddr
+ swizzled_gpu_offset
,
467 cpu_vaddr
+ cpu_offset
,
472 cpu_offset
+= this_length
;
473 gpu_offset
+= this_length
;
474 length
-= this_length
;
481 * Pins the specified object's pages and synchronizes the object with
482 * GPU accesses. Sets needs_clflush to non-zero if the caller should
483 * flush the object from the CPU cache.
485 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object
*obj
,
492 if (WARN_ON((obj
->ops
->flags
& I915_GEM_OBJECT_HAS_STRUCT_PAGE
) == 0))
495 if (!(obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
)) {
496 /* If we're not in the cpu read domain, set ourself into the gtt
497 * read domain and manually flush cachelines (if required). This
498 * optimizes for the case when the gpu will dirty the data
499 * anyway again before the next pread happens. */
500 *needs_clflush
= !cpu_cache_is_coherent(obj
->base
.dev
,
502 ret
= i915_gem_object_wait_rendering(obj
, true);
507 ret
= i915_gem_object_get_pages(obj
);
511 i915_gem_object_pin_pages(obj
);
516 /* Per-page copy function for the shmem pread fastpath.
517 * Flushes invalid cachelines before reading the target if
518 * needs_clflush is set. */
520 shmem_pread_fast(struct page
*page
, int shmem_page_offset
, int page_length
,
521 char __user
*user_data
,
522 bool page_do_bit17_swizzling
, bool needs_clflush
)
527 if (unlikely(page_do_bit17_swizzling
))
530 vaddr
= kmap_atomic(page
);
532 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
534 ret
= __copy_to_user_inatomic(user_data
,
535 vaddr
+ shmem_page_offset
,
537 kunmap_atomic(vaddr
);
539 return ret
? -EFAULT
: 0;
543 shmem_clflush_swizzled_range(char *addr
, unsigned long length
,
546 if (unlikely(swizzled
)) {
547 unsigned long start
= (unsigned long) addr
;
548 unsigned long end
= (unsigned long) addr
+ length
;
550 /* For swizzling simply ensure that we always flush both
551 * channels. Lame, but simple and it works. Swizzled
552 * pwrite/pread is far from a hotpath - current userspace
553 * doesn't use it at all. */
554 start
= round_down(start
, 128);
555 end
= round_up(end
, 128);
557 drm_clflush_virt_range((void *)start
, end
- start
);
559 drm_clflush_virt_range(addr
, length
);
564 /* Only difference to the fast-path function is that this can handle bit17
565 * and uses non-atomic copy and kmap functions. */
567 shmem_pread_slow(struct page
*page
, int shmem_page_offset
, int page_length
,
568 char __user
*user_data
,
569 bool page_do_bit17_swizzling
, bool needs_clflush
)
576 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
578 page_do_bit17_swizzling
);
580 if (page_do_bit17_swizzling
)
581 ret
= __copy_to_user_swizzled(user_data
,
582 vaddr
, shmem_page_offset
,
585 ret
= __copy_to_user(user_data
,
586 vaddr
+ shmem_page_offset
,
590 return ret
? - EFAULT
: 0;
594 i915_gem_shmem_pread(struct drm_device
*dev
,
595 struct drm_i915_gem_object
*obj
,
596 struct drm_i915_gem_pread
*args
,
597 struct drm_file
*file
)
599 char __user
*user_data
;
602 int shmem_page_offset
, page_length
, ret
= 0;
603 int obj_do_bit17_swizzling
, page_do_bit17_swizzling
;
605 int needs_clflush
= 0;
606 struct sg_page_iter sg_iter
;
608 user_data
= to_user_ptr(args
->data_ptr
);
611 obj_do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
613 ret
= i915_gem_obj_prepare_shmem_read(obj
, &needs_clflush
);
617 offset
= args
->offset
;
619 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
,
620 offset
>> PAGE_SHIFT
) {
621 struct page
*page
= sg_page_iter_page(&sg_iter
);
626 /* Operation in this page
628 * shmem_page_offset = offset within page in shmem file
629 * page_length = bytes to copy for this page
631 shmem_page_offset
= offset_in_page(offset
);
632 page_length
= remain
;
633 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
634 page_length
= PAGE_SIZE
- shmem_page_offset
;
636 page_do_bit17_swizzling
= obj_do_bit17_swizzling
&&
637 (page_to_phys(page
) & (1 << 17)) != 0;
639 ret
= shmem_pread_fast(page
, shmem_page_offset
, page_length
,
640 user_data
, page_do_bit17_swizzling
,
645 mutex_unlock(&dev
->struct_mutex
);
647 if (likely(!i915
.prefault_disable
) && !prefaulted
) {
648 ret
= fault_in_multipages_writeable(user_data
, remain
);
649 /* Userspace is tricking us, but we've already clobbered
650 * its pages with the prefault and promised to write the
651 * data up to the first fault. Hence ignore any errors
652 * and just continue. */
657 ret
= shmem_pread_slow(page
, shmem_page_offset
, page_length
,
658 user_data
, page_do_bit17_swizzling
,
661 mutex_lock(&dev
->struct_mutex
);
667 remain
-= page_length
;
668 user_data
+= page_length
;
669 offset
+= page_length
;
673 i915_gem_object_unpin_pages(obj
);
679 * Reads data from the object referenced by handle.
681 * On error, the contents of *data are undefined.
684 i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
685 struct drm_file
*file
)
687 struct drm_i915_gem_pread
*args
= data
;
688 struct drm_i915_gem_object
*obj
;
694 if (!access_ok(VERIFY_WRITE
,
695 to_user_ptr(args
->data_ptr
),
699 ret
= i915_mutex_lock_interruptible(dev
);
703 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
704 if (&obj
->base
== NULL
) {
709 /* Bounds check source. */
710 if (args
->offset
> obj
->base
.size
||
711 args
->size
> obj
->base
.size
- args
->offset
) {
716 /* prime objects have no backing filp to GEM pread/pwrite
719 if (!obj
->base
.filp
) {
724 trace_i915_gem_object_pread(obj
, args
->offset
, args
->size
);
726 ret
= i915_gem_shmem_pread(dev
, obj
, args
, file
);
729 drm_gem_object_unreference(&obj
->base
);
731 mutex_unlock(&dev
->struct_mutex
);
735 /* This is the fast write path which cannot handle
736 * page faults in the source data
740 fast_user_write(struct io_mapping
*mapping
,
741 loff_t page_base
, int page_offset
,
742 char __user
*user_data
,
745 void __iomem
*vaddr_atomic
;
747 unsigned long unwritten
;
749 vaddr_atomic
= io_mapping_map_atomic_wc(mapping
, page_base
);
750 /* We can use the cpu mem copy function because this is X86. */
751 vaddr
= (void __force
*)vaddr_atomic
+ page_offset
;
752 unwritten
= __copy_from_user_inatomic_nocache(vaddr
,
754 io_mapping_unmap_atomic(vaddr_atomic
);
759 * This is the fast pwrite path, where we copy the data directly from the
760 * user into the GTT, uncached.
763 i915_gem_gtt_pwrite_fast(struct drm_device
*dev
,
764 struct drm_i915_gem_object
*obj
,
765 struct drm_i915_gem_pwrite
*args
,
766 struct drm_file
*file
)
768 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
770 loff_t offset
, page_base
;
771 char __user
*user_data
;
772 int page_offset
, page_length
, ret
;
774 ret
= i915_gem_obj_ggtt_pin(obj
, 0, PIN_MAPPABLE
| PIN_NONBLOCK
);
778 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
782 ret
= i915_gem_object_put_fence(obj
);
786 user_data
= to_user_ptr(args
->data_ptr
);
789 offset
= i915_gem_obj_ggtt_offset(obj
) + args
->offset
;
791 intel_fb_obj_invalidate(obj
, ORIGIN_GTT
);
794 /* Operation in this page
796 * page_base = page offset within aperture
797 * page_offset = offset within page
798 * page_length = bytes to copy for this page
800 page_base
= offset
& PAGE_MASK
;
801 page_offset
= offset_in_page(offset
);
802 page_length
= remain
;
803 if ((page_offset
+ remain
) > PAGE_SIZE
)
804 page_length
= PAGE_SIZE
- page_offset
;
806 /* If we get a fault while copying data, then (presumably) our
807 * source page isn't available. Return the error and we'll
808 * retry in the slow path.
810 if (fast_user_write(dev_priv
->ggtt
.mappable
, page_base
,
811 page_offset
, user_data
, page_length
)) {
816 remain
-= page_length
;
817 user_data
+= page_length
;
818 offset
+= page_length
;
822 intel_fb_obj_flush(obj
, false, ORIGIN_GTT
);
824 i915_gem_object_ggtt_unpin(obj
);
829 /* Per-page copy function for the shmem pwrite fastpath.
830 * Flushes invalid cachelines before writing to the target if
831 * needs_clflush_before is set and flushes out any written cachelines after
832 * writing if needs_clflush is set. */
834 shmem_pwrite_fast(struct page
*page
, int shmem_page_offset
, int page_length
,
835 char __user
*user_data
,
836 bool page_do_bit17_swizzling
,
837 bool needs_clflush_before
,
838 bool needs_clflush_after
)
843 if (unlikely(page_do_bit17_swizzling
))
846 vaddr
= kmap_atomic(page
);
847 if (needs_clflush_before
)
848 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
850 ret
= __copy_from_user_inatomic(vaddr
+ shmem_page_offset
,
851 user_data
, page_length
);
852 if (needs_clflush_after
)
853 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
855 kunmap_atomic(vaddr
);
857 return ret
? -EFAULT
: 0;
860 /* Only difference to the fast-path function is that this can handle bit17
861 * and uses non-atomic copy and kmap functions. */
863 shmem_pwrite_slow(struct page
*page
, int shmem_page_offset
, int page_length
,
864 char __user
*user_data
,
865 bool page_do_bit17_swizzling
,
866 bool needs_clflush_before
,
867 bool needs_clflush_after
)
873 if (unlikely(needs_clflush_before
|| page_do_bit17_swizzling
))
874 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
876 page_do_bit17_swizzling
);
877 if (page_do_bit17_swizzling
)
878 ret
= __copy_from_user_swizzled(vaddr
, shmem_page_offset
,
882 ret
= __copy_from_user(vaddr
+ shmem_page_offset
,
885 if (needs_clflush_after
)
886 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
888 page_do_bit17_swizzling
);
891 return ret
? -EFAULT
: 0;
895 i915_gem_shmem_pwrite(struct drm_device
*dev
,
896 struct drm_i915_gem_object
*obj
,
897 struct drm_i915_gem_pwrite
*args
,
898 struct drm_file
*file
)
902 char __user
*user_data
;
903 int shmem_page_offset
, page_length
, ret
= 0;
904 int obj_do_bit17_swizzling
, page_do_bit17_swizzling
;
905 int hit_slowpath
= 0;
906 int needs_clflush_after
= 0;
907 int needs_clflush_before
= 0;
908 struct sg_page_iter sg_iter
;
910 user_data
= to_user_ptr(args
->data_ptr
);
913 obj_do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
915 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
916 /* If we're not in the cpu write domain, set ourself into the gtt
917 * write domain and manually flush cachelines (if required). This
918 * optimizes for the case when the gpu will use the data
919 * right away and we therefore have to clflush anyway. */
920 needs_clflush_after
= cpu_write_needs_clflush(obj
);
921 ret
= i915_gem_object_wait_rendering(obj
, false);
925 /* Same trick applies to invalidate partially written cachelines read
927 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) == 0)
928 needs_clflush_before
=
929 !cpu_cache_is_coherent(dev
, obj
->cache_level
);
931 ret
= i915_gem_object_get_pages(obj
);
935 intel_fb_obj_invalidate(obj
, ORIGIN_CPU
);
937 i915_gem_object_pin_pages(obj
);
939 offset
= args
->offset
;
942 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
,
943 offset
>> PAGE_SHIFT
) {
944 struct page
*page
= sg_page_iter_page(&sg_iter
);
945 int partial_cacheline_write
;
950 /* Operation in this page
952 * shmem_page_offset = offset within page in shmem file
953 * page_length = bytes to copy for this page
955 shmem_page_offset
= offset_in_page(offset
);
957 page_length
= remain
;
958 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
959 page_length
= PAGE_SIZE
- shmem_page_offset
;
961 /* If we don't overwrite a cacheline completely we need to be
962 * careful to have up-to-date data by first clflushing. Don't
963 * overcomplicate things and flush the entire patch. */
964 partial_cacheline_write
= needs_clflush_before
&&
965 ((shmem_page_offset
| page_length
)
966 & (boot_cpu_data
.x86_clflush_size
- 1));
968 page_do_bit17_swizzling
= obj_do_bit17_swizzling
&&
969 (page_to_phys(page
) & (1 << 17)) != 0;
971 ret
= shmem_pwrite_fast(page
, shmem_page_offset
, page_length
,
972 user_data
, page_do_bit17_swizzling
,
973 partial_cacheline_write
,
974 needs_clflush_after
);
979 mutex_unlock(&dev
->struct_mutex
);
980 ret
= shmem_pwrite_slow(page
, shmem_page_offset
, page_length
,
981 user_data
, page_do_bit17_swizzling
,
982 partial_cacheline_write
,
983 needs_clflush_after
);
985 mutex_lock(&dev
->struct_mutex
);
991 remain
-= page_length
;
992 user_data
+= page_length
;
993 offset
+= page_length
;
997 i915_gem_object_unpin_pages(obj
);
1001 * Fixup: Flush cpu caches in case we didn't flush the dirty
1002 * cachelines in-line while writing and the object moved
1003 * out of the cpu write domain while we've dropped the lock.
1005 if (!needs_clflush_after
&&
1006 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
1007 if (i915_gem_clflush_object(obj
, obj
->pin_display
))
1008 needs_clflush_after
= true;
1012 if (needs_clflush_after
)
1013 i915_gem_chipset_flush(dev
);
1015 obj
->cache_dirty
= true;
1017 intel_fb_obj_flush(obj
, false, ORIGIN_CPU
);
1022 * Writes data to the object referenced by handle.
1024 * On error, the contents of the buffer that were to be modified are undefined.
1027 i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
1028 struct drm_file
*file
)
1030 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1031 struct drm_i915_gem_pwrite
*args
= data
;
1032 struct drm_i915_gem_object
*obj
;
1035 if (args
->size
== 0)
1038 if (!access_ok(VERIFY_READ
,
1039 to_user_ptr(args
->data_ptr
),
1043 if (likely(!i915
.prefault_disable
)) {
1044 ret
= fault_in_multipages_readable(to_user_ptr(args
->data_ptr
),
1050 intel_runtime_pm_get(dev_priv
);
1052 ret
= i915_mutex_lock_interruptible(dev
);
1056 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1057 if (&obj
->base
== NULL
) {
1062 /* Bounds check destination. */
1063 if (args
->offset
> obj
->base
.size
||
1064 args
->size
> obj
->base
.size
- args
->offset
) {
1069 /* prime objects have no backing filp to GEM pread/pwrite
1072 if (!obj
->base
.filp
) {
1077 trace_i915_gem_object_pwrite(obj
, args
->offset
, args
->size
);
1080 /* We can only do the GTT pwrite on untiled buffers, as otherwise
1081 * it would end up going through the fenced access, and we'll get
1082 * different detiling behavior between reading and writing.
1083 * pread/pwrite currently are reading and writing from the CPU
1084 * perspective, requiring manual detiling by the client.
1086 if (obj
->tiling_mode
== I915_TILING_NONE
&&
1087 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
&&
1088 cpu_write_needs_clflush(obj
)) {
1089 ret
= i915_gem_gtt_pwrite_fast(dev
, obj
, args
, file
);
1090 /* Note that the gtt paths might fail with non-page-backed user
1091 * pointers (e.g. gtt mappings when moving data between
1092 * textures). Fallback to the shmem path in that case. */
1095 if (ret
== -EFAULT
|| ret
== -ENOSPC
) {
1096 if (obj
->phys_handle
)
1097 ret
= i915_gem_phys_pwrite(obj
, args
, file
);
1099 ret
= i915_gem_shmem_pwrite(dev
, obj
, args
, file
);
1103 drm_gem_object_unreference(&obj
->base
);
1105 mutex_unlock(&dev
->struct_mutex
);
1107 intel_runtime_pm_put(dev_priv
);
1113 i915_gem_check_wedge(struct i915_gpu_error
*error
,
1116 if (i915_reset_in_progress(error
)) {
1117 /* Non-interruptible callers can't handle -EAGAIN, hence return
1118 * -EIO unconditionally for these. */
1122 /* Recovery complete, but the reset failed ... */
1123 if (i915_terminally_wedged(error
))
1127 * Check if GPU Reset is in progress - we need intel_ring_begin
1128 * to work properly to reinit the hw state while the gpu is
1129 * still marked as reset-in-progress. Handle this with a flag.
1131 if (!error
->reload_in_reset
)
1138 static void fake_irq(unsigned long data
)
1140 wake_up_process((struct task_struct
*)data
);
1143 static bool missed_irq(struct drm_i915_private
*dev_priv
,
1144 struct intel_engine_cs
*engine
)
1146 return test_bit(engine
->id
, &dev_priv
->gpu_error
.missed_irq_rings
);
1149 static unsigned long local_clock_us(unsigned *cpu
)
1153 /* Cheaply and approximately convert from nanoseconds to microseconds.
1154 * The result and subsequent calculations are also defined in the same
1155 * approximate microseconds units. The principal source of timing
1156 * error here is from the simple truncation.
1158 * Note that local_clock() is only defined wrt to the current CPU;
1159 * the comparisons are no longer valid if we switch CPUs. Instead of
1160 * blocking preemption for the entire busywait, we can detect the CPU
1161 * switch and use that as indicator of system load and a reason to
1162 * stop busywaiting, see busywait_stop().
1165 t
= local_clock() >> 10;
1171 static bool busywait_stop(unsigned long timeout
, unsigned cpu
)
1175 if (time_after(local_clock_us(&this_cpu
), timeout
))
1178 return this_cpu
!= cpu
;
1181 static int __i915_spin_request(struct drm_i915_gem_request
*req
, int state
)
1183 unsigned long timeout
;
1186 /* When waiting for high frequency requests, e.g. during synchronous
1187 * rendering split between the CPU and GPU, the finite amount of time
1188 * required to set up the irq and wait upon it limits the response
1189 * rate. By busywaiting on the request completion for a short while we
1190 * can service the high frequency waits as quick as possible. However,
1191 * if it is a slow request, we want to sleep as quickly as possible.
1192 * The tradeoff between waiting and sleeping is roughly the time it
1193 * takes to sleep on a request, on the order of a microsecond.
1196 if (req
->engine
->irq_refcount
)
1199 /* Only spin if we know the GPU is processing this request */
1200 if (!i915_gem_request_started(req
, true))
1203 timeout
= local_clock_us(&cpu
) + 5;
1204 while (!need_resched()) {
1205 if (i915_gem_request_completed(req
, true))
1208 if (signal_pending_state(state
, current
))
1211 if (busywait_stop(timeout
, cpu
))
1214 cpu_relax_lowlatency();
1217 if (i915_gem_request_completed(req
, false))
1224 * __i915_wait_request - wait until execution of request has finished
1226 * @reset_counter: reset sequence associated with the given request
1227 * @interruptible: do an interruptible wait (normally yes)
1228 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
1230 * Note: It is of utmost importance that the passed in seqno and reset_counter
1231 * values have been read by the caller in an smp safe manner. Where read-side
1232 * locks are involved, it is sufficient to read the reset_counter before
1233 * unlocking the lock that protects the seqno. For lockless tricks, the
1234 * reset_counter _must_ be read before, and an appropriate smp_rmb must be
1237 * Returns 0 if the request was found within the alloted time. Else returns the
1238 * errno with remaining time filled in timeout argument.
1240 int __i915_wait_request(struct drm_i915_gem_request
*req
,
1241 unsigned reset_counter
,
1244 struct intel_rps_client
*rps
)
1246 struct intel_engine_cs
*engine
= i915_gem_request_get_engine(req
);
1247 struct drm_device
*dev
= engine
->dev
;
1248 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1249 const bool irq_test_in_progress
=
1250 ACCESS_ONCE(dev_priv
->gpu_error
.test_irq_rings
) & intel_engine_flag(engine
);
1251 int state
= interruptible
? TASK_INTERRUPTIBLE
: TASK_UNINTERRUPTIBLE
;
1253 unsigned long timeout_expire
;
1254 s64 before
= 0; /* Only to silence a compiler warning. */
1257 WARN(!intel_irqs_enabled(dev_priv
), "IRQs disabled");
1259 if (list_empty(&req
->list
))
1262 if (i915_gem_request_completed(req
, true))
1267 if (WARN_ON(*timeout
< 0))
1273 timeout_expire
= jiffies
+ nsecs_to_jiffies_timeout(*timeout
);
1276 * Record current time in case interrupted by signal, or wedged.
1278 before
= ktime_get_raw_ns();
1281 if (INTEL_INFO(dev_priv
)->gen
>= 6)
1282 gen6_rps_boost(dev_priv
, rps
, req
->emitted_jiffies
);
1284 trace_i915_gem_request_wait_begin(req
);
1286 /* Optimistic spin for the next jiffie before touching IRQs */
1287 ret
= __i915_spin_request(req
, state
);
1291 if (!irq_test_in_progress
&& WARN_ON(!engine
->irq_get(engine
))) {
1297 struct timer_list timer
;
1299 prepare_to_wait(&engine
->irq_queue
, &wait
, state
);
1301 /* We need to check whether any gpu reset happened in between
1302 * the caller grabbing the seqno and now ... */
1303 if (reset_counter
!= atomic_read(&dev_priv
->gpu_error
.reset_counter
)) {
1304 /* ... but upgrade the -EAGAIN to an -EIO if the gpu
1305 * is truely gone. */
1306 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, interruptible
);
1312 if (i915_gem_request_completed(req
, false)) {
1317 if (signal_pending_state(state
, current
)) {
1322 if (timeout
&& time_after_eq(jiffies
, timeout_expire
)) {
1327 timer
.function
= NULL
;
1328 if (timeout
|| missed_irq(dev_priv
, engine
)) {
1329 unsigned long expire
;
1331 setup_timer_on_stack(&timer
, fake_irq
, (unsigned long)current
);
1332 expire
= missed_irq(dev_priv
, engine
) ? jiffies
+ 1 : timeout_expire
;
1333 mod_timer(&timer
, expire
);
1338 if (timer
.function
) {
1339 del_singleshot_timer_sync(&timer
);
1340 destroy_timer_on_stack(&timer
);
1343 if (!irq_test_in_progress
)
1344 engine
->irq_put(engine
);
1346 finish_wait(&engine
->irq_queue
, &wait
);
1349 trace_i915_gem_request_wait_end(req
);
1352 s64 tres
= *timeout
- (ktime_get_raw_ns() - before
);
1354 *timeout
= tres
< 0 ? 0 : tres
;
1357 * Apparently ktime isn't accurate enough and occasionally has a
1358 * bit of mismatch in the jiffies<->nsecs<->ktime loop. So patch
1359 * things up to make the test happy. We allow up to 1 jiffy.
1361 * This is a regrssion from the timespec->ktime conversion.
1363 if (ret
== -ETIME
&& *timeout
< jiffies_to_usecs(1)*1000)
1370 int i915_gem_request_add_to_client(struct drm_i915_gem_request
*req
,
1371 struct drm_file
*file
)
1373 struct drm_i915_file_private
*file_priv
;
1375 WARN_ON(!req
|| !file
|| req
->file_priv
);
1383 file_priv
= file
->driver_priv
;
1385 spin_lock(&file_priv
->mm
.lock
);
1386 req
->file_priv
= file_priv
;
1387 list_add_tail(&req
->client_list
, &file_priv
->mm
.request_list
);
1388 spin_unlock(&file_priv
->mm
.lock
);
1390 req
->pid
= get_pid(task_pid(current
));
1396 i915_gem_request_remove_from_client(struct drm_i915_gem_request
*request
)
1398 struct drm_i915_file_private
*file_priv
= request
->file_priv
;
1403 spin_lock(&file_priv
->mm
.lock
);
1404 list_del(&request
->client_list
);
1405 request
->file_priv
= NULL
;
1406 spin_unlock(&file_priv
->mm
.lock
);
1408 put_pid(request
->pid
);
1409 request
->pid
= NULL
;
1412 static void i915_gem_request_retire(struct drm_i915_gem_request
*request
)
1414 trace_i915_gem_request_retire(request
);
1416 /* We know the GPU must have read the request to have
1417 * sent us the seqno + interrupt, so use the position
1418 * of tail of the request to update the last known position
1421 * Note this requires that we are always called in request
1424 request
->ringbuf
->last_retired_head
= request
->postfix
;
1426 list_del_init(&request
->list
);
1427 i915_gem_request_remove_from_client(request
);
1429 i915_gem_request_unreference(request
);
1433 __i915_gem_request_retire__upto(struct drm_i915_gem_request
*req
)
1435 struct intel_engine_cs
*engine
= req
->engine
;
1436 struct drm_i915_gem_request
*tmp
;
1438 lockdep_assert_held(&engine
->dev
->struct_mutex
);
1440 if (list_empty(&req
->list
))
1444 tmp
= list_first_entry(&engine
->request_list
,
1445 typeof(*tmp
), list
);
1447 i915_gem_request_retire(tmp
);
1448 } while (tmp
!= req
);
1450 WARN_ON(i915_verify_lists(engine
->dev
));
1454 * Waits for a request to be signaled, and cleans up the
1455 * request and object lists appropriately for that event.
1458 i915_wait_request(struct drm_i915_gem_request
*req
)
1460 struct drm_device
*dev
;
1461 struct drm_i915_private
*dev_priv
;
1465 BUG_ON(req
== NULL
);
1467 dev
= req
->engine
->dev
;
1468 dev_priv
= dev
->dev_private
;
1469 interruptible
= dev_priv
->mm
.interruptible
;
1471 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
1473 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, interruptible
);
1477 ret
= __i915_wait_request(req
,
1478 atomic_read(&dev_priv
->gpu_error
.reset_counter
),
1479 interruptible
, NULL
, NULL
);
1483 __i915_gem_request_retire__upto(req
);
1488 * Ensures that all rendering to the object has completed and the object is
1489 * safe to unbind from the GTT or access from the CPU.
1492 i915_gem_object_wait_rendering(struct drm_i915_gem_object
*obj
,
1501 if (obj
->last_write_req
!= NULL
) {
1502 ret
= i915_wait_request(obj
->last_write_req
);
1506 i
= obj
->last_write_req
->engine
->id
;
1507 if (obj
->last_read_req
[i
] == obj
->last_write_req
)
1508 i915_gem_object_retire__read(obj
, i
);
1510 i915_gem_object_retire__write(obj
);
1513 for (i
= 0; i
< I915_NUM_ENGINES
; i
++) {
1514 if (obj
->last_read_req
[i
] == NULL
)
1517 ret
= i915_wait_request(obj
->last_read_req
[i
]);
1521 i915_gem_object_retire__read(obj
, i
);
1523 RQ_BUG_ON(obj
->active
);
1530 i915_gem_object_retire_request(struct drm_i915_gem_object
*obj
,
1531 struct drm_i915_gem_request
*req
)
1533 int ring
= req
->engine
->id
;
1535 if (obj
->last_read_req
[ring
] == req
)
1536 i915_gem_object_retire__read(obj
, ring
);
1537 else if (obj
->last_write_req
== req
)
1538 i915_gem_object_retire__write(obj
);
1540 __i915_gem_request_retire__upto(req
);
1543 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1544 * as the object state may change during this call.
1546 static __must_check
int
1547 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object
*obj
,
1548 struct intel_rps_client
*rps
,
1551 struct drm_device
*dev
= obj
->base
.dev
;
1552 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1553 struct drm_i915_gem_request
*requests
[I915_NUM_ENGINES
];
1554 unsigned reset_counter
;
1557 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
1558 BUG_ON(!dev_priv
->mm
.interruptible
);
1563 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, true);
1567 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
1570 struct drm_i915_gem_request
*req
;
1572 req
= obj
->last_write_req
;
1576 requests
[n
++] = i915_gem_request_reference(req
);
1578 for (i
= 0; i
< I915_NUM_ENGINES
; i
++) {
1579 struct drm_i915_gem_request
*req
;
1581 req
= obj
->last_read_req
[i
];
1585 requests
[n
++] = i915_gem_request_reference(req
);
1589 mutex_unlock(&dev
->struct_mutex
);
1590 for (i
= 0; ret
== 0 && i
< n
; i
++)
1591 ret
= __i915_wait_request(requests
[i
], reset_counter
, true,
1593 mutex_lock(&dev
->struct_mutex
);
1595 for (i
= 0; i
< n
; i
++) {
1597 i915_gem_object_retire_request(obj
, requests
[i
]);
1598 i915_gem_request_unreference(requests
[i
]);
1604 static struct intel_rps_client
*to_rps_client(struct drm_file
*file
)
1606 struct drm_i915_file_private
*fpriv
= file
->driver_priv
;
1611 * Called when user space prepares to use an object with the CPU, either
1612 * through the mmap ioctl's mapping or a GTT mapping.
1615 i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
1616 struct drm_file
*file
)
1618 struct drm_i915_gem_set_domain
*args
= data
;
1619 struct drm_i915_gem_object
*obj
;
1620 uint32_t read_domains
= args
->read_domains
;
1621 uint32_t write_domain
= args
->write_domain
;
1624 /* Only handle setting domains to types used by the CPU. */
1625 if (write_domain
& I915_GEM_GPU_DOMAINS
)
1628 if (read_domains
& I915_GEM_GPU_DOMAINS
)
1631 /* Having something in the write domain implies it's in the read
1632 * domain, and only that read domain. Enforce that in the request.
1634 if (write_domain
!= 0 && read_domains
!= write_domain
)
1637 ret
= i915_mutex_lock_interruptible(dev
);
1641 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1642 if (&obj
->base
== NULL
) {
1647 /* Try to flush the object off the GPU without holding the lock.
1648 * We will repeat the flush holding the lock in the normal manner
1649 * to catch cases where we are gazumped.
1651 ret
= i915_gem_object_wait_rendering__nonblocking(obj
,
1652 to_rps_client(file
),
1657 if (read_domains
& I915_GEM_DOMAIN_GTT
)
1658 ret
= i915_gem_object_set_to_gtt_domain(obj
, write_domain
!= 0);
1660 ret
= i915_gem_object_set_to_cpu_domain(obj
, write_domain
!= 0);
1662 if (write_domain
!= 0)
1663 intel_fb_obj_invalidate(obj
,
1664 write_domain
== I915_GEM_DOMAIN_GTT
?
1665 ORIGIN_GTT
: ORIGIN_CPU
);
1668 drm_gem_object_unreference(&obj
->base
);
1670 mutex_unlock(&dev
->struct_mutex
);
1675 * Called when user space has done writes to this buffer
1678 i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1679 struct drm_file
*file
)
1681 struct drm_i915_gem_sw_finish
*args
= data
;
1682 struct drm_i915_gem_object
*obj
;
1685 ret
= i915_mutex_lock_interruptible(dev
);
1689 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1690 if (&obj
->base
== NULL
) {
1695 /* Pinned buffers may be scanout, so flush the cache */
1696 if (obj
->pin_display
)
1697 i915_gem_object_flush_cpu_write_domain(obj
);
1699 drm_gem_object_unreference(&obj
->base
);
1701 mutex_unlock(&dev
->struct_mutex
);
1706 * Maps the contents of an object, returning the address it is mapped
1709 * While the mapping holds a reference on the contents of the object, it doesn't
1710 * imply a ref on the object itself.
1714 * DRM driver writers who look a this function as an example for how to do GEM
1715 * mmap support, please don't implement mmap support like here. The modern way
1716 * to implement DRM mmap support is with an mmap offset ioctl (like
1717 * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly.
1718 * That way debug tooling like valgrind will understand what's going on, hiding
1719 * the mmap call in a driver private ioctl will break that. The i915 driver only
1720 * does cpu mmaps this way because we didn't know better.
1723 i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1724 struct drm_file
*file
)
1726 struct drm_i915_gem_mmap
*args
= data
;
1727 struct drm_gem_object
*obj
;
1730 if (args
->flags
& ~(I915_MMAP_WC
))
1733 if (args
->flags
& I915_MMAP_WC
&& !cpu_has_pat
)
1736 obj
= drm_gem_object_lookup(dev
, file
, args
->handle
);
1740 /* prime objects have no backing filp to GEM mmap
1744 drm_gem_object_unreference_unlocked(obj
);
1748 addr
= vm_mmap(obj
->filp
, 0, args
->size
,
1749 PROT_READ
| PROT_WRITE
, MAP_SHARED
,
1751 if (args
->flags
& I915_MMAP_WC
) {
1752 struct mm_struct
*mm
= current
->mm
;
1753 struct vm_area_struct
*vma
;
1755 down_write(&mm
->mmap_sem
);
1756 vma
= find_vma(mm
, addr
);
1759 pgprot_writecombine(vm_get_page_prot(vma
->vm_flags
));
1762 up_write(&mm
->mmap_sem
);
1764 drm_gem_object_unreference_unlocked(obj
);
1765 if (IS_ERR((void *)addr
))
1768 args
->addr_ptr
= (uint64_t) addr
;
1774 * i915_gem_fault - fault a page into the GTT
1775 * @vma: VMA in question
1778 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1779 * from userspace. The fault handler takes care of binding the object to
1780 * the GTT (if needed), allocating and programming a fence register (again,
1781 * only if needed based on whether the old reg is still valid or the object
1782 * is tiled) and inserting a new PTE into the faulting process.
1784 * Note that the faulting process may involve evicting existing objects
1785 * from the GTT and/or fence registers to make room. So performance may
1786 * suffer if the GTT working set is large or there are few fence registers
1789 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
)
1791 struct drm_i915_gem_object
*obj
= to_intel_bo(vma
->vm_private_data
);
1792 struct drm_device
*dev
= obj
->base
.dev
;
1793 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1794 struct i915_ggtt_view view
= i915_ggtt_view_normal
;
1795 pgoff_t page_offset
;
1798 bool write
= !!(vmf
->flags
& FAULT_FLAG_WRITE
);
1800 intel_runtime_pm_get(dev_priv
);
1802 /* We don't use vmf->pgoff since that has the fake offset */
1803 page_offset
= ((unsigned long)vmf
->virtual_address
- vma
->vm_start
) >>
1806 ret
= i915_mutex_lock_interruptible(dev
);
1810 trace_i915_gem_object_fault(obj
, page_offset
, true, write
);
1812 /* Try to flush the object off the GPU first without holding the lock.
1813 * Upon reacquiring the lock, we will perform our sanity checks and then
1814 * repeat the flush holding the lock in the normal manner to catch cases
1815 * where we are gazumped.
1817 ret
= i915_gem_object_wait_rendering__nonblocking(obj
, NULL
, !write
);
1821 /* Access to snoopable pages through the GTT is incoherent. */
1822 if (obj
->cache_level
!= I915_CACHE_NONE
&& !HAS_LLC(dev
)) {
1827 /* Use a partial view if the object is bigger than the aperture. */
1828 if (obj
->base
.size
>= dev_priv
->ggtt
.mappable_end
&&
1829 obj
->tiling_mode
== I915_TILING_NONE
) {
1830 static const unsigned int chunk_size
= 256; // 1 MiB
1832 memset(&view
, 0, sizeof(view
));
1833 view
.type
= I915_GGTT_VIEW_PARTIAL
;
1834 view
.params
.partial
.offset
= rounddown(page_offset
, chunk_size
);
1835 view
.params
.partial
.size
=
1838 (vma
->vm_end
- vma
->vm_start
)/PAGE_SIZE
-
1839 view
.params
.partial
.offset
);
1842 /* Now pin it into the GTT if needed */
1843 ret
= i915_gem_object_ggtt_pin(obj
, &view
, 0, PIN_MAPPABLE
);
1847 ret
= i915_gem_object_set_to_gtt_domain(obj
, write
);
1851 ret
= i915_gem_object_get_fence(obj
);
1855 /* Finally, remap it using the new GTT offset */
1856 pfn
= dev_priv
->ggtt
.mappable_base
+
1857 i915_gem_obj_ggtt_offset_view(obj
, &view
);
1860 if (unlikely(view
.type
== I915_GGTT_VIEW_PARTIAL
)) {
1861 /* Overriding existing pages in partial view does not cause
1862 * us any trouble as TLBs are still valid because the fault
1863 * is due to userspace losing part of the mapping or never
1864 * having accessed it before (at this partials' range).
1866 unsigned long base
= vma
->vm_start
+
1867 (view
.params
.partial
.offset
<< PAGE_SHIFT
);
1870 for (i
= 0; i
< view
.params
.partial
.size
; i
++) {
1871 ret
= vm_insert_pfn(vma
, base
+ i
* PAGE_SIZE
, pfn
+ i
);
1876 obj
->fault_mappable
= true;
1878 if (!obj
->fault_mappable
) {
1879 unsigned long size
= min_t(unsigned long,
1880 vma
->vm_end
- vma
->vm_start
,
1884 for (i
= 0; i
< size
>> PAGE_SHIFT
; i
++) {
1885 ret
= vm_insert_pfn(vma
,
1886 (unsigned long)vma
->vm_start
+ i
* PAGE_SIZE
,
1892 obj
->fault_mappable
= true;
1894 ret
= vm_insert_pfn(vma
,
1895 (unsigned long)vmf
->virtual_address
,
1899 i915_gem_object_ggtt_unpin_view(obj
, &view
);
1901 mutex_unlock(&dev
->struct_mutex
);
1906 * We eat errors when the gpu is terminally wedged to avoid
1907 * userspace unduly crashing (gl has no provisions for mmaps to
1908 * fail). But any other -EIO isn't ours (e.g. swap in failure)
1909 * and so needs to be reported.
1911 if (!i915_terminally_wedged(&dev_priv
->gpu_error
)) {
1912 ret
= VM_FAULT_SIGBUS
;
1917 * EAGAIN means the gpu is hung and we'll wait for the error
1918 * handler to reset everything when re-faulting in
1919 * i915_mutex_lock_interruptible.
1926 * EBUSY is ok: this just means that another thread
1927 * already did the job.
1929 ret
= VM_FAULT_NOPAGE
;
1936 ret
= VM_FAULT_SIGBUS
;
1939 WARN_ONCE(ret
, "unhandled error in i915_gem_fault: %i\n", ret
);
1940 ret
= VM_FAULT_SIGBUS
;
1944 intel_runtime_pm_put(dev_priv
);
1949 * i915_gem_release_mmap - remove physical page mappings
1950 * @obj: obj in question
1952 * Preserve the reservation of the mmapping with the DRM core code, but
1953 * relinquish ownership of the pages back to the system.
1955 * It is vital that we remove the page mapping if we have mapped a tiled
1956 * object through the GTT and then lose the fence register due to
1957 * resource pressure. Similarly if the object has been moved out of the
1958 * aperture, than pages mapped into userspace must be revoked. Removing the
1959 * mapping will then trigger a page fault on the next user access, allowing
1960 * fixup by i915_gem_fault().
1963 i915_gem_release_mmap(struct drm_i915_gem_object
*obj
)
1965 if (!obj
->fault_mappable
)
1968 drm_vma_node_unmap(&obj
->base
.vma_node
,
1969 obj
->base
.dev
->anon_inode
->i_mapping
);
1970 obj
->fault_mappable
= false;
1974 i915_gem_release_all_mmaps(struct drm_i915_private
*dev_priv
)
1976 struct drm_i915_gem_object
*obj
;
1978 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
)
1979 i915_gem_release_mmap(obj
);
1983 i915_gem_get_gtt_size(struct drm_device
*dev
, uint32_t size
, int tiling_mode
)
1987 if (INTEL_INFO(dev
)->gen
>= 4 ||
1988 tiling_mode
== I915_TILING_NONE
)
1991 /* Previous chips need a power-of-two fence region when tiling */
1992 if (INTEL_INFO(dev
)->gen
== 3)
1993 gtt_size
= 1024*1024;
1995 gtt_size
= 512*1024;
1997 while (gtt_size
< size
)
2004 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
2005 * @obj: object to check
2007 * Return the required GTT alignment for an object, taking into account
2008 * potential fence register mapping.
2011 i915_gem_get_gtt_alignment(struct drm_device
*dev
, uint32_t size
,
2012 int tiling_mode
, bool fenced
)
2015 * Minimum alignment is 4k (GTT page size), but might be greater
2016 * if a fence register is needed for the object.
2018 if (INTEL_INFO(dev
)->gen
>= 4 || (!fenced
&& IS_G33(dev
)) ||
2019 tiling_mode
== I915_TILING_NONE
)
2023 * Previous chips need to be aligned to the size of the smallest
2024 * fence register that can contain the object.
2026 return i915_gem_get_gtt_size(dev
, size
, tiling_mode
);
2029 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object
*obj
)
2031 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2034 if (drm_vma_node_has_offset(&obj
->base
.vma_node
))
2037 dev_priv
->mm
.shrinker_no_lock_stealing
= true;
2039 ret
= drm_gem_create_mmap_offset(&obj
->base
);
2043 /* Badly fragmented mmap space? The only way we can recover
2044 * space is by destroying unwanted objects. We can't randomly release
2045 * mmap_offsets as userspace expects them to be persistent for the
2046 * lifetime of the objects. The closest we can is to release the
2047 * offsets on purgeable objects by truncating it and marking it purged,
2048 * which prevents userspace from ever using that object again.
2050 i915_gem_shrink(dev_priv
,
2051 obj
->base
.size
>> PAGE_SHIFT
,
2053 I915_SHRINK_UNBOUND
|
2054 I915_SHRINK_PURGEABLE
);
2055 ret
= drm_gem_create_mmap_offset(&obj
->base
);
2059 i915_gem_shrink_all(dev_priv
);
2060 ret
= drm_gem_create_mmap_offset(&obj
->base
);
2062 dev_priv
->mm
.shrinker_no_lock_stealing
= false;
2067 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object
*obj
)
2069 drm_gem_free_mmap_offset(&obj
->base
);
2073 i915_gem_mmap_gtt(struct drm_file
*file
,
2074 struct drm_device
*dev
,
2078 struct drm_i915_gem_object
*obj
;
2081 ret
= i915_mutex_lock_interruptible(dev
);
2085 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, handle
));
2086 if (&obj
->base
== NULL
) {
2091 if (obj
->madv
!= I915_MADV_WILLNEED
) {
2092 DRM_DEBUG("Attempting to mmap a purgeable buffer\n");
2097 ret
= i915_gem_object_create_mmap_offset(obj
);
2101 *offset
= drm_vma_node_offset_addr(&obj
->base
.vma_node
);
2104 drm_gem_object_unreference(&obj
->base
);
2106 mutex_unlock(&dev
->struct_mutex
);
2111 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
2113 * @data: GTT mapping ioctl data
2114 * @file: GEM object info
2116 * Simply returns the fake offset to userspace so it can mmap it.
2117 * The mmap call will end up in drm_gem_mmap(), which will set things
2118 * up so we can get faults in the handler above.
2120 * The fault handler will take care of binding the object into the GTT
2121 * (since it may have been evicted to make room for something), allocating
2122 * a fence register, and mapping the appropriate aperture address into
2126 i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
2127 struct drm_file
*file
)
2129 struct drm_i915_gem_mmap_gtt
*args
= data
;
2131 return i915_gem_mmap_gtt(file
, dev
, args
->handle
, &args
->offset
);
2134 /* Immediately discard the backing storage */
2136 i915_gem_object_truncate(struct drm_i915_gem_object
*obj
)
2138 i915_gem_object_free_mmap_offset(obj
);
2140 if (obj
->base
.filp
== NULL
)
2143 /* Our goal here is to return as much of the memory as
2144 * is possible back to the system as we are called from OOM.
2145 * To do this we must instruct the shmfs to drop all of its
2146 * backing pages, *now*.
2148 shmem_truncate_range(file_inode(obj
->base
.filp
), 0, (loff_t
)-1);
2149 obj
->madv
= __I915_MADV_PURGED
;
2152 /* Try to discard unwanted pages */
2154 i915_gem_object_invalidate(struct drm_i915_gem_object
*obj
)
2156 struct address_space
*mapping
;
2158 switch (obj
->madv
) {
2159 case I915_MADV_DONTNEED
:
2160 i915_gem_object_truncate(obj
);
2161 case __I915_MADV_PURGED
:
2165 if (obj
->base
.filp
== NULL
)
2168 mapping
= file_inode(obj
->base
.filp
)->i_mapping
,
2169 invalidate_mapping_pages(mapping
, 0, (loff_t
)-1);
2173 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object
*obj
)
2175 struct sg_page_iter sg_iter
;
2178 BUG_ON(obj
->madv
== __I915_MADV_PURGED
);
2180 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
2182 /* In the event of a disaster, abandon all caches and
2183 * hope for the best.
2185 WARN_ON(ret
!= -EIO
);
2186 i915_gem_clflush_object(obj
, true);
2187 obj
->base
.read_domains
= obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
2190 i915_gem_gtt_finish_object(obj
);
2192 if (i915_gem_object_needs_bit17_swizzle(obj
))
2193 i915_gem_object_save_bit_17_swizzle(obj
);
2195 if (obj
->madv
== I915_MADV_DONTNEED
)
2198 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
, 0) {
2199 struct page
*page
= sg_page_iter_page(&sg_iter
);
2202 set_page_dirty(page
);
2204 if (obj
->madv
== I915_MADV_WILLNEED
)
2205 mark_page_accessed(page
);
2207 page_cache_release(page
);
2211 sg_free_table(obj
->pages
);
2216 i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
)
2218 const struct drm_i915_gem_object_ops
*ops
= obj
->ops
;
2220 if (obj
->pages
== NULL
)
2223 if (obj
->pages_pin_count
)
2226 BUG_ON(i915_gem_obj_bound_any(obj
));
2228 /* ->put_pages might need to allocate memory for the bit17 swizzle
2229 * array, hence protect them from being reaped by removing them from gtt
2231 list_del(&obj
->global_list
);
2233 ops
->put_pages(obj
);
2236 i915_gem_object_invalidate(obj
);
2242 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object
*obj
)
2244 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2246 struct address_space
*mapping
;
2247 struct sg_table
*st
;
2248 struct scatterlist
*sg
;
2249 struct sg_page_iter sg_iter
;
2251 unsigned long last_pfn
= 0; /* suppress gcc warning */
2255 /* Assert that the object is not currently in any GPU domain. As it
2256 * wasn't in the GTT, there shouldn't be any way it could have been in
2259 BUG_ON(obj
->base
.read_domains
& I915_GEM_GPU_DOMAINS
);
2260 BUG_ON(obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
);
2262 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
2266 page_count
= obj
->base
.size
/ PAGE_SIZE
;
2267 if (sg_alloc_table(st
, page_count
, GFP_KERNEL
)) {
2272 /* Get the list of pages out of our struct file. They'll be pinned
2273 * at this point until we release them.
2275 * Fail silently without starting the shrinker
2277 mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
2278 gfp
= mapping_gfp_constraint(mapping
, ~(__GFP_IO
| __GFP_RECLAIM
));
2279 gfp
|= __GFP_NORETRY
| __GFP_NOWARN
;
2282 for (i
= 0; i
< page_count
; i
++) {
2283 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
2285 i915_gem_shrink(dev_priv
,
2288 I915_SHRINK_UNBOUND
|
2289 I915_SHRINK_PURGEABLE
);
2290 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
2293 /* We've tried hard to allocate the memory by reaping
2294 * our own buffer, now let the real VM do its job and
2295 * go down in flames if truly OOM.
2297 i915_gem_shrink_all(dev_priv
);
2298 page
= shmem_read_mapping_page(mapping
, i
);
2300 ret
= PTR_ERR(page
);
2304 #ifdef CONFIG_SWIOTLB
2305 if (swiotlb_nr_tbl()) {
2307 sg_set_page(sg
, page
, PAGE_SIZE
, 0);
2312 if (!i
|| page_to_pfn(page
) != last_pfn
+ 1) {
2316 sg_set_page(sg
, page
, PAGE_SIZE
, 0);
2318 sg
->length
+= PAGE_SIZE
;
2320 last_pfn
= page_to_pfn(page
);
2322 /* Check that the i965g/gm workaround works. */
2323 WARN_ON((gfp
& __GFP_DMA32
) && (last_pfn
>= 0x00100000UL
));
2325 #ifdef CONFIG_SWIOTLB
2326 if (!swiotlb_nr_tbl())
2331 ret
= i915_gem_gtt_prepare_object(obj
);
2335 if (i915_gem_object_needs_bit17_swizzle(obj
))
2336 i915_gem_object_do_bit_17_swizzle(obj
);
2338 if (obj
->tiling_mode
!= I915_TILING_NONE
&&
2339 dev_priv
->quirks
& QUIRK_PIN_SWIZZLED_PAGES
)
2340 i915_gem_object_pin_pages(obj
);
2346 for_each_sg_page(st
->sgl
, &sg_iter
, st
->nents
, 0)
2347 page_cache_release(sg_page_iter_page(&sg_iter
));
2351 /* shmemfs first checks if there is enough memory to allocate the page
2352 * and reports ENOSPC should there be insufficient, along with the usual
2353 * ENOMEM for a genuine allocation failure.
2355 * We use ENOSPC in our driver to mean that we have run out of aperture
2356 * space and so want to translate the error from shmemfs back to our
2357 * usual understanding of ENOMEM.
2365 /* Ensure that the associated pages are gathered from the backing storage
2366 * and pinned into our object. i915_gem_object_get_pages() may be called
2367 * multiple times before they are released by a single call to
2368 * i915_gem_object_put_pages() - once the pages are no longer referenced
2369 * either as a result of memory pressure (reaping pages under the shrinker)
2370 * or as the object is itself released.
2373 i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
)
2375 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2376 const struct drm_i915_gem_object_ops
*ops
= obj
->ops
;
2382 if (obj
->madv
!= I915_MADV_WILLNEED
) {
2383 DRM_DEBUG("Attempting to obtain a purgeable object\n");
2387 BUG_ON(obj
->pages_pin_count
);
2389 ret
= ops
->get_pages(obj
);
2393 list_add_tail(&obj
->global_list
, &dev_priv
->mm
.unbound_list
);
2395 obj
->get_page
.sg
= obj
->pages
->sgl
;
2396 obj
->get_page
.last
= 0;
2401 void i915_vma_move_to_active(struct i915_vma
*vma
,
2402 struct drm_i915_gem_request
*req
)
2404 struct drm_i915_gem_object
*obj
= vma
->obj
;
2405 struct intel_engine_cs
*engine
;
2407 engine
= i915_gem_request_get_engine(req
);
2409 /* Add a reference if we're newly entering the active list. */
2410 if (obj
->active
== 0)
2411 drm_gem_object_reference(&obj
->base
);
2412 obj
->active
|= intel_engine_flag(engine
);
2414 list_move_tail(&obj
->engine_list
[engine
->id
], &engine
->active_list
);
2415 i915_gem_request_assign(&obj
->last_read_req
[engine
->id
], req
);
2417 list_move_tail(&vma
->vm_link
, &vma
->vm
->active_list
);
2421 i915_gem_object_retire__write(struct drm_i915_gem_object
*obj
)
2423 RQ_BUG_ON(obj
->last_write_req
== NULL
);
2424 RQ_BUG_ON(!(obj
->active
& intel_engine_flag(obj
->last_write_req
->engine
)));
2426 i915_gem_request_assign(&obj
->last_write_req
, NULL
);
2427 intel_fb_obj_flush(obj
, true, ORIGIN_CS
);
2431 i915_gem_object_retire__read(struct drm_i915_gem_object
*obj
, int ring
)
2433 struct i915_vma
*vma
;
2435 RQ_BUG_ON(obj
->last_read_req
[ring
] == NULL
);
2436 RQ_BUG_ON(!(obj
->active
& (1 << ring
)));
2438 list_del_init(&obj
->engine_list
[ring
]);
2439 i915_gem_request_assign(&obj
->last_read_req
[ring
], NULL
);
2441 if (obj
->last_write_req
&& obj
->last_write_req
->engine
->id
== ring
)
2442 i915_gem_object_retire__write(obj
);
2444 obj
->active
&= ~(1 << ring
);
2448 /* Bump our place on the bound list to keep it roughly in LRU order
2449 * so that we don't steal from recently used but inactive objects
2450 * (unless we are forced to ofc!)
2452 list_move_tail(&obj
->global_list
,
2453 &to_i915(obj
->base
.dev
)->mm
.bound_list
);
2455 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
) {
2456 if (!list_empty(&vma
->vm_link
))
2457 list_move_tail(&vma
->vm_link
, &vma
->vm
->inactive_list
);
2460 i915_gem_request_assign(&obj
->last_fenced_req
, NULL
);
2461 drm_gem_object_unreference(&obj
->base
);
2465 i915_gem_init_seqno(struct drm_device
*dev
, u32 seqno
)
2467 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2468 struct intel_engine_cs
*engine
;
2471 /* Carefully retire all requests without writing to the rings */
2472 for_each_engine(engine
, dev_priv
) {
2473 ret
= intel_engine_idle(engine
);
2477 i915_gem_retire_requests(dev
);
2479 /* Finally reset hw state */
2480 for_each_engine(engine
, dev_priv
) {
2481 intel_ring_init_seqno(engine
, seqno
);
2483 for (j
= 0; j
< ARRAY_SIZE(engine
->semaphore
.sync_seqno
); j
++)
2484 engine
->semaphore
.sync_seqno
[j
] = 0;
2490 int i915_gem_set_seqno(struct drm_device
*dev
, u32 seqno
)
2492 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2498 /* HWS page needs to be set less than what we
2499 * will inject to ring
2501 ret
= i915_gem_init_seqno(dev
, seqno
- 1);
2505 /* Carefully set the last_seqno value so that wrap
2506 * detection still works
2508 dev_priv
->next_seqno
= seqno
;
2509 dev_priv
->last_seqno
= seqno
- 1;
2510 if (dev_priv
->last_seqno
== 0)
2511 dev_priv
->last_seqno
--;
2517 i915_gem_get_seqno(struct drm_device
*dev
, u32
*seqno
)
2519 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2521 /* reserve 0 for non-seqno */
2522 if (dev_priv
->next_seqno
== 0) {
2523 int ret
= i915_gem_init_seqno(dev
, 0);
2527 dev_priv
->next_seqno
= 1;
2530 *seqno
= dev_priv
->last_seqno
= dev_priv
->next_seqno
++;
2535 * NB: This function is not allowed to fail. Doing so would mean the the
2536 * request is not being tracked for completion but the work itself is
2537 * going to happen on the hardware. This would be a Bad Thing(tm).
2539 void __i915_add_request(struct drm_i915_gem_request
*request
,
2540 struct drm_i915_gem_object
*obj
,
2543 struct intel_engine_cs
*engine
;
2544 struct drm_i915_private
*dev_priv
;
2545 struct intel_ringbuffer
*ringbuf
;
2549 if (WARN_ON(request
== NULL
))
2552 engine
= request
->engine
;
2553 dev_priv
= request
->i915
;
2554 ringbuf
= request
->ringbuf
;
2557 * To ensure that this call will not fail, space for its emissions
2558 * should already have been reserved in the ring buffer. Let the ring
2559 * know that it is time to use that space up.
2561 intel_ring_reserved_space_use(ringbuf
);
2563 request_start
= intel_ring_get_tail(ringbuf
);
2565 * Emit any outstanding flushes - execbuf can fail to emit the flush
2566 * after having emitted the batchbuffer command. Hence we need to fix
2567 * things up similar to emitting the lazy request. The difference here
2568 * is that the flush _must_ happen before the next request, no matter
2572 if (i915
.enable_execlists
)
2573 ret
= logical_ring_flush_all_caches(request
);
2575 ret
= intel_ring_flush_all_caches(request
);
2576 /* Not allowed to fail! */
2577 WARN(ret
, "*_ring_flush_all_caches failed: %d!\n", ret
);
2580 /* Record the position of the start of the request so that
2581 * should we detect the updated seqno part-way through the
2582 * GPU processing the request, we never over-estimate the
2583 * position of the head.
2585 request
->postfix
= intel_ring_get_tail(ringbuf
);
2587 if (i915
.enable_execlists
)
2588 ret
= engine
->emit_request(request
);
2590 ret
= engine
->add_request(request
);
2592 request
->tail
= intel_ring_get_tail(ringbuf
);
2594 /* Not allowed to fail! */
2595 WARN(ret
, "emit|add_request failed: %d!\n", ret
);
2597 request
->head
= request_start
;
2599 /* Whilst this request exists, batch_obj will be on the
2600 * active_list, and so will hold the active reference. Only when this
2601 * request is retired will the the batch_obj be moved onto the
2602 * inactive_list and lose its active reference. Hence we do not need
2603 * to explicitly hold another reference here.
2605 request
->batch_obj
= obj
;
2607 request
->emitted_jiffies
= jiffies
;
2608 request
->previous_seqno
= engine
->last_submitted_seqno
;
2609 engine
->last_submitted_seqno
= request
->seqno
;
2610 list_add_tail(&request
->list
, &engine
->request_list
);
2612 trace_i915_gem_request_add(request
);
2614 i915_queue_hangcheck(engine
->dev
);
2616 queue_delayed_work(dev_priv
->wq
,
2617 &dev_priv
->mm
.retire_work
,
2618 round_jiffies_up_relative(HZ
));
2619 intel_mark_busy(dev_priv
->dev
);
2621 /* Sanity check that the reserved size was large enough. */
2622 intel_ring_reserved_space_end(ringbuf
);
2625 static bool i915_context_is_banned(struct drm_i915_private
*dev_priv
,
2626 const struct intel_context
*ctx
)
2628 unsigned long elapsed
;
2630 elapsed
= get_seconds() - ctx
->hang_stats
.guilty_ts
;
2632 if (ctx
->hang_stats
.banned
)
2635 if (ctx
->hang_stats
.ban_period_seconds
&&
2636 elapsed
<= ctx
->hang_stats
.ban_period_seconds
) {
2637 if (!i915_gem_context_is_default(ctx
)) {
2638 DRM_DEBUG("context hanging too fast, banning!\n");
2640 } else if (i915_stop_ring_allow_ban(dev_priv
)) {
2641 if (i915_stop_ring_allow_warn(dev_priv
))
2642 DRM_ERROR("gpu hanging too fast, banning!\n");
2650 static void i915_set_reset_status(struct drm_i915_private
*dev_priv
,
2651 struct intel_context
*ctx
,
2654 struct i915_ctx_hang_stats
*hs
;
2659 hs
= &ctx
->hang_stats
;
2662 hs
->banned
= i915_context_is_banned(dev_priv
, ctx
);
2664 hs
->guilty_ts
= get_seconds();
2666 hs
->batch_pending
++;
2670 void i915_gem_request_free(struct kref
*req_ref
)
2672 struct drm_i915_gem_request
*req
= container_of(req_ref
,
2674 struct intel_context
*ctx
= req
->ctx
;
2677 i915_gem_request_remove_from_client(req
);
2680 if (i915
.enable_execlists
&& ctx
!= req
->i915
->kernel_context
)
2681 intel_lr_context_unpin(ctx
, req
->engine
);
2683 i915_gem_context_unreference(ctx
);
2686 kmem_cache_free(req
->i915
->requests
, req
);
2690 __i915_gem_request_alloc(struct intel_engine_cs
*engine
,
2691 struct intel_context
*ctx
,
2692 struct drm_i915_gem_request
**req_out
)
2694 struct drm_i915_private
*dev_priv
= to_i915(engine
->dev
);
2695 struct drm_i915_gem_request
*req
;
2703 req
= kmem_cache_zalloc(dev_priv
->requests
, GFP_KERNEL
);
2707 ret
= i915_gem_get_seqno(engine
->dev
, &req
->seqno
);
2711 kref_init(&req
->ref
);
2712 req
->i915
= dev_priv
;
2713 req
->engine
= engine
;
2715 i915_gem_context_reference(req
->ctx
);
2717 if (i915
.enable_execlists
)
2718 ret
= intel_logical_ring_alloc_request_extras(req
);
2720 ret
= intel_ring_alloc_request_extras(req
);
2722 i915_gem_context_unreference(req
->ctx
);
2727 * Reserve space in the ring buffer for all the commands required to
2728 * eventually emit this request. This is to guarantee that the
2729 * i915_add_request() call can't fail. Note that the reserve may need
2730 * to be redone if the request is not actually submitted straight
2731 * away, e.g. because a GPU scheduler has deferred it.
2733 if (i915
.enable_execlists
)
2734 ret
= intel_logical_ring_reserve_space(req
);
2736 ret
= intel_ring_reserve_space(req
);
2739 * At this point, the request is fully allocated even if not
2740 * fully prepared. Thus it can be cleaned up using the proper
2743 i915_gem_request_cancel(req
);
2751 kmem_cache_free(dev_priv
->requests
, req
);
2756 * i915_gem_request_alloc - allocate a request structure
2758 * @engine: engine that we wish to issue the request on.
2759 * @ctx: context that the request will be associated with.
2760 * This can be NULL if the request is not directly related to
2761 * any specific user context, in which case this function will
2762 * choose an appropriate context to use.
2764 * Returns a pointer to the allocated request if successful,
2765 * or an error code if not.
2767 struct drm_i915_gem_request
*
2768 i915_gem_request_alloc(struct intel_engine_cs
*engine
,
2769 struct intel_context
*ctx
)
2771 struct drm_i915_gem_request
*req
;
2775 ctx
= to_i915(engine
->dev
)->kernel_context
;
2776 err
= __i915_gem_request_alloc(engine
, ctx
, &req
);
2777 return err
? ERR_PTR(err
) : req
;
2780 void i915_gem_request_cancel(struct drm_i915_gem_request
*req
)
2782 intel_ring_reserved_space_cancel(req
->ringbuf
);
2784 i915_gem_request_unreference(req
);
2787 struct drm_i915_gem_request
*
2788 i915_gem_find_active_request(struct intel_engine_cs
*engine
)
2790 struct drm_i915_gem_request
*request
;
2792 list_for_each_entry(request
, &engine
->request_list
, list
) {
2793 if (i915_gem_request_completed(request
, false))
2802 static void i915_gem_reset_engine_status(struct drm_i915_private
*dev_priv
,
2803 struct intel_engine_cs
*engine
)
2805 struct drm_i915_gem_request
*request
;
2808 request
= i915_gem_find_active_request(engine
);
2810 if (request
== NULL
)
2813 ring_hung
= engine
->hangcheck
.score
>= HANGCHECK_SCORE_RING_HUNG
;
2815 i915_set_reset_status(dev_priv
, request
->ctx
, ring_hung
);
2817 list_for_each_entry_continue(request
, &engine
->request_list
, list
)
2818 i915_set_reset_status(dev_priv
, request
->ctx
, false);
2821 static void i915_gem_reset_engine_cleanup(struct drm_i915_private
*dev_priv
,
2822 struct intel_engine_cs
*engine
)
2824 struct intel_ringbuffer
*buffer
;
2826 while (!list_empty(&engine
->active_list
)) {
2827 struct drm_i915_gem_object
*obj
;
2829 obj
= list_first_entry(&engine
->active_list
,
2830 struct drm_i915_gem_object
,
2831 engine_list
[engine
->id
]);
2833 i915_gem_object_retire__read(obj
, engine
->id
);
2837 * Clear the execlists queue up before freeing the requests, as those
2838 * are the ones that keep the context and ringbuffer backing objects
2842 if (i915
.enable_execlists
) {
2843 spin_lock_irq(&engine
->execlist_lock
);
2845 /* list_splice_tail_init checks for empty lists */
2846 list_splice_tail_init(&engine
->execlist_queue
,
2847 &engine
->execlist_retired_req_list
);
2849 spin_unlock_irq(&engine
->execlist_lock
);
2850 intel_execlists_retire_requests(engine
);
2854 * We must free the requests after all the corresponding objects have
2855 * been moved off active lists. Which is the same order as the normal
2856 * retire_requests function does. This is important if object hold
2857 * implicit references on things like e.g. ppgtt address spaces through
2860 while (!list_empty(&engine
->request_list
)) {
2861 struct drm_i915_gem_request
*request
;
2863 request
= list_first_entry(&engine
->request_list
,
2864 struct drm_i915_gem_request
,
2867 i915_gem_request_retire(request
);
2870 /* Having flushed all requests from all queues, we know that all
2871 * ringbuffers must now be empty. However, since we do not reclaim
2872 * all space when retiring the request (to prevent HEADs colliding
2873 * with rapid ringbuffer wraparound) the amount of available space
2874 * upon reset is less than when we start. Do one more pass over
2875 * all the ringbuffers to reset last_retired_head.
2877 list_for_each_entry(buffer
, &engine
->buffers
, link
) {
2878 buffer
->last_retired_head
= buffer
->tail
;
2879 intel_ring_update_space(buffer
);
2883 void i915_gem_reset(struct drm_device
*dev
)
2885 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2886 struct intel_engine_cs
*engine
;
2889 * Before we free the objects from the requests, we need to inspect
2890 * them for finding the guilty party. As the requests only borrow
2891 * their reference to the objects, the inspection must be done first.
2893 for_each_engine(engine
, dev_priv
)
2894 i915_gem_reset_engine_status(dev_priv
, engine
);
2896 for_each_engine(engine
, dev_priv
)
2897 i915_gem_reset_engine_cleanup(dev_priv
, engine
);
2899 i915_gem_context_reset(dev
);
2901 i915_gem_restore_fences(dev
);
2903 WARN_ON(i915_verify_lists(dev
));
2907 * This function clears the request list as sequence numbers are passed.
2910 i915_gem_retire_requests_ring(struct intel_engine_cs
*engine
)
2912 WARN_ON(i915_verify_lists(engine
->dev
));
2914 /* Retire requests first as we use it above for the early return.
2915 * If we retire requests last, we may use a later seqno and so clear
2916 * the requests lists without clearing the active list, leading to
2919 while (!list_empty(&engine
->request_list
)) {
2920 struct drm_i915_gem_request
*request
;
2922 request
= list_first_entry(&engine
->request_list
,
2923 struct drm_i915_gem_request
,
2926 if (!i915_gem_request_completed(request
, true))
2929 i915_gem_request_retire(request
);
2932 /* Move any buffers on the active list that are no longer referenced
2933 * by the ringbuffer to the flushing/inactive lists as appropriate,
2934 * before we free the context associated with the requests.
2936 while (!list_empty(&engine
->active_list
)) {
2937 struct drm_i915_gem_object
*obj
;
2939 obj
= list_first_entry(&engine
->active_list
,
2940 struct drm_i915_gem_object
,
2941 engine_list
[engine
->id
]);
2943 if (!list_empty(&obj
->last_read_req
[engine
->id
]->list
))
2946 i915_gem_object_retire__read(obj
, engine
->id
);
2949 if (unlikely(engine
->trace_irq_req
&&
2950 i915_gem_request_completed(engine
->trace_irq_req
, true))) {
2951 engine
->irq_put(engine
);
2952 i915_gem_request_assign(&engine
->trace_irq_req
, NULL
);
2955 WARN_ON(i915_verify_lists(engine
->dev
));
2959 i915_gem_retire_requests(struct drm_device
*dev
)
2961 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2962 struct intel_engine_cs
*engine
;
2965 for_each_engine(engine
, dev_priv
) {
2966 i915_gem_retire_requests_ring(engine
);
2967 idle
&= list_empty(&engine
->request_list
);
2968 if (i915
.enable_execlists
) {
2969 spin_lock_irq(&engine
->execlist_lock
);
2970 idle
&= list_empty(&engine
->execlist_queue
);
2971 spin_unlock_irq(&engine
->execlist_lock
);
2973 intel_execlists_retire_requests(engine
);
2978 mod_delayed_work(dev_priv
->wq
,
2979 &dev_priv
->mm
.idle_work
,
2980 msecs_to_jiffies(100));
2986 i915_gem_retire_work_handler(struct work_struct
*work
)
2988 struct drm_i915_private
*dev_priv
=
2989 container_of(work
, typeof(*dev_priv
), mm
.retire_work
.work
);
2990 struct drm_device
*dev
= dev_priv
->dev
;
2993 /* Come back later if the device is busy... */
2995 if (mutex_trylock(&dev
->struct_mutex
)) {
2996 idle
= i915_gem_retire_requests(dev
);
2997 mutex_unlock(&dev
->struct_mutex
);
3000 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
,
3001 round_jiffies_up_relative(HZ
));
3005 i915_gem_idle_work_handler(struct work_struct
*work
)
3007 struct drm_i915_private
*dev_priv
=
3008 container_of(work
, typeof(*dev_priv
), mm
.idle_work
.work
);
3009 struct drm_device
*dev
= dev_priv
->dev
;
3010 struct intel_engine_cs
*engine
;
3012 for_each_engine(engine
, dev_priv
)
3013 if (!list_empty(&engine
->request_list
))
3016 /* we probably should sync with hangcheck here, using cancel_work_sync.
3017 * Also locking seems to be fubar here, engine->request_list is protected
3018 * by dev->struct_mutex. */
3020 intel_mark_idle(dev
);
3022 if (mutex_trylock(&dev
->struct_mutex
)) {
3023 for_each_engine(engine
, dev_priv
)
3024 i915_gem_batch_pool_fini(&engine
->batch_pool
);
3026 mutex_unlock(&dev
->struct_mutex
);
3031 * Ensures that an object will eventually get non-busy by flushing any required
3032 * write domains, emitting any outstanding lazy request and retiring and
3033 * completed requests.
3036 i915_gem_object_flush_active(struct drm_i915_gem_object
*obj
)
3043 for (i
= 0; i
< I915_NUM_ENGINES
; i
++) {
3044 struct drm_i915_gem_request
*req
;
3046 req
= obj
->last_read_req
[i
];
3050 if (list_empty(&req
->list
))
3053 if (i915_gem_request_completed(req
, true)) {
3054 __i915_gem_request_retire__upto(req
);
3056 i915_gem_object_retire__read(obj
, i
);
3064 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
3065 * @DRM_IOCTL_ARGS: standard ioctl arguments
3067 * Returns 0 if successful, else an error is returned with the remaining time in
3068 * the timeout parameter.
3069 * -ETIME: object is still busy after timeout
3070 * -ERESTARTSYS: signal interrupted the wait
3071 * -ENONENT: object doesn't exist
3072 * Also possible, but rare:
3073 * -EAGAIN: GPU wedged
3075 * -ENODEV: Internal IRQ fail
3076 * -E?: The add request failed
3078 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
3079 * non-zero timeout parameter the wait ioctl will wait for the given number of
3080 * nanoseconds on an object becoming unbusy. Since the wait itself does so
3081 * without holding struct_mutex the object may become re-busied before this
3082 * function completes. A similar but shorter * race condition exists in the busy
3086 i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
, struct drm_file
*file
)
3088 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3089 struct drm_i915_gem_wait
*args
= data
;
3090 struct drm_i915_gem_object
*obj
;
3091 struct drm_i915_gem_request
*req
[I915_NUM_ENGINES
];
3092 unsigned reset_counter
;
3096 if (args
->flags
!= 0)
3099 ret
= i915_mutex_lock_interruptible(dev
);
3103 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->bo_handle
));
3104 if (&obj
->base
== NULL
) {
3105 mutex_unlock(&dev
->struct_mutex
);
3109 /* Need to make sure the object gets inactive eventually. */
3110 ret
= i915_gem_object_flush_active(obj
);
3117 /* Do this after OLR check to make sure we make forward progress polling
3118 * on this IOCTL with a timeout == 0 (like busy ioctl)
3120 if (args
->timeout_ns
== 0) {
3125 drm_gem_object_unreference(&obj
->base
);
3126 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
3128 for (i
= 0; i
< I915_NUM_ENGINES
; i
++) {
3129 if (obj
->last_read_req
[i
] == NULL
)
3132 req
[n
++] = i915_gem_request_reference(obj
->last_read_req
[i
]);
3135 mutex_unlock(&dev
->struct_mutex
);
3137 for (i
= 0; i
< n
; i
++) {
3139 ret
= __i915_wait_request(req
[i
], reset_counter
, true,
3140 args
->timeout_ns
> 0 ? &args
->timeout_ns
: NULL
,
3141 to_rps_client(file
));
3142 i915_gem_request_unreference__unlocked(req
[i
]);
3147 drm_gem_object_unreference(&obj
->base
);
3148 mutex_unlock(&dev
->struct_mutex
);
3153 __i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
3154 struct intel_engine_cs
*to
,
3155 struct drm_i915_gem_request
*from_req
,
3156 struct drm_i915_gem_request
**to_req
)
3158 struct intel_engine_cs
*from
;
3161 from
= i915_gem_request_get_engine(from_req
);
3165 if (i915_gem_request_completed(from_req
, true))
3168 if (!i915_semaphore_is_enabled(obj
->base
.dev
)) {
3169 struct drm_i915_private
*i915
= to_i915(obj
->base
.dev
);
3170 ret
= __i915_wait_request(from_req
,
3171 atomic_read(&i915
->gpu_error
.reset_counter
),
3172 i915
->mm
.interruptible
,
3174 &i915
->rps
.semaphores
);
3178 i915_gem_object_retire_request(obj
, from_req
);
3180 int idx
= intel_ring_sync_index(from
, to
);
3181 u32 seqno
= i915_gem_request_get_seqno(from_req
);
3185 if (seqno
<= from
->semaphore
.sync_seqno
[idx
])
3188 if (*to_req
== NULL
) {
3189 struct drm_i915_gem_request
*req
;
3191 req
= i915_gem_request_alloc(to
, NULL
);
3193 return PTR_ERR(req
);
3198 trace_i915_gem_ring_sync_to(*to_req
, from
, from_req
);
3199 ret
= to
->semaphore
.sync_to(*to_req
, from
, seqno
);
3203 /* We use last_read_req because sync_to()
3204 * might have just caused seqno wrap under
3207 from
->semaphore
.sync_seqno
[idx
] =
3208 i915_gem_request_get_seqno(obj
->last_read_req
[from
->id
]);
3215 * i915_gem_object_sync - sync an object to a ring.
3217 * @obj: object which may be in use on another ring.
3218 * @to: ring we wish to use the object on. May be NULL.
3219 * @to_req: request we wish to use the object for. See below.
3220 * This will be allocated and returned if a request is
3221 * required but not passed in.
3223 * This code is meant to abstract object synchronization with the GPU.
3224 * Calling with NULL implies synchronizing the object with the CPU
3225 * rather than a particular GPU ring. Conceptually we serialise writes
3226 * between engines inside the GPU. We only allow one engine to write
3227 * into a buffer at any time, but multiple readers. To ensure each has
3228 * a coherent view of memory, we must:
3230 * - If there is an outstanding write request to the object, the new
3231 * request must wait for it to complete (either CPU or in hw, requests
3232 * on the same ring will be naturally ordered).
3234 * - If we are a write request (pending_write_domain is set), the new
3235 * request must wait for outstanding read requests to complete.
3237 * For CPU synchronisation (NULL to) no request is required. For syncing with
3238 * rings to_req must be non-NULL. However, a request does not have to be
3239 * pre-allocated. If *to_req is NULL and sync commands will be emitted then a
3240 * request will be allocated automatically and returned through *to_req. Note
3241 * that it is not guaranteed that commands will be emitted (because the system
3242 * might already be idle). Hence there is no need to create a request that
3243 * might never have any work submitted. Note further that if a request is
3244 * returned in *to_req, it is the responsibility of the caller to submit
3245 * that request (after potentially adding more work to it).
3247 * Returns 0 if successful, else propagates up the lower layer error.
3250 i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
3251 struct intel_engine_cs
*to
,
3252 struct drm_i915_gem_request
**to_req
)
3254 const bool readonly
= obj
->base
.pending_write_domain
== 0;
3255 struct drm_i915_gem_request
*req
[I915_NUM_ENGINES
];
3262 return i915_gem_object_wait_rendering(obj
, readonly
);
3266 if (obj
->last_write_req
)
3267 req
[n
++] = obj
->last_write_req
;
3269 for (i
= 0; i
< I915_NUM_ENGINES
; i
++)
3270 if (obj
->last_read_req
[i
])
3271 req
[n
++] = obj
->last_read_req
[i
];
3273 for (i
= 0; i
< n
; i
++) {
3274 ret
= __i915_gem_object_sync(obj
, to
, req
[i
], to_req
);
3282 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object
*obj
)
3284 u32 old_write_domain
, old_read_domains
;
3286 /* Force a pagefault for domain tracking on next user access */
3287 i915_gem_release_mmap(obj
);
3289 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
) == 0)
3292 /* Wait for any direct GTT access to complete */
3295 old_read_domains
= obj
->base
.read_domains
;
3296 old_write_domain
= obj
->base
.write_domain
;
3298 obj
->base
.read_domains
&= ~I915_GEM_DOMAIN_GTT
;
3299 obj
->base
.write_domain
&= ~I915_GEM_DOMAIN_GTT
;
3301 trace_i915_gem_object_change_domain(obj
,
3306 static int __i915_vma_unbind(struct i915_vma
*vma
, bool wait
)
3308 struct drm_i915_gem_object
*obj
= vma
->obj
;
3309 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
3312 if (list_empty(&vma
->obj_link
))
3315 if (!drm_mm_node_allocated(&vma
->node
)) {
3316 i915_gem_vma_destroy(vma
);
3323 BUG_ON(obj
->pages
== NULL
);
3326 ret
= i915_gem_object_wait_rendering(obj
, false);
3331 if (vma
->is_ggtt
&& vma
->ggtt_view
.type
== I915_GGTT_VIEW_NORMAL
) {
3332 i915_gem_object_finish_gtt(obj
);
3334 /* release the fence reg _after_ flushing */
3335 ret
= i915_gem_object_put_fence(obj
);
3340 trace_i915_vma_unbind(vma
);
3342 vma
->vm
->unbind_vma(vma
);
3345 list_del_init(&vma
->vm_link
);
3347 if (vma
->ggtt_view
.type
== I915_GGTT_VIEW_NORMAL
) {
3348 obj
->map_and_fenceable
= false;
3349 } else if (vma
->ggtt_view
.pages
) {
3350 sg_free_table(vma
->ggtt_view
.pages
);
3351 kfree(vma
->ggtt_view
.pages
);
3353 vma
->ggtt_view
.pages
= NULL
;
3356 drm_mm_remove_node(&vma
->node
);
3357 i915_gem_vma_destroy(vma
);
3359 /* Since the unbound list is global, only move to that list if
3360 * no more VMAs exist. */
3361 if (list_empty(&obj
->vma_list
))
3362 list_move_tail(&obj
->global_list
, &dev_priv
->mm
.unbound_list
);
3364 /* And finally now the object is completely decoupled from this vma,
3365 * we can drop its hold on the backing storage and allow it to be
3366 * reaped by the shrinker.
3368 i915_gem_object_unpin_pages(obj
);
3373 int i915_vma_unbind(struct i915_vma
*vma
)
3375 return __i915_vma_unbind(vma
, true);
3378 int __i915_vma_unbind_no_wait(struct i915_vma
*vma
)
3380 return __i915_vma_unbind(vma
, false);
3383 int i915_gpu_idle(struct drm_device
*dev
)
3385 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3386 struct intel_engine_cs
*engine
;
3389 /* Flush everything onto the inactive list. */
3390 for_each_engine(engine
, dev_priv
) {
3391 if (!i915
.enable_execlists
) {
3392 struct drm_i915_gem_request
*req
;
3394 req
= i915_gem_request_alloc(engine
, NULL
);
3396 return PTR_ERR(req
);
3398 ret
= i915_switch_context(req
);
3400 i915_gem_request_cancel(req
);
3404 i915_add_request_no_flush(req
);
3407 ret
= intel_engine_idle(engine
);
3412 WARN_ON(i915_verify_lists(dev
));
3416 static bool i915_gem_valid_gtt_space(struct i915_vma
*vma
,
3417 unsigned long cache_level
)
3419 struct drm_mm_node
*gtt_space
= &vma
->node
;
3420 struct drm_mm_node
*other
;
3423 * On some machines we have to be careful when putting differing types
3424 * of snoopable memory together to avoid the prefetcher crossing memory
3425 * domains and dying. During vm initialisation, we decide whether or not
3426 * these constraints apply and set the drm_mm.color_adjust
3429 if (vma
->vm
->mm
.color_adjust
== NULL
)
3432 if (!drm_mm_node_allocated(gtt_space
))
3435 if (list_empty(>t_space
->node_list
))
3438 other
= list_entry(gtt_space
->node_list
.prev
, struct drm_mm_node
, node_list
);
3439 if (other
->allocated
&& !other
->hole_follows
&& other
->color
!= cache_level
)
3442 other
= list_entry(gtt_space
->node_list
.next
, struct drm_mm_node
, node_list
);
3443 if (other
->allocated
&& !gtt_space
->hole_follows
&& other
->color
!= cache_level
)
3450 * Finds free space in the GTT aperture and binds the object or a view of it
3453 static struct i915_vma
*
3454 i915_gem_object_bind_to_vm(struct drm_i915_gem_object
*obj
,
3455 struct i915_address_space
*vm
,
3456 const struct i915_ggtt_view
*ggtt_view
,
3460 struct drm_device
*dev
= obj
->base
.dev
;
3461 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3462 u32 fence_alignment
, unfenced_alignment
;
3463 u32 search_flag
, alloc_flag
;
3465 u64 size
, fence_size
;
3466 struct i915_vma
*vma
;
3469 if (i915_is_ggtt(vm
)) {
3472 if (WARN_ON(!ggtt_view
))
3473 return ERR_PTR(-EINVAL
);
3475 view_size
= i915_ggtt_view_size(obj
, ggtt_view
);
3477 fence_size
= i915_gem_get_gtt_size(dev
,
3480 fence_alignment
= i915_gem_get_gtt_alignment(dev
,
3484 unfenced_alignment
= i915_gem_get_gtt_alignment(dev
,
3488 size
= flags
& PIN_MAPPABLE
? fence_size
: view_size
;
3490 fence_size
= i915_gem_get_gtt_size(dev
,
3493 fence_alignment
= i915_gem_get_gtt_alignment(dev
,
3497 unfenced_alignment
=
3498 i915_gem_get_gtt_alignment(dev
,
3502 size
= flags
& PIN_MAPPABLE
? fence_size
: obj
->base
.size
;
3505 start
= flags
& PIN_OFFSET_BIAS
? flags
& PIN_OFFSET_MASK
: 0;
3507 if (flags
& PIN_MAPPABLE
)
3508 end
= min_t(u64
, end
, dev_priv
->ggtt
.mappable_end
);
3509 if (flags
& PIN_ZONE_4G
)
3510 end
= min_t(u64
, end
, (1ULL << 32) - PAGE_SIZE
);
3513 alignment
= flags
& PIN_MAPPABLE
? fence_alignment
:
3515 if (flags
& PIN_MAPPABLE
&& alignment
& (fence_alignment
- 1)) {
3516 DRM_DEBUG("Invalid object (view type=%u) alignment requested %u\n",
3517 ggtt_view
? ggtt_view
->type
: 0,
3519 return ERR_PTR(-EINVAL
);
3522 /* If binding the object/GGTT view requires more space than the entire
3523 * aperture has, reject it early before evicting everything in a vain
3524 * attempt to find space.
3527 DRM_DEBUG("Attempting to bind an object (view type=%u) larger than the aperture: size=%llu > %s aperture=%llu\n",
3528 ggtt_view
? ggtt_view
->type
: 0,
3530 flags
& PIN_MAPPABLE
? "mappable" : "total",
3532 return ERR_PTR(-E2BIG
);
3535 ret
= i915_gem_object_get_pages(obj
);
3537 return ERR_PTR(ret
);
3539 i915_gem_object_pin_pages(obj
);
3541 vma
= ggtt_view
? i915_gem_obj_lookup_or_create_ggtt_vma(obj
, ggtt_view
) :
3542 i915_gem_obj_lookup_or_create_vma(obj
, vm
);
3547 if (flags
& PIN_OFFSET_FIXED
) {
3548 uint64_t offset
= flags
& PIN_OFFSET_MASK
;
3550 if (offset
& (alignment
- 1) || offset
+ size
> end
) {
3554 vma
->node
.start
= offset
;
3555 vma
->node
.size
= size
;
3556 vma
->node
.color
= obj
->cache_level
;
3557 ret
= drm_mm_reserve_node(&vm
->mm
, &vma
->node
);
3559 ret
= i915_gem_evict_for_vma(vma
);
3561 ret
= drm_mm_reserve_node(&vm
->mm
, &vma
->node
);
3566 if (flags
& PIN_HIGH
) {
3567 search_flag
= DRM_MM_SEARCH_BELOW
;
3568 alloc_flag
= DRM_MM_CREATE_TOP
;
3570 search_flag
= DRM_MM_SEARCH_DEFAULT
;
3571 alloc_flag
= DRM_MM_CREATE_DEFAULT
;
3575 ret
= drm_mm_insert_node_in_range_generic(&vm
->mm
, &vma
->node
,
3582 ret
= i915_gem_evict_something(dev
, vm
, size
, alignment
,
3592 if (WARN_ON(!i915_gem_valid_gtt_space(vma
, obj
->cache_level
))) {
3594 goto err_remove_node
;
3597 trace_i915_vma_bind(vma
, flags
);
3598 ret
= i915_vma_bind(vma
, obj
->cache_level
, flags
);
3600 goto err_remove_node
;
3602 list_move_tail(&obj
->global_list
, &dev_priv
->mm
.bound_list
);
3603 list_add_tail(&vma
->vm_link
, &vm
->inactive_list
);
3608 drm_mm_remove_node(&vma
->node
);
3610 i915_gem_vma_destroy(vma
);
3613 i915_gem_object_unpin_pages(obj
);
3618 i915_gem_clflush_object(struct drm_i915_gem_object
*obj
,
3621 /* If we don't have a page list set up, then we're not pinned
3622 * to GPU, and we can ignore the cache flush because it'll happen
3623 * again at bind time.
3625 if (obj
->pages
== NULL
)
3629 * Stolen memory is always coherent with the GPU as it is explicitly
3630 * marked as wc by the system, or the system is cache-coherent.
3632 if (obj
->stolen
|| obj
->phys_handle
)
3635 /* If the GPU is snooping the contents of the CPU cache,
3636 * we do not need to manually clear the CPU cache lines. However,
3637 * the caches are only snooped when the render cache is
3638 * flushed/invalidated. As we always have to emit invalidations
3639 * and flushes when moving into and out of the RENDER domain, correct
3640 * snooping behaviour occurs naturally as the result of our domain
3643 if (!force
&& cpu_cache_is_coherent(obj
->base
.dev
, obj
->cache_level
)) {
3644 obj
->cache_dirty
= true;
3648 trace_i915_gem_object_clflush(obj
);
3649 drm_clflush_sg(obj
->pages
);
3650 obj
->cache_dirty
= false;
3655 /** Flushes the GTT write domain for the object if it's dirty. */
3657 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
)
3659 uint32_t old_write_domain
;
3661 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_GTT
)
3664 /* No actual flushing is required for the GTT write domain. Writes
3665 * to it immediately go to main memory as far as we know, so there's
3666 * no chipset flush. It also doesn't land in render cache.
3668 * However, we do have to enforce the order so that all writes through
3669 * the GTT land before any writes to the device, such as updates to
3674 old_write_domain
= obj
->base
.write_domain
;
3675 obj
->base
.write_domain
= 0;
3677 intel_fb_obj_flush(obj
, false, ORIGIN_GTT
);
3679 trace_i915_gem_object_change_domain(obj
,
3680 obj
->base
.read_domains
,
3684 /** Flushes the CPU write domain for the object if it's dirty. */
3686 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
)
3688 uint32_t old_write_domain
;
3690 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
)
3693 if (i915_gem_clflush_object(obj
, obj
->pin_display
))
3694 i915_gem_chipset_flush(obj
->base
.dev
);
3696 old_write_domain
= obj
->base
.write_domain
;
3697 obj
->base
.write_domain
= 0;
3699 intel_fb_obj_flush(obj
, false, ORIGIN_CPU
);
3701 trace_i915_gem_object_change_domain(obj
,
3702 obj
->base
.read_domains
,
3707 * Moves a single object to the GTT read, and possibly write domain.
3709 * This function returns when the move is complete, including waiting on
3713 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
, bool write
)
3715 uint32_t old_write_domain
, old_read_domains
;
3716 struct i915_vma
*vma
;
3719 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_GTT
)
3722 ret
= i915_gem_object_wait_rendering(obj
, !write
);
3726 /* Flush and acquire obj->pages so that we are coherent through
3727 * direct access in memory with previous cached writes through
3728 * shmemfs and that our cache domain tracking remains valid.
3729 * For example, if the obj->filp was moved to swap without us
3730 * being notified and releasing the pages, we would mistakenly
3731 * continue to assume that the obj remained out of the CPU cached
3734 ret
= i915_gem_object_get_pages(obj
);
3738 i915_gem_object_flush_cpu_write_domain(obj
);
3740 /* Serialise direct access to this object with the barriers for
3741 * coherent writes from the GPU, by effectively invalidating the
3742 * GTT domain upon first access.
3744 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
) == 0)
3747 old_write_domain
= obj
->base
.write_domain
;
3748 old_read_domains
= obj
->base
.read_domains
;
3750 /* It should now be out of any other write domains, and we can update
3751 * the domain values for our changes.
3753 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
3754 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
3756 obj
->base
.read_domains
= I915_GEM_DOMAIN_GTT
;
3757 obj
->base
.write_domain
= I915_GEM_DOMAIN_GTT
;
3761 trace_i915_gem_object_change_domain(obj
,
3765 /* And bump the LRU for this access */
3766 vma
= i915_gem_obj_to_ggtt(obj
);
3767 if (vma
&& drm_mm_node_allocated(&vma
->node
) && !obj
->active
)
3768 list_move_tail(&vma
->vm_link
,
3769 &to_i915(obj
->base
.dev
)->ggtt
.base
.inactive_list
);
3775 * Changes the cache-level of an object across all VMA.
3777 * After this function returns, the object will be in the new cache-level
3778 * across all GTT and the contents of the backing storage will be coherent,
3779 * with respect to the new cache-level. In order to keep the backing storage
3780 * coherent for all users, we only allow a single cache level to be set
3781 * globally on the object and prevent it from being changed whilst the
3782 * hardware is reading from the object. That is if the object is currently
3783 * on the scanout it will be set to uncached (or equivalent display
3784 * cache coherency) and all non-MOCS GPU access will also be uncached so
3785 * that all direct access to the scanout remains coherent.
3787 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
3788 enum i915_cache_level cache_level
)
3790 struct drm_device
*dev
= obj
->base
.dev
;
3791 struct i915_vma
*vma
, *next
;
3795 if (obj
->cache_level
== cache_level
)
3798 /* Inspect the list of currently bound VMA and unbind any that would
3799 * be invalid given the new cache-level. This is principally to
3800 * catch the issue of the CS prefetch crossing page boundaries and
3801 * reading an invalid PTE on older architectures.
3803 list_for_each_entry_safe(vma
, next
, &obj
->vma_list
, obj_link
) {
3804 if (!drm_mm_node_allocated(&vma
->node
))
3807 if (vma
->pin_count
) {
3808 DRM_DEBUG("can not change the cache level of pinned objects\n");
3812 if (!i915_gem_valid_gtt_space(vma
, cache_level
)) {
3813 ret
= i915_vma_unbind(vma
);
3820 /* We can reuse the existing drm_mm nodes but need to change the
3821 * cache-level on the PTE. We could simply unbind them all and
3822 * rebind with the correct cache-level on next use. However since
3823 * we already have a valid slot, dma mapping, pages etc, we may as
3824 * rewrite the PTE in the belief that doing so tramples upon less
3825 * state and so involves less work.
3828 /* Before we change the PTE, the GPU must not be accessing it.
3829 * If we wait upon the object, we know that all the bound
3830 * VMA are no longer active.
3832 ret
= i915_gem_object_wait_rendering(obj
, false);
3836 if (!HAS_LLC(dev
) && cache_level
!= I915_CACHE_NONE
) {
3837 /* Access to snoopable pages through the GTT is
3838 * incoherent and on some machines causes a hard
3839 * lockup. Relinquish the CPU mmaping to force
3840 * userspace to refault in the pages and we can
3841 * then double check if the GTT mapping is still
3842 * valid for that pointer access.
3844 i915_gem_release_mmap(obj
);
3846 /* As we no longer need a fence for GTT access,
3847 * we can relinquish it now (and so prevent having
3848 * to steal a fence from someone else on the next
3849 * fence request). Note GPU activity would have
3850 * dropped the fence as all snoopable access is
3851 * supposed to be linear.
3853 ret
= i915_gem_object_put_fence(obj
);
3857 /* We either have incoherent backing store and
3858 * so no GTT access or the architecture is fully
3859 * coherent. In such cases, existing GTT mmaps
3860 * ignore the cache bit in the PTE and we can
3861 * rewrite it without confusing the GPU or having
3862 * to force userspace to fault back in its mmaps.
3866 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
) {
3867 if (!drm_mm_node_allocated(&vma
->node
))
3870 ret
= i915_vma_bind(vma
, cache_level
, PIN_UPDATE
);
3876 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
)
3877 vma
->node
.color
= cache_level
;
3878 obj
->cache_level
= cache_level
;
3881 /* Flush the dirty CPU caches to the backing storage so that the
3882 * object is now coherent at its new cache level (with respect
3883 * to the access domain).
3885 if (obj
->cache_dirty
&&
3886 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
&&
3887 cpu_write_needs_clflush(obj
)) {
3888 if (i915_gem_clflush_object(obj
, true))
3889 i915_gem_chipset_flush(obj
->base
.dev
);
3895 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
3896 struct drm_file
*file
)
3898 struct drm_i915_gem_caching
*args
= data
;
3899 struct drm_i915_gem_object
*obj
;
3901 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3902 if (&obj
->base
== NULL
)
3905 switch (obj
->cache_level
) {
3906 case I915_CACHE_LLC
:
3907 case I915_CACHE_L3_LLC
:
3908 args
->caching
= I915_CACHING_CACHED
;
3912 args
->caching
= I915_CACHING_DISPLAY
;
3916 args
->caching
= I915_CACHING_NONE
;
3920 drm_gem_object_unreference_unlocked(&obj
->base
);
3924 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
3925 struct drm_file
*file
)
3927 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3928 struct drm_i915_gem_caching
*args
= data
;
3929 struct drm_i915_gem_object
*obj
;
3930 enum i915_cache_level level
;
3933 switch (args
->caching
) {
3934 case I915_CACHING_NONE
:
3935 level
= I915_CACHE_NONE
;
3937 case I915_CACHING_CACHED
:
3939 * Due to a HW issue on BXT A stepping, GPU stores via a
3940 * snooped mapping may leave stale data in a corresponding CPU
3941 * cacheline, whereas normally such cachelines would get
3944 if (!HAS_LLC(dev
) && !HAS_SNOOP(dev
))
3947 level
= I915_CACHE_LLC
;
3949 case I915_CACHING_DISPLAY
:
3950 level
= HAS_WT(dev
) ? I915_CACHE_WT
: I915_CACHE_NONE
;
3956 intel_runtime_pm_get(dev_priv
);
3958 ret
= i915_mutex_lock_interruptible(dev
);
3962 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3963 if (&obj
->base
== NULL
) {
3968 ret
= i915_gem_object_set_cache_level(obj
, level
);
3970 drm_gem_object_unreference(&obj
->base
);
3972 mutex_unlock(&dev
->struct_mutex
);
3974 intel_runtime_pm_put(dev_priv
);
3980 * Prepare buffer for display plane (scanout, cursors, etc).
3981 * Can be called from an uninterruptible phase (modesetting) and allows
3982 * any flushes to be pipelined (for pageflips).
3985 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
3987 const struct i915_ggtt_view
*view
)
3989 u32 old_read_domains
, old_write_domain
;
3992 /* Mark the pin_display early so that we account for the
3993 * display coherency whilst setting up the cache domains.
3997 /* The display engine is not coherent with the LLC cache on gen6. As
3998 * a result, we make sure that the pinning that is about to occur is
3999 * done with uncached PTEs. This is lowest common denominator for all
4002 * However for gen6+, we could do better by using the GFDT bit instead
4003 * of uncaching, which would allow us to flush all the LLC-cached data
4004 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
4006 ret
= i915_gem_object_set_cache_level(obj
,
4007 HAS_WT(obj
->base
.dev
) ? I915_CACHE_WT
: I915_CACHE_NONE
);
4009 goto err_unpin_display
;
4011 /* As the user may map the buffer once pinned in the display plane
4012 * (e.g. libkms for the bootup splash), we have to ensure that we
4013 * always use map_and_fenceable for all scanout buffers.
4015 ret
= i915_gem_object_ggtt_pin(obj
, view
, alignment
,
4016 view
->type
== I915_GGTT_VIEW_NORMAL
?
4019 goto err_unpin_display
;
4021 i915_gem_object_flush_cpu_write_domain(obj
);
4023 old_write_domain
= obj
->base
.write_domain
;
4024 old_read_domains
= obj
->base
.read_domains
;
4026 /* It should now be out of any other write domains, and we can update
4027 * the domain values for our changes.
4029 obj
->base
.write_domain
= 0;
4030 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
4032 trace_i915_gem_object_change_domain(obj
,
4044 i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object
*obj
,
4045 const struct i915_ggtt_view
*view
)
4047 if (WARN_ON(obj
->pin_display
== 0))
4050 i915_gem_object_ggtt_unpin_view(obj
, view
);
4056 * Moves a single object to the CPU read, and possibly write domain.
4058 * This function returns when the move is complete, including waiting on
4062 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
)
4064 uint32_t old_write_domain
, old_read_domains
;
4067 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_CPU
)
4070 ret
= i915_gem_object_wait_rendering(obj
, !write
);
4074 i915_gem_object_flush_gtt_write_domain(obj
);
4076 old_write_domain
= obj
->base
.write_domain
;
4077 old_read_domains
= obj
->base
.read_domains
;
4079 /* Flush the CPU cache if it's still invalid. */
4080 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) == 0) {
4081 i915_gem_clflush_object(obj
, false);
4083 obj
->base
.read_domains
|= I915_GEM_DOMAIN_CPU
;
4086 /* It should now be out of any other write domains, and we can update
4087 * the domain values for our changes.
4089 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
4091 /* If we're writing through the CPU, then the GPU read domains will
4092 * need to be invalidated at next use.
4095 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
4096 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
4099 trace_i915_gem_object_change_domain(obj
,
4106 /* Throttle our rendering by waiting until the ring has completed our requests
4107 * emitted over 20 msec ago.
4109 * Note that if we were to use the current jiffies each time around the loop,
4110 * we wouldn't escape the function with any frames outstanding if the time to
4111 * render a frame was over 20ms.
4113 * This should get us reasonable parallelism between CPU and GPU but also
4114 * relatively low latency when blocking on a particular request to finish.
4117 i915_gem_ring_throttle(struct drm_device
*dev
, struct drm_file
*file
)
4119 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4120 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
4121 unsigned long recent_enough
= jiffies
- DRM_I915_THROTTLE_JIFFIES
;
4122 struct drm_i915_gem_request
*request
, *target
= NULL
;
4123 unsigned reset_counter
;
4126 ret
= i915_gem_wait_for_error(&dev_priv
->gpu_error
);
4130 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, false);
4134 spin_lock(&file_priv
->mm
.lock
);
4135 list_for_each_entry(request
, &file_priv
->mm
.request_list
, client_list
) {
4136 if (time_after_eq(request
->emitted_jiffies
, recent_enough
))
4140 * Note that the request might not have been submitted yet.
4141 * In which case emitted_jiffies will be zero.
4143 if (!request
->emitted_jiffies
)
4148 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
4150 i915_gem_request_reference(target
);
4151 spin_unlock(&file_priv
->mm
.lock
);
4156 ret
= __i915_wait_request(target
, reset_counter
, true, NULL
, NULL
);
4158 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, 0);
4160 i915_gem_request_unreference__unlocked(target
);
4166 i915_vma_misplaced(struct i915_vma
*vma
, uint32_t alignment
, uint64_t flags
)
4168 struct drm_i915_gem_object
*obj
= vma
->obj
;
4171 vma
->node
.start
& (alignment
- 1))
4174 if (flags
& PIN_MAPPABLE
&& !obj
->map_and_fenceable
)
4177 if (flags
& PIN_OFFSET_BIAS
&&
4178 vma
->node
.start
< (flags
& PIN_OFFSET_MASK
))
4181 if (flags
& PIN_OFFSET_FIXED
&&
4182 vma
->node
.start
!= (flags
& PIN_OFFSET_MASK
))
4188 void __i915_vma_set_map_and_fenceable(struct i915_vma
*vma
)
4190 struct drm_i915_gem_object
*obj
= vma
->obj
;
4191 bool mappable
, fenceable
;
4192 u32 fence_size
, fence_alignment
;
4194 fence_size
= i915_gem_get_gtt_size(obj
->base
.dev
,
4197 fence_alignment
= i915_gem_get_gtt_alignment(obj
->base
.dev
,
4202 fenceable
= (vma
->node
.size
== fence_size
&&
4203 (vma
->node
.start
& (fence_alignment
- 1)) == 0);
4205 mappable
= (vma
->node
.start
+ fence_size
<=
4206 to_i915(obj
->base
.dev
)->ggtt
.mappable_end
);
4208 obj
->map_and_fenceable
= mappable
&& fenceable
;
4212 i915_gem_object_do_pin(struct drm_i915_gem_object
*obj
,
4213 struct i915_address_space
*vm
,
4214 const struct i915_ggtt_view
*ggtt_view
,
4218 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
4219 struct i915_vma
*vma
;
4223 if (WARN_ON(vm
== &dev_priv
->mm
.aliasing_ppgtt
->base
))
4226 if (WARN_ON(flags
& (PIN_GLOBAL
| PIN_MAPPABLE
) && !i915_is_ggtt(vm
)))
4229 if (WARN_ON((flags
& (PIN_MAPPABLE
| PIN_GLOBAL
)) == PIN_MAPPABLE
))
4232 if (WARN_ON(i915_is_ggtt(vm
) != !!ggtt_view
))
4235 vma
= ggtt_view
? i915_gem_obj_to_ggtt_view(obj
, ggtt_view
) :
4236 i915_gem_obj_to_vma(obj
, vm
);
4239 if (WARN_ON(vma
->pin_count
== DRM_I915_GEM_OBJECT_MAX_PIN_COUNT
))
4242 if (i915_vma_misplaced(vma
, alignment
, flags
)) {
4243 WARN(vma
->pin_count
,
4244 "bo is already pinned in %s with incorrect alignment:"
4245 " offset=%08x %08x, req.alignment=%x, req.map_and_fenceable=%d,"
4246 " obj->map_and_fenceable=%d\n",
4247 ggtt_view
? "ggtt" : "ppgtt",
4248 upper_32_bits(vma
->node
.start
),
4249 lower_32_bits(vma
->node
.start
),
4251 !!(flags
& PIN_MAPPABLE
),
4252 obj
->map_and_fenceable
);
4253 ret
= i915_vma_unbind(vma
);
4261 bound
= vma
? vma
->bound
: 0;
4262 if (vma
== NULL
|| !drm_mm_node_allocated(&vma
->node
)) {
4263 vma
= i915_gem_object_bind_to_vm(obj
, vm
, ggtt_view
, alignment
,
4266 return PTR_ERR(vma
);
4268 ret
= i915_vma_bind(vma
, obj
->cache_level
, flags
);
4273 if (ggtt_view
&& ggtt_view
->type
== I915_GGTT_VIEW_NORMAL
&&
4274 (bound
^ vma
->bound
) & GLOBAL_BIND
) {
4275 __i915_vma_set_map_and_fenceable(vma
);
4276 WARN_ON(flags
& PIN_MAPPABLE
&& !obj
->map_and_fenceable
);
4284 i915_gem_object_pin(struct drm_i915_gem_object
*obj
,
4285 struct i915_address_space
*vm
,
4289 return i915_gem_object_do_pin(obj
, vm
,
4290 i915_is_ggtt(vm
) ? &i915_ggtt_view_normal
: NULL
,
4295 i915_gem_object_ggtt_pin(struct drm_i915_gem_object
*obj
,
4296 const struct i915_ggtt_view
*view
,
4302 return i915_gem_object_do_pin(obj
, i915_obj_to_ggtt(obj
), view
,
4303 alignment
, flags
| PIN_GLOBAL
);
4307 i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object
*obj
,
4308 const struct i915_ggtt_view
*view
)
4310 struct i915_vma
*vma
= i915_gem_obj_to_ggtt_view(obj
, view
);
4313 WARN_ON(vma
->pin_count
== 0);
4314 WARN_ON(!i915_gem_obj_ggtt_bound_view(obj
, view
));
4320 i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
4321 struct drm_file
*file
)
4323 struct drm_i915_gem_busy
*args
= data
;
4324 struct drm_i915_gem_object
*obj
;
4327 ret
= i915_mutex_lock_interruptible(dev
);
4331 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
4332 if (&obj
->base
== NULL
) {
4337 /* Count all active objects as busy, even if they are currently not used
4338 * by the gpu. Users of this interface expect objects to eventually
4339 * become non-busy without any further actions, therefore emit any
4340 * necessary flushes here.
4342 ret
= i915_gem_object_flush_active(obj
);
4350 for (i
= 0; i
< I915_NUM_ENGINES
; i
++) {
4351 struct drm_i915_gem_request
*req
;
4353 req
= obj
->last_read_req
[i
];
4355 args
->busy
|= 1 << (16 + req
->engine
->exec_id
);
4357 if (obj
->last_write_req
)
4358 args
->busy
|= obj
->last_write_req
->engine
->exec_id
;
4362 drm_gem_object_unreference(&obj
->base
);
4364 mutex_unlock(&dev
->struct_mutex
);
4369 i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
4370 struct drm_file
*file_priv
)
4372 return i915_gem_ring_throttle(dev
, file_priv
);
4376 i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
4377 struct drm_file
*file_priv
)
4379 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4380 struct drm_i915_gem_madvise
*args
= data
;
4381 struct drm_i915_gem_object
*obj
;
4384 switch (args
->madv
) {
4385 case I915_MADV_DONTNEED
:
4386 case I915_MADV_WILLNEED
:
4392 ret
= i915_mutex_lock_interruptible(dev
);
4396 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file_priv
, args
->handle
));
4397 if (&obj
->base
== NULL
) {
4402 if (i915_gem_obj_is_pinned(obj
)) {
4408 obj
->tiling_mode
!= I915_TILING_NONE
&&
4409 dev_priv
->quirks
& QUIRK_PIN_SWIZZLED_PAGES
) {
4410 if (obj
->madv
== I915_MADV_WILLNEED
)
4411 i915_gem_object_unpin_pages(obj
);
4412 if (args
->madv
== I915_MADV_WILLNEED
)
4413 i915_gem_object_pin_pages(obj
);
4416 if (obj
->madv
!= __I915_MADV_PURGED
)
4417 obj
->madv
= args
->madv
;
4419 /* if the object is no longer attached, discard its backing storage */
4420 if (obj
->madv
== I915_MADV_DONTNEED
&& obj
->pages
== NULL
)
4421 i915_gem_object_truncate(obj
);
4423 args
->retained
= obj
->madv
!= __I915_MADV_PURGED
;
4426 drm_gem_object_unreference(&obj
->base
);
4428 mutex_unlock(&dev
->struct_mutex
);
4432 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
4433 const struct drm_i915_gem_object_ops
*ops
)
4437 INIT_LIST_HEAD(&obj
->global_list
);
4438 for (i
= 0; i
< I915_NUM_ENGINES
; i
++)
4439 INIT_LIST_HEAD(&obj
->engine_list
[i
]);
4440 INIT_LIST_HEAD(&obj
->obj_exec_link
);
4441 INIT_LIST_HEAD(&obj
->vma_list
);
4442 INIT_LIST_HEAD(&obj
->batch_pool_link
);
4446 obj
->fence_reg
= I915_FENCE_REG_NONE
;
4447 obj
->madv
= I915_MADV_WILLNEED
;
4449 i915_gem_info_add_obj(obj
->base
.dev
->dev_private
, obj
->base
.size
);
4452 static const struct drm_i915_gem_object_ops i915_gem_object_ops
= {
4453 .flags
= I915_GEM_OBJECT_HAS_STRUCT_PAGE
,
4454 .get_pages
= i915_gem_object_get_pages_gtt
,
4455 .put_pages
= i915_gem_object_put_pages_gtt
,
4458 struct drm_i915_gem_object
*i915_gem_alloc_object(struct drm_device
*dev
,
4461 struct drm_i915_gem_object
*obj
;
4462 struct address_space
*mapping
;
4465 obj
= i915_gem_object_alloc(dev
);
4469 if (drm_gem_object_init(dev
, &obj
->base
, size
) != 0) {
4470 i915_gem_object_free(obj
);
4474 mask
= GFP_HIGHUSER
| __GFP_RECLAIMABLE
;
4475 if (IS_CRESTLINE(dev
) || IS_BROADWATER(dev
)) {
4476 /* 965gm cannot relocate objects above 4GiB. */
4477 mask
&= ~__GFP_HIGHMEM
;
4478 mask
|= __GFP_DMA32
;
4481 mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
4482 mapping_set_gfp_mask(mapping
, mask
);
4484 i915_gem_object_init(obj
, &i915_gem_object_ops
);
4486 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
4487 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
4490 /* On some devices, we can have the GPU use the LLC (the CPU
4491 * cache) for about a 10% performance improvement
4492 * compared to uncached. Graphics requests other than
4493 * display scanout are coherent with the CPU in
4494 * accessing this cache. This means in this mode we
4495 * don't need to clflush on the CPU side, and on the
4496 * GPU side we only need to flush internal caches to
4497 * get data visible to the CPU.
4499 * However, we maintain the display planes as UC, and so
4500 * need to rebind when first used as such.
4502 obj
->cache_level
= I915_CACHE_LLC
;
4504 obj
->cache_level
= I915_CACHE_NONE
;
4506 trace_i915_gem_object_create(obj
);
4511 static bool discard_backing_storage(struct drm_i915_gem_object
*obj
)
4513 /* If we are the last user of the backing storage (be it shmemfs
4514 * pages or stolen etc), we know that the pages are going to be
4515 * immediately released. In this case, we can then skip copying
4516 * back the contents from the GPU.
4519 if (obj
->madv
!= I915_MADV_WILLNEED
)
4522 if (obj
->base
.filp
== NULL
)
4525 /* At first glance, this looks racy, but then again so would be
4526 * userspace racing mmap against close. However, the first external
4527 * reference to the filp can only be obtained through the
4528 * i915_gem_mmap_ioctl() which safeguards us against the user
4529 * acquiring such a reference whilst we are in the middle of
4530 * freeing the object.
4532 return atomic_long_read(&obj
->base
.filp
->f_count
) == 1;
4535 void i915_gem_free_object(struct drm_gem_object
*gem_obj
)
4537 struct drm_i915_gem_object
*obj
= to_intel_bo(gem_obj
);
4538 struct drm_device
*dev
= obj
->base
.dev
;
4539 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4540 struct i915_vma
*vma
, *next
;
4542 intel_runtime_pm_get(dev_priv
);
4544 trace_i915_gem_object_destroy(obj
);
4546 list_for_each_entry_safe(vma
, next
, &obj
->vma_list
, obj_link
) {
4550 ret
= i915_vma_unbind(vma
);
4551 if (WARN_ON(ret
== -ERESTARTSYS
)) {
4552 bool was_interruptible
;
4554 was_interruptible
= dev_priv
->mm
.interruptible
;
4555 dev_priv
->mm
.interruptible
= false;
4557 WARN_ON(i915_vma_unbind(vma
));
4559 dev_priv
->mm
.interruptible
= was_interruptible
;
4563 /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
4564 * before progressing. */
4566 i915_gem_object_unpin_pages(obj
);
4568 WARN_ON(obj
->frontbuffer_bits
);
4570 if (obj
->pages
&& obj
->madv
== I915_MADV_WILLNEED
&&
4571 dev_priv
->quirks
& QUIRK_PIN_SWIZZLED_PAGES
&&
4572 obj
->tiling_mode
!= I915_TILING_NONE
)
4573 i915_gem_object_unpin_pages(obj
);
4575 if (WARN_ON(obj
->pages_pin_count
))
4576 obj
->pages_pin_count
= 0;
4577 if (discard_backing_storage(obj
))
4578 obj
->madv
= I915_MADV_DONTNEED
;
4579 i915_gem_object_put_pages(obj
);
4580 i915_gem_object_free_mmap_offset(obj
);
4584 if (obj
->base
.import_attach
)
4585 drm_prime_gem_destroy(&obj
->base
, NULL
);
4587 if (obj
->ops
->release
)
4588 obj
->ops
->release(obj
);
4590 drm_gem_object_release(&obj
->base
);
4591 i915_gem_info_remove_obj(dev_priv
, obj
->base
.size
);
4594 i915_gem_object_free(obj
);
4596 intel_runtime_pm_put(dev_priv
);
4599 struct i915_vma
*i915_gem_obj_to_vma(struct drm_i915_gem_object
*obj
,
4600 struct i915_address_space
*vm
)
4602 struct i915_vma
*vma
;
4603 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
) {
4604 if (vma
->ggtt_view
.type
== I915_GGTT_VIEW_NORMAL
&&
4611 struct i915_vma
*i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object
*obj
,
4612 const struct i915_ggtt_view
*view
)
4614 struct i915_address_space
*ggtt
= i915_obj_to_ggtt(obj
);
4615 struct i915_vma
*vma
;
4619 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
)
4620 if (vma
->vm
== ggtt
&&
4621 i915_ggtt_view_equal(&vma
->ggtt_view
, view
))
4626 void i915_gem_vma_destroy(struct i915_vma
*vma
)
4628 WARN_ON(vma
->node
.allocated
);
4630 /* Keep the vma as a placeholder in the execbuffer reservation lists */
4631 if (!list_empty(&vma
->exec_list
))
4635 i915_ppgtt_put(i915_vm_to_ppgtt(vma
->vm
));
4637 list_del(&vma
->obj_link
);
4639 kmem_cache_free(to_i915(vma
->obj
->base
.dev
)->vmas
, vma
);
4643 i915_gem_stop_engines(struct drm_device
*dev
)
4645 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4646 struct intel_engine_cs
*engine
;
4648 for_each_engine(engine
, dev_priv
)
4649 dev_priv
->gt
.stop_engine(engine
);
4653 i915_gem_suspend(struct drm_device
*dev
)
4655 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4658 mutex_lock(&dev
->struct_mutex
);
4659 ret
= i915_gpu_idle(dev
);
4663 i915_gem_retire_requests(dev
);
4665 i915_gem_stop_engines(dev
);
4666 mutex_unlock(&dev
->struct_mutex
);
4668 cancel_delayed_work_sync(&dev_priv
->gpu_error
.hangcheck_work
);
4669 cancel_delayed_work_sync(&dev_priv
->mm
.retire_work
);
4670 flush_delayed_work(&dev_priv
->mm
.idle_work
);
4672 /* Assert that we sucessfully flushed all the work and
4673 * reset the GPU back to its idle, low power state.
4675 WARN_ON(dev_priv
->mm
.busy
);
4680 mutex_unlock(&dev
->struct_mutex
);
4684 int i915_gem_l3_remap(struct drm_i915_gem_request
*req
, int slice
)
4686 struct intel_engine_cs
*engine
= req
->engine
;
4687 struct drm_device
*dev
= engine
->dev
;
4688 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4689 u32
*remap_info
= dev_priv
->l3_parity
.remap_info
[slice
];
4692 if (!HAS_L3_DPF(dev
) || !remap_info
)
4695 ret
= intel_ring_begin(req
, GEN7_L3LOG_SIZE
/ 4 * 3);
4700 * Note: We do not worry about the concurrent register cacheline hang
4701 * here because no other code should access these registers other than
4702 * at initialization time.
4704 for (i
= 0; i
< GEN7_L3LOG_SIZE
/ 4; i
++) {
4705 intel_ring_emit(engine
, MI_LOAD_REGISTER_IMM(1));
4706 intel_ring_emit_reg(engine
, GEN7_L3LOG(slice
, i
));
4707 intel_ring_emit(engine
, remap_info
[i
]);
4710 intel_ring_advance(engine
);
4715 void i915_gem_init_swizzling(struct drm_device
*dev
)
4717 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4719 if (INTEL_INFO(dev
)->gen
< 5 ||
4720 dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_NONE
)
4723 I915_WRITE(DISP_ARB_CTL
, I915_READ(DISP_ARB_CTL
) |
4724 DISP_TILE_SURFACE_SWIZZLING
);
4729 I915_WRITE(TILECTL
, I915_READ(TILECTL
) | TILECTL_SWZCTL
);
4731 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB
));
4732 else if (IS_GEN7(dev
))
4733 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB
));
4734 else if (IS_GEN8(dev
))
4735 I915_WRITE(GAMTARBMODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW
));
4740 static void init_unused_ring(struct drm_device
*dev
, u32 base
)
4742 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4744 I915_WRITE(RING_CTL(base
), 0);
4745 I915_WRITE(RING_HEAD(base
), 0);
4746 I915_WRITE(RING_TAIL(base
), 0);
4747 I915_WRITE(RING_START(base
), 0);
4750 static void init_unused_rings(struct drm_device
*dev
)
4753 init_unused_ring(dev
, PRB1_BASE
);
4754 init_unused_ring(dev
, SRB0_BASE
);
4755 init_unused_ring(dev
, SRB1_BASE
);
4756 init_unused_ring(dev
, SRB2_BASE
);
4757 init_unused_ring(dev
, SRB3_BASE
);
4758 } else if (IS_GEN2(dev
)) {
4759 init_unused_ring(dev
, SRB0_BASE
);
4760 init_unused_ring(dev
, SRB1_BASE
);
4761 } else if (IS_GEN3(dev
)) {
4762 init_unused_ring(dev
, PRB1_BASE
);
4763 init_unused_ring(dev
, PRB2_BASE
);
4767 int i915_gem_init_engines(struct drm_device
*dev
)
4769 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4772 ret
= intel_init_render_ring_buffer(dev
);
4777 ret
= intel_init_bsd_ring_buffer(dev
);
4779 goto cleanup_render_ring
;
4783 ret
= intel_init_blt_ring_buffer(dev
);
4785 goto cleanup_bsd_ring
;
4788 if (HAS_VEBOX(dev
)) {
4789 ret
= intel_init_vebox_ring_buffer(dev
);
4791 goto cleanup_blt_ring
;
4794 if (HAS_BSD2(dev
)) {
4795 ret
= intel_init_bsd2_ring_buffer(dev
);
4797 goto cleanup_vebox_ring
;
4803 intel_cleanup_engine(&dev_priv
->engine
[VECS
]);
4805 intel_cleanup_engine(&dev_priv
->engine
[BCS
]);
4807 intel_cleanup_engine(&dev_priv
->engine
[VCS
]);
4808 cleanup_render_ring
:
4809 intel_cleanup_engine(&dev_priv
->engine
[RCS
]);
4815 i915_gem_init_hw(struct drm_device
*dev
)
4817 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4818 struct intel_engine_cs
*engine
;
4821 if (INTEL_INFO(dev
)->gen
< 6 && !intel_enable_gtt())
4824 /* Double layer security blanket, see i915_gem_init() */
4825 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
4827 if (dev_priv
->ellc_size
)
4828 I915_WRITE(HSW_IDICR
, I915_READ(HSW_IDICR
) | IDIHASHMSK(0xf));
4830 if (IS_HASWELL(dev
))
4831 I915_WRITE(MI_PREDICATE_RESULT_2
, IS_HSW_GT3(dev
) ?
4832 LOWER_SLICE_ENABLED
: LOWER_SLICE_DISABLED
);
4834 if (HAS_PCH_NOP(dev
)) {
4835 if (IS_IVYBRIDGE(dev
)) {
4836 u32 temp
= I915_READ(GEN7_MSG_CTL
);
4837 temp
&= ~(WAIT_FOR_PCH_FLR_ACK
| WAIT_FOR_PCH_RESET_ACK
);
4838 I915_WRITE(GEN7_MSG_CTL
, temp
);
4839 } else if (INTEL_INFO(dev
)->gen
>= 7) {
4840 u32 temp
= I915_READ(HSW_NDE_RSTWRN_OPT
);
4841 temp
&= ~RESET_PCH_HANDSHAKE_ENABLE
;
4842 I915_WRITE(HSW_NDE_RSTWRN_OPT
, temp
);
4846 i915_gem_init_swizzling(dev
);
4849 * At least 830 can leave some of the unused rings
4850 * "active" (ie. head != tail) after resume which
4851 * will prevent c3 entry. Makes sure all unused rings
4854 init_unused_rings(dev
);
4856 BUG_ON(!dev_priv
->kernel_context
);
4858 ret
= i915_ppgtt_init_hw(dev
);
4860 DRM_ERROR("PPGTT enable HW failed %d\n", ret
);
4864 /* Need to do basic initialisation of all rings first: */
4865 for_each_engine(engine
, dev_priv
) {
4866 ret
= engine
->init_hw(engine
);
4871 /* We can't enable contexts until all firmware is loaded */
4872 if (HAS_GUC_UCODE(dev
)) {
4873 ret
= intel_guc_ucode_load(dev
);
4875 DRM_ERROR("Failed to initialize GuC, error %d\n", ret
);
4882 * Increment the next seqno by 0x100 so we have a visible break
4883 * on re-initialisation
4885 ret
= i915_gem_set_seqno(dev
, dev_priv
->next_seqno
+0x100);
4889 /* Now it is safe to go back round and do everything else: */
4890 for_each_engine(engine
, dev_priv
) {
4891 struct drm_i915_gem_request
*req
;
4893 req
= i915_gem_request_alloc(engine
, NULL
);
4896 i915_gem_cleanup_engines(dev
);
4900 if (engine
->id
== RCS
) {
4901 for (j
= 0; j
< NUM_L3_SLICES(dev
); j
++)
4902 i915_gem_l3_remap(req
, j
);
4905 ret
= i915_ppgtt_init_ring(req
);
4906 if (ret
&& ret
!= -EIO
) {
4907 DRM_ERROR("PPGTT enable %s failed %d\n",
4909 i915_gem_request_cancel(req
);
4910 i915_gem_cleanup_engines(dev
);
4914 ret
= i915_gem_context_enable(req
);
4915 if (ret
&& ret
!= -EIO
) {
4916 DRM_ERROR("Context enable %s failed %d\n",
4918 i915_gem_request_cancel(req
);
4919 i915_gem_cleanup_engines(dev
);
4923 i915_add_request_no_flush(req
);
4927 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
4931 int i915_gem_init(struct drm_device
*dev
)
4933 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4936 i915
.enable_execlists
= intel_sanitize_enable_execlists(dev
,
4937 i915
.enable_execlists
);
4939 mutex_lock(&dev
->struct_mutex
);
4941 if (!i915
.enable_execlists
) {
4942 dev_priv
->gt
.execbuf_submit
= i915_gem_ringbuffer_submission
;
4943 dev_priv
->gt
.init_engines
= i915_gem_init_engines
;
4944 dev_priv
->gt
.cleanup_engine
= intel_cleanup_engine
;
4945 dev_priv
->gt
.stop_engine
= intel_stop_engine
;
4947 dev_priv
->gt
.execbuf_submit
= intel_execlists_submission
;
4948 dev_priv
->gt
.init_engines
= intel_logical_rings_init
;
4949 dev_priv
->gt
.cleanup_engine
= intel_logical_ring_cleanup
;
4950 dev_priv
->gt
.stop_engine
= intel_logical_ring_stop
;
4953 /* This is just a security blanket to placate dragons.
4954 * On some systems, we very sporadically observe that the first TLBs
4955 * used by the CS may be stale, despite us poking the TLB reset. If
4956 * we hold the forcewake during initialisation these problems
4957 * just magically go away.
4959 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
4961 ret
= i915_gem_init_userptr(dev
);
4965 i915_gem_init_ggtt(dev
);
4967 ret
= i915_gem_context_init(dev
);
4971 ret
= dev_priv
->gt
.init_engines(dev
);
4975 ret
= i915_gem_init_hw(dev
);
4977 /* Allow ring initialisation to fail by marking the GPU as
4978 * wedged. But we only want to do this where the GPU is angry,
4979 * for all other failure, such as an allocation failure, bail.
4981 DRM_ERROR("Failed to initialize GPU, declaring it wedged\n");
4982 atomic_or(I915_WEDGED
, &dev_priv
->gpu_error
.reset_counter
);
4987 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
4988 mutex_unlock(&dev
->struct_mutex
);
4994 i915_gem_cleanup_engines(struct drm_device
*dev
)
4996 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4997 struct intel_engine_cs
*engine
;
4999 for_each_engine(engine
, dev_priv
)
5000 dev_priv
->gt
.cleanup_engine(engine
);
5002 if (i915
.enable_execlists
)
5004 * Neither the BIOS, ourselves or any other kernel
5005 * expects the system to be in execlists mode on startup,
5006 * so we need to reset the GPU back to legacy mode.
5008 intel_gpu_reset(dev
, ALL_ENGINES
);
5012 init_engine_lists(struct intel_engine_cs
*engine
)
5014 INIT_LIST_HEAD(&engine
->active_list
);
5015 INIT_LIST_HEAD(&engine
->request_list
);
5019 i915_gem_load_init_fences(struct drm_i915_private
*dev_priv
)
5021 struct drm_device
*dev
= dev_priv
->dev
;
5023 if (INTEL_INFO(dev_priv
)->gen
>= 7 && !IS_VALLEYVIEW(dev_priv
) &&
5024 !IS_CHERRYVIEW(dev_priv
))
5025 dev_priv
->num_fence_regs
= 32;
5026 else if (INTEL_INFO(dev_priv
)->gen
>= 4 || IS_I945G(dev_priv
) ||
5027 IS_I945GM(dev_priv
) || IS_G33(dev_priv
))
5028 dev_priv
->num_fence_regs
= 16;
5030 dev_priv
->num_fence_regs
= 8;
5032 if (intel_vgpu_active(dev
))
5033 dev_priv
->num_fence_regs
=
5034 I915_READ(vgtif_reg(avail_rs
.fence_num
));
5036 /* Initialize fence registers to zero */
5037 i915_gem_restore_fences(dev
);
5039 i915_gem_detect_bit_6_swizzle(dev
);
5043 i915_gem_load_init(struct drm_device
*dev
)
5045 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5049 kmem_cache_create("i915_gem_object",
5050 sizeof(struct drm_i915_gem_object
), 0,
5054 kmem_cache_create("i915_gem_vma",
5055 sizeof(struct i915_vma
), 0,
5058 dev_priv
->requests
=
5059 kmem_cache_create("i915_gem_request",
5060 sizeof(struct drm_i915_gem_request
), 0,
5064 INIT_LIST_HEAD(&dev_priv
->vm_list
);
5065 INIT_LIST_HEAD(&dev_priv
->context_list
);
5066 INIT_LIST_HEAD(&dev_priv
->mm
.unbound_list
);
5067 INIT_LIST_HEAD(&dev_priv
->mm
.bound_list
);
5068 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
5069 for (i
= 0; i
< I915_NUM_ENGINES
; i
++)
5070 init_engine_lists(&dev_priv
->engine
[i
]);
5071 for (i
= 0; i
< I915_MAX_NUM_FENCES
; i
++)
5072 INIT_LIST_HEAD(&dev_priv
->fence_regs
[i
].lru_list
);
5073 INIT_DELAYED_WORK(&dev_priv
->mm
.retire_work
,
5074 i915_gem_retire_work_handler
);
5075 INIT_DELAYED_WORK(&dev_priv
->mm
.idle_work
,
5076 i915_gem_idle_work_handler
);
5077 init_waitqueue_head(&dev_priv
->gpu_error
.reset_queue
);
5079 dev_priv
->relative_constants_mode
= I915_EXEC_CONSTANTS_REL_GENERAL
;
5082 * Set initial sequence number for requests.
5083 * Using this number allows the wraparound to happen early,
5084 * catching any obvious problems.
5086 dev_priv
->next_seqno
= ((u32
)~0 - 0x1100);
5087 dev_priv
->last_seqno
= ((u32
)~0 - 0x1101);
5089 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
5091 init_waitqueue_head(&dev_priv
->pending_flip_queue
);
5093 dev_priv
->mm
.interruptible
= true;
5095 mutex_init(&dev_priv
->fb_tracking
.lock
);
5098 void i915_gem_load_cleanup(struct drm_device
*dev
)
5100 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5102 kmem_cache_destroy(dev_priv
->requests
);
5103 kmem_cache_destroy(dev_priv
->vmas
);
5104 kmem_cache_destroy(dev_priv
->objects
);
5107 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
)
5109 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
5111 /* Clean up our request list when the client is going away, so that
5112 * later retire_requests won't dereference our soon-to-be-gone
5115 spin_lock(&file_priv
->mm
.lock
);
5116 while (!list_empty(&file_priv
->mm
.request_list
)) {
5117 struct drm_i915_gem_request
*request
;
5119 request
= list_first_entry(&file_priv
->mm
.request_list
,
5120 struct drm_i915_gem_request
,
5122 list_del(&request
->client_list
);
5123 request
->file_priv
= NULL
;
5125 spin_unlock(&file_priv
->mm
.lock
);
5127 if (!list_empty(&file_priv
->rps
.link
)) {
5128 spin_lock(&to_i915(dev
)->rps
.client_lock
);
5129 list_del(&file_priv
->rps
.link
);
5130 spin_unlock(&to_i915(dev
)->rps
.client_lock
);
5134 int i915_gem_open(struct drm_device
*dev
, struct drm_file
*file
)
5136 struct drm_i915_file_private
*file_priv
;
5139 DRM_DEBUG_DRIVER("\n");
5141 file_priv
= kzalloc(sizeof(*file_priv
), GFP_KERNEL
);
5145 file
->driver_priv
= file_priv
;
5146 file_priv
->dev_priv
= dev
->dev_private
;
5147 file_priv
->file
= file
;
5148 INIT_LIST_HEAD(&file_priv
->rps
.link
);
5150 spin_lock_init(&file_priv
->mm
.lock
);
5151 INIT_LIST_HEAD(&file_priv
->mm
.request_list
);
5153 file_priv
->bsd_ring
= -1;
5155 ret
= i915_gem_context_open(dev
, file
);
5163 * i915_gem_track_fb - update frontbuffer tracking
5164 * @old: current GEM buffer for the frontbuffer slots
5165 * @new: new GEM buffer for the frontbuffer slots
5166 * @frontbuffer_bits: bitmask of frontbuffer slots
5168 * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them
5169 * from @old and setting them in @new. Both @old and @new can be NULL.
5171 void i915_gem_track_fb(struct drm_i915_gem_object
*old
,
5172 struct drm_i915_gem_object
*new,
5173 unsigned frontbuffer_bits
)
5176 WARN_ON(!mutex_is_locked(&old
->base
.dev
->struct_mutex
));
5177 WARN_ON(!(old
->frontbuffer_bits
& frontbuffer_bits
));
5178 old
->frontbuffer_bits
&= ~frontbuffer_bits
;
5182 WARN_ON(!mutex_is_locked(&new->base
.dev
->struct_mutex
));
5183 WARN_ON(new->frontbuffer_bits
& frontbuffer_bits
);
5184 new->frontbuffer_bits
|= frontbuffer_bits
;
5188 /* All the new VM stuff */
5189 u64
i915_gem_obj_offset(struct drm_i915_gem_object
*o
,
5190 struct i915_address_space
*vm
)
5192 struct drm_i915_private
*dev_priv
= o
->base
.dev
->dev_private
;
5193 struct i915_vma
*vma
;
5195 WARN_ON(vm
== &dev_priv
->mm
.aliasing_ppgtt
->base
);
5197 list_for_each_entry(vma
, &o
->vma_list
, obj_link
) {
5199 vma
->ggtt_view
.type
!= I915_GGTT_VIEW_NORMAL
)
5202 return vma
->node
.start
;
5205 WARN(1, "%s vma for this object not found.\n",
5206 i915_is_ggtt(vm
) ? "global" : "ppgtt");
5210 u64
i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object
*o
,
5211 const struct i915_ggtt_view
*view
)
5213 struct i915_address_space
*ggtt
= i915_obj_to_ggtt(o
);
5214 struct i915_vma
*vma
;
5216 list_for_each_entry(vma
, &o
->vma_list
, obj_link
)
5217 if (vma
->vm
== ggtt
&&
5218 i915_ggtt_view_equal(&vma
->ggtt_view
, view
))
5219 return vma
->node
.start
;
5221 WARN(1, "global vma for this object not found. (view=%u)\n", view
->type
);
5225 bool i915_gem_obj_bound(struct drm_i915_gem_object
*o
,
5226 struct i915_address_space
*vm
)
5228 struct i915_vma
*vma
;
5230 list_for_each_entry(vma
, &o
->vma_list
, obj_link
) {
5232 vma
->ggtt_view
.type
!= I915_GGTT_VIEW_NORMAL
)
5234 if (vma
->vm
== vm
&& drm_mm_node_allocated(&vma
->node
))
5241 bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object
*o
,
5242 const struct i915_ggtt_view
*view
)
5244 struct i915_address_space
*ggtt
= i915_obj_to_ggtt(o
);
5245 struct i915_vma
*vma
;
5247 list_for_each_entry(vma
, &o
->vma_list
, obj_link
)
5248 if (vma
->vm
== ggtt
&&
5249 i915_ggtt_view_equal(&vma
->ggtt_view
, view
) &&
5250 drm_mm_node_allocated(&vma
->node
))
5256 bool i915_gem_obj_bound_any(struct drm_i915_gem_object
*o
)
5258 struct i915_vma
*vma
;
5260 list_for_each_entry(vma
, &o
->vma_list
, obj_link
)
5261 if (drm_mm_node_allocated(&vma
->node
))
5267 unsigned long i915_gem_obj_size(struct drm_i915_gem_object
*o
,
5268 struct i915_address_space
*vm
)
5270 struct drm_i915_private
*dev_priv
= o
->base
.dev
->dev_private
;
5271 struct i915_vma
*vma
;
5273 WARN_ON(vm
== &dev_priv
->mm
.aliasing_ppgtt
->base
);
5275 BUG_ON(list_empty(&o
->vma_list
));
5277 list_for_each_entry(vma
, &o
->vma_list
, obj_link
) {
5279 vma
->ggtt_view
.type
!= I915_GGTT_VIEW_NORMAL
)
5282 return vma
->node
.size
;
5287 bool i915_gem_obj_is_pinned(struct drm_i915_gem_object
*obj
)
5289 struct i915_vma
*vma
;
5290 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
)
5291 if (vma
->pin_count
> 0)
5297 /* Like i915_gem_object_get_page(), but mark the returned page dirty */
5299 i915_gem_object_get_dirty_page(struct drm_i915_gem_object
*obj
, int n
)
5303 /* Only default objects have per-page dirty tracking */
5304 if (WARN_ON((obj
->ops
->flags
& I915_GEM_OBJECT_HAS_STRUCT_PAGE
) == 0))
5307 page
= i915_gem_object_get_page(obj
, n
);
5308 set_page_dirty(page
);
5312 /* Allocate a new GEM object and fill it with the supplied data */
5313 struct drm_i915_gem_object
*
5314 i915_gem_object_create_from_data(struct drm_device
*dev
,
5315 const void *data
, size_t size
)
5317 struct drm_i915_gem_object
*obj
;
5318 struct sg_table
*sg
;
5322 obj
= i915_gem_alloc_object(dev
, round_up(size
, PAGE_SIZE
));
5323 if (IS_ERR_OR_NULL(obj
))
5326 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
5330 ret
= i915_gem_object_get_pages(obj
);
5334 i915_gem_object_pin_pages(obj
);
5336 bytes
= sg_copy_from_buffer(sg
->sgl
, sg
->nents
, (void *)data
, size
);
5337 obj
->dirty
= 1; /* Backing store is now out of date */
5338 i915_gem_object_unpin_pages(obj
);
5340 if (WARN_ON(bytes
!= size
)) {
5341 DRM_ERROR("Incomplete copy, wrote %zu of %zu", bytes
, size
);
5349 drm_gem_object_unreference(&obj
->base
);
5350 return ERR_PTR(ret
);