2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/shmem_fs.h>
35 #include <linux/slab.h>
36 #include <linux/swap.h>
37 #include <linux/pci.h>
39 static __must_check
int i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object
*obj
);
40 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
);
41 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
);
42 static __must_check
int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object
*obj
,
44 bool map_and_fenceable
);
45 static int i915_gem_phys_pwrite(struct drm_device
*dev
,
46 struct drm_i915_gem_object
*obj
,
47 struct drm_i915_gem_pwrite
*args
,
48 struct drm_file
*file
);
50 static void i915_gem_write_fence(struct drm_device
*dev
, int reg
,
51 struct drm_i915_gem_object
*obj
);
52 static void i915_gem_object_update_fence(struct drm_i915_gem_object
*obj
,
53 struct drm_i915_fence_reg
*fence
,
56 static int i915_gem_inactive_shrink(struct shrinker
*shrinker
,
57 struct shrink_control
*sc
);
58 static void i915_gem_object_truncate(struct drm_i915_gem_object
*obj
);
60 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object
*obj
)
63 i915_gem_release_mmap(obj
);
65 /* As we do not have an associated fence register, we will force
66 * a tiling change if we ever need to acquire one.
68 obj
->fence_dirty
= false;
69 obj
->fence_reg
= I915_FENCE_REG_NONE
;
72 /* some bookkeeping */
73 static void i915_gem_info_add_obj(struct drm_i915_private
*dev_priv
,
76 dev_priv
->mm
.object_count
++;
77 dev_priv
->mm
.object_memory
+= size
;
80 static void i915_gem_info_remove_obj(struct drm_i915_private
*dev_priv
,
83 dev_priv
->mm
.object_count
--;
84 dev_priv
->mm
.object_memory
-= size
;
88 i915_gem_wait_for_error(struct drm_device
*dev
)
90 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
91 struct completion
*x
= &dev_priv
->error_completion
;
95 if (!atomic_read(&dev_priv
->mm
.wedged
))
98 ret
= wait_for_completion_interruptible(x
);
102 if (atomic_read(&dev_priv
->mm
.wedged
)) {
103 /* GPU is hung, bump the completion count to account for
104 * the token we just consumed so that we never hit zero and
105 * end up waiting upon a subsequent completion event that
108 spin_lock_irqsave(&x
->wait
.lock
, flags
);
110 spin_unlock_irqrestore(&x
->wait
.lock
, flags
);
115 int i915_mutex_lock_interruptible(struct drm_device
*dev
)
119 ret
= i915_gem_wait_for_error(dev
);
123 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
127 WARN_ON(i915_verify_lists(dev
));
132 i915_gem_object_is_inactive(struct drm_i915_gem_object
*obj
)
138 i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
139 struct drm_file
*file
)
141 struct drm_i915_gem_init
*args
= data
;
143 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
146 if (args
->gtt_start
>= args
->gtt_end
||
147 (args
->gtt_end
| args
->gtt_start
) & (PAGE_SIZE
- 1))
150 /* GEM with user mode setting was never supported on ilk and later. */
151 if (INTEL_INFO(dev
)->gen
>= 5)
154 mutex_lock(&dev
->struct_mutex
);
155 i915_gem_init_global_gtt(dev
, args
->gtt_start
,
156 args
->gtt_end
, args
->gtt_end
);
157 mutex_unlock(&dev
->struct_mutex
);
163 i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
164 struct drm_file
*file
)
166 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
167 struct drm_i915_gem_get_aperture
*args
= data
;
168 struct drm_i915_gem_object
*obj
;
171 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
175 mutex_lock(&dev
->struct_mutex
);
176 list_for_each_entry(obj
, &dev_priv
->mm
.gtt_list
, gtt_list
)
178 pinned
+= obj
->gtt_space
->size
;
179 mutex_unlock(&dev
->struct_mutex
);
181 args
->aper_size
= dev_priv
->mm
.gtt_total
;
182 args
->aper_available_size
= args
->aper_size
- pinned
;
188 i915_gem_create(struct drm_file
*file
,
189 struct drm_device
*dev
,
193 struct drm_i915_gem_object
*obj
;
197 size
= roundup(size
, PAGE_SIZE
);
201 /* Allocate the new object */
202 obj
= i915_gem_alloc_object(dev
, size
);
206 ret
= drm_gem_handle_create(file
, &obj
->base
, &handle
);
208 drm_gem_object_release(&obj
->base
);
209 i915_gem_info_remove_obj(dev
->dev_private
, obj
->base
.size
);
214 /* drop reference from allocate - handle holds it now */
215 drm_gem_object_unreference(&obj
->base
);
216 trace_i915_gem_object_create(obj
);
223 i915_gem_dumb_create(struct drm_file
*file
,
224 struct drm_device
*dev
,
225 struct drm_mode_create_dumb
*args
)
227 /* have to work out size/pitch and return them */
228 args
->pitch
= ALIGN(args
->width
* ((args
->bpp
+ 7) / 8), 64);
229 args
->size
= args
->pitch
* args
->height
;
230 return i915_gem_create(file
, dev
,
231 args
->size
, &args
->handle
);
234 int i915_gem_dumb_destroy(struct drm_file
*file
,
235 struct drm_device
*dev
,
238 return drm_gem_handle_delete(file
, handle
);
242 * Creates a new mm object and returns a handle to it.
245 i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
246 struct drm_file
*file
)
248 struct drm_i915_gem_create
*args
= data
;
249 return i915_gem_create(file
, dev
,
250 args
->size
, &args
->handle
);
253 static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object
*obj
)
255 drm_i915_private_t
*dev_priv
= obj
->base
.dev
->dev_private
;
257 return dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_9_10_17
&&
258 obj
->tiling_mode
!= I915_TILING_NONE
;
262 __copy_to_user_swizzled(char __user
*cpu_vaddr
,
263 const char *gpu_vaddr
, int gpu_offset
,
266 int ret
, cpu_offset
= 0;
269 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
270 int this_length
= min(cacheline_end
- gpu_offset
, length
);
271 int swizzled_gpu_offset
= gpu_offset
^ 64;
273 ret
= __copy_to_user(cpu_vaddr
+ cpu_offset
,
274 gpu_vaddr
+ swizzled_gpu_offset
,
279 cpu_offset
+= this_length
;
280 gpu_offset
+= this_length
;
281 length
-= this_length
;
288 __copy_from_user_swizzled(char *gpu_vaddr
, int gpu_offset
,
289 const char __user
*cpu_vaddr
,
292 int ret
, cpu_offset
= 0;
295 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
296 int this_length
= min(cacheline_end
- gpu_offset
, length
);
297 int swizzled_gpu_offset
= gpu_offset
^ 64;
299 ret
= __copy_from_user(gpu_vaddr
+ swizzled_gpu_offset
,
300 cpu_vaddr
+ cpu_offset
,
305 cpu_offset
+= this_length
;
306 gpu_offset
+= this_length
;
307 length
-= this_length
;
313 /* Per-page copy function for the shmem pread fastpath.
314 * Flushes invalid cachelines before reading the target if
315 * needs_clflush is set. */
317 shmem_pread_fast(struct page
*page
, int shmem_page_offset
, int page_length
,
318 char __user
*user_data
,
319 bool page_do_bit17_swizzling
, bool needs_clflush
)
324 if (unlikely(page_do_bit17_swizzling
))
327 vaddr
= kmap_atomic(page
);
329 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
331 ret
= __copy_to_user_inatomic(user_data
,
332 vaddr
+ shmem_page_offset
,
334 kunmap_atomic(vaddr
);
340 shmem_clflush_swizzled_range(char *addr
, unsigned long length
,
343 if (unlikely(swizzled
)) {
344 unsigned long start
= (unsigned long) addr
;
345 unsigned long end
= (unsigned long) addr
+ length
;
347 /* For swizzling simply ensure that we always flush both
348 * channels. Lame, but simple and it works. Swizzled
349 * pwrite/pread is far from a hotpath - current userspace
350 * doesn't use it at all. */
351 start
= round_down(start
, 128);
352 end
= round_up(end
, 128);
354 drm_clflush_virt_range((void *)start
, end
- start
);
356 drm_clflush_virt_range(addr
, length
);
361 /* Only difference to the fast-path function is that this can handle bit17
362 * and uses non-atomic copy and kmap functions. */
364 shmem_pread_slow(struct page
*page
, int shmem_page_offset
, int page_length
,
365 char __user
*user_data
,
366 bool page_do_bit17_swizzling
, bool needs_clflush
)
373 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
375 page_do_bit17_swizzling
);
377 if (page_do_bit17_swizzling
)
378 ret
= __copy_to_user_swizzled(user_data
,
379 vaddr
, shmem_page_offset
,
382 ret
= __copy_to_user(user_data
,
383 vaddr
+ shmem_page_offset
,
391 i915_gem_shmem_pread(struct drm_device
*dev
,
392 struct drm_i915_gem_object
*obj
,
393 struct drm_i915_gem_pread
*args
,
394 struct drm_file
*file
)
396 struct address_space
*mapping
= obj
->base
.filp
->f_path
.dentry
->d_inode
->i_mapping
;
397 char __user
*user_data
;
400 int shmem_page_offset
, page_length
, ret
= 0;
401 int obj_do_bit17_swizzling
, page_do_bit17_swizzling
;
402 int hit_slowpath
= 0;
404 int needs_clflush
= 0;
407 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
410 obj_do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
412 if (!(obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
)) {
413 /* If we're not in the cpu read domain, set ourself into the gtt
414 * read domain and manually flush cachelines (if required). This
415 * optimizes for the case when the gpu will dirty the data
416 * anyway again before the next pread happens. */
417 if (obj
->cache_level
== I915_CACHE_NONE
)
419 ret
= i915_gem_object_set_to_gtt_domain(obj
, false);
424 offset
= args
->offset
;
429 /* Operation in this page
431 * shmem_page_offset = offset within page in shmem file
432 * page_length = bytes to copy for this page
434 shmem_page_offset
= offset_in_page(offset
);
435 page_length
= remain
;
436 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
437 page_length
= PAGE_SIZE
- shmem_page_offset
;
440 page
= obj
->pages
[offset
>> PAGE_SHIFT
];
443 page
= shmem_read_mapping_page(mapping
, offset
>> PAGE_SHIFT
);
451 page_do_bit17_swizzling
= obj_do_bit17_swizzling
&&
452 (page_to_phys(page
) & (1 << 17)) != 0;
454 ret
= shmem_pread_fast(page
, shmem_page_offset
, page_length
,
455 user_data
, page_do_bit17_swizzling
,
461 page_cache_get(page
);
462 mutex_unlock(&dev
->struct_mutex
);
465 ret
= fault_in_multipages_writeable(user_data
, remain
);
466 /* Userspace is tricking us, but we've already clobbered
467 * its pages with the prefault and promised to write the
468 * data up to the first fault. Hence ignore any errors
469 * and just continue. */
474 ret
= shmem_pread_slow(page
, shmem_page_offset
, page_length
,
475 user_data
, page_do_bit17_swizzling
,
478 mutex_lock(&dev
->struct_mutex
);
479 page_cache_release(page
);
481 mark_page_accessed(page
);
483 page_cache_release(page
);
490 remain
-= page_length
;
491 user_data
+= page_length
;
492 offset
+= page_length
;
497 /* Fixup: Kill any reinstated backing storage pages */
498 if (obj
->madv
== __I915_MADV_PURGED
)
499 i915_gem_object_truncate(obj
);
506 * Reads data from the object referenced by handle.
508 * On error, the contents of *data are undefined.
511 i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
512 struct drm_file
*file
)
514 struct drm_i915_gem_pread
*args
= data
;
515 struct drm_i915_gem_object
*obj
;
521 if (!access_ok(VERIFY_WRITE
,
522 (char __user
*)(uintptr_t)args
->data_ptr
,
526 ret
= i915_mutex_lock_interruptible(dev
);
530 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
531 if (&obj
->base
== NULL
) {
536 /* Bounds check source. */
537 if (args
->offset
> obj
->base
.size
||
538 args
->size
> obj
->base
.size
- args
->offset
) {
543 trace_i915_gem_object_pread(obj
, args
->offset
, args
->size
);
545 ret
= i915_gem_shmem_pread(dev
, obj
, args
, file
);
548 drm_gem_object_unreference(&obj
->base
);
550 mutex_unlock(&dev
->struct_mutex
);
554 /* This is the fast write path which cannot handle
555 * page faults in the source data
559 fast_user_write(struct io_mapping
*mapping
,
560 loff_t page_base
, int page_offset
,
561 char __user
*user_data
,
564 void __iomem
*vaddr_atomic
;
566 unsigned long unwritten
;
568 vaddr_atomic
= io_mapping_map_atomic_wc(mapping
, page_base
);
569 /* We can use the cpu mem copy function because this is X86. */
570 vaddr
= (void __force
*)vaddr_atomic
+ page_offset
;
571 unwritten
= __copy_from_user_inatomic_nocache(vaddr
,
573 io_mapping_unmap_atomic(vaddr_atomic
);
578 * This is the fast pwrite path, where we copy the data directly from the
579 * user into the GTT, uncached.
582 i915_gem_gtt_pwrite_fast(struct drm_device
*dev
,
583 struct drm_i915_gem_object
*obj
,
584 struct drm_i915_gem_pwrite
*args
,
585 struct drm_file
*file
)
587 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
589 loff_t offset
, page_base
;
590 char __user
*user_data
;
591 int page_offset
, page_length
, ret
;
593 ret
= i915_gem_object_pin(obj
, 0, true);
597 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
601 ret
= i915_gem_object_put_fence(obj
);
605 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
608 offset
= obj
->gtt_offset
+ args
->offset
;
611 /* Operation in this page
613 * page_base = page offset within aperture
614 * page_offset = offset within page
615 * page_length = bytes to copy for this page
617 page_base
= offset
& PAGE_MASK
;
618 page_offset
= offset_in_page(offset
);
619 page_length
= remain
;
620 if ((page_offset
+ remain
) > PAGE_SIZE
)
621 page_length
= PAGE_SIZE
- page_offset
;
623 /* If we get a fault while copying data, then (presumably) our
624 * source page isn't available. Return the error and we'll
625 * retry in the slow path.
627 if (fast_user_write(dev_priv
->mm
.gtt_mapping
, page_base
,
628 page_offset
, user_data
, page_length
)) {
633 remain
-= page_length
;
634 user_data
+= page_length
;
635 offset
+= page_length
;
639 i915_gem_object_unpin(obj
);
644 /* Per-page copy function for the shmem pwrite fastpath.
645 * Flushes invalid cachelines before writing to the target if
646 * needs_clflush_before is set and flushes out any written cachelines after
647 * writing if needs_clflush is set. */
649 shmem_pwrite_fast(struct page
*page
, int shmem_page_offset
, int page_length
,
650 char __user
*user_data
,
651 bool page_do_bit17_swizzling
,
652 bool needs_clflush_before
,
653 bool needs_clflush_after
)
658 if (unlikely(page_do_bit17_swizzling
))
661 vaddr
= kmap_atomic(page
);
662 if (needs_clflush_before
)
663 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
665 ret
= __copy_from_user_inatomic_nocache(vaddr
+ shmem_page_offset
,
668 if (needs_clflush_after
)
669 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
671 kunmap_atomic(vaddr
);
676 /* Only difference to the fast-path function is that this can handle bit17
677 * and uses non-atomic copy and kmap functions. */
679 shmem_pwrite_slow(struct page
*page
, int shmem_page_offset
, int page_length
,
680 char __user
*user_data
,
681 bool page_do_bit17_swizzling
,
682 bool needs_clflush_before
,
683 bool needs_clflush_after
)
689 if (unlikely(needs_clflush_before
|| page_do_bit17_swizzling
))
690 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
692 page_do_bit17_swizzling
);
693 if (page_do_bit17_swizzling
)
694 ret
= __copy_from_user_swizzled(vaddr
, shmem_page_offset
,
698 ret
= __copy_from_user(vaddr
+ shmem_page_offset
,
701 if (needs_clflush_after
)
702 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
704 page_do_bit17_swizzling
);
711 i915_gem_shmem_pwrite(struct drm_device
*dev
,
712 struct drm_i915_gem_object
*obj
,
713 struct drm_i915_gem_pwrite
*args
,
714 struct drm_file
*file
)
716 struct address_space
*mapping
= obj
->base
.filp
->f_path
.dentry
->d_inode
->i_mapping
;
719 char __user
*user_data
;
720 int shmem_page_offset
, page_length
, ret
= 0;
721 int obj_do_bit17_swizzling
, page_do_bit17_swizzling
;
722 int hit_slowpath
= 0;
723 int needs_clflush_after
= 0;
724 int needs_clflush_before
= 0;
727 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
730 obj_do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
732 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
733 /* If we're not in the cpu write domain, set ourself into the gtt
734 * write domain and manually flush cachelines (if required). This
735 * optimizes for the case when the gpu will use the data
736 * right away and we therefore have to clflush anyway. */
737 if (obj
->cache_level
== I915_CACHE_NONE
)
738 needs_clflush_after
= 1;
739 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
743 /* Same trick applies for invalidate partially written cachelines before
745 if (!(obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
)
746 && obj
->cache_level
== I915_CACHE_NONE
)
747 needs_clflush_before
= 1;
749 offset
= args
->offset
;
754 int partial_cacheline_write
;
756 /* Operation in this page
758 * shmem_page_offset = offset within page in shmem file
759 * page_length = bytes to copy for this page
761 shmem_page_offset
= offset_in_page(offset
);
763 page_length
= remain
;
764 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
765 page_length
= PAGE_SIZE
- shmem_page_offset
;
767 /* If we don't overwrite a cacheline completely we need to be
768 * careful to have up-to-date data by first clflushing. Don't
769 * overcomplicate things and flush the entire patch. */
770 partial_cacheline_write
= needs_clflush_before
&&
771 ((shmem_page_offset
| page_length
)
772 & (boot_cpu_data
.x86_clflush_size
- 1));
775 page
= obj
->pages
[offset
>> PAGE_SHIFT
];
778 page
= shmem_read_mapping_page(mapping
, offset
>> PAGE_SHIFT
);
786 page_do_bit17_swizzling
= obj_do_bit17_swizzling
&&
787 (page_to_phys(page
) & (1 << 17)) != 0;
789 ret
= shmem_pwrite_fast(page
, shmem_page_offset
, page_length
,
790 user_data
, page_do_bit17_swizzling
,
791 partial_cacheline_write
,
792 needs_clflush_after
);
797 page_cache_get(page
);
798 mutex_unlock(&dev
->struct_mutex
);
800 ret
= shmem_pwrite_slow(page
, shmem_page_offset
, page_length
,
801 user_data
, page_do_bit17_swizzling
,
802 partial_cacheline_write
,
803 needs_clflush_after
);
805 mutex_lock(&dev
->struct_mutex
);
806 page_cache_release(page
);
808 set_page_dirty(page
);
809 mark_page_accessed(page
);
811 page_cache_release(page
);
818 remain
-= page_length
;
819 user_data
+= page_length
;
820 offset
+= page_length
;
825 /* Fixup: Kill any reinstated backing storage pages */
826 if (obj
->madv
== __I915_MADV_PURGED
)
827 i915_gem_object_truncate(obj
);
828 /* and flush dirty cachelines in case the object isn't in the cpu write
830 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
831 i915_gem_clflush_object(obj
);
832 intel_gtt_chipset_flush();
836 if (needs_clflush_after
)
837 intel_gtt_chipset_flush();
843 * Writes data to the object referenced by handle.
845 * On error, the contents of the buffer that were to be modified are undefined.
848 i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
849 struct drm_file
*file
)
851 struct drm_i915_gem_pwrite
*args
= data
;
852 struct drm_i915_gem_object
*obj
;
858 if (!access_ok(VERIFY_READ
,
859 (char __user
*)(uintptr_t)args
->data_ptr
,
863 ret
= fault_in_multipages_readable((char __user
*)(uintptr_t)args
->data_ptr
,
868 ret
= i915_mutex_lock_interruptible(dev
);
872 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
873 if (&obj
->base
== NULL
) {
878 /* Bounds check destination. */
879 if (args
->offset
> obj
->base
.size
||
880 args
->size
> obj
->base
.size
- args
->offset
) {
885 trace_i915_gem_object_pwrite(obj
, args
->offset
, args
->size
);
888 /* We can only do the GTT pwrite on untiled buffers, as otherwise
889 * it would end up going through the fenced access, and we'll get
890 * different detiling behavior between reading and writing.
891 * pread/pwrite currently are reading and writing from the CPU
892 * perspective, requiring manual detiling by the client.
895 ret
= i915_gem_phys_pwrite(dev
, obj
, args
, file
);
899 if (obj
->gtt_space
&&
900 obj
->cache_level
== I915_CACHE_NONE
&&
901 obj
->tiling_mode
== I915_TILING_NONE
&&
902 obj
->map_and_fenceable
&&
903 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
904 ret
= i915_gem_gtt_pwrite_fast(dev
, obj
, args
, file
);
905 /* Note that the gtt paths might fail with non-page-backed user
906 * pointers (e.g. gtt mappings when moving data between
907 * textures). Fallback to the shmem path in that case. */
911 ret
= i915_gem_shmem_pwrite(dev
, obj
, args
, file
);
914 drm_gem_object_unreference(&obj
->base
);
916 mutex_unlock(&dev
->struct_mutex
);
921 * Called when user space prepares to use an object with the CPU, either
922 * through the mmap ioctl's mapping or a GTT mapping.
925 i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
926 struct drm_file
*file
)
928 struct drm_i915_gem_set_domain
*args
= data
;
929 struct drm_i915_gem_object
*obj
;
930 uint32_t read_domains
= args
->read_domains
;
931 uint32_t write_domain
= args
->write_domain
;
934 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
937 /* Only handle setting domains to types used by the CPU. */
938 if (write_domain
& I915_GEM_GPU_DOMAINS
)
941 if (read_domains
& I915_GEM_GPU_DOMAINS
)
944 /* Having something in the write domain implies it's in the read
945 * domain, and only that read domain. Enforce that in the request.
947 if (write_domain
!= 0 && read_domains
!= write_domain
)
950 ret
= i915_mutex_lock_interruptible(dev
);
954 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
955 if (&obj
->base
== NULL
) {
960 if (read_domains
& I915_GEM_DOMAIN_GTT
) {
961 ret
= i915_gem_object_set_to_gtt_domain(obj
, write_domain
!= 0);
963 /* Silently promote "you're not bound, there was nothing to do"
964 * to success, since the client was just asking us to
965 * make sure everything was done.
970 ret
= i915_gem_object_set_to_cpu_domain(obj
, write_domain
!= 0);
973 drm_gem_object_unreference(&obj
->base
);
975 mutex_unlock(&dev
->struct_mutex
);
980 * Called when user space has done writes to this buffer
983 i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
984 struct drm_file
*file
)
986 struct drm_i915_gem_sw_finish
*args
= data
;
987 struct drm_i915_gem_object
*obj
;
990 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
993 ret
= i915_mutex_lock_interruptible(dev
);
997 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
998 if (&obj
->base
== NULL
) {
1003 /* Pinned buffers may be scanout, so flush the cache */
1005 i915_gem_object_flush_cpu_write_domain(obj
);
1007 drm_gem_object_unreference(&obj
->base
);
1009 mutex_unlock(&dev
->struct_mutex
);
1014 * Maps the contents of an object, returning the address it is mapped
1017 * While the mapping holds a reference on the contents of the object, it doesn't
1018 * imply a ref on the object itself.
1021 i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1022 struct drm_file
*file
)
1024 struct drm_i915_gem_mmap
*args
= data
;
1025 struct drm_gem_object
*obj
;
1028 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1031 obj
= drm_gem_object_lookup(dev
, file
, args
->handle
);
1035 down_write(¤t
->mm
->mmap_sem
);
1036 addr
= do_mmap(obj
->filp
, 0, args
->size
,
1037 PROT_READ
| PROT_WRITE
, MAP_SHARED
,
1039 up_write(¤t
->mm
->mmap_sem
);
1040 drm_gem_object_unreference_unlocked(obj
);
1041 if (IS_ERR((void *)addr
))
1044 args
->addr_ptr
= (uint64_t) addr
;
1050 * i915_gem_fault - fault a page into the GTT
1051 * vma: VMA in question
1054 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1055 * from userspace. The fault handler takes care of binding the object to
1056 * the GTT (if needed), allocating and programming a fence register (again,
1057 * only if needed based on whether the old reg is still valid or the object
1058 * is tiled) and inserting a new PTE into the faulting process.
1060 * Note that the faulting process may involve evicting existing objects
1061 * from the GTT and/or fence registers to make room. So performance may
1062 * suffer if the GTT working set is large or there are few fence registers
1065 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
)
1067 struct drm_i915_gem_object
*obj
= to_intel_bo(vma
->vm_private_data
);
1068 struct drm_device
*dev
= obj
->base
.dev
;
1069 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1070 pgoff_t page_offset
;
1073 bool write
= !!(vmf
->flags
& FAULT_FLAG_WRITE
);
1075 /* We don't use vmf->pgoff since that has the fake offset */
1076 page_offset
= ((unsigned long)vmf
->virtual_address
- vma
->vm_start
) >>
1079 ret
= i915_mutex_lock_interruptible(dev
);
1083 trace_i915_gem_object_fault(obj
, page_offset
, true, write
);
1085 /* Now bind it into the GTT if needed */
1086 if (!obj
->map_and_fenceable
) {
1087 ret
= i915_gem_object_unbind(obj
);
1091 if (!obj
->gtt_space
) {
1092 ret
= i915_gem_object_bind_to_gtt(obj
, 0, true);
1096 ret
= i915_gem_object_set_to_gtt_domain(obj
, write
);
1101 if (!obj
->has_global_gtt_mapping
)
1102 i915_gem_gtt_bind_object(obj
, obj
->cache_level
);
1104 ret
= i915_gem_object_get_fence(obj
);
1108 if (i915_gem_object_is_inactive(obj
))
1109 list_move_tail(&obj
->mm_list
, &dev_priv
->mm
.inactive_list
);
1111 obj
->fault_mappable
= true;
1113 pfn
= ((dev
->agp
->base
+ obj
->gtt_offset
) >> PAGE_SHIFT
) +
1116 /* Finally, remap it using the new GTT offset */
1117 ret
= vm_insert_pfn(vma
, (unsigned long)vmf
->virtual_address
, pfn
);
1119 mutex_unlock(&dev
->struct_mutex
);
1124 /* Give the error handler a chance to run and move the
1125 * objects off the GPU active list. Next time we service the
1126 * fault, we should be able to transition the page into the
1127 * GTT without touching the GPU (and so avoid further
1128 * EIO/EGAIN). If the GPU is wedged, then there is no issue
1129 * with coherency, just lost writes.
1135 return VM_FAULT_NOPAGE
;
1137 return VM_FAULT_OOM
;
1139 return VM_FAULT_SIGBUS
;
1144 * i915_gem_release_mmap - remove physical page mappings
1145 * @obj: obj in question
1147 * Preserve the reservation of the mmapping with the DRM core code, but
1148 * relinquish ownership of the pages back to the system.
1150 * It is vital that we remove the page mapping if we have mapped a tiled
1151 * object through the GTT and then lose the fence register due to
1152 * resource pressure. Similarly if the object has been moved out of the
1153 * aperture, than pages mapped into userspace must be revoked. Removing the
1154 * mapping will then trigger a page fault on the next user access, allowing
1155 * fixup by i915_gem_fault().
1158 i915_gem_release_mmap(struct drm_i915_gem_object
*obj
)
1160 if (!obj
->fault_mappable
)
1163 if (obj
->base
.dev
->dev_mapping
)
1164 unmap_mapping_range(obj
->base
.dev
->dev_mapping
,
1165 (loff_t
)obj
->base
.map_list
.hash
.key
<<PAGE_SHIFT
,
1168 obj
->fault_mappable
= false;
1172 i915_gem_get_gtt_size(struct drm_device
*dev
, uint32_t size
, int tiling_mode
)
1176 if (INTEL_INFO(dev
)->gen
>= 4 ||
1177 tiling_mode
== I915_TILING_NONE
)
1180 /* Previous chips need a power-of-two fence region when tiling */
1181 if (INTEL_INFO(dev
)->gen
== 3)
1182 gtt_size
= 1024*1024;
1184 gtt_size
= 512*1024;
1186 while (gtt_size
< size
)
1193 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1194 * @obj: object to check
1196 * Return the required GTT alignment for an object, taking into account
1197 * potential fence register mapping.
1200 i915_gem_get_gtt_alignment(struct drm_device
*dev
,
1205 * Minimum alignment is 4k (GTT page size), but might be greater
1206 * if a fence register is needed for the object.
1208 if (INTEL_INFO(dev
)->gen
>= 4 ||
1209 tiling_mode
== I915_TILING_NONE
)
1213 * Previous chips need to be aligned to the size of the smallest
1214 * fence register that can contain the object.
1216 return i915_gem_get_gtt_size(dev
, size
, tiling_mode
);
1220 * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an
1223 * @size: size of the object
1224 * @tiling_mode: tiling mode of the object
1226 * Return the required GTT alignment for an object, only taking into account
1227 * unfenced tiled surface requirements.
1230 i915_gem_get_unfenced_gtt_alignment(struct drm_device
*dev
,
1235 * Minimum alignment is 4k (GTT page size) for sane hw.
1237 if (INTEL_INFO(dev
)->gen
>= 4 || IS_G33(dev
) ||
1238 tiling_mode
== I915_TILING_NONE
)
1241 /* Previous hardware however needs to be aligned to a power-of-two
1242 * tile height. The simplest method for determining this is to reuse
1243 * the power-of-tile object size.
1245 return i915_gem_get_gtt_size(dev
, size
, tiling_mode
);
1249 i915_gem_mmap_gtt(struct drm_file
*file
,
1250 struct drm_device
*dev
,
1254 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1255 struct drm_i915_gem_object
*obj
;
1258 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1261 ret
= i915_mutex_lock_interruptible(dev
);
1265 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, handle
));
1266 if (&obj
->base
== NULL
) {
1271 if (obj
->base
.size
> dev_priv
->mm
.gtt_mappable_end
) {
1276 if (obj
->madv
!= I915_MADV_WILLNEED
) {
1277 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1282 if (!obj
->base
.map_list
.map
) {
1283 ret
= drm_gem_create_mmap_offset(&obj
->base
);
1288 *offset
= (u64
)obj
->base
.map_list
.hash
.key
<< PAGE_SHIFT
;
1291 drm_gem_object_unreference(&obj
->base
);
1293 mutex_unlock(&dev
->struct_mutex
);
1298 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1300 * @data: GTT mapping ioctl data
1301 * @file: GEM object info
1303 * Simply returns the fake offset to userspace so it can mmap it.
1304 * The mmap call will end up in drm_gem_mmap(), which will set things
1305 * up so we can get faults in the handler above.
1307 * The fault handler will take care of binding the object into the GTT
1308 * (since it may have been evicted to make room for something), allocating
1309 * a fence register, and mapping the appropriate aperture address into
1313 i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
1314 struct drm_file
*file
)
1316 struct drm_i915_gem_mmap_gtt
*args
= data
;
1318 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1321 return i915_gem_mmap_gtt(file
, dev
, args
->handle
, &args
->offset
);
1326 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object
*obj
,
1330 struct address_space
*mapping
;
1331 struct inode
*inode
;
1334 /* Get the list of pages out of our struct file. They'll be pinned
1335 * at this point until we release them.
1337 page_count
= obj
->base
.size
/ PAGE_SIZE
;
1338 BUG_ON(obj
->pages
!= NULL
);
1339 obj
->pages
= drm_malloc_ab(page_count
, sizeof(struct page
*));
1340 if (obj
->pages
== NULL
)
1343 inode
= obj
->base
.filp
->f_path
.dentry
->d_inode
;
1344 mapping
= inode
->i_mapping
;
1345 gfpmask
|= mapping_gfp_mask(mapping
);
1347 for (i
= 0; i
< page_count
; i
++) {
1348 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfpmask
);
1352 obj
->pages
[i
] = page
;
1355 if (i915_gem_object_needs_bit17_swizzle(obj
))
1356 i915_gem_object_do_bit_17_swizzle(obj
);
1362 page_cache_release(obj
->pages
[i
]);
1364 drm_free_large(obj
->pages
);
1366 return PTR_ERR(page
);
1370 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object
*obj
)
1372 int page_count
= obj
->base
.size
/ PAGE_SIZE
;
1375 BUG_ON(obj
->madv
== __I915_MADV_PURGED
);
1377 if (i915_gem_object_needs_bit17_swizzle(obj
))
1378 i915_gem_object_save_bit_17_swizzle(obj
);
1380 if (obj
->madv
== I915_MADV_DONTNEED
)
1383 for (i
= 0; i
< page_count
; i
++) {
1385 set_page_dirty(obj
->pages
[i
]);
1387 if (obj
->madv
== I915_MADV_WILLNEED
)
1388 mark_page_accessed(obj
->pages
[i
]);
1390 page_cache_release(obj
->pages
[i
]);
1394 drm_free_large(obj
->pages
);
1399 i915_gem_object_move_to_active(struct drm_i915_gem_object
*obj
,
1400 struct intel_ring_buffer
*ring
,
1403 struct drm_device
*dev
= obj
->base
.dev
;
1404 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1406 BUG_ON(ring
== NULL
);
1409 /* Add a reference if we're newly entering the active list. */
1411 drm_gem_object_reference(&obj
->base
);
1415 /* Move from whatever list we were on to the tail of execution. */
1416 list_move_tail(&obj
->mm_list
, &dev_priv
->mm
.active_list
);
1417 list_move_tail(&obj
->ring_list
, &ring
->active_list
);
1419 obj
->last_rendering_seqno
= seqno
;
1421 if (obj
->fenced_gpu_access
) {
1422 obj
->last_fenced_seqno
= seqno
;
1424 /* Bump MRU to take account of the delayed flush */
1425 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
1426 struct drm_i915_fence_reg
*reg
;
1428 reg
= &dev_priv
->fence_regs
[obj
->fence_reg
];
1429 list_move_tail(®
->lru_list
,
1430 &dev_priv
->mm
.fence_list
);
1436 i915_gem_object_move_off_active(struct drm_i915_gem_object
*obj
)
1438 list_del_init(&obj
->ring_list
);
1439 obj
->last_rendering_seqno
= 0;
1440 obj
->last_fenced_seqno
= 0;
1444 i915_gem_object_move_to_flushing(struct drm_i915_gem_object
*obj
)
1446 struct drm_device
*dev
= obj
->base
.dev
;
1447 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1449 BUG_ON(!obj
->active
);
1450 list_move_tail(&obj
->mm_list
, &dev_priv
->mm
.flushing_list
);
1452 i915_gem_object_move_off_active(obj
);
1456 i915_gem_object_move_to_inactive(struct drm_i915_gem_object
*obj
)
1458 struct drm_device
*dev
= obj
->base
.dev
;
1459 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1461 list_move_tail(&obj
->mm_list
, &dev_priv
->mm
.inactive_list
);
1463 BUG_ON(!list_empty(&obj
->gpu_write_list
));
1464 BUG_ON(!obj
->active
);
1467 i915_gem_object_move_off_active(obj
);
1468 obj
->fenced_gpu_access
= false;
1471 obj
->pending_gpu_write
= false;
1472 drm_gem_object_unreference(&obj
->base
);
1474 WARN_ON(i915_verify_lists(dev
));
1477 /* Immediately discard the backing storage */
1479 i915_gem_object_truncate(struct drm_i915_gem_object
*obj
)
1481 struct inode
*inode
;
1483 /* Our goal here is to return as much of the memory as
1484 * is possible back to the system as we are called from OOM.
1485 * To do this we must instruct the shmfs to drop all of its
1486 * backing pages, *now*.
1488 inode
= obj
->base
.filp
->f_path
.dentry
->d_inode
;
1489 shmem_truncate_range(inode
, 0, (loff_t
)-1);
1491 if (obj
->base
.map_list
.map
)
1492 drm_gem_free_mmap_offset(&obj
->base
);
1494 obj
->madv
= __I915_MADV_PURGED
;
1498 i915_gem_object_is_purgeable(struct drm_i915_gem_object
*obj
)
1500 return obj
->madv
== I915_MADV_DONTNEED
;
1504 i915_gem_process_flushing_list(struct intel_ring_buffer
*ring
,
1505 uint32_t flush_domains
)
1507 struct drm_i915_gem_object
*obj
, *next
;
1509 list_for_each_entry_safe(obj
, next
,
1510 &ring
->gpu_write_list
,
1512 if (obj
->base
.write_domain
& flush_domains
) {
1513 uint32_t old_write_domain
= obj
->base
.write_domain
;
1515 obj
->base
.write_domain
= 0;
1516 list_del_init(&obj
->gpu_write_list
);
1517 i915_gem_object_move_to_active(obj
, ring
,
1518 i915_gem_next_request_seqno(ring
));
1520 trace_i915_gem_object_change_domain(obj
,
1521 obj
->base
.read_domains
,
1528 i915_gem_get_seqno(struct drm_device
*dev
)
1530 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1531 u32 seqno
= dev_priv
->next_seqno
;
1533 /* reserve 0 for non-seqno */
1534 if (++dev_priv
->next_seqno
== 0)
1535 dev_priv
->next_seqno
= 1;
1541 i915_gem_next_request_seqno(struct intel_ring_buffer
*ring
)
1543 if (ring
->outstanding_lazy_request
== 0)
1544 ring
->outstanding_lazy_request
= i915_gem_get_seqno(ring
->dev
);
1546 return ring
->outstanding_lazy_request
;
1550 i915_add_request(struct intel_ring_buffer
*ring
,
1551 struct drm_file
*file
,
1552 struct drm_i915_gem_request
*request
)
1554 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
1556 u32 request_ring_position
;
1560 BUG_ON(request
== NULL
);
1561 seqno
= i915_gem_next_request_seqno(ring
);
1563 /* Record the position of the start of the request so that
1564 * should we detect the updated seqno part-way through the
1565 * GPU processing the request, we never over-estimate the
1566 * position of the head.
1568 request_ring_position
= intel_ring_get_tail(ring
);
1570 ret
= ring
->add_request(ring
, &seqno
);
1574 trace_i915_gem_request_add(ring
, seqno
);
1576 request
->seqno
= seqno
;
1577 request
->ring
= ring
;
1578 request
->tail
= request_ring_position
;
1579 request
->emitted_jiffies
= jiffies
;
1580 was_empty
= list_empty(&ring
->request_list
);
1581 list_add_tail(&request
->list
, &ring
->request_list
);
1584 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
1586 spin_lock(&file_priv
->mm
.lock
);
1587 request
->file_priv
= file_priv
;
1588 list_add_tail(&request
->client_list
,
1589 &file_priv
->mm
.request_list
);
1590 spin_unlock(&file_priv
->mm
.lock
);
1593 ring
->outstanding_lazy_request
= 0;
1595 if (!dev_priv
->mm
.suspended
) {
1596 if (i915_enable_hangcheck
) {
1597 mod_timer(&dev_priv
->hangcheck_timer
,
1599 msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD
));
1602 queue_delayed_work(dev_priv
->wq
,
1603 &dev_priv
->mm
.retire_work
, HZ
);
1609 i915_gem_request_remove_from_client(struct drm_i915_gem_request
*request
)
1611 struct drm_i915_file_private
*file_priv
= request
->file_priv
;
1616 spin_lock(&file_priv
->mm
.lock
);
1617 if (request
->file_priv
) {
1618 list_del(&request
->client_list
);
1619 request
->file_priv
= NULL
;
1621 spin_unlock(&file_priv
->mm
.lock
);
1624 static void i915_gem_reset_ring_lists(struct drm_i915_private
*dev_priv
,
1625 struct intel_ring_buffer
*ring
)
1627 while (!list_empty(&ring
->request_list
)) {
1628 struct drm_i915_gem_request
*request
;
1630 request
= list_first_entry(&ring
->request_list
,
1631 struct drm_i915_gem_request
,
1634 list_del(&request
->list
);
1635 i915_gem_request_remove_from_client(request
);
1639 while (!list_empty(&ring
->active_list
)) {
1640 struct drm_i915_gem_object
*obj
;
1642 obj
= list_first_entry(&ring
->active_list
,
1643 struct drm_i915_gem_object
,
1646 obj
->base
.write_domain
= 0;
1647 list_del_init(&obj
->gpu_write_list
);
1648 i915_gem_object_move_to_inactive(obj
);
1652 static void i915_gem_reset_fences(struct drm_device
*dev
)
1654 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1657 for (i
= 0; i
< dev_priv
->num_fence_regs
; i
++) {
1658 struct drm_i915_fence_reg
*reg
= &dev_priv
->fence_regs
[i
];
1660 i915_gem_write_fence(dev
, i
, NULL
);
1663 i915_gem_object_fence_lost(reg
->obj
);
1667 INIT_LIST_HEAD(®
->lru_list
);
1670 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
1673 void i915_gem_reset(struct drm_device
*dev
)
1675 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1676 struct drm_i915_gem_object
*obj
;
1679 for (i
= 0; i
< I915_NUM_RINGS
; i
++)
1680 i915_gem_reset_ring_lists(dev_priv
, &dev_priv
->ring
[i
]);
1682 /* Remove anything from the flushing lists. The GPU cache is likely
1683 * to be lost on reset along with the data, so simply move the
1684 * lost bo to the inactive list.
1686 while (!list_empty(&dev_priv
->mm
.flushing_list
)) {
1687 obj
= list_first_entry(&dev_priv
->mm
.flushing_list
,
1688 struct drm_i915_gem_object
,
1691 obj
->base
.write_domain
= 0;
1692 list_del_init(&obj
->gpu_write_list
);
1693 i915_gem_object_move_to_inactive(obj
);
1696 /* Move everything out of the GPU domains to ensure we do any
1697 * necessary invalidation upon reuse.
1699 list_for_each_entry(obj
,
1700 &dev_priv
->mm
.inactive_list
,
1703 obj
->base
.read_domains
&= ~I915_GEM_GPU_DOMAINS
;
1706 /* The fence registers are invalidated so clear them out */
1707 i915_gem_reset_fences(dev
);
1711 * This function clears the request list as sequence numbers are passed.
1714 i915_gem_retire_requests_ring(struct intel_ring_buffer
*ring
)
1719 if (list_empty(&ring
->request_list
))
1722 WARN_ON(i915_verify_lists(ring
->dev
));
1724 seqno
= ring
->get_seqno(ring
);
1726 for (i
= 0; i
< ARRAY_SIZE(ring
->sync_seqno
); i
++)
1727 if (seqno
>= ring
->sync_seqno
[i
])
1728 ring
->sync_seqno
[i
] = 0;
1730 while (!list_empty(&ring
->request_list
)) {
1731 struct drm_i915_gem_request
*request
;
1733 request
= list_first_entry(&ring
->request_list
,
1734 struct drm_i915_gem_request
,
1737 if (!i915_seqno_passed(seqno
, request
->seqno
))
1740 trace_i915_gem_request_retire(ring
, request
->seqno
);
1741 /* We know the GPU must have read the request to have
1742 * sent us the seqno + interrupt, so use the position
1743 * of tail of the request to update the last known position
1746 ring
->last_retired_head
= request
->tail
;
1748 list_del(&request
->list
);
1749 i915_gem_request_remove_from_client(request
);
1753 /* Move any buffers on the active list that are no longer referenced
1754 * by the ringbuffer to the flushing/inactive lists as appropriate.
1756 while (!list_empty(&ring
->active_list
)) {
1757 struct drm_i915_gem_object
*obj
;
1759 obj
= list_first_entry(&ring
->active_list
,
1760 struct drm_i915_gem_object
,
1763 if (!i915_seqno_passed(seqno
, obj
->last_rendering_seqno
))
1766 if (obj
->base
.write_domain
!= 0)
1767 i915_gem_object_move_to_flushing(obj
);
1769 i915_gem_object_move_to_inactive(obj
);
1772 if (unlikely(ring
->trace_irq_seqno
&&
1773 i915_seqno_passed(seqno
, ring
->trace_irq_seqno
))) {
1774 ring
->irq_put(ring
);
1775 ring
->trace_irq_seqno
= 0;
1778 WARN_ON(i915_verify_lists(ring
->dev
));
1782 i915_gem_retire_requests(struct drm_device
*dev
)
1784 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1787 for (i
= 0; i
< I915_NUM_RINGS
; i
++)
1788 i915_gem_retire_requests_ring(&dev_priv
->ring
[i
]);
1792 i915_gem_retire_work_handler(struct work_struct
*work
)
1794 drm_i915_private_t
*dev_priv
;
1795 struct drm_device
*dev
;
1799 dev_priv
= container_of(work
, drm_i915_private_t
,
1800 mm
.retire_work
.work
);
1801 dev
= dev_priv
->dev
;
1803 /* Come back later if the device is busy... */
1804 if (!mutex_trylock(&dev
->struct_mutex
)) {
1805 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, HZ
);
1809 i915_gem_retire_requests(dev
);
1811 /* Send a periodic flush down the ring so we don't hold onto GEM
1812 * objects indefinitely.
1815 for (i
= 0; i
< I915_NUM_RINGS
; i
++) {
1816 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[i
];
1818 if (!list_empty(&ring
->gpu_write_list
)) {
1819 struct drm_i915_gem_request
*request
;
1822 ret
= i915_gem_flush_ring(ring
,
1823 0, I915_GEM_GPU_DOMAINS
);
1824 request
= kzalloc(sizeof(*request
), GFP_KERNEL
);
1825 if (ret
|| request
== NULL
||
1826 i915_add_request(ring
, NULL
, request
))
1830 idle
&= list_empty(&ring
->request_list
);
1833 if (!dev_priv
->mm
.suspended
&& !idle
)
1834 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, HZ
);
1836 mutex_unlock(&dev
->struct_mutex
);
1840 * Waits for a sequence number to be signaled, and cleans up the
1841 * request and object lists appropriately for that event.
1844 i915_wait_request(struct intel_ring_buffer
*ring
,
1848 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
1854 if (atomic_read(&dev_priv
->mm
.wedged
)) {
1855 struct completion
*x
= &dev_priv
->error_completion
;
1856 bool recovery_complete
;
1857 unsigned long flags
;
1859 /* Give the error handler a chance to run. */
1860 spin_lock_irqsave(&x
->wait
.lock
, flags
);
1861 recovery_complete
= x
->done
> 0;
1862 spin_unlock_irqrestore(&x
->wait
.lock
, flags
);
1864 return recovery_complete
? -EIO
: -EAGAIN
;
1867 if (seqno
== ring
->outstanding_lazy_request
) {
1868 struct drm_i915_gem_request
*request
;
1870 request
= kzalloc(sizeof(*request
), GFP_KERNEL
);
1871 if (request
== NULL
)
1874 ret
= i915_add_request(ring
, NULL
, request
);
1880 seqno
= request
->seqno
;
1883 if (!i915_seqno_passed(ring
->get_seqno(ring
), seqno
)) {
1884 if (HAS_PCH_SPLIT(ring
->dev
))
1885 ier
= I915_READ(DEIER
) | I915_READ(GTIER
);
1886 else if (IS_VALLEYVIEW(ring
->dev
))
1887 ier
= I915_READ(GTIER
) | I915_READ(VLV_IER
);
1889 ier
= I915_READ(IER
);
1891 DRM_ERROR("something (likely vbetool) disabled "
1892 "interrupts, re-enabling\n");
1893 ring
->dev
->driver
->irq_preinstall(ring
->dev
);
1894 ring
->dev
->driver
->irq_postinstall(ring
->dev
);
1897 trace_i915_gem_request_wait_begin(ring
, seqno
);
1899 ring
->waiting_seqno
= seqno
;
1900 if (ring
->irq_get(ring
)) {
1901 if (dev_priv
->mm
.interruptible
)
1902 ret
= wait_event_interruptible(ring
->irq_queue
,
1903 i915_seqno_passed(ring
->get_seqno(ring
), seqno
)
1904 || atomic_read(&dev_priv
->mm
.wedged
));
1906 wait_event(ring
->irq_queue
,
1907 i915_seqno_passed(ring
->get_seqno(ring
), seqno
)
1908 || atomic_read(&dev_priv
->mm
.wedged
));
1910 ring
->irq_put(ring
);
1911 } else if (wait_for_atomic(i915_seqno_passed(ring
->get_seqno(ring
),
1913 atomic_read(&dev_priv
->mm
.wedged
), 3000))
1915 ring
->waiting_seqno
= 0;
1917 trace_i915_gem_request_wait_end(ring
, seqno
);
1919 if (atomic_read(&dev_priv
->mm
.wedged
))
1922 /* Directly dispatch request retiring. While we have the work queue
1923 * to handle this, the waiter on a request often wants an associated
1924 * buffer to have made it to the inactive list, and we would need
1925 * a separate wait queue to handle that.
1927 if (ret
== 0 && do_retire
)
1928 i915_gem_retire_requests_ring(ring
);
1934 * Ensures that all rendering to the object has completed and the object is
1935 * safe to unbind from the GTT or access from the CPU.
1938 i915_gem_object_wait_rendering(struct drm_i915_gem_object
*obj
)
1942 /* This function only exists to support waiting for existing rendering,
1943 * not for emitting required flushes.
1945 BUG_ON((obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
) != 0);
1947 /* If there is rendering queued on the buffer being evicted, wait for
1951 ret
= i915_wait_request(obj
->ring
, obj
->last_rendering_seqno
,
1961 * i915_gem_object_sync - sync an object to a ring.
1963 * @obj: object which may be in use on another ring.
1964 * @to: ring we wish to use the object on. May be NULL.
1966 * This code is meant to abstract object synchronization with the GPU.
1967 * Calling with NULL implies synchronizing the object with the CPU
1968 * rather than a particular GPU ring.
1970 * Returns 0 if successful, else propagates up the lower layer error.
1973 i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
1974 struct intel_ring_buffer
*to
)
1976 struct intel_ring_buffer
*from
= obj
->ring
;
1980 if (from
== NULL
|| to
== from
)
1983 if (to
== NULL
|| !i915_semaphore_is_enabled(obj
->base
.dev
))
1984 return i915_gem_object_wait_rendering(obj
);
1986 idx
= intel_ring_sync_index(from
, to
);
1988 seqno
= obj
->last_rendering_seqno
;
1989 if (seqno
<= from
->sync_seqno
[idx
])
1992 if (seqno
== from
->outstanding_lazy_request
) {
1993 struct drm_i915_gem_request
*request
;
1995 request
= kzalloc(sizeof(*request
), GFP_KERNEL
);
1996 if (request
== NULL
)
1999 ret
= i915_add_request(from
, NULL
, request
);
2005 seqno
= request
->seqno
;
2009 ret
= to
->sync_to(to
, from
, seqno
);
2011 from
->sync_seqno
[idx
] = seqno
;
2016 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object
*obj
)
2018 u32 old_write_domain
, old_read_domains
;
2020 /* Act a barrier for all accesses through the GTT */
2023 /* Force a pagefault for domain tracking on next user access */
2024 i915_gem_release_mmap(obj
);
2026 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
) == 0)
2029 old_read_domains
= obj
->base
.read_domains
;
2030 old_write_domain
= obj
->base
.write_domain
;
2032 obj
->base
.read_domains
&= ~I915_GEM_DOMAIN_GTT
;
2033 obj
->base
.write_domain
&= ~I915_GEM_DOMAIN_GTT
;
2035 trace_i915_gem_object_change_domain(obj
,
2041 * Unbinds an object from the GTT aperture.
2044 i915_gem_object_unbind(struct drm_i915_gem_object
*obj
)
2046 drm_i915_private_t
*dev_priv
= obj
->base
.dev
->dev_private
;
2049 if (obj
->gtt_space
== NULL
)
2052 if (obj
->pin_count
!= 0) {
2053 DRM_ERROR("Attempting to unbind pinned buffer\n");
2057 ret
= i915_gem_object_finish_gpu(obj
);
2060 /* Continue on if we fail due to EIO, the GPU is hung so we
2061 * should be safe and we need to cleanup or else we might
2062 * cause memory corruption through use-after-free.
2065 i915_gem_object_finish_gtt(obj
);
2067 /* Move the object to the CPU domain to ensure that
2068 * any possible CPU writes while it's not in the GTT
2069 * are flushed when we go to remap it.
2072 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
2073 if (ret
== -ERESTARTSYS
)
2076 /* In the event of a disaster, abandon all caches and
2077 * hope for the best.
2079 i915_gem_clflush_object(obj
);
2080 obj
->base
.read_domains
= obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
2083 /* release the fence reg _after_ flushing */
2084 ret
= i915_gem_object_put_fence(obj
);
2088 trace_i915_gem_object_unbind(obj
);
2090 if (obj
->has_global_gtt_mapping
)
2091 i915_gem_gtt_unbind_object(obj
);
2092 if (obj
->has_aliasing_ppgtt_mapping
) {
2093 i915_ppgtt_unbind_object(dev_priv
->mm
.aliasing_ppgtt
, obj
);
2094 obj
->has_aliasing_ppgtt_mapping
= 0;
2096 i915_gem_gtt_finish_object(obj
);
2098 i915_gem_object_put_pages_gtt(obj
);
2100 list_del_init(&obj
->gtt_list
);
2101 list_del_init(&obj
->mm_list
);
2102 /* Avoid an unnecessary call to unbind on rebind. */
2103 obj
->map_and_fenceable
= true;
2105 drm_mm_put_block(obj
->gtt_space
);
2106 obj
->gtt_space
= NULL
;
2107 obj
->gtt_offset
= 0;
2109 if (i915_gem_object_is_purgeable(obj
))
2110 i915_gem_object_truncate(obj
);
2116 i915_gem_flush_ring(struct intel_ring_buffer
*ring
,
2117 uint32_t invalidate_domains
,
2118 uint32_t flush_domains
)
2122 if (((invalidate_domains
| flush_domains
) & I915_GEM_GPU_DOMAINS
) == 0)
2125 trace_i915_gem_ring_flush(ring
, invalidate_domains
, flush_domains
);
2127 ret
= ring
->flush(ring
, invalidate_domains
, flush_domains
);
2131 if (flush_domains
& I915_GEM_GPU_DOMAINS
)
2132 i915_gem_process_flushing_list(ring
, flush_domains
);
2137 static int i915_ring_idle(struct intel_ring_buffer
*ring
, bool do_retire
)
2141 if (list_empty(&ring
->gpu_write_list
) && list_empty(&ring
->active_list
))
2144 if (!list_empty(&ring
->gpu_write_list
)) {
2145 ret
= i915_gem_flush_ring(ring
,
2146 I915_GEM_GPU_DOMAINS
, I915_GEM_GPU_DOMAINS
);
2151 return i915_wait_request(ring
, i915_gem_next_request_seqno(ring
),
2155 int i915_gpu_idle(struct drm_device
*dev
, bool do_retire
)
2157 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2160 /* Flush everything onto the inactive list. */
2161 for (i
= 0; i
< I915_NUM_RINGS
; i
++) {
2162 ret
= i915_ring_idle(&dev_priv
->ring
[i
], do_retire
);
2170 static void sandybridge_write_fence_reg(struct drm_device
*dev
, int reg
,
2171 struct drm_i915_gem_object
*obj
)
2173 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2177 u32 size
= obj
->gtt_space
->size
;
2179 val
= (uint64_t)((obj
->gtt_offset
+ size
- 4096) &
2181 val
|= obj
->gtt_offset
& 0xfffff000;
2182 val
|= (uint64_t)((obj
->stride
/ 128) - 1) <<
2183 SANDYBRIDGE_FENCE_PITCH_SHIFT
;
2185 if (obj
->tiling_mode
== I915_TILING_Y
)
2186 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
2187 val
|= I965_FENCE_REG_VALID
;
2191 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0
+ reg
* 8, val
);
2192 POSTING_READ(FENCE_REG_SANDYBRIDGE_0
+ reg
* 8);
2195 static void i965_write_fence_reg(struct drm_device
*dev
, int reg
,
2196 struct drm_i915_gem_object
*obj
)
2198 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2202 u32 size
= obj
->gtt_space
->size
;
2204 val
= (uint64_t)((obj
->gtt_offset
+ size
- 4096) &
2206 val
|= obj
->gtt_offset
& 0xfffff000;
2207 val
|= ((obj
->stride
/ 128) - 1) << I965_FENCE_PITCH_SHIFT
;
2208 if (obj
->tiling_mode
== I915_TILING_Y
)
2209 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
2210 val
|= I965_FENCE_REG_VALID
;
2214 I915_WRITE64(FENCE_REG_965_0
+ reg
* 8, val
);
2215 POSTING_READ(FENCE_REG_965_0
+ reg
* 8);
2218 static void i915_write_fence_reg(struct drm_device
*dev
, int reg
,
2219 struct drm_i915_gem_object
*obj
)
2221 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2225 u32 size
= obj
->gtt_space
->size
;
2229 WARN((obj
->gtt_offset
& ~I915_FENCE_START_MASK
) ||
2230 (size
& -size
) != size
||
2231 (obj
->gtt_offset
& (size
- 1)),
2232 "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2233 obj
->gtt_offset
, obj
->map_and_fenceable
, size
);
2235 if (obj
->tiling_mode
== I915_TILING_Y
&& HAS_128_BYTE_Y_TILING(dev
))
2240 /* Note: pitch better be a power of two tile widths */
2241 pitch_val
= obj
->stride
/ tile_width
;
2242 pitch_val
= ffs(pitch_val
) - 1;
2244 val
= obj
->gtt_offset
;
2245 if (obj
->tiling_mode
== I915_TILING_Y
)
2246 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2247 val
|= I915_FENCE_SIZE_BITS(size
);
2248 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2249 val
|= I830_FENCE_REG_VALID
;
2254 reg
= FENCE_REG_830_0
+ reg
* 4;
2256 reg
= FENCE_REG_945_8
+ (reg
- 8) * 4;
2258 I915_WRITE(reg
, val
);
2262 static void i830_write_fence_reg(struct drm_device
*dev
, int reg
,
2263 struct drm_i915_gem_object
*obj
)
2265 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2269 u32 size
= obj
->gtt_space
->size
;
2272 WARN((obj
->gtt_offset
& ~I830_FENCE_START_MASK
) ||
2273 (size
& -size
) != size
||
2274 (obj
->gtt_offset
& (size
- 1)),
2275 "object 0x%08x not 512K or pot-size 0x%08x aligned\n",
2276 obj
->gtt_offset
, size
);
2278 pitch_val
= obj
->stride
/ 128;
2279 pitch_val
= ffs(pitch_val
) - 1;
2281 val
= obj
->gtt_offset
;
2282 if (obj
->tiling_mode
== I915_TILING_Y
)
2283 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2284 val
|= I830_FENCE_SIZE_BITS(size
);
2285 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2286 val
|= I830_FENCE_REG_VALID
;
2290 I915_WRITE(FENCE_REG_830_0
+ reg
* 4, val
);
2291 POSTING_READ(FENCE_REG_830_0
+ reg
* 4);
2294 static void i915_gem_write_fence(struct drm_device
*dev
, int reg
,
2295 struct drm_i915_gem_object
*obj
)
2297 switch (INTEL_INFO(dev
)->gen
) {
2299 case 6: sandybridge_write_fence_reg(dev
, reg
, obj
); break;
2301 case 4: i965_write_fence_reg(dev
, reg
, obj
); break;
2302 case 3: i915_write_fence_reg(dev
, reg
, obj
); break;
2303 case 2: i830_write_fence_reg(dev
, reg
, obj
); break;
2308 static inline int fence_number(struct drm_i915_private
*dev_priv
,
2309 struct drm_i915_fence_reg
*fence
)
2311 return fence
- dev_priv
->fence_regs
;
2314 static void i915_gem_object_update_fence(struct drm_i915_gem_object
*obj
,
2315 struct drm_i915_fence_reg
*fence
,
2318 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2319 int reg
= fence_number(dev_priv
, fence
);
2321 i915_gem_write_fence(obj
->base
.dev
, reg
, enable
? obj
: NULL
);
2324 obj
->fence_reg
= reg
;
2326 list_move_tail(&fence
->lru_list
, &dev_priv
->mm
.fence_list
);
2328 obj
->fence_reg
= I915_FENCE_REG_NONE
;
2330 list_del_init(&fence
->lru_list
);
2335 i915_gem_object_flush_fence(struct drm_i915_gem_object
*obj
)
2339 if (obj
->fenced_gpu_access
) {
2340 if (obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
) {
2341 ret
= i915_gem_flush_ring(obj
->ring
,
2342 0, obj
->base
.write_domain
);
2347 obj
->fenced_gpu_access
= false;
2350 if (obj
->last_fenced_seqno
) {
2351 ret
= i915_wait_request(obj
->ring
,
2352 obj
->last_fenced_seqno
,
2357 obj
->last_fenced_seqno
= 0;
2360 /* Ensure that all CPU reads are completed before installing a fence
2361 * and all writes before removing the fence.
2363 if (obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
)
2370 i915_gem_object_put_fence(struct drm_i915_gem_object
*obj
)
2372 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2375 ret
= i915_gem_object_flush_fence(obj
);
2379 if (obj
->fence_reg
== I915_FENCE_REG_NONE
)
2382 i915_gem_object_update_fence(obj
,
2383 &dev_priv
->fence_regs
[obj
->fence_reg
],
2385 i915_gem_object_fence_lost(obj
);
2390 static struct drm_i915_fence_reg
*
2391 i915_find_fence_reg(struct drm_device
*dev
)
2393 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2394 struct drm_i915_fence_reg
*reg
, *avail
;
2397 /* First try to find a free reg */
2399 for (i
= dev_priv
->fence_reg_start
; i
< dev_priv
->num_fence_regs
; i
++) {
2400 reg
= &dev_priv
->fence_regs
[i
];
2404 if (!reg
->pin_count
)
2411 /* None available, try to steal one or wait for a user to finish */
2412 list_for_each_entry(reg
, &dev_priv
->mm
.fence_list
, lru_list
) {
2423 * i915_gem_object_get_fence - set up fencing for an object
2424 * @obj: object to map through a fence reg
2426 * When mapping objects through the GTT, userspace wants to be able to write
2427 * to them without having to worry about swizzling if the object is tiled.
2428 * This function walks the fence regs looking for a free one for @obj,
2429 * stealing one if it can't find any.
2431 * It then sets up the reg based on the object's properties: address, pitch
2432 * and tiling format.
2434 * For an untiled surface, this removes any existing fence.
2437 i915_gem_object_get_fence(struct drm_i915_gem_object
*obj
)
2439 struct drm_device
*dev
= obj
->base
.dev
;
2440 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2441 bool enable
= obj
->tiling_mode
!= I915_TILING_NONE
;
2442 struct drm_i915_fence_reg
*reg
;
2445 /* Have we updated the tiling parameters upon the object and so
2446 * will need to serialise the write to the associated fence register?
2448 if (obj
->fence_dirty
) {
2449 ret
= i915_gem_object_flush_fence(obj
);
2454 /* Just update our place in the LRU if our fence is getting reused. */
2455 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
2456 reg
= &dev_priv
->fence_regs
[obj
->fence_reg
];
2457 if (!obj
->fence_dirty
) {
2458 list_move_tail(®
->lru_list
,
2459 &dev_priv
->mm
.fence_list
);
2462 } else if (enable
) {
2463 reg
= i915_find_fence_reg(dev
);
2468 struct drm_i915_gem_object
*old
= reg
->obj
;
2470 ret
= i915_gem_object_flush_fence(old
);
2474 i915_gem_object_fence_lost(old
);
2479 i915_gem_object_update_fence(obj
, reg
, enable
);
2480 obj
->fence_dirty
= false;
2486 * Finds free space in the GTT aperture and binds the object there.
2489 i915_gem_object_bind_to_gtt(struct drm_i915_gem_object
*obj
,
2491 bool map_and_fenceable
)
2493 struct drm_device
*dev
= obj
->base
.dev
;
2494 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2495 struct drm_mm_node
*free_space
;
2496 gfp_t gfpmask
= __GFP_NORETRY
| __GFP_NOWARN
;
2497 u32 size
, fence_size
, fence_alignment
, unfenced_alignment
;
2498 bool mappable
, fenceable
;
2501 if (obj
->madv
!= I915_MADV_WILLNEED
) {
2502 DRM_ERROR("Attempting to bind a purgeable object\n");
2506 fence_size
= i915_gem_get_gtt_size(dev
,
2509 fence_alignment
= i915_gem_get_gtt_alignment(dev
,
2512 unfenced_alignment
=
2513 i915_gem_get_unfenced_gtt_alignment(dev
,
2518 alignment
= map_and_fenceable
? fence_alignment
:
2520 if (map_and_fenceable
&& alignment
& (fence_alignment
- 1)) {
2521 DRM_ERROR("Invalid object alignment requested %u\n", alignment
);
2525 size
= map_and_fenceable
? fence_size
: obj
->base
.size
;
2527 /* If the object is bigger than the entire aperture, reject it early
2528 * before evicting everything in a vain attempt to find space.
2530 if (obj
->base
.size
>
2531 (map_and_fenceable
? dev_priv
->mm
.gtt_mappable_end
: dev_priv
->mm
.gtt_total
)) {
2532 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2537 if (map_and_fenceable
)
2539 drm_mm_search_free_in_range(&dev_priv
->mm
.gtt_space
,
2541 dev_priv
->mm
.gtt_mappable_end
,
2544 free_space
= drm_mm_search_free(&dev_priv
->mm
.gtt_space
,
2545 size
, alignment
, 0);
2547 if (free_space
!= NULL
) {
2548 if (map_and_fenceable
)
2550 drm_mm_get_block_range_generic(free_space
,
2552 dev_priv
->mm
.gtt_mappable_end
,
2556 drm_mm_get_block(free_space
, size
, alignment
);
2558 if (obj
->gtt_space
== NULL
) {
2559 /* If the gtt is empty and we're still having trouble
2560 * fitting our object in, we're out of memory.
2562 ret
= i915_gem_evict_something(dev
, size
, alignment
,
2570 ret
= i915_gem_object_get_pages_gtt(obj
, gfpmask
);
2572 drm_mm_put_block(obj
->gtt_space
);
2573 obj
->gtt_space
= NULL
;
2575 if (ret
== -ENOMEM
) {
2576 /* first try to reclaim some memory by clearing the GTT */
2577 ret
= i915_gem_evict_everything(dev
, false);
2579 /* now try to shrink everyone else */
2594 ret
= i915_gem_gtt_prepare_object(obj
);
2596 i915_gem_object_put_pages_gtt(obj
);
2597 drm_mm_put_block(obj
->gtt_space
);
2598 obj
->gtt_space
= NULL
;
2600 if (i915_gem_evict_everything(dev
, false))
2606 if (!dev_priv
->mm
.aliasing_ppgtt
)
2607 i915_gem_gtt_bind_object(obj
, obj
->cache_level
);
2609 list_add_tail(&obj
->gtt_list
, &dev_priv
->mm
.gtt_list
);
2610 list_add_tail(&obj
->mm_list
, &dev_priv
->mm
.inactive_list
);
2612 /* Assert that the object is not currently in any GPU domain. As it
2613 * wasn't in the GTT, there shouldn't be any way it could have been in
2616 BUG_ON(obj
->base
.read_domains
& I915_GEM_GPU_DOMAINS
);
2617 BUG_ON(obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
);
2619 obj
->gtt_offset
= obj
->gtt_space
->start
;
2622 obj
->gtt_space
->size
== fence_size
&&
2623 (obj
->gtt_space
->start
& (fence_alignment
- 1)) == 0;
2626 obj
->gtt_offset
+ obj
->base
.size
<= dev_priv
->mm
.gtt_mappable_end
;
2628 obj
->map_and_fenceable
= mappable
&& fenceable
;
2630 trace_i915_gem_object_bind(obj
, map_and_fenceable
);
2635 i915_gem_clflush_object(struct drm_i915_gem_object
*obj
)
2637 /* If we don't have a page list set up, then we're not pinned
2638 * to GPU, and we can ignore the cache flush because it'll happen
2639 * again at bind time.
2641 if (obj
->pages
== NULL
)
2644 /* If the GPU is snooping the contents of the CPU cache,
2645 * we do not need to manually clear the CPU cache lines. However,
2646 * the caches are only snooped when the render cache is
2647 * flushed/invalidated. As we always have to emit invalidations
2648 * and flushes when moving into and out of the RENDER domain, correct
2649 * snooping behaviour occurs naturally as the result of our domain
2652 if (obj
->cache_level
!= I915_CACHE_NONE
)
2655 trace_i915_gem_object_clflush(obj
);
2657 drm_clflush_pages(obj
->pages
, obj
->base
.size
/ PAGE_SIZE
);
2660 /** Flushes any GPU write domain for the object if it's dirty. */
2662 i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object
*obj
)
2664 if ((obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
) == 0)
2667 /* Queue the GPU write cache flushing we need. */
2668 return i915_gem_flush_ring(obj
->ring
, 0, obj
->base
.write_domain
);
2671 /** Flushes the GTT write domain for the object if it's dirty. */
2673 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
)
2675 uint32_t old_write_domain
;
2677 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_GTT
)
2680 /* No actual flushing is required for the GTT write domain. Writes
2681 * to it immediately go to main memory as far as we know, so there's
2682 * no chipset flush. It also doesn't land in render cache.
2684 * However, we do have to enforce the order so that all writes through
2685 * the GTT land before any writes to the device, such as updates to
2690 old_write_domain
= obj
->base
.write_domain
;
2691 obj
->base
.write_domain
= 0;
2693 trace_i915_gem_object_change_domain(obj
,
2694 obj
->base
.read_domains
,
2698 /** Flushes the CPU write domain for the object if it's dirty. */
2700 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
)
2702 uint32_t old_write_domain
;
2704 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
)
2707 i915_gem_clflush_object(obj
);
2708 intel_gtt_chipset_flush();
2709 old_write_domain
= obj
->base
.write_domain
;
2710 obj
->base
.write_domain
= 0;
2712 trace_i915_gem_object_change_domain(obj
,
2713 obj
->base
.read_domains
,
2718 * Moves a single object to the GTT read, and possibly write domain.
2720 * This function returns when the move is complete, including waiting on
2724 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
, bool write
)
2726 drm_i915_private_t
*dev_priv
= obj
->base
.dev
->dev_private
;
2727 uint32_t old_write_domain
, old_read_domains
;
2730 /* Not valid to be called on unbound objects. */
2731 if (obj
->gtt_space
== NULL
)
2734 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_GTT
)
2737 ret
= i915_gem_object_flush_gpu_write_domain(obj
);
2741 if (obj
->pending_gpu_write
|| write
) {
2742 ret
= i915_gem_object_wait_rendering(obj
);
2747 i915_gem_object_flush_cpu_write_domain(obj
);
2749 old_write_domain
= obj
->base
.write_domain
;
2750 old_read_domains
= obj
->base
.read_domains
;
2752 /* It should now be out of any other write domains, and we can update
2753 * the domain values for our changes.
2755 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
2756 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
2758 obj
->base
.read_domains
= I915_GEM_DOMAIN_GTT
;
2759 obj
->base
.write_domain
= I915_GEM_DOMAIN_GTT
;
2763 trace_i915_gem_object_change_domain(obj
,
2767 /* And bump the LRU for this access */
2768 if (i915_gem_object_is_inactive(obj
))
2769 list_move_tail(&obj
->mm_list
, &dev_priv
->mm
.inactive_list
);
2774 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
2775 enum i915_cache_level cache_level
)
2777 struct drm_device
*dev
= obj
->base
.dev
;
2778 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2781 if (obj
->cache_level
== cache_level
)
2784 if (obj
->pin_count
) {
2785 DRM_DEBUG("can not change the cache level of pinned objects\n");
2789 if (obj
->gtt_space
) {
2790 ret
= i915_gem_object_finish_gpu(obj
);
2794 i915_gem_object_finish_gtt(obj
);
2796 /* Before SandyBridge, you could not use tiling or fence
2797 * registers with snooped memory, so relinquish any fences
2798 * currently pointing to our region in the aperture.
2800 if (INTEL_INFO(obj
->base
.dev
)->gen
< 6) {
2801 ret
= i915_gem_object_put_fence(obj
);
2806 if (obj
->has_global_gtt_mapping
)
2807 i915_gem_gtt_bind_object(obj
, cache_level
);
2808 if (obj
->has_aliasing_ppgtt_mapping
)
2809 i915_ppgtt_bind_object(dev_priv
->mm
.aliasing_ppgtt
,
2813 if (cache_level
== I915_CACHE_NONE
) {
2814 u32 old_read_domains
, old_write_domain
;
2816 /* If we're coming from LLC cached, then we haven't
2817 * actually been tracking whether the data is in the
2818 * CPU cache or not, since we only allow one bit set
2819 * in obj->write_domain and have been skipping the clflushes.
2820 * Just set it to the CPU cache for now.
2822 WARN_ON(obj
->base
.write_domain
& ~I915_GEM_DOMAIN_CPU
);
2823 WARN_ON(obj
->base
.read_domains
& ~I915_GEM_DOMAIN_CPU
);
2825 old_read_domains
= obj
->base
.read_domains
;
2826 old_write_domain
= obj
->base
.write_domain
;
2828 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
2829 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
2831 trace_i915_gem_object_change_domain(obj
,
2836 obj
->cache_level
= cache_level
;
2841 * Prepare buffer for display plane (scanout, cursors, etc).
2842 * Can be called from an uninterruptible phase (modesetting) and allows
2843 * any flushes to be pipelined (for pageflips).
2846 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
2848 struct intel_ring_buffer
*pipelined
)
2850 u32 old_read_domains
, old_write_domain
;
2853 ret
= i915_gem_object_flush_gpu_write_domain(obj
);
2857 if (pipelined
!= obj
->ring
) {
2858 ret
= i915_gem_object_sync(obj
, pipelined
);
2863 /* The display engine is not coherent with the LLC cache on gen6. As
2864 * a result, we make sure that the pinning that is about to occur is
2865 * done with uncached PTEs. This is lowest common denominator for all
2868 * However for gen6+, we could do better by using the GFDT bit instead
2869 * of uncaching, which would allow us to flush all the LLC-cached data
2870 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
2872 ret
= i915_gem_object_set_cache_level(obj
, I915_CACHE_NONE
);
2876 /* As the user may map the buffer once pinned in the display plane
2877 * (e.g. libkms for the bootup splash), we have to ensure that we
2878 * always use map_and_fenceable for all scanout buffers.
2880 ret
= i915_gem_object_pin(obj
, alignment
, true);
2884 i915_gem_object_flush_cpu_write_domain(obj
);
2886 old_write_domain
= obj
->base
.write_domain
;
2887 old_read_domains
= obj
->base
.read_domains
;
2889 /* It should now be out of any other write domains, and we can update
2890 * the domain values for our changes.
2892 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
2893 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
2895 trace_i915_gem_object_change_domain(obj
,
2903 i915_gem_object_finish_gpu(struct drm_i915_gem_object
*obj
)
2907 if ((obj
->base
.read_domains
& I915_GEM_GPU_DOMAINS
) == 0)
2910 if (obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
) {
2911 ret
= i915_gem_flush_ring(obj
->ring
, 0, obj
->base
.write_domain
);
2916 ret
= i915_gem_object_wait_rendering(obj
);
2920 /* Ensure that we invalidate the GPU's caches and TLBs. */
2921 obj
->base
.read_domains
&= ~I915_GEM_GPU_DOMAINS
;
2926 * Moves a single object to the CPU read, and possibly write domain.
2928 * This function returns when the move is complete, including waiting on
2932 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
)
2934 uint32_t old_write_domain
, old_read_domains
;
2937 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_CPU
)
2940 ret
= i915_gem_object_flush_gpu_write_domain(obj
);
2944 if (write
|| obj
->pending_gpu_write
) {
2945 ret
= i915_gem_object_wait_rendering(obj
);
2950 i915_gem_object_flush_gtt_write_domain(obj
);
2952 old_write_domain
= obj
->base
.write_domain
;
2953 old_read_domains
= obj
->base
.read_domains
;
2955 /* Flush the CPU cache if it's still invalid. */
2956 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) == 0) {
2957 i915_gem_clflush_object(obj
);
2959 obj
->base
.read_domains
|= I915_GEM_DOMAIN_CPU
;
2962 /* It should now be out of any other write domains, and we can update
2963 * the domain values for our changes.
2965 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
2967 /* If we're writing through the CPU, then the GPU read domains will
2968 * need to be invalidated at next use.
2971 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
2972 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
2975 trace_i915_gem_object_change_domain(obj
,
2982 /* Throttle our rendering by waiting until the ring has completed our requests
2983 * emitted over 20 msec ago.
2985 * Note that if we were to use the current jiffies each time around the loop,
2986 * we wouldn't escape the function with any frames outstanding if the time to
2987 * render a frame was over 20ms.
2989 * This should get us reasonable parallelism between CPU and GPU but also
2990 * relatively low latency when blocking on a particular request to finish.
2993 i915_gem_ring_throttle(struct drm_device
*dev
, struct drm_file
*file
)
2995 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2996 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
2997 unsigned long recent_enough
= jiffies
- msecs_to_jiffies(20);
2998 struct drm_i915_gem_request
*request
;
2999 struct intel_ring_buffer
*ring
= NULL
;
3003 if (atomic_read(&dev_priv
->mm
.wedged
))
3006 spin_lock(&file_priv
->mm
.lock
);
3007 list_for_each_entry(request
, &file_priv
->mm
.request_list
, client_list
) {
3008 if (time_after_eq(request
->emitted_jiffies
, recent_enough
))
3011 ring
= request
->ring
;
3012 seqno
= request
->seqno
;
3014 spin_unlock(&file_priv
->mm
.lock
);
3020 if (!i915_seqno_passed(ring
->get_seqno(ring
), seqno
)) {
3021 /* And wait for the seqno passing without holding any locks and
3022 * causing extra latency for others. This is safe as the irq
3023 * generation is designed to be run atomically and so is
3026 if (ring
->irq_get(ring
)) {
3027 ret
= wait_event_interruptible(ring
->irq_queue
,
3028 i915_seqno_passed(ring
->get_seqno(ring
), seqno
)
3029 || atomic_read(&dev_priv
->mm
.wedged
));
3030 ring
->irq_put(ring
);
3032 if (ret
== 0 && atomic_read(&dev_priv
->mm
.wedged
))
3034 } else if (wait_for_atomic(i915_seqno_passed(ring
->get_seqno(ring
),
3036 atomic_read(&dev_priv
->mm
.wedged
), 3000)) {
3042 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, 0);
3048 i915_gem_object_pin(struct drm_i915_gem_object
*obj
,
3050 bool map_and_fenceable
)
3054 BUG_ON(obj
->pin_count
== DRM_I915_GEM_OBJECT_MAX_PIN_COUNT
);
3056 if (obj
->gtt_space
!= NULL
) {
3057 if ((alignment
&& obj
->gtt_offset
& (alignment
- 1)) ||
3058 (map_and_fenceable
&& !obj
->map_and_fenceable
)) {
3059 WARN(obj
->pin_count
,
3060 "bo is already pinned with incorrect alignment:"
3061 " offset=%x, req.alignment=%x, req.map_and_fenceable=%d,"
3062 " obj->map_and_fenceable=%d\n",
3063 obj
->gtt_offset
, alignment
,
3065 obj
->map_and_fenceable
);
3066 ret
= i915_gem_object_unbind(obj
);
3072 if (obj
->gtt_space
== NULL
) {
3073 ret
= i915_gem_object_bind_to_gtt(obj
, alignment
,
3079 if (!obj
->has_global_gtt_mapping
&& map_and_fenceable
)
3080 i915_gem_gtt_bind_object(obj
, obj
->cache_level
);
3083 obj
->pin_mappable
|= map_and_fenceable
;
3089 i915_gem_object_unpin(struct drm_i915_gem_object
*obj
)
3091 BUG_ON(obj
->pin_count
== 0);
3092 BUG_ON(obj
->gtt_space
== NULL
);
3094 if (--obj
->pin_count
== 0)
3095 obj
->pin_mappable
= false;
3099 i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
3100 struct drm_file
*file
)
3102 struct drm_i915_gem_pin
*args
= data
;
3103 struct drm_i915_gem_object
*obj
;
3106 ret
= i915_mutex_lock_interruptible(dev
);
3110 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3111 if (&obj
->base
== NULL
) {
3116 if (obj
->madv
!= I915_MADV_WILLNEED
) {
3117 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3122 if (obj
->pin_filp
!= NULL
&& obj
->pin_filp
!= file
) {
3123 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3129 obj
->user_pin_count
++;
3130 obj
->pin_filp
= file
;
3131 if (obj
->user_pin_count
== 1) {
3132 ret
= i915_gem_object_pin(obj
, args
->alignment
, true);
3137 /* XXX - flush the CPU caches for pinned objects
3138 * as the X server doesn't manage domains yet
3140 i915_gem_object_flush_cpu_write_domain(obj
);
3141 args
->offset
= obj
->gtt_offset
;
3143 drm_gem_object_unreference(&obj
->base
);
3145 mutex_unlock(&dev
->struct_mutex
);
3150 i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
3151 struct drm_file
*file
)
3153 struct drm_i915_gem_pin
*args
= data
;
3154 struct drm_i915_gem_object
*obj
;
3157 ret
= i915_mutex_lock_interruptible(dev
);
3161 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3162 if (&obj
->base
== NULL
) {
3167 if (obj
->pin_filp
!= file
) {
3168 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3173 obj
->user_pin_count
--;
3174 if (obj
->user_pin_count
== 0) {
3175 obj
->pin_filp
= NULL
;
3176 i915_gem_object_unpin(obj
);
3180 drm_gem_object_unreference(&obj
->base
);
3182 mutex_unlock(&dev
->struct_mutex
);
3187 i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
3188 struct drm_file
*file
)
3190 struct drm_i915_gem_busy
*args
= data
;
3191 struct drm_i915_gem_object
*obj
;
3194 ret
= i915_mutex_lock_interruptible(dev
);
3198 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3199 if (&obj
->base
== NULL
) {
3204 /* Count all active objects as busy, even if they are currently not used
3205 * by the gpu. Users of this interface expect objects to eventually
3206 * become non-busy without any further actions, therefore emit any
3207 * necessary flushes here.
3209 args
->busy
= obj
->active
;
3211 /* Unconditionally flush objects, even when the gpu still uses this
3212 * object. Userspace calling this function indicates that it wants to
3213 * use this buffer rather sooner than later, so issuing the required
3214 * flush earlier is beneficial.
3216 if (obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
) {
3217 ret
= i915_gem_flush_ring(obj
->ring
,
3218 0, obj
->base
.write_domain
);
3219 } else if (obj
->ring
->outstanding_lazy_request
==
3220 obj
->last_rendering_seqno
) {
3221 struct drm_i915_gem_request
*request
;
3223 /* This ring is not being cleared by active usage,
3224 * so emit a request to do so.
3226 request
= kzalloc(sizeof(*request
), GFP_KERNEL
);
3228 ret
= i915_add_request(obj
->ring
, NULL
, request
);
3235 /* Update the active list for the hardware's current position.
3236 * Otherwise this only updates on a delayed timer or when irqs
3237 * are actually unmasked, and our working set ends up being
3238 * larger than required.
3240 i915_gem_retire_requests_ring(obj
->ring
);
3242 args
->busy
= obj
->active
;
3245 drm_gem_object_unreference(&obj
->base
);
3247 mutex_unlock(&dev
->struct_mutex
);
3252 i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
3253 struct drm_file
*file_priv
)
3255 return i915_gem_ring_throttle(dev
, file_priv
);
3259 i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
3260 struct drm_file
*file_priv
)
3262 struct drm_i915_gem_madvise
*args
= data
;
3263 struct drm_i915_gem_object
*obj
;
3266 switch (args
->madv
) {
3267 case I915_MADV_DONTNEED
:
3268 case I915_MADV_WILLNEED
:
3274 ret
= i915_mutex_lock_interruptible(dev
);
3278 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file_priv
, args
->handle
));
3279 if (&obj
->base
== NULL
) {
3284 if (obj
->pin_count
) {
3289 if (obj
->madv
!= __I915_MADV_PURGED
)
3290 obj
->madv
= args
->madv
;
3292 /* if the object is no longer bound, discard its backing storage */
3293 if (i915_gem_object_is_purgeable(obj
) &&
3294 obj
->gtt_space
== NULL
)
3295 i915_gem_object_truncate(obj
);
3297 args
->retained
= obj
->madv
!= __I915_MADV_PURGED
;
3300 drm_gem_object_unreference(&obj
->base
);
3302 mutex_unlock(&dev
->struct_mutex
);
3306 struct drm_i915_gem_object
*i915_gem_alloc_object(struct drm_device
*dev
,
3309 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3310 struct drm_i915_gem_object
*obj
;
3311 struct address_space
*mapping
;
3313 obj
= kzalloc(sizeof(*obj
), GFP_KERNEL
);
3317 if (drm_gem_object_init(dev
, &obj
->base
, size
) != 0) {
3322 mapping
= obj
->base
.filp
->f_path
.dentry
->d_inode
->i_mapping
;
3323 mapping_set_gfp_mask(mapping
, GFP_HIGHUSER
| __GFP_RECLAIMABLE
);
3325 i915_gem_info_add_obj(dev_priv
, size
);
3327 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
3328 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
3331 /* On some devices, we can have the GPU use the LLC (the CPU
3332 * cache) for about a 10% performance improvement
3333 * compared to uncached. Graphics requests other than
3334 * display scanout are coherent with the CPU in
3335 * accessing this cache. This means in this mode we
3336 * don't need to clflush on the CPU side, and on the
3337 * GPU side we only need to flush internal caches to
3338 * get data visible to the CPU.
3340 * However, we maintain the display planes as UC, and so
3341 * need to rebind when first used as such.
3343 obj
->cache_level
= I915_CACHE_LLC
;
3345 obj
->cache_level
= I915_CACHE_NONE
;
3347 obj
->base
.driver_private
= NULL
;
3348 obj
->fence_reg
= I915_FENCE_REG_NONE
;
3349 INIT_LIST_HEAD(&obj
->mm_list
);
3350 INIT_LIST_HEAD(&obj
->gtt_list
);
3351 INIT_LIST_HEAD(&obj
->ring_list
);
3352 INIT_LIST_HEAD(&obj
->exec_list
);
3353 INIT_LIST_HEAD(&obj
->gpu_write_list
);
3354 obj
->madv
= I915_MADV_WILLNEED
;
3355 /* Avoid an unnecessary call to unbind on the first bind. */
3356 obj
->map_and_fenceable
= true;
3361 int i915_gem_init_object(struct drm_gem_object
*obj
)
3368 void i915_gem_free_object(struct drm_gem_object
*gem_obj
)
3370 struct drm_i915_gem_object
*obj
= to_intel_bo(gem_obj
);
3371 struct drm_device
*dev
= obj
->base
.dev
;
3372 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3374 trace_i915_gem_object_destroy(obj
);
3377 i915_gem_detach_phys_object(dev
, obj
);
3380 if (WARN_ON(i915_gem_object_unbind(obj
) == -ERESTARTSYS
)) {
3381 bool was_interruptible
;
3383 was_interruptible
= dev_priv
->mm
.interruptible
;
3384 dev_priv
->mm
.interruptible
= false;
3386 WARN_ON(i915_gem_object_unbind(obj
));
3388 dev_priv
->mm
.interruptible
= was_interruptible
;
3391 if (obj
->base
.map_list
.map
)
3392 drm_gem_free_mmap_offset(&obj
->base
);
3394 drm_gem_object_release(&obj
->base
);
3395 i915_gem_info_remove_obj(dev_priv
, obj
->base
.size
);
3402 i915_gem_idle(struct drm_device
*dev
)
3404 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3407 mutex_lock(&dev
->struct_mutex
);
3409 if (dev_priv
->mm
.suspended
) {
3410 mutex_unlock(&dev
->struct_mutex
);
3414 ret
= i915_gpu_idle(dev
, true);
3416 mutex_unlock(&dev
->struct_mutex
);
3420 /* Under UMS, be paranoid and evict. */
3421 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
3422 i915_gem_evict_everything(dev
, false);
3424 i915_gem_reset_fences(dev
);
3426 /* Hack! Don't let anybody do execbuf while we don't control the chip.
3427 * We need to replace this with a semaphore, or something.
3428 * And not confound mm.suspended!
3430 dev_priv
->mm
.suspended
= 1;
3431 del_timer_sync(&dev_priv
->hangcheck_timer
);
3433 i915_kernel_lost_context(dev
);
3434 i915_gem_cleanup_ringbuffer(dev
);
3436 mutex_unlock(&dev
->struct_mutex
);
3438 /* Cancel the retire work handler, which should be idle now. */
3439 cancel_delayed_work_sync(&dev_priv
->mm
.retire_work
);
3444 void i915_gem_init_swizzling(struct drm_device
*dev
)
3446 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3448 if (INTEL_INFO(dev
)->gen
< 5 ||
3449 dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_NONE
)
3452 I915_WRITE(DISP_ARB_CTL
, I915_READ(DISP_ARB_CTL
) |
3453 DISP_TILE_SURFACE_SWIZZLING
);
3458 I915_WRITE(TILECTL
, I915_READ(TILECTL
) | TILECTL_SWZCTL
);
3460 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB
));
3462 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB
));
3465 void i915_gem_init_ppgtt(struct drm_device
*dev
)
3467 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3469 struct intel_ring_buffer
*ring
;
3470 struct i915_hw_ppgtt
*ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
3471 uint32_t __iomem
*pd_addr
;
3475 if (!dev_priv
->mm
.aliasing_ppgtt
)
3479 pd_addr
= dev_priv
->mm
.gtt
->gtt
+ ppgtt
->pd_offset
/sizeof(uint32_t);
3480 for (i
= 0; i
< ppgtt
->num_pd_entries
; i
++) {
3483 if (dev_priv
->mm
.gtt
->needs_dmar
)
3484 pt_addr
= ppgtt
->pt_dma_addr
[i
];
3486 pt_addr
= page_to_phys(ppgtt
->pt_pages
[i
]);
3488 pd_entry
= GEN6_PDE_ADDR_ENCODE(pt_addr
);
3489 pd_entry
|= GEN6_PDE_VALID
;
3491 writel(pd_entry
, pd_addr
+ i
);
3495 pd_offset
= ppgtt
->pd_offset
;
3496 pd_offset
/= 64; /* in cachelines, */
3499 if (INTEL_INFO(dev
)->gen
== 6) {
3500 uint32_t ecochk
, gab_ctl
, ecobits
;
3502 ecobits
= I915_READ(GAC_ECO_BITS
);
3503 I915_WRITE(GAC_ECO_BITS
, ecobits
| ECOBITS_PPGTT_CACHE64B
);
3505 gab_ctl
= I915_READ(GAB_CTL
);
3506 I915_WRITE(GAB_CTL
, gab_ctl
| GAB_CTL_CONT_AFTER_PAGEFAULT
);
3508 ecochk
= I915_READ(GAM_ECOCHK
);
3509 I915_WRITE(GAM_ECOCHK
, ecochk
| ECOCHK_SNB_BIT
|
3510 ECOCHK_PPGTT_CACHE64B
);
3511 I915_WRITE(GFX_MODE
, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE
));
3512 } else if (INTEL_INFO(dev
)->gen
>= 7) {
3513 I915_WRITE(GAM_ECOCHK
, ECOCHK_PPGTT_CACHE64B
);
3514 /* GFX_MODE is per-ring on gen7+ */
3517 for (i
= 0; i
< I915_NUM_RINGS
; i
++) {
3518 ring
= &dev_priv
->ring
[i
];
3520 if (INTEL_INFO(dev
)->gen
>= 7)
3521 I915_WRITE(RING_MODE_GEN7(ring
),
3522 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE
));
3524 I915_WRITE(RING_PP_DIR_DCLV(ring
), PP_DIR_DCLV_2G
);
3525 I915_WRITE(RING_PP_DIR_BASE(ring
), pd_offset
);
3530 i915_gem_init_hw(struct drm_device
*dev
)
3532 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3535 i915_gem_init_swizzling(dev
);
3537 ret
= intel_init_render_ring_buffer(dev
);
3542 ret
= intel_init_bsd_ring_buffer(dev
);
3544 goto cleanup_render_ring
;
3548 ret
= intel_init_blt_ring_buffer(dev
);
3550 goto cleanup_bsd_ring
;
3553 dev_priv
->next_seqno
= 1;
3555 i915_gem_init_ppgtt(dev
);
3560 intel_cleanup_ring_buffer(&dev_priv
->ring
[VCS
]);
3561 cleanup_render_ring
:
3562 intel_cleanup_ring_buffer(&dev_priv
->ring
[RCS
]);
3567 intel_enable_ppgtt(struct drm_device
*dev
)
3569 if (i915_enable_ppgtt
>= 0)
3570 return i915_enable_ppgtt
;
3572 #ifdef CONFIG_INTEL_IOMMU
3573 /* Disable ppgtt on SNB if VT-d is on. */
3574 if (INTEL_INFO(dev
)->gen
== 6 && intel_iommu_gfx_mapped
)
3581 int i915_gem_init(struct drm_device
*dev
)
3583 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3584 unsigned long gtt_size
, mappable_size
;
3587 gtt_size
= dev_priv
->mm
.gtt
->gtt_total_entries
<< PAGE_SHIFT
;
3588 mappable_size
= dev_priv
->mm
.gtt
->gtt_mappable_entries
<< PAGE_SHIFT
;
3590 mutex_lock(&dev
->struct_mutex
);
3591 if (intel_enable_ppgtt(dev
) && HAS_ALIASING_PPGTT(dev
)) {
3592 /* PPGTT pdes are stolen from global gtt ptes, so shrink the
3593 * aperture accordingly when using aliasing ppgtt. */
3594 gtt_size
-= I915_PPGTT_PD_ENTRIES
*PAGE_SIZE
;
3596 i915_gem_init_global_gtt(dev
, 0, mappable_size
, gtt_size
);
3598 ret
= i915_gem_init_aliasing_ppgtt(dev
);
3600 mutex_unlock(&dev
->struct_mutex
);
3604 /* Let GEM Manage all of the aperture.
3606 * However, leave one page at the end still bound to the scratch
3607 * page. There are a number of places where the hardware
3608 * apparently prefetches past the end of the object, and we've
3609 * seen multiple hangs with the GPU head pointer stuck in a
3610 * batchbuffer bound at the last page of the aperture. One page
3611 * should be enough to keep any prefetching inside of the
3614 i915_gem_init_global_gtt(dev
, 0, mappable_size
,
3618 ret
= i915_gem_init_hw(dev
);
3619 mutex_unlock(&dev
->struct_mutex
);
3621 i915_gem_cleanup_aliasing_ppgtt(dev
);
3625 /* Allow hardware batchbuffers unless told otherwise. */
3626 dev_priv
->allow_batchbuffer
= 1;
3631 i915_gem_cleanup_ringbuffer(struct drm_device
*dev
)
3633 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3636 for (i
= 0; i
< I915_NUM_RINGS
; i
++)
3637 intel_cleanup_ring_buffer(&dev_priv
->ring
[i
]);
3641 i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
3642 struct drm_file
*file_priv
)
3644 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3647 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
3650 if (atomic_read(&dev_priv
->mm
.wedged
)) {
3651 DRM_ERROR("Reenabling wedged hardware, good luck\n");
3652 atomic_set(&dev_priv
->mm
.wedged
, 0);
3655 mutex_lock(&dev
->struct_mutex
);
3656 dev_priv
->mm
.suspended
= 0;
3658 ret
= i915_gem_init_hw(dev
);
3660 mutex_unlock(&dev
->struct_mutex
);
3664 BUG_ON(!list_empty(&dev_priv
->mm
.active_list
));
3665 BUG_ON(!list_empty(&dev_priv
->mm
.flushing_list
));
3666 BUG_ON(!list_empty(&dev_priv
->mm
.inactive_list
));
3667 for (i
= 0; i
< I915_NUM_RINGS
; i
++) {
3668 BUG_ON(!list_empty(&dev_priv
->ring
[i
].active_list
));
3669 BUG_ON(!list_empty(&dev_priv
->ring
[i
].request_list
));
3671 mutex_unlock(&dev
->struct_mutex
);
3673 ret
= drm_irq_install(dev
);
3675 goto cleanup_ringbuffer
;
3680 mutex_lock(&dev
->struct_mutex
);
3681 i915_gem_cleanup_ringbuffer(dev
);
3682 dev_priv
->mm
.suspended
= 1;
3683 mutex_unlock(&dev
->struct_mutex
);
3689 i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
3690 struct drm_file
*file_priv
)
3692 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
3695 drm_irq_uninstall(dev
);
3696 return i915_gem_idle(dev
);
3700 i915_gem_lastclose(struct drm_device
*dev
)
3704 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
3707 ret
= i915_gem_idle(dev
);
3709 DRM_ERROR("failed to idle hardware: %d\n", ret
);
3713 init_ring_lists(struct intel_ring_buffer
*ring
)
3715 INIT_LIST_HEAD(&ring
->active_list
);
3716 INIT_LIST_HEAD(&ring
->request_list
);
3717 INIT_LIST_HEAD(&ring
->gpu_write_list
);
3721 i915_gem_load(struct drm_device
*dev
)
3724 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3726 INIT_LIST_HEAD(&dev_priv
->mm
.active_list
);
3727 INIT_LIST_HEAD(&dev_priv
->mm
.flushing_list
);
3728 INIT_LIST_HEAD(&dev_priv
->mm
.inactive_list
);
3729 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
3730 INIT_LIST_HEAD(&dev_priv
->mm
.gtt_list
);
3731 for (i
= 0; i
< I915_NUM_RINGS
; i
++)
3732 init_ring_lists(&dev_priv
->ring
[i
]);
3733 for (i
= 0; i
< I915_MAX_NUM_FENCES
; i
++)
3734 INIT_LIST_HEAD(&dev_priv
->fence_regs
[i
].lru_list
);
3735 INIT_DELAYED_WORK(&dev_priv
->mm
.retire_work
,
3736 i915_gem_retire_work_handler
);
3737 init_completion(&dev_priv
->error_completion
);
3739 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
3741 u32 tmp
= I915_READ(MI_ARB_STATE
);
3742 if (!(tmp
& MI_ARB_C3_LP_WRITE_ENABLE
)) {
3743 /* arb state is a masked write, so set bit + bit in mask */
3744 tmp
= MI_ARB_C3_LP_WRITE_ENABLE
| (MI_ARB_C3_LP_WRITE_ENABLE
<< MI_ARB_MASK_SHIFT
);
3745 I915_WRITE(MI_ARB_STATE
, tmp
);
3749 dev_priv
->relative_constants_mode
= I915_EXEC_CONSTANTS_REL_GENERAL
;
3751 /* Old X drivers will take 0-2 for front, back, depth buffers */
3752 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
3753 dev_priv
->fence_reg_start
= 3;
3755 if (INTEL_INFO(dev
)->gen
>= 4 || IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
3756 dev_priv
->num_fence_regs
= 16;
3758 dev_priv
->num_fence_regs
= 8;
3760 /* Initialize fence registers to zero */
3761 i915_gem_reset_fences(dev
);
3763 i915_gem_detect_bit_6_swizzle(dev
);
3764 init_waitqueue_head(&dev_priv
->pending_flip_queue
);
3766 dev_priv
->mm
.interruptible
= true;
3768 dev_priv
->mm
.inactive_shrinker
.shrink
= i915_gem_inactive_shrink
;
3769 dev_priv
->mm
.inactive_shrinker
.seeks
= DEFAULT_SEEKS
;
3770 register_shrinker(&dev_priv
->mm
.inactive_shrinker
);
3774 * Create a physically contiguous memory object for this object
3775 * e.g. for cursor + overlay regs
3777 static int i915_gem_init_phys_object(struct drm_device
*dev
,
3778 int id
, int size
, int align
)
3780 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3781 struct drm_i915_gem_phys_object
*phys_obj
;
3784 if (dev_priv
->mm
.phys_objs
[id
- 1] || !size
)
3787 phys_obj
= kzalloc(sizeof(struct drm_i915_gem_phys_object
), GFP_KERNEL
);
3793 phys_obj
->handle
= drm_pci_alloc(dev
, size
, align
);
3794 if (!phys_obj
->handle
) {
3799 set_memory_wc((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
3802 dev_priv
->mm
.phys_objs
[id
- 1] = phys_obj
;
3810 static void i915_gem_free_phys_object(struct drm_device
*dev
, int id
)
3812 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3813 struct drm_i915_gem_phys_object
*phys_obj
;
3815 if (!dev_priv
->mm
.phys_objs
[id
- 1])
3818 phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
3819 if (phys_obj
->cur_obj
) {
3820 i915_gem_detach_phys_object(dev
, phys_obj
->cur_obj
);
3824 set_memory_wb((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
3826 drm_pci_free(dev
, phys_obj
->handle
);
3828 dev_priv
->mm
.phys_objs
[id
- 1] = NULL
;
3831 void i915_gem_free_all_phys_object(struct drm_device
*dev
)
3835 for (i
= I915_GEM_PHYS_CURSOR_0
; i
<= I915_MAX_PHYS_OBJECT
; i
++)
3836 i915_gem_free_phys_object(dev
, i
);
3839 void i915_gem_detach_phys_object(struct drm_device
*dev
,
3840 struct drm_i915_gem_object
*obj
)
3842 struct address_space
*mapping
= obj
->base
.filp
->f_path
.dentry
->d_inode
->i_mapping
;
3849 vaddr
= obj
->phys_obj
->handle
->vaddr
;
3851 page_count
= obj
->base
.size
/ PAGE_SIZE
;
3852 for (i
= 0; i
< page_count
; i
++) {
3853 struct page
*page
= shmem_read_mapping_page(mapping
, i
);
3854 if (!IS_ERR(page
)) {
3855 char *dst
= kmap_atomic(page
);
3856 memcpy(dst
, vaddr
+ i
*PAGE_SIZE
, PAGE_SIZE
);
3859 drm_clflush_pages(&page
, 1);
3861 set_page_dirty(page
);
3862 mark_page_accessed(page
);
3863 page_cache_release(page
);
3866 intel_gtt_chipset_flush();
3868 obj
->phys_obj
->cur_obj
= NULL
;
3869 obj
->phys_obj
= NULL
;
3873 i915_gem_attach_phys_object(struct drm_device
*dev
,
3874 struct drm_i915_gem_object
*obj
,
3878 struct address_space
*mapping
= obj
->base
.filp
->f_path
.dentry
->d_inode
->i_mapping
;
3879 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3884 if (id
> I915_MAX_PHYS_OBJECT
)
3887 if (obj
->phys_obj
) {
3888 if (obj
->phys_obj
->id
== id
)
3890 i915_gem_detach_phys_object(dev
, obj
);
3893 /* create a new object */
3894 if (!dev_priv
->mm
.phys_objs
[id
- 1]) {
3895 ret
= i915_gem_init_phys_object(dev
, id
,
3896 obj
->base
.size
, align
);
3898 DRM_ERROR("failed to init phys object %d size: %zu\n",
3899 id
, obj
->base
.size
);
3904 /* bind to the object */
3905 obj
->phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
3906 obj
->phys_obj
->cur_obj
= obj
;
3908 page_count
= obj
->base
.size
/ PAGE_SIZE
;
3910 for (i
= 0; i
< page_count
; i
++) {
3914 page
= shmem_read_mapping_page(mapping
, i
);
3916 return PTR_ERR(page
);
3918 src
= kmap_atomic(page
);
3919 dst
= obj
->phys_obj
->handle
->vaddr
+ (i
* PAGE_SIZE
);
3920 memcpy(dst
, src
, PAGE_SIZE
);
3923 mark_page_accessed(page
);
3924 page_cache_release(page
);
3931 i915_gem_phys_pwrite(struct drm_device
*dev
,
3932 struct drm_i915_gem_object
*obj
,
3933 struct drm_i915_gem_pwrite
*args
,
3934 struct drm_file
*file_priv
)
3936 void *vaddr
= obj
->phys_obj
->handle
->vaddr
+ args
->offset
;
3937 char __user
*user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
3939 if (__copy_from_user_inatomic_nocache(vaddr
, user_data
, args
->size
)) {
3940 unsigned long unwritten
;
3942 /* The physical object once assigned is fixed for the lifetime
3943 * of the obj, so we can safely drop the lock and continue
3946 mutex_unlock(&dev
->struct_mutex
);
3947 unwritten
= copy_from_user(vaddr
, user_data
, args
->size
);
3948 mutex_lock(&dev
->struct_mutex
);
3953 intel_gtt_chipset_flush();
3957 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
)
3959 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
3961 /* Clean up our request list when the client is going away, so that
3962 * later retire_requests won't dereference our soon-to-be-gone
3965 spin_lock(&file_priv
->mm
.lock
);
3966 while (!list_empty(&file_priv
->mm
.request_list
)) {
3967 struct drm_i915_gem_request
*request
;
3969 request
= list_first_entry(&file_priv
->mm
.request_list
,
3970 struct drm_i915_gem_request
,
3972 list_del(&request
->client_list
);
3973 request
->file_priv
= NULL
;
3975 spin_unlock(&file_priv
->mm
.lock
);
3979 i915_gpu_is_active(struct drm_device
*dev
)
3981 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3984 lists_empty
= list_empty(&dev_priv
->mm
.flushing_list
) &&
3985 list_empty(&dev_priv
->mm
.active_list
);
3987 return !lists_empty
;
3991 i915_gem_inactive_shrink(struct shrinker
*shrinker
, struct shrink_control
*sc
)
3993 struct drm_i915_private
*dev_priv
=
3994 container_of(shrinker
,
3995 struct drm_i915_private
,
3996 mm
.inactive_shrinker
);
3997 struct drm_device
*dev
= dev_priv
->dev
;
3998 struct drm_i915_gem_object
*obj
, *next
;
3999 int nr_to_scan
= sc
->nr_to_scan
;
4002 if (!mutex_trylock(&dev
->struct_mutex
))
4005 /* "fast-path" to count number of available objects */
4006 if (nr_to_scan
== 0) {
4008 list_for_each_entry(obj
,
4009 &dev_priv
->mm
.inactive_list
,
4012 mutex_unlock(&dev
->struct_mutex
);
4013 return cnt
/ 100 * sysctl_vfs_cache_pressure
;
4017 /* first scan for clean buffers */
4018 i915_gem_retire_requests(dev
);
4020 list_for_each_entry_safe(obj
, next
,
4021 &dev_priv
->mm
.inactive_list
,
4023 if (i915_gem_object_is_purgeable(obj
)) {
4024 if (i915_gem_object_unbind(obj
) == 0 &&
4030 /* second pass, evict/count anything still on the inactive list */
4032 list_for_each_entry_safe(obj
, next
,
4033 &dev_priv
->mm
.inactive_list
,
4036 i915_gem_object_unbind(obj
) == 0)
4042 if (nr_to_scan
&& i915_gpu_is_active(dev
)) {
4044 * We are desperate for pages, so as a last resort, wait
4045 * for the GPU to finish and discard whatever we can.
4046 * This has a dramatic impact to reduce the number of
4047 * OOM-killer events whilst running the GPU aggressively.
4049 if (i915_gpu_idle(dev
, true) == 0)
4052 mutex_unlock(&dev
->struct_mutex
);
4053 return cnt
/ 100 * sysctl_vfs_cache_pressure
;