2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/slab.h>
35 #include <linux/swap.h>
36 #include <linux/pci.h>
37 #include <linux/intel-gtt.h>
39 static uint32_t i915_gem_get_gtt_alignment(struct drm_gem_object
*obj
);
40 static int i915_gem_object_flush_gpu_write_domain(struct drm_gem_object
*obj
);
41 static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object
*obj
);
42 static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object
*obj
);
43 static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object
*obj
,
45 static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object
*obj
,
48 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object
*obj
);
49 static int i915_gem_object_wait_rendering(struct drm_gem_object
*obj
,
51 static int i915_gem_object_bind_to_gtt(struct drm_gem_object
*obj
,
53 static void i915_gem_clear_fence_reg(struct drm_gem_object
*obj
);
54 static int i915_gem_phys_pwrite(struct drm_device
*dev
, struct drm_gem_object
*obj
,
55 struct drm_i915_gem_pwrite
*args
,
56 struct drm_file
*file_priv
);
57 static void i915_gem_free_object_tail(struct drm_gem_object
*obj
);
59 static LIST_HEAD(shrink_list
);
60 static DEFINE_SPINLOCK(shrink_list_lock
);
63 i915_gem_object_is_inactive(struct drm_i915_gem_object
*obj_priv
)
65 return obj_priv
->gtt_space
&&
67 obj_priv
->pin_count
== 0;
70 int i915_gem_do_init(struct drm_device
*dev
, unsigned long start
,
73 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
76 (start
& (PAGE_SIZE
- 1)) != 0 ||
77 (end
& (PAGE_SIZE
- 1)) != 0) {
81 drm_mm_init(&dev_priv
->mm
.gtt_space
, start
,
84 dev
->gtt_total
= (uint32_t) (end
- start
);
90 i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
91 struct drm_file
*file_priv
)
93 struct drm_i915_gem_init
*args
= data
;
96 mutex_lock(&dev
->struct_mutex
);
97 ret
= i915_gem_do_init(dev
, args
->gtt_start
, args
->gtt_end
);
98 mutex_unlock(&dev
->struct_mutex
);
104 i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
105 struct drm_file
*file_priv
)
107 struct drm_i915_gem_get_aperture
*args
= data
;
109 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
112 args
->aper_size
= dev
->gtt_total
;
113 args
->aper_available_size
= (args
->aper_size
-
114 atomic_read(&dev
->pin_memory
));
121 * Creates a new mm object and returns a handle to it.
124 i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
125 struct drm_file
*file_priv
)
127 struct drm_i915_gem_create
*args
= data
;
128 struct drm_gem_object
*obj
;
132 args
->size
= roundup(args
->size
, PAGE_SIZE
);
134 /* Allocate the new object */
135 obj
= i915_gem_alloc_object(dev
, args
->size
);
139 ret
= drm_gem_handle_create(file_priv
, obj
, &handle
);
141 drm_gem_object_unreference_unlocked(obj
);
145 /* Sink the floating reference from kref_init(handlecount) */
146 drm_gem_object_handle_unreference_unlocked(obj
);
148 args
->handle
= handle
;
153 fast_shmem_read(struct page
**pages
,
154 loff_t page_base
, int page_offset
,
161 vaddr
= kmap_atomic(pages
[page_base
>> PAGE_SHIFT
], KM_USER0
);
164 unwritten
= __copy_to_user_inatomic(data
, vaddr
+ page_offset
, length
);
165 kunmap_atomic(vaddr
, KM_USER0
);
173 static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object
*obj
)
175 drm_i915_private_t
*dev_priv
= obj
->dev
->dev_private
;
176 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
178 return dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_9_10_17
&&
179 obj_priv
->tiling_mode
!= I915_TILING_NONE
;
183 slow_shmem_copy(struct page
*dst_page
,
185 struct page
*src_page
,
189 char *dst_vaddr
, *src_vaddr
;
191 dst_vaddr
= kmap(dst_page
);
192 src_vaddr
= kmap(src_page
);
194 memcpy(dst_vaddr
+ dst_offset
, src_vaddr
+ src_offset
, length
);
201 slow_shmem_bit17_copy(struct page
*gpu_page
,
203 struct page
*cpu_page
,
208 char *gpu_vaddr
, *cpu_vaddr
;
210 /* Use the unswizzled path if this page isn't affected. */
211 if ((page_to_phys(gpu_page
) & (1 << 17)) == 0) {
213 return slow_shmem_copy(cpu_page
, cpu_offset
,
214 gpu_page
, gpu_offset
, length
);
216 return slow_shmem_copy(gpu_page
, gpu_offset
,
217 cpu_page
, cpu_offset
, length
);
220 gpu_vaddr
= kmap(gpu_page
);
221 cpu_vaddr
= kmap(cpu_page
);
223 /* Copy the data, XORing A6 with A17 (1). The user already knows he's
224 * XORing with the other bits (A9 for Y, A9 and A10 for X)
227 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
228 int this_length
= min(cacheline_end
- gpu_offset
, length
);
229 int swizzled_gpu_offset
= gpu_offset
^ 64;
232 memcpy(cpu_vaddr
+ cpu_offset
,
233 gpu_vaddr
+ swizzled_gpu_offset
,
236 memcpy(gpu_vaddr
+ swizzled_gpu_offset
,
237 cpu_vaddr
+ cpu_offset
,
240 cpu_offset
+= this_length
;
241 gpu_offset
+= this_length
;
242 length
-= this_length
;
250 * This is the fast shmem pread path, which attempts to copy_from_user directly
251 * from the backing pages of the object to the user's address space. On a
252 * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
255 i915_gem_shmem_pread_fast(struct drm_device
*dev
, struct drm_gem_object
*obj
,
256 struct drm_i915_gem_pread
*args
,
257 struct drm_file
*file_priv
)
259 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
261 loff_t offset
, page_base
;
262 char __user
*user_data
;
263 int page_offset
, page_length
;
266 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
269 mutex_lock(&dev
->struct_mutex
);
271 ret
= i915_gem_object_get_pages(obj
, 0);
275 ret
= i915_gem_object_set_cpu_read_domain_range(obj
, args
->offset
,
280 obj_priv
= to_intel_bo(obj
);
281 offset
= args
->offset
;
284 /* Operation in this page
286 * page_base = page offset within aperture
287 * page_offset = offset within page
288 * page_length = bytes to copy for this page
290 page_base
= (offset
& ~(PAGE_SIZE
-1));
291 page_offset
= offset
& (PAGE_SIZE
-1);
292 page_length
= remain
;
293 if ((page_offset
+ remain
) > PAGE_SIZE
)
294 page_length
= PAGE_SIZE
- page_offset
;
296 ret
= fast_shmem_read(obj_priv
->pages
,
297 page_base
, page_offset
,
298 user_data
, page_length
);
302 remain
-= page_length
;
303 user_data
+= page_length
;
304 offset
+= page_length
;
308 i915_gem_object_put_pages(obj
);
310 mutex_unlock(&dev
->struct_mutex
);
316 i915_gem_object_get_pages_or_evict(struct drm_gem_object
*obj
)
320 ret
= i915_gem_object_get_pages(obj
, __GFP_NORETRY
| __GFP_NOWARN
);
322 /* If we've insufficient memory to map in the pages, attempt
323 * to make some space by throwing out some old buffers.
325 if (ret
== -ENOMEM
) {
326 struct drm_device
*dev
= obj
->dev
;
328 ret
= i915_gem_evict_something(dev
, obj
->size
,
329 i915_gem_get_gtt_alignment(obj
));
333 ret
= i915_gem_object_get_pages(obj
, 0);
340 * This is the fallback shmem pread path, which allocates temporary storage
341 * in kernel space to copy_to_user into outside of the struct_mutex, so we
342 * can copy out of the object's backing pages while holding the struct mutex
343 * and not take page faults.
346 i915_gem_shmem_pread_slow(struct drm_device
*dev
, struct drm_gem_object
*obj
,
347 struct drm_i915_gem_pread
*args
,
348 struct drm_file
*file_priv
)
350 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
351 struct mm_struct
*mm
= current
->mm
;
352 struct page
**user_pages
;
354 loff_t offset
, pinned_pages
, i
;
355 loff_t first_data_page
, last_data_page
, num_pages
;
356 int shmem_page_index
, shmem_page_offset
;
357 int data_page_index
, data_page_offset
;
360 uint64_t data_ptr
= args
->data_ptr
;
361 int do_bit17_swizzling
;
365 /* Pin the user pages containing the data. We can't fault while
366 * holding the struct mutex, yet we want to hold it while
367 * dereferencing the user data.
369 first_data_page
= data_ptr
/ PAGE_SIZE
;
370 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
371 num_pages
= last_data_page
- first_data_page
+ 1;
373 user_pages
= drm_calloc_large(num_pages
, sizeof(struct page
*));
374 if (user_pages
== NULL
)
377 down_read(&mm
->mmap_sem
);
378 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
379 num_pages
, 1, 0, user_pages
, NULL
);
380 up_read(&mm
->mmap_sem
);
381 if (pinned_pages
< num_pages
) {
383 goto fail_put_user_pages
;
386 do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
388 mutex_lock(&dev
->struct_mutex
);
390 ret
= i915_gem_object_get_pages_or_evict(obj
);
394 ret
= i915_gem_object_set_cpu_read_domain_range(obj
, args
->offset
,
399 obj_priv
= to_intel_bo(obj
);
400 offset
= args
->offset
;
403 /* Operation in this page
405 * shmem_page_index = page number within shmem file
406 * shmem_page_offset = offset within page in shmem file
407 * data_page_index = page number in get_user_pages return
408 * data_page_offset = offset with data_page_index page.
409 * page_length = bytes to copy for this page
411 shmem_page_index
= offset
/ PAGE_SIZE
;
412 shmem_page_offset
= offset
& ~PAGE_MASK
;
413 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
414 data_page_offset
= data_ptr
& ~PAGE_MASK
;
416 page_length
= remain
;
417 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
418 page_length
= PAGE_SIZE
- shmem_page_offset
;
419 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
420 page_length
= PAGE_SIZE
- data_page_offset
;
422 if (do_bit17_swizzling
) {
423 slow_shmem_bit17_copy(obj_priv
->pages
[shmem_page_index
],
425 user_pages
[data_page_index
],
430 slow_shmem_copy(user_pages
[data_page_index
],
432 obj_priv
->pages
[shmem_page_index
],
437 remain
-= page_length
;
438 data_ptr
+= page_length
;
439 offset
+= page_length
;
443 i915_gem_object_put_pages(obj
);
445 mutex_unlock(&dev
->struct_mutex
);
447 for (i
= 0; i
< pinned_pages
; i
++) {
448 SetPageDirty(user_pages
[i
]);
449 page_cache_release(user_pages
[i
]);
451 drm_free_large(user_pages
);
457 * Reads data from the object referenced by handle.
459 * On error, the contents of *data are undefined.
462 i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
463 struct drm_file
*file_priv
)
465 struct drm_i915_gem_pread
*args
= data
;
466 struct drm_gem_object
*obj
;
467 struct drm_i915_gem_object
*obj_priv
;
470 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
473 obj_priv
= to_intel_bo(obj
);
475 /* Bounds check source.
477 * XXX: This could use review for overflow issues...
479 if (args
->offset
> obj
->size
|| args
->size
> obj
->size
||
480 args
->offset
+ args
->size
> obj
->size
) {
481 drm_gem_object_unreference_unlocked(obj
);
485 if (i915_gem_object_needs_bit17_swizzle(obj
)) {
486 ret
= i915_gem_shmem_pread_slow(dev
, obj
, args
, file_priv
);
488 ret
= i915_gem_shmem_pread_fast(dev
, obj
, args
, file_priv
);
490 ret
= i915_gem_shmem_pread_slow(dev
, obj
, args
,
494 drm_gem_object_unreference_unlocked(obj
);
499 /* This is the fast write path which cannot handle
500 * page faults in the source data
504 fast_user_write(struct io_mapping
*mapping
,
505 loff_t page_base
, int page_offset
,
506 char __user
*user_data
,
510 unsigned long unwritten
;
512 vaddr_atomic
= io_mapping_map_atomic_wc(mapping
, page_base
, KM_USER0
);
513 unwritten
= __copy_from_user_inatomic_nocache(vaddr_atomic
+ page_offset
,
515 io_mapping_unmap_atomic(vaddr_atomic
, KM_USER0
);
521 /* Here's the write path which can sleep for
526 slow_kernel_write(struct io_mapping
*mapping
,
527 loff_t gtt_base
, int gtt_offset
,
528 struct page
*user_page
, int user_offset
,
531 char __iomem
*dst_vaddr
;
534 dst_vaddr
= io_mapping_map_wc(mapping
, gtt_base
);
535 src_vaddr
= kmap(user_page
);
537 memcpy_toio(dst_vaddr
+ gtt_offset
,
538 src_vaddr
+ user_offset
,
542 io_mapping_unmap(dst_vaddr
);
546 fast_shmem_write(struct page
**pages
,
547 loff_t page_base
, int page_offset
,
552 unsigned long unwritten
;
554 vaddr
= kmap_atomic(pages
[page_base
>> PAGE_SHIFT
], KM_USER0
);
557 unwritten
= __copy_from_user_inatomic(vaddr
+ page_offset
, data
, length
);
558 kunmap_atomic(vaddr
, KM_USER0
);
566 * This is the fast pwrite path, where we copy the data directly from the
567 * user into the GTT, uncached.
570 i915_gem_gtt_pwrite_fast(struct drm_device
*dev
, struct drm_gem_object
*obj
,
571 struct drm_i915_gem_pwrite
*args
,
572 struct drm_file
*file_priv
)
574 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
575 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
577 loff_t offset
, page_base
;
578 char __user
*user_data
;
579 int page_offset
, page_length
;
582 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
584 if (!access_ok(VERIFY_READ
, user_data
, remain
))
588 mutex_lock(&dev
->struct_mutex
);
589 ret
= i915_gem_object_pin(obj
, 0);
591 mutex_unlock(&dev
->struct_mutex
);
594 ret
= i915_gem_object_set_to_gtt_domain(obj
, 1);
598 obj_priv
= to_intel_bo(obj
);
599 offset
= obj_priv
->gtt_offset
+ args
->offset
;
602 /* Operation in this page
604 * page_base = page offset within aperture
605 * page_offset = offset within page
606 * page_length = bytes to copy for this page
608 page_base
= (offset
& ~(PAGE_SIZE
-1));
609 page_offset
= offset
& (PAGE_SIZE
-1);
610 page_length
= remain
;
611 if ((page_offset
+ remain
) > PAGE_SIZE
)
612 page_length
= PAGE_SIZE
- page_offset
;
614 ret
= fast_user_write (dev_priv
->mm
.gtt_mapping
, page_base
,
615 page_offset
, user_data
, page_length
);
617 /* If we get a fault while copying data, then (presumably) our
618 * source page isn't available. Return the error and we'll
619 * retry in the slow path.
624 remain
-= page_length
;
625 user_data
+= page_length
;
626 offset
+= page_length
;
630 i915_gem_object_unpin(obj
);
631 mutex_unlock(&dev
->struct_mutex
);
637 * This is the fallback GTT pwrite path, which uses get_user_pages to pin
638 * the memory and maps it using kmap_atomic for copying.
640 * This code resulted in x11perf -rgb10text consuming about 10% more CPU
641 * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
644 i915_gem_gtt_pwrite_slow(struct drm_device
*dev
, struct drm_gem_object
*obj
,
645 struct drm_i915_gem_pwrite
*args
,
646 struct drm_file
*file_priv
)
648 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
649 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
651 loff_t gtt_page_base
, offset
;
652 loff_t first_data_page
, last_data_page
, num_pages
;
653 loff_t pinned_pages
, i
;
654 struct page
**user_pages
;
655 struct mm_struct
*mm
= current
->mm
;
656 int gtt_page_offset
, data_page_offset
, data_page_index
, page_length
;
658 uint64_t data_ptr
= args
->data_ptr
;
662 /* Pin the user pages containing the data. We can't fault while
663 * holding the struct mutex, and all of the pwrite implementations
664 * want to hold it while dereferencing the user data.
666 first_data_page
= data_ptr
/ PAGE_SIZE
;
667 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
668 num_pages
= last_data_page
- first_data_page
+ 1;
670 user_pages
= drm_calloc_large(num_pages
, sizeof(struct page
*));
671 if (user_pages
== NULL
)
674 down_read(&mm
->mmap_sem
);
675 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
676 num_pages
, 0, 0, user_pages
, NULL
);
677 up_read(&mm
->mmap_sem
);
678 if (pinned_pages
< num_pages
) {
680 goto out_unpin_pages
;
683 mutex_lock(&dev
->struct_mutex
);
684 ret
= i915_gem_object_pin(obj
, 0);
688 ret
= i915_gem_object_set_to_gtt_domain(obj
, 1);
690 goto out_unpin_object
;
692 obj_priv
= to_intel_bo(obj
);
693 offset
= obj_priv
->gtt_offset
+ args
->offset
;
696 /* Operation in this page
698 * gtt_page_base = page offset within aperture
699 * gtt_page_offset = offset within page in aperture
700 * data_page_index = page number in get_user_pages return
701 * data_page_offset = offset with data_page_index page.
702 * page_length = bytes to copy for this page
704 gtt_page_base
= offset
& PAGE_MASK
;
705 gtt_page_offset
= offset
& ~PAGE_MASK
;
706 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
707 data_page_offset
= data_ptr
& ~PAGE_MASK
;
709 page_length
= remain
;
710 if ((gtt_page_offset
+ page_length
) > PAGE_SIZE
)
711 page_length
= PAGE_SIZE
- gtt_page_offset
;
712 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
713 page_length
= PAGE_SIZE
- data_page_offset
;
715 slow_kernel_write(dev_priv
->mm
.gtt_mapping
,
716 gtt_page_base
, gtt_page_offset
,
717 user_pages
[data_page_index
],
721 remain
-= page_length
;
722 offset
+= page_length
;
723 data_ptr
+= page_length
;
727 i915_gem_object_unpin(obj
);
729 mutex_unlock(&dev
->struct_mutex
);
731 for (i
= 0; i
< pinned_pages
; i
++)
732 page_cache_release(user_pages
[i
]);
733 drm_free_large(user_pages
);
739 * This is the fast shmem pwrite path, which attempts to directly
740 * copy_from_user into the kmapped pages backing the object.
743 i915_gem_shmem_pwrite_fast(struct drm_device
*dev
, struct drm_gem_object
*obj
,
744 struct drm_i915_gem_pwrite
*args
,
745 struct drm_file
*file_priv
)
747 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
749 loff_t offset
, page_base
;
750 char __user
*user_data
;
751 int page_offset
, page_length
;
754 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
757 mutex_lock(&dev
->struct_mutex
);
759 ret
= i915_gem_object_get_pages(obj
, 0);
763 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
767 obj_priv
= to_intel_bo(obj
);
768 offset
= args
->offset
;
772 /* Operation in this page
774 * page_base = page offset within aperture
775 * page_offset = offset within page
776 * page_length = bytes to copy for this page
778 page_base
= (offset
& ~(PAGE_SIZE
-1));
779 page_offset
= offset
& (PAGE_SIZE
-1);
780 page_length
= remain
;
781 if ((page_offset
+ remain
) > PAGE_SIZE
)
782 page_length
= PAGE_SIZE
- page_offset
;
784 ret
= fast_shmem_write(obj_priv
->pages
,
785 page_base
, page_offset
,
786 user_data
, page_length
);
790 remain
-= page_length
;
791 user_data
+= page_length
;
792 offset
+= page_length
;
796 i915_gem_object_put_pages(obj
);
798 mutex_unlock(&dev
->struct_mutex
);
804 * This is the fallback shmem pwrite path, which uses get_user_pages to pin
805 * the memory and maps it using kmap_atomic for copying.
807 * This avoids taking mmap_sem for faulting on the user's address while the
808 * struct_mutex is held.
811 i915_gem_shmem_pwrite_slow(struct drm_device
*dev
, struct drm_gem_object
*obj
,
812 struct drm_i915_gem_pwrite
*args
,
813 struct drm_file
*file_priv
)
815 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
816 struct mm_struct
*mm
= current
->mm
;
817 struct page
**user_pages
;
819 loff_t offset
, pinned_pages
, i
;
820 loff_t first_data_page
, last_data_page
, num_pages
;
821 int shmem_page_index
, shmem_page_offset
;
822 int data_page_index
, data_page_offset
;
825 uint64_t data_ptr
= args
->data_ptr
;
826 int do_bit17_swizzling
;
830 /* Pin the user pages containing the data. We can't fault while
831 * holding the struct mutex, and all of the pwrite implementations
832 * want to hold it while dereferencing the user data.
834 first_data_page
= data_ptr
/ PAGE_SIZE
;
835 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
836 num_pages
= last_data_page
- first_data_page
+ 1;
838 user_pages
= drm_calloc_large(num_pages
, sizeof(struct page
*));
839 if (user_pages
== NULL
)
842 down_read(&mm
->mmap_sem
);
843 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
844 num_pages
, 0, 0, user_pages
, NULL
);
845 up_read(&mm
->mmap_sem
);
846 if (pinned_pages
< num_pages
) {
848 goto fail_put_user_pages
;
851 do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
853 mutex_lock(&dev
->struct_mutex
);
855 ret
= i915_gem_object_get_pages_or_evict(obj
);
859 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
863 obj_priv
= to_intel_bo(obj
);
864 offset
= args
->offset
;
868 /* Operation in this page
870 * shmem_page_index = page number within shmem file
871 * shmem_page_offset = offset within page in shmem file
872 * data_page_index = page number in get_user_pages return
873 * data_page_offset = offset with data_page_index page.
874 * page_length = bytes to copy for this page
876 shmem_page_index
= offset
/ PAGE_SIZE
;
877 shmem_page_offset
= offset
& ~PAGE_MASK
;
878 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
879 data_page_offset
= data_ptr
& ~PAGE_MASK
;
881 page_length
= remain
;
882 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
883 page_length
= PAGE_SIZE
- shmem_page_offset
;
884 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
885 page_length
= PAGE_SIZE
- data_page_offset
;
887 if (do_bit17_swizzling
) {
888 slow_shmem_bit17_copy(obj_priv
->pages
[shmem_page_index
],
890 user_pages
[data_page_index
],
895 slow_shmem_copy(obj_priv
->pages
[shmem_page_index
],
897 user_pages
[data_page_index
],
902 remain
-= page_length
;
903 data_ptr
+= page_length
;
904 offset
+= page_length
;
908 i915_gem_object_put_pages(obj
);
910 mutex_unlock(&dev
->struct_mutex
);
912 for (i
= 0; i
< pinned_pages
; i
++)
913 page_cache_release(user_pages
[i
]);
914 drm_free_large(user_pages
);
920 * Writes data to the object referenced by handle.
922 * On error, the contents of the buffer that were to be modified are undefined.
925 i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
926 struct drm_file
*file_priv
)
928 struct drm_i915_gem_pwrite
*args
= data
;
929 struct drm_gem_object
*obj
;
930 struct drm_i915_gem_object
*obj_priv
;
933 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
936 obj_priv
= to_intel_bo(obj
);
938 /* Bounds check destination.
940 * XXX: This could use review for overflow issues...
942 if (args
->offset
> obj
->size
|| args
->size
> obj
->size
||
943 args
->offset
+ args
->size
> obj
->size
) {
944 drm_gem_object_unreference_unlocked(obj
);
948 /* We can only do the GTT pwrite on untiled buffers, as otherwise
949 * it would end up going through the fenced access, and we'll get
950 * different detiling behavior between reading and writing.
951 * pread/pwrite currently are reading and writing from the CPU
952 * perspective, requiring manual detiling by the client.
954 if (obj_priv
->phys_obj
)
955 ret
= i915_gem_phys_pwrite(dev
, obj
, args
, file_priv
);
956 else if (obj_priv
->tiling_mode
== I915_TILING_NONE
&&
957 dev
->gtt_total
!= 0 &&
958 obj
->write_domain
!= I915_GEM_DOMAIN_CPU
) {
959 ret
= i915_gem_gtt_pwrite_fast(dev
, obj
, args
, file_priv
);
960 if (ret
== -EFAULT
) {
961 ret
= i915_gem_gtt_pwrite_slow(dev
, obj
, args
,
964 } else if (i915_gem_object_needs_bit17_swizzle(obj
)) {
965 ret
= i915_gem_shmem_pwrite_slow(dev
, obj
, args
, file_priv
);
967 ret
= i915_gem_shmem_pwrite_fast(dev
, obj
, args
, file_priv
);
968 if (ret
== -EFAULT
) {
969 ret
= i915_gem_shmem_pwrite_slow(dev
, obj
, args
,
976 DRM_INFO("pwrite failed %d\n", ret
);
979 drm_gem_object_unreference_unlocked(obj
);
985 * Called when user space prepares to use an object with the CPU, either
986 * through the mmap ioctl's mapping or a GTT mapping.
989 i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
990 struct drm_file
*file_priv
)
992 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
993 struct drm_i915_gem_set_domain
*args
= data
;
994 struct drm_gem_object
*obj
;
995 struct drm_i915_gem_object
*obj_priv
;
996 uint32_t read_domains
= args
->read_domains
;
997 uint32_t write_domain
= args
->write_domain
;
1000 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1003 /* Only handle setting domains to types used by the CPU. */
1004 if (write_domain
& I915_GEM_GPU_DOMAINS
)
1007 if (read_domains
& I915_GEM_GPU_DOMAINS
)
1010 /* Having something in the write domain implies it's in the read
1011 * domain, and only that read domain. Enforce that in the request.
1013 if (write_domain
!= 0 && read_domains
!= write_domain
)
1016 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1019 obj_priv
= to_intel_bo(obj
);
1021 mutex_lock(&dev
->struct_mutex
);
1023 intel_mark_busy(dev
, obj
);
1026 DRM_INFO("set_domain_ioctl %p(%zd), %08x %08x\n",
1027 obj
, obj
->size
, read_domains
, write_domain
);
1029 if (read_domains
& I915_GEM_DOMAIN_GTT
) {
1030 ret
= i915_gem_object_set_to_gtt_domain(obj
, write_domain
!= 0);
1032 /* Update the LRU on the fence for the CPU access that's
1035 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
) {
1036 struct drm_i915_fence_reg
*reg
=
1037 &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
1038 list_move_tail(®
->lru_list
,
1039 &dev_priv
->mm
.fence_list
);
1042 /* Silently promote "you're not bound, there was nothing to do"
1043 * to success, since the client was just asking us to
1044 * make sure everything was done.
1049 ret
= i915_gem_object_set_to_cpu_domain(obj
, write_domain
!= 0);
1053 /* Maintain LRU order of "inactive" objects */
1054 if (ret
== 0 && i915_gem_object_is_inactive(obj_priv
))
1055 list_move_tail(&obj_priv
->list
, &dev_priv
->mm
.inactive_list
);
1057 drm_gem_object_unreference(obj
);
1058 mutex_unlock(&dev
->struct_mutex
);
1063 * Called when user space has done writes to this buffer
1066 i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1067 struct drm_file
*file_priv
)
1069 struct drm_i915_gem_sw_finish
*args
= data
;
1070 struct drm_gem_object
*obj
;
1071 struct drm_i915_gem_object
*obj_priv
;
1074 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1077 mutex_lock(&dev
->struct_mutex
);
1078 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1080 mutex_unlock(&dev
->struct_mutex
);
1085 DRM_INFO("%s: sw_finish %d (%p %zd)\n",
1086 __func__
, args
->handle
, obj
, obj
->size
);
1088 obj_priv
= to_intel_bo(obj
);
1090 /* Pinned buffers may be scanout, so flush the cache */
1091 if (obj_priv
->pin_count
)
1092 i915_gem_object_flush_cpu_write_domain(obj
);
1094 drm_gem_object_unreference(obj
);
1095 mutex_unlock(&dev
->struct_mutex
);
1100 * Maps the contents of an object, returning the address it is mapped
1103 * While the mapping holds a reference on the contents of the object, it doesn't
1104 * imply a ref on the object itself.
1107 i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1108 struct drm_file
*file_priv
)
1110 struct drm_i915_gem_mmap
*args
= data
;
1111 struct drm_gem_object
*obj
;
1115 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1118 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1122 offset
= args
->offset
;
1124 down_write(¤t
->mm
->mmap_sem
);
1125 addr
= do_mmap(obj
->filp
, 0, args
->size
,
1126 PROT_READ
| PROT_WRITE
, MAP_SHARED
,
1128 up_write(¤t
->mm
->mmap_sem
);
1129 drm_gem_object_unreference_unlocked(obj
);
1130 if (IS_ERR((void *)addr
))
1133 args
->addr_ptr
= (uint64_t) addr
;
1139 * i915_gem_fault - fault a page into the GTT
1140 * vma: VMA in question
1143 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1144 * from userspace. The fault handler takes care of binding the object to
1145 * the GTT (if needed), allocating and programming a fence register (again,
1146 * only if needed based on whether the old reg is still valid or the object
1147 * is tiled) and inserting a new PTE into the faulting process.
1149 * Note that the faulting process may involve evicting existing objects
1150 * from the GTT and/or fence registers to make room. So performance may
1151 * suffer if the GTT working set is large or there are few fence registers
1154 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
)
1156 struct drm_gem_object
*obj
= vma
->vm_private_data
;
1157 struct drm_device
*dev
= obj
->dev
;
1158 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1159 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1160 pgoff_t page_offset
;
1163 bool write
= !!(vmf
->flags
& FAULT_FLAG_WRITE
);
1165 /* We don't use vmf->pgoff since that has the fake offset */
1166 page_offset
= ((unsigned long)vmf
->virtual_address
- vma
->vm_start
) >>
1169 /* Now bind it into the GTT if needed */
1170 mutex_lock(&dev
->struct_mutex
);
1171 if (!obj_priv
->gtt_space
) {
1172 ret
= i915_gem_object_bind_to_gtt(obj
, 0);
1176 ret
= i915_gem_object_set_to_gtt_domain(obj
, write
);
1181 /* Need a new fence register? */
1182 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
) {
1183 ret
= i915_gem_object_get_fence_reg(obj
);
1188 if (i915_gem_object_is_inactive(obj_priv
))
1189 list_move_tail(&obj_priv
->list
, &dev_priv
->mm
.inactive_list
);
1191 pfn
= ((dev
->agp
->base
+ obj_priv
->gtt_offset
) >> PAGE_SHIFT
) +
1194 /* Finally, remap it using the new GTT offset */
1195 ret
= vm_insert_pfn(vma
, (unsigned long)vmf
->virtual_address
, pfn
);
1197 mutex_unlock(&dev
->struct_mutex
);
1202 return VM_FAULT_NOPAGE
;
1205 return VM_FAULT_OOM
;
1207 return VM_FAULT_SIGBUS
;
1212 * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1213 * @obj: obj in question
1215 * GEM memory mapping works by handing back to userspace a fake mmap offset
1216 * it can use in a subsequent mmap(2) call. The DRM core code then looks
1217 * up the object based on the offset and sets up the various memory mapping
1220 * This routine allocates and attaches a fake offset for @obj.
1223 i915_gem_create_mmap_offset(struct drm_gem_object
*obj
)
1225 struct drm_device
*dev
= obj
->dev
;
1226 struct drm_gem_mm
*mm
= dev
->mm_private
;
1227 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1228 struct drm_map_list
*list
;
1229 struct drm_local_map
*map
;
1232 /* Set the object up for mmap'ing */
1233 list
= &obj
->map_list
;
1234 list
->map
= kzalloc(sizeof(struct drm_map_list
), GFP_KERNEL
);
1239 map
->type
= _DRM_GEM
;
1240 map
->size
= obj
->size
;
1243 /* Get a DRM GEM mmap offset allocated... */
1244 list
->file_offset_node
= drm_mm_search_free(&mm
->offset_manager
,
1245 obj
->size
/ PAGE_SIZE
, 0, 0);
1246 if (!list
->file_offset_node
) {
1247 DRM_ERROR("failed to allocate offset for bo %d\n", obj
->name
);
1252 list
->file_offset_node
= drm_mm_get_block(list
->file_offset_node
,
1253 obj
->size
/ PAGE_SIZE
, 0);
1254 if (!list
->file_offset_node
) {
1259 list
->hash
.key
= list
->file_offset_node
->start
;
1260 if (drm_ht_insert_item(&mm
->offset_hash
, &list
->hash
)) {
1261 DRM_ERROR("failed to add to map hash\n");
1266 /* By now we should be all set, any drm_mmap request on the offset
1267 * below will get to our mmap & fault handler */
1268 obj_priv
->mmap_offset
= ((uint64_t) list
->hash
.key
) << PAGE_SHIFT
;
1273 drm_mm_put_block(list
->file_offset_node
);
1281 * i915_gem_release_mmap - remove physical page mappings
1282 * @obj: obj in question
1284 * Preserve the reservation of the mmapping with the DRM core code, but
1285 * relinquish ownership of the pages back to the system.
1287 * It is vital that we remove the page mapping if we have mapped a tiled
1288 * object through the GTT and then lose the fence register due to
1289 * resource pressure. Similarly if the object has been moved out of the
1290 * aperture, than pages mapped into userspace must be revoked. Removing the
1291 * mapping will then trigger a page fault on the next user access, allowing
1292 * fixup by i915_gem_fault().
1295 i915_gem_release_mmap(struct drm_gem_object
*obj
)
1297 struct drm_device
*dev
= obj
->dev
;
1298 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1300 if (dev
->dev_mapping
)
1301 unmap_mapping_range(dev
->dev_mapping
,
1302 obj_priv
->mmap_offset
, obj
->size
, 1);
1306 i915_gem_free_mmap_offset(struct drm_gem_object
*obj
)
1308 struct drm_device
*dev
= obj
->dev
;
1309 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1310 struct drm_gem_mm
*mm
= dev
->mm_private
;
1311 struct drm_map_list
*list
;
1313 list
= &obj
->map_list
;
1314 drm_ht_remove_item(&mm
->offset_hash
, &list
->hash
);
1316 if (list
->file_offset_node
) {
1317 drm_mm_put_block(list
->file_offset_node
);
1318 list
->file_offset_node
= NULL
;
1326 obj_priv
->mmap_offset
= 0;
1330 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1331 * @obj: object to check
1333 * Return the required GTT alignment for an object, taking into account
1334 * potential fence register mapping if needed.
1337 i915_gem_get_gtt_alignment(struct drm_gem_object
*obj
)
1339 struct drm_device
*dev
= obj
->dev
;
1340 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1344 * Minimum alignment is 4k (GTT page size), but might be greater
1345 * if a fence register is needed for the object.
1347 if (IS_I965G(dev
) || obj_priv
->tiling_mode
== I915_TILING_NONE
)
1351 * Previous chips need to be aligned to the size of the smallest
1352 * fence register that can contain the object.
1359 for (i
= start
; i
< obj
->size
; i
<<= 1)
1366 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1368 * @data: GTT mapping ioctl data
1369 * @file_priv: GEM object info
1371 * Simply returns the fake offset to userspace so it can mmap it.
1372 * The mmap call will end up in drm_gem_mmap(), which will set things
1373 * up so we can get faults in the handler above.
1375 * The fault handler will take care of binding the object into the GTT
1376 * (since it may have been evicted to make room for something), allocating
1377 * a fence register, and mapping the appropriate aperture address into
1381 i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
1382 struct drm_file
*file_priv
)
1384 struct drm_i915_gem_mmap_gtt
*args
= data
;
1385 struct drm_gem_object
*obj
;
1386 struct drm_i915_gem_object
*obj_priv
;
1389 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1392 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1396 mutex_lock(&dev
->struct_mutex
);
1398 obj_priv
= to_intel_bo(obj
);
1400 if (obj_priv
->madv
!= I915_MADV_WILLNEED
) {
1401 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1402 drm_gem_object_unreference(obj
);
1403 mutex_unlock(&dev
->struct_mutex
);
1408 if (!obj_priv
->mmap_offset
) {
1409 ret
= i915_gem_create_mmap_offset(obj
);
1411 drm_gem_object_unreference(obj
);
1412 mutex_unlock(&dev
->struct_mutex
);
1417 args
->offset
= obj_priv
->mmap_offset
;
1420 * Pull it into the GTT so that we have a page list (makes the
1421 * initial fault faster and any subsequent flushing possible).
1423 if (!obj_priv
->agp_mem
) {
1424 ret
= i915_gem_object_bind_to_gtt(obj
, 0);
1426 drm_gem_object_unreference(obj
);
1427 mutex_unlock(&dev
->struct_mutex
);
1432 drm_gem_object_unreference(obj
);
1433 mutex_unlock(&dev
->struct_mutex
);
1439 i915_gem_object_put_pages(struct drm_gem_object
*obj
)
1441 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1442 int page_count
= obj
->size
/ PAGE_SIZE
;
1445 BUG_ON(obj_priv
->pages_refcount
== 0);
1446 BUG_ON(obj_priv
->madv
== __I915_MADV_PURGED
);
1448 if (--obj_priv
->pages_refcount
!= 0)
1451 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
)
1452 i915_gem_object_save_bit_17_swizzle(obj
);
1454 if (obj_priv
->madv
== I915_MADV_DONTNEED
)
1455 obj_priv
->dirty
= 0;
1457 for (i
= 0; i
< page_count
; i
++) {
1458 if (obj_priv
->dirty
)
1459 set_page_dirty(obj_priv
->pages
[i
]);
1461 if (obj_priv
->madv
== I915_MADV_WILLNEED
)
1462 mark_page_accessed(obj_priv
->pages
[i
]);
1464 page_cache_release(obj_priv
->pages
[i
]);
1466 obj_priv
->dirty
= 0;
1468 drm_free_large(obj_priv
->pages
);
1469 obj_priv
->pages
= NULL
;
1473 i915_gem_next_request_seqno(struct drm_device
*dev
)
1475 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1477 return dev_priv
->next_seqno
;
1481 i915_gem_object_move_to_active(struct drm_gem_object
*obj
, uint32_t seqno
,
1482 struct intel_ring_buffer
*ring
)
1484 struct drm_device
*dev
= obj
->dev
;
1485 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1486 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1487 BUG_ON(ring
== NULL
);
1488 obj_priv
->ring
= ring
;
1490 /* Add a reference if we're newly entering the active list. */
1491 if (!obj_priv
->active
) {
1492 drm_gem_object_reference(obj
);
1493 obj_priv
->active
= 1;
1496 /* Take the seqno of the next request if none is given */
1498 seqno
= i915_gem_next_request_seqno(dev
);
1500 /* Move from whatever list we were on to the tail of execution. */
1501 spin_lock(&dev_priv
->mm
.active_list_lock
);
1502 list_move_tail(&obj_priv
->list
, &ring
->active_list
);
1503 spin_unlock(&dev_priv
->mm
.active_list_lock
);
1504 obj_priv
->last_rendering_seqno
= seqno
;
1508 i915_gem_object_move_to_flushing(struct drm_gem_object
*obj
)
1510 struct drm_device
*dev
= obj
->dev
;
1511 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1512 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1514 BUG_ON(!obj_priv
->active
);
1515 list_move_tail(&obj_priv
->list
, &dev_priv
->mm
.flushing_list
);
1516 obj_priv
->last_rendering_seqno
= 0;
1519 /* Immediately discard the backing storage */
1521 i915_gem_object_truncate(struct drm_gem_object
*obj
)
1523 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1524 struct inode
*inode
;
1526 /* Our goal here is to return as much of the memory as
1527 * is possible back to the system as we are called from OOM.
1528 * To do this we must instruct the shmfs to drop all of its
1529 * backing pages, *now*. Here we mirror the actions taken
1530 * when by shmem_delete_inode() to release the backing store.
1532 inode
= obj
->filp
->f_path
.dentry
->d_inode
;
1533 truncate_inode_pages(inode
->i_mapping
, 0);
1534 if (inode
->i_op
->truncate_range
)
1535 inode
->i_op
->truncate_range(inode
, 0, (loff_t
)-1);
1537 obj_priv
->madv
= __I915_MADV_PURGED
;
1541 i915_gem_object_is_purgeable(struct drm_i915_gem_object
*obj_priv
)
1543 return obj_priv
->madv
== I915_MADV_DONTNEED
;
1547 i915_gem_object_move_to_inactive(struct drm_gem_object
*obj
)
1549 struct drm_device
*dev
= obj
->dev
;
1550 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1551 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1553 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
1554 if (obj_priv
->pin_count
!= 0)
1555 list_del_init(&obj_priv
->list
);
1557 list_move_tail(&obj_priv
->list
, &dev_priv
->mm
.inactive_list
);
1559 BUG_ON(!list_empty(&obj_priv
->gpu_write_list
));
1561 obj_priv
->last_rendering_seqno
= 0;
1562 obj_priv
->ring
= NULL
;
1563 if (obj_priv
->active
) {
1564 obj_priv
->active
= 0;
1565 drm_gem_object_unreference(obj
);
1567 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
1571 i915_gem_process_flushing_list(struct drm_device
*dev
,
1572 uint32_t flush_domains
, uint32_t seqno
,
1573 struct intel_ring_buffer
*ring
)
1575 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1576 struct drm_i915_gem_object
*obj_priv
, *next
;
1578 list_for_each_entry_safe(obj_priv
, next
,
1579 &dev_priv
->mm
.gpu_write_list
,
1581 struct drm_gem_object
*obj
= &obj_priv
->base
;
1583 if ((obj
->write_domain
& flush_domains
) ==
1584 obj
->write_domain
&&
1585 obj_priv
->ring
->ring_flag
== ring
->ring_flag
) {
1586 uint32_t old_write_domain
= obj
->write_domain
;
1588 obj
->write_domain
= 0;
1589 list_del_init(&obj_priv
->gpu_write_list
);
1590 i915_gem_object_move_to_active(obj
, seqno
, ring
);
1592 /* update the fence lru list */
1593 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
) {
1594 struct drm_i915_fence_reg
*reg
=
1595 &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
1596 list_move_tail(®
->lru_list
,
1597 &dev_priv
->mm
.fence_list
);
1600 trace_i915_gem_object_change_domain(obj
,
1608 i915_add_request(struct drm_device
*dev
, struct drm_file
*file_priv
,
1609 uint32_t flush_domains
, struct intel_ring_buffer
*ring
)
1611 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1612 struct drm_i915_file_private
*i915_file_priv
= NULL
;
1613 struct drm_i915_gem_request
*request
;
1617 if (file_priv
!= NULL
)
1618 i915_file_priv
= file_priv
->driver_priv
;
1620 request
= kzalloc(sizeof(*request
), GFP_KERNEL
);
1621 if (request
== NULL
)
1624 seqno
= ring
->add_request(dev
, ring
, file_priv
, flush_domains
);
1626 request
->seqno
= seqno
;
1627 request
->ring
= ring
;
1628 request
->emitted_jiffies
= jiffies
;
1629 was_empty
= list_empty(&ring
->request_list
);
1630 list_add_tail(&request
->list
, &ring
->request_list
);
1632 if (i915_file_priv
) {
1633 list_add_tail(&request
->client_list
,
1634 &i915_file_priv
->mm
.request_list
);
1636 INIT_LIST_HEAD(&request
->client_list
);
1639 /* Associate any objects on the flushing list matching the write
1640 * domain we're flushing with our flush.
1642 if (flush_domains
!= 0)
1643 i915_gem_process_flushing_list(dev
, flush_domains
, seqno
, ring
);
1645 if (!dev_priv
->mm
.suspended
) {
1646 mod_timer(&dev_priv
->hangcheck_timer
, jiffies
+ DRM_I915_HANGCHECK_PERIOD
);
1648 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, HZ
);
1654 * Command execution barrier
1656 * Ensures that all commands in the ring are finished
1657 * before signalling the CPU
1660 i915_retire_commands(struct drm_device
*dev
, struct intel_ring_buffer
*ring
)
1662 uint32_t flush_domains
= 0;
1664 /* The sampler always gets flushed on i965 (sigh) */
1666 flush_domains
|= I915_GEM_DOMAIN_SAMPLER
;
1668 ring
->flush(dev
, ring
,
1669 I915_GEM_DOMAIN_COMMAND
, flush_domains
);
1670 return flush_domains
;
1674 * Moves buffers associated only with the given active seqno from the active
1675 * to inactive list, potentially freeing them.
1678 i915_gem_retire_request(struct drm_device
*dev
,
1679 struct drm_i915_gem_request
*request
)
1681 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1683 trace_i915_gem_request_retire(dev
, request
->seqno
);
1685 /* Move any buffers on the active list that are no longer referenced
1686 * by the ringbuffer to the flushing/inactive lists as appropriate.
1688 spin_lock(&dev_priv
->mm
.active_list_lock
);
1689 while (!list_empty(&request
->ring
->active_list
)) {
1690 struct drm_gem_object
*obj
;
1691 struct drm_i915_gem_object
*obj_priv
;
1693 obj_priv
= list_first_entry(&request
->ring
->active_list
,
1694 struct drm_i915_gem_object
,
1696 obj
= &obj_priv
->base
;
1698 /* If the seqno being retired doesn't match the oldest in the
1699 * list, then the oldest in the list must still be newer than
1702 if (obj_priv
->last_rendering_seqno
!= request
->seqno
)
1706 DRM_INFO("%s: retire %d moves to inactive list %p\n",
1707 __func__
, request
->seqno
, obj
);
1710 if (obj
->write_domain
!= 0)
1711 i915_gem_object_move_to_flushing(obj
);
1713 /* Take a reference on the object so it won't be
1714 * freed while the spinlock is held. The list
1715 * protection for this spinlock is safe when breaking
1716 * the lock like this since the next thing we do
1717 * is just get the head of the list again.
1719 drm_gem_object_reference(obj
);
1720 i915_gem_object_move_to_inactive(obj
);
1721 spin_unlock(&dev_priv
->mm
.active_list_lock
);
1722 drm_gem_object_unreference(obj
);
1723 spin_lock(&dev_priv
->mm
.active_list_lock
);
1727 spin_unlock(&dev_priv
->mm
.active_list_lock
);
1731 * Returns true if seq1 is later than seq2.
1734 i915_seqno_passed(uint32_t seq1
, uint32_t seq2
)
1736 return (int32_t)(seq1
- seq2
) >= 0;
1740 i915_get_gem_seqno(struct drm_device
*dev
,
1741 struct intel_ring_buffer
*ring
)
1743 return ring
->get_gem_seqno(dev
, ring
);
1747 * This function clears the request list as sequence numbers are passed.
1750 i915_gem_retire_requests_ring(struct drm_device
*dev
,
1751 struct intel_ring_buffer
*ring
)
1753 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1756 if (!ring
->status_page
.page_addr
1757 || list_empty(&ring
->request_list
))
1760 seqno
= i915_get_gem_seqno(dev
, ring
);
1762 while (!list_empty(&ring
->request_list
)) {
1763 struct drm_i915_gem_request
*request
;
1764 uint32_t retiring_seqno
;
1766 request
= list_first_entry(&ring
->request_list
,
1767 struct drm_i915_gem_request
,
1769 retiring_seqno
= request
->seqno
;
1771 if (i915_seqno_passed(seqno
, retiring_seqno
) ||
1772 atomic_read(&dev_priv
->mm
.wedged
)) {
1773 i915_gem_retire_request(dev
, request
);
1775 list_del(&request
->list
);
1776 list_del(&request
->client_list
);
1782 if (unlikely (dev_priv
->trace_irq_seqno
&&
1783 i915_seqno_passed(dev_priv
->trace_irq_seqno
, seqno
))) {
1785 ring
->user_irq_put(dev
, ring
);
1786 dev_priv
->trace_irq_seqno
= 0;
1791 i915_gem_retire_requests(struct drm_device
*dev
)
1793 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1795 if (!list_empty(&dev_priv
->mm
.deferred_free_list
)) {
1796 struct drm_i915_gem_object
*obj_priv
, *tmp
;
1798 /* We must be careful that during unbind() we do not
1799 * accidentally infinitely recurse into retire requests.
1801 * retire -> free -> unbind -> wait -> retire_ring
1803 list_for_each_entry_safe(obj_priv
, tmp
,
1804 &dev_priv
->mm
.deferred_free_list
,
1806 i915_gem_free_object_tail(&obj_priv
->base
);
1809 i915_gem_retire_requests_ring(dev
, &dev_priv
->render_ring
);
1811 i915_gem_retire_requests_ring(dev
, &dev_priv
->bsd_ring
);
1815 i915_gem_retire_work_handler(struct work_struct
*work
)
1817 drm_i915_private_t
*dev_priv
;
1818 struct drm_device
*dev
;
1820 dev_priv
= container_of(work
, drm_i915_private_t
,
1821 mm
.retire_work
.work
);
1822 dev
= dev_priv
->dev
;
1824 mutex_lock(&dev
->struct_mutex
);
1825 i915_gem_retire_requests(dev
);
1827 if (!dev_priv
->mm
.suspended
&&
1828 (!list_empty(&dev_priv
->render_ring
.request_list
) ||
1830 !list_empty(&dev_priv
->bsd_ring
.request_list
))))
1831 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, HZ
);
1832 mutex_unlock(&dev
->struct_mutex
);
1836 i915_do_wait_request(struct drm_device
*dev
, uint32_t seqno
,
1837 int interruptible
, struct intel_ring_buffer
*ring
)
1839 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1845 if (seqno
== dev_priv
->next_seqno
) {
1846 seqno
= i915_add_request(dev
, NULL
, 0, ring
);
1851 if (atomic_read(&dev_priv
->mm
.wedged
))
1854 if (!i915_seqno_passed(ring
->get_gem_seqno(dev
, ring
), seqno
)) {
1855 if (HAS_PCH_SPLIT(dev
))
1856 ier
= I915_READ(DEIER
) | I915_READ(GTIER
);
1858 ier
= I915_READ(IER
);
1860 DRM_ERROR("something (likely vbetool) disabled "
1861 "interrupts, re-enabling\n");
1862 i915_driver_irq_preinstall(dev
);
1863 i915_driver_irq_postinstall(dev
);
1866 trace_i915_gem_request_wait_begin(dev
, seqno
);
1868 ring
->waiting_gem_seqno
= seqno
;
1869 ring
->user_irq_get(dev
, ring
);
1871 ret
= wait_event_interruptible(ring
->irq_queue
,
1873 ring
->get_gem_seqno(dev
, ring
), seqno
)
1874 || atomic_read(&dev_priv
->mm
.wedged
));
1876 wait_event(ring
->irq_queue
,
1878 ring
->get_gem_seqno(dev
, ring
), seqno
)
1879 || atomic_read(&dev_priv
->mm
.wedged
));
1881 ring
->user_irq_put(dev
, ring
);
1882 ring
->waiting_gem_seqno
= 0;
1884 trace_i915_gem_request_wait_end(dev
, seqno
);
1886 if (atomic_read(&dev_priv
->mm
.wedged
))
1889 if (ret
&& ret
!= -ERESTARTSYS
)
1890 DRM_ERROR("%s returns %d (awaiting %d at %d)\n",
1891 __func__
, ret
, seqno
, ring
->get_gem_seqno(dev
, ring
));
1893 /* Directly dispatch request retiring. While we have the work queue
1894 * to handle this, the waiter on a request often wants an associated
1895 * buffer to have made it to the inactive list, and we would need
1896 * a separate wait queue to handle that.
1899 i915_gem_retire_requests_ring(dev
, ring
);
1905 * Waits for a sequence number to be signaled, and cleans up the
1906 * request and object lists appropriately for that event.
1909 i915_wait_request(struct drm_device
*dev
, uint32_t seqno
,
1910 struct intel_ring_buffer
*ring
)
1912 return i915_do_wait_request(dev
, seqno
, 1, ring
);
1916 i915_gem_flush(struct drm_device
*dev
,
1917 uint32_t invalidate_domains
,
1918 uint32_t flush_domains
)
1920 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1921 if (flush_domains
& I915_GEM_DOMAIN_CPU
)
1922 drm_agp_chipset_flush(dev
);
1923 dev_priv
->render_ring
.flush(dev
, &dev_priv
->render_ring
,
1928 dev_priv
->bsd_ring
.flush(dev
, &dev_priv
->bsd_ring
,
1934 * Ensures that all rendering to the object has completed and the object is
1935 * safe to unbind from the GTT or access from the CPU.
1938 i915_gem_object_wait_rendering(struct drm_gem_object
*obj
,
1941 struct drm_device
*dev
= obj
->dev
;
1942 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1945 /* This function only exists to support waiting for existing rendering,
1946 * not for emitting required flushes.
1948 BUG_ON((obj
->write_domain
& I915_GEM_GPU_DOMAINS
) != 0);
1950 /* If there is rendering queued on the buffer being evicted, wait for
1953 if (obj_priv
->active
) {
1955 DRM_INFO("%s: object %p wait for seqno %08x\n",
1956 __func__
, obj
, obj_priv
->last_rendering_seqno
);
1958 ret
= i915_do_wait_request(dev
,
1959 obj_priv
->last_rendering_seqno
,
1970 * Unbinds an object from the GTT aperture.
1973 i915_gem_object_unbind(struct drm_gem_object
*obj
)
1975 struct drm_device
*dev
= obj
->dev
;
1976 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1977 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1981 DRM_INFO("%s:%d %p\n", __func__
, __LINE__
, obj
);
1982 DRM_INFO("gtt_space %p\n", obj_priv
->gtt_space
);
1984 if (obj_priv
->gtt_space
== NULL
)
1987 if (obj_priv
->pin_count
!= 0) {
1988 DRM_ERROR("Attempting to unbind pinned buffer\n");
1992 /* blow away mappings if mapped through GTT */
1993 i915_gem_release_mmap(obj
);
1995 /* Move the object to the CPU domain to ensure that
1996 * any possible CPU writes while it's not in the GTT
1997 * are flushed when we go to remap it. This will
1998 * also ensure that all pending GPU writes are finished
2001 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
2002 if (ret
== -ERESTARTSYS
)
2004 /* Continue on if we fail due to EIO, the GPU is hung so we
2005 * should be safe and we need to cleanup or else we might
2006 * cause memory corruption through use-after-free.
2009 /* release the fence reg _after_ flushing */
2010 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
)
2011 i915_gem_clear_fence_reg(obj
);
2013 if (obj_priv
->agp_mem
!= NULL
) {
2014 drm_unbind_agp(obj_priv
->agp_mem
);
2015 drm_free_agp(obj_priv
->agp_mem
, obj
->size
/ PAGE_SIZE
);
2016 obj_priv
->agp_mem
= NULL
;
2019 i915_gem_object_put_pages(obj
);
2020 BUG_ON(obj_priv
->pages_refcount
);
2022 if (obj_priv
->gtt_space
) {
2023 atomic_dec(&dev
->gtt_count
);
2024 atomic_sub(obj
->size
, &dev
->gtt_memory
);
2026 drm_mm_put_block(obj_priv
->gtt_space
);
2027 obj_priv
->gtt_space
= NULL
;
2030 /* Remove ourselves from the LRU list if present. */
2031 spin_lock(&dev_priv
->mm
.active_list_lock
);
2032 if (!list_empty(&obj_priv
->list
))
2033 list_del_init(&obj_priv
->list
);
2034 spin_unlock(&dev_priv
->mm
.active_list_lock
);
2036 if (i915_gem_object_is_purgeable(obj_priv
))
2037 i915_gem_object_truncate(obj
);
2039 trace_i915_gem_object_unbind(obj
);
2045 i915_gpu_idle(struct drm_device
*dev
)
2047 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2049 uint32_t seqno1
, seqno2
;
2052 spin_lock(&dev_priv
->mm
.active_list_lock
);
2053 lists_empty
= (list_empty(&dev_priv
->mm
.flushing_list
) &&
2054 list_empty(&dev_priv
->render_ring
.active_list
) &&
2056 list_empty(&dev_priv
->bsd_ring
.active_list
)));
2057 spin_unlock(&dev_priv
->mm
.active_list_lock
);
2062 /* Flush everything onto the inactive list. */
2063 i915_gem_flush(dev
, I915_GEM_GPU_DOMAINS
, I915_GEM_GPU_DOMAINS
);
2064 seqno1
= i915_add_request(dev
, NULL
, I915_GEM_GPU_DOMAINS
,
2065 &dev_priv
->render_ring
);
2068 ret
= i915_wait_request(dev
, seqno1
, &dev_priv
->render_ring
);
2071 seqno2
= i915_add_request(dev
, NULL
, I915_GEM_GPU_DOMAINS
,
2072 &dev_priv
->bsd_ring
);
2076 ret
= i915_wait_request(dev
, seqno2
, &dev_priv
->bsd_ring
);
2086 i915_gem_object_get_pages(struct drm_gem_object
*obj
,
2089 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2091 struct address_space
*mapping
;
2092 struct inode
*inode
;
2095 BUG_ON(obj_priv
->pages_refcount
2096 == DRM_I915_GEM_OBJECT_MAX_PAGES_REFCOUNT
);
2098 if (obj_priv
->pages_refcount
++ != 0)
2101 /* Get the list of pages out of our struct file. They'll be pinned
2102 * at this point until we release them.
2104 page_count
= obj
->size
/ PAGE_SIZE
;
2105 BUG_ON(obj_priv
->pages
!= NULL
);
2106 obj_priv
->pages
= drm_calloc_large(page_count
, sizeof(struct page
*));
2107 if (obj_priv
->pages
== NULL
) {
2108 obj_priv
->pages_refcount
--;
2112 inode
= obj
->filp
->f_path
.dentry
->d_inode
;
2113 mapping
= inode
->i_mapping
;
2114 for (i
= 0; i
< page_count
; i
++) {
2115 page
= read_cache_page_gfp(mapping
, i
,
2123 obj_priv
->pages
[i
] = page
;
2126 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
)
2127 i915_gem_object_do_bit_17_swizzle(obj
);
2133 page_cache_release(obj_priv
->pages
[i
]);
2135 drm_free_large(obj_priv
->pages
);
2136 obj_priv
->pages
= NULL
;
2137 obj_priv
->pages_refcount
--;
2138 return PTR_ERR(page
);
2141 static void sandybridge_write_fence_reg(struct drm_i915_fence_reg
*reg
)
2143 struct drm_gem_object
*obj
= reg
->obj
;
2144 struct drm_device
*dev
= obj
->dev
;
2145 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2146 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2147 int regnum
= obj_priv
->fence_reg
;
2150 val
= (uint64_t)((obj_priv
->gtt_offset
+ obj
->size
- 4096) &
2152 val
|= obj_priv
->gtt_offset
& 0xfffff000;
2153 val
|= (uint64_t)((obj_priv
->stride
/ 128) - 1) <<
2154 SANDYBRIDGE_FENCE_PITCH_SHIFT
;
2156 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2157 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
2158 val
|= I965_FENCE_REG_VALID
;
2160 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0
+ (regnum
* 8), val
);
2163 static void i965_write_fence_reg(struct drm_i915_fence_reg
*reg
)
2165 struct drm_gem_object
*obj
= reg
->obj
;
2166 struct drm_device
*dev
= obj
->dev
;
2167 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2168 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2169 int regnum
= obj_priv
->fence_reg
;
2172 val
= (uint64_t)((obj_priv
->gtt_offset
+ obj
->size
- 4096) &
2174 val
|= obj_priv
->gtt_offset
& 0xfffff000;
2175 val
|= ((obj_priv
->stride
/ 128) - 1) << I965_FENCE_PITCH_SHIFT
;
2176 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2177 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
2178 val
|= I965_FENCE_REG_VALID
;
2180 I915_WRITE64(FENCE_REG_965_0
+ (regnum
* 8), val
);
2183 static void i915_write_fence_reg(struct drm_i915_fence_reg
*reg
)
2185 struct drm_gem_object
*obj
= reg
->obj
;
2186 struct drm_device
*dev
= obj
->dev
;
2187 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2188 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2189 int regnum
= obj_priv
->fence_reg
;
2191 uint32_t fence_reg
, val
;
2194 if ((obj_priv
->gtt_offset
& ~I915_FENCE_START_MASK
) ||
2195 (obj_priv
->gtt_offset
& (obj
->size
- 1))) {
2196 WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
2197 __func__
, obj_priv
->gtt_offset
, obj
->size
);
2201 if (obj_priv
->tiling_mode
== I915_TILING_Y
&&
2202 HAS_128_BYTE_Y_TILING(dev
))
2207 /* Note: pitch better be a power of two tile widths */
2208 pitch_val
= obj_priv
->stride
/ tile_width
;
2209 pitch_val
= ffs(pitch_val
) - 1;
2211 if (obj_priv
->tiling_mode
== I915_TILING_Y
&&
2212 HAS_128_BYTE_Y_TILING(dev
))
2213 WARN_ON(pitch_val
> I830_FENCE_MAX_PITCH_VAL
);
2215 WARN_ON(pitch_val
> I915_FENCE_MAX_PITCH_VAL
);
2217 val
= obj_priv
->gtt_offset
;
2218 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2219 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2220 val
|= I915_FENCE_SIZE_BITS(obj
->size
);
2221 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2222 val
|= I830_FENCE_REG_VALID
;
2225 fence_reg
= FENCE_REG_830_0
+ (regnum
* 4);
2227 fence_reg
= FENCE_REG_945_8
+ ((regnum
- 8) * 4);
2228 I915_WRITE(fence_reg
, val
);
2231 static void i830_write_fence_reg(struct drm_i915_fence_reg
*reg
)
2233 struct drm_gem_object
*obj
= reg
->obj
;
2234 struct drm_device
*dev
= obj
->dev
;
2235 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2236 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2237 int regnum
= obj_priv
->fence_reg
;
2240 uint32_t fence_size_bits
;
2242 if ((obj_priv
->gtt_offset
& ~I830_FENCE_START_MASK
) ||
2243 (obj_priv
->gtt_offset
& (obj
->size
- 1))) {
2244 WARN(1, "%s: object 0x%08x not 512K or size aligned\n",
2245 __func__
, obj_priv
->gtt_offset
);
2249 pitch_val
= obj_priv
->stride
/ 128;
2250 pitch_val
= ffs(pitch_val
) - 1;
2251 WARN_ON(pitch_val
> I830_FENCE_MAX_PITCH_VAL
);
2253 val
= obj_priv
->gtt_offset
;
2254 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2255 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2256 fence_size_bits
= I830_FENCE_SIZE_BITS(obj
->size
);
2257 WARN_ON(fence_size_bits
& ~0x00000f00);
2258 val
|= fence_size_bits
;
2259 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2260 val
|= I830_FENCE_REG_VALID
;
2262 I915_WRITE(FENCE_REG_830_0
+ (regnum
* 4), val
);
2265 static int i915_find_fence_reg(struct drm_device
*dev
)
2267 struct drm_i915_fence_reg
*reg
= NULL
;
2268 struct drm_i915_gem_object
*obj_priv
= NULL
;
2269 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2270 struct drm_gem_object
*obj
= NULL
;
2273 /* First try to find a free reg */
2275 for (i
= dev_priv
->fence_reg_start
; i
< dev_priv
->num_fence_regs
; i
++) {
2276 reg
= &dev_priv
->fence_regs
[i
];
2280 obj_priv
= to_intel_bo(reg
->obj
);
2281 if (!obj_priv
->pin_count
)
2288 /* None available, try to steal one or wait for a user to finish */
2289 i
= I915_FENCE_REG_NONE
;
2290 list_for_each_entry(reg
, &dev_priv
->mm
.fence_list
,
2293 obj_priv
= to_intel_bo(obj
);
2295 if (obj_priv
->pin_count
)
2299 i
= obj_priv
->fence_reg
;
2303 BUG_ON(i
== I915_FENCE_REG_NONE
);
2305 /* We only have a reference on obj from the active list. put_fence_reg
2306 * might drop that one, causing a use-after-free in it. So hold a
2307 * private reference to obj like the other callers of put_fence_reg
2308 * (set_tiling ioctl) do. */
2309 drm_gem_object_reference(obj
);
2310 ret
= i915_gem_object_put_fence_reg(obj
);
2311 drm_gem_object_unreference(obj
);
2319 * i915_gem_object_get_fence_reg - set up a fence reg for an object
2320 * @obj: object to map through a fence reg
2322 * When mapping objects through the GTT, userspace wants to be able to write
2323 * to them without having to worry about swizzling if the object is tiled.
2325 * This function walks the fence regs looking for a free one for @obj,
2326 * stealing one if it can't find any.
2328 * It then sets up the reg based on the object's properties: address, pitch
2329 * and tiling format.
2332 i915_gem_object_get_fence_reg(struct drm_gem_object
*obj
)
2334 struct drm_device
*dev
= obj
->dev
;
2335 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2336 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2337 struct drm_i915_fence_reg
*reg
= NULL
;
2340 /* Just update our place in the LRU if our fence is getting used. */
2341 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
) {
2342 reg
= &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
2343 list_move_tail(®
->lru_list
, &dev_priv
->mm
.fence_list
);
2347 switch (obj_priv
->tiling_mode
) {
2348 case I915_TILING_NONE
:
2349 WARN(1, "allocating a fence for non-tiled object?\n");
2352 if (!obj_priv
->stride
)
2354 WARN((obj_priv
->stride
& (512 - 1)),
2355 "object 0x%08x is X tiled but has non-512B pitch\n",
2356 obj_priv
->gtt_offset
);
2359 if (!obj_priv
->stride
)
2361 WARN((obj_priv
->stride
& (128 - 1)),
2362 "object 0x%08x is Y tiled but has non-128B pitch\n",
2363 obj_priv
->gtt_offset
);
2367 ret
= i915_find_fence_reg(dev
);
2371 obj_priv
->fence_reg
= ret
;
2372 reg
= &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
2373 list_add_tail(®
->lru_list
, &dev_priv
->mm
.fence_list
);
2378 sandybridge_write_fence_reg(reg
);
2379 else if (IS_I965G(dev
))
2380 i965_write_fence_reg(reg
);
2381 else if (IS_I9XX(dev
))
2382 i915_write_fence_reg(reg
);
2384 i830_write_fence_reg(reg
);
2386 trace_i915_gem_object_get_fence(obj
, obj_priv
->fence_reg
,
2387 obj_priv
->tiling_mode
);
2393 * i915_gem_clear_fence_reg - clear out fence register info
2394 * @obj: object to clear
2396 * Zeroes out the fence register itself and clears out the associated
2397 * data structures in dev_priv and obj_priv.
2400 i915_gem_clear_fence_reg(struct drm_gem_object
*obj
)
2402 struct drm_device
*dev
= obj
->dev
;
2403 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2404 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2405 struct drm_i915_fence_reg
*reg
=
2406 &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
2409 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0
+
2410 (obj_priv
->fence_reg
* 8), 0);
2411 } else if (IS_I965G(dev
)) {
2412 I915_WRITE64(FENCE_REG_965_0
+ (obj_priv
->fence_reg
* 8), 0);
2416 if (obj_priv
->fence_reg
< 8)
2417 fence_reg
= FENCE_REG_830_0
+ obj_priv
->fence_reg
* 4;
2419 fence_reg
= FENCE_REG_945_8
+ (obj_priv
->fence_reg
-
2422 I915_WRITE(fence_reg
, 0);
2426 obj_priv
->fence_reg
= I915_FENCE_REG_NONE
;
2427 list_del_init(®
->lru_list
);
2431 * i915_gem_object_put_fence_reg - waits on outstanding fenced access
2432 * to the buffer to finish, and then resets the fence register.
2433 * @obj: tiled object holding a fence register.
2435 * Zeroes out the fence register itself and clears out the associated
2436 * data structures in dev_priv and obj_priv.
2439 i915_gem_object_put_fence_reg(struct drm_gem_object
*obj
)
2441 struct drm_device
*dev
= obj
->dev
;
2442 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2444 if (obj_priv
->fence_reg
== I915_FENCE_REG_NONE
)
2447 /* If we've changed tiling, GTT-mappings of the object
2448 * need to re-fault to ensure that the correct fence register
2449 * setup is in place.
2451 i915_gem_release_mmap(obj
);
2453 /* On the i915, GPU access to tiled buffers is via a fence,
2454 * therefore we must wait for any outstanding access to complete
2455 * before clearing the fence.
2457 if (!IS_I965G(dev
)) {
2460 ret
= i915_gem_object_flush_gpu_write_domain(obj
);
2464 ret
= i915_gem_object_wait_rendering(obj
, true);
2469 i915_gem_object_flush_gtt_write_domain(obj
);
2470 i915_gem_clear_fence_reg (obj
);
2476 * Finds free space in the GTT aperture and binds the object there.
2479 i915_gem_object_bind_to_gtt(struct drm_gem_object
*obj
, unsigned alignment
)
2481 struct drm_device
*dev
= obj
->dev
;
2482 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2483 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2484 struct drm_mm_node
*free_space
;
2485 gfp_t gfpmask
= __GFP_NORETRY
| __GFP_NOWARN
;
2488 if (obj_priv
->madv
!= I915_MADV_WILLNEED
) {
2489 DRM_ERROR("Attempting to bind a purgeable object\n");
2494 alignment
= i915_gem_get_gtt_alignment(obj
);
2495 if (alignment
& (i915_gem_get_gtt_alignment(obj
) - 1)) {
2496 DRM_ERROR("Invalid object alignment requested %u\n", alignment
);
2500 /* If the object is bigger than the entire aperture, reject it early
2501 * before evicting everything in a vain attempt to find space.
2503 if (obj
->size
> dev
->gtt_total
) {
2504 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2509 free_space
= drm_mm_search_free(&dev_priv
->mm
.gtt_space
,
2510 obj
->size
, alignment
, 0);
2511 if (free_space
!= NULL
) {
2512 obj_priv
->gtt_space
= drm_mm_get_block(free_space
, obj
->size
,
2514 if (obj_priv
->gtt_space
!= NULL
)
2515 obj_priv
->gtt_offset
= obj_priv
->gtt_space
->start
;
2517 if (obj_priv
->gtt_space
== NULL
) {
2518 /* If the gtt is empty and we're still having trouble
2519 * fitting our object in, we're out of memory.
2522 DRM_INFO("%s: GTT full, evicting something\n", __func__
);
2524 ret
= i915_gem_evict_something(dev
, obj
->size
, alignment
);
2532 DRM_INFO("Binding object of size %zd at 0x%08x\n",
2533 obj
->size
, obj_priv
->gtt_offset
);
2535 ret
= i915_gem_object_get_pages(obj
, gfpmask
);
2537 drm_mm_put_block(obj_priv
->gtt_space
);
2538 obj_priv
->gtt_space
= NULL
;
2540 if (ret
== -ENOMEM
) {
2541 /* first try to clear up some space from the GTT */
2542 ret
= i915_gem_evict_something(dev
, obj
->size
,
2545 /* now try to shrink everyone else */
2560 /* Create an AGP memory structure pointing at our pages, and bind it
2563 obj_priv
->agp_mem
= drm_agp_bind_pages(dev
,
2565 obj
->size
>> PAGE_SHIFT
,
2566 obj_priv
->gtt_offset
,
2567 obj_priv
->agp_type
);
2568 if (obj_priv
->agp_mem
== NULL
) {
2569 i915_gem_object_put_pages(obj
);
2570 drm_mm_put_block(obj_priv
->gtt_space
);
2571 obj_priv
->gtt_space
= NULL
;
2573 ret
= i915_gem_evict_something(dev
, obj
->size
, alignment
);
2579 atomic_inc(&dev
->gtt_count
);
2580 atomic_add(obj
->size
, &dev
->gtt_memory
);
2582 /* keep track of bounds object by adding it to the inactive list */
2583 list_add_tail(&obj_priv
->list
, &dev_priv
->mm
.inactive_list
);
2585 /* Assert that the object is not currently in any GPU domain. As it
2586 * wasn't in the GTT, there shouldn't be any way it could have been in
2589 BUG_ON(obj
->read_domains
& I915_GEM_GPU_DOMAINS
);
2590 BUG_ON(obj
->write_domain
& I915_GEM_GPU_DOMAINS
);
2592 trace_i915_gem_object_bind(obj
, obj_priv
->gtt_offset
);
2598 i915_gem_clflush_object(struct drm_gem_object
*obj
)
2600 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2602 /* If we don't have a page list set up, then we're not pinned
2603 * to GPU, and we can ignore the cache flush because it'll happen
2604 * again at bind time.
2606 if (obj_priv
->pages
== NULL
)
2609 trace_i915_gem_object_clflush(obj
);
2611 drm_clflush_pages(obj_priv
->pages
, obj
->size
/ PAGE_SIZE
);
2614 /** Flushes any GPU write domain for the object if it's dirty. */
2616 i915_gem_object_flush_gpu_write_domain(struct drm_gem_object
*obj
)
2618 struct drm_device
*dev
= obj
->dev
;
2619 uint32_t old_write_domain
;
2620 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2622 if ((obj
->write_domain
& I915_GEM_GPU_DOMAINS
) == 0)
2625 /* Queue the GPU write cache flushing we need. */
2626 old_write_domain
= obj
->write_domain
;
2627 i915_gem_flush(dev
, 0, obj
->write_domain
);
2628 if (i915_add_request(dev
, NULL
, obj
->write_domain
, obj_priv
->ring
) == 0)
2631 trace_i915_gem_object_change_domain(obj
,
2637 /** Flushes the GTT write domain for the object if it's dirty. */
2639 i915_gem_object_flush_gtt_write_domain(struct drm_gem_object
*obj
)
2641 uint32_t old_write_domain
;
2643 if (obj
->write_domain
!= I915_GEM_DOMAIN_GTT
)
2646 /* No actual flushing is required for the GTT write domain. Writes
2647 * to it immediately go to main memory as far as we know, so there's
2648 * no chipset flush. It also doesn't land in render cache.
2650 old_write_domain
= obj
->write_domain
;
2651 obj
->write_domain
= 0;
2653 trace_i915_gem_object_change_domain(obj
,
2658 /** Flushes the CPU write domain for the object if it's dirty. */
2660 i915_gem_object_flush_cpu_write_domain(struct drm_gem_object
*obj
)
2662 struct drm_device
*dev
= obj
->dev
;
2663 uint32_t old_write_domain
;
2665 if (obj
->write_domain
!= I915_GEM_DOMAIN_CPU
)
2668 i915_gem_clflush_object(obj
);
2669 drm_agp_chipset_flush(dev
);
2670 old_write_domain
= obj
->write_domain
;
2671 obj
->write_domain
= 0;
2673 trace_i915_gem_object_change_domain(obj
,
2679 i915_gem_object_flush_write_domain(struct drm_gem_object
*obj
)
2683 switch (obj
->write_domain
) {
2684 case I915_GEM_DOMAIN_GTT
:
2685 i915_gem_object_flush_gtt_write_domain(obj
);
2687 case I915_GEM_DOMAIN_CPU
:
2688 i915_gem_object_flush_cpu_write_domain(obj
);
2691 ret
= i915_gem_object_flush_gpu_write_domain(obj
);
2699 * Moves a single object to the GTT read, and possibly write domain.
2701 * This function returns when the move is complete, including waiting on
2705 i915_gem_object_set_to_gtt_domain(struct drm_gem_object
*obj
, int write
)
2707 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2708 uint32_t old_write_domain
, old_read_domains
;
2711 /* Not valid to be called on unbound objects. */
2712 if (obj_priv
->gtt_space
== NULL
)
2715 ret
= i915_gem_object_flush_gpu_write_domain(obj
);
2719 /* Wait on any GPU rendering and flushing to occur. */
2720 ret
= i915_gem_object_wait_rendering(obj
, true);
2724 old_write_domain
= obj
->write_domain
;
2725 old_read_domains
= obj
->read_domains
;
2727 /* If we're writing through the GTT domain, then CPU and GPU caches
2728 * will need to be invalidated at next use.
2731 obj
->read_domains
&= I915_GEM_DOMAIN_GTT
;
2733 i915_gem_object_flush_cpu_write_domain(obj
);
2735 /* It should now be out of any other write domains, and we can update
2736 * the domain values for our changes.
2738 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
2739 obj
->read_domains
|= I915_GEM_DOMAIN_GTT
;
2741 obj
->write_domain
= I915_GEM_DOMAIN_GTT
;
2742 obj_priv
->dirty
= 1;
2745 trace_i915_gem_object_change_domain(obj
,
2753 * Prepare buffer for display plane. Use uninterruptible for possible flush
2754 * wait, as in modesetting process we're not supposed to be interrupted.
2757 i915_gem_object_set_to_display_plane(struct drm_gem_object
*obj
)
2759 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2760 uint32_t old_write_domain
, old_read_domains
;
2763 /* Not valid to be called on unbound objects. */
2764 if (obj_priv
->gtt_space
== NULL
)
2767 ret
= i915_gem_object_flush_gpu_write_domain(obj
);
2771 /* Wait on any GPU rendering and flushing to occur. */
2772 ret
= i915_gem_object_wait_rendering(obj
, false);
2776 i915_gem_object_flush_cpu_write_domain(obj
);
2778 old_write_domain
= obj
->write_domain
;
2779 old_read_domains
= obj
->read_domains
;
2781 /* It should now be out of any other write domains, and we can update
2782 * the domain values for our changes.
2784 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
2785 obj
->read_domains
= I915_GEM_DOMAIN_GTT
;
2786 obj
->write_domain
= I915_GEM_DOMAIN_GTT
;
2787 obj_priv
->dirty
= 1;
2789 trace_i915_gem_object_change_domain(obj
,
2797 * Moves a single object to the CPU read, and possibly write domain.
2799 * This function returns when the move is complete, including waiting on
2803 i915_gem_object_set_to_cpu_domain(struct drm_gem_object
*obj
, int write
)
2805 uint32_t old_write_domain
, old_read_domains
;
2808 ret
= i915_gem_object_flush_gpu_write_domain(obj
);
2812 /* Wait on any GPU rendering and flushing to occur. */
2813 ret
= i915_gem_object_wait_rendering(obj
, true);
2817 i915_gem_object_flush_gtt_write_domain(obj
);
2819 /* If we have a partially-valid cache of the object in the CPU,
2820 * finish invalidating it and free the per-page flags.
2822 i915_gem_object_set_to_full_cpu_read_domain(obj
);
2824 old_write_domain
= obj
->write_domain
;
2825 old_read_domains
= obj
->read_domains
;
2827 /* Flush the CPU cache if it's still invalid. */
2828 if ((obj
->read_domains
& I915_GEM_DOMAIN_CPU
) == 0) {
2829 i915_gem_clflush_object(obj
);
2831 obj
->read_domains
|= I915_GEM_DOMAIN_CPU
;
2834 /* It should now be out of any other write domains, and we can update
2835 * the domain values for our changes.
2837 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
2839 /* If we're writing through the CPU, then the GPU read domains will
2840 * need to be invalidated at next use.
2843 obj
->read_domains
&= I915_GEM_DOMAIN_CPU
;
2844 obj
->write_domain
= I915_GEM_DOMAIN_CPU
;
2847 trace_i915_gem_object_change_domain(obj
,
2855 * Set the next domain for the specified object. This
2856 * may not actually perform the necessary flushing/invaliding though,
2857 * as that may want to be batched with other set_domain operations
2859 * This is (we hope) the only really tricky part of gem. The goal
2860 * is fairly simple -- track which caches hold bits of the object
2861 * and make sure they remain coherent. A few concrete examples may
2862 * help to explain how it works. For shorthand, we use the notation
2863 * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
2864 * a pair of read and write domain masks.
2866 * Case 1: the batch buffer
2872 * 5. Unmapped from GTT
2875 * Let's take these a step at a time
2878 * Pages allocated from the kernel may still have
2879 * cache contents, so we set them to (CPU, CPU) always.
2880 * 2. Written by CPU (using pwrite)
2881 * The pwrite function calls set_domain (CPU, CPU) and
2882 * this function does nothing (as nothing changes)
2884 * This function asserts that the object is not
2885 * currently in any GPU-based read or write domains
2887 * i915_gem_execbuffer calls set_domain (COMMAND, 0).
2888 * As write_domain is zero, this function adds in the
2889 * current read domains (CPU+COMMAND, 0).
2890 * flush_domains is set to CPU.
2891 * invalidate_domains is set to COMMAND
2892 * clflush is run to get data out of the CPU caches
2893 * then i915_dev_set_domain calls i915_gem_flush to
2894 * emit an MI_FLUSH and drm_agp_chipset_flush
2895 * 5. Unmapped from GTT
2896 * i915_gem_object_unbind calls set_domain (CPU, CPU)
2897 * flush_domains and invalidate_domains end up both zero
2898 * so no flushing/invalidating happens
2902 * Case 2: The shared render buffer
2906 * 3. Read/written by GPU
2907 * 4. set_domain to (CPU,CPU)
2908 * 5. Read/written by CPU
2909 * 6. Read/written by GPU
2912 * Same as last example, (CPU, CPU)
2914 * Nothing changes (assertions find that it is not in the GPU)
2915 * 3. Read/written by GPU
2916 * execbuffer calls set_domain (RENDER, RENDER)
2917 * flush_domains gets CPU
2918 * invalidate_domains gets GPU
2920 * MI_FLUSH and drm_agp_chipset_flush
2921 * 4. set_domain (CPU, CPU)
2922 * flush_domains gets GPU
2923 * invalidate_domains gets CPU
2924 * wait_rendering (obj) to make sure all drawing is complete.
2925 * This will include an MI_FLUSH to get the data from GPU
2927 * clflush (obj) to invalidate the CPU cache
2928 * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
2929 * 5. Read/written by CPU
2930 * cache lines are loaded and dirtied
2931 * 6. Read written by GPU
2932 * Same as last GPU access
2934 * Case 3: The constant buffer
2939 * 4. Updated (written) by CPU again
2948 * flush_domains = CPU
2949 * invalidate_domains = RENDER
2952 * drm_agp_chipset_flush
2953 * 4. Updated (written) by CPU again
2955 * flush_domains = 0 (no previous write domain)
2956 * invalidate_domains = 0 (no new read domains)
2959 * flush_domains = CPU
2960 * invalidate_domains = RENDER
2963 * drm_agp_chipset_flush
2966 i915_gem_object_set_to_gpu_domain(struct drm_gem_object
*obj
)
2968 struct drm_device
*dev
= obj
->dev
;
2969 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2970 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2971 uint32_t invalidate_domains
= 0;
2972 uint32_t flush_domains
= 0;
2973 uint32_t old_read_domains
;
2975 BUG_ON(obj
->pending_read_domains
& I915_GEM_DOMAIN_CPU
);
2976 BUG_ON(obj
->pending_write_domain
== I915_GEM_DOMAIN_CPU
);
2978 intel_mark_busy(dev
, obj
);
2981 DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
2983 obj
->read_domains
, obj
->pending_read_domains
,
2984 obj
->write_domain
, obj
->pending_write_domain
);
2987 * If the object isn't moving to a new write domain,
2988 * let the object stay in multiple read domains
2990 if (obj
->pending_write_domain
== 0)
2991 obj
->pending_read_domains
|= obj
->read_domains
;
2993 obj_priv
->dirty
= 1;
2996 * Flush the current write domain if
2997 * the new read domains don't match. Invalidate
2998 * any read domains which differ from the old
3001 if (obj
->write_domain
&&
3002 obj
->write_domain
!= obj
->pending_read_domains
) {
3003 flush_domains
|= obj
->write_domain
;
3004 invalidate_domains
|=
3005 obj
->pending_read_domains
& ~obj
->write_domain
;
3008 * Invalidate any read caches which may have
3009 * stale data. That is, any new read domains.
3011 invalidate_domains
|= obj
->pending_read_domains
& ~obj
->read_domains
;
3012 if ((flush_domains
| invalidate_domains
) & I915_GEM_DOMAIN_CPU
) {
3014 DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
3015 __func__
, flush_domains
, invalidate_domains
);
3017 i915_gem_clflush_object(obj
);
3020 old_read_domains
= obj
->read_domains
;
3022 /* The actual obj->write_domain will be updated with
3023 * pending_write_domain after we emit the accumulated flush for all
3024 * of our domain changes in execbuffers (which clears objects'
3025 * write_domains). So if we have a current write domain that we
3026 * aren't changing, set pending_write_domain to that.
3028 if (flush_domains
== 0 && obj
->pending_write_domain
== 0)
3029 obj
->pending_write_domain
= obj
->write_domain
;
3030 obj
->read_domains
= obj
->pending_read_domains
;
3032 if (flush_domains
& I915_GEM_GPU_DOMAINS
) {
3033 if (obj_priv
->ring
== &dev_priv
->render_ring
)
3034 dev_priv
->flush_rings
|= FLUSH_RENDER_RING
;
3035 else if (obj_priv
->ring
== &dev_priv
->bsd_ring
)
3036 dev_priv
->flush_rings
|= FLUSH_BSD_RING
;
3039 dev
->invalidate_domains
|= invalidate_domains
;
3040 dev
->flush_domains
|= flush_domains
;
3042 DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n",
3044 obj
->read_domains
, obj
->write_domain
,
3045 dev
->invalidate_domains
, dev
->flush_domains
);
3048 trace_i915_gem_object_change_domain(obj
,
3054 * Moves the object from a partially CPU read to a full one.
3056 * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3057 * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
3060 i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object
*obj
)
3062 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
3064 if (!obj_priv
->page_cpu_valid
)
3067 /* If we're partially in the CPU read domain, finish moving it in.
3069 if (obj
->read_domains
& I915_GEM_DOMAIN_CPU
) {
3072 for (i
= 0; i
<= (obj
->size
- 1) / PAGE_SIZE
; i
++) {
3073 if (obj_priv
->page_cpu_valid
[i
])
3075 drm_clflush_pages(obj_priv
->pages
+ i
, 1);
3079 /* Free the page_cpu_valid mappings which are now stale, whether
3080 * or not we've got I915_GEM_DOMAIN_CPU.
3082 kfree(obj_priv
->page_cpu_valid
);
3083 obj_priv
->page_cpu_valid
= NULL
;
3087 * Set the CPU read domain on a range of the object.
3089 * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3090 * not entirely valid. The page_cpu_valid member of the object flags which
3091 * pages have been flushed, and will be respected by
3092 * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3093 * of the whole object.
3095 * This function returns when the move is complete, including waiting on
3099 i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object
*obj
,
3100 uint64_t offset
, uint64_t size
)
3102 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
3103 uint32_t old_read_domains
;
3106 if (offset
== 0 && size
== obj
->size
)
3107 return i915_gem_object_set_to_cpu_domain(obj
, 0);
3109 ret
= i915_gem_object_flush_gpu_write_domain(obj
);
3113 /* Wait on any GPU rendering and flushing to occur. */
3114 ret
= i915_gem_object_wait_rendering(obj
, true);
3117 i915_gem_object_flush_gtt_write_domain(obj
);
3119 /* If we're already fully in the CPU read domain, we're done. */
3120 if (obj_priv
->page_cpu_valid
== NULL
&&
3121 (obj
->read_domains
& I915_GEM_DOMAIN_CPU
) != 0)
3124 /* Otherwise, create/clear the per-page CPU read domain flag if we're
3125 * newly adding I915_GEM_DOMAIN_CPU
3127 if (obj_priv
->page_cpu_valid
== NULL
) {
3128 obj_priv
->page_cpu_valid
= kzalloc(obj
->size
/ PAGE_SIZE
,
3130 if (obj_priv
->page_cpu_valid
== NULL
)
3132 } else if ((obj
->read_domains
& I915_GEM_DOMAIN_CPU
) == 0)
3133 memset(obj_priv
->page_cpu_valid
, 0, obj
->size
/ PAGE_SIZE
);
3135 /* Flush the cache on any pages that are still invalid from the CPU's
3138 for (i
= offset
/ PAGE_SIZE
; i
<= (offset
+ size
- 1) / PAGE_SIZE
;
3140 if (obj_priv
->page_cpu_valid
[i
])
3143 drm_clflush_pages(obj_priv
->pages
+ i
, 1);
3145 obj_priv
->page_cpu_valid
[i
] = 1;
3148 /* It should now be out of any other write domains, and we can update
3149 * the domain values for our changes.
3151 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
3153 old_read_domains
= obj
->read_domains
;
3154 obj
->read_domains
|= I915_GEM_DOMAIN_CPU
;
3156 trace_i915_gem_object_change_domain(obj
,
3164 * Pin an object to the GTT and evaluate the relocations landing in it.
3167 i915_gem_object_pin_and_relocate(struct drm_gem_object
*obj
,
3168 struct drm_file
*file_priv
,
3169 struct drm_i915_gem_exec_object2
*entry
,
3170 struct drm_i915_gem_relocation_entry
*relocs
)
3172 struct drm_device
*dev
= obj
->dev
;
3173 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3174 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
3176 void __iomem
*reloc_page
;
3179 need_fence
= entry
->flags
& EXEC_OBJECT_NEEDS_FENCE
&&
3180 obj_priv
->tiling_mode
!= I915_TILING_NONE
;
3182 /* Check fence reg constraints and rebind if necessary */
3184 !i915_gem_object_fence_offset_ok(obj
,
3185 obj_priv
->tiling_mode
)) {
3186 ret
= i915_gem_object_unbind(obj
);
3191 /* Choose the GTT offset for our buffer and put it there. */
3192 ret
= i915_gem_object_pin(obj
, (uint32_t) entry
->alignment
);
3197 * Pre-965 chips need a fence register set up in order to
3198 * properly handle blits to/from tiled surfaces.
3201 ret
= i915_gem_object_get_fence_reg(obj
);
3203 i915_gem_object_unpin(obj
);
3208 entry
->offset
= obj_priv
->gtt_offset
;
3210 /* Apply the relocations, using the GTT aperture to avoid cache
3211 * flushing requirements.
3213 for (i
= 0; i
< entry
->relocation_count
; i
++) {
3214 struct drm_i915_gem_relocation_entry
*reloc
= &relocs
[i
];
3215 struct drm_gem_object
*target_obj
;
3216 struct drm_i915_gem_object
*target_obj_priv
;
3217 uint32_t reloc_val
, reloc_offset
;
3218 uint32_t __iomem
*reloc_entry
;
3220 target_obj
= drm_gem_object_lookup(obj
->dev
, file_priv
,
3221 reloc
->target_handle
);
3222 if (target_obj
== NULL
) {
3223 i915_gem_object_unpin(obj
);
3226 target_obj_priv
= to_intel_bo(target_obj
);
3229 DRM_INFO("%s: obj %p offset %08x target %d "
3230 "read %08x write %08x gtt %08x "
3231 "presumed %08x delta %08x\n",
3234 (int) reloc
->offset
,
3235 (int) reloc
->target_handle
,
3236 (int) reloc
->read_domains
,
3237 (int) reloc
->write_domain
,
3238 (int) target_obj_priv
->gtt_offset
,
3239 (int) reloc
->presumed_offset
,
3243 /* The target buffer should have appeared before us in the
3244 * exec_object list, so it should have a GTT space bound by now.
3246 if (target_obj_priv
->gtt_space
== NULL
) {
3247 DRM_ERROR("No GTT space found for object %d\n",
3248 reloc
->target_handle
);
3249 drm_gem_object_unreference(target_obj
);
3250 i915_gem_object_unpin(obj
);
3254 /* Validate that the target is in a valid r/w GPU domain */
3255 if (reloc
->write_domain
& (reloc
->write_domain
- 1)) {
3256 DRM_ERROR("reloc with multiple write domains: "
3257 "obj %p target %d offset %d "
3258 "read %08x write %08x",
3259 obj
, reloc
->target_handle
,
3260 (int) reloc
->offset
,
3261 reloc
->read_domains
,
3262 reloc
->write_domain
);
3265 if (reloc
->write_domain
& I915_GEM_DOMAIN_CPU
||
3266 reloc
->read_domains
& I915_GEM_DOMAIN_CPU
) {
3267 DRM_ERROR("reloc with read/write CPU domains: "
3268 "obj %p target %d offset %d "
3269 "read %08x write %08x",
3270 obj
, reloc
->target_handle
,
3271 (int) reloc
->offset
,
3272 reloc
->read_domains
,
3273 reloc
->write_domain
);
3274 drm_gem_object_unreference(target_obj
);
3275 i915_gem_object_unpin(obj
);
3278 if (reloc
->write_domain
&& target_obj
->pending_write_domain
&&
3279 reloc
->write_domain
!= target_obj
->pending_write_domain
) {
3280 DRM_ERROR("Write domain conflict: "
3281 "obj %p target %d offset %d "
3282 "new %08x old %08x\n",
3283 obj
, reloc
->target_handle
,
3284 (int) reloc
->offset
,
3285 reloc
->write_domain
,
3286 target_obj
->pending_write_domain
);
3287 drm_gem_object_unreference(target_obj
);
3288 i915_gem_object_unpin(obj
);
3292 target_obj
->pending_read_domains
|= reloc
->read_domains
;
3293 target_obj
->pending_write_domain
|= reloc
->write_domain
;
3295 /* If the relocation already has the right value in it, no
3296 * more work needs to be done.
3298 if (target_obj_priv
->gtt_offset
== reloc
->presumed_offset
) {
3299 drm_gem_object_unreference(target_obj
);
3303 /* Check that the relocation address is valid... */
3304 if (reloc
->offset
> obj
->size
- 4) {
3305 DRM_ERROR("Relocation beyond object bounds: "
3306 "obj %p target %d offset %d size %d.\n",
3307 obj
, reloc
->target_handle
,
3308 (int) reloc
->offset
, (int) obj
->size
);
3309 drm_gem_object_unreference(target_obj
);
3310 i915_gem_object_unpin(obj
);
3313 if (reloc
->offset
& 3) {
3314 DRM_ERROR("Relocation not 4-byte aligned: "
3315 "obj %p target %d offset %d.\n",
3316 obj
, reloc
->target_handle
,
3317 (int) reloc
->offset
);
3318 drm_gem_object_unreference(target_obj
);
3319 i915_gem_object_unpin(obj
);
3323 /* and points to somewhere within the target object. */
3324 if (reloc
->delta
>= target_obj
->size
) {
3325 DRM_ERROR("Relocation beyond target object bounds: "
3326 "obj %p target %d delta %d size %d.\n",
3327 obj
, reloc
->target_handle
,
3328 (int) reloc
->delta
, (int) target_obj
->size
);
3329 drm_gem_object_unreference(target_obj
);
3330 i915_gem_object_unpin(obj
);
3334 ret
= i915_gem_object_set_to_gtt_domain(obj
, 1);
3336 drm_gem_object_unreference(target_obj
);
3337 i915_gem_object_unpin(obj
);
3341 /* Map the page containing the relocation we're going to
3344 reloc_offset
= obj_priv
->gtt_offset
+ reloc
->offset
;
3345 reloc_page
= io_mapping_map_atomic_wc(dev_priv
->mm
.gtt_mapping
,
3349 reloc_entry
= (uint32_t __iomem
*)(reloc_page
+
3350 (reloc_offset
& (PAGE_SIZE
- 1)));
3351 reloc_val
= target_obj_priv
->gtt_offset
+ reloc
->delta
;
3354 DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n",
3355 obj
, (unsigned int) reloc
->offset
,
3356 readl(reloc_entry
), reloc_val
);
3358 writel(reloc_val
, reloc_entry
);
3359 io_mapping_unmap_atomic(reloc_page
, KM_USER0
);
3361 /* The updated presumed offset for this entry will be
3362 * copied back out to the user.
3364 reloc
->presumed_offset
= target_obj_priv
->gtt_offset
;
3366 drm_gem_object_unreference(target_obj
);
3371 i915_gem_dump_object(obj
, 128, __func__
, ~0);
3376 /* Throttle our rendering by waiting until the ring has completed our requests
3377 * emitted over 20 msec ago.
3379 * Note that if we were to use the current jiffies each time around the loop,
3380 * we wouldn't escape the function with any frames outstanding if the time to
3381 * render a frame was over 20ms.
3383 * This should get us reasonable parallelism between CPU and GPU but also
3384 * relatively low latency when blocking on a particular request to finish.
3387 i915_gem_ring_throttle(struct drm_device
*dev
, struct drm_file
*file_priv
)
3389 struct drm_i915_file_private
*i915_file_priv
= file_priv
->driver_priv
;
3391 unsigned long recent_enough
= jiffies
- msecs_to_jiffies(20);
3393 mutex_lock(&dev
->struct_mutex
);
3394 while (!list_empty(&i915_file_priv
->mm
.request_list
)) {
3395 struct drm_i915_gem_request
*request
;
3397 request
= list_first_entry(&i915_file_priv
->mm
.request_list
,
3398 struct drm_i915_gem_request
,
3401 if (time_after_eq(request
->emitted_jiffies
, recent_enough
))
3404 ret
= i915_wait_request(dev
, request
->seqno
, request
->ring
);
3408 mutex_unlock(&dev
->struct_mutex
);
3414 i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object2
*exec_list
,
3415 uint32_t buffer_count
,
3416 struct drm_i915_gem_relocation_entry
**relocs
)
3418 uint32_t reloc_count
= 0, reloc_index
= 0, i
;
3422 for (i
= 0; i
< buffer_count
; i
++) {
3423 if (reloc_count
+ exec_list
[i
].relocation_count
< reloc_count
)
3425 reloc_count
+= exec_list
[i
].relocation_count
;
3428 *relocs
= drm_calloc_large(reloc_count
, sizeof(**relocs
));
3429 if (*relocs
== NULL
) {
3430 DRM_ERROR("failed to alloc relocs, count %d\n", reloc_count
);
3434 for (i
= 0; i
< buffer_count
; i
++) {
3435 struct drm_i915_gem_relocation_entry __user
*user_relocs
;
3437 user_relocs
= (void __user
*)(uintptr_t)exec_list
[i
].relocs_ptr
;
3439 ret
= copy_from_user(&(*relocs
)[reloc_index
],
3441 exec_list
[i
].relocation_count
*
3444 drm_free_large(*relocs
);
3449 reloc_index
+= exec_list
[i
].relocation_count
;
3456 i915_gem_put_relocs_to_user(struct drm_i915_gem_exec_object2
*exec_list
,
3457 uint32_t buffer_count
,
3458 struct drm_i915_gem_relocation_entry
*relocs
)
3460 uint32_t reloc_count
= 0, i
;
3466 for (i
= 0; i
< buffer_count
; i
++) {
3467 struct drm_i915_gem_relocation_entry __user
*user_relocs
;
3470 user_relocs
= (void __user
*)(uintptr_t)exec_list
[i
].relocs_ptr
;
3472 unwritten
= copy_to_user(user_relocs
,
3473 &relocs
[reloc_count
],
3474 exec_list
[i
].relocation_count
*
3482 reloc_count
+= exec_list
[i
].relocation_count
;
3486 drm_free_large(relocs
);
3492 i915_gem_check_execbuffer (struct drm_i915_gem_execbuffer2
*exec
,
3493 uint64_t exec_offset
)
3495 uint32_t exec_start
, exec_len
;
3497 exec_start
= (uint32_t) exec_offset
+ exec
->batch_start_offset
;
3498 exec_len
= (uint32_t) exec
->batch_len
;
3500 if ((exec_start
| exec_len
) & 0x7)
3510 i915_gem_wait_for_pending_flip(struct drm_device
*dev
,
3511 struct drm_gem_object
**object_list
,
3514 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3515 struct drm_i915_gem_object
*obj_priv
;
3520 prepare_to_wait(&dev_priv
->pending_flip_queue
,
3521 &wait
, TASK_INTERRUPTIBLE
);
3522 for (i
= 0; i
< count
; i
++) {
3523 obj_priv
= to_intel_bo(object_list
[i
]);
3524 if (atomic_read(&obj_priv
->pending_flip
) > 0)
3530 if (!signal_pending(current
)) {
3531 mutex_unlock(&dev
->struct_mutex
);
3533 mutex_lock(&dev
->struct_mutex
);
3539 finish_wait(&dev_priv
->pending_flip_queue
, &wait
);
3546 i915_gem_do_execbuffer(struct drm_device
*dev
, void *data
,
3547 struct drm_file
*file_priv
,
3548 struct drm_i915_gem_execbuffer2
*args
,
3549 struct drm_i915_gem_exec_object2
*exec_list
)
3551 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3552 struct drm_gem_object
**object_list
= NULL
;
3553 struct drm_gem_object
*batch_obj
;
3554 struct drm_i915_gem_object
*obj_priv
;
3555 struct drm_clip_rect
*cliprects
= NULL
;
3556 struct drm_i915_gem_relocation_entry
*relocs
= NULL
;
3557 int ret
= 0, ret2
, i
, pinned
= 0;
3558 uint64_t exec_offset
;
3559 uint32_t seqno
, flush_domains
, reloc_index
;
3560 int pin_tries
, flips
;
3562 struct intel_ring_buffer
*ring
= NULL
;
3565 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3566 (int) args
->buffers_ptr
, args
->buffer_count
, args
->batch_len
);
3568 if (args
->flags
& I915_EXEC_BSD
) {
3569 if (!HAS_BSD(dev
)) {
3570 DRM_ERROR("execbuf with wrong flag\n");
3573 ring
= &dev_priv
->bsd_ring
;
3575 ring
= &dev_priv
->render_ring
;
3578 if (args
->buffer_count
< 1) {
3579 DRM_ERROR("execbuf with %d buffers\n", args
->buffer_count
);
3582 object_list
= drm_malloc_ab(sizeof(*object_list
), args
->buffer_count
);
3583 if (object_list
== NULL
) {
3584 DRM_ERROR("Failed to allocate object list for %d buffers\n",
3585 args
->buffer_count
);
3590 if (args
->num_cliprects
!= 0) {
3591 cliprects
= kcalloc(args
->num_cliprects
, sizeof(*cliprects
),
3593 if (cliprects
== NULL
) {
3598 ret
= copy_from_user(cliprects
,
3599 (struct drm_clip_rect __user
*)
3600 (uintptr_t) args
->cliprects_ptr
,
3601 sizeof(*cliprects
) * args
->num_cliprects
);
3603 DRM_ERROR("copy %d cliprects failed: %d\n",
3604 args
->num_cliprects
, ret
);
3610 ret
= i915_gem_get_relocs_from_user(exec_list
, args
->buffer_count
,
3615 mutex_lock(&dev
->struct_mutex
);
3617 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3619 if (atomic_read(&dev_priv
->mm
.wedged
)) {
3620 mutex_unlock(&dev
->struct_mutex
);
3625 if (dev_priv
->mm
.suspended
) {
3626 mutex_unlock(&dev
->struct_mutex
);
3631 /* Look up object handles */
3633 for (i
= 0; i
< args
->buffer_count
; i
++) {
3634 object_list
[i
] = drm_gem_object_lookup(dev
, file_priv
,
3635 exec_list
[i
].handle
);
3636 if (object_list
[i
] == NULL
) {
3637 DRM_ERROR("Invalid object handle %d at index %d\n",
3638 exec_list
[i
].handle
, i
);
3639 /* prevent error path from reading uninitialized data */
3640 args
->buffer_count
= i
+ 1;
3645 obj_priv
= to_intel_bo(object_list
[i
]);
3646 if (obj_priv
->in_execbuffer
) {
3647 DRM_ERROR("Object %p appears more than once in object list\n",
3649 /* prevent error path from reading uninitialized data */
3650 args
->buffer_count
= i
+ 1;
3654 obj_priv
->in_execbuffer
= true;
3655 flips
+= atomic_read(&obj_priv
->pending_flip
);
3659 ret
= i915_gem_wait_for_pending_flip(dev
, object_list
,
3660 args
->buffer_count
);
3665 /* Pin and relocate */
3666 for (pin_tries
= 0; ; pin_tries
++) {
3670 for (i
= 0; i
< args
->buffer_count
; i
++) {
3671 object_list
[i
]->pending_read_domains
= 0;
3672 object_list
[i
]->pending_write_domain
= 0;
3673 ret
= i915_gem_object_pin_and_relocate(object_list
[i
],
3676 &relocs
[reloc_index
]);
3680 reloc_index
+= exec_list
[i
].relocation_count
;
3686 /* error other than GTT full, or we've already tried again */
3687 if (ret
!= -ENOSPC
|| pin_tries
>= 1) {
3688 if (ret
!= -ERESTARTSYS
) {
3689 unsigned long long total_size
= 0;
3691 for (i
= 0; i
< args
->buffer_count
; i
++) {
3692 obj_priv
= to_intel_bo(object_list
[i
]);
3694 total_size
+= object_list
[i
]->size
;
3696 exec_list
[i
].flags
& EXEC_OBJECT_NEEDS_FENCE
&&
3697 obj_priv
->tiling_mode
!= I915_TILING_NONE
;
3699 DRM_ERROR("Failed to pin buffer %d of %d, total %llu bytes, %d fences: %d\n",
3700 pinned
+1, args
->buffer_count
,
3701 total_size
, num_fences
,
3703 DRM_ERROR("%d objects [%d pinned], "
3704 "%d object bytes [%d pinned], "
3705 "%d/%d gtt bytes\n",
3706 atomic_read(&dev
->object_count
),
3707 atomic_read(&dev
->pin_count
),
3708 atomic_read(&dev
->object_memory
),
3709 atomic_read(&dev
->pin_memory
),
3710 atomic_read(&dev
->gtt_memory
),
3716 /* unpin all of our buffers */
3717 for (i
= 0; i
< pinned
; i
++)
3718 i915_gem_object_unpin(object_list
[i
]);
3721 /* evict everyone we can from the aperture */
3722 ret
= i915_gem_evict_everything(dev
);
3723 if (ret
&& ret
!= -ENOSPC
)
3727 /* Set the pending read domains for the batch buffer to COMMAND */
3728 batch_obj
= object_list
[args
->buffer_count
-1];
3729 if (batch_obj
->pending_write_domain
) {
3730 DRM_ERROR("Attempting to use self-modifying batch buffer\n");
3734 batch_obj
->pending_read_domains
|= I915_GEM_DOMAIN_COMMAND
;
3736 /* Sanity check the batch buffer, prior to moving objects */
3737 exec_offset
= exec_list
[args
->buffer_count
- 1].offset
;
3738 ret
= i915_gem_check_execbuffer (args
, exec_offset
);
3740 DRM_ERROR("execbuf with invalid offset/length\n");
3744 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3746 /* Zero the global flush/invalidate flags. These
3747 * will be modified as new domains are computed
3750 dev
->invalidate_domains
= 0;
3751 dev
->flush_domains
= 0;
3752 dev_priv
->flush_rings
= 0;
3754 for (i
= 0; i
< args
->buffer_count
; i
++) {
3755 struct drm_gem_object
*obj
= object_list
[i
];
3757 /* Compute new gpu domains and update invalidate/flush */
3758 i915_gem_object_set_to_gpu_domain(obj
);
3761 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3763 if (dev
->invalidate_domains
| dev
->flush_domains
) {
3765 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
3767 dev
->invalidate_domains
,
3768 dev
->flush_domains
);
3771 dev
->invalidate_domains
,
3772 dev
->flush_domains
);
3773 if (dev_priv
->flush_rings
& FLUSH_RENDER_RING
)
3774 (void)i915_add_request(dev
, file_priv
,
3776 &dev_priv
->render_ring
);
3777 if (dev_priv
->flush_rings
& FLUSH_BSD_RING
)
3778 (void)i915_add_request(dev
, file_priv
,
3780 &dev_priv
->bsd_ring
);
3783 for (i
= 0; i
< args
->buffer_count
; i
++) {
3784 struct drm_gem_object
*obj
= object_list
[i
];
3785 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
3786 uint32_t old_write_domain
= obj
->write_domain
;
3788 obj
->write_domain
= obj
->pending_write_domain
;
3789 if (obj
->write_domain
)
3790 list_move_tail(&obj_priv
->gpu_write_list
,
3791 &dev_priv
->mm
.gpu_write_list
);
3793 list_del_init(&obj_priv
->gpu_write_list
);
3795 trace_i915_gem_object_change_domain(obj
,
3800 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3803 for (i
= 0; i
< args
->buffer_count
; i
++) {
3804 i915_gem_object_check_coherency(object_list
[i
],
3805 exec_list
[i
].handle
);
3810 i915_gem_dump_object(batch_obj
,
3816 /* Exec the batchbuffer */
3817 ret
= ring
->dispatch_gem_execbuffer(dev
, ring
, args
,
3818 cliprects
, exec_offset
);
3820 DRM_ERROR("dispatch failed %d\n", ret
);
3825 * Ensure that the commands in the batch buffer are
3826 * finished before the interrupt fires
3828 flush_domains
= i915_retire_commands(dev
, ring
);
3830 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3833 * Get a seqno representing the execution of the current buffer,
3834 * which we can wait on. We would like to mitigate these interrupts,
3835 * likely by only creating seqnos occasionally (so that we have
3836 * *some* interrupts representing completion of buffers that we can
3837 * wait on when trying to clear up gtt space).
3839 seqno
= i915_add_request(dev
, file_priv
, flush_domains
, ring
);
3841 for (i
= 0; i
< args
->buffer_count
; i
++) {
3842 struct drm_gem_object
*obj
= object_list
[i
];
3843 obj_priv
= to_intel_bo(obj
);
3845 i915_gem_object_move_to_active(obj
, seqno
, ring
);
3847 DRM_INFO("%s: move to exec list %p\n", __func__
, obj
);
3851 i915_dump_lru(dev
, __func__
);
3854 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3857 for (i
= 0; i
< pinned
; i
++)
3858 i915_gem_object_unpin(object_list
[i
]);
3860 for (i
= 0; i
< args
->buffer_count
; i
++) {
3861 if (object_list
[i
]) {
3862 obj_priv
= to_intel_bo(object_list
[i
]);
3863 obj_priv
->in_execbuffer
= false;
3865 drm_gem_object_unreference(object_list
[i
]);
3868 mutex_unlock(&dev
->struct_mutex
);
3871 /* Copy the updated relocations out regardless of current error
3872 * state. Failure to update the relocs would mean that the next
3873 * time userland calls execbuf, it would do so with presumed offset
3874 * state that didn't match the actual object state.
3876 ret2
= i915_gem_put_relocs_to_user(exec_list
, args
->buffer_count
,
3879 DRM_ERROR("Failed to copy relocations back out: %d\n", ret2
);
3885 drm_free_large(object_list
);
3892 * Legacy execbuffer just creates an exec2 list from the original exec object
3893 * list array and passes it to the real function.
3896 i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
3897 struct drm_file
*file_priv
)
3899 struct drm_i915_gem_execbuffer
*args
= data
;
3900 struct drm_i915_gem_execbuffer2 exec2
;
3901 struct drm_i915_gem_exec_object
*exec_list
= NULL
;
3902 struct drm_i915_gem_exec_object2
*exec2_list
= NULL
;
3906 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3907 (int) args
->buffers_ptr
, args
->buffer_count
, args
->batch_len
);
3910 if (args
->buffer_count
< 1) {
3911 DRM_ERROR("execbuf with %d buffers\n", args
->buffer_count
);
3915 /* Copy in the exec list from userland */
3916 exec_list
= drm_malloc_ab(sizeof(*exec_list
), args
->buffer_count
);
3917 exec2_list
= drm_malloc_ab(sizeof(*exec2_list
), args
->buffer_count
);
3918 if (exec_list
== NULL
|| exec2_list
== NULL
) {
3919 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
3920 args
->buffer_count
);
3921 drm_free_large(exec_list
);
3922 drm_free_large(exec2_list
);
3925 ret
= copy_from_user(exec_list
,
3926 (struct drm_i915_relocation_entry __user
*)
3927 (uintptr_t) args
->buffers_ptr
,
3928 sizeof(*exec_list
) * args
->buffer_count
);
3930 DRM_ERROR("copy %d exec entries failed %d\n",
3931 args
->buffer_count
, ret
);
3932 drm_free_large(exec_list
);
3933 drm_free_large(exec2_list
);
3937 for (i
= 0; i
< args
->buffer_count
; i
++) {
3938 exec2_list
[i
].handle
= exec_list
[i
].handle
;
3939 exec2_list
[i
].relocation_count
= exec_list
[i
].relocation_count
;
3940 exec2_list
[i
].relocs_ptr
= exec_list
[i
].relocs_ptr
;
3941 exec2_list
[i
].alignment
= exec_list
[i
].alignment
;
3942 exec2_list
[i
].offset
= exec_list
[i
].offset
;
3944 exec2_list
[i
].flags
= EXEC_OBJECT_NEEDS_FENCE
;
3946 exec2_list
[i
].flags
= 0;
3949 exec2
.buffers_ptr
= args
->buffers_ptr
;
3950 exec2
.buffer_count
= args
->buffer_count
;
3951 exec2
.batch_start_offset
= args
->batch_start_offset
;
3952 exec2
.batch_len
= args
->batch_len
;
3953 exec2
.DR1
= args
->DR1
;
3954 exec2
.DR4
= args
->DR4
;
3955 exec2
.num_cliprects
= args
->num_cliprects
;
3956 exec2
.cliprects_ptr
= args
->cliprects_ptr
;
3957 exec2
.flags
= I915_EXEC_RENDER
;
3959 ret
= i915_gem_do_execbuffer(dev
, data
, file_priv
, &exec2
, exec2_list
);
3961 /* Copy the new buffer offsets back to the user's exec list. */
3962 for (i
= 0; i
< args
->buffer_count
; i
++)
3963 exec_list
[i
].offset
= exec2_list
[i
].offset
;
3964 /* ... and back out to userspace */
3965 ret
= copy_to_user((struct drm_i915_relocation_entry __user
*)
3966 (uintptr_t) args
->buffers_ptr
,
3968 sizeof(*exec_list
) * args
->buffer_count
);
3971 DRM_ERROR("failed to copy %d exec entries "
3972 "back to user (%d)\n",
3973 args
->buffer_count
, ret
);
3977 drm_free_large(exec_list
);
3978 drm_free_large(exec2_list
);
3983 i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
3984 struct drm_file
*file_priv
)
3986 struct drm_i915_gem_execbuffer2
*args
= data
;
3987 struct drm_i915_gem_exec_object2
*exec2_list
= NULL
;
3991 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3992 (int) args
->buffers_ptr
, args
->buffer_count
, args
->batch_len
);
3995 if (args
->buffer_count
< 1) {
3996 DRM_ERROR("execbuf2 with %d buffers\n", args
->buffer_count
);
4000 exec2_list
= drm_malloc_ab(sizeof(*exec2_list
), args
->buffer_count
);
4001 if (exec2_list
== NULL
) {
4002 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
4003 args
->buffer_count
);
4006 ret
= copy_from_user(exec2_list
,
4007 (struct drm_i915_relocation_entry __user
*)
4008 (uintptr_t) args
->buffers_ptr
,
4009 sizeof(*exec2_list
) * args
->buffer_count
);
4011 DRM_ERROR("copy %d exec entries failed %d\n",
4012 args
->buffer_count
, ret
);
4013 drm_free_large(exec2_list
);
4017 ret
= i915_gem_do_execbuffer(dev
, data
, file_priv
, args
, exec2_list
);
4019 /* Copy the new buffer offsets back to the user's exec list. */
4020 ret
= copy_to_user((struct drm_i915_relocation_entry __user
*)
4021 (uintptr_t) args
->buffers_ptr
,
4023 sizeof(*exec2_list
) * args
->buffer_count
);
4026 DRM_ERROR("failed to copy %d exec entries "
4027 "back to user (%d)\n",
4028 args
->buffer_count
, ret
);
4032 drm_free_large(exec2_list
);
4037 i915_gem_object_pin(struct drm_gem_object
*obj
, uint32_t alignment
)
4039 struct drm_device
*dev
= obj
->dev
;
4040 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
4043 BUG_ON(obj_priv
->pin_count
== DRM_I915_GEM_OBJECT_MAX_PIN_COUNT
);
4045 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
4047 if (obj_priv
->gtt_space
!= NULL
) {
4049 alignment
= i915_gem_get_gtt_alignment(obj
);
4050 if (obj_priv
->gtt_offset
& (alignment
- 1)) {
4051 WARN(obj_priv
->pin_count
,
4052 "bo is already pinned with incorrect alignment:"
4053 " offset=%x, req.alignment=%x\n",
4054 obj_priv
->gtt_offset
, alignment
);
4055 ret
= i915_gem_object_unbind(obj
);
4061 if (obj_priv
->gtt_space
== NULL
) {
4062 ret
= i915_gem_object_bind_to_gtt(obj
, alignment
);
4067 obj_priv
->pin_count
++;
4069 /* If the object is not active and not pending a flush,
4070 * remove it from the inactive list
4072 if (obj_priv
->pin_count
== 1) {
4073 atomic_inc(&dev
->pin_count
);
4074 atomic_add(obj
->size
, &dev
->pin_memory
);
4075 if (!obj_priv
->active
&&
4076 (obj
->write_domain
& I915_GEM_GPU_DOMAINS
) == 0)
4077 list_del_init(&obj_priv
->list
);
4079 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
4085 i915_gem_object_unpin(struct drm_gem_object
*obj
)
4087 struct drm_device
*dev
= obj
->dev
;
4088 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4089 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
4091 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
4092 obj_priv
->pin_count
--;
4093 BUG_ON(obj_priv
->pin_count
< 0);
4094 BUG_ON(obj_priv
->gtt_space
== NULL
);
4096 /* If the object is no longer pinned, and is
4097 * neither active nor being flushed, then stick it on
4100 if (obj_priv
->pin_count
== 0) {
4101 if (!obj_priv
->active
&&
4102 (obj
->write_domain
& I915_GEM_GPU_DOMAINS
) == 0)
4103 list_move_tail(&obj_priv
->list
,
4104 &dev_priv
->mm
.inactive_list
);
4105 atomic_dec(&dev
->pin_count
);
4106 atomic_sub(obj
->size
, &dev
->pin_memory
);
4108 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
4112 i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
4113 struct drm_file
*file_priv
)
4115 struct drm_i915_gem_pin
*args
= data
;
4116 struct drm_gem_object
*obj
;
4117 struct drm_i915_gem_object
*obj_priv
;
4120 mutex_lock(&dev
->struct_mutex
);
4122 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4124 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
4126 mutex_unlock(&dev
->struct_mutex
);
4129 obj_priv
= to_intel_bo(obj
);
4131 if (obj_priv
->madv
!= I915_MADV_WILLNEED
) {
4132 DRM_ERROR("Attempting to pin a purgeable buffer\n");
4133 drm_gem_object_unreference(obj
);
4134 mutex_unlock(&dev
->struct_mutex
);
4138 if (obj_priv
->pin_filp
!= NULL
&& obj_priv
->pin_filp
!= file_priv
) {
4139 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
4141 drm_gem_object_unreference(obj
);
4142 mutex_unlock(&dev
->struct_mutex
);
4146 obj_priv
->user_pin_count
++;
4147 obj_priv
->pin_filp
= file_priv
;
4148 if (obj_priv
->user_pin_count
== 1) {
4149 ret
= i915_gem_object_pin(obj
, args
->alignment
);
4151 drm_gem_object_unreference(obj
);
4152 mutex_unlock(&dev
->struct_mutex
);
4157 /* XXX - flush the CPU caches for pinned objects
4158 * as the X server doesn't manage domains yet
4160 i915_gem_object_flush_cpu_write_domain(obj
);
4161 args
->offset
= obj_priv
->gtt_offset
;
4162 drm_gem_object_unreference(obj
);
4163 mutex_unlock(&dev
->struct_mutex
);
4169 i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
4170 struct drm_file
*file_priv
)
4172 struct drm_i915_gem_pin
*args
= data
;
4173 struct drm_gem_object
*obj
;
4174 struct drm_i915_gem_object
*obj_priv
;
4176 mutex_lock(&dev
->struct_mutex
);
4178 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4180 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
4182 mutex_unlock(&dev
->struct_mutex
);
4186 obj_priv
= to_intel_bo(obj
);
4187 if (obj_priv
->pin_filp
!= file_priv
) {
4188 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4190 drm_gem_object_unreference(obj
);
4191 mutex_unlock(&dev
->struct_mutex
);
4194 obj_priv
->user_pin_count
--;
4195 if (obj_priv
->user_pin_count
== 0) {
4196 obj_priv
->pin_filp
= NULL
;
4197 i915_gem_object_unpin(obj
);
4200 drm_gem_object_unreference(obj
);
4201 mutex_unlock(&dev
->struct_mutex
);
4206 i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
4207 struct drm_file
*file_priv
)
4209 struct drm_i915_gem_busy
*args
= data
;
4210 struct drm_gem_object
*obj
;
4211 struct drm_i915_gem_object
*obj_priv
;
4213 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4215 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
4220 mutex_lock(&dev
->struct_mutex
);
4222 /* Count all active objects as busy, even if they are currently not used
4223 * by the gpu. Users of this interface expect objects to eventually
4224 * become non-busy without any further actions, therefore emit any
4225 * necessary flushes here.
4227 obj_priv
= to_intel_bo(obj
);
4228 args
->busy
= obj_priv
->active
;
4230 /* Unconditionally flush objects, even when the gpu still uses this
4231 * object. Userspace calling this function indicates that it wants to
4232 * use this buffer rather sooner than later, so issuing the required
4233 * flush earlier is beneficial.
4235 if (obj
->write_domain
) {
4236 i915_gem_flush(dev
, 0, obj
->write_domain
);
4237 (void)i915_add_request(dev
, file_priv
, obj
->write_domain
, obj_priv
->ring
);
4240 /* Update the active list for the hardware's current position.
4241 * Otherwise this only updates on a delayed timer or when irqs
4242 * are actually unmasked, and our working set ends up being
4243 * larger than required.
4245 i915_gem_retire_requests_ring(dev
, obj_priv
->ring
);
4247 args
->busy
= obj_priv
->active
;
4250 drm_gem_object_unreference(obj
);
4251 mutex_unlock(&dev
->struct_mutex
);
4256 i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
4257 struct drm_file
*file_priv
)
4259 return i915_gem_ring_throttle(dev
, file_priv
);
4263 i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
4264 struct drm_file
*file_priv
)
4266 struct drm_i915_gem_madvise
*args
= data
;
4267 struct drm_gem_object
*obj
;
4268 struct drm_i915_gem_object
*obj_priv
;
4270 switch (args
->madv
) {
4271 case I915_MADV_DONTNEED
:
4272 case I915_MADV_WILLNEED
:
4278 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4280 DRM_ERROR("Bad handle in i915_gem_madvise_ioctl(): %d\n",
4285 mutex_lock(&dev
->struct_mutex
);
4286 obj_priv
= to_intel_bo(obj
);
4288 if (obj_priv
->pin_count
) {
4289 drm_gem_object_unreference(obj
);
4290 mutex_unlock(&dev
->struct_mutex
);
4292 DRM_ERROR("Attempted i915_gem_madvise_ioctl() on a pinned object\n");
4296 if (obj_priv
->madv
!= __I915_MADV_PURGED
)
4297 obj_priv
->madv
= args
->madv
;
4299 /* if the object is no longer bound, discard its backing storage */
4300 if (i915_gem_object_is_purgeable(obj_priv
) &&
4301 obj_priv
->gtt_space
== NULL
)
4302 i915_gem_object_truncate(obj
);
4304 args
->retained
= obj_priv
->madv
!= __I915_MADV_PURGED
;
4306 drm_gem_object_unreference(obj
);
4307 mutex_unlock(&dev
->struct_mutex
);
4312 struct drm_gem_object
* i915_gem_alloc_object(struct drm_device
*dev
,
4315 struct drm_i915_gem_object
*obj
;
4317 obj
= kzalloc(sizeof(*obj
), GFP_KERNEL
);
4321 if (drm_gem_object_init(dev
, &obj
->base
, size
) != 0) {
4326 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
4327 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
4329 obj
->agp_type
= AGP_USER_MEMORY
;
4330 obj
->base
.driver_private
= NULL
;
4331 obj
->fence_reg
= I915_FENCE_REG_NONE
;
4332 INIT_LIST_HEAD(&obj
->list
);
4333 INIT_LIST_HEAD(&obj
->gpu_write_list
);
4334 obj
->madv
= I915_MADV_WILLNEED
;
4336 trace_i915_gem_object_create(&obj
->base
);
4341 int i915_gem_init_object(struct drm_gem_object
*obj
)
4348 static void i915_gem_free_object_tail(struct drm_gem_object
*obj
)
4350 struct drm_device
*dev
= obj
->dev
;
4351 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4352 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
4355 ret
= i915_gem_object_unbind(obj
);
4356 if (ret
== -ERESTARTSYS
) {
4357 list_move(&obj_priv
->list
,
4358 &dev_priv
->mm
.deferred_free_list
);
4362 if (obj_priv
->mmap_offset
)
4363 i915_gem_free_mmap_offset(obj
);
4365 drm_gem_object_release(obj
);
4367 kfree(obj_priv
->page_cpu_valid
);
4368 kfree(obj_priv
->bit_17
);
4372 void i915_gem_free_object(struct drm_gem_object
*obj
)
4374 struct drm_device
*dev
= obj
->dev
;
4375 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
4377 trace_i915_gem_object_destroy(obj
);
4379 while (obj_priv
->pin_count
> 0)
4380 i915_gem_object_unpin(obj
);
4382 if (obj_priv
->phys_obj
)
4383 i915_gem_detach_phys_object(dev
, obj
);
4385 i915_gem_free_object_tail(obj
);
4389 i915_gem_idle(struct drm_device
*dev
)
4391 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4394 mutex_lock(&dev
->struct_mutex
);
4396 if (dev_priv
->mm
.suspended
||
4397 (dev_priv
->render_ring
.gem_object
== NULL
) ||
4399 dev_priv
->bsd_ring
.gem_object
== NULL
)) {
4400 mutex_unlock(&dev
->struct_mutex
);
4404 ret
= i915_gpu_idle(dev
);
4406 mutex_unlock(&dev
->struct_mutex
);
4410 /* Under UMS, be paranoid and evict. */
4411 if (!drm_core_check_feature(dev
, DRIVER_MODESET
)) {
4412 ret
= i915_gem_evict_inactive(dev
);
4414 mutex_unlock(&dev
->struct_mutex
);
4419 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4420 * We need to replace this with a semaphore, or something.
4421 * And not confound mm.suspended!
4423 dev_priv
->mm
.suspended
= 1;
4424 del_timer_sync(&dev_priv
->hangcheck_timer
);
4426 i915_kernel_lost_context(dev
);
4427 i915_gem_cleanup_ringbuffer(dev
);
4429 mutex_unlock(&dev
->struct_mutex
);
4431 /* Cancel the retire work handler, which should be idle now. */
4432 cancel_delayed_work_sync(&dev_priv
->mm
.retire_work
);
4438 * 965+ support PIPE_CONTROL commands, which provide finer grained control
4439 * over cache flushing.
4442 i915_gem_init_pipe_control(struct drm_device
*dev
)
4444 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4445 struct drm_gem_object
*obj
;
4446 struct drm_i915_gem_object
*obj_priv
;
4449 obj
= i915_gem_alloc_object(dev
, 4096);
4451 DRM_ERROR("Failed to allocate seqno page\n");
4455 obj_priv
= to_intel_bo(obj
);
4456 obj_priv
->agp_type
= AGP_USER_CACHED_MEMORY
;
4458 ret
= i915_gem_object_pin(obj
, 4096);
4462 dev_priv
->seqno_gfx_addr
= obj_priv
->gtt_offset
;
4463 dev_priv
->seqno_page
= kmap(obj_priv
->pages
[0]);
4464 if (dev_priv
->seqno_page
== NULL
)
4467 dev_priv
->seqno_obj
= obj
;
4468 memset(dev_priv
->seqno_page
, 0, PAGE_SIZE
);
4473 i915_gem_object_unpin(obj
);
4475 drm_gem_object_unreference(obj
);
4482 i915_gem_cleanup_pipe_control(struct drm_device
*dev
)
4484 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4485 struct drm_gem_object
*obj
;
4486 struct drm_i915_gem_object
*obj_priv
;
4488 obj
= dev_priv
->seqno_obj
;
4489 obj_priv
= to_intel_bo(obj
);
4490 kunmap(obj_priv
->pages
[0]);
4491 i915_gem_object_unpin(obj
);
4492 drm_gem_object_unreference(obj
);
4493 dev_priv
->seqno_obj
= NULL
;
4495 dev_priv
->seqno_page
= NULL
;
4499 i915_gem_init_ringbuffer(struct drm_device
*dev
)
4501 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4504 dev_priv
->render_ring
= render_ring
;
4506 if (!I915_NEED_GFX_HWS(dev
)) {
4507 dev_priv
->render_ring
.status_page
.page_addr
4508 = dev_priv
->status_page_dmah
->vaddr
;
4509 memset(dev_priv
->render_ring
.status_page
.page_addr
,
4513 if (HAS_PIPE_CONTROL(dev
)) {
4514 ret
= i915_gem_init_pipe_control(dev
);
4519 ret
= intel_init_ring_buffer(dev
, &dev_priv
->render_ring
);
4521 goto cleanup_pipe_control
;
4524 dev_priv
->bsd_ring
= bsd_ring
;
4525 ret
= intel_init_ring_buffer(dev
, &dev_priv
->bsd_ring
);
4527 goto cleanup_render_ring
;
4530 dev_priv
->next_seqno
= 1;
4534 cleanup_render_ring
:
4535 intel_cleanup_ring_buffer(dev
, &dev_priv
->render_ring
);
4536 cleanup_pipe_control
:
4537 if (HAS_PIPE_CONTROL(dev
))
4538 i915_gem_cleanup_pipe_control(dev
);
4543 i915_gem_cleanup_ringbuffer(struct drm_device
*dev
)
4545 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4547 intel_cleanup_ring_buffer(dev
, &dev_priv
->render_ring
);
4549 intel_cleanup_ring_buffer(dev
, &dev_priv
->bsd_ring
);
4550 if (HAS_PIPE_CONTROL(dev
))
4551 i915_gem_cleanup_pipe_control(dev
);
4555 i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
4556 struct drm_file
*file_priv
)
4558 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4561 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4564 if (atomic_read(&dev_priv
->mm
.wedged
)) {
4565 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4566 atomic_set(&dev_priv
->mm
.wedged
, 0);
4569 mutex_lock(&dev
->struct_mutex
);
4570 dev_priv
->mm
.suspended
= 0;
4572 ret
= i915_gem_init_ringbuffer(dev
);
4574 mutex_unlock(&dev
->struct_mutex
);
4578 spin_lock(&dev_priv
->mm
.active_list_lock
);
4579 BUG_ON(!list_empty(&dev_priv
->render_ring
.active_list
));
4580 BUG_ON(HAS_BSD(dev
) && !list_empty(&dev_priv
->bsd_ring
.active_list
));
4581 spin_unlock(&dev_priv
->mm
.active_list_lock
);
4583 BUG_ON(!list_empty(&dev_priv
->mm
.flushing_list
));
4584 BUG_ON(!list_empty(&dev_priv
->mm
.inactive_list
));
4585 BUG_ON(!list_empty(&dev_priv
->render_ring
.request_list
));
4586 BUG_ON(HAS_BSD(dev
) && !list_empty(&dev_priv
->bsd_ring
.request_list
));
4587 mutex_unlock(&dev
->struct_mutex
);
4589 ret
= drm_irq_install(dev
);
4591 goto cleanup_ringbuffer
;
4596 mutex_lock(&dev
->struct_mutex
);
4597 i915_gem_cleanup_ringbuffer(dev
);
4598 dev_priv
->mm
.suspended
= 1;
4599 mutex_unlock(&dev
->struct_mutex
);
4605 i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
4606 struct drm_file
*file_priv
)
4608 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4611 drm_irq_uninstall(dev
);
4612 return i915_gem_idle(dev
);
4616 i915_gem_lastclose(struct drm_device
*dev
)
4620 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4623 ret
= i915_gem_idle(dev
);
4625 DRM_ERROR("failed to idle hardware: %d\n", ret
);
4629 i915_gem_load(struct drm_device
*dev
)
4632 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4634 spin_lock_init(&dev_priv
->mm
.active_list_lock
);
4635 INIT_LIST_HEAD(&dev_priv
->mm
.flushing_list
);
4636 INIT_LIST_HEAD(&dev_priv
->mm
.gpu_write_list
);
4637 INIT_LIST_HEAD(&dev_priv
->mm
.inactive_list
);
4638 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
4639 INIT_LIST_HEAD(&dev_priv
->mm
.deferred_free_list
);
4640 INIT_LIST_HEAD(&dev_priv
->render_ring
.active_list
);
4641 INIT_LIST_HEAD(&dev_priv
->render_ring
.request_list
);
4643 INIT_LIST_HEAD(&dev_priv
->bsd_ring
.active_list
);
4644 INIT_LIST_HEAD(&dev_priv
->bsd_ring
.request_list
);
4646 for (i
= 0; i
< 16; i
++)
4647 INIT_LIST_HEAD(&dev_priv
->fence_regs
[i
].lru_list
);
4648 INIT_DELAYED_WORK(&dev_priv
->mm
.retire_work
,
4649 i915_gem_retire_work_handler
);
4650 spin_lock(&shrink_list_lock
);
4651 list_add(&dev_priv
->mm
.shrink_list
, &shrink_list
);
4652 spin_unlock(&shrink_list_lock
);
4654 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4656 u32 tmp
= I915_READ(MI_ARB_STATE
);
4657 if (!(tmp
& MI_ARB_C3_LP_WRITE_ENABLE
)) {
4658 /* arb state is a masked write, so set bit + bit in mask */
4659 tmp
= MI_ARB_C3_LP_WRITE_ENABLE
| (MI_ARB_C3_LP_WRITE_ENABLE
<< MI_ARB_MASK_SHIFT
);
4660 I915_WRITE(MI_ARB_STATE
, tmp
);
4664 /* Old X drivers will take 0-2 for front, back, depth buffers */
4665 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
4666 dev_priv
->fence_reg_start
= 3;
4668 if (IS_I965G(dev
) || IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
4669 dev_priv
->num_fence_regs
= 16;
4671 dev_priv
->num_fence_regs
= 8;
4673 /* Initialize fence registers to zero */
4674 if (IS_I965G(dev
)) {
4675 for (i
= 0; i
< 16; i
++)
4676 I915_WRITE64(FENCE_REG_965_0
+ (i
* 8), 0);
4678 for (i
= 0; i
< 8; i
++)
4679 I915_WRITE(FENCE_REG_830_0
+ (i
* 4), 0);
4680 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
4681 for (i
= 0; i
< 8; i
++)
4682 I915_WRITE(FENCE_REG_945_8
+ (i
* 4), 0);
4684 i915_gem_detect_bit_6_swizzle(dev
);
4685 init_waitqueue_head(&dev_priv
->pending_flip_queue
);
4689 * Create a physically contiguous memory object for this object
4690 * e.g. for cursor + overlay regs
4692 int i915_gem_init_phys_object(struct drm_device
*dev
,
4693 int id
, int size
, int align
)
4695 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4696 struct drm_i915_gem_phys_object
*phys_obj
;
4699 if (dev_priv
->mm
.phys_objs
[id
- 1] || !size
)
4702 phys_obj
= kzalloc(sizeof(struct drm_i915_gem_phys_object
), GFP_KERNEL
);
4708 phys_obj
->handle
= drm_pci_alloc(dev
, size
, align
);
4709 if (!phys_obj
->handle
) {
4714 set_memory_wc((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
4717 dev_priv
->mm
.phys_objs
[id
- 1] = phys_obj
;
4725 void i915_gem_free_phys_object(struct drm_device
*dev
, int id
)
4727 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4728 struct drm_i915_gem_phys_object
*phys_obj
;
4730 if (!dev_priv
->mm
.phys_objs
[id
- 1])
4733 phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
4734 if (phys_obj
->cur_obj
) {
4735 i915_gem_detach_phys_object(dev
, phys_obj
->cur_obj
);
4739 set_memory_wb((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
4741 drm_pci_free(dev
, phys_obj
->handle
);
4743 dev_priv
->mm
.phys_objs
[id
- 1] = NULL
;
4746 void i915_gem_free_all_phys_object(struct drm_device
*dev
)
4750 for (i
= I915_GEM_PHYS_CURSOR_0
; i
<= I915_MAX_PHYS_OBJECT
; i
++)
4751 i915_gem_free_phys_object(dev
, i
);
4754 void i915_gem_detach_phys_object(struct drm_device
*dev
,
4755 struct drm_gem_object
*obj
)
4757 struct drm_i915_gem_object
*obj_priv
;
4762 obj_priv
= to_intel_bo(obj
);
4763 if (!obj_priv
->phys_obj
)
4766 ret
= i915_gem_object_get_pages(obj
, 0);
4770 page_count
= obj
->size
/ PAGE_SIZE
;
4772 for (i
= 0; i
< page_count
; i
++) {
4773 char *dst
= kmap_atomic(obj_priv
->pages
[i
], KM_USER0
);
4774 char *src
= obj_priv
->phys_obj
->handle
->vaddr
+ (i
* PAGE_SIZE
);
4776 memcpy(dst
, src
, PAGE_SIZE
);
4777 kunmap_atomic(dst
, KM_USER0
);
4779 drm_clflush_pages(obj_priv
->pages
, page_count
);
4780 drm_agp_chipset_flush(dev
);
4782 i915_gem_object_put_pages(obj
);
4784 obj_priv
->phys_obj
->cur_obj
= NULL
;
4785 obj_priv
->phys_obj
= NULL
;
4789 i915_gem_attach_phys_object(struct drm_device
*dev
,
4790 struct drm_gem_object
*obj
,
4794 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4795 struct drm_i915_gem_object
*obj_priv
;
4800 if (id
> I915_MAX_PHYS_OBJECT
)
4803 obj_priv
= to_intel_bo(obj
);
4805 if (obj_priv
->phys_obj
) {
4806 if (obj_priv
->phys_obj
->id
== id
)
4808 i915_gem_detach_phys_object(dev
, obj
);
4811 /* create a new object */
4812 if (!dev_priv
->mm
.phys_objs
[id
- 1]) {
4813 ret
= i915_gem_init_phys_object(dev
, id
,
4816 DRM_ERROR("failed to init phys object %d size: %zu\n", id
, obj
->size
);
4821 /* bind to the object */
4822 obj_priv
->phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
4823 obj_priv
->phys_obj
->cur_obj
= obj
;
4825 ret
= i915_gem_object_get_pages(obj
, 0);
4827 DRM_ERROR("failed to get page list\n");
4831 page_count
= obj
->size
/ PAGE_SIZE
;
4833 for (i
= 0; i
< page_count
; i
++) {
4834 char *src
= kmap_atomic(obj_priv
->pages
[i
], KM_USER0
);
4835 char *dst
= obj_priv
->phys_obj
->handle
->vaddr
+ (i
* PAGE_SIZE
);
4837 memcpy(dst
, src
, PAGE_SIZE
);
4838 kunmap_atomic(src
, KM_USER0
);
4841 i915_gem_object_put_pages(obj
);
4849 i915_gem_phys_pwrite(struct drm_device
*dev
, struct drm_gem_object
*obj
,
4850 struct drm_i915_gem_pwrite
*args
,
4851 struct drm_file
*file_priv
)
4853 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
4856 char __user
*user_data
;
4858 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
4859 obj_addr
= obj_priv
->phys_obj
->handle
->vaddr
+ args
->offset
;
4861 DRM_DEBUG_DRIVER("obj_addr %p, %lld\n", obj_addr
, args
->size
);
4862 ret
= copy_from_user(obj_addr
, user_data
, args
->size
);
4866 drm_agp_chipset_flush(dev
);
4870 void i915_gem_release(struct drm_device
* dev
, struct drm_file
*file_priv
)
4872 struct drm_i915_file_private
*i915_file_priv
= file_priv
->driver_priv
;
4874 /* Clean up our request list when the client is going away, so that
4875 * later retire_requests won't dereference our soon-to-be-gone
4878 mutex_lock(&dev
->struct_mutex
);
4879 while (!list_empty(&i915_file_priv
->mm
.request_list
))
4880 list_del_init(i915_file_priv
->mm
.request_list
.next
);
4881 mutex_unlock(&dev
->struct_mutex
);
4885 i915_gpu_is_active(struct drm_device
*dev
)
4887 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4890 spin_lock(&dev_priv
->mm
.active_list_lock
);
4891 lists_empty
= list_empty(&dev_priv
->mm
.flushing_list
) &&
4892 list_empty(&dev_priv
->render_ring
.active_list
);
4894 lists_empty
&= list_empty(&dev_priv
->bsd_ring
.active_list
);
4895 spin_unlock(&dev_priv
->mm
.active_list_lock
);
4897 return !lists_empty
;
4901 i915_gem_shrink(struct shrinker
*shrink
, int nr_to_scan
, gfp_t gfp_mask
)
4903 drm_i915_private_t
*dev_priv
, *next_dev
;
4904 struct drm_i915_gem_object
*obj_priv
, *next_obj
;
4906 int would_deadlock
= 1;
4908 /* "fast-path" to count number of available objects */
4909 if (nr_to_scan
== 0) {
4910 spin_lock(&shrink_list_lock
);
4911 list_for_each_entry(dev_priv
, &shrink_list
, mm
.shrink_list
) {
4912 struct drm_device
*dev
= dev_priv
->dev
;
4914 if (mutex_trylock(&dev
->struct_mutex
)) {
4915 list_for_each_entry(obj_priv
,
4916 &dev_priv
->mm
.inactive_list
,
4919 mutex_unlock(&dev
->struct_mutex
);
4922 spin_unlock(&shrink_list_lock
);
4924 return (cnt
/ 100) * sysctl_vfs_cache_pressure
;
4927 spin_lock(&shrink_list_lock
);
4930 /* first scan for clean buffers */
4931 list_for_each_entry_safe(dev_priv
, next_dev
,
4932 &shrink_list
, mm
.shrink_list
) {
4933 struct drm_device
*dev
= dev_priv
->dev
;
4935 if (! mutex_trylock(&dev
->struct_mutex
))
4938 spin_unlock(&shrink_list_lock
);
4939 i915_gem_retire_requests(dev
);
4941 list_for_each_entry_safe(obj_priv
, next_obj
,
4942 &dev_priv
->mm
.inactive_list
,
4944 if (i915_gem_object_is_purgeable(obj_priv
)) {
4945 i915_gem_object_unbind(&obj_priv
->base
);
4946 if (--nr_to_scan
<= 0)
4951 spin_lock(&shrink_list_lock
);
4952 mutex_unlock(&dev
->struct_mutex
);
4956 if (nr_to_scan
<= 0)
4960 /* second pass, evict/count anything still on the inactive list */
4961 list_for_each_entry_safe(dev_priv
, next_dev
,
4962 &shrink_list
, mm
.shrink_list
) {
4963 struct drm_device
*dev
= dev_priv
->dev
;
4965 if (! mutex_trylock(&dev
->struct_mutex
))
4968 spin_unlock(&shrink_list_lock
);
4970 list_for_each_entry_safe(obj_priv
, next_obj
,
4971 &dev_priv
->mm
.inactive_list
,
4973 if (nr_to_scan
> 0) {
4974 i915_gem_object_unbind(&obj_priv
->base
);
4980 spin_lock(&shrink_list_lock
);
4981 mutex_unlock(&dev
->struct_mutex
);
4990 * We are desperate for pages, so as a last resort, wait
4991 * for the GPU to finish and discard whatever we can.
4992 * This has a dramatic impact to reduce the number of
4993 * OOM-killer events whilst running the GPU aggressively.
4995 list_for_each_entry(dev_priv
, &shrink_list
, mm
.shrink_list
) {
4996 struct drm_device
*dev
= dev_priv
->dev
;
4998 if (!mutex_trylock(&dev
->struct_mutex
))
5001 spin_unlock(&shrink_list_lock
);
5003 if (i915_gpu_is_active(dev
)) {
5008 spin_lock(&shrink_list_lock
);
5009 mutex_unlock(&dev
->struct_mutex
);
5016 spin_unlock(&shrink_list_lock
);
5021 return (cnt
/ 100) * sysctl_vfs_cache_pressure
;
5026 static struct shrinker shrinker
= {
5027 .shrink
= i915_gem_shrink
,
5028 .seeks
= DEFAULT_SEEKS
,
5032 i915_gem_shrinker_init(void)
5034 register_shrinker(&shrinker
);
5038 i915_gem_shrinker_exit(void)
5040 unregister_shrinker(&shrinker
);