2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/slab.h>
35 #include <linux/swap.h>
36 #include <linux/pci.h>
37 #include <linux/intel-gtt.h>
39 static uint32_t i915_gem_get_gtt_alignment(struct drm_gem_object
*obj
);
41 static int i915_gem_object_flush_gpu_write_domain(struct drm_gem_object
*obj
,
43 static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object
*obj
);
44 static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object
*obj
);
45 static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object
*obj
,
47 static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object
*obj
,
50 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object
*obj
);
51 static int i915_gem_object_wait_rendering(struct drm_gem_object
*obj
,
53 static int i915_gem_object_bind_to_gtt(struct drm_gem_object
*obj
,
55 static void i915_gem_clear_fence_reg(struct drm_gem_object
*obj
);
56 static int i915_gem_phys_pwrite(struct drm_device
*dev
, struct drm_gem_object
*obj
,
57 struct drm_i915_gem_pwrite
*args
,
58 struct drm_file
*file_priv
);
59 static void i915_gem_free_object_tail(struct drm_gem_object
*obj
);
62 i915_gem_object_get_pages(struct drm_gem_object
*obj
,
66 i915_gem_object_put_pages(struct drm_gem_object
*obj
);
68 static LIST_HEAD(shrink_list
);
69 static DEFINE_SPINLOCK(shrink_list_lock
);
72 i915_gem_check_is_wedged(struct drm_device
*dev
)
74 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
75 struct completion
*x
= &dev_priv
->error_completion
;
79 if (!atomic_read(&dev_priv
->mm
.wedged
))
82 ret
= wait_for_completion_interruptible(x
);
86 /* Success, we reset the GPU! */
87 if (!atomic_read(&dev_priv
->mm
.wedged
))
90 /* GPU is hung, bump the completion count to account for
91 * the token we just consumed so that we never hit zero and
92 * end up waiting upon a subsequent completion event that
95 spin_lock_irqsave(&x
->wait
.lock
, flags
);
97 spin_unlock_irqrestore(&x
->wait
.lock
, flags
);
101 static int i915_mutex_lock_interruptible(struct drm_device
*dev
)
103 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
106 ret
= i915_gem_check_is_wedged(dev
);
110 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
114 if (atomic_read(&dev_priv
->mm
.wedged
)) {
115 mutex_unlock(&dev
->struct_mutex
);
119 WARN_ON(i915_verify_lists(dev
));
124 i915_gem_object_is_inactive(struct drm_i915_gem_object
*obj_priv
)
126 return obj_priv
->gtt_space
&&
128 obj_priv
->pin_count
== 0;
131 int i915_gem_do_init(struct drm_device
*dev
, unsigned long start
,
134 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
137 (start
& (PAGE_SIZE
- 1)) != 0 ||
138 (end
& (PAGE_SIZE
- 1)) != 0) {
142 drm_mm_init(&dev_priv
->mm
.gtt_space
, start
,
145 dev
->gtt_total
= (uint32_t) (end
- start
);
151 i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
152 struct drm_file
*file_priv
)
154 struct drm_i915_gem_init
*args
= data
;
157 mutex_lock(&dev
->struct_mutex
);
158 ret
= i915_gem_do_init(dev
, args
->gtt_start
, args
->gtt_end
);
159 mutex_unlock(&dev
->struct_mutex
);
165 i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
166 struct drm_file
*file_priv
)
168 struct drm_i915_gem_get_aperture
*args
= data
;
170 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
173 args
->aper_size
= dev
->gtt_total
;
174 args
->aper_available_size
= (args
->aper_size
-
175 atomic_read(&dev
->pin_memory
));
182 * Creates a new mm object and returns a handle to it.
185 i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
186 struct drm_file
*file_priv
)
188 struct drm_i915_gem_create
*args
= data
;
189 struct drm_gem_object
*obj
;
193 args
->size
= roundup(args
->size
, PAGE_SIZE
);
195 /* Allocate the new object */
196 obj
= i915_gem_alloc_object(dev
, args
->size
);
200 ret
= drm_gem_handle_create(file_priv
, obj
, &handle
);
202 drm_gem_object_unreference_unlocked(obj
);
206 /* Sink the floating reference from kref_init(handlecount) */
207 drm_gem_object_handle_unreference_unlocked(obj
);
209 args
->handle
= handle
;
214 fast_shmem_read(struct page
**pages
,
215 loff_t page_base
, int page_offset
,
222 vaddr
= kmap_atomic(pages
[page_base
>> PAGE_SHIFT
], KM_USER0
);
225 unwritten
= __copy_to_user_inatomic(data
, vaddr
+ page_offset
, length
);
226 kunmap_atomic(vaddr
, KM_USER0
);
234 static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object
*obj
)
236 drm_i915_private_t
*dev_priv
= obj
->dev
->dev_private
;
237 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
239 return dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_9_10_17
&&
240 obj_priv
->tiling_mode
!= I915_TILING_NONE
;
244 slow_shmem_copy(struct page
*dst_page
,
246 struct page
*src_page
,
250 char *dst_vaddr
, *src_vaddr
;
252 dst_vaddr
= kmap(dst_page
);
253 src_vaddr
= kmap(src_page
);
255 memcpy(dst_vaddr
+ dst_offset
, src_vaddr
+ src_offset
, length
);
262 slow_shmem_bit17_copy(struct page
*gpu_page
,
264 struct page
*cpu_page
,
269 char *gpu_vaddr
, *cpu_vaddr
;
271 /* Use the unswizzled path if this page isn't affected. */
272 if ((page_to_phys(gpu_page
) & (1 << 17)) == 0) {
274 return slow_shmem_copy(cpu_page
, cpu_offset
,
275 gpu_page
, gpu_offset
, length
);
277 return slow_shmem_copy(gpu_page
, gpu_offset
,
278 cpu_page
, cpu_offset
, length
);
281 gpu_vaddr
= kmap(gpu_page
);
282 cpu_vaddr
= kmap(cpu_page
);
284 /* Copy the data, XORing A6 with A17 (1). The user already knows he's
285 * XORing with the other bits (A9 for Y, A9 and A10 for X)
288 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
289 int this_length
= min(cacheline_end
- gpu_offset
, length
);
290 int swizzled_gpu_offset
= gpu_offset
^ 64;
293 memcpy(cpu_vaddr
+ cpu_offset
,
294 gpu_vaddr
+ swizzled_gpu_offset
,
297 memcpy(gpu_vaddr
+ swizzled_gpu_offset
,
298 cpu_vaddr
+ cpu_offset
,
301 cpu_offset
+= this_length
;
302 gpu_offset
+= this_length
;
303 length
-= this_length
;
311 * This is the fast shmem pread path, which attempts to copy_from_user directly
312 * from the backing pages of the object to the user's address space. On a
313 * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
316 i915_gem_shmem_pread_fast(struct drm_device
*dev
, struct drm_gem_object
*obj
,
317 struct drm_i915_gem_pread
*args
,
318 struct drm_file
*file_priv
)
320 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
322 loff_t offset
, page_base
;
323 char __user
*user_data
;
324 int page_offset
, page_length
;
327 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
330 ret
= i915_mutex_lock_interruptible(dev
);
334 ret
= i915_gem_object_get_pages(obj
, 0);
338 ret
= i915_gem_object_set_cpu_read_domain_range(obj
, args
->offset
,
343 obj_priv
= to_intel_bo(obj
);
344 offset
= args
->offset
;
347 /* Operation in this page
349 * page_base = page offset within aperture
350 * page_offset = offset within page
351 * page_length = bytes to copy for this page
353 page_base
= (offset
& ~(PAGE_SIZE
-1));
354 page_offset
= offset
& (PAGE_SIZE
-1);
355 page_length
= remain
;
356 if ((page_offset
+ remain
) > PAGE_SIZE
)
357 page_length
= PAGE_SIZE
- page_offset
;
359 ret
= fast_shmem_read(obj_priv
->pages
,
360 page_base
, page_offset
,
361 user_data
, page_length
);
365 remain
-= page_length
;
366 user_data
+= page_length
;
367 offset
+= page_length
;
371 i915_gem_object_put_pages(obj
);
373 mutex_unlock(&dev
->struct_mutex
);
379 i915_gem_object_get_pages_or_evict(struct drm_gem_object
*obj
)
383 ret
= i915_gem_object_get_pages(obj
, __GFP_NORETRY
| __GFP_NOWARN
);
385 /* If we've insufficient memory to map in the pages, attempt
386 * to make some space by throwing out some old buffers.
388 if (ret
== -ENOMEM
) {
389 struct drm_device
*dev
= obj
->dev
;
391 ret
= i915_gem_evict_something(dev
, obj
->size
,
392 i915_gem_get_gtt_alignment(obj
));
396 ret
= i915_gem_object_get_pages(obj
, 0);
403 * This is the fallback shmem pread path, which allocates temporary storage
404 * in kernel space to copy_to_user into outside of the struct_mutex, so we
405 * can copy out of the object's backing pages while holding the struct mutex
406 * and not take page faults.
409 i915_gem_shmem_pread_slow(struct drm_device
*dev
, struct drm_gem_object
*obj
,
410 struct drm_i915_gem_pread
*args
,
411 struct drm_file
*file_priv
)
413 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
414 struct mm_struct
*mm
= current
->mm
;
415 struct page
**user_pages
;
417 loff_t offset
, pinned_pages
, i
;
418 loff_t first_data_page
, last_data_page
, num_pages
;
419 int shmem_page_index
, shmem_page_offset
;
420 int data_page_index
, data_page_offset
;
423 uint64_t data_ptr
= args
->data_ptr
;
424 int do_bit17_swizzling
;
428 /* Pin the user pages containing the data. We can't fault while
429 * holding the struct mutex, yet we want to hold it while
430 * dereferencing the user data.
432 first_data_page
= data_ptr
/ PAGE_SIZE
;
433 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
434 num_pages
= last_data_page
- first_data_page
+ 1;
436 user_pages
= drm_calloc_large(num_pages
, sizeof(struct page
*));
437 if (user_pages
== NULL
)
440 down_read(&mm
->mmap_sem
);
441 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
442 num_pages
, 1, 0, user_pages
, NULL
);
443 up_read(&mm
->mmap_sem
);
444 if (pinned_pages
< num_pages
) {
446 goto fail_put_user_pages
;
449 do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
451 ret
= i915_mutex_lock_interruptible(dev
);
453 goto fail_put_user_pages
;
455 ret
= i915_gem_object_get_pages_or_evict(obj
);
459 ret
= i915_gem_object_set_cpu_read_domain_range(obj
, args
->offset
,
464 obj_priv
= to_intel_bo(obj
);
465 offset
= args
->offset
;
468 /* Operation in this page
470 * shmem_page_index = page number within shmem file
471 * shmem_page_offset = offset within page in shmem file
472 * data_page_index = page number in get_user_pages return
473 * data_page_offset = offset with data_page_index page.
474 * page_length = bytes to copy for this page
476 shmem_page_index
= offset
/ PAGE_SIZE
;
477 shmem_page_offset
= offset
& ~PAGE_MASK
;
478 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
479 data_page_offset
= data_ptr
& ~PAGE_MASK
;
481 page_length
= remain
;
482 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
483 page_length
= PAGE_SIZE
- shmem_page_offset
;
484 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
485 page_length
= PAGE_SIZE
- data_page_offset
;
487 if (do_bit17_swizzling
) {
488 slow_shmem_bit17_copy(obj_priv
->pages
[shmem_page_index
],
490 user_pages
[data_page_index
],
495 slow_shmem_copy(user_pages
[data_page_index
],
497 obj_priv
->pages
[shmem_page_index
],
502 remain
-= page_length
;
503 data_ptr
+= page_length
;
504 offset
+= page_length
;
508 i915_gem_object_put_pages(obj
);
510 mutex_unlock(&dev
->struct_mutex
);
512 for (i
= 0; i
< pinned_pages
; i
++) {
513 SetPageDirty(user_pages
[i
]);
514 page_cache_release(user_pages
[i
]);
516 drm_free_large(user_pages
);
522 * Reads data from the object referenced by handle.
524 * On error, the contents of *data are undefined.
527 i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
528 struct drm_file
*file_priv
)
530 struct drm_i915_gem_pread
*args
= data
;
531 struct drm_gem_object
*obj
;
532 struct drm_i915_gem_object
*obj_priv
;
535 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
538 obj_priv
= to_intel_bo(obj
);
540 /* Bounds check source.
542 * XXX: This could use review for overflow issues...
544 if (args
->offset
> obj
->size
|| args
->size
> obj
->size
||
545 args
->offset
+ args
->size
> obj
->size
) {
546 drm_gem_object_unreference_unlocked(obj
);
550 if (i915_gem_object_needs_bit17_swizzle(obj
)) {
551 ret
= i915_gem_shmem_pread_slow(dev
, obj
, args
, file_priv
);
553 ret
= i915_gem_shmem_pread_fast(dev
, obj
, args
, file_priv
);
555 ret
= i915_gem_shmem_pread_slow(dev
, obj
, args
,
559 drm_gem_object_unreference_unlocked(obj
);
564 /* This is the fast write path which cannot handle
565 * page faults in the source data
569 fast_user_write(struct io_mapping
*mapping
,
570 loff_t page_base
, int page_offset
,
571 char __user
*user_data
,
575 unsigned long unwritten
;
577 vaddr_atomic
= io_mapping_map_atomic_wc(mapping
, page_base
, KM_USER0
);
578 unwritten
= __copy_from_user_inatomic_nocache(vaddr_atomic
+ page_offset
,
580 io_mapping_unmap_atomic(vaddr_atomic
, KM_USER0
);
586 /* Here's the write path which can sleep for
591 slow_kernel_write(struct io_mapping
*mapping
,
592 loff_t gtt_base
, int gtt_offset
,
593 struct page
*user_page
, int user_offset
,
596 char __iomem
*dst_vaddr
;
599 dst_vaddr
= io_mapping_map_wc(mapping
, gtt_base
);
600 src_vaddr
= kmap(user_page
);
602 memcpy_toio(dst_vaddr
+ gtt_offset
,
603 src_vaddr
+ user_offset
,
607 io_mapping_unmap(dst_vaddr
);
611 fast_shmem_write(struct page
**pages
,
612 loff_t page_base
, int page_offset
,
617 unsigned long unwritten
;
619 vaddr
= kmap_atomic(pages
[page_base
>> PAGE_SHIFT
], KM_USER0
);
622 unwritten
= __copy_from_user_inatomic(vaddr
+ page_offset
, data
, length
);
623 kunmap_atomic(vaddr
, KM_USER0
);
631 * This is the fast pwrite path, where we copy the data directly from the
632 * user into the GTT, uncached.
635 i915_gem_gtt_pwrite_fast(struct drm_device
*dev
, struct drm_gem_object
*obj
,
636 struct drm_i915_gem_pwrite
*args
,
637 struct drm_file
*file_priv
)
639 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
640 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
642 loff_t offset
, page_base
;
643 char __user
*user_data
;
644 int page_offset
, page_length
;
647 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
649 if (!access_ok(VERIFY_READ
, user_data
, remain
))
652 ret
= i915_mutex_lock_interruptible(dev
);
656 ret
= i915_gem_object_pin(obj
, 0);
658 mutex_unlock(&dev
->struct_mutex
);
661 ret
= i915_gem_object_set_to_gtt_domain(obj
, 1);
665 obj_priv
= to_intel_bo(obj
);
666 offset
= obj_priv
->gtt_offset
+ args
->offset
;
669 /* Operation in this page
671 * page_base = page offset within aperture
672 * page_offset = offset within page
673 * page_length = bytes to copy for this page
675 page_base
= (offset
& ~(PAGE_SIZE
-1));
676 page_offset
= offset
& (PAGE_SIZE
-1);
677 page_length
= remain
;
678 if ((page_offset
+ remain
) > PAGE_SIZE
)
679 page_length
= PAGE_SIZE
- page_offset
;
681 ret
= fast_user_write (dev_priv
->mm
.gtt_mapping
, page_base
,
682 page_offset
, user_data
, page_length
);
684 /* If we get a fault while copying data, then (presumably) our
685 * source page isn't available. Return the error and we'll
686 * retry in the slow path.
691 remain
-= page_length
;
692 user_data
+= page_length
;
693 offset
+= page_length
;
697 i915_gem_object_unpin(obj
);
698 mutex_unlock(&dev
->struct_mutex
);
704 * This is the fallback GTT pwrite path, which uses get_user_pages to pin
705 * the memory and maps it using kmap_atomic for copying.
707 * This code resulted in x11perf -rgb10text consuming about 10% more CPU
708 * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
711 i915_gem_gtt_pwrite_slow(struct drm_device
*dev
, struct drm_gem_object
*obj
,
712 struct drm_i915_gem_pwrite
*args
,
713 struct drm_file
*file_priv
)
715 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
716 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
718 loff_t gtt_page_base
, offset
;
719 loff_t first_data_page
, last_data_page
, num_pages
;
720 loff_t pinned_pages
, i
;
721 struct page
**user_pages
;
722 struct mm_struct
*mm
= current
->mm
;
723 int gtt_page_offset
, data_page_offset
, data_page_index
, page_length
;
725 uint64_t data_ptr
= args
->data_ptr
;
729 /* Pin the user pages containing the data. We can't fault while
730 * holding the struct mutex, and all of the pwrite implementations
731 * want to hold it while dereferencing the user data.
733 first_data_page
= data_ptr
/ PAGE_SIZE
;
734 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
735 num_pages
= last_data_page
- first_data_page
+ 1;
737 user_pages
= drm_calloc_large(num_pages
, sizeof(struct page
*));
738 if (user_pages
== NULL
)
741 down_read(&mm
->mmap_sem
);
742 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
743 num_pages
, 0, 0, user_pages
, NULL
);
744 up_read(&mm
->mmap_sem
);
745 if (pinned_pages
< num_pages
) {
747 goto out_unpin_pages
;
750 ret
= i915_mutex_lock_interruptible(dev
);
752 goto out_unpin_pages
;
754 ret
= i915_gem_object_pin(obj
, 0);
758 ret
= i915_gem_object_set_to_gtt_domain(obj
, 1);
760 goto out_unpin_object
;
762 obj_priv
= to_intel_bo(obj
);
763 offset
= obj_priv
->gtt_offset
+ args
->offset
;
766 /* Operation in this page
768 * gtt_page_base = page offset within aperture
769 * gtt_page_offset = offset within page in aperture
770 * data_page_index = page number in get_user_pages return
771 * data_page_offset = offset with data_page_index page.
772 * page_length = bytes to copy for this page
774 gtt_page_base
= offset
& PAGE_MASK
;
775 gtt_page_offset
= offset
& ~PAGE_MASK
;
776 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
777 data_page_offset
= data_ptr
& ~PAGE_MASK
;
779 page_length
= remain
;
780 if ((gtt_page_offset
+ page_length
) > PAGE_SIZE
)
781 page_length
= PAGE_SIZE
- gtt_page_offset
;
782 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
783 page_length
= PAGE_SIZE
- data_page_offset
;
785 slow_kernel_write(dev_priv
->mm
.gtt_mapping
,
786 gtt_page_base
, gtt_page_offset
,
787 user_pages
[data_page_index
],
791 remain
-= page_length
;
792 offset
+= page_length
;
793 data_ptr
+= page_length
;
797 i915_gem_object_unpin(obj
);
799 mutex_unlock(&dev
->struct_mutex
);
801 for (i
= 0; i
< pinned_pages
; i
++)
802 page_cache_release(user_pages
[i
]);
803 drm_free_large(user_pages
);
809 * This is the fast shmem pwrite path, which attempts to directly
810 * copy_from_user into the kmapped pages backing the object.
813 i915_gem_shmem_pwrite_fast(struct drm_device
*dev
, struct drm_gem_object
*obj
,
814 struct drm_i915_gem_pwrite
*args
,
815 struct drm_file
*file_priv
)
817 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
819 loff_t offset
, page_base
;
820 char __user
*user_data
;
821 int page_offset
, page_length
;
824 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
827 ret
= i915_mutex_lock_interruptible(dev
);
831 ret
= i915_gem_object_get_pages(obj
, 0);
835 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
839 obj_priv
= to_intel_bo(obj
);
840 offset
= args
->offset
;
844 /* Operation in this page
846 * page_base = page offset within aperture
847 * page_offset = offset within page
848 * page_length = bytes to copy for this page
850 page_base
= (offset
& ~(PAGE_SIZE
-1));
851 page_offset
= offset
& (PAGE_SIZE
-1);
852 page_length
= remain
;
853 if ((page_offset
+ remain
) > PAGE_SIZE
)
854 page_length
= PAGE_SIZE
- page_offset
;
856 ret
= fast_shmem_write(obj_priv
->pages
,
857 page_base
, page_offset
,
858 user_data
, page_length
);
862 remain
-= page_length
;
863 user_data
+= page_length
;
864 offset
+= page_length
;
868 i915_gem_object_put_pages(obj
);
870 mutex_unlock(&dev
->struct_mutex
);
876 * This is the fallback shmem pwrite path, which uses get_user_pages to pin
877 * the memory and maps it using kmap_atomic for copying.
879 * This avoids taking mmap_sem for faulting on the user's address while the
880 * struct_mutex is held.
883 i915_gem_shmem_pwrite_slow(struct drm_device
*dev
, struct drm_gem_object
*obj
,
884 struct drm_i915_gem_pwrite
*args
,
885 struct drm_file
*file_priv
)
887 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
888 struct mm_struct
*mm
= current
->mm
;
889 struct page
**user_pages
;
891 loff_t offset
, pinned_pages
, i
;
892 loff_t first_data_page
, last_data_page
, num_pages
;
893 int shmem_page_index
, shmem_page_offset
;
894 int data_page_index
, data_page_offset
;
897 uint64_t data_ptr
= args
->data_ptr
;
898 int do_bit17_swizzling
;
902 /* Pin the user pages containing the data. We can't fault while
903 * holding the struct mutex, and all of the pwrite implementations
904 * want to hold it while dereferencing the user data.
906 first_data_page
= data_ptr
/ PAGE_SIZE
;
907 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
908 num_pages
= last_data_page
- first_data_page
+ 1;
910 user_pages
= drm_calloc_large(num_pages
, sizeof(struct page
*));
911 if (user_pages
== NULL
)
914 down_read(&mm
->mmap_sem
);
915 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
916 num_pages
, 0, 0, user_pages
, NULL
);
917 up_read(&mm
->mmap_sem
);
918 if (pinned_pages
< num_pages
) {
920 goto fail_put_user_pages
;
923 do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
925 ret
= i915_mutex_lock_interruptible(dev
);
927 goto fail_put_user_pages
;
929 ret
= i915_gem_object_get_pages_or_evict(obj
);
933 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
937 obj_priv
= to_intel_bo(obj
);
938 offset
= args
->offset
;
942 /* Operation in this page
944 * shmem_page_index = page number within shmem file
945 * shmem_page_offset = offset within page in shmem file
946 * data_page_index = page number in get_user_pages return
947 * data_page_offset = offset with data_page_index page.
948 * page_length = bytes to copy for this page
950 shmem_page_index
= offset
/ PAGE_SIZE
;
951 shmem_page_offset
= offset
& ~PAGE_MASK
;
952 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
953 data_page_offset
= data_ptr
& ~PAGE_MASK
;
955 page_length
= remain
;
956 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
957 page_length
= PAGE_SIZE
- shmem_page_offset
;
958 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
959 page_length
= PAGE_SIZE
- data_page_offset
;
961 if (do_bit17_swizzling
) {
962 slow_shmem_bit17_copy(obj_priv
->pages
[shmem_page_index
],
964 user_pages
[data_page_index
],
969 slow_shmem_copy(obj_priv
->pages
[shmem_page_index
],
971 user_pages
[data_page_index
],
976 remain
-= page_length
;
977 data_ptr
+= page_length
;
978 offset
+= page_length
;
982 i915_gem_object_put_pages(obj
);
984 mutex_unlock(&dev
->struct_mutex
);
986 for (i
= 0; i
< pinned_pages
; i
++)
987 page_cache_release(user_pages
[i
]);
988 drm_free_large(user_pages
);
994 * Writes data to the object referenced by handle.
996 * On error, the contents of the buffer that were to be modified are undefined.
999 i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
1000 struct drm_file
*file_priv
)
1002 struct drm_i915_gem_pwrite
*args
= data
;
1003 struct drm_gem_object
*obj
;
1004 struct drm_i915_gem_object
*obj_priv
;
1007 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1010 obj_priv
= to_intel_bo(obj
);
1012 /* Bounds check destination.
1014 * XXX: This could use review for overflow issues...
1016 if (args
->offset
> obj
->size
|| args
->size
> obj
->size
||
1017 args
->offset
+ args
->size
> obj
->size
) {
1018 drm_gem_object_unreference_unlocked(obj
);
1022 /* We can only do the GTT pwrite on untiled buffers, as otherwise
1023 * it would end up going through the fenced access, and we'll get
1024 * different detiling behavior between reading and writing.
1025 * pread/pwrite currently are reading and writing from the CPU
1026 * perspective, requiring manual detiling by the client.
1028 if (obj_priv
->phys_obj
)
1029 ret
= i915_gem_phys_pwrite(dev
, obj
, args
, file_priv
);
1030 else if (obj_priv
->tiling_mode
== I915_TILING_NONE
&&
1031 obj_priv
->gtt_space
&&
1032 obj
->write_domain
!= I915_GEM_DOMAIN_CPU
) {
1033 ret
= i915_gem_gtt_pwrite_fast(dev
, obj
, args
, file_priv
);
1034 if (ret
== -EFAULT
) {
1035 ret
= i915_gem_gtt_pwrite_slow(dev
, obj
, args
,
1038 } else if (i915_gem_object_needs_bit17_swizzle(obj
)) {
1039 ret
= i915_gem_shmem_pwrite_slow(dev
, obj
, args
, file_priv
);
1041 ret
= i915_gem_shmem_pwrite_fast(dev
, obj
, args
, file_priv
);
1042 if (ret
== -EFAULT
) {
1043 ret
= i915_gem_shmem_pwrite_slow(dev
, obj
, args
,
1050 DRM_INFO("pwrite failed %d\n", ret
);
1053 drm_gem_object_unreference_unlocked(obj
);
1059 * Called when user space prepares to use an object with the CPU, either
1060 * through the mmap ioctl's mapping or a GTT mapping.
1063 i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
1064 struct drm_file
*file_priv
)
1066 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1067 struct drm_i915_gem_set_domain
*args
= data
;
1068 struct drm_gem_object
*obj
;
1069 struct drm_i915_gem_object
*obj_priv
;
1070 uint32_t read_domains
= args
->read_domains
;
1071 uint32_t write_domain
= args
->write_domain
;
1074 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1077 /* Only handle setting domains to types used by the CPU. */
1078 if (write_domain
& I915_GEM_GPU_DOMAINS
)
1081 if (read_domains
& I915_GEM_GPU_DOMAINS
)
1084 /* Having something in the write domain implies it's in the read
1085 * domain, and only that read domain. Enforce that in the request.
1087 if (write_domain
!= 0 && read_domains
!= write_domain
)
1090 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1093 obj_priv
= to_intel_bo(obj
);
1095 ret
= i915_mutex_lock_interruptible(dev
);
1097 drm_gem_object_unreference_unlocked(obj
);
1101 intel_mark_busy(dev
, obj
);
1103 if (read_domains
& I915_GEM_DOMAIN_GTT
) {
1104 ret
= i915_gem_object_set_to_gtt_domain(obj
, write_domain
!= 0);
1106 /* Update the LRU on the fence for the CPU access that's
1109 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
) {
1110 struct drm_i915_fence_reg
*reg
=
1111 &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
1112 list_move_tail(®
->lru_list
,
1113 &dev_priv
->mm
.fence_list
);
1116 /* Silently promote "you're not bound, there was nothing to do"
1117 * to success, since the client was just asking us to
1118 * make sure everything was done.
1123 ret
= i915_gem_object_set_to_cpu_domain(obj
, write_domain
!= 0);
1126 /* Maintain LRU order of "inactive" objects */
1127 if (ret
== 0 && i915_gem_object_is_inactive(obj_priv
))
1128 list_move_tail(&obj_priv
->list
, &dev_priv
->mm
.inactive_list
);
1130 drm_gem_object_unreference(obj
);
1131 mutex_unlock(&dev
->struct_mutex
);
1136 * Called when user space has done writes to this buffer
1139 i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1140 struct drm_file
*file_priv
)
1142 struct drm_i915_gem_sw_finish
*args
= data
;
1143 struct drm_gem_object
*obj
;
1146 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1149 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1153 ret
= i915_mutex_lock_interruptible(dev
);
1155 drm_gem_object_unreference_unlocked(obj
);
1159 /* Pinned buffers may be scanout, so flush the cache */
1160 if (to_intel_bo(obj
)->pin_count
)
1161 i915_gem_object_flush_cpu_write_domain(obj
);
1163 drm_gem_object_unreference(obj
);
1164 mutex_unlock(&dev
->struct_mutex
);
1169 * Maps the contents of an object, returning the address it is mapped
1172 * While the mapping holds a reference on the contents of the object, it doesn't
1173 * imply a ref on the object itself.
1176 i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1177 struct drm_file
*file_priv
)
1179 struct drm_i915_gem_mmap
*args
= data
;
1180 struct drm_gem_object
*obj
;
1184 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1187 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1191 offset
= args
->offset
;
1193 down_write(¤t
->mm
->mmap_sem
);
1194 addr
= do_mmap(obj
->filp
, 0, args
->size
,
1195 PROT_READ
| PROT_WRITE
, MAP_SHARED
,
1197 up_write(¤t
->mm
->mmap_sem
);
1198 drm_gem_object_unreference_unlocked(obj
);
1199 if (IS_ERR((void *)addr
))
1202 args
->addr_ptr
= (uint64_t) addr
;
1208 * i915_gem_fault - fault a page into the GTT
1209 * vma: VMA in question
1212 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1213 * from userspace. The fault handler takes care of binding the object to
1214 * the GTT (if needed), allocating and programming a fence register (again,
1215 * only if needed based on whether the old reg is still valid or the object
1216 * is tiled) and inserting a new PTE into the faulting process.
1218 * Note that the faulting process may involve evicting existing objects
1219 * from the GTT and/or fence registers to make room. So performance may
1220 * suffer if the GTT working set is large or there are few fence registers
1223 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
)
1225 struct drm_gem_object
*obj
= vma
->vm_private_data
;
1226 struct drm_device
*dev
= obj
->dev
;
1227 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1228 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1229 pgoff_t page_offset
;
1232 bool write
= !!(vmf
->flags
& FAULT_FLAG_WRITE
);
1234 /* We don't use vmf->pgoff since that has the fake offset */
1235 page_offset
= ((unsigned long)vmf
->virtual_address
- vma
->vm_start
) >>
1238 /* Now bind it into the GTT if needed */
1239 mutex_lock(&dev
->struct_mutex
);
1240 if (!obj_priv
->gtt_space
) {
1241 ret
= i915_gem_object_bind_to_gtt(obj
, 0);
1245 ret
= i915_gem_object_set_to_gtt_domain(obj
, write
);
1250 /* Need a new fence register? */
1251 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
) {
1252 ret
= i915_gem_object_get_fence_reg(obj
, true);
1257 if (i915_gem_object_is_inactive(obj_priv
))
1258 list_move_tail(&obj_priv
->list
, &dev_priv
->mm
.inactive_list
);
1260 pfn
= ((dev
->agp
->base
+ obj_priv
->gtt_offset
) >> PAGE_SHIFT
) +
1263 /* Finally, remap it using the new GTT offset */
1264 ret
= vm_insert_pfn(vma
, (unsigned long)vmf
->virtual_address
, pfn
);
1266 mutex_unlock(&dev
->struct_mutex
);
1271 return VM_FAULT_NOPAGE
;
1274 return VM_FAULT_OOM
;
1276 return VM_FAULT_SIGBUS
;
1281 * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1282 * @obj: obj in question
1284 * GEM memory mapping works by handing back to userspace a fake mmap offset
1285 * it can use in a subsequent mmap(2) call. The DRM core code then looks
1286 * up the object based on the offset and sets up the various memory mapping
1289 * This routine allocates and attaches a fake offset for @obj.
1292 i915_gem_create_mmap_offset(struct drm_gem_object
*obj
)
1294 struct drm_device
*dev
= obj
->dev
;
1295 struct drm_gem_mm
*mm
= dev
->mm_private
;
1296 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1297 struct drm_map_list
*list
;
1298 struct drm_local_map
*map
;
1301 /* Set the object up for mmap'ing */
1302 list
= &obj
->map_list
;
1303 list
->map
= kzalloc(sizeof(struct drm_map_list
), GFP_KERNEL
);
1308 map
->type
= _DRM_GEM
;
1309 map
->size
= obj
->size
;
1312 /* Get a DRM GEM mmap offset allocated... */
1313 list
->file_offset_node
= drm_mm_search_free(&mm
->offset_manager
,
1314 obj
->size
/ PAGE_SIZE
, 0, 0);
1315 if (!list
->file_offset_node
) {
1316 DRM_ERROR("failed to allocate offset for bo %d\n", obj
->name
);
1321 list
->file_offset_node
= drm_mm_get_block(list
->file_offset_node
,
1322 obj
->size
/ PAGE_SIZE
, 0);
1323 if (!list
->file_offset_node
) {
1328 list
->hash
.key
= list
->file_offset_node
->start
;
1329 ret
= drm_ht_insert_item(&mm
->offset_hash
, &list
->hash
);
1331 DRM_ERROR("failed to add to map hash\n");
1335 /* By now we should be all set, any drm_mmap request on the offset
1336 * below will get to our mmap & fault handler */
1337 obj_priv
->mmap_offset
= ((uint64_t) list
->hash
.key
) << PAGE_SHIFT
;
1342 drm_mm_put_block(list
->file_offset_node
);
1350 * i915_gem_release_mmap - remove physical page mappings
1351 * @obj: obj in question
1353 * Preserve the reservation of the mmapping with the DRM core code, but
1354 * relinquish ownership of the pages back to the system.
1356 * It is vital that we remove the page mapping if we have mapped a tiled
1357 * object through the GTT and then lose the fence register due to
1358 * resource pressure. Similarly if the object has been moved out of the
1359 * aperture, than pages mapped into userspace must be revoked. Removing the
1360 * mapping will then trigger a page fault on the next user access, allowing
1361 * fixup by i915_gem_fault().
1364 i915_gem_release_mmap(struct drm_gem_object
*obj
)
1366 struct drm_device
*dev
= obj
->dev
;
1367 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1369 if (dev
->dev_mapping
)
1370 unmap_mapping_range(dev
->dev_mapping
,
1371 obj_priv
->mmap_offset
, obj
->size
, 1);
1375 i915_gem_free_mmap_offset(struct drm_gem_object
*obj
)
1377 struct drm_device
*dev
= obj
->dev
;
1378 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1379 struct drm_gem_mm
*mm
= dev
->mm_private
;
1380 struct drm_map_list
*list
;
1382 list
= &obj
->map_list
;
1383 drm_ht_remove_item(&mm
->offset_hash
, &list
->hash
);
1385 if (list
->file_offset_node
) {
1386 drm_mm_put_block(list
->file_offset_node
);
1387 list
->file_offset_node
= NULL
;
1395 obj_priv
->mmap_offset
= 0;
1399 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1400 * @obj: object to check
1402 * Return the required GTT alignment for an object, taking into account
1403 * potential fence register mapping if needed.
1406 i915_gem_get_gtt_alignment(struct drm_gem_object
*obj
)
1408 struct drm_device
*dev
= obj
->dev
;
1409 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1413 * Minimum alignment is 4k (GTT page size), but might be greater
1414 * if a fence register is needed for the object.
1416 if (INTEL_INFO(dev
)->gen
>= 4 || obj_priv
->tiling_mode
== I915_TILING_NONE
)
1420 * Previous chips need to be aligned to the size of the smallest
1421 * fence register that can contain the object.
1423 if (INTEL_INFO(dev
)->gen
== 3)
1428 for (i
= start
; i
< obj
->size
; i
<<= 1)
1435 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1437 * @data: GTT mapping ioctl data
1438 * @file_priv: GEM object info
1440 * Simply returns the fake offset to userspace so it can mmap it.
1441 * The mmap call will end up in drm_gem_mmap(), which will set things
1442 * up so we can get faults in the handler above.
1444 * The fault handler will take care of binding the object into the GTT
1445 * (since it may have been evicted to make room for something), allocating
1446 * a fence register, and mapping the appropriate aperture address into
1450 i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
1451 struct drm_file
*file_priv
)
1453 struct drm_i915_gem_mmap_gtt
*args
= data
;
1454 struct drm_gem_object
*obj
;
1455 struct drm_i915_gem_object
*obj_priv
;
1458 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1461 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1465 ret
= i915_mutex_lock_interruptible(dev
);
1467 drm_gem_object_unreference_unlocked(obj
);
1471 obj_priv
= to_intel_bo(obj
);
1473 if (obj_priv
->madv
!= I915_MADV_WILLNEED
) {
1474 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1475 drm_gem_object_unreference(obj
);
1476 mutex_unlock(&dev
->struct_mutex
);
1481 if (!obj_priv
->mmap_offset
) {
1482 ret
= i915_gem_create_mmap_offset(obj
);
1484 drm_gem_object_unreference(obj
);
1485 mutex_unlock(&dev
->struct_mutex
);
1490 args
->offset
= obj_priv
->mmap_offset
;
1493 * Pull it into the GTT so that we have a page list (makes the
1494 * initial fault faster and any subsequent flushing possible).
1496 if (!obj_priv
->agp_mem
) {
1497 ret
= i915_gem_object_bind_to_gtt(obj
, 0);
1499 drm_gem_object_unreference(obj
);
1500 mutex_unlock(&dev
->struct_mutex
);
1505 drm_gem_object_unreference(obj
);
1506 mutex_unlock(&dev
->struct_mutex
);
1512 i915_gem_object_put_pages(struct drm_gem_object
*obj
)
1514 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1515 int page_count
= obj
->size
/ PAGE_SIZE
;
1518 BUG_ON(obj_priv
->pages_refcount
== 0);
1519 BUG_ON(obj_priv
->madv
== __I915_MADV_PURGED
);
1521 if (--obj_priv
->pages_refcount
!= 0)
1524 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
)
1525 i915_gem_object_save_bit_17_swizzle(obj
);
1527 if (obj_priv
->madv
== I915_MADV_DONTNEED
)
1528 obj_priv
->dirty
= 0;
1530 for (i
= 0; i
< page_count
; i
++) {
1531 if (obj_priv
->dirty
)
1532 set_page_dirty(obj_priv
->pages
[i
]);
1534 if (obj_priv
->madv
== I915_MADV_WILLNEED
)
1535 mark_page_accessed(obj_priv
->pages
[i
]);
1537 page_cache_release(obj_priv
->pages
[i
]);
1539 obj_priv
->dirty
= 0;
1541 drm_free_large(obj_priv
->pages
);
1542 obj_priv
->pages
= NULL
;
1546 i915_gem_next_request_seqno(struct drm_device
*dev
,
1547 struct intel_ring_buffer
*ring
)
1549 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1551 ring
->outstanding_lazy_request
= true;
1552 return dev_priv
->next_seqno
;
1556 i915_gem_object_move_to_active(struct drm_gem_object
*obj
,
1557 struct intel_ring_buffer
*ring
)
1559 struct drm_device
*dev
= obj
->dev
;
1560 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1561 uint32_t seqno
= i915_gem_next_request_seqno(dev
, ring
);
1563 BUG_ON(ring
== NULL
);
1564 obj_priv
->ring
= ring
;
1566 /* Add a reference if we're newly entering the active list. */
1567 if (!obj_priv
->active
) {
1568 drm_gem_object_reference(obj
);
1569 obj_priv
->active
= 1;
1572 /* Move from whatever list we were on to the tail of execution. */
1573 list_move_tail(&obj_priv
->list
, &ring
->active_list
);
1574 obj_priv
->last_rendering_seqno
= seqno
;
1578 i915_gem_object_move_to_flushing(struct drm_gem_object
*obj
)
1580 struct drm_device
*dev
= obj
->dev
;
1581 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1582 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1584 BUG_ON(!obj_priv
->active
);
1585 list_move_tail(&obj_priv
->list
, &dev_priv
->mm
.flushing_list
);
1586 obj_priv
->last_rendering_seqno
= 0;
1589 /* Immediately discard the backing storage */
1591 i915_gem_object_truncate(struct drm_gem_object
*obj
)
1593 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1594 struct inode
*inode
;
1596 /* Our goal here is to return as much of the memory as
1597 * is possible back to the system as we are called from OOM.
1598 * To do this we must instruct the shmfs to drop all of its
1599 * backing pages, *now*. Here we mirror the actions taken
1600 * when by shmem_delete_inode() to release the backing store.
1602 inode
= obj
->filp
->f_path
.dentry
->d_inode
;
1603 truncate_inode_pages(inode
->i_mapping
, 0);
1604 if (inode
->i_op
->truncate_range
)
1605 inode
->i_op
->truncate_range(inode
, 0, (loff_t
)-1);
1607 obj_priv
->madv
= __I915_MADV_PURGED
;
1611 i915_gem_object_is_purgeable(struct drm_i915_gem_object
*obj_priv
)
1613 return obj_priv
->madv
== I915_MADV_DONTNEED
;
1617 i915_gem_object_move_to_inactive(struct drm_gem_object
*obj
)
1619 struct drm_device
*dev
= obj
->dev
;
1620 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1621 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1623 if (obj_priv
->pin_count
!= 0)
1624 list_move_tail(&obj_priv
->list
, &dev_priv
->mm
.pinned_list
);
1626 list_move_tail(&obj_priv
->list
, &dev_priv
->mm
.inactive_list
);
1628 BUG_ON(!list_empty(&obj_priv
->gpu_write_list
));
1630 obj_priv
->last_rendering_seqno
= 0;
1631 obj_priv
->ring
= NULL
;
1632 if (obj_priv
->active
) {
1633 obj_priv
->active
= 0;
1634 drm_gem_object_unreference(obj
);
1636 WARN_ON(i915_verify_lists(dev
));
1640 i915_gem_process_flushing_list(struct drm_device
*dev
,
1641 uint32_t flush_domains
,
1642 struct intel_ring_buffer
*ring
)
1644 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1645 struct drm_i915_gem_object
*obj_priv
, *next
;
1647 list_for_each_entry_safe(obj_priv
, next
,
1648 &dev_priv
->mm
.gpu_write_list
,
1650 struct drm_gem_object
*obj
= &obj_priv
->base
;
1652 if (obj
->write_domain
& flush_domains
&&
1653 obj_priv
->ring
== ring
) {
1654 uint32_t old_write_domain
= obj
->write_domain
;
1656 obj
->write_domain
= 0;
1657 list_del_init(&obj_priv
->gpu_write_list
);
1658 i915_gem_object_move_to_active(obj
, ring
);
1660 /* update the fence lru list */
1661 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
) {
1662 struct drm_i915_fence_reg
*reg
=
1663 &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
1664 list_move_tail(®
->lru_list
,
1665 &dev_priv
->mm
.fence_list
);
1668 trace_i915_gem_object_change_domain(obj
,
1676 i915_add_request(struct drm_device
*dev
,
1677 struct drm_file
*file
,
1678 struct drm_i915_gem_request
*request
,
1679 struct intel_ring_buffer
*ring
)
1681 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1682 struct drm_i915_file_private
*file_priv
= NULL
;
1687 file_priv
= file
->driver_priv
;
1689 if (request
== NULL
) {
1690 request
= kzalloc(sizeof(*request
), GFP_KERNEL
);
1691 if (request
== NULL
)
1695 seqno
= ring
->add_request(dev
, ring
, 0);
1696 ring
->outstanding_lazy_request
= false;
1698 request
->seqno
= seqno
;
1699 request
->ring
= ring
;
1700 request
->emitted_jiffies
= jiffies
;
1701 was_empty
= list_empty(&ring
->request_list
);
1702 list_add_tail(&request
->list
, &ring
->request_list
);
1705 spin_lock(&file_priv
->mm
.lock
);
1706 request
->file_priv
= file_priv
;
1707 list_add_tail(&request
->client_list
,
1708 &file_priv
->mm
.request_list
);
1709 spin_unlock(&file_priv
->mm
.lock
);
1712 if (!dev_priv
->mm
.suspended
) {
1713 mod_timer(&dev_priv
->hangcheck_timer
,
1714 jiffies
+ msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD
));
1716 queue_delayed_work(dev_priv
->wq
,
1717 &dev_priv
->mm
.retire_work
, HZ
);
1723 * Command execution barrier
1725 * Ensures that all commands in the ring are finished
1726 * before signalling the CPU
1729 i915_retire_commands(struct drm_device
*dev
, struct intel_ring_buffer
*ring
)
1731 uint32_t flush_domains
= 0;
1733 /* The sampler always gets flushed on i965 (sigh) */
1734 if (INTEL_INFO(dev
)->gen
>= 4)
1735 flush_domains
|= I915_GEM_DOMAIN_SAMPLER
;
1737 ring
->flush(dev
, ring
,
1738 I915_GEM_DOMAIN_COMMAND
, flush_domains
);
1742 i915_gem_request_remove_from_client(struct drm_i915_gem_request
*request
)
1744 struct drm_i915_file_private
*file_priv
= request
->file_priv
;
1749 spin_lock(&file_priv
->mm
.lock
);
1750 list_del(&request
->client_list
);
1751 request
->file_priv
= NULL
;
1752 spin_unlock(&file_priv
->mm
.lock
);
1755 static void i915_gem_reset_ring_lists(struct drm_i915_private
*dev_priv
,
1756 struct intel_ring_buffer
*ring
)
1758 while (!list_empty(&ring
->request_list
)) {
1759 struct drm_i915_gem_request
*request
;
1761 request
= list_first_entry(&ring
->request_list
,
1762 struct drm_i915_gem_request
,
1765 list_del(&request
->list
);
1766 i915_gem_request_remove_from_client(request
);
1770 while (!list_empty(&ring
->active_list
)) {
1771 struct drm_i915_gem_object
*obj_priv
;
1773 obj_priv
= list_first_entry(&ring
->active_list
,
1774 struct drm_i915_gem_object
,
1777 obj_priv
->base
.write_domain
= 0;
1778 list_del_init(&obj_priv
->gpu_write_list
);
1779 i915_gem_object_move_to_inactive(&obj_priv
->base
);
1783 void i915_gem_reset_lists(struct drm_device
*dev
)
1785 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1786 struct drm_i915_gem_object
*obj_priv
;
1788 i915_gem_reset_ring_lists(dev_priv
, &dev_priv
->render_ring
);
1790 i915_gem_reset_ring_lists(dev_priv
, &dev_priv
->bsd_ring
);
1792 /* Remove anything from the flushing lists. The GPU cache is likely
1793 * to be lost on reset along with the data, so simply move the
1794 * lost bo to the inactive list.
1796 while (!list_empty(&dev_priv
->mm
.flushing_list
)) {
1797 obj_priv
= list_first_entry(&dev_priv
->mm
.flushing_list
,
1798 struct drm_i915_gem_object
,
1801 obj_priv
->base
.write_domain
= 0;
1802 list_del_init(&obj_priv
->gpu_write_list
);
1803 i915_gem_object_move_to_inactive(&obj_priv
->base
);
1806 /* Move everything out of the GPU domains to ensure we do any
1807 * necessary invalidation upon reuse.
1809 list_for_each_entry(obj_priv
,
1810 &dev_priv
->mm
.inactive_list
,
1813 obj_priv
->base
.read_domains
&= ~I915_GEM_GPU_DOMAINS
;
1818 * This function clears the request list as sequence numbers are passed.
1821 i915_gem_retire_requests_ring(struct drm_device
*dev
,
1822 struct intel_ring_buffer
*ring
)
1824 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1827 if (!ring
->status_page
.page_addr
||
1828 list_empty(&ring
->request_list
))
1831 WARN_ON(i915_verify_lists(dev
));
1833 seqno
= ring
->get_seqno(dev
, ring
);
1834 while (!list_empty(&ring
->request_list
)) {
1835 struct drm_i915_gem_request
*request
;
1837 request
= list_first_entry(&ring
->request_list
,
1838 struct drm_i915_gem_request
,
1841 if (!i915_seqno_passed(seqno
, request
->seqno
))
1844 trace_i915_gem_request_retire(dev
, request
->seqno
);
1846 list_del(&request
->list
);
1847 i915_gem_request_remove_from_client(request
);
1851 /* Move any buffers on the active list that are no longer referenced
1852 * by the ringbuffer to the flushing/inactive lists as appropriate.
1854 while (!list_empty(&ring
->active_list
)) {
1855 struct drm_gem_object
*obj
;
1856 struct drm_i915_gem_object
*obj_priv
;
1858 obj_priv
= list_first_entry(&ring
->active_list
,
1859 struct drm_i915_gem_object
,
1862 if (!i915_seqno_passed(seqno
, obj_priv
->last_rendering_seqno
))
1865 obj
= &obj_priv
->base
;
1866 if (obj
->write_domain
!= 0)
1867 i915_gem_object_move_to_flushing(obj
);
1869 i915_gem_object_move_to_inactive(obj
);
1872 if (unlikely (dev_priv
->trace_irq_seqno
&&
1873 i915_seqno_passed(dev_priv
->trace_irq_seqno
, seqno
))) {
1874 ring
->user_irq_put(dev
, ring
);
1875 dev_priv
->trace_irq_seqno
= 0;
1878 WARN_ON(i915_verify_lists(dev
));
1882 i915_gem_retire_requests(struct drm_device
*dev
)
1884 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1886 if (!list_empty(&dev_priv
->mm
.deferred_free_list
)) {
1887 struct drm_i915_gem_object
*obj_priv
, *tmp
;
1889 /* We must be careful that during unbind() we do not
1890 * accidentally infinitely recurse into retire requests.
1892 * retire -> free -> unbind -> wait -> retire_ring
1894 list_for_each_entry_safe(obj_priv
, tmp
,
1895 &dev_priv
->mm
.deferred_free_list
,
1897 i915_gem_free_object_tail(&obj_priv
->base
);
1900 i915_gem_retire_requests_ring(dev
, &dev_priv
->render_ring
);
1902 i915_gem_retire_requests_ring(dev
, &dev_priv
->bsd_ring
);
1906 i915_gem_retire_work_handler(struct work_struct
*work
)
1908 drm_i915_private_t
*dev_priv
;
1909 struct drm_device
*dev
;
1911 dev_priv
= container_of(work
, drm_i915_private_t
,
1912 mm
.retire_work
.work
);
1913 dev
= dev_priv
->dev
;
1915 /* Come back later if the device is busy... */
1916 if (!mutex_trylock(&dev
->struct_mutex
)) {
1917 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, HZ
);
1921 i915_gem_retire_requests(dev
);
1923 if (!dev_priv
->mm
.suspended
&&
1924 (!list_empty(&dev_priv
->render_ring
.request_list
) ||
1926 !list_empty(&dev_priv
->bsd_ring
.request_list
))))
1927 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, HZ
);
1928 mutex_unlock(&dev
->struct_mutex
);
1932 i915_do_wait_request(struct drm_device
*dev
, uint32_t seqno
,
1933 bool interruptible
, struct intel_ring_buffer
*ring
)
1935 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1941 if (atomic_read(&dev_priv
->mm
.wedged
))
1944 if (ring
->outstanding_lazy_request
) {
1945 seqno
= i915_add_request(dev
, NULL
, NULL
, ring
);
1949 BUG_ON(seqno
== dev_priv
->next_seqno
);
1951 if (!i915_seqno_passed(ring
->get_seqno(dev
, ring
), seqno
)) {
1952 if (HAS_PCH_SPLIT(dev
))
1953 ier
= I915_READ(DEIER
) | I915_READ(GTIER
);
1955 ier
= I915_READ(IER
);
1957 DRM_ERROR("something (likely vbetool) disabled "
1958 "interrupts, re-enabling\n");
1959 i915_driver_irq_preinstall(dev
);
1960 i915_driver_irq_postinstall(dev
);
1963 trace_i915_gem_request_wait_begin(dev
, seqno
);
1965 ring
->waiting_gem_seqno
= seqno
;
1966 ring
->user_irq_get(dev
, ring
);
1968 ret
= wait_event_interruptible(ring
->irq_queue
,
1970 ring
->get_seqno(dev
, ring
), seqno
)
1971 || atomic_read(&dev_priv
->mm
.wedged
));
1973 wait_event(ring
->irq_queue
,
1975 ring
->get_seqno(dev
, ring
), seqno
)
1976 || atomic_read(&dev_priv
->mm
.wedged
));
1978 ring
->user_irq_put(dev
, ring
);
1979 ring
->waiting_gem_seqno
= 0;
1981 trace_i915_gem_request_wait_end(dev
, seqno
);
1983 if (atomic_read(&dev_priv
->mm
.wedged
))
1986 if (ret
&& ret
!= -ERESTARTSYS
)
1987 DRM_ERROR("%s returns %d (awaiting %d at %d, next %d)\n",
1988 __func__
, ret
, seqno
, ring
->get_seqno(dev
, ring
),
1989 dev_priv
->next_seqno
);
1991 /* Directly dispatch request retiring. While we have the work queue
1992 * to handle this, the waiter on a request often wants an associated
1993 * buffer to have made it to the inactive list, and we would need
1994 * a separate wait queue to handle that.
1997 i915_gem_retire_requests_ring(dev
, ring
);
2003 * Waits for a sequence number to be signaled, and cleans up the
2004 * request and object lists appropriately for that event.
2007 i915_wait_request(struct drm_device
*dev
, uint32_t seqno
,
2008 struct intel_ring_buffer
*ring
)
2010 return i915_do_wait_request(dev
, seqno
, 1, ring
);
2014 i915_gem_flush_ring(struct drm_device
*dev
,
2015 struct drm_file
*file_priv
,
2016 struct intel_ring_buffer
*ring
,
2017 uint32_t invalidate_domains
,
2018 uint32_t flush_domains
)
2020 ring
->flush(dev
, ring
, invalidate_domains
, flush_domains
);
2021 i915_gem_process_flushing_list(dev
, flush_domains
, ring
);
2025 i915_gem_flush(struct drm_device
*dev
,
2026 struct drm_file
*file_priv
,
2027 uint32_t invalidate_domains
,
2028 uint32_t flush_domains
,
2029 uint32_t flush_rings
)
2031 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2033 if (flush_domains
& I915_GEM_DOMAIN_CPU
)
2034 drm_agp_chipset_flush(dev
);
2036 if ((flush_domains
| invalidate_domains
) & I915_GEM_GPU_DOMAINS
) {
2037 if (flush_rings
& RING_RENDER
)
2038 i915_gem_flush_ring(dev
, file_priv
,
2039 &dev_priv
->render_ring
,
2040 invalidate_domains
, flush_domains
);
2041 if (flush_rings
& RING_BSD
)
2042 i915_gem_flush_ring(dev
, file_priv
,
2043 &dev_priv
->bsd_ring
,
2044 invalidate_domains
, flush_domains
);
2049 * Ensures that all rendering to the object has completed and the object is
2050 * safe to unbind from the GTT or access from the CPU.
2053 i915_gem_object_wait_rendering(struct drm_gem_object
*obj
,
2056 struct drm_device
*dev
= obj
->dev
;
2057 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2060 /* This function only exists to support waiting for existing rendering,
2061 * not for emitting required flushes.
2063 BUG_ON((obj
->write_domain
& I915_GEM_GPU_DOMAINS
) != 0);
2065 /* If there is rendering queued on the buffer being evicted, wait for
2068 if (obj_priv
->active
) {
2069 ret
= i915_do_wait_request(dev
,
2070 obj_priv
->last_rendering_seqno
,
2081 * Unbinds an object from the GTT aperture.
2084 i915_gem_object_unbind(struct drm_gem_object
*obj
)
2086 struct drm_device
*dev
= obj
->dev
;
2087 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2090 if (obj_priv
->gtt_space
== NULL
)
2093 if (obj_priv
->pin_count
!= 0) {
2094 DRM_ERROR("Attempting to unbind pinned buffer\n");
2098 /* blow away mappings if mapped through GTT */
2099 i915_gem_release_mmap(obj
);
2101 /* Move the object to the CPU domain to ensure that
2102 * any possible CPU writes while it's not in the GTT
2103 * are flushed when we go to remap it. This will
2104 * also ensure that all pending GPU writes are finished
2107 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
2108 if (ret
== -ERESTARTSYS
)
2110 /* Continue on if we fail due to EIO, the GPU is hung so we
2111 * should be safe and we need to cleanup or else we might
2112 * cause memory corruption through use-after-free.
2115 /* release the fence reg _after_ flushing */
2116 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
)
2117 i915_gem_clear_fence_reg(obj
);
2119 if (obj_priv
->agp_mem
!= NULL
) {
2120 drm_unbind_agp(obj_priv
->agp_mem
);
2121 drm_free_agp(obj_priv
->agp_mem
, obj
->size
/ PAGE_SIZE
);
2122 obj_priv
->agp_mem
= NULL
;
2125 i915_gem_object_put_pages(obj
);
2126 BUG_ON(obj_priv
->pages_refcount
);
2128 if (obj_priv
->gtt_space
) {
2129 atomic_dec(&dev
->gtt_count
);
2130 atomic_sub(obj
->size
, &dev
->gtt_memory
);
2132 drm_mm_put_block(obj_priv
->gtt_space
);
2133 obj_priv
->gtt_space
= NULL
;
2136 list_del_init(&obj_priv
->list
);
2138 if (i915_gem_object_is_purgeable(obj_priv
))
2139 i915_gem_object_truncate(obj
);
2141 trace_i915_gem_object_unbind(obj
);
2146 static int i915_ring_idle(struct drm_device
*dev
,
2147 struct intel_ring_buffer
*ring
)
2149 i915_gem_flush_ring(dev
, NULL
, ring
,
2150 I915_GEM_GPU_DOMAINS
, I915_GEM_GPU_DOMAINS
);
2151 return i915_wait_request(dev
,
2152 i915_gem_next_request_seqno(dev
, ring
),
2157 i915_gpu_idle(struct drm_device
*dev
)
2159 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2163 lists_empty
= (list_empty(&dev_priv
->mm
.flushing_list
) &&
2164 list_empty(&dev_priv
->render_ring
.active_list
) &&
2166 list_empty(&dev_priv
->bsd_ring
.active_list
)));
2170 /* Flush everything onto the inactive list. */
2171 ret
= i915_ring_idle(dev
, &dev_priv
->render_ring
);
2176 ret
= i915_ring_idle(dev
, &dev_priv
->bsd_ring
);
2185 i915_gem_object_get_pages(struct drm_gem_object
*obj
,
2188 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2190 struct address_space
*mapping
;
2191 struct inode
*inode
;
2194 BUG_ON(obj_priv
->pages_refcount
2195 == DRM_I915_GEM_OBJECT_MAX_PAGES_REFCOUNT
);
2197 if (obj_priv
->pages_refcount
++ != 0)
2200 /* Get the list of pages out of our struct file. They'll be pinned
2201 * at this point until we release them.
2203 page_count
= obj
->size
/ PAGE_SIZE
;
2204 BUG_ON(obj_priv
->pages
!= NULL
);
2205 obj_priv
->pages
= drm_calloc_large(page_count
, sizeof(struct page
*));
2206 if (obj_priv
->pages
== NULL
) {
2207 obj_priv
->pages_refcount
--;
2211 inode
= obj
->filp
->f_path
.dentry
->d_inode
;
2212 mapping
= inode
->i_mapping
;
2213 for (i
= 0; i
< page_count
; i
++) {
2214 page
= read_cache_page_gfp(mapping
, i
,
2222 obj_priv
->pages
[i
] = page
;
2225 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
)
2226 i915_gem_object_do_bit_17_swizzle(obj
);
2232 page_cache_release(obj_priv
->pages
[i
]);
2234 drm_free_large(obj_priv
->pages
);
2235 obj_priv
->pages
= NULL
;
2236 obj_priv
->pages_refcount
--;
2237 return PTR_ERR(page
);
2240 static void sandybridge_write_fence_reg(struct drm_i915_fence_reg
*reg
)
2242 struct drm_gem_object
*obj
= reg
->obj
;
2243 struct drm_device
*dev
= obj
->dev
;
2244 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2245 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2246 int regnum
= obj_priv
->fence_reg
;
2249 val
= (uint64_t)((obj_priv
->gtt_offset
+ obj
->size
- 4096) &
2251 val
|= obj_priv
->gtt_offset
& 0xfffff000;
2252 val
|= (uint64_t)((obj_priv
->stride
/ 128) - 1) <<
2253 SANDYBRIDGE_FENCE_PITCH_SHIFT
;
2255 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2256 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
2257 val
|= I965_FENCE_REG_VALID
;
2259 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0
+ (regnum
* 8), val
);
2262 static void i965_write_fence_reg(struct drm_i915_fence_reg
*reg
)
2264 struct drm_gem_object
*obj
= reg
->obj
;
2265 struct drm_device
*dev
= obj
->dev
;
2266 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2267 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2268 int regnum
= obj_priv
->fence_reg
;
2271 val
= (uint64_t)((obj_priv
->gtt_offset
+ obj
->size
- 4096) &
2273 val
|= obj_priv
->gtt_offset
& 0xfffff000;
2274 val
|= ((obj_priv
->stride
/ 128) - 1) << I965_FENCE_PITCH_SHIFT
;
2275 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2276 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
2277 val
|= I965_FENCE_REG_VALID
;
2279 I915_WRITE64(FENCE_REG_965_0
+ (regnum
* 8), val
);
2282 static void i915_write_fence_reg(struct drm_i915_fence_reg
*reg
)
2284 struct drm_gem_object
*obj
= reg
->obj
;
2285 struct drm_device
*dev
= obj
->dev
;
2286 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2287 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2288 int regnum
= obj_priv
->fence_reg
;
2290 uint32_t fence_reg
, val
;
2293 if ((obj_priv
->gtt_offset
& ~I915_FENCE_START_MASK
) ||
2294 (obj_priv
->gtt_offset
& (obj
->size
- 1))) {
2295 WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
2296 __func__
, obj_priv
->gtt_offset
, obj
->size
);
2300 if (obj_priv
->tiling_mode
== I915_TILING_Y
&&
2301 HAS_128_BYTE_Y_TILING(dev
))
2306 /* Note: pitch better be a power of two tile widths */
2307 pitch_val
= obj_priv
->stride
/ tile_width
;
2308 pitch_val
= ffs(pitch_val
) - 1;
2310 if (obj_priv
->tiling_mode
== I915_TILING_Y
&&
2311 HAS_128_BYTE_Y_TILING(dev
))
2312 WARN_ON(pitch_val
> I830_FENCE_MAX_PITCH_VAL
);
2314 WARN_ON(pitch_val
> I915_FENCE_MAX_PITCH_VAL
);
2316 val
= obj_priv
->gtt_offset
;
2317 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2318 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2319 val
|= I915_FENCE_SIZE_BITS(obj
->size
);
2320 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2321 val
|= I830_FENCE_REG_VALID
;
2324 fence_reg
= FENCE_REG_830_0
+ (regnum
* 4);
2326 fence_reg
= FENCE_REG_945_8
+ ((regnum
- 8) * 4);
2327 I915_WRITE(fence_reg
, val
);
2330 static void i830_write_fence_reg(struct drm_i915_fence_reg
*reg
)
2332 struct drm_gem_object
*obj
= reg
->obj
;
2333 struct drm_device
*dev
= obj
->dev
;
2334 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2335 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2336 int regnum
= obj_priv
->fence_reg
;
2339 uint32_t fence_size_bits
;
2341 if ((obj_priv
->gtt_offset
& ~I830_FENCE_START_MASK
) ||
2342 (obj_priv
->gtt_offset
& (obj
->size
- 1))) {
2343 WARN(1, "%s: object 0x%08x not 512K or size aligned\n",
2344 __func__
, obj_priv
->gtt_offset
);
2348 pitch_val
= obj_priv
->stride
/ 128;
2349 pitch_val
= ffs(pitch_val
) - 1;
2350 WARN_ON(pitch_val
> I830_FENCE_MAX_PITCH_VAL
);
2352 val
= obj_priv
->gtt_offset
;
2353 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2354 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2355 fence_size_bits
= I830_FENCE_SIZE_BITS(obj
->size
);
2356 WARN_ON(fence_size_bits
& ~0x00000f00);
2357 val
|= fence_size_bits
;
2358 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2359 val
|= I830_FENCE_REG_VALID
;
2361 I915_WRITE(FENCE_REG_830_0
+ (regnum
* 4), val
);
2364 static int i915_find_fence_reg(struct drm_device
*dev
,
2367 struct drm_i915_fence_reg
*reg
= NULL
;
2368 struct drm_i915_gem_object
*obj_priv
= NULL
;
2369 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2370 struct drm_gem_object
*obj
= NULL
;
2373 /* First try to find a free reg */
2375 for (i
= dev_priv
->fence_reg_start
; i
< dev_priv
->num_fence_regs
; i
++) {
2376 reg
= &dev_priv
->fence_regs
[i
];
2380 obj_priv
= to_intel_bo(reg
->obj
);
2381 if (!obj_priv
->pin_count
)
2388 /* None available, try to steal one or wait for a user to finish */
2389 i
= I915_FENCE_REG_NONE
;
2390 list_for_each_entry(reg
, &dev_priv
->mm
.fence_list
,
2393 obj_priv
= to_intel_bo(obj
);
2395 if (obj_priv
->pin_count
)
2399 i
= obj_priv
->fence_reg
;
2403 BUG_ON(i
== I915_FENCE_REG_NONE
);
2405 /* We only have a reference on obj from the active list. put_fence_reg
2406 * might drop that one, causing a use-after-free in it. So hold a
2407 * private reference to obj like the other callers of put_fence_reg
2408 * (set_tiling ioctl) do. */
2409 drm_gem_object_reference(obj
);
2410 ret
= i915_gem_object_put_fence_reg(obj
, interruptible
);
2411 drm_gem_object_unreference(obj
);
2419 * i915_gem_object_get_fence_reg - set up a fence reg for an object
2420 * @obj: object to map through a fence reg
2422 * When mapping objects through the GTT, userspace wants to be able to write
2423 * to them without having to worry about swizzling if the object is tiled.
2425 * This function walks the fence regs looking for a free one for @obj,
2426 * stealing one if it can't find any.
2428 * It then sets up the reg based on the object's properties: address, pitch
2429 * and tiling format.
2432 i915_gem_object_get_fence_reg(struct drm_gem_object
*obj
,
2435 struct drm_device
*dev
= obj
->dev
;
2436 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2437 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2438 struct drm_i915_fence_reg
*reg
= NULL
;
2441 /* Just update our place in the LRU if our fence is getting used. */
2442 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
) {
2443 reg
= &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
2444 list_move_tail(®
->lru_list
, &dev_priv
->mm
.fence_list
);
2448 switch (obj_priv
->tiling_mode
) {
2449 case I915_TILING_NONE
:
2450 WARN(1, "allocating a fence for non-tiled object?\n");
2453 if (!obj_priv
->stride
)
2455 WARN((obj_priv
->stride
& (512 - 1)),
2456 "object 0x%08x is X tiled but has non-512B pitch\n",
2457 obj_priv
->gtt_offset
);
2460 if (!obj_priv
->stride
)
2462 WARN((obj_priv
->stride
& (128 - 1)),
2463 "object 0x%08x is Y tiled but has non-128B pitch\n",
2464 obj_priv
->gtt_offset
);
2468 ret
= i915_find_fence_reg(dev
, interruptible
);
2472 obj_priv
->fence_reg
= ret
;
2473 reg
= &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
2474 list_add_tail(®
->lru_list
, &dev_priv
->mm
.fence_list
);
2478 switch (INTEL_INFO(dev
)->gen
) {
2480 sandybridge_write_fence_reg(reg
);
2484 i965_write_fence_reg(reg
);
2487 i915_write_fence_reg(reg
);
2490 i830_write_fence_reg(reg
);
2494 trace_i915_gem_object_get_fence(obj
, obj_priv
->fence_reg
,
2495 obj_priv
->tiling_mode
);
2501 * i915_gem_clear_fence_reg - clear out fence register info
2502 * @obj: object to clear
2504 * Zeroes out the fence register itself and clears out the associated
2505 * data structures in dev_priv and obj_priv.
2508 i915_gem_clear_fence_reg(struct drm_gem_object
*obj
)
2510 struct drm_device
*dev
= obj
->dev
;
2511 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2512 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2513 struct drm_i915_fence_reg
*reg
=
2514 &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
2517 switch (INTEL_INFO(dev
)->gen
) {
2519 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0
+
2520 (obj_priv
->fence_reg
* 8), 0);
2524 I915_WRITE64(FENCE_REG_965_0
+ (obj_priv
->fence_reg
* 8), 0);
2527 if (obj_priv
->fence_reg
>= 8)
2528 fence_reg
= FENCE_REG_945_8
+ (obj_priv
->fence_reg
- 8) * 4;
2531 fence_reg
= FENCE_REG_830_0
+ obj_priv
->fence_reg
* 4;
2533 I915_WRITE(fence_reg
, 0);
2538 obj_priv
->fence_reg
= I915_FENCE_REG_NONE
;
2539 list_del_init(®
->lru_list
);
2543 * i915_gem_object_put_fence_reg - waits on outstanding fenced access
2544 * to the buffer to finish, and then resets the fence register.
2545 * @obj: tiled object holding a fence register.
2546 * @bool: whether the wait upon the fence is interruptible
2548 * Zeroes out the fence register itself and clears out the associated
2549 * data structures in dev_priv and obj_priv.
2552 i915_gem_object_put_fence_reg(struct drm_gem_object
*obj
,
2555 struct drm_device
*dev
= obj
->dev
;
2556 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2557 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2558 struct drm_i915_fence_reg
*reg
;
2560 if (obj_priv
->fence_reg
== I915_FENCE_REG_NONE
)
2563 /* If we've changed tiling, GTT-mappings of the object
2564 * need to re-fault to ensure that the correct fence register
2565 * setup is in place.
2567 i915_gem_release_mmap(obj
);
2569 /* On the i915, GPU access to tiled buffers is via a fence,
2570 * therefore we must wait for any outstanding access to complete
2571 * before clearing the fence.
2573 reg
= &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
2577 ret
= i915_gem_object_flush_gpu_write_domain(obj
, true);
2581 ret
= i915_gem_object_wait_rendering(obj
, interruptible
);
2588 i915_gem_object_flush_gtt_write_domain(obj
);
2589 i915_gem_clear_fence_reg(obj
);
2595 * Finds free space in the GTT aperture and binds the object there.
2598 i915_gem_object_bind_to_gtt(struct drm_gem_object
*obj
, unsigned alignment
)
2600 struct drm_device
*dev
= obj
->dev
;
2601 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2602 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2603 struct drm_mm_node
*free_space
;
2604 gfp_t gfpmask
= __GFP_NORETRY
| __GFP_NOWARN
;
2607 if (obj_priv
->madv
!= I915_MADV_WILLNEED
) {
2608 DRM_ERROR("Attempting to bind a purgeable object\n");
2613 alignment
= i915_gem_get_gtt_alignment(obj
);
2614 if (alignment
& (i915_gem_get_gtt_alignment(obj
) - 1)) {
2615 DRM_ERROR("Invalid object alignment requested %u\n", alignment
);
2619 /* If the object is bigger than the entire aperture, reject it early
2620 * before evicting everything in a vain attempt to find space.
2622 if (obj
->size
> dev
->gtt_total
) {
2623 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2628 free_space
= drm_mm_search_free(&dev_priv
->mm
.gtt_space
,
2629 obj
->size
, alignment
, 0);
2630 if (free_space
!= NULL
) {
2631 obj_priv
->gtt_space
= drm_mm_get_block(free_space
, obj
->size
,
2633 if (obj_priv
->gtt_space
!= NULL
)
2634 obj_priv
->gtt_offset
= obj_priv
->gtt_space
->start
;
2636 if (obj_priv
->gtt_space
== NULL
) {
2637 /* If the gtt is empty and we're still having trouble
2638 * fitting our object in, we're out of memory.
2640 ret
= i915_gem_evict_something(dev
, obj
->size
, alignment
);
2647 ret
= i915_gem_object_get_pages(obj
, gfpmask
);
2649 drm_mm_put_block(obj_priv
->gtt_space
);
2650 obj_priv
->gtt_space
= NULL
;
2652 if (ret
== -ENOMEM
) {
2653 /* first try to clear up some space from the GTT */
2654 ret
= i915_gem_evict_something(dev
, obj
->size
,
2657 /* now try to shrink everyone else */
2672 /* Create an AGP memory structure pointing at our pages, and bind it
2675 obj_priv
->agp_mem
= drm_agp_bind_pages(dev
,
2677 obj
->size
>> PAGE_SHIFT
,
2678 obj_priv
->gtt_offset
,
2679 obj_priv
->agp_type
);
2680 if (obj_priv
->agp_mem
== NULL
) {
2681 i915_gem_object_put_pages(obj
);
2682 drm_mm_put_block(obj_priv
->gtt_space
);
2683 obj_priv
->gtt_space
= NULL
;
2685 ret
= i915_gem_evict_something(dev
, obj
->size
, alignment
);
2691 atomic_inc(&dev
->gtt_count
);
2692 atomic_add(obj
->size
, &dev
->gtt_memory
);
2694 /* keep track of bounds object by adding it to the inactive list */
2695 list_add_tail(&obj_priv
->list
, &dev_priv
->mm
.inactive_list
);
2697 /* Assert that the object is not currently in any GPU domain. As it
2698 * wasn't in the GTT, there shouldn't be any way it could have been in
2701 BUG_ON(obj
->read_domains
& I915_GEM_GPU_DOMAINS
);
2702 BUG_ON(obj
->write_domain
& I915_GEM_GPU_DOMAINS
);
2704 trace_i915_gem_object_bind(obj
, obj_priv
->gtt_offset
);
2710 i915_gem_clflush_object(struct drm_gem_object
*obj
)
2712 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2714 /* If we don't have a page list set up, then we're not pinned
2715 * to GPU, and we can ignore the cache flush because it'll happen
2716 * again at bind time.
2718 if (obj_priv
->pages
== NULL
)
2721 trace_i915_gem_object_clflush(obj
);
2723 drm_clflush_pages(obj_priv
->pages
, obj
->size
/ PAGE_SIZE
);
2726 /** Flushes any GPU write domain for the object if it's dirty. */
2728 i915_gem_object_flush_gpu_write_domain(struct drm_gem_object
*obj
,
2731 struct drm_device
*dev
= obj
->dev
;
2732 uint32_t old_write_domain
;
2734 if ((obj
->write_domain
& I915_GEM_GPU_DOMAINS
) == 0)
2737 /* Queue the GPU write cache flushing we need. */
2738 old_write_domain
= obj
->write_domain
;
2739 i915_gem_flush_ring(dev
, NULL
,
2740 to_intel_bo(obj
)->ring
,
2741 0, obj
->write_domain
);
2742 BUG_ON(obj
->write_domain
);
2744 trace_i915_gem_object_change_domain(obj
,
2751 return i915_gem_object_wait_rendering(obj
, true);
2754 /** Flushes the GTT write domain for the object if it's dirty. */
2756 i915_gem_object_flush_gtt_write_domain(struct drm_gem_object
*obj
)
2758 uint32_t old_write_domain
;
2760 if (obj
->write_domain
!= I915_GEM_DOMAIN_GTT
)
2763 /* No actual flushing is required for the GTT write domain. Writes
2764 * to it immediately go to main memory as far as we know, so there's
2765 * no chipset flush. It also doesn't land in render cache.
2767 old_write_domain
= obj
->write_domain
;
2768 obj
->write_domain
= 0;
2770 trace_i915_gem_object_change_domain(obj
,
2775 /** Flushes the CPU write domain for the object if it's dirty. */
2777 i915_gem_object_flush_cpu_write_domain(struct drm_gem_object
*obj
)
2779 struct drm_device
*dev
= obj
->dev
;
2780 uint32_t old_write_domain
;
2782 if (obj
->write_domain
!= I915_GEM_DOMAIN_CPU
)
2785 i915_gem_clflush_object(obj
);
2786 drm_agp_chipset_flush(dev
);
2787 old_write_domain
= obj
->write_domain
;
2788 obj
->write_domain
= 0;
2790 trace_i915_gem_object_change_domain(obj
,
2796 * Moves a single object to the GTT read, and possibly write domain.
2798 * This function returns when the move is complete, including waiting on
2802 i915_gem_object_set_to_gtt_domain(struct drm_gem_object
*obj
, int write
)
2804 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2805 uint32_t old_write_domain
, old_read_domains
;
2808 /* Not valid to be called on unbound objects. */
2809 if (obj_priv
->gtt_space
== NULL
)
2812 ret
= i915_gem_object_flush_gpu_write_domain(obj
, false);
2816 i915_gem_object_flush_cpu_write_domain(obj
);
2819 ret
= i915_gem_object_wait_rendering(obj
, true);
2824 old_write_domain
= obj
->write_domain
;
2825 old_read_domains
= obj
->read_domains
;
2827 /* It should now be out of any other write domains, and we can update
2828 * the domain values for our changes.
2830 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
2831 obj
->read_domains
|= I915_GEM_DOMAIN_GTT
;
2833 obj
->read_domains
= I915_GEM_DOMAIN_GTT
;
2834 obj
->write_domain
= I915_GEM_DOMAIN_GTT
;
2835 obj_priv
->dirty
= 1;
2838 trace_i915_gem_object_change_domain(obj
,
2846 * Prepare buffer for display plane. Use uninterruptible for possible flush
2847 * wait, as in modesetting process we're not supposed to be interrupted.
2850 i915_gem_object_set_to_display_plane(struct drm_gem_object
*obj
,
2853 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2854 uint32_t old_read_domains
;
2857 /* Not valid to be called on unbound objects. */
2858 if (obj_priv
->gtt_space
== NULL
)
2861 ret
= i915_gem_object_flush_gpu_write_domain(obj
, true);
2865 /* Currently, we are always called from an non-interruptible context. */
2867 ret
= i915_gem_object_wait_rendering(obj
, false);
2872 i915_gem_object_flush_cpu_write_domain(obj
);
2874 old_read_domains
= obj
->read_domains
;
2875 obj
->read_domains
|= I915_GEM_DOMAIN_GTT
;
2877 trace_i915_gem_object_change_domain(obj
,
2885 * Moves a single object to the CPU read, and possibly write domain.
2887 * This function returns when the move is complete, including waiting on
2891 i915_gem_object_set_to_cpu_domain(struct drm_gem_object
*obj
, int write
)
2893 uint32_t old_write_domain
, old_read_domains
;
2896 ret
= i915_gem_object_flush_gpu_write_domain(obj
, false);
2900 i915_gem_object_flush_gtt_write_domain(obj
);
2902 /* If we have a partially-valid cache of the object in the CPU,
2903 * finish invalidating it and free the per-page flags.
2905 i915_gem_object_set_to_full_cpu_read_domain(obj
);
2908 ret
= i915_gem_object_wait_rendering(obj
, true);
2913 old_write_domain
= obj
->write_domain
;
2914 old_read_domains
= obj
->read_domains
;
2916 /* Flush the CPU cache if it's still invalid. */
2917 if ((obj
->read_domains
& I915_GEM_DOMAIN_CPU
) == 0) {
2918 i915_gem_clflush_object(obj
);
2920 obj
->read_domains
|= I915_GEM_DOMAIN_CPU
;
2923 /* It should now be out of any other write domains, and we can update
2924 * the domain values for our changes.
2926 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
2928 /* If we're writing through the CPU, then the GPU read domains will
2929 * need to be invalidated at next use.
2932 obj
->read_domains
= I915_GEM_DOMAIN_CPU
;
2933 obj
->write_domain
= I915_GEM_DOMAIN_CPU
;
2936 trace_i915_gem_object_change_domain(obj
,
2944 * Set the next domain for the specified object. This
2945 * may not actually perform the necessary flushing/invaliding though,
2946 * as that may want to be batched with other set_domain operations
2948 * This is (we hope) the only really tricky part of gem. The goal
2949 * is fairly simple -- track which caches hold bits of the object
2950 * and make sure they remain coherent. A few concrete examples may
2951 * help to explain how it works. For shorthand, we use the notation
2952 * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
2953 * a pair of read and write domain masks.
2955 * Case 1: the batch buffer
2961 * 5. Unmapped from GTT
2964 * Let's take these a step at a time
2967 * Pages allocated from the kernel may still have
2968 * cache contents, so we set them to (CPU, CPU) always.
2969 * 2. Written by CPU (using pwrite)
2970 * The pwrite function calls set_domain (CPU, CPU) and
2971 * this function does nothing (as nothing changes)
2973 * This function asserts that the object is not
2974 * currently in any GPU-based read or write domains
2976 * i915_gem_execbuffer calls set_domain (COMMAND, 0).
2977 * As write_domain is zero, this function adds in the
2978 * current read domains (CPU+COMMAND, 0).
2979 * flush_domains is set to CPU.
2980 * invalidate_domains is set to COMMAND
2981 * clflush is run to get data out of the CPU caches
2982 * then i915_dev_set_domain calls i915_gem_flush to
2983 * emit an MI_FLUSH and drm_agp_chipset_flush
2984 * 5. Unmapped from GTT
2985 * i915_gem_object_unbind calls set_domain (CPU, CPU)
2986 * flush_domains and invalidate_domains end up both zero
2987 * so no flushing/invalidating happens
2991 * Case 2: The shared render buffer
2995 * 3. Read/written by GPU
2996 * 4. set_domain to (CPU,CPU)
2997 * 5. Read/written by CPU
2998 * 6. Read/written by GPU
3001 * Same as last example, (CPU, CPU)
3003 * Nothing changes (assertions find that it is not in the GPU)
3004 * 3. Read/written by GPU
3005 * execbuffer calls set_domain (RENDER, RENDER)
3006 * flush_domains gets CPU
3007 * invalidate_domains gets GPU
3009 * MI_FLUSH and drm_agp_chipset_flush
3010 * 4. set_domain (CPU, CPU)
3011 * flush_domains gets GPU
3012 * invalidate_domains gets CPU
3013 * wait_rendering (obj) to make sure all drawing is complete.
3014 * This will include an MI_FLUSH to get the data from GPU
3016 * clflush (obj) to invalidate the CPU cache
3017 * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
3018 * 5. Read/written by CPU
3019 * cache lines are loaded and dirtied
3020 * 6. Read written by GPU
3021 * Same as last GPU access
3023 * Case 3: The constant buffer
3028 * 4. Updated (written) by CPU again
3037 * flush_domains = CPU
3038 * invalidate_domains = RENDER
3041 * drm_agp_chipset_flush
3042 * 4. Updated (written) by CPU again
3044 * flush_domains = 0 (no previous write domain)
3045 * invalidate_domains = 0 (no new read domains)
3048 * flush_domains = CPU
3049 * invalidate_domains = RENDER
3052 * drm_agp_chipset_flush
3055 i915_gem_object_set_to_gpu_domain(struct drm_gem_object
*obj
)
3057 struct drm_device
*dev
= obj
->dev
;
3058 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3059 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
3060 uint32_t invalidate_domains
= 0;
3061 uint32_t flush_domains
= 0;
3062 uint32_t old_read_domains
;
3064 BUG_ON(obj
->pending_read_domains
& I915_GEM_DOMAIN_CPU
);
3065 BUG_ON(obj
->pending_write_domain
== I915_GEM_DOMAIN_CPU
);
3067 intel_mark_busy(dev
, obj
);
3070 * If the object isn't moving to a new write domain,
3071 * let the object stay in multiple read domains
3073 if (obj
->pending_write_domain
== 0)
3074 obj
->pending_read_domains
|= obj
->read_domains
;
3076 obj_priv
->dirty
= 1;
3079 * Flush the current write domain if
3080 * the new read domains don't match. Invalidate
3081 * any read domains which differ from the old
3084 if (obj
->write_domain
&&
3085 obj
->write_domain
!= obj
->pending_read_domains
) {
3086 flush_domains
|= obj
->write_domain
;
3087 invalidate_domains
|=
3088 obj
->pending_read_domains
& ~obj
->write_domain
;
3091 * Invalidate any read caches which may have
3092 * stale data. That is, any new read domains.
3094 invalidate_domains
|= obj
->pending_read_domains
& ~obj
->read_domains
;
3095 if ((flush_domains
| invalidate_domains
) & I915_GEM_DOMAIN_CPU
)
3096 i915_gem_clflush_object(obj
);
3098 old_read_domains
= obj
->read_domains
;
3100 /* The actual obj->write_domain will be updated with
3101 * pending_write_domain after we emit the accumulated flush for all
3102 * of our domain changes in execbuffers (which clears objects'
3103 * write_domains). So if we have a current write domain that we
3104 * aren't changing, set pending_write_domain to that.
3106 if (flush_domains
== 0 && obj
->pending_write_domain
== 0)
3107 obj
->pending_write_domain
= obj
->write_domain
;
3108 obj
->read_domains
= obj
->pending_read_domains
;
3110 dev
->invalidate_domains
|= invalidate_domains
;
3111 dev
->flush_domains
|= flush_domains
;
3113 dev_priv
->mm
.flush_rings
|= obj_priv
->ring
->id
;
3115 trace_i915_gem_object_change_domain(obj
,
3121 * Moves the object from a partially CPU read to a full one.
3123 * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3124 * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
3127 i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object
*obj
)
3129 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
3131 if (!obj_priv
->page_cpu_valid
)
3134 /* If we're partially in the CPU read domain, finish moving it in.
3136 if (obj
->read_domains
& I915_GEM_DOMAIN_CPU
) {
3139 for (i
= 0; i
<= (obj
->size
- 1) / PAGE_SIZE
; i
++) {
3140 if (obj_priv
->page_cpu_valid
[i
])
3142 drm_clflush_pages(obj_priv
->pages
+ i
, 1);
3146 /* Free the page_cpu_valid mappings which are now stale, whether
3147 * or not we've got I915_GEM_DOMAIN_CPU.
3149 kfree(obj_priv
->page_cpu_valid
);
3150 obj_priv
->page_cpu_valid
= NULL
;
3154 * Set the CPU read domain on a range of the object.
3156 * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3157 * not entirely valid. The page_cpu_valid member of the object flags which
3158 * pages have been flushed, and will be respected by
3159 * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3160 * of the whole object.
3162 * This function returns when the move is complete, including waiting on
3166 i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object
*obj
,
3167 uint64_t offset
, uint64_t size
)
3169 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
3170 uint32_t old_read_domains
;
3173 if (offset
== 0 && size
== obj
->size
)
3174 return i915_gem_object_set_to_cpu_domain(obj
, 0);
3176 ret
= i915_gem_object_flush_gpu_write_domain(obj
, false);
3179 i915_gem_object_flush_gtt_write_domain(obj
);
3181 /* If we're already fully in the CPU read domain, we're done. */
3182 if (obj_priv
->page_cpu_valid
== NULL
&&
3183 (obj
->read_domains
& I915_GEM_DOMAIN_CPU
) != 0)
3186 /* Otherwise, create/clear the per-page CPU read domain flag if we're
3187 * newly adding I915_GEM_DOMAIN_CPU
3189 if (obj_priv
->page_cpu_valid
== NULL
) {
3190 obj_priv
->page_cpu_valid
= kzalloc(obj
->size
/ PAGE_SIZE
,
3192 if (obj_priv
->page_cpu_valid
== NULL
)
3194 } else if ((obj
->read_domains
& I915_GEM_DOMAIN_CPU
) == 0)
3195 memset(obj_priv
->page_cpu_valid
, 0, obj
->size
/ PAGE_SIZE
);
3197 /* Flush the cache on any pages that are still invalid from the CPU's
3200 for (i
= offset
/ PAGE_SIZE
; i
<= (offset
+ size
- 1) / PAGE_SIZE
;
3202 if (obj_priv
->page_cpu_valid
[i
])
3205 drm_clflush_pages(obj_priv
->pages
+ i
, 1);
3207 obj_priv
->page_cpu_valid
[i
] = 1;
3210 /* It should now be out of any other write domains, and we can update
3211 * the domain values for our changes.
3213 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
3215 old_read_domains
= obj
->read_domains
;
3216 obj
->read_domains
|= I915_GEM_DOMAIN_CPU
;
3218 trace_i915_gem_object_change_domain(obj
,
3226 * Pin an object to the GTT and evaluate the relocations landing in it.
3229 i915_gem_object_pin_and_relocate(struct drm_gem_object
*obj
,
3230 struct drm_file
*file_priv
,
3231 struct drm_i915_gem_exec_object2
*entry
,
3232 struct drm_i915_gem_relocation_entry
*relocs
)
3234 struct drm_device
*dev
= obj
->dev
;
3235 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3236 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
3238 void __iomem
*reloc_page
;
3241 need_fence
= entry
->flags
& EXEC_OBJECT_NEEDS_FENCE
&&
3242 obj_priv
->tiling_mode
!= I915_TILING_NONE
;
3244 /* Check fence reg constraints and rebind if necessary */
3246 !i915_gem_object_fence_offset_ok(obj
,
3247 obj_priv
->tiling_mode
)) {
3248 ret
= i915_gem_object_unbind(obj
);
3253 /* Choose the GTT offset for our buffer and put it there. */
3254 ret
= i915_gem_object_pin(obj
, (uint32_t) entry
->alignment
);
3259 * Pre-965 chips need a fence register set up in order to
3260 * properly handle blits to/from tiled surfaces.
3263 ret
= i915_gem_object_get_fence_reg(obj
, true);
3265 i915_gem_object_unpin(obj
);
3269 dev_priv
->fence_regs
[obj_priv
->fence_reg
].gpu
= true;
3272 entry
->offset
= obj_priv
->gtt_offset
;
3274 /* Apply the relocations, using the GTT aperture to avoid cache
3275 * flushing requirements.
3277 for (i
= 0; i
< entry
->relocation_count
; i
++) {
3278 struct drm_i915_gem_relocation_entry
*reloc
= &relocs
[i
];
3279 struct drm_gem_object
*target_obj
;
3280 struct drm_i915_gem_object
*target_obj_priv
;
3281 uint32_t reloc_val
, reloc_offset
;
3282 uint32_t __iomem
*reloc_entry
;
3284 target_obj
= drm_gem_object_lookup(obj
->dev
, file_priv
,
3285 reloc
->target_handle
);
3286 if (target_obj
== NULL
) {
3287 i915_gem_object_unpin(obj
);
3290 target_obj_priv
= to_intel_bo(target_obj
);
3293 DRM_INFO("%s: obj %p offset %08x target %d "
3294 "read %08x write %08x gtt %08x "
3295 "presumed %08x delta %08x\n",
3298 (int) reloc
->offset
,
3299 (int) reloc
->target_handle
,
3300 (int) reloc
->read_domains
,
3301 (int) reloc
->write_domain
,
3302 (int) target_obj_priv
->gtt_offset
,
3303 (int) reloc
->presumed_offset
,
3307 /* The target buffer should have appeared before us in the
3308 * exec_object list, so it should have a GTT space bound by now.
3310 if (target_obj_priv
->gtt_space
== NULL
) {
3311 DRM_ERROR("No GTT space found for object %d\n",
3312 reloc
->target_handle
);
3313 drm_gem_object_unreference(target_obj
);
3314 i915_gem_object_unpin(obj
);
3318 /* Validate that the target is in a valid r/w GPU domain */
3319 if (reloc
->write_domain
& (reloc
->write_domain
- 1)) {
3320 DRM_ERROR("reloc with multiple write domains: "
3321 "obj %p target %d offset %d "
3322 "read %08x write %08x",
3323 obj
, reloc
->target_handle
,
3324 (int) reloc
->offset
,
3325 reloc
->read_domains
,
3326 reloc
->write_domain
);
3329 if (reloc
->write_domain
& I915_GEM_DOMAIN_CPU
||
3330 reloc
->read_domains
& I915_GEM_DOMAIN_CPU
) {
3331 DRM_ERROR("reloc with read/write CPU domains: "
3332 "obj %p target %d offset %d "
3333 "read %08x write %08x",
3334 obj
, reloc
->target_handle
,
3335 (int) reloc
->offset
,
3336 reloc
->read_domains
,
3337 reloc
->write_domain
);
3338 drm_gem_object_unreference(target_obj
);
3339 i915_gem_object_unpin(obj
);
3342 if (reloc
->write_domain
&& target_obj
->pending_write_domain
&&
3343 reloc
->write_domain
!= target_obj
->pending_write_domain
) {
3344 DRM_ERROR("Write domain conflict: "
3345 "obj %p target %d offset %d "
3346 "new %08x old %08x\n",
3347 obj
, reloc
->target_handle
,
3348 (int) reloc
->offset
,
3349 reloc
->write_domain
,
3350 target_obj
->pending_write_domain
);
3351 drm_gem_object_unreference(target_obj
);
3352 i915_gem_object_unpin(obj
);
3356 target_obj
->pending_read_domains
|= reloc
->read_domains
;
3357 target_obj
->pending_write_domain
|= reloc
->write_domain
;
3359 /* If the relocation already has the right value in it, no
3360 * more work needs to be done.
3362 if (target_obj_priv
->gtt_offset
== reloc
->presumed_offset
) {
3363 drm_gem_object_unreference(target_obj
);
3367 /* Check that the relocation address is valid... */
3368 if (reloc
->offset
> obj
->size
- 4) {
3369 DRM_ERROR("Relocation beyond object bounds: "
3370 "obj %p target %d offset %d size %d.\n",
3371 obj
, reloc
->target_handle
,
3372 (int) reloc
->offset
, (int) obj
->size
);
3373 drm_gem_object_unreference(target_obj
);
3374 i915_gem_object_unpin(obj
);
3377 if (reloc
->offset
& 3) {
3378 DRM_ERROR("Relocation not 4-byte aligned: "
3379 "obj %p target %d offset %d.\n",
3380 obj
, reloc
->target_handle
,
3381 (int) reloc
->offset
);
3382 drm_gem_object_unreference(target_obj
);
3383 i915_gem_object_unpin(obj
);
3387 /* and points to somewhere within the target object. */
3388 if (reloc
->delta
>= target_obj
->size
) {
3389 DRM_ERROR("Relocation beyond target object bounds: "
3390 "obj %p target %d delta %d size %d.\n",
3391 obj
, reloc
->target_handle
,
3392 (int) reloc
->delta
, (int) target_obj
->size
);
3393 drm_gem_object_unreference(target_obj
);
3394 i915_gem_object_unpin(obj
);
3398 ret
= i915_gem_object_set_to_gtt_domain(obj
, 1);
3400 drm_gem_object_unreference(target_obj
);
3401 i915_gem_object_unpin(obj
);
3405 /* Map the page containing the relocation we're going to
3408 reloc_offset
= obj_priv
->gtt_offset
+ reloc
->offset
;
3409 reloc_page
= io_mapping_map_atomic_wc(dev_priv
->mm
.gtt_mapping
,
3413 reloc_entry
= (uint32_t __iomem
*)(reloc_page
+
3414 (reloc_offset
& (PAGE_SIZE
- 1)));
3415 reloc_val
= target_obj_priv
->gtt_offset
+ reloc
->delta
;
3417 writel(reloc_val
, reloc_entry
);
3418 io_mapping_unmap_atomic(reloc_page
, KM_USER0
);
3420 /* The updated presumed offset for this entry will be
3421 * copied back out to the user.
3423 reloc
->presumed_offset
= target_obj_priv
->gtt_offset
;
3425 drm_gem_object_unreference(target_obj
);
3431 /* Throttle our rendering by waiting until the ring has completed our requests
3432 * emitted over 20 msec ago.
3434 * Note that if we were to use the current jiffies each time around the loop,
3435 * we wouldn't escape the function with any frames outstanding if the time to
3436 * render a frame was over 20ms.
3438 * This should get us reasonable parallelism between CPU and GPU but also
3439 * relatively low latency when blocking on a particular request to finish.
3442 i915_gem_ring_throttle(struct drm_device
*dev
, struct drm_file
*file
)
3444 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3445 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
3446 unsigned long recent_enough
= jiffies
- msecs_to_jiffies(20);
3447 struct drm_i915_gem_request
*request
;
3448 struct intel_ring_buffer
*ring
= NULL
;
3452 spin_lock(&file_priv
->mm
.lock
);
3453 list_for_each_entry(request
, &file_priv
->mm
.request_list
, client_list
) {
3454 if (time_after_eq(request
->emitted_jiffies
, recent_enough
))
3457 ring
= request
->ring
;
3458 seqno
= request
->seqno
;
3460 spin_unlock(&file_priv
->mm
.lock
);
3466 if (!i915_seqno_passed(ring
->get_seqno(dev
, ring
), seqno
)) {
3467 /* And wait for the seqno passing without holding any locks and
3468 * causing extra latency for others. This is safe as the irq
3469 * generation is designed to be run atomically and so is
3472 ring
->user_irq_get(dev
, ring
);
3473 ret
= wait_event_interruptible(ring
->irq_queue
,
3474 i915_seqno_passed(ring
->get_seqno(dev
, ring
), seqno
)
3475 || atomic_read(&dev_priv
->mm
.wedged
));
3476 ring
->user_irq_put(dev
, ring
);
3478 if (ret
== 0 && atomic_read(&dev_priv
->mm
.wedged
))
3483 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, 0);
3489 i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object2
*exec_list
,
3490 uint32_t buffer_count
,
3491 struct drm_i915_gem_relocation_entry
**relocs
)
3493 uint32_t reloc_count
= 0, reloc_index
= 0, i
;
3497 for (i
= 0; i
< buffer_count
; i
++) {
3498 if (reloc_count
+ exec_list
[i
].relocation_count
< reloc_count
)
3500 reloc_count
+= exec_list
[i
].relocation_count
;
3503 *relocs
= drm_calloc_large(reloc_count
, sizeof(**relocs
));
3504 if (*relocs
== NULL
) {
3505 DRM_ERROR("failed to alloc relocs, count %d\n", reloc_count
);
3509 for (i
= 0; i
< buffer_count
; i
++) {
3510 struct drm_i915_gem_relocation_entry __user
*user_relocs
;
3512 user_relocs
= (void __user
*)(uintptr_t)exec_list
[i
].relocs_ptr
;
3514 ret
= copy_from_user(&(*relocs
)[reloc_index
],
3516 exec_list
[i
].relocation_count
*
3519 drm_free_large(*relocs
);
3524 reloc_index
+= exec_list
[i
].relocation_count
;
3531 i915_gem_put_relocs_to_user(struct drm_i915_gem_exec_object2
*exec_list
,
3532 uint32_t buffer_count
,
3533 struct drm_i915_gem_relocation_entry
*relocs
)
3535 uint32_t reloc_count
= 0, i
;
3541 for (i
= 0; i
< buffer_count
; i
++) {
3542 struct drm_i915_gem_relocation_entry __user
*user_relocs
;
3545 user_relocs
= (void __user
*)(uintptr_t)exec_list
[i
].relocs_ptr
;
3547 unwritten
= copy_to_user(user_relocs
,
3548 &relocs
[reloc_count
],
3549 exec_list
[i
].relocation_count
*
3557 reloc_count
+= exec_list
[i
].relocation_count
;
3561 drm_free_large(relocs
);
3567 i915_gem_check_execbuffer (struct drm_i915_gem_execbuffer2
*exec
,
3568 uint64_t exec_offset
)
3570 uint32_t exec_start
, exec_len
;
3572 exec_start
= (uint32_t) exec_offset
+ exec
->batch_start_offset
;
3573 exec_len
= (uint32_t) exec
->batch_len
;
3575 if ((exec_start
| exec_len
) & 0x7)
3585 i915_gem_wait_for_pending_flip(struct drm_device
*dev
,
3586 struct drm_gem_object
**object_list
,
3589 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3590 struct drm_i915_gem_object
*obj_priv
;
3595 prepare_to_wait(&dev_priv
->pending_flip_queue
,
3596 &wait
, TASK_INTERRUPTIBLE
);
3597 for (i
= 0; i
< count
; i
++) {
3598 obj_priv
= to_intel_bo(object_list
[i
]);
3599 if (atomic_read(&obj_priv
->pending_flip
) > 0)
3605 if (!signal_pending(current
)) {
3606 mutex_unlock(&dev
->struct_mutex
);
3608 mutex_lock(&dev
->struct_mutex
);
3614 finish_wait(&dev_priv
->pending_flip_queue
, &wait
);
3620 i915_gem_do_execbuffer(struct drm_device
*dev
, void *data
,
3621 struct drm_file
*file_priv
,
3622 struct drm_i915_gem_execbuffer2
*args
,
3623 struct drm_i915_gem_exec_object2
*exec_list
)
3625 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3626 struct drm_gem_object
**object_list
= NULL
;
3627 struct drm_gem_object
*batch_obj
;
3628 struct drm_i915_gem_object
*obj_priv
;
3629 struct drm_clip_rect
*cliprects
= NULL
;
3630 struct drm_i915_gem_relocation_entry
*relocs
= NULL
;
3631 struct drm_i915_gem_request
*request
= NULL
;
3632 int ret
, ret2
, i
, pinned
= 0;
3633 uint64_t exec_offset
;
3634 uint32_t reloc_index
;
3635 int pin_tries
, flips
;
3637 struct intel_ring_buffer
*ring
= NULL
;
3639 ret
= i915_gem_check_is_wedged(dev
);
3644 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3645 (int) args
->buffers_ptr
, args
->buffer_count
, args
->batch_len
);
3647 if (args
->flags
& I915_EXEC_BSD
) {
3648 if (!HAS_BSD(dev
)) {
3649 DRM_ERROR("execbuf with wrong flag\n");
3652 ring
= &dev_priv
->bsd_ring
;
3654 ring
= &dev_priv
->render_ring
;
3657 if (args
->buffer_count
< 1) {
3658 DRM_ERROR("execbuf with %d buffers\n", args
->buffer_count
);
3661 object_list
= drm_malloc_ab(sizeof(*object_list
), args
->buffer_count
);
3662 if (object_list
== NULL
) {
3663 DRM_ERROR("Failed to allocate object list for %d buffers\n",
3664 args
->buffer_count
);
3669 if (args
->num_cliprects
!= 0) {
3670 cliprects
= kcalloc(args
->num_cliprects
, sizeof(*cliprects
),
3672 if (cliprects
== NULL
) {
3677 ret
= copy_from_user(cliprects
,
3678 (struct drm_clip_rect __user
*)
3679 (uintptr_t) args
->cliprects_ptr
,
3680 sizeof(*cliprects
) * args
->num_cliprects
);
3682 DRM_ERROR("copy %d cliprects failed: %d\n",
3683 args
->num_cliprects
, ret
);
3689 request
= kzalloc(sizeof(*request
), GFP_KERNEL
);
3690 if (request
== NULL
) {
3695 ret
= i915_gem_get_relocs_from_user(exec_list
, args
->buffer_count
,
3700 ret
= i915_mutex_lock_interruptible(dev
);
3704 if (dev_priv
->mm
.suspended
) {
3705 mutex_unlock(&dev
->struct_mutex
);
3710 /* Look up object handles */
3712 for (i
= 0; i
< args
->buffer_count
; i
++) {
3713 object_list
[i
] = drm_gem_object_lookup(dev
, file_priv
,
3714 exec_list
[i
].handle
);
3715 if (object_list
[i
] == NULL
) {
3716 DRM_ERROR("Invalid object handle %d at index %d\n",
3717 exec_list
[i
].handle
, i
);
3718 /* prevent error path from reading uninitialized data */
3719 args
->buffer_count
= i
+ 1;
3724 obj_priv
= to_intel_bo(object_list
[i
]);
3725 if (obj_priv
->in_execbuffer
) {
3726 DRM_ERROR("Object %p appears more than once in object list\n",
3728 /* prevent error path from reading uninitialized data */
3729 args
->buffer_count
= i
+ 1;
3733 obj_priv
->in_execbuffer
= true;
3734 flips
+= atomic_read(&obj_priv
->pending_flip
);
3738 ret
= i915_gem_wait_for_pending_flip(dev
, object_list
,
3739 args
->buffer_count
);
3744 /* Pin and relocate */
3745 for (pin_tries
= 0; ; pin_tries
++) {
3749 for (i
= 0; i
< args
->buffer_count
; i
++) {
3750 object_list
[i
]->pending_read_domains
= 0;
3751 object_list
[i
]->pending_write_domain
= 0;
3752 ret
= i915_gem_object_pin_and_relocate(object_list
[i
],
3755 &relocs
[reloc_index
]);
3759 reloc_index
+= exec_list
[i
].relocation_count
;
3765 /* error other than GTT full, or we've already tried again */
3766 if (ret
!= -ENOSPC
|| pin_tries
>= 1) {
3767 if (ret
!= -ERESTARTSYS
) {
3768 unsigned long long total_size
= 0;
3770 for (i
= 0; i
< args
->buffer_count
; i
++) {
3771 obj_priv
= to_intel_bo(object_list
[i
]);
3773 total_size
+= object_list
[i
]->size
;
3775 exec_list
[i
].flags
& EXEC_OBJECT_NEEDS_FENCE
&&
3776 obj_priv
->tiling_mode
!= I915_TILING_NONE
;
3778 DRM_ERROR("Failed to pin buffer %d of %d, total %llu bytes, %d fences: %d\n",
3779 pinned
+1, args
->buffer_count
,
3780 total_size
, num_fences
,
3782 DRM_ERROR("%d objects [%d pinned], "
3783 "%d object bytes [%d pinned], "
3784 "%d/%d gtt bytes\n",
3785 atomic_read(&dev
->object_count
),
3786 atomic_read(&dev
->pin_count
),
3787 atomic_read(&dev
->object_memory
),
3788 atomic_read(&dev
->pin_memory
),
3789 atomic_read(&dev
->gtt_memory
),
3795 /* unpin all of our buffers */
3796 for (i
= 0; i
< pinned
; i
++)
3797 i915_gem_object_unpin(object_list
[i
]);
3800 /* evict everyone we can from the aperture */
3801 ret
= i915_gem_evict_everything(dev
);
3802 if (ret
&& ret
!= -ENOSPC
)
3806 /* Set the pending read domains for the batch buffer to COMMAND */
3807 batch_obj
= object_list
[args
->buffer_count
-1];
3808 if (batch_obj
->pending_write_domain
) {
3809 DRM_ERROR("Attempting to use self-modifying batch buffer\n");
3813 batch_obj
->pending_read_domains
|= I915_GEM_DOMAIN_COMMAND
;
3815 /* Sanity check the batch buffer, prior to moving objects */
3816 exec_offset
= exec_list
[args
->buffer_count
- 1].offset
;
3817 ret
= i915_gem_check_execbuffer (args
, exec_offset
);
3819 DRM_ERROR("execbuf with invalid offset/length\n");
3823 /* Zero the global flush/invalidate flags. These
3824 * will be modified as new domains are computed
3827 dev
->invalidate_domains
= 0;
3828 dev
->flush_domains
= 0;
3829 dev_priv
->mm
.flush_rings
= 0;
3831 for (i
= 0; i
< args
->buffer_count
; i
++) {
3832 struct drm_gem_object
*obj
= object_list
[i
];
3834 /* Compute new gpu domains and update invalidate/flush */
3835 i915_gem_object_set_to_gpu_domain(obj
);
3838 if (dev
->invalidate_domains
| dev
->flush_domains
) {
3840 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
3842 dev
->invalidate_domains
,
3843 dev
->flush_domains
);
3845 i915_gem_flush(dev
, file_priv
,
3846 dev
->invalidate_domains
,
3848 dev_priv
->mm
.flush_rings
);
3851 for (i
= 0; i
< args
->buffer_count
; i
++) {
3852 struct drm_gem_object
*obj
= object_list
[i
];
3853 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
3854 uint32_t old_write_domain
= obj
->write_domain
;
3856 obj
->write_domain
= obj
->pending_write_domain
;
3857 if (obj
->write_domain
)
3858 list_move_tail(&obj_priv
->gpu_write_list
,
3859 &dev_priv
->mm
.gpu_write_list
);
3861 trace_i915_gem_object_change_domain(obj
,
3867 for (i
= 0; i
< args
->buffer_count
; i
++) {
3868 i915_gem_object_check_coherency(object_list
[i
],
3869 exec_list
[i
].handle
);
3874 i915_gem_dump_object(batch_obj
,
3880 /* Exec the batchbuffer */
3881 ret
= ring
->dispatch_gem_execbuffer(dev
, ring
, args
,
3882 cliprects
, exec_offset
);
3884 DRM_ERROR("dispatch failed %d\n", ret
);
3889 * Ensure that the commands in the batch buffer are
3890 * finished before the interrupt fires
3892 i915_retire_commands(dev
, ring
);
3894 for (i
= 0; i
< args
->buffer_count
; i
++) {
3895 struct drm_gem_object
*obj
= object_list
[i
];
3896 obj_priv
= to_intel_bo(obj
);
3898 i915_gem_object_move_to_active(obj
, ring
);
3901 i915_add_request(dev
, file_priv
, request
, ring
);
3905 for (i
= 0; i
< pinned
; i
++)
3906 i915_gem_object_unpin(object_list
[i
]);
3908 for (i
= 0; i
< args
->buffer_count
; i
++) {
3909 if (object_list
[i
]) {
3910 obj_priv
= to_intel_bo(object_list
[i
]);
3911 obj_priv
->in_execbuffer
= false;
3913 drm_gem_object_unreference(object_list
[i
]);
3916 mutex_unlock(&dev
->struct_mutex
);
3919 /* Copy the updated relocations out regardless of current error
3920 * state. Failure to update the relocs would mean that the next
3921 * time userland calls execbuf, it would do so with presumed offset
3922 * state that didn't match the actual object state.
3924 ret2
= i915_gem_put_relocs_to_user(exec_list
, args
->buffer_count
,
3927 DRM_ERROR("Failed to copy relocations back out: %d\n", ret2
);
3933 drm_free_large(object_list
);
3941 * Legacy execbuffer just creates an exec2 list from the original exec object
3942 * list array and passes it to the real function.
3945 i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
3946 struct drm_file
*file_priv
)
3948 struct drm_i915_gem_execbuffer
*args
= data
;
3949 struct drm_i915_gem_execbuffer2 exec2
;
3950 struct drm_i915_gem_exec_object
*exec_list
= NULL
;
3951 struct drm_i915_gem_exec_object2
*exec2_list
= NULL
;
3955 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3956 (int) args
->buffers_ptr
, args
->buffer_count
, args
->batch_len
);
3959 if (args
->buffer_count
< 1) {
3960 DRM_ERROR("execbuf with %d buffers\n", args
->buffer_count
);
3964 /* Copy in the exec list from userland */
3965 exec_list
= drm_malloc_ab(sizeof(*exec_list
), args
->buffer_count
);
3966 exec2_list
= drm_malloc_ab(sizeof(*exec2_list
), args
->buffer_count
);
3967 if (exec_list
== NULL
|| exec2_list
== NULL
) {
3968 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
3969 args
->buffer_count
);
3970 drm_free_large(exec_list
);
3971 drm_free_large(exec2_list
);
3974 ret
= copy_from_user(exec_list
,
3975 (struct drm_i915_relocation_entry __user
*)
3976 (uintptr_t) args
->buffers_ptr
,
3977 sizeof(*exec_list
) * args
->buffer_count
);
3979 DRM_ERROR("copy %d exec entries failed %d\n",
3980 args
->buffer_count
, ret
);
3981 drm_free_large(exec_list
);
3982 drm_free_large(exec2_list
);
3986 for (i
= 0; i
< args
->buffer_count
; i
++) {
3987 exec2_list
[i
].handle
= exec_list
[i
].handle
;
3988 exec2_list
[i
].relocation_count
= exec_list
[i
].relocation_count
;
3989 exec2_list
[i
].relocs_ptr
= exec_list
[i
].relocs_ptr
;
3990 exec2_list
[i
].alignment
= exec_list
[i
].alignment
;
3991 exec2_list
[i
].offset
= exec_list
[i
].offset
;
3992 if (INTEL_INFO(dev
)->gen
< 4)
3993 exec2_list
[i
].flags
= EXEC_OBJECT_NEEDS_FENCE
;
3995 exec2_list
[i
].flags
= 0;
3998 exec2
.buffers_ptr
= args
->buffers_ptr
;
3999 exec2
.buffer_count
= args
->buffer_count
;
4000 exec2
.batch_start_offset
= args
->batch_start_offset
;
4001 exec2
.batch_len
= args
->batch_len
;
4002 exec2
.DR1
= args
->DR1
;
4003 exec2
.DR4
= args
->DR4
;
4004 exec2
.num_cliprects
= args
->num_cliprects
;
4005 exec2
.cliprects_ptr
= args
->cliprects_ptr
;
4006 exec2
.flags
= I915_EXEC_RENDER
;
4008 ret
= i915_gem_do_execbuffer(dev
, data
, file_priv
, &exec2
, exec2_list
);
4010 /* Copy the new buffer offsets back to the user's exec list. */
4011 for (i
= 0; i
< args
->buffer_count
; i
++)
4012 exec_list
[i
].offset
= exec2_list
[i
].offset
;
4013 /* ... and back out to userspace */
4014 ret
= copy_to_user((struct drm_i915_relocation_entry __user
*)
4015 (uintptr_t) args
->buffers_ptr
,
4017 sizeof(*exec_list
) * args
->buffer_count
);
4020 DRM_ERROR("failed to copy %d exec entries "
4021 "back to user (%d)\n",
4022 args
->buffer_count
, ret
);
4026 drm_free_large(exec_list
);
4027 drm_free_large(exec2_list
);
4032 i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
4033 struct drm_file
*file_priv
)
4035 struct drm_i915_gem_execbuffer2
*args
= data
;
4036 struct drm_i915_gem_exec_object2
*exec2_list
= NULL
;
4040 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
4041 (int) args
->buffers_ptr
, args
->buffer_count
, args
->batch_len
);
4044 if (args
->buffer_count
< 1) {
4045 DRM_ERROR("execbuf2 with %d buffers\n", args
->buffer_count
);
4049 exec2_list
= drm_malloc_ab(sizeof(*exec2_list
), args
->buffer_count
);
4050 if (exec2_list
== NULL
) {
4051 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
4052 args
->buffer_count
);
4055 ret
= copy_from_user(exec2_list
,
4056 (struct drm_i915_relocation_entry __user
*)
4057 (uintptr_t) args
->buffers_ptr
,
4058 sizeof(*exec2_list
) * args
->buffer_count
);
4060 DRM_ERROR("copy %d exec entries failed %d\n",
4061 args
->buffer_count
, ret
);
4062 drm_free_large(exec2_list
);
4066 ret
= i915_gem_do_execbuffer(dev
, data
, file_priv
, args
, exec2_list
);
4068 /* Copy the new buffer offsets back to the user's exec list. */
4069 ret
= copy_to_user((struct drm_i915_relocation_entry __user
*)
4070 (uintptr_t) args
->buffers_ptr
,
4072 sizeof(*exec2_list
) * args
->buffer_count
);
4075 DRM_ERROR("failed to copy %d exec entries "
4076 "back to user (%d)\n",
4077 args
->buffer_count
, ret
);
4081 drm_free_large(exec2_list
);
4086 i915_gem_object_pin(struct drm_gem_object
*obj
, uint32_t alignment
)
4088 struct drm_device
*dev
= obj
->dev
;
4089 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4090 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
4093 BUG_ON(obj_priv
->pin_count
== DRM_I915_GEM_OBJECT_MAX_PIN_COUNT
);
4094 WARN_ON(i915_verify_lists(dev
));
4096 if (obj_priv
->gtt_space
!= NULL
) {
4098 alignment
= i915_gem_get_gtt_alignment(obj
);
4099 if (obj_priv
->gtt_offset
& (alignment
- 1)) {
4100 WARN(obj_priv
->pin_count
,
4101 "bo is already pinned with incorrect alignment:"
4102 " offset=%x, req.alignment=%x\n",
4103 obj_priv
->gtt_offset
, alignment
);
4104 ret
= i915_gem_object_unbind(obj
);
4110 if (obj_priv
->gtt_space
== NULL
) {
4111 ret
= i915_gem_object_bind_to_gtt(obj
, alignment
);
4116 obj_priv
->pin_count
++;
4118 /* If the object is not active and not pending a flush,
4119 * remove it from the inactive list
4121 if (obj_priv
->pin_count
== 1) {
4122 atomic_inc(&dev
->pin_count
);
4123 atomic_add(obj
->size
, &dev
->pin_memory
);
4124 if (!obj_priv
->active
)
4125 list_move_tail(&obj_priv
->list
,
4126 &dev_priv
->mm
.pinned_list
);
4129 WARN_ON(i915_verify_lists(dev
));
4134 i915_gem_object_unpin(struct drm_gem_object
*obj
)
4136 struct drm_device
*dev
= obj
->dev
;
4137 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4138 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
4140 WARN_ON(i915_verify_lists(dev
));
4141 obj_priv
->pin_count
--;
4142 BUG_ON(obj_priv
->pin_count
< 0);
4143 BUG_ON(obj_priv
->gtt_space
== NULL
);
4145 /* If the object is no longer pinned, and is
4146 * neither active nor being flushed, then stick it on
4149 if (obj_priv
->pin_count
== 0) {
4150 if (!obj_priv
->active
)
4151 list_move_tail(&obj_priv
->list
,
4152 &dev_priv
->mm
.inactive_list
);
4153 atomic_dec(&dev
->pin_count
);
4154 atomic_sub(obj
->size
, &dev
->pin_memory
);
4156 WARN_ON(i915_verify_lists(dev
));
4160 i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
4161 struct drm_file
*file_priv
)
4163 struct drm_i915_gem_pin
*args
= data
;
4164 struct drm_gem_object
*obj
;
4165 struct drm_i915_gem_object
*obj_priv
;
4168 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4170 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
4174 obj_priv
= to_intel_bo(obj
);
4176 ret
= i915_mutex_lock_interruptible(dev
);
4178 drm_gem_object_unreference_unlocked(obj
);
4182 if (obj_priv
->madv
!= I915_MADV_WILLNEED
) {
4183 DRM_ERROR("Attempting to pin a purgeable buffer\n");
4184 drm_gem_object_unreference(obj
);
4185 mutex_unlock(&dev
->struct_mutex
);
4189 if (obj_priv
->pin_filp
!= NULL
&& obj_priv
->pin_filp
!= file_priv
) {
4190 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
4192 drm_gem_object_unreference(obj
);
4193 mutex_unlock(&dev
->struct_mutex
);
4197 obj_priv
->user_pin_count
++;
4198 obj_priv
->pin_filp
= file_priv
;
4199 if (obj_priv
->user_pin_count
== 1) {
4200 ret
= i915_gem_object_pin(obj
, args
->alignment
);
4202 drm_gem_object_unreference(obj
);
4203 mutex_unlock(&dev
->struct_mutex
);
4208 /* XXX - flush the CPU caches for pinned objects
4209 * as the X server doesn't manage domains yet
4211 i915_gem_object_flush_cpu_write_domain(obj
);
4212 args
->offset
= obj_priv
->gtt_offset
;
4213 drm_gem_object_unreference(obj
);
4214 mutex_unlock(&dev
->struct_mutex
);
4220 i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
4221 struct drm_file
*file_priv
)
4223 struct drm_i915_gem_pin
*args
= data
;
4224 struct drm_gem_object
*obj
;
4225 struct drm_i915_gem_object
*obj_priv
;
4228 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4230 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
4235 obj_priv
= to_intel_bo(obj
);
4237 ret
= i915_mutex_lock_interruptible(dev
);
4239 drm_gem_object_unreference_unlocked(obj
);
4243 if (obj_priv
->pin_filp
!= file_priv
) {
4244 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4246 drm_gem_object_unreference(obj
);
4247 mutex_unlock(&dev
->struct_mutex
);
4250 obj_priv
->user_pin_count
--;
4251 if (obj_priv
->user_pin_count
== 0) {
4252 obj_priv
->pin_filp
= NULL
;
4253 i915_gem_object_unpin(obj
);
4256 drm_gem_object_unreference(obj
);
4257 mutex_unlock(&dev
->struct_mutex
);
4262 i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
4263 struct drm_file
*file_priv
)
4265 struct drm_i915_gem_busy
*args
= data
;
4266 struct drm_gem_object
*obj
;
4267 struct drm_i915_gem_object
*obj_priv
;
4270 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4272 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
4277 ret
= i915_mutex_lock_interruptible(dev
);
4279 drm_gem_object_unreference_unlocked(obj
);
4283 /* Count all active objects as busy, even if they are currently not used
4284 * by the gpu. Users of this interface expect objects to eventually
4285 * become non-busy without any further actions, therefore emit any
4286 * necessary flushes here.
4288 obj_priv
= to_intel_bo(obj
);
4289 args
->busy
= obj_priv
->active
;
4291 /* Unconditionally flush objects, even when the gpu still uses this
4292 * object. Userspace calling this function indicates that it wants to
4293 * use this buffer rather sooner than later, so issuing the required
4294 * flush earlier is beneficial.
4296 if (obj
->write_domain
& I915_GEM_GPU_DOMAINS
)
4297 i915_gem_flush_ring(dev
, file_priv
,
4299 0, obj
->write_domain
);
4301 /* Update the active list for the hardware's current position.
4302 * Otherwise this only updates on a delayed timer or when irqs
4303 * are actually unmasked, and our working set ends up being
4304 * larger than required.
4306 i915_gem_retire_requests_ring(dev
, obj_priv
->ring
);
4308 args
->busy
= obj_priv
->active
;
4311 drm_gem_object_unreference(obj
);
4312 mutex_unlock(&dev
->struct_mutex
);
4317 i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
4318 struct drm_file
*file_priv
)
4320 return i915_gem_ring_throttle(dev
, file_priv
);
4324 i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
4325 struct drm_file
*file_priv
)
4327 struct drm_i915_gem_madvise
*args
= data
;
4328 struct drm_gem_object
*obj
;
4329 struct drm_i915_gem_object
*obj_priv
;
4332 switch (args
->madv
) {
4333 case I915_MADV_DONTNEED
:
4334 case I915_MADV_WILLNEED
:
4340 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4342 DRM_ERROR("Bad handle in i915_gem_madvise_ioctl(): %d\n",
4346 obj_priv
= to_intel_bo(obj
);
4348 ret
= i915_mutex_lock_interruptible(dev
);
4350 drm_gem_object_unreference_unlocked(obj
);
4354 if (obj_priv
->pin_count
) {
4355 drm_gem_object_unreference(obj
);
4356 mutex_unlock(&dev
->struct_mutex
);
4358 DRM_ERROR("Attempted i915_gem_madvise_ioctl() on a pinned object\n");
4362 if (obj_priv
->madv
!= __I915_MADV_PURGED
)
4363 obj_priv
->madv
= args
->madv
;
4365 /* if the object is no longer bound, discard its backing storage */
4366 if (i915_gem_object_is_purgeable(obj_priv
) &&
4367 obj_priv
->gtt_space
== NULL
)
4368 i915_gem_object_truncate(obj
);
4370 args
->retained
= obj_priv
->madv
!= __I915_MADV_PURGED
;
4372 drm_gem_object_unreference(obj
);
4373 mutex_unlock(&dev
->struct_mutex
);
4378 struct drm_gem_object
* i915_gem_alloc_object(struct drm_device
*dev
,
4381 struct drm_i915_gem_object
*obj
;
4383 obj
= kzalloc(sizeof(*obj
), GFP_KERNEL
);
4387 if (drm_gem_object_init(dev
, &obj
->base
, size
) != 0) {
4392 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
4393 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
4395 obj
->agp_type
= AGP_USER_MEMORY
;
4396 obj
->base
.driver_private
= NULL
;
4397 obj
->fence_reg
= I915_FENCE_REG_NONE
;
4398 INIT_LIST_HEAD(&obj
->list
);
4399 INIT_LIST_HEAD(&obj
->gpu_write_list
);
4400 obj
->madv
= I915_MADV_WILLNEED
;
4402 trace_i915_gem_object_create(&obj
->base
);
4407 int i915_gem_init_object(struct drm_gem_object
*obj
)
4414 static void i915_gem_free_object_tail(struct drm_gem_object
*obj
)
4416 struct drm_device
*dev
= obj
->dev
;
4417 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4418 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
4421 ret
= i915_gem_object_unbind(obj
);
4422 if (ret
== -ERESTARTSYS
) {
4423 list_move(&obj_priv
->list
,
4424 &dev_priv
->mm
.deferred_free_list
);
4428 if (obj_priv
->mmap_offset
)
4429 i915_gem_free_mmap_offset(obj
);
4431 drm_gem_object_release(obj
);
4433 kfree(obj_priv
->page_cpu_valid
);
4434 kfree(obj_priv
->bit_17
);
4438 void i915_gem_free_object(struct drm_gem_object
*obj
)
4440 struct drm_device
*dev
= obj
->dev
;
4441 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
4443 trace_i915_gem_object_destroy(obj
);
4445 while (obj_priv
->pin_count
> 0)
4446 i915_gem_object_unpin(obj
);
4448 if (obj_priv
->phys_obj
)
4449 i915_gem_detach_phys_object(dev
, obj
);
4451 i915_gem_free_object_tail(obj
);
4455 i915_gem_idle(struct drm_device
*dev
)
4457 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4460 mutex_lock(&dev
->struct_mutex
);
4462 if (dev_priv
->mm
.suspended
||
4463 (dev_priv
->render_ring
.gem_object
== NULL
) ||
4465 dev_priv
->bsd_ring
.gem_object
== NULL
)) {
4466 mutex_unlock(&dev
->struct_mutex
);
4470 ret
= i915_gpu_idle(dev
);
4472 mutex_unlock(&dev
->struct_mutex
);
4476 /* Under UMS, be paranoid and evict. */
4477 if (!drm_core_check_feature(dev
, DRIVER_MODESET
)) {
4478 ret
= i915_gem_evict_inactive(dev
);
4480 mutex_unlock(&dev
->struct_mutex
);
4485 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4486 * We need to replace this with a semaphore, or something.
4487 * And not confound mm.suspended!
4489 dev_priv
->mm
.suspended
= 1;
4490 del_timer_sync(&dev_priv
->hangcheck_timer
);
4492 i915_kernel_lost_context(dev
);
4493 i915_gem_cleanup_ringbuffer(dev
);
4495 mutex_unlock(&dev
->struct_mutex
);
4497 /* Cancel the retire work handler, which should be idle now. */
4498 cancel_delayed_work_sync(&dev_priv
->mm
.retire_work
);
4504 * 965+ support PIPE_CONTROL commands, which provide finer grained control
4505 * over cache flushing.
4508 i915_gem_init_pipe_control(struct drm_device
*dev
)
4510 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4511 struct drm_gem_object
*obj
;
4512 struct drm_i915_gem_object
*obj_priv
;
4515 obj
= i915_gem_alloc_object(dev
, 4096);
4517 DRM_ERROR("Failed to allocate seqno page\n");
4521 obj_priv
= to_intel_bo(obj
);
4522 obj_priv
->agp_type
= AGP_USER_CACHED_MEMORY
;
4524 ret
= i915_gem_object_pin(obj
, 4096);
4528 dev_priv
->seqno_gfx_addr
= obj_priv
->gtt_offset
;
4529 dev_priv
->seqno_page
= kmap(obj_priv
->pages
[0]);
4530 if (dev_priv
->seqno_page
== NULL
)
4533 dev_priv
->seqno_obj
= obj
;
4534 memset(dev_priv
->seqno_page
, 0, PAGE_SIZE
);
4539 i915_gem_object_unpin(obj
);
4541 drm_gem_object_unreference(obj
);
4548 i915_gem_cleanup_pipe_control(struct drm_device
*dev
)
4550 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4551 struct drm_gem_object
*obj
;
4552 struct drm_i915_gem_object
*obj_priv
;
4554 obj
= dev_priv
->seqno_obj
;
4555 obj_priv
= to_intel_bo(obj
);
4556 kunmap(obj_priv
->pages
[0]);
4557 i915_gem_object_unpin(obj
);
4558 drm_gem_object_unreference(obj
);
4559 dev_priv
->seqno_obj
= NULL
;
4561 dev_priv
->seqno_page
= NULL
;
4565 i915_gem_init_ringbuffer(struct drm_device
*dev
)
4567 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4570 if (HAS_PIPE_CONTROL(dev
)) {
4571 ret
= i915_gem_init_pipe_control(dev
);
4576 ret
= intel_init_render_ring_buffer(dev
);
4578 goto cleanup_pipe_control
;
4581 ret
= intel_init_bsd_ring_buffer(dev
);
4583 goto cleanup_render_ring
;
4586 dev_priv
->next_seqno
= 1;
4590 cleanup_render_ring
:
4591 intel_cleanup_ring_buffer(dev
, &dev_priv
->render_ring
);
4592 cleanup_pipe_control
:
4593 if (HAS_PIPE_CONTROL(dev
))
4594 i915_gem_cleanup_pipe_control(dev
);
4599 i915_gem_cleanup_ringbuffer(struct drm_device
*dev
)
4601 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4603 intel_cleanup_ring_buffer(dev
, &dev_priv
->render_ring
);
4605 intel_cleanup_ring_buffer(dev
, &dev_priv
->bsd_ring
);
4606 if (HAS_PIPE_CONTROL(dev
))
4607 i915_gem_cleanup_pipe_control(dev
);
4611 i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
4612 struct drm_file
*file_priv
)
4614 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4617 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4620 if (atomic_read(&dev_priv
->mm
.wedged
)) {
4621 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4622 atomic_set(&dev_priv
->mm
.wedged
, 0);
4625 mutex_lock(&dev
->struct_mutex
);
4626 dev_priv
->mm
.suspended
= 0;
4628 ret
= i915_gem_init_ringbuffer(dev
);
4630 mutex_unlock(&dev
->struct_mutex
);
4634 BUG_ON(!list_empty(&dev_priv
->render_ring
.active_list
));
4635 BUG_ON(HAS_BSD(dev
) && !list_empty(&dev_priv
->bsd_ring
.active_list
));
4636 BUG_ON(!list_empty(&dev_priv
->mm
.flushing_list
));
4637 BUG_ON(!list_empty(&dev_priv
->mm
.inactive_list
));
4638 BUG_ON(!list_empty(&dev_priv
->render_ring
.request_list
));
4639 BUG_ON(HAS_BSD(dev
) && !list_empty(&dev_priv
->bsd_ring
.request_list
));
4640 mutex_unlock(&dev
->struct_mutex
);
4642 ret
= drm_irq_install(dev
);
4644 goto cleanup_ringbuffer
;
4649 mutex_lock(&dev
->struct_mutex
);
4650 i915_gem_cleanup_ringbuffer(dev
);
4651 dev_priv
->mm
.suspended
= 1;
4652 mutex_unlock(&dev
->struct_mutex
);
4658 i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
4659 struct drm_file
*file_priv
)
4661 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4664 drm_irq_uninstall(dev
);
4665 return i915_gem_idle(dev
);
4669 i915_gem_lastclose(struct drm_device
*dev
)
4673 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4676 ret
= i915_gem_idle(dev
);
4678 DRM_ERROR("failed to idle hardware: %d\n", ret
);
4682 i915_gem_load(struct drm_device
*dev
)
4685 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4687 INIT_LIST_HEAD(&dev_priv
->mm
.flushing_list
);
4688 INIT_LIST_HEAD(&dev_priv
->mm
.gpu_write_list
);
4689 INIT_LIST_HEAD(&dev_priv
->mm
.inactive_list
);
4690 INIT_LIST_HEAD(&dev_priv
->mm
.pinned_list
);
4691 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
4692 INIT_LIST_HEAD(&dev_priv
->mm
.deferred_free_list
);
4693 INIT_LIST_HEAD(&dev_priv
->render_ring
.active_list
);
4694 INIT_LIST_HEAD(&dev_priv
->render_ring
.request_list
);
4696 INIT_LIST_HEAD(&dev_priv
->bsd_ring
.active_list
);
4697 INIT_LIST_HEAD(&dev_priv
->bsd_ring
.request_list
);
4699 for (i
= 0; i
< 16; i
++)
4700 INIT_LIST_HEAD(&dev_priv
->fence_regs
[i
].lru_list
);
4701 INIT_DELAYED_WORK(&dev_priv
->mm
.retire_work
,
4702 i915_gem_retire_work_handler
);
4703 init_completion(&dev_priv
->error_completion
);
4704 spin_lock(&shrink_list_lock
);
4705 list_add(&dev_priv
->mm
.shrink_list
, &shrink_list
);
4706 spin_unlock(&shrink_list_lock
);
4708 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4710 u32 tmp
= I915_READ(MI_ARB_STATE
);
4711 if (!(tmp
& MI_ARB_C3_LP_WRITE_ENABLE
)) {
4712 /* arb state is a masked write, so set bit + bit in mask */
4713 tmp
= MI_ARB_C3_LP_WRITE_ENABLE
| (MI_ARB_C3_LP_WRITE_ENABLE
<< MI_ARB_MASK_SHIFT
);
4714 I915_WRITE(MI_ARB_STATE
, tmp
);
4718 /* Old X drivers will take 0-2 for front, back, depth buffers */
4719 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
4720 dev_priv
->fence_reg_start
= 3;
4722 if (INTEL_INFO(dev
)->gen
>= 4 || IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
4723 dev_priv
->num_fence_regs
= 16;
4725 dev_priv
->num_fence_regs
= 8;
4727 /* Initialize fence registers to zero */
4728 switch (INTEL_INFO(dev
)->gen
) {
4730 for (i
= 0; i
< 16; i
++)
4731 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0
+ (i
* 8), 0);
4735 for (i
= 0; i
< 16; i
++)
4736 I915_WRITE64(FENCE_REG_965_0
+ (i
* 8), 0);
4739 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
4740 for (i
= 0; i
< 8; i
++)
4741 I915_WRITE(FENCE_REG_945_8
+ (i
* 4), 0);
4743 for (i
= 0; i
< 8; i
++)
4744 I915_WRITE(FENCE_REG_830_0
+ (i
* 4), 0);
4747 i915_gem_detect_bit_6_swizzle(dev
);
4748 init_waitqueue_head(&dev_priv
->pending_flip_queue
);
4752 * Create a physically contiguous memory object for this object
4753 * e.g. for cursor + overlay regs
4755 static int i915_gem_init_phys_object(struct drm_device
*dev
,
4756 int id
, int size
, int align
)
4758 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4759 struct drm_i915_gem_phys_object
*phys_obj
;
4762 if (dev_priv
->mm
.phys_objs
[id
- 1] || !size
)
4765 phys_obj
= kzalloc(sizeof(struct drm_i915_gem_phys_object
), GFP_KERNEL
);
4771 phys_obj
->handle
= drm_pci_alloc(dev
, size
, align
);
4772 if (!phys_obj
->handle
) {
4777 set_memory_wc((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
4780 dev_priv
->mm
.phys_objs
[id
- 1] = phys_obj
;
4788 static void i915_gem_free_phys_object(struct drm_device
*dev
, int id
)
4790 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4791 struct drm_i915_gem_phys_object
*phys_obj
;
4793 if (!dev_priv
->mm
.phys_objs
[id
- 1])
4796 phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
4797 if (phys_obj
->cur_obj
) {
4798 i915_gem_detach_phys_object(dev
, phys_obj
->cur_obj
);
4802 set_memory_wb((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
4804 drm_pci_free(dev
, phys_obj
->handle
);
4806 dev_priv
->mm
.phys_objs
[id
- 1] = NULL
;
4809 void i915_gem_free_all_phys_object(struct drm_device
*dev
)
4813 for (i
= I915_GEM_PHYS_CURSOR_0
; i
<= I915_MAX_PHYS_OBJECT
; i
++)
4814 i915_gem_free_phys_object(dev
, i
);
4817 void i915_gem_detach_phys_object(struct drm_device
*dev
,
4818 struct drm_gem_object
*obj
)
4820 struct drm_i915_gem_object
*obj_priv
;
4825 obj_priv
= to_intel_bo(obj
);
4826 if (!obj_priv
->phys_obj
)
4829 ret
= i915_gem_object_get_pages(obj
, 0);
4833 page_count
= obj
->size
/ PAGE_SIZE
;
4835 for (i
= 0; i
< page_count
; i
++) {
4836 char *dst
= kmap_atomic(obj_priv
->pages
[i
], KM_USER0
);
4837 char *src
= obj_priv
->phys_obj
->handle
->vaddr
+ (i
* PAGE_SIZE
);
4839 memcpy(dst
, src
, PAGE_SIZE
);
4840 kunmap_atomic(dst
, KM_USER0
);
4842 drm_clflush_pages(obj_priv
->pages
, page_count
);
4843 drm_agp_chipset_flush(dev
);
4845 i915_gem_object_put_pages(obj
);
4847 obj_priv
->phys_obj
->cur_obj
= NULL
;
4848 obj_priv
->phys_obj
= NULL
;
4852 i915_gem_attach_phys_object(struct drm_device
*dev
,
4853 struct drm_gem_object
*obj
,
4857 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4858 struct drm_i915_gem_object
*obj_priv
;
4863 if (id
> I915_MAX_PHYS_OBJECT
)
4866 obj_priv
= to_intel_bo(obj
);
4868 if (obj_priv
->phys_obj
) {
4869 if (obj_priv
->phys_obj
->id
== id
)
4871 i915_gem_detach_phys_object(dev
, obj
);
4874 /* create a new object */
4875 if (!dev_priv
->mm
.phys_objs
[id
- 1]) {
4876 ret
= i915_gem_init_phys_object(dev
, id
,
4879 DRM_ERROR("failed to init phys object %d size: %zu\n", id
, obj
->size
);
4884 /* bind to the object */
4885 obj_priv
->phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
4886 obj_priv
->phys_obj
->cur_obj
= obj
;
4888 ret
= i915_gem_object_get_pages(obj
, 0);
4890 DRM_ERROR("failed to get page list\n");
4894 page_count
= obj
->size
/ PAGE_SIZE
;
4896 for (i
= 0; i
< page_count
; i
++) {
4897 char *src
= kmap_atomic(obj_priv
->pages
[i
], KM_USER0
);
4898 char *dst
= obj_priv
->phys_obj
->handle
->vaddr
+ (i
* PAGE_SIZE
);
4900 memcpy(dst
, src
, PAGE_SIZE
);
4901 kunmap_atomic(src
, KM_USER0
);
4904 i915_gem_object_put_pages(obj
);
4912 i915_gem_phys_pwrite(struct drm_device
*dev
, struct drm_gem_object
*obj
,
4913 struct drm_i915_gem_pwrite
*args
,
4914 struct drm_file
*file_priv
)
4916 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
4919 char __user
*user_data
;
4921 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
4922 obj_addr
= obj_priv
->phys_obj
->handle
->vaddr
+ args
->offset
;
4924 DRM_DEBUG_DRIVER("obj_addr %p, %lld\n", obj_addr
, args
->size
);
4925 ret
= copy_from_user(obj_addr
, user_data
, args
->size
);
4929 drm_agp_chipset_flush(dev
);
4933 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
)
4935 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
4937 /* Clean up our request list when the client is going away, so that
4938 * later retire_requests won't dereference our soon-to-be-gone
4941 spin_lock(&file_priv
->mm
.lock
);
4942 while (!list_empty(&file_priv
->mm
.request_list
)) {
4943 struct drm_i915_gem_request
*request
;
4945 request
= list_first_entry(&file_priv
->mm
.request_list
,
4946 struct drm_i915_gem_request
,
4948 list_del(&request
->client_list
);
4949 request
->file_priv
= NULL
;
4951 spin_unlock(&file_priv
->mm
.lock
);
4955 i915_gpu_is_active(struct drm_device
*dev
)
4957 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4960 lists_empty
= list_empty(&dev_priv
->mm
.flushing_list
) &&
4961 list_empty(&dev_priv
->render_ring
.active_list
);
4963 lists_empty
&= list_empty(&dev_priv
->bsd_ring
.active_list
);
4965 return !lists_empty
;
4969 i915_gem_shrink(struct shrinker
*shrink
, int nr_to_scan
, gfp_t gfp_mask
)
4971 drm_i915_private_t
*dev_priv
, *next_dev
;
4972 struct drm_i915_gem_object
*obj_priv
, *next_obj
;
4974 int would_deadlock
= 1;
4976 /* "fast-path" to count number of available objects */
4977 if (nr_to_scan
== 0) {
4978 spin_lock(&shrink_list_lock
);
4979 list_for_each_entry(dev_priv
, &shrink_list
, mm
.shrink_list
) {
4980 struct drm_device
*dev
= dev_priv
->dev
;
4982 if (mutex_trylock(&dev
->struct_mutex
)) {
4983 list_for_each_entry(obj_priv
,
4984 &dev_priv
->mm
.inactive_list
,
4987 mutex_unlock(&dev
->struct_mutex
);
4990 spin_unlock(&shrink_list_lock
);
4992 return (cnt
/ 100) * sysctl_vfs_cache_pressure
;
4995 spin_lock(&shrink_list_lock
);
4998 /* first scan for clean buffers */
4999 list_for_each_entry_safe(dev_priv
, next_dev
,
5000 &shrink_list
, mm
.shrink_list
) {
5001 struct drm_device
*dev
= dev_priv
->dev
;
5003 if (! mutex_trylock(&dev
->struct_mutex
))
5006 spin_unlock(&shrink_list_lock
);
5007 i915_gem_retire_requests(dev
);
5009 list_for_each_entry_safe(obj_priv
, next_obj
,
5010 &dev_priv
->mm
.inactive_list
,
5012 if (i915_gem_object_is_purgeable(obj_priv
)) {
5013 i915_gem_object_unbind(&obj_priv
->base
);
5014 if (--nr_to_scan
<= 0)
5019 spin_lock(&shrink_list_lock
);
5020 mutex_unlock(&dev
->struct_mutex
);
5024 if (nr_to_scan
<= 0)
5028 /* second pass, evict/count anything still on the inactive list */
5029 list_for_each_entry_safe(dev_priv
, next_dev
,
5030 &shrink_list
, mm
.shrink_list
) {
5031 struct drm_device
*dev
= dev_priv
->dev
;
5033 if (! mutex_trylock(&dev
->struct_mutex
))
5036 spin_unlock(&shrink_list_lock
);
5038 list_for_each_entry_safe(obj_priv
, next_obj
,
5039 &dev_priv
->mm
.inactive_list
,
5041 if (nr_to_scan
> 0) {
5042 i915_gem_object_unbind(&obj_priv
->base
);
5048 spin_lock(&shrink_list_lock
);
5049 mutex_unlock(&dev
->struct_mutex
);
5058 * We are desperate for pages, so as a last resort, wait
5059 * for the GPU to finish and discard whatever we can.
5060 * This has a dramatic impact to reduce the number of
5061 * OOM-killer events whilst running the GPU aggressively.
5063 list_for_each_entry(dev_priv
, &shrink_list
, mm
.shrink_list
) {
5064 struct drm_device
*dev
= dev_priv
->dev
;
5066 if (!mutex_trylock(&dev
->struct_mutex
))
5069 spin_unlock(&shrink_list_lock
);
5071 if (i915_gpu_is_active(dev
)) {
5076 spin_lock(&shrink_list_lock
);
5077 mutex_unlock(&dev
->struct_mutex
);
5084 spin_unlock(&shrink_list_lock
);
5089 return (cnt
/ 100) * sysctl_vfs_cache_pressure
;
5094 static struct shrinker shrinker
= {
5095 .shrink
= i915_gem_shrink
,
5096 .seeks
= DEFAULT_SEEKS
,
5100 i915_gem_shrinker_init(void)
5102 register_shrinker(&shrinker
);
5106 i915_gem_shrinker_exit(void)
5108 unregister_shrinker(&shrinker
);