2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/shmem_fs.h>
35 #include <linux/slab.h>
36 #include <linux/swap.h>
37 #include <linux/pci.h>
38 #include <linux/dma-buf.h>
40 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
);
41 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
);
42 static __must_check
int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object
*obj
,
44 bool map_and_fenceable
,
46 static int i915_gem_phys_pwrite(struct drm_device
*dev
,
47 struct drm_i915_gem_object
*obj
,
48 struct drm_i915_gem_pwrite
*args
,
49 struct drm_file
*file
);
51 static void i915_gem_write_fence(struct drm_device
*dev
, int reg
,
52 struct drm_i915_gem_object
*obj
);
53 static void i915_gem_object_update_fence(struct drm_i915_gem_object
*obj
,
54 struct drm_i915_fence_reg
*fence
,
57 static int i915_gem_inactive_shrink(struct shrinker
*shrinker
,
58 struct shrink_control
*sc
);
59 static long i915_gem_purge(struct drm_i915_private
*dev_priv
, long target
);
60 static void i915_gem_shrink_all(struct drm_i915_private
*dev_priv
);
61 static void i915_gem_object_truncate(struct drm_i915_gem_object
*obj
);
63 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object
*obj
)
66 i915_gem_release_mmap(obj
);
68 /* As we do not have an associated fence register, we will force
69 * a tiling change if we ever need to acquire one.
71 obj
->fence_dirty
= false;
72 obj
->fence_reg
= I915_FENCE_REG_NONE
;
75 /* some bookkeeping */
76 static void i915_gem_info_add_obj(struct drm_i915_private
*dev_priv
,
79 dev_priv
->mm
.object_count
++;
80 dev_priv
->mm
.object_memory
+= size
;
83 static void i915_gem_info_remove_obj(struct drm_i915_private
*dev_priv
,
86 dev_priv
->mm
.object_count
--;
87 dev_priv
->mm
.object_memory
-= size
;
91 i915_gem_wait_for_error(struct drm_device
*dev
)
93 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
94 struct completion
*x
= &dev_priv
->error_completion
;
98 if (!atomic_read(&dev_priv
->mm
.wedged
))
102 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
103 * userspace. If it takes that long something really bad is going on and
104 * we should simply try to bail out and fail as gracefully as possible.
106 ret
= wait_for_completion_interruptible_timeout(x
, 10*HZ
);
108 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
110 } else if (ret
< 0) {
114 if (atomic_read(&dev_priv
->mm
.wedged
)) {
115 /* GPU is hung, bump the completion count to account for
116 * the token we just consumed so that we never hit zero and
117 * end up waiting upon a subsequent completion event that
120 spin_lock_irqsave(&x
->wait
.lock
, flags
);
122 spin_unlock_irqrestore(&x
->wait
.lock
, flags
);
127 int i915_mutex_lock_interruptible(struct drm_device
*dev
)
131 ret
= i915_gem_wait_for_error(dev
);
135 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
139 WARN_ON(i915_verify_lists(dev
));
144 i915_gem_object_is_inactive(struct drm_i915_gem_object
*obj
)
146 return obj
->gtt_space
&& !obj
->active
;
150 i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
151 struct drm_file
*file
)
153 struct drm_i915_gem_init
*args
= data
;
155 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
158 if (args
->gtt_start
>= args
->gtt_end
||
159 (args
->gtt_end
| args
->gtt_start
) & (PAGE_SIZE
- 1))
162 /* GEM with user mode setting was never supported on ilk and later. */
163 if (INTEL_INFO(dev
)->gen
>= 5)
166 mutex_lock(&dev
->struct_mutex
);
167 i915_gem_init_global_gtt(dev
, args
->gtt_start
,
168 args
->gtt_end
, args
->gtt_end
);
169 mutex_unlock(&dev
->struct_mutex
);
175 i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
176 struct drm_file
*file
)
178 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
179 struct drm_i915_gem_get_aperture
*args
= data
;
180 struct drm_i915_gem_object
*obj
;
184 mutex_lock(&dev
->struct_mutex
);
185 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, gtt_list
)
187 pinned
+= obj
->gtt_space
->size
;
188 mutex_unlock(&dev
->struct_mutex
);
190 args
->aper_size
= dev_priv
->mm
.gtt_total
;
191 args
->aper_available_size
= args
->aper_size
- pinned
;
197 i915_gem_create(struct drm_file
*file
,
198 struct drm_device
*dev
,
202 struct drm_i915_gem_object
*obj
;
206 size
= roundup(size
, PAGE_SIZE
);
210 /* Allocate the new object */
211 obj
= i915_gem_alloc_object(dev
, size
);
215 ret
= drm_gem_handle_create(file
, &obj
->base
, &handle
);
217 drm_gem_object_release(&obj
->base
);
218 i915_gem_info_remove_obj(dev
->dev_private
, obj
->base
.size
);
223 /* drop reference from allocate - handle holds it now */
224 drm_gem_object_unreference(&obj
->base
);
225 trace_i915_gem_object_create(obj
);
232 i915_gem_dumb_create(struct drm_file
*file
,
233 struct drm_device
*dev
,
234 struct drm_mode_create_dumb
*args
)
236 /* have to work out size/pitch and return them */
237 args
->pitch
= ALIGN(args
->width
* ((args
->bpp
+ 7) / 8), 64);
238 args
->size
= args
->pitch
* args
->height
;
239 return i915_gem_create(file
, dev
,
240 args
->size
, &args
->handle
);
243 int i915_gem_dumb_destroy(struct drm_file
*file
,
244 struct drm_device
*dev
,
247 return drm_gem_handle_delete(file
, handle
);
251 * Creates a new mm object and returns a handle to it.
254 i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
255 struct drm_file
*file
)
257 struct drm_i915_gem_create
*args
= data
;
259 return i915_gem_create(file
, dev
,
260 args
->size
, &args
->handle
);
263 static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object
*obj
)
265 drm_i915_private_t
*dev_priv
= obj
->base
.dev
->dev_private
;
267 return dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_9_10_17
&&
268 obj
->tiling_mode
!= I915_TILING_NONE
;
272 __copy_to_user_swizzled(char __user
*cpu_vaddr
,
273 const char *gpu_vaddr
, int gpu_offset
,
276 int ret
, cpu_offset
= 0;
279 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
280 int this_length
= min(cacheline_end
- gpu_offset
, length
);
281 int swizzled_gpu_offset
= gpu_offset
^ 64;
283 ret
= __copy_to_user(cpu_vaddr
+ cpu_offset
,
284 gpu_vaddr
+ swizzled_gpu_offset
,
289 cpu_offset
+= this_length
;
290 gpu_offset
+= this_length
;
291 length
-= this_length
;
298 __copy_from_user_swizzled(char *gpu_vaddr
, int gpu_offset
,
299 const char __user
*cpu_vaddr
,
302 int ret
, cpu_offset
= 0;
305 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
306 int this_length
= min(cacheline_end
- gpu_offset
, length
);
307 int swizzled_gpu_offset
= gpu_offset
^ 64;
309 ret
= __copy_from_user(gpu_vaddr
+ swizzled_gpu_offset
,
310 cpu_vaddr
+ cpu_offset
,
315 cpu_offset
+= this_length
;
316 gpu_offset
+= this_length
;
317 length
-= this_length
;
323 /* Per-page copy function for the shmem pread fastpath.
324 * Flushes invalid cachelines before reading the target if
325 * needs_clflush is set. */
327 shmem_pread_fast(struct page
*page
, int shmem_page_offset
, int page_length
,
328 char __user
*user_data
,
329 bool page_do_bit17_swizzling
, bool needs_clflush
)
334 if (unlikely(page_do_bit17_swizzling
))
337 vaddr
= kmap_atomic(page
);
339 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
341 ret
= __copy_to_user_inatomic(user_data
,
342 vaddr
+ shmem_page_offset
,
344 kunmap_atomic(vaddr
);
346 return ret
? -EFAULT
: 0;
350 shmem_clflush_swizzled_range(char *addr
, unsigned long length
,
353 if (unlikely(swizzled
)) {
354 unsigned long start
= (unsigned long) addr
;
355 unsigned long end
= (unsigned long) addr
+ length
;
357 /* For swizzling simply ensure that we always flush both
358 * channels. Lame, but simple and it works. Swizzled
359 * pwrite/pread is far from a hotpath - current userspace
360 * doesn't use it at all. */
361 start
= round_down(start
, 128);
362 end
= round_up(end
, 128);
364 drm_clflush_virt_range((void *)start
, end
- start
);
366 drm_clflush_virt_range(addr
, length
);
371 /* Only difference to the fast-path function is that this can handle bit17
372 * and uses non-atomic copy and kmap functions. */
374 shmem_pread_slow(struct page
*page
, int shmem_page_offset
, int page_length
,
375 char __user
*user_data
,
376 bool page_do_bit17_swizzling
, bool needs_clflush
)
383 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
385 page_do_bit17_swizzling
);
387 if (page_do_bit17_swizzling
)
388 ret
= __copy_to_user_swizzled(user_data
,
389 vaddr
, shmem_page_offset
,
392 ret
= __copy_to_user(user_data
,
393 vaddr
+ shmem_page_offset
,
397 return ret
? - EFAULT
: 0;
401 i915_gem_shmem_pread(struct drm_device
*dev
,
402 struct drm_i915_gem_object
*obj
,
403 struct drm_i915_gem_pread
*args
,
404 struct drm_file
*file
)
406 char __user
*user_data
;
409 int shmem_page_offset
, page_length
, ret
= 0;
410 int obj_do_bit17_swizzling
, page_do_bit17_swizzling
;
411 int hit_slowpath
= 0;
413 int needs_clflush
= 0;
414 struct scatterlist
*sg
;
417 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
420 obj_do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
422 if (!(obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
)) {
423 /* If we're not in the cpu read domain, set ourself into the gtt
424 * read domain and manually flush cachelines (if required). This
425 * optimizes for the case when the gpu will dirty the data
426 * anyway again before the next pread happens. */
427 if (obj
->cache_level
== I915_CACHE_NONE
)
429 if (obj
->gtt_space
) {
430 ret
= i915_gem_object_set_to_gtt_domain(obj
, false);
436 ret
= i915_gem_object_get_pages(obj
);
440 i915_gem_object_pin_pages(obj
);
442 offset
= args
->offset
;
444 for_each_sg(obj
->pages
->sgl
, sg
, obj
->pages
->nents
, i
) {
447 if (i
< offset
>> PAGE_SHIFT
)
453 /* Operation in this page
455 * shmem_page_offset = offset within page in shmem file
456 * page_length = bytes to copy for this page
458 shmem_page_offset
= offset_in_page(offset
);
459 page_length
= remain
;
460 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
461 page_length
= PAGE_SIZE
- shmem_page_offset
;
464 page_do_bit17_swizzling
= obj_do_bit17_swizzling
&&
465 (page_to_phys(page
) & (1 << 17)) != 0;
467 ret
= shmem_pread_fast(page
, shmem_page_offset
, page_length
,
468 user_data
, page_do_bit17_swizzling
,
474 mutex_unlock(&dev
->struct_mutex
);
477 ret
= fault_in_multipages_writeable(user_data
, remain
);
478 /* Userspace is tricking us, but we've already clobbered
479 * its pages with the prefault and promised to write the
480 * data up to the first fault. Hence ignore any errors
481 * and just continue. */
486 ret
= shmem_pread_slow(page
, shmem_page_offset
, page_length
,
487 user_data
, page_do_bit17_swizzling
,
490 mutex_lock(&dev
->struct_mutex
);
493 mark_page_accessed(page
);
498 remain
-= page_length
;
499 user_data
+= page_length
;
500 offset
+= page_length
;
504 i915_gem_object_unpin_pages(obj
);
507 /* Fixup: Kill any reinstated backing storage pages */
508 if (obj
->madv
== __I915_MADV_PURGED
)
509 i915_gem_object_truncate(obj
);
516 * Reads data from the object referenced by handle.
518 * On error, the contents of *data are undefined.
521 i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
522 struct drm_file
*file
)
524 struct drm_i915_gem_pread
*args
= data
;
525 struct drm_i915_gem_object
*obj
;
531 if (!access_ok(VERIFY_WRITE
,
532 (char __user
*)(uintptr_t)args
->data_ptr
,
536 ret
= i915_mutex_lock_interruptible(dev
);
540 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
541 if (&obj
->base
== NULL
) {
546 /* Bounds check source. */
547 if (args
->offset
> obj
->base
.size
||
548 args
->size
> obj
->base
.size
- args
->offset
) {
553 /* prime objects have no backing filp to GEM pread/pwrite
556 if (!obj
->base
.filp
) {
561 trace_i915_gem_object_pread(obj
, args
->offset
, args
->size
);
563 ret
= i915_gem_shmem_pread(dev
, obj
, args
, file
);
566 drm_gem_object_unreference(&obj
->base
);
568 mutex_unlock(&dev
->struct_mutex
);
572 /* This is the fast write path which cannot handle
573 * page faults in the source data
577 fast_user_write(struct io_mapping
*mapping
,
578 loff_t page_base
, int page_offset
,
579 char __user
*user_data
,
582 void __iomem
*vaddr_atomic
;
584 unsigned long unwritten
;
586 vaddr_atomic
= io_mapping_map_atomic_wc(mapping
, page_base
);
587 /* We can use the cpu mem copy function because this is X86. */
588 vaddr
= (void __force
*)vaddr_atomic
+ page_offset
;
589 unwritten
= __copy_from_user_inatomic_nocache(vaddr
,
591 io_mapping_unmap_atomic(vaddr_atomic
);
596 * This is the fast pwrite path, where we copy the data directly from the
597 * user into the GTT, uncached.
600 i915_gem_gtt_pwrite_fast(struct drm_device
*dev
,
601 struct drm_i915_gem_object
*obj
,
602 struct drm_i915_gem_pwrite
*args
,
603 struct drm_file
*file
)
605 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
607 loff_t offset
, page_base
;
608 char __user
*user_data
;
609 int page_offset
, page_length
, ret
;
611 ret
= i915_gem_object_pin(obj
, 0, true, true);
615 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
619 ret
= i915_gem_object_put_fence(obj
);
623 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
626 offset
= obj
->gtt_offset
+ args
->offset
;
629 /* Operation in this page
631 * page_base = page offset within aperture
632 * page_offset = offset within page
633 * page_length = bytes to copy for this page
635 page_base
= offset
& PAGE_MASK
;
636 page_offset
= offset_in_page(offset
);
637 page_length
= remain
;
638 if ((page_offset
+ remain
) > PAGE_SIZE
)
639 page_length
= PAGE_SIZE
- page_offset
;
641 /* If we get a fault while copying data, then (presumably) our
642 * source page isn't available. Return the error and we'll
643 * retry in the slow path.
645 if (fast_user_write(dev_priv
->mm
.gtt_mapping
, page_base
,
646 page_offset
, user_data
, page_length
)) {
651 remain
-= page_length
;
652 user_data
+= page_length
;
653 offset
+= page_length
;
657 i915_gem_object_unpin(obj
);
662 /* Per-page copy function for the shmem pwrite fastpath.
663 * Flushes invalid cachelines before writing to the target if
664 * needs_clflush_before is set and flushes out any written cachelines after
665 * writing if needs_clflush is set. */
667 shmem_pwrite_fast(struct page
*page
, int shmem_page_offset
, int page_length
,
668 char __user
*user_data
,
669 bool page_do_bit17_swizzling
,
670 bool needs_clflush_before
,
671 bool needs_clflush_after
)
676 if (unlikely(page_do_bit17_swizzling
))
679 vaddr
= kmap_atomic(page
);
680 if (needs_clflush_before
)
681 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
683 ret
= __copy_from_user_inatomic_nocache(vaddr
+ shmem_page_offset
,
686 if (needs_clflush_after
)
687 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
689 kunmap_atomic(vaddr
);
691 return ret
? -EFAULT
: 0;
694 /* Only difference to the fast-path function is that this can handle bit17
695 * and uses non-atomic copy and kmap functions. */
697 shmem_pwrite_slow(struct page
*page
, int shmem_page_offset
, int page_length
,
698 char __user
*user_data
,
699 bool page_do_bit17_swizzling
,
700 bool needs_clflush_before
,
701 bool needs_clflush_after
)
707 if (unlikely(needs_clflush_before
|| page_do_bit17_swizzling
))
708 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
710 page_do_bit17_swizzling
);
711 if (page_do_bit17_swizzling
)
712 ret
= __copy_from_user_swizzled(vaddr
, shmem_page_offset
,
716 ret
= __copy_from_user(vaddr
+ shmem_page_offset
,
719 if (needs_clflush_after
)
720 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
722 page_do_bit17_swizzling
);
725 return ret
? -EFAULT
: 0;
729 i915_gem_shmem_pwrite(struct drm_device
*dev
,
730 struct drm_i915_gem_object
*obj
,
731 struct drm_i915_gem_pwrite
*args
,
732 struct drm_file
*file
)
736 char __user
*user_data
;
737 int shmem_page_offset
, page_length
, ret
= 0;
738 int obj_do_bit17_swizzling
, page_do_bit17_swizzling
;
739 int hit_slowpath
= 0;
740 int needs_clflush_after
= 0;
741 int needs_clflush_before
= 0;
743 struct scatterlist
*sg
;
745 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
748 obj_do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
750 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
751 /* If we're not in the cpu write domain, set ourself into the gtt
752 * write domain and manually flush cachelines (if required). This
753 * optimizes for the case when the gpu will use the data
754 * right away and we therefore have to clflush anyway. */
755 if (obj
->cache_level
== I915_CACHE_NONE
)
756 needs_clflush_after
= 1;
757 if (obj
->gtt_space
) {
758 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
763 /* Same trick applies for invalidate partially written cachelines before
765 if (!(obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
)
766 && obj
->cache_level
== I915_CACHE_NONE
)
767 needs_clflush_before
= 1;
769 ret
= i915_gem_object_get_pages(obj
);
773 i915_gem_object_pin_pages(obj
);
775 offset
= args
->offset
;
778 for_each_sg(obj
->pages
->sgl
, sg
, obj
->pages
->nents
, i
) {
780 int partial_cacheline_write
;
782 if (i
< offset
>> PAGE_SHIFT
)
788 /* Operation in this page
790 * shmem_page_offset = offset within page in shmem file
791 * page_length = bytes to copy for this page
793 shmem_page_offset
= offset_in_page(offset
);
795 page_length
= remain
;
796 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
797 page_length
= PAGE_SIZE
- shmem_page_offset
;
799 /* If we don't overwrite a cacheline completely we need to be
800 * careful to have up-to-date data by first clflushing. Don't
801 * overcomplicate things and flush the entire patch. */
802 partial_cacheline_write
= needs_clflush_before
&&
803 ((shmem_page_offset
| page_length
)
804 & (boot_cpu_data
.x86_clflush_size
- 1));
807 page_do_bit17_swizzling
= obj_do_bit17_swizzling
&&
808 (page_to_phys(page
) & (1 << 17)) != 0;
810 ret
= shmem_pwrite_fast(page
, shmem_page_offset
, page_length
,
811 user_data
, page_do_bit17_swizzling
,
812 partial_cacheline_write
,
813 needs_clflush_after
);
818 mutex_unlock(&dev
->struct_mutex
);
819 ret
= shmem_pwrite_slow(page
, shmem_page_offset
, page_length
,
820 user_data
, page_do_bit17_swizzling
,
821 partial_cacheline_write
,
822 needs_clflush_after
);
824 mutex_lock(&dev
->struct_mutex
);
827 set_page_dirty(page
);
828 mark_page_accessed(page
);
833 remain
-= page_length
;
834 user_data
+= page_length
;
835 offset
+= page_length
;
839 i915_gem_object_unpin_pages(obj
);
842 /* Fixup: Kill any reinstated backing storage pages */
843 if (obj
->madv
== __I915_MADV_PURGED
)
844 i915_gem_object_truncate(obj
);
845 /* and flush dirty cachelines in case the object isn't in the cpu write
847 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
848 i915_gem_clflush_object(obj
);
849 intel_gtt_chipset_flush();
853 if (needs_clflush_after
)
854 intel_gtt_chipset_flush();
860 * Writes data to the object referenced by handle.
862 * On error, the contents of the buffer that were to be modified are undefined.
865 i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
866 struct drm_file
*file
)
868 struct drm_i915_gem_pwrite
*args
= data
;
869 struct drm_i915_gem_object
*obj
;
875 if (!access_ok(VERIFY_READ
,
876 (char __user
*)(uintptr_t)args
->data_ptr
,
880 ret
= fault_in_multipages_readable((char __user
*)(uintptr_t)args
->data_ptr
,
885 ret
= i915_mutex_lock_interruptible(dev
);
889 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
890 if (&obj
->base
== NULL
) {
895 /* Bounds check destination. */
896 if (args
->offset
> obj
->base
.size
||
897 args
->size
> obj
->base
.size
- args
->offset
) {
902 /* prime objects have no backing filp to GEM pread/pwrite
905 if (!obj
->base
.filp
) {
910 trace_i915_gem_object_pwrite(obj
, args
->offset
, args
->size
);
913 /* We can only do the GTT pwrite on untiled buffers, as otherwise
914 * it would end up going through the fenced access, and we'll get
915 * different detiling behavior between reading and writing.
916 * pread/pwrite currently are reading and writing from the CPU
917 * perspective, requiring manual detiling by the client.
920 ret
= i915_gem_phys_pwrite(dev
, obj
, args
, file
);
924 if (obj
->cache_level
== I915_CACHE_NONE
&&
925 obj
->tiling_mode
== I915_TILING_NONE
&&
926 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
927 ret
= i915_gem_gtt_pwrite_fast(dev
, obj
, args
, file
);
928 /* Note that the gtt paths might fail with non-page-backed user
929 * pointers (e.g. gtt mappings when moving data between
930 * textures). Fallback to the shmem path in that case. */
933 if (ret
== -EFAULT
|| ret
== -ENOSPC
)
934 ret
= i915_gem_shmem_pwrite(dev
, obj
, args
, file
);
937 drm_gem_object_unreference(&obj
->base
);
939 mutex_unlock(&dev
->struct_mutex
);
944 i915_gem_check_wedge(struct drm_i915_private
*dev_priv
,
947 if (atomic_read(&dev_priv
->mm
.wedged
)) {
948 struct completion
*x
= &dev_priv
->error_completion
;
949 bool recovery_complete
;
952 /* Give the error handler a chance to run. */
953 spin_lock_irqsave(&x
->wait
.lock
, flags
);
954 recovery_complete
= x
->done
> 0;
955 spin_unlock_irqrestore(&x
->wait
.lock
, flags
);
957 /* Non-interruptible callers can't handle -EAGAIN, hence return
958 * -EIO unconditionally for these. */
962 /* Recovery complete, but still wedged means reset failure. */
963 if (recovery_complete
)
973 * Compare seqno against outstanding lazy request. Emit a request if they are
977 i915_gem_check_olr(struct intel_ring_buffer
*ring
, u32 seqno
)
981 BUG_ON(!mutex_is_locked(&ring
->dev
->struct_mutex
));
984 if (seqno
== ring
->outstanding_lazy_request
)
985 ret
= i915_add_request(ring
, NULL
, NULL
);
991 * __wait_seqno - wait until execution of seqno has finished
992 * @ring: the ring expected to report seqno
994 * @interruptible: do an interruptible wait (normally yes)
995 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
997 * Returns 0 if the seqno was found within the alloted time. Else returns the
998 * errno with remaining time filled in timeout argument.
1000 static int __wait_seqno(struct intel_ring_buffer
*ring
, u32 seqno
,
1001 bool interruptible
, struct timespec
*timeout
)
1003 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
1004 struct timespec before
, now
, wait_time
={1,0};
1005 unsigned long timeout_jiffies
;
1007 bool wait_forever
= true;
1010 if (i915_seqno_passed(ring
->get_seqno(ring
, true), seqno
))
1013 trace_i915_gem_request_wait_begin(ring
, seqno
);
1015 if (timeout
!= NULL
) {
1016 wait_time
= *timeout
;
1017 wait_forever
= false;
1020 timeout_jiffies
= timespec_to_jiffies(&wait_time
);
1022 if (WARN_ON(!ring
->irq_get(ring
)))
1025 /* Record current time in case interrupted by signal, or wedged * */
1026 getrawmonotonic(&before
);
1029 (i915_seqno_passed(ring->get_seqno(ring, false), seqno) || \
1030 atomic_read(&dev_priv->mm.wedged))
1033 end
= wait_event_interruptible_timeout(ring
->irq_queue
,
1037 end
= wait_event_timeout(ring
->irq_queue
, EXIT_COND
,
1040 ret
= i915_gem_check_wedge(dev_priv
, interruptible
);
1043 } while (end
== 0 && wait_forever
);
1045 getrawmonotonic(&now
);
1047 ring
->irq_put(ring
);
1048 trace_i915_gem_request_wait_end(ring
, seqno
);
1052 struct timespec sleep_time
= timespec_sub(now
, before
);
1053 *timeout
= timespec_sub(*timeout
, sleep_time
);
1058 case -EAGAIN
: /* Wedged */
1059 case -ERESTARTSYS
: /* Signal */
1061 case 0: /* Timeout */
1063 set_normalized_timespec(timeout
, 0, 0);
1065 default: /* Completed */
1066 WARN_ON(end
< 0); /* We're not aware of other errors */
1072 * Waits for a sequence number to be signaled, and cleans up the
1073 * request and object lists appropriately for that event.
1076 i915_wait_seqno(struct intel_ring_buffer
*ring
, uint32_t seqno
)
1078 struct drm_device
*dev
= ring
->dev
;
1079 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1080 bool interruptible
= dev_priv
->mm
.interruptible
;
1083 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
1086 ret
= i915_gem_check_wedge(dev_priv
, interruptible
);
1090 ret
= i915_gem_check_olr(ring
, seqno
);
1094 return __wait_seqno(ring
, seqno
, interruptible
, NULL
);
1098 * Ensures that all rendering to the object has completed and the object is
1099 * safe to unbind from the GTT or access from the CPU.
1101 static __must_check
int
1102 i915_gem_object_wait_rendering(struct drm_i915_gem_object
*obj
,
1105 struct intel_ring_buffer
*ring
= obj
->ring
;
1109 seqno
= readonly
? obj
->last_write_seqno
: obj
->last_read_seqno
;
1113 ret
= i915_wait_seqno(ring
, seqno
);
1117 i915_gem_retire_requests_ring(ring
);
1119 /* Manually manage the write flush as we may have not yet
1120 * retired the buffer.
1122 if (obj
->last_write_seqno
&&
1123 i915_seqno_passed(seqno
, obj
->last_write_seqno
)) {
1124 obj
->last_write_seqno
= 0;
1125 obj
->base
.write_domain
&= ~I915_GEM_GPU_DOMAINS
;
1131 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1132 * as the object state may change during this call.
1134 static __must_check
int
1135 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object
*obj
,
1138 struct drm_device
*dev
= obj
->base
.dev
;
1139 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1140 struct intel_ring_buffer
*ring
= obj
->ring
;
1144 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
1145 BUG_ON(!dev_priv
->mm
.interruptible
);
1147 seqno
= readonly
? obj
->last_write_seqno
: obj
->last_read_seqno
;
1151 ret
= i915_gem_check_wedge(dev_priv
, true);
1155 ret
= i915_gem_check_olr(ring
, seqno
);
1159 mutex_unlock(&dev
->struct_mutex
);
1160 ret
= __wait_seqno(ring
, seqno
, true, NULL
);
1161 mutex_lock(&dev
->struct_mutex
);
1163 i915_gem_retire_requests_ring(ring
);
1165 /* Manually manage the write flush as we may have not yet
1166 * retired the buffer.
1168 if (obj
->last_write_seqno
&&
1169 i915_seqno_passed(seqno
, obj
->last_write_seqno
)) {
1170 obj
->last_write_seqno
= 0;
1171 obj
->base
.write_domain
&= ~I915_GEM_GPU_DOMAINS
;
1178 * Called when user space prepares to use an object with the CPU, either
1179 * through the mmap ioctl's mapping or a GTT mapping.
1182 i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
1183 struct drm_file
*file
)
1185 struct drm_i915_gem_set_domain
*args
= data
;
1186 struct drm_i915_gem_object
*obj
;
1187 uint32_t read_domains
= args
->read_domains
;
1188 uint32_t write_domain
= args
->write_domain
;
1191 /* Only handle setting domains to types used by the CPU. */
1192 if (write_domain
& I915_GEM_GPU_DOMAINS
)
1195 if (read_domains
& I915_GEM_GPU_DOMAINS
)
1198 /* Having something in the write domain implies it's in the read
1199 * domain, and only that read domain. Enforce that in the request.
1201 if (write_domain
!= 0 && read_domains
!= write_domain
)
1204 ret
= i915_mutex_lock_interruptible(dev
);
1208 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1209 if (&obj
->base
== NULL
) {
1214 /* Try to flush the object off the GPU without holding the lock.
1215 * We will repeat the flush holding the lock in the normal manner
1216 * to catch cases where we are gazumped.
1218 ret
= i915_gem_object_wait_rendering__nonblocking(obj
, !write_domain
);
1222 if (read_domains
& I915_GEM_DOMAIN_GTT
) {
1223 ret
= i915_gem_object_set_to_gtt_domain(obj
, write_domain
!= 0);
1225 /* Silently promote "you're not bound, there was nothing to do"
1226 * to success, since the client was just asking us to
1227 * make sure everything was done.
1232 ret
= i915_gem_object_set_to_cpu_domain(obj
, write_domain
!= 0);
1236 drm_gem_object_unreference(&obj
->base
);
1238 mutex_unlock(&dev
->struct_mutex
);
1243 * Called when user space has done writes to this buffer
1246 i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1247 struct drm_file
*file
)
1249 struct drm_i915_gem_sw_finish
*args
= data
;
1250 struct drm_i915_gem_object
*obj
;
1253 ret
= i915_mutex_lock_interruptible(dev
);
1257 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1258 if (&obj
->base
== NULL
) {
1263 /* Pinned buffers may be scanout, so flush the cache */
1265 i915_gem_object_flush_cpu_write_domain(obj
);
1267 drm_gem_object_unreference(&obj
->base
);
1269 mutex_unlock(&dev
->struct_mutex
);
1274 * Maps the contents of an object, returning the address it is mapped
1277 * While the mapping holds a reference on the contents of the object, it doesn't
1278 * imply a ref on the object itself.
1281 i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1282 struct drm_file
*file
)
1284 struct drm_i915_gem_mmap
*args
= data
;
1285 struct drm_gem_object
*obj
;
1288 obj
= drm_gem_object_lookup(dev
, file
, args
->handle
);
1292 /* prime objects have no backing filp to GEM mmap
1296 drm_gem_object_unreference_unlocked(obj
);
1300 addr
= vm_mmap(obj
->filp
, 0, args
->size
,
1301 PROT_READ
| PROT_WRITE
, MAP_SHARED
,
1303 drm_gem_object_unreference_unlocked(obj
);
1304 if (IS_ERR((void *)addr
))
1307 args
->addr_ptr
= (uint64_t) addr
;
1313 * i915_gem_fault - fault a page into the GTT
1314 * vma: VMA in question
1317 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1318 * from userspace. The fault handler takes care of binding the object to
1319 * the GTT (if needed), allocating and programming a fence register (again,
1320 * only if needed based on whether the old reg is still valid or the object
1321 * is tiled) and inserting a new PTE into the faulting process.
1323 * Note that the faulting process may involve evicting existing objects
1324 * from the GTT and/or fence registers to make room. So performance may
1325 * suffer if the GTT working set is large or there are few fence registers
1328 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
)
1330 struct drm_i915_gem_object
*obj
= to_intel_bo(vma
->vm_private_data
);
1331 struct drm_device
*dev
= obj
->base
.dev
;
1332 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1333 pgoff_t page_offset
;
1336 bool write
= !!(vmf
->flags
& FAULT_FLAG_WRITE
);
1338 /* We don't use vmf->pgoff since that has the fake offset */
1339 page_offset
= ((unsigned long)vmf
->virtual_address
- vma
->vm_start
) >>
1342 ret
= i915_mutex_lock_interruptible(dev
);
1346 trace_i915_gem_object_fault(obj
, page_offset
, true, write
);
1348 /* Now bind it into the GTT if needed */
1349 if (!obj
->map_and_fenceable
) {
1350 ret
= i915_gem_object_unbind(obj
);
1354 if (!obj
->gtt_space
) {
1355 ret
= i915_gem_object_bind_to_gtt(obj
, 0, true, false);
1359 ret
= i915_gem_object_set_to_gtt_domain(obj
, write
);
1364 if (!obj
->has_global_gtt_mapping
)
1365 i915_gem_gtt_bind_object(obj
, obj
->cache_level
);
1367 ret
= i915_gem_object_get_fence(obj
);
1371 if (i915_gem_object_is_inactive(obj
))
1372 list_move_tail(&obj
->mm_list
, &dev_priv
->mm
.inactive_list
);
1374 obj
->fault_mappable
= true;
1376 pfn
= ((dev_priv
->mm
.gtt_base_addr
+ obj
->gtt_offset
) >> PAGE_SHIFT
) +
1379 /* Finally, remap it using the new GTT offset */
1380 ret
= vm_insert_pfn(vma
, (unsigned long)vmf
->virtual_address
, pfn
);
1382 mutex_unlock(&dev
->struct_mutex
);
1386 /* If this -EIO is due to a gpu hang, give the reset code a
1387 * chance to clean up the mess. Otherwise return the proper
1389 if (!atomic_read(&dev_priv
->mm
.wedged
))
1390 return VM_FAULT_SIGBUS
;
1392 /* Give the error handler a chance to run and move the
1393 * objects off the GPU active list. Next time we service the
1394 * fault, we should be able to transition the page into the
1395 * GTT without touching the GPU (and so avoid further
1396 * EIO/EGAIN). If the GPU is wedged, then there is no issue
1397 * with coherency, just lost writes.
1403 return VM_FAULT_NOPAGE
;
1405 return VM_FAULT_OOM
;
1407 return VM_FAULT_SIGBUS
;
1412 * i915_gem_release_mmap - remove physical page mappings
1413 * @obj: obj in question
1415 * Preserve the reservation of the mmapping with the DRM core code, but
1416 * relinquish ownership of the pages back to the system.
1418 * It is vital that we remove the page mapping if we have mapped a tiled
1419 * object through the GTT and then lose the fence register due to
1420 * resource pressure. Similarly if the object has been moved out of the
1421 * aperture, than pages mapped into userspace must be revoked. Removing the
1422 * mapping will then trigger a page fault on the next user access, allowing
1423 * fixup by i915_gem_fault().
1426 i915_gem_release_mmap(struct drm_i915_gem_object
*obj
)
1428 if (!obj
->fault_mappable
)
1431 if (obj
->base
.dev
->dev_mapping
)
1432 unmap_mapping_range(obj
->base
.dev
->dev_mapping
,
1433 (loff_t
)obj
->base
.map_list
.hash
.key
<<PAGE_SHIFT
,
1436 obj
->fault_mappable
= false;
1440 i915_gem_get_gtt_size(struct drm_device
*dev
, uint32_t size
, int tiling_mode
)
1444 if (INTEL_INFO(dev
)->gen
>= 4 ||
1445 tiling_mode
== I915_TILING_NONE
)
1448 /* Previous chips need a power-of-two fence region when tiling */
1449 if (INTEL_INFO(dev
)->gen
== 3)
1450 gtt_size
= 1024*1024;
1452 gtt_size
= 512*1024;
1454 while (gtt_size
< size
)
1461 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1462 * @obj: object to check
1464 * Return the required GTT alignment for an object, taking into account
1465 * potential fence register mapping.
1468 i915_gem_get_gtt_alignment(struct drm_device
*dev
,
1473 * Minimum alignment is 4k (GTT page size), but might be greater
1474 * if a fence register is needed for the object.
1476 if (INTEL_INFO(dev
)->gen
>= 4 ||
1477 tiling_mode
== I915_TILING_NONE
)
1481 * Previous chips need to be aligned to the size of the smallest
1482 * fence register that can contain the object.
1484 return i915_gem_get_gtt_size(dev
, size
, tiling_mode
);
1488 * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an
1491 * @size: size of the object
1492 * @tiling_mode: tiling mode of the object
1494 * Return the required GTT alignment for an object, only taking into account
1495 * unfenced tiled surface requirements.
1498 i915_gem_get_unfenced_gtt_alignment(struct drm_device
*dev
,
1503 * Minimum alignment is 4k (GTT page size) for sane hw.
1505 if (INTEL_INFO(dev
)->gen
>= 4 || IS_G33(dev
) ||
1506 tiling_mode
== I915_TILING_NONE
)
1509 /* Previous hardware however needs to be aligned to a power-of-two
1510 * tile height. The simplest method for determining this is to reuse
1511 * the power-of-tile object size.
1513 return i915_gem_get_gtt_size(dev
, size
, tiling_mode
);
1516 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object
*obj
)
1518 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
1521 if (obj
->base
.map_list
.map
)
1524 ret
= drm_gem_create_mmap_offset(&obj
->base
);
1528 /* Badly fragmented mmap space? The only way we can recover
1529 * space is by destroying unwanted objects. We can't randomly release
1530 * mmap_offsets as userspace expects them to be persistent for the
1531 * lifetime of the objects. The closest we can is to release the
1532 * offsets on purgeable objects by truncating it and marking it purged,
1533 * which prevents userspace from ever using that object again.
1535 i915_gem_purge(dev_priv
, obj
->base
.size
>> PAGE_SHIFT
);
1536 ret
= drm_gem_create_mmap_offset(&obj
->base
);
1540 i915_gem_shrink_all(dev_priv
);
1541 return drm_gem_create_mmap_offset(&obj
->base
);
1544 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object
*obj
)
1546 if (!obj
->base
.map_list
.map
)
1549 drm_gem_free_mmap_offset(&obj
->base
);
1553 i915_gem_mmap_gtt(struct drm_file
*file
,
1554 struct drm_device
*dev
,
1558 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1559 struct drm_i915_gem_object
*obj
;
1562 ret
= i915_mutex_lock_interruptible(dev
);
1566 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, handle
));
1567 if (&obj
->base
== NULL
) {
1572 if (obj
->base
.size
> dev_priv
->mm
.gtt_mappable_end
) {
1577 if (obj
->madv
!= I915_MADV_WILLNEED
) {
1578 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1583 ret
= i915_gem_object_create_mmap_offset(obj
);
1587 *offset
= (u64
)obj
->base
.map_list
.hash
.key
<< PAGE_SHIFT
;
1590 drm_gem_object_unreference(&obj
->base
);
1592 mutex_unlock(&dev
->struct_mutex
);
1597 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1599 * @data: GTT mapping ioctl data
1600 * @file: GEM object info
1602 * Simply returns the fake offset to userspace so it can mmap it.
1603 * The mmap call will end up in drm_gem_mmap(), which will set things
1604 * up so we can get faults in the handler above.
1606 * The fault handler will take care of binding the object into the GTT
1607 * (since it may have been evicted to make room for something), allocating
1608 * a fence register, and mapping the appropriate aperture address into
1612 i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
1613 struct drm_file
*file
)
1615 struct drm_i915_gem_mmap_gtt
*args
= data
;
1617 return i915_gem_mmap_gtt(file
, dev
, args
->handle
, &args
->offset
);
1620 /* Immediately discard the backing storage */
1622 i915_gem_object_truncate(struct drm_i915_gem_object
*obj
)
1624 struct inode
*inode
;
1626 i915_gem_object_free_mmap_offset(obj
);
1628 if (obj
->base
.filp
== NULL
)
1631 /* Our goal here is to return as much of the memory as
1632 * is possible back to the system as we are called from OOM.
1633 * To do this we must instruct the shmfs to drop all of its
1634 * backing pages, *now*.
1636 inode
= obj
->base
.filp
->f_path
.dentry
->d_inode
;
1637 shmem_truncate_range(inode
, 0, (loff_t
)-1);
1639 obj
->madv
= __I915_MADV_PURGED
;
1643 i915_gem_object_is_purgeable(struct drm_i915_gem_object
*obj
)
1645 return obj
->madv
== I915_MADV_DONTNEED
;
1649 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object
*obj
)
1651 int page_count
= obj
->base
.size
/ PAGE_SIZE
;
1652 struct scatterlist
*sg
;
1655 BUG_ON(obj
->madv
== __I915_MADV_PURGED
);
1657 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
1659 /* In the event of a disaster, abandon all caches and
1660 * hope for the best.
1662 WARN_ON(ret
!= -EIO
);
1663 i915_gem_clflush_object(obj
);
1664 obj
->base
.read_domains
= obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
1667 if (i915_gem_object_needs_bit17_swizzle(obj
))
1668 i915_gem_object_save_bit_17_swizzle(obj
);
1670 if (obj
->madv
== I915_MADV_DONTNEED
)
1673 for_each_sg(obj
->pages
->sgl
, sg
, page_count
, i
) {
1674 struct page
*page
= sg_page(sg
);
1677 set_page_dirty(page
);
1679 if (obj
->madv
== I915_MADV_WILLNEED
)
1680 mark_page_accessed(page
);
1682 page_cache_release(page
);
1686 sg_free_table(obj
->pages
);
1691 i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
)
1693 const struct drm_i915_gem_object_ops
*ops
= obj
->ops
;
1695 if (obj
->pages
== NULL
)
1698 BUG_ON(obj
->gtt_space
);
1700 if (obj
->pages_pin_count
)
1703 ops
->put_pages(obj
);
1706 list_del(&obj
->gtt_list
);
1707 if (i915_gem_object_is_purgeable(obj
))
1708 i915_gem_object_truncate(obj
);
1714 i915_gem_purge(struct drm_i915_private
*dev_priv
, long target
)
1716 struct drm_i915_gem_object
*obj
, *next
;
1719 list_for_each_entry_safe(obj
, next
,
1720 &dev_priv
->mm
.unbound_list
,
1722 if (i915_gem_object_is_purgeable(obj
) &&
1723 i915_gem_object_put_pages(obj
) == 0) {
1724 count
+= obj
->base
.size
>> PAGE_SHIFT
;
1725 if (count
>= target
)
1730 list_for_each_entry_safe(obj
, next
,
1731 &dev_priv
->mm
.inactive_list
,
1733 if (i915_gem_object_is_purgeable(obj
) &&
1734 i915_gem_object_unbind(obj
) == 0 &&
1735 i915_gem_object_put_pages(obj
) == 0) {
1736 count
+= obj
->base
.size
>> PAGE_SHIFT
;
1737 if (count
>= target
)
1746 i915_gem_shrink_all(struct drm_i915_private
*dev_priv
)
1748 struct drm_i915_gem_object
*obj
, *next
;
1750 i915_gem_evict_everything(dev_priv
->dev
);
1752 list_for_each_entry_safe(obj
, next
, &dev_priv
->mm
.unbound_list
, gtt_list
)
1753 i915_gem_object_put_pages(obj
);
1757 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object
*obj
)
1759 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
1761 struct address_space
*mapping
;
1762 struct sg_table
*st
;
1763 struct scatterlist
*sg
;
1767 /* Assert that the object is not currently in any GPU domain. As it
1768 * wasn't in the GTT, there shouldn't be any way it could have been in
1771 BUG_ON(obj
->base
.read_domains
& I915_GEM_GPU_DOMAINS
);
1772 BUG_ON(obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
);
1774 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
1778 page_count
= obj
->base
.size
/ PAGE_SIZE
;
1779 if (sg_alloc_table(st
, page_count
, GFP_KERNEL
)) {
1785 /* Get the list of pages out of our struct file. They'll be pinned
1786 * at this point until we release them.
1788 * Fail silently without starting the shrinker
1790 mapping
= obj
->base
.filp
->f_path
.dentry
->d_inode
->i_mapping
;
1791 gfp
= mapping_gfp_mask(mapping
);
1792 gfp
|= __GFP_NORETRY
| __GFP_NOWARN
;
1793 gfp
&= ~(__GFP_IO
| __GFP_WAIT
);
1794 for_each_sg(st
->sgl
, sg
, page_count
, i
) {
1795 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
1797 i915_gem_purge(dev_priv
, page_count
);
1798 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
1801 /* We've tried hard to allocate the memory by reaping
1802 * our own buffer, now let the real VM do its job and
1803 * go down in flames if truly OOM.
1805 gfp
&= ~(__GFP_NORETRY
| __GFP_NOWARN
);
1806 gfp
|= __GFP_IO
| __GFP_WAIT
;
1808 i915_gem_shrink_all(dev_priv
);
1809 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
1813 gfp
|= __GFP_NORETRY
| __GFP_NOWARN
;
1814 gfp
&= ~(__GFP_IO
| __GFP_WAIT
);
1817 sg_set_page(sg
, page
, PAGE_SIZE
, 0);
1820 if (i915_gem_object_needs_bit17_swizzle(obj
))
1821 i915_gem_object_do_bit_17_swizzle(obj
);
1827 for_each_sg(st
->sgl
, sg
, i
, page_count
)
1828 page_cache_release(sg_page(sg
));
1831 return PTR_ERR(page
);
1834 /* Ensure that the associated pages are gathered from the backing storage
1835 * and pinned into our object. i915_gem_object_get_pages() may be called
1836 * multiple times before they are released by a single call to
1837 * i915_gem_object_put_pages() - once the pages are no longer referenced
1838 * either as a result of memory pressure (reaping pages under the shrinker)
1839 * or as the object is itself released.
1842 i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
)
1844 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
1845 const struct drm_i915_gem_object_ops
*ops
= obj
->ops
;
1851 BUG_ON(obj
->pages_pin_count
);
1853 ret
= ops
->get_pages(obj
);
1857 list_add_tail(&obj
->gtt_list
, &dev_priv
->mm
.unbound_list
);
1862 i915_gem_object_move_to_active(struct drm_i915_gem_object
*obj
,
1863 struct intel_ring_buffer
*ring
,
1866 struct drm_device
*dev
= obj
->base
.dev
;
1867 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1869 BUG_ON(ring
== NULL
);
1872 /* Add a reference if we're newly entering the active list. */
1874 drm_gem_object_reference(&obj
->base
);
1878 /* Move from whatever list we were on to the tail of execution. */
1879 list_move_tail(&obj
->mm_list
, &dev_priv
->mm
.active_list
);
1880 list_move_tail(&obj
->ring_list
, &ring
->active_list
);
1882 obj
->last_read_seqno
= seqno
;
1884 if (obj
->fenced_gpu_access
) {
1885 obj
->last_fenced_seqno
= seqno
;
1887 /* Bump MRU to take account of the delayed flush */
1888 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
1889 struct drm_i915_fence_reg
*reg
;
1891 reg
= &dev_priv
->fence_regs
[obj
->fence_reg
];
1892 list_move_tail(®
->lru_list
,
1893 &dev_priv
->mm
.fence_list
);
1899 i915_gem_object_move_to_inactive(struct drm_i915_gem_object
*obj
)
1901 struct drm_device
*dev
= obj
->base
.dev
;
1902 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1904 BUG_ON(obj
->base
.write_domain
& ~I915_GEM_GPU_DOMAINS
);
1905 BUG_ON(!obj
->active
);
1907 if (obj
->pin_count
) /* are we a framebuffer? */
1908 intel_mark_fb_idle(obj
);
1910 list_move_tail(&obj
->mm_list
, &dev_priv
->mm
.inactive_list
);
1912 list_del_init(&obj
->ring_list
);
1915 obj
->last_read_seqno
= 0;
1916 obj
->last_write_seqno
= 0;
1917 obj
->base
.write_domain
= 0;
1919 obj
->last_fenced_seqno
= 0;
1920 obj
->fenced_gpu_access
= false;
1923 drm_gem_object_unreference(&obj
->base
);
1925 WARN_ON(i915_verify_lists(dev
));
1929 i915_gem_get_seqno(struct drm_device
*dev
)
1931 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1932 u32 seqno
= dev_priv
->next_seqno
;
1934 /* reserve 0 for non-seqno */
1935 if (++dev_priv
->next_seqno
== 0)
1936 dev_priv
->next_seqno
= 1;
1942 i915_gem_next_request_seqno(struct intel_ring_buffer
*ring
)
1944 if (ring
->outstanding_lazy_request
== 0)
1945 ring
->outstanding_lazy_request
= i915_gem_get_seqno(ring
->dev
);
1947 return ring
->outstanding_lazy_request
;
1951 i915_add_request(struct intel_ring_buffer
*ring
,
1952 struct drm_file
*file
,
1953 struct drm_i915_gem_request
*request
)
1955 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
1957 u32 request_ring_position
;
1962 * Emit any outstanding flushes - execbuf can fail to emit the flush
1963 * after having emitted the batchbuffer command. Hence we need to fix
1964 * things up similar to emitting the lazy request. The difference here
1965 * is that the flush _must_ happen before the next request, no matter
1968 ret
= intel_ring_flush_all_caches(ring
);
1972 if (request
== NULL
) {
1973 request
= kmalloc(sizeof(*request
), GFP_KERNEL
);
1974 if (request
== NULL
)
1978 seqno
= i915_gem_next_request_seqno(ring
);
1980 /* Record the position of the start of the request so that
1981 * should we detect the updated seqno part-way through the
1982 * GPU processing the request, we never over-estimate the
1983 * position of the head.
1985 request_ring_position
= intel_ring_get_tail(ring
);
1987 ret
= ring
->add_request(ring
, &seqno
);
1993 trace_i915_gem_request_add(ring
, seqno
);
1995 request
->seqno
= seqno
;
1996 request
->ring
= ring
;
1997 request
->tail
= request_ring_position
;
1998 request
->emitted_jiffies
= jiffies
;
1999 was_empty
= list_empty(&ring
->request_list
);
2000 list_add_tail(&request
->list
, &ring
->request_list
);
2001 request
->file_priv
= NULL
;
2004 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
2006 spin_lock(&file_priv
->mm
.lock
);
2007 request
->file_priv
= file_priv
;
2008 list_add_tail(&request
->client_list
,
2009 &file_priv
->mm
.request_list
);
2010 spin_unlock(&file_priv
->mm
.lock
);
2013 ring
->outstanding_lazy_request
= 0;
2015 if (!dev_priv
->mm
.suspended
) {
2016 if (i915_enable_hangcheck
) {
2017 mod_timer(&dev_priv
->hangcheck_timer
,
2019 msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD
));
2022 queue_delayed_work(dev_priv
->wq
,
2023 &dev_priv
->mm
.retire_work
, HZ
);
2024 intel_mark_busy(dev_priv
->dev
);
2032 i915_gem_request_remove_from_client(struct drm_i915_gem_request
*request
)
2034 struct drm_i915_file_private
*file_priv
= request
->file_priv
;
2039 spin_lock(&file_priv
->mm
.lock
);
2040 if (request
->file_priv
) {
2041 list_del(&request
->client_list
);
2042 request
->file_priv
= NULL
;
2044 spin_unlock(&file_priv
->mm
.lock
);
2047 static void i915_gem_reset_ring_lists(struct drm_i915_private
*dev_priv
,
2048 struct intel_ring_buffer
*ring
)
2050 while (!list_empty(&ring
->request_list
)) {
2051 struct drm_i915_gem_request
*request
;
2053 request
= list_first_entry(&ring
->request_list
,
2054 struct drm_i915_gem_request
,
2057 list_del(&request
->list
);
2058 i915_gem_request_remove_from_client(request
);
2062 while (!list_empty(&ring
->active_list
)) {
2063 struct drm_i915_gem_object
*obj
;
2065 obj
= list_first_entry(&ring
->active_list
,
2066 struct drm_i915_gem_object
,
2069 i915_gem_object_move_to_inactive(obj
);
2073 static void i915_gem_reset_fences(struct drm_device
*dev
)
2075 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2078 for (i
= 0; i
< dev_priv
->num_fence_regs
; i
++) {
2079 struct drm_i915_fence_reg
*reg
= &dev_priv
->fence_regs
[i
];
2081 i915_gem_write_fence(dev
, i
, NULL
);
2084 i915_gem_object_fence_lost(reg
->obj
);
2088 INIT_LIST_HEAD(®
->lru_list
);
2091 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
2094 void i915_gem_reset(struct drm_device
*dev
)
2096 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2097 struct drm_i915_gem_object
*obj
;
2098 struct intel_ring_buffer
*ring
;
2101 for_each_ring(ring
, dev_priv
, i
)
2102 i915_gem_reset_ring_lists(dev_priv
, ring
);
2104 /* Move everything out of the GPU domains to ensure we do any
2105 * necessary invalidation upon reuse.
2107 list_for_each_entry(obj
,
2108 &dev_priv
->mm
.inactive_list
,
2111 obj
->base
.read_domains
&= ~I915_GEM_GPU_DOMAINS
;
2114 /* The fence registers are invalidated so clear them out */
2115 i915_gem_reset_fences(dev
);
2119 * This function clears the request list as sequence numbers are passed.
2122 i915_gem_retire_requests_ring(struct intel_ring_buffer
*ring
)
2127 if (list_empty(&ring
->request_list
))
2130 WARN_ON(i915_verify_lists(ring
->dev
));
2132 seqno
= ring
->get_seqno(ring
, true);
2134 for (i
= 0; i
< ARRAY_SIZE(ring
->sync_seqno
); i
++)
2135 if (seqno
>= ring
->sync_seqno
[i
])
2136 ring
->sync_seqno
[i
] = 0;
2138 while (!list_empty(&ring
->request_list
)) {
2139 struct drm_i915_gem_request
*request
;
2141 request
= list_first_entry(&ring
->request_list
,
2142 struct drm_i915_gem_request
,
2145 if (!i915_seqno_passed(seqno
, request
->seqno
))
2148 trace_i915_gem_request_retire(ring
, request
->seqno
);
2149 /* We know the GPU must have read the request to have
2150 * sent us the seqno + interrupt, so use the position
2151 * of tail of the request to update the last known position
2154 ring
->last_retired_head
= request
->tail
;
2156 list_del(&request
->list
);
2157 i915_gem_request_remove_from_client(request
);
2161 /* Move any buffers on the active list that are no longer referenced
2162 * by the ringbuffer to the flushing/inactive lists as appropriate.
2164 while (!list_empty(&ring
->active_list
)) {
2165 struct drm_i915_gem_object
*obj
;
2167 obj
= list_first_entry(&ring
->active_list
,
2168 struct drm_i915_gem_object
,
2171 if (!i915_seqno_passed(seqno
, obj
->last_read_seqno
))
2174 i915_gem_object_move_to_inactive(obj
);
2177 if (unlikely(ring
->trace_irq_seqno
&&
2178 i915_seqno_passed(seqno
, ring
->trace_irq_seqno
))) {
2179 ring
->irq_put(ring
);
2180 ring
->trace_irq_seqno
= 0;
2183 WARN_ON(i915_verify_lists(ring
->dev
));
2187 i915_gem_retire_requests(struct drm_device
*dev
)
2189 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2190 struct intel_ring_buffer
*ring
;
2193 for_each_ring(ring
, dev_priv
, i
)
2194 i915_gem_retire_requests_ring(ring
);
2198 i915_gem_retire_work_handler(struct work_struct
*work
)
2200 drm_i915_private_t
*dev_priv
;
2201 struct drm_device
*dev
;
2202 struct intel_ring_buffer
*ring
;
2206 dev_priv
= container_of(work
, drm_i915_private_t
,
2207 mm
.retire_work
.work
);
2208 dev
= dev_priv
->dev
;
2210 /* Come back later if the device is busy... */
2211 if (!mutex_trylock(&dev
->struct_mutex
)) {
2212 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, HZ
);
2216 i915_gem_retire_requests(dev
);
2218 /* Send a periodic flush down the ring so we don't hold onto GEM
2219 * objects indefinitely.
2222 for_each_ring(ring
, dev_priv
, i
) {
2223 if (ring
->gpu_caches_dirty
)
2224 i915_add_request(ring
, NULL
, NULL
);
2226 idle
&= list_empty(&ring
->request_list
);
2229 if (!dev_priv
->mm
.suspended
&& !idle
)
2230 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, HZ
);
2232 intel_mark_idle(dev
);
2234 mutex_unlock(&dev
->struct_mutex
);
2238 * Ensures that an object will eventually get non-busy by flushing any required
2239 * write domains, emitting any outstanding lazy request and retiring and
2240 * completed requests.
2243 i915_gem_object_flush_active(struct drm_i915_gem_object
*obj
)
2248 ret
= i915_gem_check_olr(obj
->ring
, obj
->last_read_seqno
);
2252 i915_gem_retire_requests_ring(obj
->ring
);
2259 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2260 * @DRM_IOCTL_ARGS: standard ioctl arguments
2262 * Returns 0 if successful, else an error is returned with the remaining time in
2263 * the timeout parameter.
2264 * -ETIME: object is still busy after timeout
2265 * -ERESTARTSYS: signal interrupted the wait
2266 * -ENONENT: object doesn't exist
2267 * Also possible, but rare:
2268 * -EAGAIN: GPU wedged
2270 * -ENODEV: Internal IRQ fail
2271 * -E?: The add request failed
2273 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2274 * non-zero timeout parameter the wait ioctl will wait for the given number of
2275 * nanoseconds on an object becoming unbusy. Since the wait itself does so
2276 * without holding struct_mutex the object may become re-busied before this
2277 * function completes. A similar but shorter * race condition exists in the busy
2281 i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
, struct drm_file
*file
)
2283 struct drm_i915_gem_wait
*args
= data
;
2284 struct drm_i915_gem_object
*obj
;
2285 struct intel_ring_buffer
*ring
= NULL
;
2286 struct timespec timeout_stack
, *timeout
= NULL
;
2290 if (args
->timeout_ns
>= 0) {
2291 timeout_stack
= ns_to_timespec(args
->timeout_ns
);
2292 timeout
= &timeout_stack
;
2295 ret
= i915_mutex_lock_interruptible(dev
);
2299 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->bo_handle
));
2300 if (&obj
->base
== NULL
) {
2301 mutex_unlock(&dev
->struct_mutex
);
2305 /* Need to make sure the object gets inactive eventually. */
2306 ret
= i915_gem_object_flush_active(obj
);
2311 seqno
= obj
->last_read_seqno
;
2318 /* Do this after OLR check to make sure we make forward progress polling
2319 * on this IOCTL with a 0 timeout (like busy ioctl)
2321 if (!args
->timeout_ns
) {
2326 drm_gem_object_unreference(&obj
->base
);
2327 mutex_unlock(&dev
->struct_mutex
);
2329 ret
= __wait_seqno(ring
, seqno
, true, timeout
);
2331 WARN_ON(!timespec_valid(timeout
));
2332 args
->timeout_ns
= timespec_to_ns(timeout
);
2337 drm_gem_object_unreference(&obj
->base
);
2338 mutex_unlock(&dev
->struct_mutex
);
2343 * i915_gem_object_sync - sync an object to a ring.
2345 * @obj: object which may be in use on another ring.
2346 * @to: ring we wish to use the object on. May be NULL.
2348 * This code is meant to abstract object synchronization with the GPU.
2349 * Calling with NULL implies synchronizing the object with the CPU
2350 * rather than a particular GPU ring.
2352 * Returns 0 if successful, else propagates up the lower layer error.
2355 i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
2356 struct intel_ring_buffer
*to
)
2358 struct intel_ring_buffer
*from
= obj
->ring
;
2362 if (from
== NULL
|| to
== from
)
2365 if (to
== NULL
|| !i915_semaphore_is_enabled(obj
->base
.dev
))
2366 return i915_gem_object_wait_rendering(obj
, false);
2368 idx
= intel_ring_sync_index(from
, to
);
2370 seqno
= obj
->last_read_seqno
;
2371 if (seqno
<= from
->sync_seqno
[idx
])
2374 ret
= i915_gem_check_olr(obj
->ring
, seqno
);
2378 ret
= to
->sync_to(to
, from
, seqno
);
2380 from
->sync_seqno
[idx
] = seqno
;
2385 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object
*obj
)
2387 u32 old_write_domain
, old_read_domains
;
2389 /* Act a barrier for all accesses through the GTT */
2392 /* Force a pagefault for domain tracking on next user access */
2393 i915_gem_release_mmap(obj
);
2395 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
) == 0)
2398 old_read_domains
= obj
->base
.read_domains
;
2399 old_write_domain
= obj
->base
.write_domain
;
2401 obj
->base
.read_domains
&= ~I915_GEM_DOMAIN_GTT
;
2402 obj
->base
.write_domain
&= ~I915_GEM_DOMAIN_GTT
;
2404 trace_i915_gem_object_change_domain(obj
,
2410 * Unbinds an object from the GTT aperture.
2413 i915_gem_object_unbind(struct drm_i915_gem_object
*obj
)
2415 drm_i915_private_t
*dev_priv
= obj
->base
.dev
->dev_private
;
2418 if (obj
->gtt_space
== NULL
)
2424 BUG_ON(obj
->pages
== NULL
);
2426 ret
= i915_gem_object_finish_gpu(obj
);
2429 /* Continue on if we fail due to EIO, the GPU is hung so we
2430 * should be safe and we need to cleanup or else we might
2431 * cause memory corruption through use-after-free.
2434 i915_gem_object_finish_gtt(obj
);
2436 /* release the fence reg _after_ flushing */
2437 ret
= i915_gem_object_put_fence(obj
);
2441 trace_i915_gem_object_unbind(obj
);
2443 if (obj
->has_global_gtt_mapping
)
2444 i915_gem_gtt_unbind_object(obj
);
2445 if (obj
->has_aliasing_ppgtt_mapping
) {
2446 i915_ppgtt_unbind_object(dev_priv
->mm
.aliasing_ppgtt
, obj
);
2447 obj
->has_aliasing_ppgtt_mapping
= 0;
2449 i915_gem_gtt_finish_object(obj
);
2451 list_del(&obj
->mm_list
);
2452 list_move_tail(&obj
->gtt_list
, &dev_priv
->mm
.unbound_list
);
2453 /* Avoid an unnecessary call to unbind on rebind. */
2454 obj
->map_and_fenceable
= true;
2456 drm_mm_put_block(obj
->gtt_space
);
2457 obj
->gtt_space
= NULL
;
2458 obj
->gtt_offset
= 0;
2463 static int i915_ring_idle(struct intel_ring_buffer
*ring
)
2465 if (list_empty(&ring
->active_list
))
2468 return i915_wait_seqno(ring
, i915_gem_next_request_seqno(ring
));
2471 int i915_gpu_idle(struct drm_device
*dev
)
2473 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2474 struct intel_ring_buffer
*ring
;
2477 /* Flush everything onto the inactive list. */
2478 for_each_ring(ring
, dev_priv
, i
) {
2479 ret
= i915_switch_context(ring
, NULL
, DEFAULT_CONTEXT_ID
);
2483 ret
= i915_ring_idle(ring
);
2491 static void sandybridge_write_fence_reg(struct drm_device
*dev
, int reg
,
2492 struct drm_i915_gem_object
*obj
)
2494 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2498 u32 size
= obj
->gtt_space
->size
;
2500 val
= (uint64_t)((obj
->gtt_offset
+ size
- 4096) &
2502 val
|= obj
->gtt_offset
& 0xfffff000;
2503 val
|= (uint64_t)((obj
->stride
/ 128) - 1) <<
2504 SANDYBRIDGE_FENCE_PITCH_SHIFT
;
2506 if (obj
->tiling_mode
== I915_TILING_Y
)
2507 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
2508 val
|= I965_FENCE_REG_VALID
;
2512 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0
+ reg
* 8, val
);
2513 POSTING_READ(FENCE_REG_SANDYBRIDGE_0
+ reg
* 8);
2516 static void i965_write_fence_reg(struct drm_device
*dev
, int reg
,
2517 struct drm_i915_gem_object
*obj
)
2519 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2523 u32 size
= obj
->gtt_space
->size
;
2525 val
= (uint64_t)((obj
->gtt_offset
+ size
- 4096) &
2527 val
|= obj
->gtt_offset
& 0xfffff000;
2528 val
|= ((obj
->stride
/ 128) - 1) << I965_FENCE_PITCH_SHIFT
;
2529 if (obj
->tiling_mode
== I915_TILING_Y
)
2530 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
2531 val
|= I965_FENCE_REG_VALID
;
2535 I915_WRITE64(FENCE_REG_965_0
+ reg
* 8, val
);
2536 POSTING_READ(FENCE_REG_965_0
+ reg
* 8);
2539 static void i915_write_fence_reg(struct drm_device
*dev
, int reg
,
2540 struct drm_i915_gem_object
*obj
)
2542 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2546 u32 size
= obj
->gtt_space
->size
;
2550 WARN((obj
->gtt_offset
& ~I915_FENCE_START_MASK
) ||
2551 (size
& -size
) != size
||
2552 (obj
->gtt_offset
& (size
- 1)),
2553 "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2554 obj
->gtt_offset
, obj
->map_and_fenceable
, size
);
2556 if (obj
->tiling_mode
== I915_TILING_Y
&& HAS_128_BYTE_Y_TILING(dev
))
2561 /* Note: pitch better be a power of two tile widths */
2562 pitch_val
= obj
->stride
/ tile_width
;
2563 pitch_val
= ffs(pitch_val
) - 1;
2565 val
= obj
->gtt_offset
;
2566 if (obj
->tiling_mode
== I915_TILING_Y
)
2567 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2568 val
|= I915_FENCE_SIZE_BITS(size
);
2569 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2570 val
|= I830_FENCE_REG_VALID
;
2575 reg
= FENCE_REG_830_0
+ reg
* 4;
2577 reg
= FENCE_REG_945_8
+ (reg
- 8) * 4;
2579 I915_WRITE(reg
, val
);
2583 static void i830_write_fence_reg(struct drm_device
*dev
, int reg
,
2584 struct drm_i915_gem_object
*obj
)
2586 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2590 u32 size
= obj
->gtt_space
->size
;
2593 WARN((obj
->gtt_offset
& ~I830_FENCE_START_MASK
) ||
2594 (size
& -size
) != size
||
2595 (obj
->gtt_offset
& (size
- 1)),
2596 "object 0x%08x not 512K or pot-size 0x%08x aligned\n",
2597 obj
->gtt_offset
, size
);
2599 pitch_val
= obj
->stride
/ 128;
2600 pitch_val
= ffs(pitch_val
) - 1;
2602 val
= obj
->gtt_offset
;
2603 if (obj
->tiling_mode
== I915_TILING_Y
)
2604 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2605 val
|= I830_FENCE_SIZE_BITS(size
);
2606 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2607 val
|= I830_FENCE_REG_VALID
;
2611 I915_WRITE(FENCE_REG_830_0
+ reg
* 4, val
);
2612 POSTING_READ(FENCE_REG_830_0
+ reg
* 4);
2615 static void i915_gem_write_fence(struct drm_device
*dev
, int reg
,
2616 struct drm_i915_gem_object
*obj
)
2618 switch (INTEL_INFO(dev
)->gen
) {
2620 case 6: sandybridge_write_fence_reg(dev
, reg
, obj
); break;
2622 case 4: i965_write_fence_reg(dev
, reg
, obj
); break;
2623 case 3: i915_write_fence_reg(dev
, reg
, obj
); break;
2624 case 2: i830_write_fence_reg(dev
, reg
, obj
); break;
2629 static inline int fence_number(struct drm_i915_private
*dev_priv
,
2630 struct drm_i915_fence_reg
*fence
)
2632 return fence
- dev_priv
->fence_regs
;
2635 static void i915_gem_object_update_fence(struct drm_i915_gem_object
*obj
,
2636 struct drm_i915_fence_reg
*fence
,
2639 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2640 int reg
= fence_number(dev_priv
, fence
);
2642 i915_gem_write_fence(obj
->base
.dev
, reg
, enable
? obj
: NULL
);
2645 obj
->fence_reg
= reg
;
2647 list_move_tail(&fence
->lru_list
, &dev_priv
->mm
.fence_list
);
2649 obj
->fence_reg
= I915_FENCE_REG_NONE
;
2651 list_del_init(&fence
->lru_list
);
2656 i915_gem_object_flush_fence(struct drm_i915_gem_object
*obj
)
2658 if (obj
->last_fenced_seqno
) {
2659 int ret
= i915_wait_seqno(obj
->ring
, obj
->last_fenced_seqno
);
2663 obj
->last_fenced_seqno
= 0;
2666 /* Ensure that all CPU reads are completed before installing a fence
2667 * and all writes before removing the fence.
2669 if (obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
)
2672 obj
->fenced_gpu_access
= false;
2677 i915_gem_object_put_fence(struct drm_i915_gem_object
*obj
)
2679 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2682 ret
= i915_gem_object_flush_fence(obj
);
2686 if (obj
->fence_reg
== I915_FENCE_REG_NONE
)
2689 i915_gem_object_update_fence(obj
,
2690 &dev_priv
->fence_regs
[obj
->fence_reg
],
2692 i915_gem_object_fence_lost(obj
);
2697 static struct drm_i915_fence_reg
*
2698 i915_find_fence_reg(struct drm_device
*dev
)
2700 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2701 struct drm_i915_fence_reg
*reg
, *avail
;
2704 /* First try to find a free reg */
2706 for (i
= dev_priv
->fence_reg_start
; i
< dev_priv
->num_fence_regs
; i
++) {
2707 reg
= &dev_priv
->fence_regs
[i
];
2711 if (!reg
->pin_count
)
2718 /* None available, try to steal one or wait for a user to finish */
2719 list_for_each_entry(reg
, &dev_priv
->mm
.fence_list
, lru_list
) {
2730 * i915_gem_object_get_fence - set up fencing for an object
2731 * @obj: object to map through a fence reg
2733 * When mapping objects through the GTT, userspace wants to be able to write
2734 * to them without having to worry about swizzling if the object is tiled.
2735 * This function walks the fence regs looking for a free one for @obj,
2736 * stealing one if it can't find any.
2738 * It then sets up the reg based on the object's properties: address, pitch
2739 * and tiling format.
2741 * For an untiled surface, this removes any existing fence.
2744 i915_gem_object_get_fence(struct drm_i915_gem_object
*obj
)
2746 struct drm_device
*dev
= obj
->base
.dev
;
2747 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2748 bool enable
= obj
->tiling_mode
!= I915_TILING_NONE
;
2749 struct drm_i915_fence_reg
*reg
;
2752 /* Have we updated the tiling parameters upon the object and so
2753 * will need to serialise the write to the associated fence register?
2755 if (obj
->fence_dirty
) {
2756 ret
= i915_gem_object_flush_fence(obj
);
2761 /* Just update our place in the LRU if our fence is getting reused. */
2762 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
2763 reg
= &dev_priv
->fence_regs
[obj
->fence_reg
];
2764 if (!obj
->fence_dirty
) {
2765 list_move_tail(®
->lru_list
,
2766 &dev_priv
->mm
.fence_list
);
2769 } else if (enable
) {
2770 reg
= i915_find_fence_reg(dev
);
2775 struct drm_i915_gem_object
*old
= reg
->obj
;
2777 ret
= i915_gem_object_flush_fence(old
);
2781 i915_gem_object_fence_lost(old
);
2786 i915_gem_object_update_fence(obj
, reg
, enable
);
2787 obj
->fence_dirty
= false;
2792 static bool i915_gem_valid_gtt_space(struct drm_device
*dev
,
2793 struct drm_mm_node
*gtt_space
,
2794 unsigned long cache_level
)
2796 struct drm_mm_node
*other
;
2798 /* On non-LLC machines we have to be careful when putting differing
2799 * types of snoopable memory together to avoid the prefetcher
2800 * crossing memory domains and dieing.
2805 if (gtt_space
== NULL
)
2808 if (list_empty(>t_space
->node_list
))
2811 other
= list_entry(gtt_space
->node_list
.prev
, struct drm_mm_node
, node_list
);
2812 if (other
->allocated
&& !other
->hole_follows
&& other
->color
!= cache_level
)
2815 other
= list_entry(gtt_space
->node_list
.next
, struct drm_mm_node
, node_list
);
2816 if (other
->allocated
&& !gtt_space
->hole_follows
&& other
->color
!= cache_level
)
2822 static void i915_gem_verify_gtt(struct drm_device
*dev
)
2825 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2826 struct drm_i915_gem_object
*obj
;
2829 list_for_each_entry(obj
, &dev_priv
->mm
.gtt_list
, gtt_list
) {
2830 if (obj
->gtt_space
== NULL
) {
2831 printk(KERN_ERR
"object found on GTT list with no space reserved\n");
2836 if (obj
->cache_level
!= obj
->gtt_space
->color
) {
2837 printk(KERN_ERR
"object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n",
2838 obj
->gtt_space
->start
,
2839 obj
->gtt_space
->start
+ obj
->gtt_space
->size
,
2841 obj
->gtt_space
->color
);
2846 if (!i915_gem_valid_gtt_space(dev
,
2848 obj
->cache_level
)) {
2849 printk(KERN_ERR
"invalid GTT space found at [%08lx, %08lx] - color=%x\n",
2850 obj
->gtt_space
->start
,
2851 obj
->gtt_space
->start
+ obj
->gtt_space
->size
,
2863 * Finds free space in the GTT aperture and binds the object there.
2866 i915_gem_object_bind_to_gtt(struct drm_i915_gem_object
*obj
,
2868 bool map_and_fenceable
,
2871 struct drm_device
*dev
= obj
->base
.dev
;
2872 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2873 struct drm_mm_node
*free_space
;
2874 u32 size
, fence_size
, fence_alignment
, unfenced_alignment
;
2875 bool mappable
, fenceable
;
2878 if (obj
->madv
!= I915_MADV_WILLNEED
) {
2879 DRM_ERROR("Attempting to bind a purgeable object\n");
2883 fence_size
= i915_gem_get_gtt_size(dev
,
2886 fence_alignment
= i915_gem_get_gtt_alignment(dev
,
2889 unfenced_alignment
=
2890 i915_gem_get_unfenced_gtt_alignment(dev
,
2895 alignment
= map_and_fenceable
? fence_alignment
:
2897 if (map_and_fenceable
&& alignment
& (fence_alignment
- 1)) {
2898 DRM_ERROR("Invalid object alignment requested %u\n", alignment
);
2902 size
= map_and_fenceable
? fence_size
: obj
->base
.size
;
2904 /* If the object is bigger than the entire aperture, reject it early
2905 * before evicting everything in a vain attempt to find space.
2907 if (obj
->base
.size
>
2908 (map_and_fenceable
? dev_priv
->mm
.gtt_mappable_end
: dev_priv
->mm
.gtt_total
)) {
2909 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2913 ret
= i915_gem_object_get_pages(obj
);
2918 if (map_and_fenceable
)
2920 drm_mm_search_free_in_range_color(&dev_priv
->mm
.gtt_space
,
2921 size
, alignment
, obj
->cache_level
,
2922 0, dev_priv
->mm
.gtt_mappable_end
,
2925 free_space
= drm_mm_search_free_color(&dev_priv
->mm
.gtt_space
,
2926 size
, alignment
, obj
->cache_level
,
2929 if (free_space
!= NULL
) {
2930 if (map_and_fenceable
)
2932 drm_mm_get_block_range_generic(free_space
,
2933 size
, alignment
, obj
->cache_level
,
2934 0, dev_priv
->mm
.gtt_mappable_end
,
2938 drm_mm_get_block_generic(free_space
,
2939 size
, alignment
, obj
->cache_level
,
2942 if (obj
->gtt_space
== NULL
) {
2943 ret
= i915_gem_evict_something(dev
, size
, alignment
,
2952 if (WARN_ON(!i915_gem_valid_gtt_space(dev
,
2954 obj
->cache_level
))) {
2955 drm_mm_put_block(obj
->gtt_space
);
2956 obj
->gtt_space
= NULL
;
2961 ret
= i915_gem_gtt_prepare_object(obj
);
2963 drm_mm_put_block(obj
->gtt_space
);
2964 obj
->gtt_space
= NULL
;
2968 if (!dev_priv
->mm
.aliasing_ppgtt
)
2969 i915_gem_gtt_bind_object(obj
, obj
->cache_level
);
2971 list_move_tail(&obj
->gtt_list
, &dev_priv
->mm
.bound_list
);
2972 list_add_tail(&obj
->mm_list
, &dev_priv
->mm
.inactive_list
);
2974 obj
->gtt_offset
= obj
->gtt_space
->start
;
2977 obj
->gtt_space
->size
== fence_size
&&
2978 (obj
->gtt_space
->start
& (fence_alignment
- 1)) == 0;
2981 obj
->gtt_offset
+ obj
->base
.size
<= dev_priv
->mm
.gtt_mappable_end
;
2983 obj
->map_and_fenceable
= mappable
&& fenceable
;
2985 trace_i915_gem_object_bind(obj
, map_and_fenceable
);
2986 i915_gem_verify_gtt(dev
);
2991 i915_gem_clflush_object(struct drm_i915_gem_object
*obj
)
2993 /* If we don't have a page list set up, then we're not pinned
2994 * to GPU, and we can ignore the cache flush because it'll happen
2995 * again at bind time.
2997 if (obj
->pages
== NULL
)
3000 /* If the GPU is snooping the contents of the CPU cache,
3001 * we do not need to manually clear the CPU cache lines. However,
3002 * the caches are only snooped when the render cache is
3003 * flushed/invalidated. As we always have to emit invalidations
3004 * and flushes when moving into and out of the RENDER domain, correct
3005 * snooping behaviour occurs naturally as the result of our domain
3008 if (obj
->cache_level
!= I915_CACHE_NONE
)
3011 trace_i915_gem_object_clflush(obj
);
3013 drm_clflush_sg(obj
->pages
);
3016 /** Flushes the GTT write domain for the object if it's dirty. */
3018 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
)
3020 uint32_t old_write_domain
;
3022 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_GTT
)
3025 /* No actual flushing is required for the GTT write domain. Writes
3026 * to it immediately go to main memory as far as we know, so there's
3027 * no chipset flush. It also doesn't land in render cache.
3029 * However, we do have to enforce the order so that all writes through
3030 * the GTT land before any writes to the device, such as updates to
3035 old_write_domain
= obj
->base
.write_domain
;
3036 obj
->base
.write_domain
= 0;
3038 trace_i915_gem_object_change_domain(obj
,
3039 obj
->base
.read_domains
,
3043 /** Flushes the CPU write domain for the object if it's dirty. */
3045 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
)
3047 uint32_t old_write_domain
;
3049 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
)
3052 i915_gem_clflush_object(obj
);
3053 intel_gtt_chipset_flush();
3054 old_write_domain
= obj
->base
.write_domain
;
3055 obj
->base
.write_domain
= 0;
3057 trace_i915_gem_object_change_domain(obj
,
3058 obj
->base
.read_domains
,
3063 * Moves a single object to the GTT read, and possibly write domain.
3065 * This function returns when the move is complete, including waiting on
3069 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
, bool write
)
3071 drm_i915_private_t
*dev_priv
= obj
->base
.dev
->dev_private
;
3072 uint32_t old_write_domain
, old_read_domains
;
3075 /* Not valid to be called on unbound objects. */
3076 if (obj
->gtt_space
== NULL
)
3079 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_GTT
)
3082 ret
= i915_gem_object_wait_rendering(obj
, !write
);
3086 i915_gem_object_flush_cpu_write_domain(obj
);
3088 old_write_domain
= obj
->base
.write_domain
;
3089 old_read_domains
= obj
->base
.read_domains
;
3091 /* It should now be out of any other write domains, and we can update
3092 * the domain values for our changes.
3094 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
3095 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
3097 obj
->base
.read_domains
= I915_GEM_DOMAIN_GTT
;
3098 obj
->base
.write_domain
= I915_GEM_DOMAIN_GTT
;
3102 trace_i915_gem_object_change_domain(obj
,
3106 /* And bump the LRU for this access */
3107 if (i915_gem_object_is_inactive(obj
))
3108 list_move_tail(&obj
->mm_list
, &dev_priv
->mm
.inactive_list
);
3113 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
3114 enum i915_cache_level cache_level
)
3116 struct drm_device
*dev
= obj
->base
.dev
;
3117 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3120 if (obj
->cache_level
== cache_level
)
3123 if (obj
->pin_count
) {
3124 DRM_DEBUG("can not change the cache level of pinned objects\n");
3128 if (!i915_gem_valid_gtt_space(dev
, obj
->gtt_space
, cache_level
)) {
3129 ret
= i915_gem_object_unbind(obj
);
3134 if (obj
->gtt_space
) {
3135 ret
= i915_gem_object_finish_gpu(obj
);
3139 i915_gem_object_finish_gtt(obj
);
3141 /* Before SandyBridge, you could not use tiling or fence
3142 * registers with snooped memory, so relinquish any fences
3143 * currently pointing to our region in the aperture.
3145 if (INTEL_INFO(dev
)->gen
< 6) {
3146 ret
= i915_gem_object_put_fence(obj
);
3151 if (obj
->has_global_gtt_mapping
)
3152 i915_gem_gtt_bind_object(obj
, cache_level
);
3153 if (obj
->has_aliasing_ppgtt_mapping
)
3154 i915_ppgtt_bind_object(dev_priv
->mm
.aliasing_ppgtt
,
3157 obj
->gtt_space
->color
= cache_level
;
3160 if (cache_level
== I915_CACHE_NONE
) {
3161 u32 old_read_domains
, old_write_domain
;
3163 /* If we're coming from LLC cached, then we haven't
3164 * actually been tracking whether the data is in the
3165 * CPU cache or not, since we only allow one bit set
3166 * in obj->write_domain and have been skipping the clflushes.
3167 * Just set it to the CPU cache for now.
3169 WARN_ON(obj
->base
.write_domain
& ~I915_GEM_DOMAIN_CPU
);
3170 WARN_ON(obj
->base
.read_domains
& ~I915_GEM_DOMAIN_CPU
);
3172 old_read_domains
= obj
->base
.read_domains
;
3173 old_write_domain
= obj
->base
.write_domain
;
3175 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
3176 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
3178 trace_i915_gem_object_change_domain(obj
,
3183 obj
->cache_level
= cache_level
;
3184 i915_gem_verify_gtt(dev
);
3188 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
3189 struct drm_file
*file
)
3191 struct drm_i915_gem_caching
*args
= data
;
3192 struct drm_i915_gem_object
*obj
;
3195 ret
= i915_mutex_lock_interruptible(dev
);
3199 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3200 if (&obj
->base
== NULL
) {
3205 args
->caching
= obj
->cache_level
!= I915_CACHE_NONE
;
3207 drm_gem_object_unreference(&obj
->base
);
3209 mutex_unlock(&dev
->struct_mutex
);
3213 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
3214 struct drm_file
*file
)
3216 struct drm_i915_gem_caching
*args
= data
;
3217 struct drm_i915_gem_object
*obj
;
3218 enum i915_cache_level level
;
3221 ret
= i915_mutex_lock_interruptible(dev
);
3225 switch (args
->caching
) {
3226 case I915_CACHING_NONE
:
3227 level
= I915_CACHE_NONE
;
3229 case I915_CACHING_CACHED
:
3230 level
= I915_CACHE_LLC
;
3236 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3237 if (&obj
->base
== NULL
) {
3242 ret
= i915_gem_object_set_cache_level(obj
, level
);
3244 drm_gem_object_unreference(&obj
->base
);
3246 mutex_unlock(&dev
->struct_mutex
);
3251 * Prepare buffer for display plane (scanout, cursors, etc).
3252 * Can be called from an uninterruptible phase (modesetting) and allows
3253 * any flushes to be pipelined (for pageflips).
3256 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
3258 struct intel_ring_buffer
*pipelined
)
3260 u32 old_read_domains
, old_write_domain
;
3263 if (pipelined
!= obj
->ring
) {
3264 ret
= i915_gem_object_sync(obj
, pipelined
);
3269 /* The display engine is not coherent with the LLC cache on gen6. As
3270 * a result, we make sure that the pinning that is about to occur is
3271 * done with uncached PTEs. This is lowest common denominator for all
3274 * However for gen6+, we could do better by using the GFDT bit instead
3275 * of uncaching, which would allow us to flush all the LLC-cached data
3276 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3278 ret
= i915_gem_object_set_cache_level(obj
, I915_CACHE_NONE
);
3282 /* As the user may map the buffer once pinned in the display plane
3283 * (e.g. libkms for the bootup splash), we have to ensure that we
3284 * always use map_and_fenceable for all scanout buffers.
3286 ret
= i915_gem_object_pin(obj
, alignment
, true, false);
3290 i915_gem_object_flush_cpu_write_domain(obj
);
3292 old_write_domain
= obj
->base
.write_domain
;
3293 old_read_domains
= obj
->base
.read_domains
;
3295 /* It should now be out of any other write domains, and we can update
3296 * the domain values for our changes.
3298 obj
->base
.write_domain
= 0;
3299 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
3301 trace_i915_gem_object_change_domain(obj
,
3309 i915_gem_object_finish_gpu(struct drm_i915_gem_object
*obj
)
3313 if ((obj
->base
.read_domains
& I915_GEM_GPU_DOMAINS
) == 0)
3316 ret
= i915_gem_object_wait_rendering(obj
, false);
3320 /* Ensure that we invalidate the GPU's caches and TLBs. */
3321 obj
->base
.read_domains
&= ~I915_GEM_GPU_DOMAINS
;
3326 * Moves a single object to the CPU read, and possibly write domain.
3328 * This function returns when the move is complete, including waiting on
3332 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
)
3334 uint32_t old_write_domain
, old_read_domains
;
3337 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_CPU
)
3340 ret
= i915_gem_object_wait_rendering(obj
, !write
);
3344 i915_gem_object_flush_gtt_write_domain(obj
);
3346 old_write_domain
= obj
->base
.write_domain
;
3347 old_read_domains
= obj
->base
.read_domains
;
3349 /* Flush the CPU cache if it's still invalid. */
3350 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) == 0) {
3351 i915_gem_clflush_object(obj
);
3353 obj
->base
.read_domains
|= I915_GEM_DOMAIN_CPU
;
3356 /* It should now be out of any other write domains, and we can update
3357 * the domain values for our changes.
3359 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
3361 /* If we're writing through the CPU, then the GPU read domains will
3362 * need to be invalidated at next use.
3365 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
3366 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
3369 trace_i915_gem_object_change_domain(obj
,
3376 /* Throttle our rendering by waiting until the ring has completed our requests
3377 * emitted over 20 msec ago.
3379 * Note that if we were to use the current jiffies each time around the loop,
3380 * we wouldn't escape the function with any frames outstanding if the time to
3381 * render a frame was over 20ms.
3383 * This should get us reasonable parallelism between CPU and GPU but also
3384 * relatively low latency when blocking on a particular request to finish.
3387 i915_gem_ring_throttle(struct drm_device
*dev
, struct drm_file
*file
)
3389 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3390 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
3391 unsigned long recent_enough
= jiffies
- msecs_to_jiffies(20);
3392 struct drm_i915_gem_request
*request
;
3393 struct intel_ring_buffer
*ring
= NULL
;
3397 if (atomic_read(&dev_priv
->mm
.wedged
))
3400 spin_lock(&file_priv
->mm
.lock
);
3401 list_for_each_entry(request
, &file_priv
->mm
.request_list
, client_list
) {
3402 if (time_after_eq(request
->emitted_jiffies
, recent_enough
))
3405 ring
= request
->ring
;
3406 seqno
= request
->seqno
;
3408 spin_unlock(&file_priv
->mm
.lock
);
3413 ret
= __wait_seqno(ring
, seqno
, true, NULL
);
3415 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, 0);
3421 i915_gem_object_pin(struct drm_i915_gem_object
*obj
,
3423 bool map_and_fenceable
,
3428 if (WARN_ON(obj
->pin_count
== DRM_I915_GEM_OBJECT_MAX_PIN_COUNT
))
3431 if (obj
->gtt_space
!= NULL
) {
3432 if ((alignment
&& obj
->gtt_offset
& (alignment
- 1)) ||
3433 (map_and_fenceable
&& !obj
->map_and_fenceable
)) {
3434 WARN(obj
->pin_count
,
3435 "bo is already pinned with incorrect alignment:"
3436 " offset=%x, req.alignment=%x, req.map_and_fenceable=%d,"
3437 " obj->map_and_fenceable=%d\n",
3438 obj
->gtt_offset
, alignment
,
3440 obj
->map_and_fenceable
);
3441 ret
= i915_gem_object_unbind(obj
);
3447 if (obj
->gtt_space
== NULL
) {
3448 ret
= i915_gem_object_bind_to_gtt(obj
, alignment
,
3455 if (!obj
->has_global_gtt_mapping
&& map_and_fenceable
)
3456 i915_gem_gtt_bind_object(obj
, obj
->cache_level
);
3459 obj
->pin_mappable
|= map_and_fenceable
;
3465 i915_gem_object_unpin(struct drm_i915_gem_object
*obj
)
3467 BUG_ON(obj
->pin_count
== 0);
3468 BUG_ON(obj
->gtt_space
== NULL
);
3470 if (--obj
->pin_count
== 0)
3471 obj
->pin_mappable
= false;
3475 i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
3476 struct drm_file
*file
)
3478 struct drm_i915_gem_pin
*args
= data
;
3479 struct drm_i915_gem_object
*obj
;
3482 ret
= i915_mutex_lock_interruptible(dev
);
3486 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3487 if (&obj
->base
== NULL
) {
3492 if (obj
->madv
!= I915_MADV_WILLNEED
) {
3493 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3498 if (obj
->pin_filp
!= NULL
&& obj
->pin_filp
!= file
) {
3499 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3505 obj
->user_pin_count
++;
3506 obj
->pin_filp
= file
;
3507 if (obj
->user_pin_count
== 1) {
3508 ret
= i915_gem_object_pin(obj
, args
->alignment
, true, false);
3513 /* XXX - flush the CPU caches for pinned objects
3514 * as the X server doesn't manage domains yet
3516 i915_gem_object_flush_cpu_write_domain(obj
);
3517 args
->offset
= obj
->gtt_offset
;
3519 drm_gem_object_unreference(&obj
->base
);
3521 mutex_unlock(&dev
->struct_mutex
);
3526 i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
3527 struct drm_file
*file
)
3529 struct drm_i915_gem_pin
*args
= data
;
3530 struct drm_i915_gem_object
*obj
;
3533 ret
= i915_mutex_lock_interruptible(dev
);
3537 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3538 if (&obj
->base
== NULL
) {
3543 if (obj
->pin_filp
!= file
) {
3544 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3549 obj
->user_pin_count
--;
3550 if (obj
->user_pin_count
== 0) {
3551 obj
->pin_filp
= NULL
;
3552 i915_gem_object_unpin(obj
);
3556 drm_gem_object_unreference(&obj
->base
);
3558 mutex_unlock(&dev
->struct_mutex
);
3563 i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
3564 struct drm_file
*file
)
3566 struct drm_i915_gem_busy
*args
= data
;
3567 struct drm_i915_gem_object
*obj
;
3570 ret
= i915_mutex_lock_interruptible(dev
);
3574 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3575 if (&obj
->base
== NULL
) {
3580 /* Count all active objects as busy, even if they are currently not used
3581 * by the gpu. Users of this interface expect objects to eventually
3582 * become non-busy without any further actions, therefore emit any
3583 * necessary flushes here.
3585 ret
= i915_gem_object_flush_active(obj
);
3587 args
->busy
= obj
->active
;
3589 BUILD_BUG_ON(I915_NUM_RINGS
> 16);
3590 args
->busy
|= intel_ring_flag(obj
->ring
) << 16;
3593 drm_gem_object_unreference(&obj
->base
);
3595 mutex_unlock(&dev
->struct_mutex
);
3600 i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
3601 struct drm_file
*file_priv
)
3603 return i915_gem_ring_throttle(dev
, file_priv
);
3607 i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
3608 struct drm_file
*file_priv
)
3610 struct drm_i915_gem_madvise
*args
= data
;
3611 struct drm_i915_gem_object
*obj
;
3614 switch (args
->madv
) {
3615 case I915_MADV_DONTNEED
:
3616 case I915_MADV_WILLNEED
:
3622 ret
= i915_mutex_lock_interruptible(dev
);
3626 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file_priv
, args
->handle
));
3627 if (&obj
->base
== NULL
) {
3632 if (obj
->pin_count
) {
3637 if (obj
->madv
!= __I915_MADV_PURGED
)
3638 obj
->madv
= args
->madv
;
3640 /* if the object is no longer attached, discard its backing storage */
3641 if (i915_gem_object_is_purgeable(obj
) && obj
->pages
== NULL
)
3642 i915_gem_object_truncate(obj
);
3644 args
->retained
= obj
->madv
!= __I915_MADV_PURGED
;
3647 drm_gem_object_unreference(&obj
->base
);
3649 mutex_unlock(&dev
->struct_mutex
);
3653 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
3654 const struct drm_i915_gem_object_ops
*ops
)
3656 INIT_LIST_HEAD(&obj
->mm_list
);
3657 INIT_LIST_HEAD(&obj
->gtt_list
);
3658 INIT_LIST_HEAD(&obj
->ring_list
);
3659 INIT_LIST_HEAD(&obj
->exec_list
);
3663 obj
->fence_reg
= I915_FENCE_REG_NONE
;
3664 obj
->madv
= I915_MADV_WILLNEED
;
3665 /* Avoid an unnecessary call to unbind on the first bind. */
3666 obj
->map_and_fenceable
= true;
3668 i915_gem_info_add_obj(obj
->base
.dev
->dev_private
, obj
->base
.size
);
3671 static const struct drm_i915_gem_object_ops i915_gem_object_ops
= {
3672 .get_pages
= i915_gem_object_get_pages_gtt
,
3673 .put_pages
= i915_gem_object_put_pages_gtt
,
3676 struct drm_i915_gem_object
*i915_gem_alloc_object(struct drm_device
*dev
,
3679 struct drm_i915_gem_object
*obj
;
3680 struct address_space
*mapping
;
3683 obj
= kzalloc(sizeof(*obj
), GFP_KERNEL
);
3687 if (drm_gem_object_init(dev
, &obj
->base
, size
) != 0) {
3692 mask
= GFP_HIGHUSER
| __GFP_RECLAIMABLE
;
3693 if (IS_CRESTLINE(dev
) || IS_BROADWATER(dev
)) {
3694 /* 965gm cannot relocate objects above 4GiB. */
3695 mask
&= ~__GFP_HIGHMEM
;
3696 mask
|= __GFP_DMA32
;
3699 mapping
= obj
->base
.filp
->f_path
.dentry
->d_inode
->i_mapping
;
3700 mapping_set_gfp_mask(mapping
, mask
);
3702 i915_gem_object_init(obj
, &i915_gem_object_ops
);
3704 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
3705 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
3708 /* On some devices, we can have the GPU use the LLC (the CPU
3709 * cache) for about a 10% performance improvement
3710 * compared to uncached. Graphics requests other than
3711 * display scanout are coherent with the CPU in
3712 * accessing this cache. This means in this mode we
3713 * don't need to clflush on the CPU side, and on the
3714 * GPU side we only need to flush internal caches to
3715 * get data visible to the CPU.
3717 * However, we maintain the display planes as UC, and so
3718 * need to rebind when first used as such.
3720 obj
->cache_level
= I915_CACHE_LLC
;
3722 obj
->cache_level
= I915_CACHE_NONE
;
3727 int i915_gem_init_object(struct drm_gem_object
*obj
)
3734 void i915_gem_free_object(struct drm_gem_object
*gem_obj
)
3736 struct drm_i915_gem_object
*obj
= to_intel_bo(gem_obj
);
3737 struct drm_device
*dev
= obj
->base
.dev
;
3738 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3740 trace_i915_gem_object_destroy(obj
);
3743 i915_gem_detach_phys_object(dev
, obj
);
3746 if (WARN_ON(i915_gem_object_unbind(obj
) == -ERESTARTSYS
)) {
3747 bool was_interruptible
;
3749 was_interruptible
= dev_priv
->mm
.interruptible
;
3750 dev_priv
->mm
.interruptible
= false;
3752 WARN_ON(i915_gem_object_unbind(obj
));
3754 dev_priv
->mm
.interruptible
= was_interruptible
;
3757 obj
->pages_pin_count
= 0;
3758 i915_gem_object_put_pages(obj
);
3759 i915_gem_object_free_mmap_offset(obj
);
3763 if (obj
->base
.import_attach
)
3764 drm_prime_gem_destroy(&obj
->base
, NULL
);
3766 drm_gem_object_release(&obj
->base
);
3767 i915_gem_info_remove_obj(dev_priv
, obj
->base
.size
);
3774 i915_gem_idle(struct drm_device
*dev
)
3776 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3779 mutex_lock(&dev
->struct_mutex
);
3781 if (dev_priv
->mm
.suspended
) {
3782 mutex_unlock(&dev
->struct_mutex
);
3786 ret
= i915_gpu_idle(dev
);
3788 mutex_unlock(&dev
->struct_mutex
);
3791 i915_gem_retire_requests(dev
);
3793 /* Under UMS, be paranoid and evict. */
3794 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
3795 i915_gem_evict_everything(dev
);
3797 i915_gem_reset_fences(dev
);
3799 /* Hack! Don't let anybody do execbuf while we don't control the chip.
3800 * We need to replace this with a semaphore, or something.
3801 * And not confound mm.suspended!
3803 dev_priv
->mm
.suspended
= 1;
3804 del_timer_sync(&dev_priv
->hangcheck_timer
);
3806 i915_kernel_lost_context(dev
);
3807 i915_gem_cleanup_ringbuffer(dev
);
3809 mutex_unlock(&dev
->struct_mutex
);
3811 /* Cancel the retire work handler, which should be idle now. */
3812 cancel_delayed_work_sync(&dev_priv
->mm
.retire_work
);
3817 void i915_gem_l3_remap(struct drm_device
*dev
)
3819 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3823 if (!IS_IVYBRIDGE(dev
))
3826 if (!dev_priv
->mm
.l3_remap_info
)
3829 misccpctl
= I915_READ(GEN7_MISCCPCTL
);
3830 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
& ~GEN7_DOP_CLOCK_GATE_ENABLE
);
3831 POSTING_READ(GEN7_MISCCPCTL
);
3833 for (i
= 0; i
< GEN7_L3LOG_SIZE
; i
+= 4) {
3834 u32 remap
= I915_READ(GEN7_L3LOG_BASE
+ i
);
3835 if (remap
&& remap
!= dev_priv
->mm
.l3_remap_info
[i
/4])
3836 DRM_DEBUG("0x%x was already programmed to %x\n",
3837 GEN7_L3LOG_BASE
+ i
, remap
);
3838 if (remap
&& !dev_priv
->mm
.l3_remap_info
[i
/4])
3839 DRM_DEBUG_DRIVER("Clearing remapped register\n");
3840 I915_WRITE(GEN7_L3LOG_BASE
+ i
, dev_priv
->mm
.l3_remap_info
[i
/4]);
3843 /* Make sure all the writes land before disabling dop clock gating */
3844 POSTING_READ(GEN7_L3LOG_BASE
);
3846 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
);
3849 void i915_gem_init_swizzling(struct drm_device
*dev
)
3851 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3853 if (INTEL_INFO(dev
)->gen
< 5 ||
3854 dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_NONE
)
3857 I915_WRITE(DISP_ARB_CTL
, I915_READ(DISP_ARB_CTL
) |
3858 DISP_TILE_SURFACE_SWIZZLING
);
3863 I915_WRITE(TILECTL
, I915_READ(TILECTL
) | TILECTL_SWZCTL
);
3865 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB
));
3867 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB
));
3870 void i915_gem_init_ppgtt(struct drm_device
*dev
)
3872 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3874 struct intel_ring_buffer
*ring
;
3875 struct i915_hw_ppgtt
*ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
3876 uint32_t __iomem
*pd_addr
;
3880 if (!dev_priv
->mm
.aliasing_ppgtt
)
3884 pd_addr
= dev_priv
->mm
.gtt
->gtt
+ ppgtt
->pd_offset
/sizeof(uint32_t);
3885 for (i
= 0; i
< ppgtt
->num_pd_entries
; i
++) {
3888 if (dev_priv
->mm
.gtt
->needs_dmar
)
3889 pt_addr
= ppgtt
->pt_dma_addr
[i
];
3891 pt_addr
= page_to_phys(ppgtt
->pt_pages
[i
]);
3893 pd_entry
= GEN6_PDE_ADDR_ENCODE(pt_addr
);
3894 pd_entry
|= GEN6_PDE_VALID
;
3896 writel(pd_entry
, pd_addr
+ i
);
3900 pd_offset
= ppgtt
->pd_offset
;
3901 pd_offset
/= 64; /* in cachelines, */
3904 if (INTEL_INFO(dev
)->gen
== 6) {
3905 uint32_t ecochk
, gab_ctl
, ecobits
;
3907 ecobits
= I915_READ(GAC_ECO_BITS
);
3908 I915_WRITE(GAC_ECO_BITS
, ecobits
| ECOBITS_PPGTT_CACHE64B
);
3910 gab_ctl
= I915_READ(GAB_CTL
);
3911 I915_WRITE(GAB_CTL
, gab_ctl
| GAB_CTL_CONT_AFTER_PAGEFAULT
);
3913 ecochk
= I915_READ(GAM_ECOCHK
);
3914 I915_WRITE(GAM_ECOCHK
, ecochk
| ECOCHK_SNB_BIT
|
3915 ECOCHK_PPGTT_CACHE64B
);
3916 I915_WRITE(GFX_MODE
, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE
));
3917 } else if (INTEL_INFO(dev
)->gen
>= 7) {
3918 I915_WRITE(GAM_ECOCHK
, ECOCHK_PPGTT_CACHE64B
);
3919 /* GFX_MODE is per-ring on gen7+ */
3922 for_each_ring(ring
, dev_priv
, i
) {
3923 if (INTEL_INFO(dev
)->gen
>= 7)
3924 I915_WRITE(RING_MODE_GEN7(ring
),
3925 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE
));
3927 I915_WRITE(RING_PP_DIR_DCLV(ring
), PP_DIR_DCLV_2G
);
3928 I915_WRITE(RING_PP_DIR_BASE(ring
), pd_offset
);
3933 intel_enable_blt(struct drm_device
*dev
)
3938 /* The blitter was dysfunctional on early prototypes */
3939 if (IS_GEN6(dev
) && dev
->pdev
->revision
< 8) {
3940 DRM_INFO("BLT not supported on this pre-production hardware;"
3941 " graphics performance will be degraded.\n");
3949 i915_gem_init_hw(struct drm_device
*dev
)
3951 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3954 if (!intel_enable_gtt())
3957 i915_gem_l3_remap(dev
);
3959 i915_gem_init_swizzling(dev
);
3961 ret
= intel_init_render_ring_buffer(dev
);
3966 ret
= intel_init_bsd_ring_buffer(dev
);
3968 goto cleanup_render_ring
;
3971 if (intel_enable_blt(dev
)) {
3972 ret
= intel_init_blt_ring_buffer(dev
);
3974 goto cleanup_bsd_ring
;
3977 dev_priv
->next_seqno
= 1;
3980 * XXX: There was some w/a described somewhere suggesting loading
3981 * contexts before PPGTT.
3983 i915_gem_context_init(dev
);
3984 i915_gem_init_ppgtt(dev
);
3989 intel_cleanup_ring_buffer(&dev_priv
->ring
[VCS
]);
3990 cleanup_render_ring
:
3991 intel_cleanup_ring_buffer(&dev_priv
->ring
[RCS
]);
3996 intel_enable_ppgtt(struct drm_device
*dev
)
3998 if (i915_enable_ppgtt
>= 0)
3999 return i915_enable_ppgtt
;
4001 #ifdef CONFIG_INTEL_IOMMU
4002 /* Disable ppgtt on SNB if VT-d is on. */
4003 if (INTEL_INFO(dev
)->gen
== 6 && intel_iommu_gfx_mapped
)
4010 int i915_gem_init(struct drm_device
*dev
)
4012 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4013 unsigned long gtt_size
, mappable_size
;
4016 gtt_size
= dev_priv
->mm
.gtt
->gtt_total_entries
<< PAGE_SHIFT
;
4017 mappable_size
= dev_priv
->mm
.gtt
->gtt_mappable_entries
<< PAGE_SHIFT
;
4019 mutex_lock(&dev
->struct_mutex
);
4020 if (intel_enable_ppgtt(dev
) && HAS_ALIASING_PPGTT(dev
)) {
4021 /* PPGTT pdes are stolen from global gtt ptes, so shrink the
4022 * aperture accordingly when using aliasing ppgtt. */
4023 gtt_size
-= I915_PPGTT_PD_ENTRIES
*PAGE_SIZE
;
4025 i915_gem_init_global_gtt(dev
, 0, mappable_size
, gtt_size
);
4027 ret
= i915_gem_init_aliasing_ppgtt(dev
);
4029 mutex_unlock(&dev
->struct_mutex
);
4033 /* Let GEM Manage all of the aperture.
4035 * However, leave one page at the end still bound to the scratch
4036 * page. There are a number of places where the hardware
4037 * apparently prefetches past the end of the object, and we've
4038 * seen multiple hangs with the GPU head pointer stuck in a
4039 * batchbuffer bound at the last page of the aperture. One page
4040 * should be enough to keep any prefetching inside of the
4043 i915_gem_init_global_gtt(dev
, 0, mappable_size
,
4047 ret
= i915_gem_init_hw(dev
);
4048 mutex_unlock(&dev
->struct_mutex
);
4050 i915_gem_cleanup_aliasing_ppgtt(dev
);
4054 /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */
4055 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
4056 dev_priv
->dri1
.allow_batchbuffer
= 1;
4061 i915_gem_cleanup_ringbuffer(struct drm_device
*dev
)
4063 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4064 struct intel_ring_buffer
*ring
;
4067 for_each_ring(ring
, dev_priv
, i
)
4068 intel_cleanup_ring_buffer(ring
);
4072 i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
4073 struct drm_file
*file_priv
)
4075 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4078 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4081 if (atomic_read(&dev_priv
->mm
.wedged
)) {
4082 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4083 atomic_set(&dev_priv
->mm
.wedged
, 0);
4086 mutex_lock(&dev
->struct_mutex
);
4087 dev_priv
->mm
.suspended
= 0;
4089 ret
= i915_gem_init_hw(dev
);
4091 mutex_unlock(&dev
->struct_mutex
);
4095 BUG_ON(!list_empty(&dev_priv
->mm
.active_list
));
4096 BUG_ON(!list_empty(&dev_priv
->mm
.inactive_list
));
4097 mutex_unlock(&dev
->struct_mutex
);
4099 ret
= drm_irq_install(dev
);
4101 goto cleanup_ringbuffer
;
4106 mutex_lock(&dev
->struct_mutex
);
4107 i915_gem_cleanup_ringbuffer(dev
);
4108 dev_priv
->mm
.suspended
= 1;
4109 mutex_unlock(&dev
->struct_mutex
);
4115 i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
4116 struct drm_file
*file_priv
)
4118 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4121 drm_irq_uninstall(dev
);
4122 return i915_gem_idle(dev
);
4126 i915_gem_lastclose(struct drm_device
*dev
)
4130 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4133 ret
= i915_gem_idle(dev
);
4135 DRM_ERROR("failed to idle hardware: %d\n", ret
);
4139 init_ring_lists(struct intel_ring_buffer
*ring
)
4141 INIT_LIST_HEAD(&ring
->active_list
);
4142 INIT_LIST_HEAD(&ring
->request_list
);
4146 i915_gem_load(struct drm_device
*dev
)
4149 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4151 INIT_LIST_HEAD(&dev_priv
->mm
.active_list
);
4152 INIT_LIST_HEAD(&dev_priv
->mm
.inactive_list
);
4153 INIT_LIST_HEAD(&dev_priv
->mm
.unbound_list
);
4154 INIT_LIST_HEAD(&dev_priv
->mm
.bound_list
);
4155 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
4156 for (i
= 0; i
< I915_NUM_RINGS
; i
++)
4157 init_ring_lists(&dev_priv
->ring
[i
]);
4158 for (i
= 0; i
< I915_MAX_NUM_FENCES
; i
++)
4159 INIT_LIST_HEAD(&dev_priv
->fence_regs
[i
].lru_list
);
4160 INIT_DELAYED_WORK(&dev_priv
->mm
.retire_work
,
4161 i915_gem_retire_work_handler
);
4162 init_completion(&dev_priv
->error_completion
);
4164 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4166 I915_WRITE(MI_ARB_STATE
,
4167 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE
));
4170 dev_priv
->relative_constants_mode
= I915_EXEC_CONSTANTS_REL_GENERAL
;
4172 /* Old X drivers will take 0-2 for front, back, depth buffers */
4173 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
4174 dev_priv
->fence_reg_start
= 3;
4176 if (INTEL_INFO(dev
)->gen
>= 4 || IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
4177 dev_priv
->num_fence_regs
= 16;
4179 dev_priv
->num_fence_regs
= 8;
4181 /* Initialize fence registers to zero */
4182 i915_gem_reset_fences(dev
);
4184 i915_gem_detect_bit_6_swizzle(dev
);
4185 init_waitqueue_head(&dev_priv
->pending_flip_queue
);
4187 dev_priv
->mm
.interruptible
= true;
4189 dev_priv
->mm
.inactive_shrinker
.shrink
= i915_gem_inactive_shrink
;
4190 dev_priv
->mm
.inactive_shrinker
.seeks
= DEFAULT_SEEKS
;
4191 register_shrinker(&dev_priv
->mm
.inactive_shrinker
);
4195 * Create a physically contiguous memory object for this object
4196 * e.g. for cursor + overlay regs
4198 static int i915_gem_init_phys_object(struct drm_device
*dev
,
4199 int id
, int size
, int align
)
4201 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4202 struct drm_i915_gem_phys_object
*phys_obj
;
4205 if (dev_priv
->mm
.phys_objs
[id
- 1] || !size
)
4208 phys_obj
= kzalloc(sizeof(struct drm_i915_gem_phys_object
), GFP_KERNEL
);
4214 phys_obj
->handle
= drm_pci_alloc(dev
, size
, align
);
4215 if (!phys_obj
->handle
) {
4220 set_memory_wc((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
4223 dev_priv
->mm
.phys_objs
[id
- 1] = phys_obj
;
4231 static void i915_gem_free_phys_object(struct drm_device
*dev
, int id
)
4233 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4234 struct drm_i915_gem_phys_object
*phys_obj
;
4236 if (!dev_priv
->mm
.phys_objs
[id
- 1])
4239 phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
4240 if (phys_obj
->cur_obj
) {
4241 i915_gem_detach_phys_object(dev
, phys_obj
->cur_obj
);
4245 set_memory_wb((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
4247 drm_pci_free(dev
, phys_obj
->handle
);
4249 dev_priv
->mm
.phys_objs
[id
- 1] = NULL
;
4252 void i915_gem_free_all_phys_object(struct drm_device
*dev
)
4256 for (i
= I915_GEM_PHYS_CURSOR_0
; i
<= I915_MAX_PHYS_OBJECT
; i
++)
4257 i915_gem_free_phys_object(dev
, i
);
4260 void i915_gem_detach_phys_object(struct drm_device
*dev
,
4261 struct drm_i915_gem_object
*obj
)
4263 struct address_space
*mapping
= obj
->base
.filp
->f_path
.dentry
->d_inode
->i_mapping
;
4270 vaddr
= obj
->phys_obj
->handle
->vaddr
;
4272 page_count
= obj
->base
.size
/ PAGE_SIZE
;
4273 for (i
= 0; i
< page_count
; i
++) {
4274 struct page
*page
= shmem_read_mapping_page(mapping
, i
);
4275 if (!IS_ERR(page
)) {
4276 char *dst
= kmap_atomic(page
);
4277 memcpy(dst
, vaddr
+ i
*PAGE_SIZE
, PAGE_SIZE
);
4280 drm_clflush_pages(&page
, 1);
4282 set_page_dirty(page
);
4283 mark_page_accessed(page
);
4284 page_cache_release(page
);
4287 intel_gtt_chipset_flush();
4289 obj
->phys_obj
->cur_obj
= NULL
;
4290 obj
->phys_obj
= NULL
;
4294 i915_gem_attach_phys_object(struct drm_device
*dev
,
4295 struct drm_i915_gem_object
*obj
,
4299 struct address_space
*mapping
= obj
->base
.filp
->f_path
.dentry
->d_inode
->i_mapping
;
4300 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4305 if (id
> I915_MAX_PHYS_OBJECT
)
4308 if (obj
->phys_obj
) {
4309 if (obj
->phys_obj
->id
== id
)
4311 i915_gem_detach_phys_object(dev
, obj
);
4314 /* create a new object */
4315 if (!dev_priv
->mm
.phys_objs
[id
- 1]) {
4316 ret
= i915_gem_init_phys_object(dev
, id
,
4317 obj
->base
.size
, align
);
4319 DRM_ERROR("failed to init phys object %d size: %zu\n",
4320 id
, obj
->base
.size
);
4325 /* bind to the object */
4326 obj
->phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
4327 obj
->phys_obj
->cur_obj
= obj
;
4329 page_count
= obj
->base
.size
/ PAGE_SIZE
;
4331 for (i
= 0; i
< page_count
; i
++) {
4335 page
= shmem_read_mapping_page(mapping
, i
);
4337 return PTR_ERR(page
);
4339 src
= kmap_atomic(page
);
4340 dst
= obj
->phys_obj
->handle
->vaddr
+ (i
* PAGE_SIZE
);
4341 memcpy(dst
, src
, PAGE_SIZE
);
4344 mark_page_accessed(page
);
4345 page_cache_release(page
);
4352 i915_gem_phys_pwrite(struct drm_device
*dev
,
4353 struct drm_i915_gem_object
*obj
,
4354 struct drm_i915_gem_pwrite
*args
,
4355 struct drm_file
*file_priv
)
4357 void *vaddr
= obj
->phys_obj
->handle
->vaddr
+ args
->offset
;
4358 char __user
*user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
4360 if (__copy_from_user_inatomic_nocache(vaddr
, user_data
, args
->size
)) {
4361 unsigned long unwritten
;
4363 /* The physical object once assigned is fixed for the lifetime
4364 * of the obj, so we can safely drop the lock and continue
4367 mutex_unlock(&dev
->struct_mutex
);
4368 unwritten
= copy_from_user(vaddr
, user_data
, args
->size
);
4369 mutex_lock(&dev
->struct_mutex
);
4374 intel_gtt_chipset_flush();
4378 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
)
4380 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
4382 /* Clean up our request list when the client is going away, so that
4383 * later retire_requests won't dereference our soon-to-be-gone
4386 spin_lock(&file_priv
->mm
.lock
);
4387 while (!list_empty(&file_priv
->mm
.request_list
)) {
4388 struct drm_i915_gem_request
*request
;
4390 request
= list_first_entry(&file_priv
->mm
.request_list
,
4391 struct drm_i915_gem_request
,
4393 list_del(&request
->client_list
);
4394 request
->file_priv
= NULL
;
4396 spin_unlock(&file_priv
->mm
.lock
);
4400 i915_gem_inactive_shrink(struct shrinker
*shrinker
, struct shrink_control
*sc
)
4402 struct drm_i915_private
*dev_priv
=
4403 container_of(shrinker
,
4404 struct drm_i915_private
,
4405 mm
.inactive_shrinker
);
4406 struct drm_device
*dev
= dev_priv
->dev
;
4407 struct drm_i915_gem_object
*obj
;
4408 int nr_to_scan
= sc
->nr_to_scan
;
4411 if (!mutex_trylock(&dev
->struct_mutex
))
4415 nr_to_scan
-= i915_gem_purge(dev_priv
, nr_to_scan
);
4417 i915_gem_shrink_all(dev_priv
);
4421 list_for_each_entry(obj
, &dev_priv
->mm
.unbound_list
, gtt_list
)
4422 if (obj
->pages_pin_count
== 0)
4423 cnt
+= obj
->base
.size
>> PAGE_SHIFT
;
4424 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, gtt_list
)
4425 if (obj
->pin_count
== 0 && obj
->pages_pin_count
== 0)
4426 cnt
+= obj
->base
.size
>> PAGE_SHIFT
;
4428 mutex_unlock(&dev
->struct_mutex
);