2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/slab.h>
35 #include <linux/swap.h>
36 #include <linux/pci.h>
38 static void i915_gem_object_flush_gpu_write_domain(struct drm_gem_object
*obj
);
39 static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object
*obj
);
40 static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object
*obj
);
41 static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object
*obj
,
43 static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object
*obj
,
46 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object
*obj
);
47 static int i915_gem_object_wait_rendering(struct drm_gem_object
*obj
);
48 static int i915_gem_object_bind_to_gtt(struct drm_gem_object
*obj
,
50 static void i915_gem_clear_fence_reg(struct drm_gem_object
*obj
);
51 static int i915_gem_evict_something(struct drm_device
*dev
, int min_size
);
52 static int i915_gem_evict_from_inactive_list(struct drm_device
*dev
);
53 static int i915_gem_phys_pwrite(struct drm_device
*dev
, struct drm_gem_object
*obj
,
54 struct drm_i915_gem_pwrite
*args
,
55 struct drm_file
*file_priv
);
57 static LIST_HEAD(shrink_list
);
58 static DEFINE_SPINLOCK(shrink_list_lock
);
60 int i915_gem_do_init(struct drm_device
*dev
, unsigned long start
,
63 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
66 (start
& (PAGE_SIZE
- 1)) != 0 ||
67 (end
& (PAGE_SIZE
- 1)) != 0) {
71 drm_mm_init(&dev_priv
->mm
.gtt_space
, start
,
74 dev
->gtt_total
= (uint32_t) (end
- start
);
80 i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
81 struct drm_file
*file_priv
)
83 struct drm_i915_gem_init
*args
= data
;
86 mutex_lock(&dev
->struct_mutex
);
87 ret
= i915_gem_do_init(dev
, args
->gtt_start
, args
->gtt_end
);
88 mutex_unlock(&dev
->struct_mutex
);
94 i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
95 struct drm_file
*file_priv
)
97 struct drm_i915_gem_get_aperture
*args
= data
;
99 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
102 args
->aper_size
= dev
->gtt_total
;
103 args
->aper_available_size
= (args
->aper_size
-
104 atomic_read(&dev
->pin_memory
));
111 * Creates a new mm object and returns a handle to it.
114 i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
115 struct drm_file
*file_priv
)
117 struct drm_i915_gem_create
*args
= data
;
118 struct drm_gem_object
*obj
;
122 args
->size
= roundup(args
->size
, PAGE_SIZE
);
124 /* Allocate the new object */
125 obj
= i915_gem_alloc_object(dev
, args
->size
);
129 ret
= drm_gem_handle_create(file_priv
, obj
, &handle
);
130 drm_gem_object_handle_unreference_unlocked(obj
);
135 args
->handle
= handle
;
141 fast_shmem_read(struct page
**pages
,
142 loff_t page_base
, int page_offset
,
149 vaddr
= kmap_atomic(pages
[page_base
>> PAGE_SHIFT
], KM_USER0
);
152 unwritten
= __copy_to_user_inatomic(data
, vaddr
+ page_offset
, length
);
153 kunmap_atomic(vaddr
, KM_USER0
);
161 static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object
*obj
)
163 drm_i915_private_t
*dev_priv
= obj
->dev
->dev_private
;
164 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
166 return dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_9_10_17
&&
167 obj_priv
->tiling_mode
!= I915_TILING_NONE
;
171 slow_shmem_copy(struct page
*dst_page
,
173 struct page
*src_page
,
177 char *dst_vaddr
, *src_vaddr
;
179 dst_vaddr
= kmap_atomic(dst_page
, KM_USER0
);
180 if (dst_vaddr
== NULL
)
183 src_vaddr
= kmap_atomic(src_page
, KM_USER1
);
184 if (src_vaddr
== NULL
) {
185 kunmap_atomic(dst_vaddr
, KM_USER0
);
189 memcpy(dst_vaddr
+ dst_offset
, src_vaddr
+ src_offset
, length
);
191 kunmap_atomic(src_vaddr
, KM_USER1
);
192 kunmap_atomic(dst_vaddr
, KM_USER0
);
198 slow_shmem_bit17_copy(struct page
*gpu_page
,
200 struct page
*cpu_page
,
205 char *gpu_vaddr
, *cpu_vaddr
;
207 /* Use the unswizzled path if this page isn't affected. */
208 if ((page_to_phys(gpu_page
) & (1 << 17)) == 0) {
210 return slow_shmem_copy(cpu_page
, cpu_offset
,
211 gpu_page
, gpu_offset
, length
);
213 return slow_shmem_copy(gpu_page
, gpu_offset
,
214 cpu_page
, cpu_offset
, length
);
217 gpu_vaddr
= kmap_atomic(gpu_page
, KM_USER0
);
218 if (gpu_vaddr
== NULL
)
221 cpu_vaddr
= kmap_atomic(cpu_page
, KM_USER1
);
222 if (cpu_vaddr
== NULL
) {
223 kunmap_atomic(gpu_vaddr
, KM_USER0
);
227 /* Copy the data, XORing A6 with A17 (1). The user already knows he's
228 * XORing with the other bits (A9 for Y, A9 and A10 for X)
231 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
232 int this_length
= min(cacheline_end
- gpu_offset
, length
);
233 int swizzled_gpu_offset
= gpu_offset
^ 64;
236 memcpy(cpu_vaddr
+ cpu_offset
,
237 gpu_vaddr
+ swizzled_gpu_offset
,
240 memcpy(gpu_vaddr
+ swizzled_gpu_offset
,
241 cpu_vaddr
+ cpu_offset
,
244 cpu_offset
+= this_length
;
245 gpu_offset
+= this_length
;
246 length
-= this_length
;
249 kunmap_atomic(cpu_vaddr
, KM_USER1
);
250 kunmap_atomic(gpu_vaddr
, KM_USER0
);
256 * This is the fast shmem pread path, which attempts to copy_from_user directly
257 * from the backing pages of the object to the user's address space. On a
258 * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
261 i915_gem_shmem_pread_fast(struct drm_device
*dev
, struct drm_gem_object
*obj
,
262 struct drm_i915_gem_pread
*args
,
263 struct drm_file
*file_priv
)
265 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
267 loff_t offset
, page_base
;
268 char __user
*user_data
;
269 int page_offset
, page_length
;
272 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
275 mutex_lock(&dev
->struct_mutex
);
277 ret
= i915_gem_object_get_pages(obj
, 0);
281 ret
= i915_gem_object_set_cpu_read_domain_range(obj
, args
->offset
,
286 obj_priv
= to_intel_bo(obj
);
287 offset
= args
->offset
;
290 /* Operation in this page
292 * page_base = page offset within aperture
293 * page_offset = offset within page
294 * page_length = bytes to copy for this page
296 page_base
= (offset
& ~(PAGE_SIZE
-1));
297 page_offset
= offset
& (PAGE_SIZE
-1);
298 page_length
= remain
;
299 if ((page_offset
+ remain
) > PAGE_SIZE
)
300 page_length
= PAGE_SIZE
- page_offset
;
302 ret
= fast_shmem_read(obj_priv
->pages
,
303 page_base
, page_offset
,
304 user_data
, page_length
);
308 remain
-= page_length
;
309 user_data
+= page_length
;
310 offset
+= page_length
;
314 i915_gem_object_put_pages(obj
);
316 mutex_unlock(&dev
->struct_mutex
);
322 i915_gem_object_get_pages_or_evict(struct drm_gem_object
*obj
)
326 ret
= i915_gem_object_get_pages(obj
, __GFP_NORETRY
| __GFP_NOWARN
);
328 /* If we've insufficient memory to map in the pages, attempt
329 * to make some space by throwing out some old buffers.
331 if (ret
== -ENOMEM
) {
332 struct drm_device
*dev
= obj
->dev
;
334 ret
= i915_gem_evict_something(dev
, obj
->size
);
338 ret
= i915_gem_object_get_pages(obj
, 0);
345 * This is the fallback shmem pread path, which allocates temporary storage
346 * in kernel space to copy_to_user into outside of the struct_mutex, so we
347 * can copy out of the object's backing pages while holding the struct mutex
348 * and not take page faults.
351 i915_gem_shmem_pread_slow(struct drm_device
*dev
, struct drm_gem_object
*obj
,
352 struct drm_i915_gem_pread
*args
,
353 struct drm_file
*file_priv
)
355 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
356 struct mm_struct
*mm
= current
->mm
;
357 struct page
**user_pages
;
359 loff_t offset
, pinned_pages
, i
;
360 loff_t first_data_page
, last_data_page
, num_pages
;
361 int shmem_page_index
, shmem_page_offset
;
362 int data_page_index
, data_page_offset
;
365 uint64_t data_ptr
= args
->data_ptr
;
366 int do_bit17_swizzling
;
370 /* Pin the user pages containing the data. We can't fault while
371 * holding the struct mutex, yet we want to hold it while
372 * dereferencing the user data.
374 first_data_page
= data_ptr
/ PAGE_SIZE
;
375 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
376 num_pages
= last_data_page
- first_data_page
+ 1;
378 user_pages
= drm_calloc_large(num_pages
, sizeof(struct page
*));
379 if (user_pages
== NULL
)
382 down_read(&mm
->mmap_sem
);
383 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
384 num_pages
, 1, 0, user_pages
, NULL
);
385 up_read(&mm
->mmap_sem
);
386 if (pinned_pages
< num_pages
) {
388 goto fail_put_user_pages
;
391 do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
393 mutex_lock(&dev
->struct_mutex
);
395 ret
= i915_gem_object_get_pages_or_evict(obj
);
399 ret
= i915_gem_object_set_cpu_read_domain_range(obj
, args
->offset
,
404 obj_priv
= to_intel_bo(obj
);
405 offset
= args
->offset
;
408 /* Operation in this page
410 * shmem_page_index = page number within shmem file
411 * shmem_page_offset = offset within page in shmem file
412 * data_page_index = page number in get_user_pages return
413 * data_page_offset = offset with data_page_index page.
414 * page_length = bytes to copy for this page
416 shmem_page_index
= offset
/ PAGE_SIZE
;
417 shmem_page_offset
= offset
& ~PAGE_MASK
;
418 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
419 data_page_offset
= data_ptr
& ~PAGE_MASK
;
421 page_length
= remain
;
422 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
423 page_length
= PAGE_SIZE
- shmem_page_offset
;
424 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
425 page_length
= PAGE_SIZE
- data_page_offset
;
427 if (do_bit17_swizzling
) {
428 ret
= slow_shmem_bit17_copy(obj_priv
->pages
[shmem_page_index
],
430 user_pages
[data_page_index
],
435 ret
= slow_shmem_copy(user_pages
[data_page_index
],
437 obj_priv
->pages
[shmem_page_index
],
444 remain
-= page_length
;
445 data_ptr
+= page_length
;
446 offset
+= page_length
;
450 i915_gem_object_put_pages(obj
);
452 mutex_unlock(&dev
->struct_mutex
);
454 for (i
= 0; i
< pinned_pages
; i
++) {
455 SetPageDirty(user_pages
[i
]);
456 page_cache_release(user_pages
[i
]);
458 drm_free_large(user_pages
);
464 * Reads data from the object referenced by handle.
466 * On error, the contents of *data are undefined.
469 i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
470 struct drm_file
*file_priv
)
472 struct drm_i915_gem_pread
*args
= data
;
473 struct drm_gem_object
*obj
;
474 struct drm_i915_gem_object
*obj_priv
;
477 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
480 obj_priv
= to_intel_bo(obj
);
482 /* Bounds check source.
484 * XXX: This could use review for overflow issues...
486 if (args
->offset
> obj
->size
|| args
->size
> obj
->size
||
487 args
->offset
+ args
->size
> obj
->size
) {
488 drm_gem_object_unreference_unlocked(obj
);
492 if (i915_gem_object_needs_bit17_swizzle(obj
)) {
493 ret
= i915_gem_shmem_pread_slow(dev
, obj
, args
, file_priv
);
495 ret
= i915_gem_shmem_pread_fast(dev
, obj
, args
, file_priv
);
497 ret
= i915_gem_shmem_pread_slow(dev
, obj
, args
,
501 drm_gem_object_unreference_unlocked(obj
);
506 /* This is the fast write path which cannot handle
507 * page faults in the source data
511 fast_user_write(struct io_mapping
*mapping
,
512 loff_t page_base
, int page_offset
,
513 char __user
*user_data
,
517 unsigned long unwritten
;
519 vaddr_atomic
= io_mapping_map_atomic_wc(mapping
, page_base
);
520 unwritten
= __copy_from_user_inatomic_nocache(vaddr_atomic
+ page_offset
,
522 io_mapping_unmap_atomic(vaddr_atomic
);
528 /* Here's the write path which can sleep for
533 slow_kernel_write(struct io_mapping
*mapping
,
534 loff_t gtt_base
, int gtt_offset
,
535 struct page
*user_page
, int user_offset
,
538 char *src_vaddr
, *dst_vaddr
;
539 unsigned long unwritten
;
541 dst_vaddr
= io_mapping_map_atomic_wc(mapping
, gtt_base
);
542 src_vaddr
= kmap_atomic(user_page
, KM_USER1
);
543 unwritten
= __copy_from_user_inatomic_nocache(dst_vaddr
+ gtt_offset
,
544 src_vaddr
+ user_offset
,
546 kunmap_atomic(src_vaddr
, KM_USER1
);
547 io_mapping_unmap_atomic(dst_vaddr
);
554 fast_shmem_write(struct page
**pages
,
555 loff_t page_base
, int page_offset
,
560 unsigned long unwritten
;
562 vaddr
= kmap_atomic(pages
[page_base
>> PAGE_SHIFT
], KM_USER0
);
565 unwritten
= __copy_from_user_inatomic(vaddr
+ page_offset
, data
, length
);
566 kunmap_atomic(vaddr
, KM_USER0
);
574 * This is the fast pwrite path, where we copy the data directly from the
575 * user into the GTT, uncached.
578 i915_gem_gtt_pwrite_fast(struct drm_device
*dev
, struct drm_gem_object
*obj
,
579 struct drm_i915_gem_pwrite
*args
,
580 struct drm_file
*file_priv
)
582 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
583 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
585 loff_t offset
, page_base
;
586 char __user
*user_data
;
587 int page_offset
, page_length
;
590 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
592 if (!access_ok(VERIFY_READ
, user_data
, remain
))
596 mutex_lock(&dev
->struct_mutex
);
597 ret
= i915_gem_object_pin(obj
, 0);
599 mutex_unlock(&dev
->struct_mutex
);
602 ret
= i915_gem_object_set_to_gtt_domain(obj
, 1);
606 obj_priv
= to_intel_bo(obj
);
607 offset
= obj_priv
->gtt_offset
+ args
->offset
;
610 /* Operation in this page
612 * page_base = page offset within aperture
613 * page_offset = offset within page
614 * page_length = bytes to copy for this page
616 page_base
= (offset
& ~(PAGE_SIZE
-1));
617 page_offset
= offset
& (PAGE_SIZE
-1);
618 page_length
= remain
;
619 if ((page_offset
+ remain
) > PAGE_SIZE
)
620 page_length
= PAGE_SIZE
- page_offset
;
622 ret
= fast_user_write (dev_priv
->mm
.gtt_mapping
, page_base
,
623 page_offset
, user_data
, page_length
);
625 /* If we get a fault while copying data, then (presumably) our
626 * source page isn't available. Return the error and we'll
627 * retry in the slow path.
632 remain
-= page_length
;
633 user_data
+= page_length
;
634 offset
+= page_length
;
638 i915_gem_object_unpin(obj
);
639 mutex_unlock(&dev
->struct_mutex
);
645 * This is the fallback GTT pwrite path, which uses get_user_pages to pin
646 * the memory and maps it using kmap_atomic for copying.
648 * This code resulted in x11perf -rgb10text consuming about 10% more CPU
649 * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
652 i915_gem_gtt_pwrite_slow(struct drm_device
*dev
, struct drm_gem_object
*obj
,
653 struct drm_i915_gem_pwrite
*args
,
654 struct drm_file
*file_priv
)
656 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
657 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
659 loff_t gtt_page_base
, offset
;
660 loff_t first_data_page
, last_data_page
, num_pages
;
661 loff_t pinned_pages
, i
;
662 struct page
**user_pages
;
663 struct mm_struct
*mm
= current
->mm
;
664 int gtt_page_offset
, data_page_offset
, data_page_index
, page_length
;
666 uint64_t data_ptr
= args
->data_ptr
;
670 /* Pin the user pages containing the data. We can't fault while
671 * holding the struct mutex, and all of the pwrite implementations
672 * want to hold it while dereferencing the user data.
674 first_data_page
= data_ptr
/ PAGE_SIZE
;
675 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
676 num_pages
= last_data_page
- first_data_page
+ 1;
678 user_pages
= drm_calloc_large(num_pages
, sizeof(struct page
*));
679 if (user_pages
== NULL
)
682 down_read(&mm
->mmap_sem
);
683 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
684 num_pages
, 0, 0, user_pages
, NULL
);
685 up_read(&mm
->mmap_sem
);
686 if (pinned_pages
< num_pages
) {
688 goto out_unpin_pages
;
691 mutex_lock(&dev
->struct_mutex
);
692 ret
= i915_gem_object_pin(obj
, 0);
696 ret
= i915_gem_object_set_to_gtt_domain(obj
, 1);
698 goto out_unpin_object
;
700 obj_priv
= to_intel_bo(obj
);
701 offset
= obj_priv
->gtt_offset
+ args
->offset
;
704 /* Operation in this page
706 * gtt_page_base = page offset within aperture
707 * gtt_page_offset = offset within page in aperture
708 * data_page_index = page number in get_user_pages return
709 * data_page_offset = offset with data_page_index page.
710 * page_length = bytes to copy for this page
712 gtt_page_base
= offset
& PAGE_MASK
;
713 gtt_page_offset
= offset
& ~PAGE_MASK
;
714 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
715 data_page_offset
= data_ptr
& ~PAGE_MASK
;
717 page_length
= remain
;
718 if ((gtt_page_offset
+ page_length
) > PAGE_SIZE
)
719 page_length
= PAGE_SIZE
- gtt_page_offset
;
720 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
721 page_length
= PAGE_SIZE
- data_page_offset
;
723 ret
= slow_kernel_write(dev_priv
->mm
.gtt_mapping
,
724 gtt_page_base
, gtt_page_offset
,
725 user_pages
[data_page_index
],
729 /* If we get a fault while copying data, then (presumably) our
730 * source page isn't available. Return the error and we'll
731 * retry in the slow path.
734 goto out_unpin_object
;
736 remain
-= page_length
;
737 offset
+= page_length
;
738 data_ptr
+= page_length
;
742 i915_gem_object_unpin(obj
);
744 mutex_unlock(&dev
->struct_mutex
);
746 for (i
= 0; i
< pinned_pages
; i
++)
747 page_cache_release(user_pages
[i
]);
748 drm_free_large(user_pages
);
754 * This is the fast shmem pwrite path, which attempts to directly
755 * copy_from_user into the kmapped pages backing the object.
758 i915_gem_shmem_pwrite_fast(struct drm_device
*dev
, struct drm_gem_object
*obj
,
759 struct drm_i915_gem_pwrite
*args
,
760 struct drm_file
*file_priv
)
762 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
764 loff_t offset
, page_base
;
765 char __user
*user_data
;
766 int page_offset
, page_length
;
769 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
772 mutex_lock(&dev
->struct_mutex
);
774 ret
= i915_gem_object_get_pages(obj
, 0);
778 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
782 obj_priv
= to_intel_bo(obj
);
783 offset
= args
->offset
;
787 /* Operation in this page
789 * page_base = page offset within aperture
790 * page_offset = offset within page
791 * page_length = bytes to copy for this page
793 page_base
= (offset
& ~(PAGE_SIZE
-1));
794 page_offset
= offset
& (PAGE_SIZE
-1);
795 page_length
= remain
;
796 if ((page_offset
+ remain
) > PAGE_SIZE
)
797 page_length
= PAGE_SIZE
- page_offset
;
799 ret
= fast_shmem_write(obj_priv
->pages
,
800 page_base
, page_offset
,
801 user_data
, page_length
);
805 remain
-= page_length
;
806 user_data
+= page_length
;
807 offset
+= page_length
;
811 i915_gem_object_put_pages(obj
);
813 mutex_unlock(&dev
->struct_mutex
);
819 * This is the fallback shmem pwrite path, which uses get_user_pages to pin
820 * the memory and maps it using kmap_atomic for copying.
822 * This avoids taking mmap_sem for faulting on the user's address while the
823 * struct_mutex is held.
826 i915_gem_shmem_pwrite_slow(struct drm_device
*dev
, struct drm_gem_object
*obj
,
827 struct drm_i915_gem_pwrite
*args
,
828 struct drm_file
*file_priv
)
830 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
831 struct mm_struct
*mm
= current
->mm
;
832 struct page
**user_pages
;
834 loff_t offset
, pinned_pages
, i
;
835 loff_t first_data_page
, last_data_page
, num_pages
;
836 int shmem_page_index
, shmem_page_offset
;
837 int data_page_index
, data_page_offset
;
840 uint64_t data_ptr
= args
->data_ptr
;
841 int do_bit17_swizzling
;
845 /* Pin the user pages containing the data. We can't fault while
846 * holding the struct mutex, and all of the pwrite implementations
847 * want to hold it while dereferencing the user data.
849 first_data_page
= data_ptr
/ PAGE_SIZE
;
850 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
851 num_pages
= last_data_page
- first_data_page
+ 1;
853 user_pages
= drm_calloc_large(num_pages
, sizeof(struct page
*));
854 if (user_pages
== NULL
)
857 down_read(&mm
->mmap_sem
);
858 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
859 num_pages
, 0, 0, user_pages
, NULL
);
860 up_read(&mm
->mmap_sem
);
861 if (pinned_pages
< num_pages
) {
863 goto fail_put_user_pages
;
866 do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
868 mutex_lock(&dev
->struct_mutex
);
870 ret
= i915_gem_object_get_pages_or_evict(obj
);
874 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
878 obj_priv
= to_intel_bo(obj
);
879 offset
= args
->offset
;
883 /* Operation in this page
885 * shmem_page_index = page number within shmem file
886 * shmem_page_offset = offset within page in shmem file
887 * data_page_index = page number in get_user_pages return
888 * data_page_offset = offset with data_page_index page.
889 * page_length = bytes to copy for this page
891 shmem_page_index
= offset
/ PAGE_SIZE
;
892 shmem_page_offset
= offset
& ~PAGE_MASK
;
893 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
894 data_page_offset
= data_ptr
& ~PAGE_MASK
;
896 page_length
= remain
;
897 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
898 page_length
= PAGE_SIZE
- shmem_page_offset
;
899 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
900 page_length
= PAGE_SIZE
- data_page_offset
;
902 if (do_bit17_swizzling
) {
903 ret
= slow_shmem_bit17_copy(obj_priv
->pages
[shmem_page_index
],
905 user_pages
[data_page_index
],
910 ret
= slow_shmem_copy(obj_priv
->pages
[shmem_page_index
],
912 user_pages
[data_page_index
],
919 remain
-= page_length
;
920 data_ptr
+= page_length
;
921 offset
+= page_length
;
925 i915_gem_object_put_pages(obj
);
927 mutex_unlock(&dev
->struct_mutex
);
929 for (i
= 0; i
< pinned_pages
; i
++)
930 page_cache_release(user_pages
[i
]);
931 drm_free_large(user_pages
);
937 * Writes data to the object referenced by handle.
939 * On error, the contents of the buffer that were to be modified are undefined.
942 i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
943 struct drm_file
*file_priv
)
945 struct drm_i915_gem_pwrite
*args
= data
;
946 struct drm_gem_object
*obj
;
947 struct drm_i915_gem_object
*obj_priv
;
950 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
953 obj_priv
= to_intel_bo(obj
);
955 /* Bounds check destination.
957 * XXX: This could use review for overflow issues...
959 if (args
->offset
> obj
->size
|| args
->size
> obj
->size
||
960 args
->offset
+ args
->size
> obj
->size
) {
961 drm_gem_object_unreference_unlocked(obj
);
965 /* We can only do the GTT pwrite on untiled buffers, as otherwise
966 * it would end up going through the fenced access, and we'll get
967 * different detiling behavior between reading and writing.
968 * pread/pwrite currently are reading and writing from the CPU
969 * perspective, requiring manual detiling by the client.
971 if (obj_priv
->phys_obj
)
972 ret
= i915_gem_phys_pwrite(dev
, obj
, args
, file_priv
);
973 else if (obj_priv
->tiling_mode
== I915_TILING_NONE
&&
974 dev
->gtt_total
!= 0) {
975 ret
= i915_gem_gtt_pwrite_fast(dev
, obj
, args
, file_priv
);
976 if (ret
== -EFAULT
) {
977 ret
= i915_gem_gtt_pwrite_slow(dev
, obj
, args
,
980 } else if (i915_gem_object_needs_bit17_swizzle(obj
)) {
981 ret
= i915_gem_shmem_pwrite_slow(dev
, obj
, args
, file_priv
);
983 ret
= i915_gem_shmem_pwrite_fast(dev
, obj
, args
, file_priv
);
984 if (ret
== -EFAULT
) {
985 ret
= i915_gem_shmem_pwrite_slow(dev
, obj
, args
,
992 DRM_INFO("pwrite failed %d\n", ret
);
995 drm_gem_object_unreference_unlocked(obj
);
1001 * Called when user space prepares to use an object with the CPU, either
1002 * through the mmap ioctl's mapping or a GTT mapping.
1005 i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
1006 struct drm_file
*file_priv
)
1008 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1009 struct drm_i915_gem_set_domain
*args
= data
;
1010 struct drm_gem_object
*obj
;
1011 struct drm_i915_gem_object
*obj_priv
;
1012 uint32_t read_domains
= args
->read_domains
;
1013 uint32_t write_domain
= args
->write_domain
;
1016 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1019 /* Only handle setting domains to types used by the CPU. */
1020 if (write_domain
& I915_GEM_GPU_DOMAINS
)
1023 if (read_domains
& I915_GEM_GPU_DOMAINS
)
1026 /* Having something in the write domain implies it's in the read
1027 * domain, and only that read domain. Enforce that in the request.
1029 if (write_domain
!= 0 && read_domains
!= write_domain
)
1032 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1035 obj_priv
= to_intel_bo(obj
);
1037 mutex_lock(&dev
->struct_mutex
);
1039 intel_mark_busy(dev
, obj
);
1042 DRM_INFO("set_domain_ioctl %p(%zd), %08x %08x\n",
1043 obj
, obj
->size
, read_domains
, write_domain
);
1045 if (read_domains
& I915_GEM_DOMAIN_GTT
) {
1046 ret
= i915_gem_object_set_to_gtt_domain(obj
, write_domain
!= 0);
1048 /* Update the LRU on the fence for the CPU access that's
1051 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
) {
1052 struct drm_i915_fence_reg
*reg
=
1053 &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
1054 list_move_tail(®
->lru_list
,
1055 &dev_priv
->mm
.fence_list
);
1058 /* Silently promote "you're not bound, there was nothing to do"
1059 * to success, since the client was just asking us to
1060 * make sure everything was done.
1065 ret
= i915_gem_object_set_to_cpu_domain(obj
, write_domain
!= 0);
1068 drm_gem_object_unreference(obj
);
1069 mutex_unlock(&dev
->struct_mutex
);
1074 * Called when user space has done writes to this buffer
1077 i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1078 struct drm_file
*file_priv
)
1080 struct drm_i915_gem_sw_finish
*args
= data
;
1081 struct drm_gem_object
*obj
;
1082 struct drm_i915_gem_object
*obj_priv
;
1085 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1088 mutex_lock(&dev
->struct_mutex
);
1089 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1091 mutex_unlock(&dev
->struct_mutex
);
1096 DRM_INFO("%s: sw_finish %d (%p %zd)\n",
1097 __func__
, args
->handle
, obj
, obj
->size
);
1099 obj_priv
= to_intel_bo(obj
);
1101 /* Pinned buffers may be scanout, so flush the cache */
1102 if (obj_priv
->pin_count
)
1103 i915_gem_object_flush_cpu_write_domain(obj
);
1105 drm_gem_object_unreference(obj
);
1106 mutex_unlock(&dev
->struct_mutex
);
1111 * Maps the contents of an object, returning the address it is mapped
1114 * While the mapping holds a reference on the contents of the object, it doesn't
1115 * imply a ref on the object itself.
1118 i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1119 struct drm_file
*file_priv
)
1121 struct drm_i915_gem_mmap
*args
= data
;
1122 struct drm_gem_object
*obj
;
1126 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1129 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1133 offset
= args
->offset
;
1135 down_write(¤t
->mm
->mmap_sem
);
1136 addr
= do_mmap(obj
->filp
, 0, args
->size
,
1137 PROT_READ
| PROT_WRITE
, MAP_SHARED
,
1139 up_write(¤t
->mm
->mmap_sem
);
1140 drm_gem_object_unreference_unlocked(obj
);
1141 if (IS_ERR((void *)addr
))
1144 args
->addr_ptr
= (uint64_t) addr
;
1150 * i915_gem_fault - fault a page into the GTT
1151 * vma: VMA in question
1154 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1155 * from userspace. The fault handler takes care of binding the object to
1156 * the GTT (if needed), allocating and programming a fence register (again,
1157 * only if needed based on whether the old reg is still valid or the object
1158 * is tiled) and inserting a new PTE into the faulting process.
1160 * Note that the faulting process may involve evicting existing objects
1161 * from the GTT and/or fence registers to make room. So performance may
1162 * suffer if the GTT working set is large or there are few fence registers
1165 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
)
1167 struct drm_gem_object
*obj
= vma
->vm_private_data
;
1168 struct drm_device
*dev
= obj
->dev
;
1169 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1170 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1171 pgoff_t page_offset
;
1174 bool write
= !!(vmf
->flags
& FAULT_FLAG_WRITE
);
1176 /* We don't use vmf->pgoff since that has the fake offset */
1177 page_offset
= ((unsigned long)vmf
->virtual_address
- vma
->vm_start
) >>
1180 /* Now bind it into the GTT if needed */
1181 mutex_lock(&dev
->struct_mutex
);
1182 if (!obj_priv
->gtt_space
) {
1183 ret
= i915_gem_object_bind_to_gtt(obj
, 0);
1187 list_add_tail(&obj_priv
->list
, &dev_priv
->mm
.inactive_list
);
1189 ret
= i915_gem_object_set_to_gtt_domain(obj
, write
);
1194 /* Need a new fence register? */
1195 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
) {
1196 ret
= i915_gem_object_get_fence_reg(obj
);
1201 pfn
= ((dev
->agp
->base
+ obj_priv
->gtt_offset
) >> PAGE_SHIFT
) +
1204 /* Finally, remap it using the new GTT offset */
1205 ret
= vm_insert_pfn(vma
, (unsigned long)vmf
->virtual_address
, pfn
);
1207 mutex_unlock(&dev
->struct_mutex
);
1212 return VM_FAULT_NOPAGE
;
1215 return VM_FAULT_OOM
;
1217 return VM_FAULT_SIGBUS
;
1222 * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1223 * @obj: obj in question
1225 * GEM memory mapping works by handing back to userspace a fake mmap offset
1226 * it can use in a subsequent mmap(2) call. The DRM core code then looks
1227 * up the object based on the offset and sets up the various memory mapping
1230 * This routine allocates and attaches a fake offset for @obj.
1233 i915_gem_create_mmap_offset(struct drm_gem_object
*obj
)
1235 struct drm_device
*dev
= obj
->dev
;
1236 struct drm_gem_mm
*mm
= dev
->mm_private
;
1237 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1238 struct drm_map_list
*list
;
1239 struct drm_local_map
*map
;
1242 /* Set the object up for mmap'ing */
1243 list
= &obj
->map_list
;
1244 list
->map
= kzalloc(sizeof(struct drm_map_list
), GFP_KERNEL
);
1249 map
->type
= _DRM_GEM
;
1250 map
->size
= obj
->size
;
1253 /* Get a DRM GEM mmap offset allocated... */
1254 list
->file_offset_node
= drm_mm_search_free(&mm
->offset_manager
,
1255 obj
->size
/ PAGE_SIZE
, 0, 0);
1256 if (!list
->file_offset_node
) {
1257 DRM_ERROR("failed to allocate offset for bo %d\n", obj
->name
);
1262 list
->file_offset_node
= drm_mm_get_block(list
->file_offset_node
,
1263 obj
->size
/ PAGE_SIZE
, 0);
1264 if (!list
->file_offset_node
) {
1269 list
->hash
.key
= list
->file_offset_node
->start
;
1270 if (drm_ht_insert_item(&mm
->offset_hash
, &list
->hash
)) {
1271 DRM_ERROR("failed to add to map hash\n");
1276 /* By now we should be all set, any drm_mmap request on the offset
1277 * below will get to our mmap & fault handler */
1278 obj_priv
->mmap_offset
= ((uint64_t) list
->hash
.key
) << PAGE_SHIFT
;
1283 drm_mm_put_block(list
->file_offset_node
);
1291 * i915_gem_release_mmap - remove physical page mappings
1292 * @obj: obj in question
1294 * Preserve the reservation of the mmapping with the DRM core code, but
1295 * relinquish ownership of the pages back to the system.
1297 * It is vital that we remove the page mapping if we have mapped a tiled
1298 * object through the GTT and then lose the fence register due to
1299 * resource pressure. Similarly if the object has been moved out of the
1300 * aperture, than pages mapped into userspace must be revoked. Removing the
1301 * mapping will then trigger a page fault on the next user access, allowing
1302 * fixup by i915_gem_fault().
1305 i915_gem_release_mmap(struct drm_gem_object
*obj
)
1307 struct drm_device
*dev
= obj
->dev
;
1308 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1310 if (dev
->dev_mapping
)
1311 unmap_mapping_range(dev
->dev_mapping
,
1312 obj_priv
->mmap_offset
, obj
->size
, 1);
1316 i915_gem_free_mmap_offset(struct drm_gem_object
*obj
)
1318 struct drm_device
*dev
= obj
->dev
;
1319 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1320 struct drm_gem_mm
*mm
= dev
->mm_private
;
1321 struct drm_map_list
*list
;
1323 list
= &obj
->map_list
;
1324 drm_ht_remove_item(&mm
->offset_hash
, &list
->hash
);
1326 if (list
->file_offset_node
) {
1327 drm_mm_put_block(list
->file_offset_node
);
1328 list
->file_offset_node
= NULL
;
1336 obj_priv
->mmap_offset
= 0;
1340 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1341 * @obj: object to check
1343 * Return the required GTT alignment for an object, taking into account
1344 * potential fence register mapping if needed.
1347 i915_gem_get_gtt_alignment(struct drm_gem_object
*obj
)
1349 struct drm_device
*dev
= obj
->dev
;
1350 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1354 * Minimum alignment is 4k (GTT page size), but might be greater
1355 * if a fence register is needed for the object.
1357 if (IS_I965G(dev
) || obj_priv
->tiling_mode
== I915_TILING_NONE
)
1361 * Previous chips need to be aligned to the size of the smallest
1362 * fence register that can contain the object.
1369 for (i
= start
; i
< obj
->size
; i
<<= 1)
1376 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1378 * @data: GTT mapping ioctl data
1379 * @file_priv: GEM object info
1381 * Simply returns the fake offset to userspace so it can mmap it.
1382 * The mmap call will end up in drm_gem_mmap(), which will set things
1383 * up so we can get faults in the handler above.
1385 * The fault handler will take care of binding the object into the GTT
1386 * (since it may have been evicted to make room for something), allocating
1387 * a fence register, and mapping the appropriate aperture address into
1391 i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
1392 struct drm_file
*file_priv
)
1394 struct drm_i915_gem_mmap_gtt
*args
= data
;
1395 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1396 struct drm_gem_object
*obj
;
1397 struct drm_i915_gem_object
*obj_priv
;
1400 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1403 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1407 mutex_lock(&dev
->struct_mutex
);
1409 obj_priv
= to_intel_bo(obj
);
1411 if (obj_priv
->madv
!= I915_MADV_WILLNEED
) {
1412 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1413 drm_gem_object_unreference(obj
);
1414 mutex_unlock(&dev
->struct_mutex
);
1419 if (!obj_priv
->mmap_offset
) {
1420 ret
= i915_gem_create_mmap_offset(obj
);
1422 drm_gem_object_unreference(obj
);
1423 mutex_unlock(&dev
->struct_mutex
);
1428 args
->offset
= obj_priv
->mmap_offset
;
1431 * Pull it into the GTT so that we have a page list (makes the
1432 * initial fault faster and any subsequent flushing possible).
1434 if (!obj_priv
->agp_mem
) {
1435 ret
= i915_gem_object_bind_to_gtt(obj
, 0);
1437 drm_gem_object_unreference(obj
);
1438 mutex_unlock(&dev
->struct_mutex
);
1441 list_add_tail(&obj_priv
->list
, &dev_priv
->mm
.inactive_list
);
1444 drm_gem_object_unreference(obj
);
1445 mutex_unlock(&dev
->struct_mutex
);
1451 i915_gem_object_put_pages(struct drm_gem_object
*obj
)
1453 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1454 int page_count
= obj
->size
/ PAGE_SIZE
;
1457 BUG_ON(obj_priv
->pages_refcount
== 0);
1458 BUG_ON(obj_priv
->madv
== __I915_MADV_PURGED
);
1460 if (--obj_priv
->pages_refcount
!= 0)
1463 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
)
1464 i915_gem_object_save_bit_17_swizzle(obj
);
1466 if (obj_priv
->madv
== I915_MADV_DONTNEED
)
1467 obj_priv
->dirty
= 0;
1469 for (i
= 0; i
< page_count
; i
++) {
1470 if (obj_priv
->dirty
)
1471 set_page_dirty(obj_priv
->pages
[i
]);
1473 if (obj_priv
->madv
== I915_MADV_WILLNEED
)
1474 mark_page_accessed(obj_priv
->pages
[i
]);
1476 page_cache_release(obj_priv
->pages
[i
]);
1478 obj_priv
->dirty
= 0;
1480 drm_free_large(obj_priv
->pages
);
1481 obj_priv
->pages
= NULL
;
1485 i915_gem_object_move_to_active(struct drm_gem_object
*obj
, uint32_t seqno
,
1486 struct intel_ring_buffer
*ring
)
1488 struct drm_device
*dev
= obj
->dev
;
1489 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1490 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1491 BUG_ON(ring
== NULL
);
1492 obj_priv
->ring
= ring
;
1494 /* Add a reference if we're newly entering the active list. */
1495 if (!obj_priv
->active
) {
1496 drm_gem_object_reference(obj
);
1497 obj_priv
->active
= 1;
1499 /* Move from whatever list we were on to the tail of execution. */
1500 spin_lock(&dev_priv
->mm
.active_list_lock
);
1501 list_move_tail(&obj_priv
->list
, &ring
->active_list
);
1502 spin_unlock(&dev_priv
->mm
.active_list_lock
);
1503 obj_priv
->last_rendering_seqno
= seqno
;
1507 i915_gem_object_move_to_flushing(struct drm_gem_object
*obj
)
1509 struct drm_device
*dev
= obj
->dev
;
1510 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1511 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1513 BUG_ON(!obj_priv
->active
);
1514 list_move_tail(&obj_priv
->list
, &dev_priv
->mm
.flushing_list
);
1515 obj_priv
->last_rendering_seqno
= 0;
1518 /* Immediately discard the backing storage */
1520 i915_gem_object_truncate(struct drm_gem_object
*obj
)
1522 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1523 struct inode
*inode
;
1525 inode
= obj
->filp
->f_path
.dentry
->d_inode
;
1526 if (inode
->i_op
->truncate
)
1527 inode
->i_op
->truncate (inode
);
1529 obj_priv
->madv
= __I915_MADV_PURGED
;
1533 i915_gem_object_is_purgeable(struct drm_i915_gem_object
*obj_priv
)
1535 return obj_priv
->madv
== I915_MADV_DONTNEED
;
1539 i915_gem_object_move_to_inactive(struct drm_gem_object
*obj
)
1541 struct drm_device
*dev
= obj
->dev
;
1542 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1543 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1545 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
1546 if (obj_priv
->pin_count
!= 0)
1547 list_del_init(&obj_priv
->list
);
1549 list_move_tail(&obj_priv
->list
, &dev_priv
->mm
.inactive_list
);
1551 BUG_ON(!list_empty(&obj_priv
->gpu_write_list
));
1553 obj_priv
->last_rendering_seqno
= 0;
1554 obj_priv
->ring
= NULL
;
1555 if (obj_priv
->active
) {
1556 obj_priv
->active
= 0;
1557 drm_gem_object_unreference(obj
);
1559 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
1563 i915_gem_process_flushing_list(struct drm_device
*dev
,
1564 uint32_t flush_domains
, uint32_t seqno
,
1565 struct intel_ring_buffer
*ring
)
1567 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1568 struct drm_i915_gem_object
*obj_priv
, *next
;
1570 list_for_each_entry_safe(obj_priv
, next
,
1571 &dev_priv
->mm
.gpu_write_list
,
1573 struct drm_gem_object
*obj
= &obj_priv
->base
;
1575 if ((obj
->write_domain
& flush_domains
) ==
1576 obj
->write_domain
&&
1577 obj_priv
->ring
->ring_flag
== ring
->ring_flag
) {
1578 uint32_t old_write_domain
= obj
->write_domain
;
1580 obj
->write_domain
= 0;
1581 list_del_init(&obj_priv
->gpu_write_list
);
1582 i915_gem_object_move_to_active(obj
, seqno
, ring
);
1584 /* update the fence lru list */
1585 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
) {
1586 struct drm_i915_fence_reg
*reg
=
1587 &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
1588 list_move_tail(®
->lru_list
,
1589 &dev_priv
->mm
.fence_list
);
1592 trace_i915_gem_object_change_domain(obj
,
1600 i915_add_request(struct drm_device
*dev
, struct drm_file
*file_priv
,
1601 uint32_t flush_domains
, struct intel_ring_buffer
*ring
)
1603 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1604 struct drm_i915_file_private
*i915_file_priv
= NULL
;
1605 struct drm_i915_gem_request
*request
;
1609 if (file_priv
!= NULL
)
1610 i915_file_priv
= file_priv
->driver_priv
;
1612 request
= kzalloc(sizeof(*request
), GFP_KERNEL
);
1613 if (request
== NULL
)
1616 seqno
= ring
->add_request(dev
, ring
, file_priv
, flush_domains
);
1618 request
->seqno
= seqno
;
1619 request
->ring
= ring
;
1620 request
->emitted_jiffies
= jiffies
;
1621 was_empty
= list_empty(&ring
->request_list
);
1622 list_add_tail(&request
->list
, &ring
->request_list
);
1624 if (i915_file_priv
) {
1625 list_add_tail(&request
->client_list
,
1626 &i915_file_priv
->mm
.request_list
);
1628 INIT_LIST_HEAD(&request
->client_list
);
1631 /* Associate any objects on the flushing list matching the write
1632 * domain we're flushing with our flush.
1634 if (flush_domains
!= 0)
1635 i915_gem_process_flushing_list(dev
, flush_domains
, seqno
, ring
);
1637 if (!dev_priv
->mm
.suspended
) {
1638 mod_timer(&dev_priv
->hangcheck_timer
, jiffies
+ DRM_I915_HANGCHECK_PERIOD
);
1640 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, HZ
);
1646 * Command execution barrier
1648 * Ensures that all commands in the ring are finished
1649 * before signalling the CPU
1652 i915_retire_commands(struct drm_device
*dev
, struct intel_ring_buffer
*ring
)
1654 uint32_t flush_domains
= 0;
1656 /* The sampler always gets flushed on i965 (sigh) */
1658 flush_domains
|= I915_GEM_DOMAIN_SAMPLER
;
1660 ring
->flush(dev
, ring
,
1661 I915_GEM_DOMAIN_COMMAND
, flush_domains
);
1662 return flush_domains
;
1666 * Moves buffers associated only with the given active seqno from the active
1667 * to inactive list, potentially freeing them.
1670 i915_gem_retire_request(struct drm_device
*dev
,
1671 struct drm_i915_gem_request
*request
)
1673 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1675 trace_i915_gem_request_retire(dev
, request
->seqno
);
1677 /* Move any buffers on the active list that are no longer referenced
1678 * by the ringbuffer to the flushing/inactive lists as appropriate.
1680 spin_lock(&dev_priv
->mm
.active_list_lock
);
1681 while (!list_empty(&request
->ring
->active_list
)) {
1682 struct drm_gem_object
*obj
;
1683 struct drm_i915_gem_object
*obj_priv
;
1685 obj_priv
= list_first_entry(&request
->ring
->active_list
,
1686 struct drm_i915_gem_object
,
1688 obj
= &obj_priv
->base
;
1690 /* If the seqno being retired doesn't match the oldest in the
1691 * list, then the oldest in the list must still be newer than
1694 if (obj_priv
->last_rendering_seqno
!= request
->seqno
)
1698 DRM_INFO("%s: retire %d moves to inactive list %p\n",
1699 __func__
, request
->seqno
, obj
);
1702 if (obj
->write_domain
!= 0)
1703 i915_gem_object_move_to_flushing(obj
);
1705 /* Take a reference on the object so it won't be
1706 * freed while the spinlock is held. The list
1707 * protection for this spinlock is safe when breaking
1708 * the lock like this since the next thing we do
1709 * is just get the head of the list again.
1711 drm_gem_object_reference(obj
);
1712 i915_gem_object_move_to_inactive(obj
);
1713 spin_unlock(&dev_priv
->mm
.active_list_lock
);
1714 drm_gem_object_unreference(obj
);
1715 spin_lock(&dev_priv
->mm
.active_list_lock
);
1719 spin_unlock(&dev_priv
->mm
.active_list_lock
);
1723 * Returns true if seq1 is later than seq2.
1726 i915_seqno_passed(uint32_t seq1
, uint32_t seq2
)
1728 return (int32_t)(seq1
- seq2
) >= 0;
1732 i915_get_gem_seqno(struct drm_device
*dev
,
1733 struct intel_ring_buffer
*ring
)
1735 return ring
->get_gem_seqno(dev
, ring
);
1739 * This function clears the request list as sequence numbers are passed.
1742 i915_gem_retire_requests(struct drm_device
*dev
,
1743 struct intel_ring_buffer
*ring
)
1745 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1748 if (!ring
->status_page
.page_addr
1749 || list_empty(&ring
->request_list
))
1752 seqno
= i915_get_gem_seqno(dev
, ring
);
1754 while (!list_empty(&ring
->request_list
)) {
1755 struct drm_i915_gem_request
*request
;
1756 uint32_t retiring_seqno
;
1758 request
= list_first_entry(&ring
->request_list
,
1759 struct drm_i915_gem_request
,
1761 retiring_seqno
= request
->seqno
;
1763 if (i915_seqno_passed(seqno
, retiring_seqno
) ||
1764 atomic_read(&dev_priv
->mm
.wedged
)) {
1765 i915_gem_retire_request(dev
, request
);
1767 list_del(&request
->list
);
1768 list_del(&request
->client_list
);
1774 if (unlikely (dev_priv
->trace_irq_seqno
&&
1775 i915_seqno_passed(dev_priv
->trace_irq_seqno
, seqno
))) {
1777 ring
->user_irq_put(dev
, ring
);
1778 dev_priv
->trace_irq_seqno
= 0;
1783 i915_gem_retire_work_handler(struct work_struct
*work
)
1785 drm_i915_private_t
*dev_priv
;
1786 struct drm_device
*dev
;
1788 dev_priv
= container_of(work
, drm_i915_private_t
,
1789 mm
.retire_work
.work
);
1790 dev
= dev_priv
->dev
;
1792 mutex_lock(&dev
->struct_mutex
);
1793 i915_gem_retire_requests(dev
, &dev_priv
->render_ring
);
1796 i915_gem_retire_requests(dev
, &dev_priv
->bsd_ring
);
1798 if (!dev_priv
->mm
.suspended
&&
1799 (!list_empty(&dev_priv
->render_ring
.request_list
) ||
1801 !list_empty(&dev_priv
->bsd_ring
.request_list
))))
1802 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, HZ
);
1803 mutex_unlock(&dev
->struct_mutex
);
1807 i915_do_wait_request(struct drm_device
*dev
, uint32_t seqno
,
1808 int interruptible
, struct intel_ring_buffer
*ring
)
1810 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1816 if (atomic_read(&dev_priv
->mm
.wedged
))
1819 if (!i915_seqno_passed(ring
->get_gem_seqno(dev
, ring
), seqno
)) {
1820 if (HAS_PCH_SPLIT(dev
))
1821 ier
= I915_READ(DEIER
) | I915_READ(GTIER
);
1823 ier
= I915_READ(IER
);
1825 DRM_ERROR("something (likely vbetool) disabled "
1826 "interrupts, re-enabling\n");
1827 i915_driver_irq_preinstall(dev
);
1828 i915_driver_irq_postinstall(dev
);
1831 trace_i915_gem_request_wait_begin(dev
, seqno
);
1833 ring
->waiting_gem_seqno
= seqno
;
1834 ring
->user_irq_get(dev
, ring
);
1836 ret
= wait_event_interruptible(ring
->irq_queue
,
1838 ring
->get_gem_seqno(dev
, ring
), seqno
)
1839 || atomic_read(&dev_priv
->mm
.wedged
));
1841 wait_event(ring
->irq_queue
,
1843 ring
->get_gem_seqno(dev
, ring
), seqno
)
1844 || atomic_read(&dev_priv
->mm
.wedged
));
1846 ring
->user_irq_put(dev
, ring
);
1847 ring
->waiting_gem_seqno
= 0;
1849 trace_i915_gem_request_wait_end(dev
, seqno
);
1851 if (atomic_read(&dev_priv
->mm
.wedged
))
1854 if (ret
&& ret
!= -ERESTARTSYS
)
1855 DRM_ERROR("%s returns %d (awaiting %d at %d)\n",
1856 __func__
, ret
, seqno
, ring
->get_gem_seqno(dev
, ring
));
1858 /* Directly dispatch request retiring. While we have the work queue
1859 * to handle this, the waiter on a request often wants an associated
1860 * buffer to have made it to the inactive list, and we would need
1861 * a separate wait queue to handle that.
1864 i915_gem_retire_requests(dev
, ring
);
1870 * Waits for a sequence number to be signaled, and cleans up the
1871 * request and object lists appropriately for that event.
1874 i915_wait_request(struct drm_device
*dev
, uint32_t seqno
,
1875 struct intel_ring_buffer
*ring
)
1877 return i915_do_wait_request(dev
, seqno
, 1, ring
);
1881 i915_gem_flush(struct drm_device
*dev
,
1882 uint32_t invalidate_domains
,
1883 uint32_t flush_domains
)
1885 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1886 if (flush_domains
& I915_GEM_DOMAIN_CPU
)
1887 drm_agp_chipset_flush(dev
);
1888 dev_priv
->render_ring
.flush(dev
, &dev_priv
->render_ring
,
1893 dev_priv
->bsd_ring
.flush(dev
, &dev_priv
->bsd_ring
,
1899 i915_gem_flush_ring(struct drm_device
*dev
,
1900 uint32_t invalidate_domains
,
1901 uint32_t flush_domains
,
1902 struct intel_ring_buffer
*ring
)
1904 if (flush_domains
& I915_GEM_DOMAIN_CPU
)
1905 drm_agp_chipset_flush(dev
);
1906 ring
->flush(dev
, ring
,
1912 * Ensures that all rendering to the object has completed and the object is
1913 * safe to unbind from the GTT or access from the CPU.
1916 i915_gem_object_wait_rendering(struct drm_gem_object
*obj
)
1918 struct drm_device
*dev
= obj
->dev
;
1919 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1922 /* This function only exists to support waiting for existing rendering,
1923 * not for emitting required flushes.
1925 BUG_ON((obj
->write_domain
& I915_GEM_GPU_DOMAINS
) != 0);
1927 /* If there is rendering queued on the buffer being evicted, wait for
1930 if (obj_priv
->active
) {
1932 DRM_INFO("%s: object %p wait for seqno %08x\n",
1933 __func__
, obj
, obj_priv
->last_rendering_seqno
);
1935 ret
= i915_wait_request(dev
,
1936 obj_priv
->last_rendering_seqno
, obj_priv
->ring
);
1945 * Unbinds an object from the GTT aperture.
1948 i915_gem_object_unbind(struct drm_gem_object
*obj
)
1950 struct drm_device
*dev
= obj
->dev
;
1951 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1952 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1956 DRM_INFO("%s:%d %p\n", __func__
, __LINE__
, obj
);
1957 DRM_INFO("gtt_space %p\n", obj_priv
->gtt_space
);
1959 if (obj_priv
->gtt_space
== NULL
)
1962 if (obj_priv
->pin_count
!= 0) {
1963 DRM_ERROR("Attempting to unbind pinned buffer\n");
1967 /* blow away mappings if mapped through GTT */
1968 i915_gem_release_mmap(obj
);
1970 /* Move the object to the CPU domain to ensure that
1971 * any possible CPU writes while it's not in the GTT
1972 * are flushed when we go to remap it. This will
1973 * also ensure that all pending GPU writes are finished
1976 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
1978 if (ret
!= -ERESTARTSYS
)
1979 DRM_ERROR("set_domain failed: %d\n", ret
);
1983 BUG_ON(obj_priv
->active
);
1985 /* release the fence reg _after_ flushing */
1986 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
)
1987 i915_gem_clear_fence_reg(obj
);
1989 if (obj_priv
->agp_mem
!= NULL
) {
1990 drm_unbind_agp(obj_priv
->agp_mem
);
1991 drm_free_agp(obj_priv
->agp_mem
, obj
->size
/ PAGE_SIZE
);
1992 obj_priv
->agp_mem
= NULL
;
1995 i915_gem_object_put_pages(obj
);
1996 BUG_ON(obj_priv
->pages_refcount
);
1998 if (obj_priv
->gtt_space
) {
1999 atomic_dec(&dev
->gtt_count
);
2000 atomic_sub(obj
->size
, &dev
->gtt_memory
);
2002 drm_mm_put_block(obj_priv
->gtt_space
);
2003 obj_priv
->gtt_space
= NULL
;
2006 /* Remove ourselves from the LRU list if present. */
2007 spin_lock(&dev_priv
->mm
.active_list_lock
);
2008 if (!list_empty(&obj_priv
->list
))
2009 list_del_init(&obj_priv
->list
);
2010 spin_unlock(&dev_priv
->mm
.active_list_lock
);
2012 if (i915_gem_object_is_purgeable(obj_priv
))
2013 i915_gem_object_truncate(obj
);
2015 trace_i915_gem_object_unbind(obj
);
2020 static struct drm_gem_object
*
2021 i915_gem_find_inactive_object(struct drm_device
*dev
, int min_size
)
2023 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2024 struct drm_i915_gem_object
*obj_priv
;
2025 struct drm_gem_object
*best
= NULL
;
2026 struct drm_gem_object
*first
= NULL
;
2028 /* Try to find the smallest clean object */
2029 list_for_each_entry(obj_priv
, &dev_priv
->mm
.inactive_list
, list
) {
2030 struct drm_gem_object
*obj
= &obj_priv
->base
;
2031 if (obj
->size
>= min_size
) {
2032 if ((!obj_priv
->dirty
||
2033 i915_gem_object_is_purgeable(obj_priv
)) &&
2034 (!best
|| obj
->size
< best
->size
)) {
2036 if (best
->size
== min_size
)
2044 return best
? best
: first
;
2048 i915_gpu_idle(struct drm_device
*dev
)
2050 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2052 uint32_t seqno1
, seqno2
;
2055 spin_lock(&dev_priv
->mm
.active_list_lock
);
2056 lists_empty
= (list_empty(&dev_priv
->mm
.flushing_list
) &&
2057 list_empty(&dev_priv
->render_ring
.active_list
) &&
2059 list_empty(&dev_priv
->bsd_ring
.active_list
)));
2060 spin_unlock(&dev_priv
->mm
.active_list_lock
);
2065 /* Flush everything onto the inactive list. */
2066 i915_gem_flush(dev
, I915_GEM_GPU_DOMAINS
, I915_GEM_GPU_DOMAINS
);
2067 seqno1
= i915_add_request(dev
, NULL
, I915_GEM_GPU_DOMAINS
,
2068 &dev_priv
->render_ring
);
2071 ret
= i915_wait_request(dev
, seqno1
, &dev_priv
->render_ring
);
2074 seqno2
= i915_add_request(dev
, NULL
, I915_GEM_GPU_DOMAINS
,
2075 &dev_priv
->bsd_ring
);
2079 ret
= i915_wait_request(dev
, seqno2
, &dev_priv
->bsd_ring
);
2089 i915_gem_evict_everything(struct drm_device
*dev
)
2091 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2095 spin_lock(&dev_priv
->mm
.active_list_lock
);
2096 lists_empty
= (list_empty(&dev_priv
->mm
.inactive_list
) &&
2097 list_empty(&dev_priv
->mm
.flushing_list
) &&
2098 list_empty(&dev_priv
->render_ring
.active_list
) &&
2100 || list_empty(&dev_priv
->bsd_ring
.active_list
)));
2101 spin_unlock(&dev_priv
->mm
.active_list_lock
);
2106 /* Flush everything (on to the inactive lists) and evict */
2107 ret
= i915_gpu_idle(dev
);
2111 BUG_ON(!list_empty(&dev_priv
->mm
.flushing_list
));
2113 ret
= i915_gem_evict_from_inactive_list(dev
);
2117 spin_lock(&dev_priv
->mm
.active_list_lock
);
2118 lists_empty
= (list_empty(&dev_priv
->mm
.inactive_list
) &&
2119 list_empty(&dev_priv
->mm
.flushing_list
) &&
2120 list_empty(&dev_priv
->render_ring
.active_list
) &&
2122 || list_empty(&dev_priv
->bsd_ring
.active_list
)));
2123 spin_unlock(&dev_priv
->mm
.active_list_lock
);
2124 BUG_ON(!lists_empty
);
2130 i915_gem_evict_something(struct drm_device
*dev
, int min_size
)
2132 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2133 struct drm_gem_object
*obj
;
2136 struct intel_ring_buffer
*render_ring
= &dev_priv
->render_ring
;
2137 struct intel_ring_buffer
*bsd_ring
= &dev_priv
->bsd_ring
;
2139 i915_gem_retire_requests(dev
, render_ring
);
2142 i915_gem_retire_requests(dev
, bsd_ring
);
2144 /* If there's an inactive buffer available now, grab it
2147 obj
= i915_gem_find_inactive_object(dev
, min_size
);
2149 struct drm_i915_gem_object
*obj_priv
;
2152 DRM_INFO("%s: evicting %p\n", __func__
, obj
);
2154 obj_priv
= to_intel_bo(obj
);
2155 BUG_ON(obj_priv
->pin_count
!= 0);
2156 BUG_ON(obj_priv
->active
);
2158 /* Wait on the rendering and unbind the buffer. */
2159 return i915_gem_object_unbind(obj
);
2162 /* If we didn't get anything, but the ring is still processing
2163 * things, wait for the next to finish and hopefully leave us
2164 * a buffer to evict.
2166 if (!list_empty(&render_ring
->request_list
)) {
2167 struct drm_i915_gem_request
*request
;
2169 request
= list_first_entry(&render_ring
->request_list
,
2170 struct drm_i915_gem_request
,
2173 ret
= i915_wait_request(dev
,
2174 request
->seqno
, request
->ring
);
2181 if (HAS_BSD(dev
) && !list_empty(&bsd_ring
->request_list
)) {
2182 struct drm_i915_gem_request
*request
;
2184 request
= list_first_entry(&bsd_ring
->request_list
,
2185 struct drm_i915_gem_request
,
2188 ret
= i915_wait_request(dev
,
2189 request
->seqno
, request
->ring
);
2196 /* If we didn't have anything on the request list but there
2197 * are buffers awaiting a flush, emit one and try again.
2198 * When we wait on it, those buffers waiting for that flush
2199 * will get moved to inactive.
2201 if (!list_empty(&dev_priv
->mm
.flushing_list
)) {
2202 struct drm_i915_gem_object
*obj_priv
;
2204 /* Find an object that we can immediately reuse */
2205 list_for_each_entry(obj_priv
, &dev_priv
->mm
.flushing_list
, list
) {
2206 obj
= &obj_priv
->base
;
2207 if (obj
->size
>= min_size
)
2216 i915_gem_flush_ring(dev
,
2220 seqno
= i915_add_request(dev
, NULL
,
2229 /* If we didn't do any of the above, there's no single buffer
2230 * large enough to swap out for the new one, so just evict
2231 * everything and start again. (This should be rare.)
2233 if (!list_empty (&dev_priv
->mm
.inactive_list
))
2234 return i915_gem_evict_from_inactive_list(dev
);
2236 return i915_gem_evict_everything(dev
);
2241 i915_gem_object_get_pages(struct drm_gem_object
*obj
,
2244 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2246 struct address_space
*mapping
;
2247 struct inode
*inode
;
2250 BUG_ON(obj_priv
->pages_refcount
2251 == DRM_I915_GEM_OBJECT_MAX_PAGES_REFCOUNT
);
2253 if (obj_priv
->pages_refcount
++ != 0)
2256 /* Get the list of pages out of our struct file. They'll be pinned
2257 * at this point until we release them.
2259 page_count
= obj
->size
/ PAGE_SIZE
;
2260 BUG_ON(obj_priv
->pages
!= NULL
);
2261 obj_priv
->pages
= drm_calloc_large(page_count
, sizeof(struct page
*));
2262 if (obj_priv
->pages
== NULL
) {
2263 obj_priv
->pages_refcount
--;
2267 inode
= obj
->filp
->f_path
.dentry
->d_inode
;
2268 mapping
= inode
->i_mapping
;
2269 for (i
= 0; i
< page_count
; i
++) {
2270 page
= read_cache_page_gfp(mapping
, i
,
2271 mapping_gfp_mask (mapping
) |
2277 obj_priv
->pages
[i
] = page
;
2280 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
)
2281 i915_gem_object_do_bit_17_swizzle(obj
);
2287 page_cache_release(obj_priv
->pages
[i
]);
2289 drm_free_large(obj_priv
->pages
);
2290 obj_priv
->pages
= NULL
;
2291 obj_priv
->pages_refcount
--;
2292 return PTR_ERR(page
);
2295 static void sandybridge_write_fence_reg(struct drm_i915_fence_reg
*reg
)
2297 struct drm_gem_object
*obj
= reg
->obj
;
2298 struct drm_device
*dev
= obj
->dev
;
2299 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2300 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2301 int regnum
= obj_priv
->fence_reg
;
2304 val
= (uint64_t)((obj_priv
->gtt_offset
+ obj
->size
- 4096) &
2306 val
|= obj_priv
->gtt_offset
& 0xfffff000;
2307 val
|= (uint64_t)((obj_priv
->stride
/ 128) - 1) <<
2308 SANDYBRIDGE_FENCE_PITCH_SHIFT
;
2310 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2311 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
2312 val
|= I965_FENCE_REG_VALID
;
2314 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0
+ (regnum
* 8), val
);
2317 static void i965_write_fence_reg(struct drm_i915_fence_reg
*reg
)
2319 struct drm_gem_object
*obj
= reg
->obj
;
2320 struct drm_device
*dev
= obj
->dev
;
2321 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2322 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2323 int regnum
= obj_priv
->fence_reg
;
2326 val
= (uint64_t)((obj_priv
->gtt_offset
+ obj
->size
- 4096) &
2328 val
|= obj_priv
->gtt_offset
& 0xfffff000;
2329 val
|= ((obj_priv
->stride
/ 128) - 1) << I965_FENCE_PITCH_SHIFT
;
2330 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2331 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
2332 val
|= I965_FENCE_REG_VALID
;
2334 I915_WRITE64(FENCE_REG_965_0
+ (regnum
* 8), val
);
2337 static void i915_write_fence_reg(struct drm_i915_fence_reg
*reg
)
2339 struct drm_gem_object
*obj
= reg
->obj
;
2340 struct drm_device
*dev
= obj
->dev
;
2341 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2342 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2343 int regnum
= obj_priv
->fence_reg
;
2345 uint32_t fence_reg
, val
;
2348 if ((obj_priv
->gtt_offset
& ~I915_FENCE_START_MASK
) ||
2349 (obj_priv
->gtt_offset
& (obj
->size
- 1))) {
2350 WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
2351 __func__
, obj_priv
->gtt_offset
, obj
->size
);
2355 if (obj_priv
->tiling_mode
== I915_TILING_Y
&&
2356 HAS_128_BYTE_Y_TILING(dev
))
2361 /* Note: pitch better be a power of two tile widths */
2362 pitch_val
= obj_priv
->stride
/ tile_width
;
2363 pitch_val
= ffs(pitch_val
) - 1;
2365 if (obj_priv
->tiling_mode
== I915_TILING_Y
&&
2366 HAS_128_BYTE_Y_TILING(dev
))
2367 WARN_ON(pitch_val
> I830_FENCE_MAX_PITCH_VAL
);
2369 WARN_ON(pitch_val
> I915_FENCE_MAX_PITCH_VAL
);
2371 val
= obj_priv
->gtt_offset
;
2372 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2373 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2374 val
|= I915_FENCE_SIZE_BITS(obj
->size
);
2375 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2376 val
|= I830_FENCE_REG_VALID
;
2379 fence_reg
= FENCE_REG_830_0
+ (regnum
* 4);
2381 fence_reg
= FENCE_REG_945_8
+ ((regnum
- 8) * 4);
2382 I915_WRITE(fence_reg
, val
);
2385 static void i830_write_fence_reg(struct drm_i915_fence_reg
*reg
)
2387 struct drm_gem_object
*obj
= reg
->obj
;
2388 struct drm_device
*dev
= obj
->dev
;
2389 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2390 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2391 int regnum
= obj_priv
->fence_reg
;
2394 uint32_t fence_size_bits
;
2396 if ((obj_priv
->gtt_offset
& ~I830_FENCE_START_MASK
) ||
2397 (obj_priv
->gtt_offset
& (obj
->size
- 1))) {
2398 WARN(1, "%s: object 0x%08x not 512K or size aligned\n",
2399 __func__
, obj_priv
->gtt_offset
);
2403 pitch_val
= obj_priv
->stride
/ 128;
2404 pitch_val
= ffs(pitch_val
) - 1;
2405 WARN_ON(pitch_val
> I830_FENCE_MAX_PITCH_VAL
);
2407 val
= obj_priv
->gtt_offset
;
2408 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2409 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2410 fence_size_bits
= I830_FENCE_SIZE_BITS(obj
->size
);
2411 WARN_ON(fence_size_bits
& ~0x00000f00);
2412 val
|= fence_size_bits
;
2413 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2414 val
|= I830_FENCE_REG_VALID
;
2416 I915_WRITE(FENCE_REG_830_0
+ (regnum
* 4), val
);
2419 static int i915_find_fence_reg(struct drm_device
*dev
)
2421 struct drm_i915_fence_reg
*reg
= NULL
;
2422 struct drm_i915_gem_object
*obj_priv
= NULL
;
2423 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2424 struct drm_gem_object
*obj
= NULL
;
2427 /* First try to find a free reg */
2429 for (i
= dev_priv
->fence_reg_start
; i
< dev_priv
->num_fence_regs
; i
++) {
2430 reg
= &dev_priv
->fence_regs
[i
];
2434 obj_priv
= to_intel_bo(reg
->obj
);
2435 if (!obj_priv
->pin_count
)
2442 /* None available, try to steal one or wait for a user to finish */
2443 i
= I915_FENCE_REG_NONE
;
2444 list_for_each_entry(reg
, &dev_priv
->mm
.fence_list
,
2447 obj_priv
= to_intel_bo(obj
);
2449 if (obj_priv
->pin_count
)
2453 i
= obj_priv
->fence_reg
;
2457 BUG_ON(i
== I915_FENCE_REG_NONE
);
2459 /* We only have a reference on obj from the active list. put_fence_reg
2460 * might drop that one, causing a use-after-free in it. So hold a
2461 * private reference to obj like the other callers of put_fence_reg
2462 * (set_tiling ioctl) do. */
2463 drm_gem_object_reference(obj
);
2464 ret
= i915_gem_object_put_fence_reg(obj
);
2465 drm_gem_object_unreference(obj
);
2473 * i915_gem_object_get_fence_reg - set up a fence reg for an object
2474 * @obj: object to map through a fence reg
2476 * When mapping objects through the GTT, userspace wants to be able to write
2477 * to them without having to worry about swizzling if the object is tiled.
2479 * This function walks the fence regs looking for a free one for @obj,
2480 * stealing one if it can't find any.
2482 * It then sets up the reg based on the object's properties: address, pitch
2483 * and tiling format.
2486 i915_gem_object_get_fence_reg(struct drm_gem_object
*obj
)
2488 struct drm_device
*dev
= obj
->dev
;
2489 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2490 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2491 struct drm_i915_fence_reg
*reg
= NULL
;
2494 /* Just update our place in the LRU if our fence is getting used. */
2495 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
) {
2496 reg
= &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
2497 list_move_tail(®
->lru_list
, &dev_priv
->mm
.fence_list
);
2501 switch (obj_priv
->tiling_mode
) {
2502 case I915_TILING_NONE
:
2503 WARN(1, "allocating a fence for non-tiled object?\n");
2506 if (!obj_priv
->stride
)
2508 WARN((obj_priv
->stride
& (512 - 1)),
2509 "object 0x%08x is X tiled but has non-512B pitch\n",
2510 obj_priv
->gtt_offset
);
2513 if (!obj_priv
->stride
)
2515 WARN((obj_priv
->stride
& (128 - 1)),
2516 "object 0x%08x is Y tiled but has non-128B pitch\n",
2517 obj_priv
->gtt_offset
);
2521 ret
= i915_find_fence_reg(dev
);
2525 obj_priv
->fence_reg
= ret
;
2526 reg
= &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
2527 list_add_tail(®
->lru_list
, &dev_priv
->mm
.fence_list
);
2532 sandybridge_write_fence_reg(reg
);
2533 else if (IS_I965G(dev
))
2534 i965_write_fence_reg(reg
);
2535 else if (IS_I9XX(dev
))
2536 i915_write_fence_reg(reg
);
2538 i830_write_fence_reg(reg
);
2540 trace_i915_gem_object_get_fence(obj
, obj_priv
->fence_reg
,
2541 obj_priv
->tiling_mode
);
2547 * i915_gem_clear_fence_reg - clear out fence register info
2548 * @obj: object to clear
2550 * Zeroes out the fence register itself and clears out the associated
2551 * data structures in dev_priv and obj_priv.
2554 i915_gem_clear_fence_reg(struct drm_gem_object
*obj
)
2556 struct drm_device
*dev
= obj
->dev
;
2557 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2558 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2559 struct drm_i915_fence_reg
*reg
=
2560 &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
2563 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0
+
2564 (obj_priv
->fence_reg
* 8), 0);
2565 } else if (IS_I965G(dev
)) {
2566 I915_WRITE64(FENCE_REG_965_0
+ (obj_priv
->fence_reg
* 8), 0);
2570 if (obj_priv
->fence_reg
< 8)
2571 fence_reg
= FENCE_REG_830_0
+ obj_priv
->fence_reg
* 4;
2573 fence_reg
= FENCE_REG_945_8
+ (obj_priv
->fence_reg
-
2576 I915_WRITE(fence_reg
, 0);
2580 obj_priv
->fence_reg
= I915_FENCE_REG_NONE
;
2581 list_del_init(®
->lru_list
);
2585 * i915_gem_object_put_fence_reg - waits on outstanding fenced access
2586 * to the buffer to finish, and then resets the fence register.
2587 * @obj: tiled object holding a fence register.
2589 * Zeroes out the fence register itself and clears out the associated
2590 * data structures in dev_priv and obj_priv.
2593 i915_gem_object_put_fence_reg(struct drm_gem_object
*obj
)
2595 struct drm_device
*dev
= obj
->dev
;
2596 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2598 if (obj_priv
->fence_reg
== I915_FENCE_REG_NONE
)
2601 /* If we've changed tiling, GTT-mappings of the object
2602 * need to re-fault to ensure that the correct fence register
2603 * setup is in place.
2605 i915_gem_release_mmap(obj
);
2607 /* On the i915, GPU access to tiled buffers is via a fence,
2608 * therefore we must wait for any outstanding access to complete
2609 * before clearing the fence.
2611 if (!IS_I965G(dev
)) {
2614 i915_gem_object_flush_gpu_write_domain(obj
);
2615 ret
= i915_gem_object_wait_rendering(obj
);
2620 i915_gem_object_flush_gtt_write_domain(obj
);
2621 i915_gem_clear_fence_reg (obj
);
2627 * Finds free space in the GTT aperture and binds the object there.
2630 i915_gem_object_bind_to_gtt(struct drm_gem_object
*obj
, unsigned alignment
)
2632 struct drm_device
*dev
= obj
->dev
;
2633 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2634 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2635 struct drm_mm_node
*free_space
;
2636 gfp_t gfpmask
= __GFP_NORETRY
| __GFP_NOWARN
;
2639 if (obj_priv
->madv
!= I915_MADV_WILLNEED
) {
2640 DRM_ERROR("Attempting to bind a purgeable object\n");
2645 alignment
= i915_gem_get_gtt_alignment(obj
);
2646 if (alignment
& (i915_gem_get_gtt_alignment(obj
) - 1)) {
2647 DRM_ERROR("Invalid object alignment requested %u\n", alignment
);
2651 /* If the object is bigger than the entire aperture, reject it early
2652 * before evicting everything in a vain attempt to find space.
2654 if (obj
->size
> dev
->gtt_total
) {
2655 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2660 free_space
= drm_mm_search_free(&dev_priv
->mm
.gtt_space
,
2661 obj
->size
, alignment
, 0);
2662 if (free_space
!= NULL
) {
2663 obj_priv
->gtt_space
= drm_mm_get_block(free_space
, obj
->size
,
2665 if (obj_priv
->gtt_space
!= NULL
) {
2666 obj_priv
->gtt_space
->private = obj
;
2667 obj_priv
->gtt_offset
= obj_priv
->gtt_space
->start
;
2670 if (obj_priv
->gtt_space
== NULL
) {
2671 /* If the gtt is empty and we're still having trouble
2672 * fitting our object in, we're out of memory.
2675 DRM_INFO("%s: GTT full, evicting something\n", __func__
);
2677 ret
= i915_gem_evict_something(dev
, obj
->size
);
2685 DRM_INFO("Binding object of size %zd at 0x%08x\n",
2686 obj
->size
, obj_priv
->gtt_offset
);
2688 ret
= i915_gem_object_get_pages(obj
, gfpmask
);
2690 drm_mm_put_block(obj_priv
->gtt_space
);
2691 obj_priv
->gtt_space
= NULL
;
2693 if (ret
== -ENOMEM
) {
2694 /* first try to clear up some space from the GTT */
2695 ret
= i915_gem_evict_something(dev
, obj
->size
);
2697 /* now try to shrink everyone else */
2712 /* Create an AGP memory structure pointing at our pages, and bind it
2715 obj_priv
->agp_mem
= drm_agp_bind_pages(dev
,
2717 obj
->size
>> PAGE_SHIFT
,
2718 obj_priv
->gtt_offset
,
2719 obj_priv
->agp_type
);
2720 if (obj_priv
->agp_mem
== NULL
) {
2721 i915_gem_object_put_pages(obj
);
2722 drm_mm_put_block(obj_priv
->gtt_space
);
2723 obj_priv
->gtt_space
= NULL
;
2725 ret
= i915_gem_evict_something(dev
, obj
->size
);
2731 atomic_inc(&dev
->gtt_count
);
2732 atomic_add(obj
->size
, &dev
->gtt_memory
);
2734 /* Assert that the object is not currently in any GPU domain. As it
2735 * wasn't in the GTT, there shouldn't be any way it could have been in
2738 BUG_ON(obj
->read_domains
& I915_GEM_GPU_DOMAINS
);
2739 BUG_ON(obj
->write_domain
& I915_GEM_GPU_DOMAINS
);
2741 trace_i915_gem_object_bind(obj
, obj_priv
->gtt_offset
);
2747 i915_gem_clflush_object(struct drm_gem_object
*obj
)
2749 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2751 /* If we don't have a page list set up, then we're not pinned
2752 * to GPU, and we can ignore the cache flush because it'll happen
2753 * again at bind time.
2755 if (obj_priv
->pages
== NULL
)
2758 trace_i915_gem_object_clflush(obj
);
2760 drm_clflush_pages(obj_priv
->pages
, obj
->size
/ PAGE_SIZE
);
2763 /** Flushes any GPU write domain for the object if it's dirty. */
2765 i915_gem_object_flush_gpu_write_domain(struct drm_gem_object
*obj
)
2767 struct drm_device
*dev
= obj
->dev
;
2768 uint32_t old_write_domain
;
2769 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2771 if ((obj
->write_domain
& I915_GEM_GPU_DOMAINS
) == 0)
2774 /* Queue the GPU write cache flushing we need. */
2775 old_write_domain
= obj
->write_domain
;
2776 i915_gem_flush(dev
, 0, obj
->write_domain
);
2777 (void) i915_add_request(dev
, NULL
, obj
->write_domain
, obj_priv
->ring
);
2778 BUG_ON(obj
->write_domain
);
2780 trace_i915_gem_object_change_domain(obj
,
2785 /** Flushes the GTT write domain for the object if it's dirty. */
2787 i915_gem_object_flush_gtt_write_domain(struct drm_gem_object
*obj
)
2789 uint32_t old_write_domain
;
2791 if (obj
->write_domain
!= I915_GEM_DOMAIN_GTT
)
2794 /* No actual flushing is required for the GTT write domain. Writes
2795 * to it immediately go to main memory as far as we know, so there's
2796 * no chipset flush. It also doesn't land in render cache.
2798 old_write_domain
= obj
->write_domain
;
2799 obj
->write_domain
= 0;
2801 trace_i915_gem_object_change_domain(obj
,
2806 /** Flushes the CPU write domain for the object if it's dirty. */
2808 i915_gem_object_flush_cpu_write_domain(struct drm_gem_object
*obj
)
2810 struct drm_device
*dev
= obj
->dev
;
2811 uint32_t old_write_domain
;
2813 if (obj
->write_domain
!= I915_GEM_DOMAIN_CPU
)
2816 i915_gem_clflush_object(obj
);
2817 drm_agp_chipset_flush(dev
);
2818 old_write_domain
= obj
->write_domain
;
2819 obj
->write_domain
= 0;
2821 trace_i915_gem_object_change_domain(obj
,
2827 i915_gem_object_flush_write_domain(struct drm_gem_object
*obj
)
2829 switch (obj
->write_domain
) {
2830 case I915_GEM_DOMAIN_GTT
:
2831 i915_gem_object_flush_gtt_write_domain(obj
);
2833 case I915_GEM_DOMAIN_CPU
:
2834 i915_gem_object_flush_cpu_write_domain(obj
);
2837 i915_gem_object_flush_gpu_write_domain(obj
);
2843 * Moves a single object to the GTT read, and possibly write domain.
2845 * This function returns when the move is complete, including waiting on
2849 i915_gem_object_set_to_gtt_domain(struct drm_gem_object
*obj
, int write
)
2851 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2852 uint32_t old_write_domain
, old_read_domains
;
2855 /* Not valid to be called on unbound objects. */
2856 if (obj_priv
->gtt_space
== NULL
)
2859 i915_gem_object_flush_gpu_write_domain(obj
);
2860 /* Wait on any GPU rendering and flushing to occur. */
2861 ret
= i915_gem_object_wait_rendering(obj
);
2865 old_write_domain
= obj
->write_domain
;
2866 old_read_domains
= obj
->read_domains
;
2868 /* If we're writing through the GTT domain, then CPU and GPU caches
2869 * will need to be invalidated at next use.
2872 obj
->read_domains
&= I915_GEM_DOMAIN_GTT
;
2874 i915_gem_object_flush_cpu_write_domain(obj
);
2876 /* It should now be out of any other write domains, and we can update
2877 * the domain values for our changes.
2879 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
2880 obj
->read_domains
|= I915_GEM_DOMAIN_GTT
;
2882 obj
->write_domain
= I915_GEM_DOMAIN_GTT
;
2883 obj_priv
->dirty
= 1;
2886 trace_i915_gem_object_change_domain(obj
,
2894 * Prepare buffer for display plane. Use uninterruptible for possible flush
2895 * wait, as in modesetting process we're not supposed to be interrupted.
2898 i915_gem_object_set_to_display_plane(struct drm_gem_object
*obj
)
2900 struct drm_device
*dev
= obj
->dev
;
2901 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2902 uint32_t old_write_domain
, old_read_domains
;
2905 /* Not valid to be called on unbound objects. */
2906 if (obj_priv
->gtt_space
== NULL
)
2909 i915_gem_object_flush_gpu_write_domain(obj
);
2911 /* Wait on any GPU rendering and flushing to occur. */
2912 if (obj_priv
->active
) {
2914 DRM_INFO("%s: object %p wait for seqno %08x\n",
2915 __func__
, obj
, obj_priv
->last_rendering_seqno
);
2917 ret
= i915_do_wait_request(dev
,
2918 obj_priv
->last_rendering_seqno
,
2925 i915_gem_object_flush_cpu_write_domain(obj
);
2927 old_write_domain
= obj
->write_domain
;
2928 old_read_domains
= obj
->read_domains
;
2930 /* It should now be out of any other write domains, and we can update
2931 * the domain values for our changes.
2933 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
2934 obj
->read_domains
= I915_GEM_DOMAIN_GTT
;
2935 obj
->write_domain
= I915_GEM_DOMAIN_GTT
;
2936 obj_priv
->dirty
= 1;
2938 trace_i915_gem_object_change_domain(obj
,
2946 * Moves a single object to the CPU read, and possibly write domain.
2948 * This function returns when the move is complete, including waiting on
2952 i915_gem_object_set_to_cpu_domain(struct drm_gem_object
*obj
, int write
)
2954 uint32_t old_write_domain
, old_read_domains
;
2957 i915_gem_object_flush_gpu_write_domain(obj
);
2958 /* Wait on any GPU rendering and flushing to occur. */
2959 ret
= i915_gem_object_wait_rendering(obj
);
2963 i915_gem_object_flush_gtt_write_domain(obj
);
2965 /* If we have a partially-valid cache of the object in the CPU,
2966 * finish invalidating it and free the per-page flags.
2968 i915_gem_object_set_to_full_cpu_read_domain(obj
);
2970 old_write_domain
= obj
->write_domain
;
2971 old_read_domains
= obj
->read_domains
;
2973 /* Flush the CPU cache if it's still invalid. */
2974 if ((obj
->read_domains
& I915_GEM_DOMAIN_CPU
) == 0) {
2975 i915_gem_clflush_object(obj
);
2977 obj
->read_domains
|= I915_GEM_DOMAIN_CPU
;
2980 /* It should now be out of any other write domains, and we can update
2981 * the domain values for our changes.
2983 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
2985 /* If we're writing through the CPU, then the GPU read domains will
2986 * need to be invalidated at next use.
2989 obj
->read_domains
&= I915_GEM_DOMAIN_CPU
;
2990 obj
->write_domain
= I915_GEM_DOMAIN_CPU
;
2993 trace_i915_gem_object_change_domain(obj
,
3001 * Set the next domain for the specified object. This
3002 * may not actually perform the necessary flushing/invaliding though,
3003 * as that may want to be batched with other set_domain operations
3005 * This is (we hope) the only really tricky part of gem. The goal
3006 * is fairly simple -- track which caches hold bits of the object
3007 * and make sure they remain coherent. A few concrete examples may
3008 * help to explain how it works. For shorthand, we use the notation
3009 * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
3010 * a pair of read and write domain masks.
3012 * Case 1: the batch buffer
3018 * 5. Unmapped from GTT
3021 * Let's take these a step at a time
3024 * Pages allocated from the kernel may still have
3025 * cache contents, so we set them to (CPU, CPU) always.
3026 * 2. Written by CPU (using pwrite)
3027 * The pwrite function calls set_domain (CPU, CPU) and
3028 * this function does nothing (as nothing changes)
3030 * This function asserts that the object is not
3031 * currently in any GPU-based read or write domains
3033 * i915_gem_execbuffer calls set_domain (COMMAND, 0).
3034 * As write_domain is zero, this function adds in the
3035 * current read domains (CPU+COMMAND, 0).
3036 * flush_domains is set to CPU.
3037 * invalidate_domains is set to COMMAND
3038 * clflush is run to get data out of the CPU caches
3039 * then i915_dev_set_domain calls i915_gem_flush to
3040 * emit an MI_FLUSH and drm_agp_chipset_flush
3041 * 5. Unmapped from GTT
3042 * i915_gem_object_unbind calls set_domain (CPU, CPU)
3043 * flush_domains and invalidate_domains end up both zero
3044 * so no flushing/invalidating happens
3048 * Case 2: The shared render buffer
3052 * 3. Read/written by GPU
3053 * 4. set_domain to (CPU,CPU)
3054 * 5. Read/written by CPU
3055 * 6. Read/written by GPU
3058 * Same as last example, (CPU, CPU)
3060 * Nothing changes (assertions find that it is not in the GPU)
3061 * 3. Read/written by GPU
3062 * execbuffer calls set_domain (RENDER, RENDER)
3063 * flush_domains gets CPU
3064 * invalidate_domains gets GPU
3066 * MI_FLUSH and drm_agp_chipset_flush
3067 * 4. set_domain (CPU, CPU)
3068 * flush_domains gets GPU
3069 * invalidate_domains gets CPU
3070 * wait_rendering (obj) to make sure all drawing is complete.
3071 * This will include an MI_FLUSH to get the data from GPU
3073 * clflush (obj) to invalidate the CPU cache
3074 * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
3075 * 5. Read/written by CPU
3076 * cache lines are loaded and dirtied
3077 * 6. Read written by GPU
3078 * Same as last GPU access
3080 * Case 3: The constant buffer
3085 * 4. Updated (written) by CPU again
3094 * flush_domains = CPU
3095 * invalidate_domains = RENDER
3098 * drm_agp_chipset_flush
3099 * 4. Updated (written) by CPU again
3101 * flush_domains = 0 (no previous write domain)
3102 * invalidate_domains = 0 (no new read domains)
3105 * flush_domains = CPU
3106 * invalidate_domains = RENDER
3109 * drm_agp_chipset_flush
3112 i915_gem_object_set_to_gpu_domain(struct drm_gem_object
*obj
)
3114 struct drm_device
*dev
= obj
->dev
;
3115 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
3116 uint32_t invalidate_domains
= 0;
3117 uint32_t flush_domains
= 0;
3118 uint32_t old_read_domains
;
3120 BUG_ON(obj
->pending_read_domains
& I915_GEM_DOMAIN_CPU
);
3121 BUG_ON(obj
->pending_write_domain
== I915_GEM_DOMAIN_CPU
);
3123 intel_mark_busy(dev
, obj
);
3126 DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
3128 obj
->read_domains
, obj
->pending_read_domains
,
3129 obj
->write_domain
, obj
->pending_write_domain
);
3132 * If the object isn't moving to a new write domain,
3133 * let the object stay in multiple read domains
3135 if (obj
->pending_write_domain
== 0)
3136 obj
->pending_read_domains
|= obj
->read_domains
;
3138 obj_priv
->dirty
= 1;
3141 * Flush the current write domain if
3142 * the new read domains don't match. Invalidate
3143 * any read domains which differ from the old
3146 if (obj
->write_domain
&&
3147 obj
->write_domain
!= obj
->pending_read_domains
) {
3148 flush_domains
|= obj
->write_domain
;
3149 invalidate_domains
|=
3150 obj
->pending_read_domains
& ~obj
->write_domain
;
3153 * Invalidate any read caches which may have
3154 * stale data. That is, any new read domains.
3156 invalidate_domains
|= obj
->pending_read_domains
& ~obj
->read_domains
;
3157 if ((flush_domains
| invalidate_domains
) & I915_GEM_DOMAIN_CPU
) {
3159 DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
3160 __func__
, flush_domains
, invalidate_domains
);
3162 i915_gem_clflush_object(obj
);
3165 old_read_domains
= obj
->read_domains
;
3167 /* The actual obj->write_domain will be updated with
3168 * pending_write_domain after we emit the accumulated flush for all
3169 * of our domain changes in execbuffers (which clears objects'
3170 * write_domains). So if we have a current write domain that we
3171 * aren't changing, set pending_write_domain to that.
3173 if (flush_domains
== 0 && obj
->pending_write_domain
== 0)
3174 obj
->pending_write_domain
= obj
->write_domain
;
3175 obj
->read_domains
= obj
->pending_read_domains
;
3177 dev
->invalidate_domains
|= invalidate_domains
;
3178 dev
->flush_domains
|= flush_domains
;
3180 DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n",
3182 obj
->read_domains
, obj
->write_domain
,
3183 dev
->invalidate_domains
, dev
->flush_domains
);
3186 trace_i915_gem_object_change_domain(obj
,
3192 * Moves the object from a partially CPU read to a full one.
3194 * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3195 * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
3198 i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object
*obj
)
3200 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
3202 if (!obj_priv
->page_cpu_valid
)
3205 /* If we're partially in the CPU read domain, finish moving it in.
3207 if (obj
->read_domains
& I915_GEM_DOMAIN_CPU
) {
3210 for (i
= 0; i
<= (obj
->size
- 1) / PAGE_SIZE
; i
++) {
3211 if (obj_priv
->page_cpu_valid
[i
])
3213 drm_clflush_pages(obj_priv
->pages
+ i
, 1);
3217 /* Free the page_cpu_valid mappings which are now stale, whether
3218 * or not we've got I915_GEM_DOMAIN_CPU.
3220 kfree(obj_priv
->page_cpu_valid
);
3221 obj_priv
->page_cpu_valid
= NULL
;
3225 * Set the CPU read domain on a range of the object.
3227 * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3228 * not entirely valid. The page_cpu_valid member of the object flags which
3229 * pages have been flushed, and will be respected by
3230 * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3231 * of the whole object.
3233 * This function returns when the move is complete, including waiting on
3237 i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object
*obj
,
3238 uint64_t offset
, uint64_t size
)
3240 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
3241 uint32_t old_read_domains
;
3244 if (offset
== 0 && size
== obj
->size
)
3245 return i915_gem_object_set_to_cpu_domain(obj
, 0);
3247 i915_gem_object_flush_gpu_write_domain(obj
);
3248 /* Wait on any GPU rendering and flushing to occur. */
3249 ret
= i915_gem_object_wait_rendering(obj
);
3252 i915_gem_object_flush_gtt_write_domain(obj
);
3254 /* If we're already fully in the CPU read domain, we're done. */
3255 if (obj_priv
->page_cpu_valid
== NULL
&&
3256 (obj
->read_domains
& I915_GEM_DOMAIN_CPU
) != 0)
3259 /* Otherwise, create/clear the per-page CPU read domain flag if we're
3260 * newly adding I915_GEM_DOMAIN_CPU
3262 if (obj_priv
->page_cpu_valid
== NULL
) {
3263 obj_priv
->page_cpu_valid
= kzalloc(obj
->size
/ PAGE_SIZE
,
3265 if (obj_priv
->page_cpu_valid
== NULL
)
3267 } else if ((obj
->read_domains
& I915_GEM_DOMAIN_CPU
) == 0)
3268 memset(obj_priv
->page_cpu_valid
, 0, obj
->size
/ PAGE_SIZE
);
3270 /* Flush the cache on any pages that are still invalid from the CPU's
3273 for (i
= offset
/ PAGE_SIZE
; i
<= (offset
+ size
- 1) / PAGE_SIZE
;
3275 if (obj_priv
->page_cpu_valid
[i
])
3278 drm_clflush_pages(obj_priv
->pages
+ i
, 1);
3280 obj_priv
->page_cpu_valid
[i
] = 1;
3283 /* It should now be out of any other write domains, and we can update
3284 * the domain values for our changes.
3286 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
3288 old_read_domains
= obj
->read_domains
;
3289 obj
->read_domains
|= I915_GEM_DOMAIN_CPU
;
3291 trace_i915_gem_object_change_domain(obj
,
3299 * Pin an object to the GTT and evaluate the relocations landing in it.
3302 i915_gem_object_pin_and_relocate(struct drm_gem_object
*obj
,
3303 struct drm_file
*file_priv
,
3304 struct drm_i915_gem_exec_object2
*entry
,
3305 struct drm_i915_gem_relocation_entry
*relocs
)
3307 struct drm_device
*dev
= obj
->dev
;
3308 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3309 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
3311 void __iomem
*reloc_page
;
3314 need_fence
= entry
->flags
& EXEC_OBJECT_NEEDS_FENCE
&&
3315 obj_priv
->tiling_mode
!= I915_TILING_NONE
;
3317 /* Check fence reg constraints and rebind if necessary */
3319 !i915_gem_object_fence_offset_ok(obj
,
3320 obj_priv
->tiling_mode
)) {
3321 ret
= i915_gem_object_unbind(obj
);
3326 /* Choose the GTT offset for our buffer and put it there. */
3327 ret
= i915_gem_object_pin(obj
, (uint32_t) entry
->alignment
);
3332 * Pre-965 chips need a fence register set up in order to
3333 * properly handle blits to/from tiled surfaces.
3336 ret
= i915_gem_object_get_fence_reg(obj
);
3338 i915_gem_object_unpin(obj
);
3343 entry
->offset
= obj_priv
->gtt_offset
;
3345 /* Apply the relocations, using the GTT aperture to avoid cache
3346 * flushing requirements.
3348 for (i
= 0; i
< entry
->relocation_count
; i
++) {
3349 struct drm_i915_gem_relocation_entry
*reloc
= &relocs
[i
];
3350 struct drm_gem_object
*target_obj
;
3351 struct drm_i915_gem_object
*target_obj_priv
;
3352 uint32_t reloc_val
, reloc_offset
;
3353 uint32_t __iomem
*reloc_entry
;
3355 target_obj
= drm_gem_object_lookup(obj
->dev
, file_priv
,
3356 reloc
->target_handle
);
3357 if (target_obj
== NULL
) {
3358 i915_gem_object_unpin(obj
);
3361 target_obj_priv
= to_intel_bo(target_obj
);
3364 DRM_INFO("%s: obj %p offset %08x target %d "
3365 "read %08x write %08x gtt %08x "
3366 "presumed %08x delta %08x\n",
3369 (int) reloc
->offset
,
3370 (int) reloc
->target_handle
,
3371 (int) reloc
->read_domains
,
3372 (int) reloc
->write_domain
,
3373 (int) target_obj_priv
->gtt_offset
,
3374 (int) reloc
->presumed_offset
,
3378 /* The target buffer should have appeared before us in the
3379 * exec_object list, so it should have a GTT space bound by now.
3381 if (target_obj_priv
->gtt_space
== NULL
) {
3382 DRM_ERROR("No GTT space found for object %d\n",
3383 reloc
->target_handle
);
3384 drm_gem_object_unreference(target_obj
);
3385 i915_gem_object_unpin(obj
);
3389 /* Validate that the target is in a valid r/w GPU domain */
3390 if (reloc
->write_domain
& (reloc
->write_domain
- 1)) {
3391 DRM_ERROR("reloc with multiple write domains: "
3392 "obj %p target %d offset %d "
3393 "read %08x write %08x",
3394 obj
, reloc
->target_handle
,
3395 (int) reloc
->offset
,
3396 reloc
->read_domains
,
3397 reloc
->write_domain
);
3400 if (reloc
->write_domain
& I915_GEM_DOMAIN_CPU
||
3401 reloc
->read_domains
& I915_GEM_DOMAIN_CPU
) {
3402 DRM_ERROR("reloc with read/write CPU domains: "
3403 "obj %p target %d offset %d "
3404 "read %08x write %08x",
3405 obj
, reloc
->target_handle
,
3406 (int) reloc
->offset
,
3407 reloc
->read_domains
,
3408 reloc
->write_domain
);
3409 drm_gem_object_unreference(target_obj
);
3410 i915_gem_object_unpin(obj
);
3413 if (reloc
->write_domain
&& target_obj
->pending_write_domain
&&
3414 reloc
->write_domain
!= target_obj
->pending_write_domain
) {
3415 DRM_ERROR("Write domain conflict: "
3416 "obj %p target %d offset %d "
3417 "new %08x old %08x\n",
3418 obj
, reloc
->target_handle
,
3419 (int) reloc
->offset
,
3420 reloc
->write_domain
,
3421 target_obj
->pending_write_domain
);
3422 drm_gem_object_unreference(target_obj
);
3423 i915_gem_object_unpin(obj
);
3427 target_obj
->pending_read_domains
|= reloc
->read_domains
;
3428 target_obj
->pending_write_domain
|= reloc
->write_domain
;
3430 /* If the relocation already has the right value in it, no
3431 * more work needs to be done.
3433 if (target_obj_priv
->gtt_offset
== reloc
->presumed_offset
) {
3434 drm_gem_object_unreference(target_obj
);
3438 /* Check that the relocation address is valid... */
3439 if (reloc
->offset
> obj
->size
- 4) {
3440 DRM_ERROR("Relocation beyond object bounds: "
3441 "obj %p target %d offset %d size %d.\n",
3442 obj
, reloc
->target_handle
,
3443 (int) reloc
->offset
, (int) obj
->size
);
3444 drm_gem_object_unreference(target_obj
);
3445 i915_gem_object_unpin(obj
);
3448 if (reloc
->offset
& 3) {
3449 DRM_ERROR("Relocation not 4-byte aligned: "
3450 "obj %p target %d offset %d.\n",
3451 obj
, reloc
->target_handle
,
3452 (int) reloc
->offset
);
3453 drm_gem_object_unreference(target_obj
);
3454 i915_gem_object_unpin(obj
);
3458 /* and points to somewhere within the target object. */
3459 if (reloc
->delta
>= target_obj
->size
) {
3460 DRM_ERROR("Relocation beyond target object bounds: "
3461 "obj %p target %d delta %d size %d.\n",
3462 obj
, reloc
->target_handle
,
3463 (int) reloc
->delta
, (int) target_obj
->size
);
3464 drm_gem_object_unreference(target_obj
);
3465 i915_gem_object_unpin(obj
);
3469 ret
= i915_gem_object_set_to_gtt_domain(obj
, 1);
3471 drm_gem_object_unreference(target_obj
);
3472 i915_gem_object_unpin(obj
);
3476 /* Map the page containing the relocation we're going to
3479 reloc_offset
= obj_priv
->gtt_offset
+ reloc
->offset
;
3480 reloc_page
= io_mapping_map_atomic_wc(dev_priv
->mm
.gtt_mapping
,
3483 reloc_entry
= (uint32_t __iomem
*)(reloc_page
+
3484 (reloc_offset
& (PAGE_SIZE
- 1)));
3485 reloc_val
= target_obj_priv
->gtt_offset
+ reloc
->delta
;
3488 DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n",
3489 obj
, (unsigned int) reloc
->offset
,
3490 readl(reloc_entry
), reloc_val
);
3492 writel(reloc_val
, reloc_entry
);
3493 io_mapping_unmap_atomic(reloc_page
);
3495 /* The updated presumed offset for this entry will be
3496 * copied back out to the user.
3498 reloc
->presumed_offset
= target_obj_priv
->gtt_offset
;
3500 drm_gem_object_unreference(target_obj
);
3505 i915_gem_dump_object(obj
, 128, __func__
, ~0);
3510 /* Throttle our rendering by waiting until the ring has completed our requests
3511 * emitted over 20 msec ago.
3513 * Note that if we were to use the current jiffies each time around the loop,
3514 * we wouldn't escape the function with any frames outstanding if the time to
3515 * render a frame was over 20ms.
3517 * This should get us reasonable parallelism between CPU and GPU but also
3518 * relatively low latency when blocking on a particular request to finish.
3521 i915_gem_ring_throttle(struct drm_device
*dev
, struct drm_file
*file_priv
)
3523 struct drm_i915_file_private
*i915_file_priv
= file_priv
->driver_priv
;
3525 unsigned long recent_enough
= jiffies
- msecs_to_jiffies(20);
3527 mutex_lock(&dev
->struct_mutex
);
3528 while (!list_empty(&i915_file_priv
->mm
.request_list
)) {
3529 struct drm_i915_gem_request
*request
;
3531 request
= list_first_entry(&i915_file_priv
->mm
.request_list
,
3532 struct drm_i915_gem_request
,
3535 if (time_after_eq(request
->emitted_jiffies
, recent_enough
))
3538 ret
= i915_wait_request(dev
, request
->seqno
, request
->ring
);
3542 mutex_unlock(&dev
->struct_mutex
);
3548 i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object2
*exec_list
,
3549 uint32_t buffer_count
,
3550 struct drm_i915_gem_relocation_entry
**relocs
)
3552 uint32_t reloc_count
= 0, reloc_index
= 0, i
;
3556 for (i
= 0; i
< buffer_count
; i
++) {
3557 if (reloc_count
+ exec_list
[i
].relocation_count
< reloc_count
)
3559 reloc_count
+= exec_list
[i
].relocation_count
;
3562 *relocs
= drm_calloc_large(reloc_count
, sizeof(**relocs
));
3563 if (*relocs
== NULL
) {
3564 DRM_ERROR("failed to alloc relocs, count %d\n", reloc_count
);
3568 for (i
= 0; i
< buffer_count
; i
++) {
3569 struct drm_i915_gem_relocation_entry __user
*user_relocs
;
3571 user_relocs
= (void __user
*)(uintptr_t)exec_list
[i
].relocs_ptr
;
3573 ret
= copy_from_user(&(*relocs
)[reloc_index
],
3575 exec_list
[i
].relocation_count
*
3578 drm_free_large(*relocs
);
3583 reloc_index
+= exec_list
[i
].relocation_count
;
3590 i915_gem_put_relocs_to_user(struct drm_i915_gem_exec_object2
*exec_list
,
3591 uint32_t buffer_count
,
3592 struct drm_i915_gem_relocation_entry
*relocs
)
3594 uint32_t reloc_count
= 0, i
;
3600 for (i
= 0; i
< buffer_count
; i
++) {
3601 struct drm_i915_gem_relocation_entry __user
*user_relocs
;
3604 user_relocs
= (void __user
*)(uintptr_t)exec_list
[i
].relocs_ptr
;
3606 unwritten
= copy_to_user(user_relocs
,
3607 &relocs
[reloc_count
],
3608 exec_list
[i
].relocation_count
*
3616 reloc_count
+= exec_list
[i
].relocation_count
;
3620 drm_free_large(relocs
);
3626 i915_gem_check_execbuffer (struct drm_i915_gem_execbuffer2
*exec
,
3627 uint64_t exec_offset
)
3629 uint32_t exec_start
, exec_len
;
3631 exec_start
= (uint32_t) exec_offset
+ exec
->batch_start_offset
;
3632 exec_len
= (uint32_t) exec
->batch_len
;
3634 if ((exec_start
| exec_len
) & 0x7)
3644 i915_gem_wait_for_pending_flip(struct drm_device
*dev
,
3645 struct drm_gem_object
**object_list
,
3648 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3649 struct drm_i915_gem_object
*obj_priv
;
3654 prepare_to_wait(&dev_priv
->pending_flip_queue
,
3655 &wait
, TASK_INTERRUPTIBLE
);
3656 for (i
= 0; i
< count
; i
++) {
3657 obj_priv
= to_intel_bo(object_list
[i
]);
3658 if (atomic_read(&obj_priv
->pending_flip
) > 0)
3664 if (!signal_pending(current
)) {
3665 mutex_unlock(&dev
->struct_mutex
);
3667 mutex_lock(&dev
->struct_mutex
);
3673 finish_wait(&dev_priv
->pending_flip_queue
, &wait
);
3679 i915_gem_do_execbuffer(struct drm_device
*dev
, void *data
,
3680 struct drm_file
*file_priv
,
3681 struct drm_i915_gem_execbuffer2
*args
,
3682 struct drm_i915_gem_exec_object2
*exec_list
)
3684 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3685 struct drm_gem_object
**object_list
= NULL
;
3686 struct drm_gem_object
*batch_obj
;
3687 struct drm_i915_gem_object
*obj_priv
;
3688 struct drm_clip_rect
*cliprects
= NULL
;
3689 struct drm_i915_gem_relocation_entry
*relocs
= NULL
;
3690 int ret
= 0, ret2
, i
, pinned
= 0;
3691 uint64_t exec_offset
;
3692 uint32_t seqno
, flush_domains
, reloc_index
;
3693 int pin_tries
, flips
;
3695 struct intel_ring_buffer
*ring
= NULL
;
3698 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3699 (int) args
->buffers_ptr
, args
->buffer_count
, args
->batch_len
);
3701 if (args
->flags
& I915_EXEC_BSD
) {
3702 if (!HAS_BSD(dev
)) {
3703 DRM_ERROR("execbuf with wrong flag\n");
3706 ring
= &dev_priv
->bsd_ring
;
3708 ring
= &dev_priv
->render_ring
;
3712 if (args
->buffer_count
< 1) {
3713 DRM_ERROR("execbuf with %d buffers\n", args
->buffer_count
);
3716 object_list
= drm_malloc_ab(sizeof(*object_list
), args
->buffer_count
);
3717 if (object_list
== NULL
) {
3718 DRM_ERROR("Failed to allocate object list for %d buffers\n",
3719 args
->buffer_count
);
3724 if (args
->num_cliprects
!= 0) {
3725 cliprects
= kcalloc(args
->num_cliprects
, sizeof(*cliprects
),
3727 if (cliprects
== NULL
) {
3732 ret
= copy_from_user(cliprects
,
3733 (struct drm_clip_rect __user
*)
3734 (uintptr_t) args
->cliprects_ptr
,
3735 sizeof(*cliprects
) * args
->num_cliprects
);
3737 DRM_ERROR("copy %d cliprects failed: %d\n",
3738 args
->num_cliprects
, ret
);
3743 ret
= i915_gem_get_relocs_from_user(exec_list
, args
->buffer_count
,
3748 mutex_lock(&dev
->struct_mutex
);
3750 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3752 if (atomic_read(&dev_priv
->mm
.wedged
)) {
3753 mutex_unlock(&dev
->struct_mutex
);
3758 if (dev_priv
->mm
.suspended
) {
3759 mutex_unlock(&dev
->struct_mutex
);
3764 /* Look up object handles */
3766 for (i
= 0; i
< args
->buffer_count
; i
++) {
3767 object_list
[i
] = drm_gem_object_lookup(dev
, file_priv
,
3768 exec_list
[i
].handle
);
3769 if (object_list
[i
] == NULL
) {
3770 DRM_ERROR("Invalid object handle %d at index %d\n",
3771 exec_list
[i
].handle
, i
);
3772 /* prevent error path from reading uninitialized data */
3773 args
->buffer_count
= i
+ 1;
3778 obj_priv
= to_intel_bo(object_list
[i
]);
3779 if (obj_priv
->in_execbuffer
) {
3780 DRM_ERROR("Object %p appears more than once in object list\n",
3782 /* prevent error path from reading uninitialized data */
3783 args
->buffer_count
= i
+ 1;
3787 obj_priv
->in_execbuffer
= true;
3788 flips
+= atomic_read(&obj_priv
->pending_flip
);
3792 ret
= i915_gem_wait_for_pending_flip(dev
, object_list
,
3793 args
->buffer_count
);
3798 /* Pin and relocate */
3799 for (pin_tries
= 0; ; pin_tries
++) {
3803 for (i
= 0; i
< args
->buffer_count
; i
++) {
3804 object_list
[i
]->pending_read_domains
= 0;
3805 object_list
[i
]->pending_write_domain
= 0;
3806 ret
= i915_gem_object_pin_and_relocate(object_list
[i
],
3809 &relocs
[reloc_index
]);
3813 reloc_index
+= exec_list
[i
].relocation_count
;
3819 /* error other than GTT full, or we've already tried again */
3820 if (ret
!= -ENOSPC
|| pin_tries
>= 1) {
3821 if (ret
!= -ERESTARTSYS
) {
3822 unsigned long long total_size
= 0;
3824 for (i
= 0; i
< args
->buffer_count
; i
++) {
3825 obj_priv
= object_list
[i
]->driver_private
;
3827 total_size
+= object_list
[i
]->size
;
3829 exec_list
[i
].flags
& EXEC_OBJECT_NEEDS_FENCE
&&
3830 obj_priv
->tiling_mode
!= I915_TILING_NONE
;
3832 DRM_ERROR("Failed to pin buffer %d of %d, total %llu bytes, %d fences: %d\n",
3833 pinned
+1, args
->buffer_count
,
3834 total_size
, num_fences
,
3836 DRM_ERROR("%d objects [%d pinned], "
3837 "%d object bytes [%d pinned], "
3838 "%d/%d gtt bytes\n",
3839 atomic_read(&dev
->object_count
),
3840 atomic_read(&dev
->pin_count
),
3841 atomic_read(&dev
->object_memory
),
3842 atomic_read(&dev
->pin_memory
),
3843 atomic_read(&dev
->gtt_memory
),
3849 /* unpin all of our buffers */
3850 for (i
= 0; i
< pinned
; i
++)
3851 i915_gem_object_unpin(object_list
[i
]);
3854 /* evict everyone we can from the aperture */
3855 ret
= i915_gem_evict_everything(dev
);
3856 if (ret
&& ret
!= -ENOSPC
)
3860 /* Set the pending read domains for the batch buffer to COMMAND */
3861 batch_obj
= object_list
[args
->buffer_count
-1];
3862 if (batch_obj
->pending_write_domain
) {
3863 DRM_ERROR("Attempting to use self-modifying batch buffer\n");
3867 batch_obj
->pending_read_domains
|= I915_GEM_DOMAIN_COMMAND
;
3869 /* Sanity check the batch buffer, prior to moving objects */
3870 exec_offset
= exec_list
[args
->buffer_count
- 1].offset
;
3871 ret
= i915_gem_check_execbuffer (args
, exec_offset
);
3873 DRM_ERROR("execbuf with invalid offset/length\n");
3877 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3879 /* Zero the global flush/invalidate flags. These
3880 * will be modified as new domains are computed
3883 dev
->invalidate_domains
= 0;
3884 dev
->flush_domains
= 0;
3886 for (i
= 0; i
< args
->buffer_count
; i
++) {
3887 struct drm_gem_object
*obj
= object_list
[i
];
3889 /* Compute new gpu domains and update invalidate/flush */
3890 i915_gem_object_set_to_gpu_domain(obj
);
3893 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3895 if (dev
->invalidate_domains
| dev
->flush_domains
) {
3897 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
3899 dev
->invalidate_domains
,
3900 dev
->flush_domains
);
3903 dev
->invalidate_domains
,
3904 dev
->flush_domains
);
3905 if (dev
->flush_domains
& I915_GEM_GPU_DOMAINS
) {
3906 (void)i915_add_request(dev
, file_priv
,
3908 &dev_priv
->render_ring
);
3911 (void)i915_add_request(dev
, file_priv
,
3913 &dev_priv
->bsd_ring
);
3917 for (i
= 0; i
< args
->buffer_count
; i
++) {
3918 struct drm_gem_object
*obj
= object_list
[i
];
3919 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
3920 uint32_t old_write_domain
= obj
->write_domain
;
3922 obj
->write_domain
= obj
->pending_write_domain
;
3923 if (obj
->write_domain
)
3924 list_move_tail(&obj_priv
->gpu_write_list
,
3925 &dev_priv
->mm
.gpu_write_list
);
3927 list_del_init(&obj_priv
->gpu_write_list
);
3929 trace_i915_gem_object_change_domain(obj
,
3934 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3937 for (i
= 0; i
< args
->buffer_count
; i
++) {
3938 i915_gem_object_check_coherency(object_list
[i
],
3939 exec_list
[i
].handle
);
3944 i915_gem_dump_object(batch_obj
,
3950 /* Exec the batchbuffer */
3951 ret
= ring
->dispatch_gem_execbuffer(dev
, ring
, args
,
3952 cliprects
, exec_offset
);
3954 DRM_ERROR("dispatch failed %d\n", ret
);
3959 * Ensure that the commands in the batch buffer are
3960 * finished before the interrupt fires
3962 flush_domains
= i915_retire_commands(dev
, ring
);
3964 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3967 * Get a seqno representing the execution of the current buffer,
3968 * which we can wait on. We would like to mitigate these interrupts,
3969 * likely by only creating seqnos occasionally (so that we have
3970 * *some* interrupts representing completion of buffers that we can
3971 * wait on when trying to clear up gtt space).
3973 seqno
= i915_add_request(dev
, file_priv
, flush_domains
, ring
);
3975 for (i
= 0; i
< args
->buffer_count
; i
++) {
3976 struct drm_gem_object
*obj
= object_list
[i
];
3977 obj_priv
= to_intel_bo(obj
);
3979 i915_gem_object_move_to_active(obj
, seqno
, ring
);
3981 DRM_INFO("%s: move to exec list %p\n", __func__
, obj
);
3985 i915_dump_lru(dev
, __func__
);
3988 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3991 for (i
= 0; i
< pinned
; i
++)
3992 i915_gem_object_unpin(object_list
[i
]);
3994 for (i
= 0; i
< args
->buffer_count
; i
++) {
3995 if (object_list
[i
]) {
3996 obj_priv
= to_intel_bo(object_list
[i
]);
3997 obj_priv
->in_execbuffer
= false;
3999 drm_gem_object_unreference(object_list
[i
]);
4002 mutex_unlock(&dev
->struct_mutex
);
4005 /* Copy the updated relocations out regardless of current error
4006 * state. Failure to update the relocs would mean that the next
4007 * time userland calls execbuf, it would do so with presumed offset
4008 * state that didn't match the actual object state.
4010 ret2
= i915_gem_put_relocs_to_user(exec_list
, args
->buffer_count
,
4013 DRM_ERROR("Failed to copy relocations back out: %d\n", ret2
);
4019 drm_free_large(object_list
);
4026 * Legacy execbuffer just creates an exec2 list from the original exec object
4027 * list array and passes it to the real function.
4030 i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
4031 struct drm_file
*file_priv
)
4033 struct drm_i915_gem_execbuffer
*args
= data
;
4034 struct drm_i915_gem_execbuffer2 exec2
;
4035 struct drm_i915_gem_exec_object
*exec_list
= NULL
;
4036 struct drm_i915_gem_exec_object2
*exec2_list
= NULL
;
4040 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
4041 (int) args
->buffers_ptr
, args
->buffer_count
, args
->batch_len
);
4044 if (args
->buffer_count
< 1) {
4045 DRM_ERROR("execbuf with %d buffers\n", args
->buffer_count
);
4049 /* Copy in the exec list from userland */
4050 exec_list
= drm_malloc_ab(sizeof(*exec_list
), args
->buffer_count
);
4051 exec2_list
= drm_malloc_ab(sizeof(*exec2_list
), args
->buffer_count
);
4052 if (exec_list
== NULL
|| exec2_list
== NULL
) {
4053 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
4054 args
->buffer_count
);
4055 drm_free_large(exec_list
);
4056 drm_free_large(exec2_list
);
4059 ret
= copy_from_user(exec_list
,
4060 (struct drm_i915_relocation_entry __user
*)
4061 (uintptr_t) args
->buffers_ptr
,
4062 sizeof(*exec_list
) * args
->buffer_count
);
4064 DRM_ERROR("copy %d exec entries failed %d\n",
4065 args
->buffer_count
, ret
);
4066 drm_free_large(exec_list
);
4067 drm_free_large(exec2_list
);
4071 for (i
= 0; i
< args
->buffer_count
; i
++) {
4072 exec2_list
[i
].handle
= exec_list
[i
].handle
;
4073 exec2_list
[i
].relocation_count
= exec_list
[i
].relocation_count
;
4074 exec2_list
[i
].relocs_ptr
= exec_list
[i
].relocs_ptr
;
4075 exec2_list
[i
].alignment
= exec_list
[i
].alignment
;
4076 exec2_list
[i
].offset
= exec_list
[i
].offset
;
4078 exec2_list
[i
].flags
= EXEC_OBJECT_NEEDS_FENCE
;
4080 exec2_list
[i
].flags
= 0;
4083 exec2
.buffers_ptr
= args
->buffers_ptr
;
4084 exec2
.buffer_count
= args
->buffer_count
;
4085 exec2
.batch_start_offset
= args
->batch_start_offset
;
4086 exec2
.batch_len
= args
->batch_len
;
4087 exec2
.DR1
= args
->DR1
;
4088 exec2
.DR4
= args
->DR4
;
4089 exec2
.num_cliprects
= args
->num_cliprects
;
4090 exec2
.cliprects_ptr
= args
->cliprects_ptr
;
4091 exec2
.flags
= I915_EXEC_RENDER
;
4093 ret
= i915_gem_do_execbuffer(dev
, data
, file_priv
, &exec2
, exec2_list
);
4095 /* Copy the new buffer offsets back to the user's exec list. */
4096 for (i
= 0; i
< args
->buffer_count
; i
++)
4097 exec_list
[i
].offset
= exec2_list
[i
].offset
;
4098 /* ... and back out to userspace */
4099 ret
= copy_to_user((struct drm_i915_relocation_entry __user
*)
4100 (uintptr_t) args
->buffers_ptr
,
4102 sizeof(*exec_list
) * args
->buffer_count
);
4105 DRM_ERROR("failed to copy %d exec entries "
4106 "back to user (%d)\n",
4107 args
->buffer_count
, ret
);
4111 drm_free_large(exec_list
);
4112 drm_free_large(exec2_list
);
4117 i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
4118 struct drm_file
*file_priv
)
4120 struct drm_i915_gem_execbuffer2
*args
= data
;
4121 struct drm_i915_gem_exec_object2
*exec2_list
= NULL
;
4125 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
4126 (int) args
->buffers_ptr
, args
->buffer_count
, args
->batch_len
);
4129 if (args
->buffer_count
< 1) {
4130 DRM_ERROR("execbuf2 with %d buffers\n", args
->buffer_count
);
4134 exec2_list
= drm_malloc_ab(sizeof(*exec2_list
), args
->buffer_count
);
4135 if (exec2_list
== NULL
) {
4136 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
4137 args
->buffer_count
);
4140 ret
= copy_from_user(exec2_list
,
4141 (struct drm_i915_relocation_entry __user
*)
4142 (uintptr_t) args
->buffers_ptr
,
4143 sizeof(*exec2_list
) * args
->buffer_count
);
4145 DRM_ERROR("copy %d exec entries failed %d\n",
4146 args
->buffer_count
, ret
);
4147 drm_free_large(exec2_list
);
4151 ret
= i915_gem_do_execbuffer(dev
, data
, file_priv
, args
, exec2_list
);
4153 /* Copy the new buffer offsets back to the user's exec list. */
4154 ret
= copy_to_user((struct drm_i915_relocation_entry __user
*)
4155 (uintptr_t) args
->buffers_ptr
,
4157 sizeof(*exec2_list
) * args
->buffer_count
);
4160 DRM_ERROR("failed to copy %d exec entries "
4161 "back to user (%d)\n",
4162 args
->buffer_count
, ret
);
4166 drm_free_large(exec2_list
);
4171 i915_gem_object_pin(struct drm_gem_object
*obj
, uint32_t alignment
)
4173 struct drm_device
*dev
= obj
->dev
;
4174 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
4177 BUG_ON(obj_priv
->pin_count
== DRM_I915_GEM_OBJECT_MAX_PIN_COUNT
);
4179 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
4181 if (obj_priv
->gtt_space
!= NULL
) {
4183 alignment
= i915_gem_get_gtt_alignment(obj
);
4184 if (obj_priv
->gtt_offset
& (alignment
- 1)) {
4185 ret
= i915_gem_object_unbind(obj
);
4191 if (obj_priv
->gtt_space
== NULL
) {
4192 ret
= i915_gem_object_bind_to_gtt(obj
, alignment
);
4197 obj_priv
->pin_count
++;
4199 /* If the object is not active and not pending a flush,
4200 * remove it from the inactive list
4202 if (obj_priv
->pin_count
== 1) {
4203 atomic_inc(&dev
->pin_count
);
4204 atomic_add(obj
->size
, &dev
->pin_memory
);
4205 if (!obj_priv
->active
&&
4206 (obj
->write_domain
& I915_GEM_GPU_DOMAINS
) == 0 &&
4207 !list_empty(&obj_priv
->list
))
4208 list_del_init(&obj_priv
->list
);
4210 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
4216 i915_gem_object_unpin(struct drm_gem_object
*obj
)
4218 struct drm_device
*dev
= obj
->dev
;
4219 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4220 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
4222 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
4223 obj_priv
->pin_count
--;
4224 BUG_ON(obj_priv
->pin_count
< 0);
4225 BUG_ON(obj_priv
->gtt_space
== NULL
);
4227 /* If the object is no longer pinned, and is
4228 * neither active nor being flushed, then stick it on
4231 if (obj_priv
->pin_count
== 0) {
4232 if (!obj_priv
->active
&&
4233 (obj
->write_domain
& I915_GEM_GPU_DOMAINS
) == 0)
4234 list_move_tail(&obj_priv
->list
,
4235 &dev_priv
->mm
.inactive_list
);
4236 atomic_dec(&dev
->pin_count
);
4237 atomic_sub(obj
->size
, &dev
->pin_memory
);
4239 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
4243 i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
4244 struct drm_file
*file_priv
)
4246 struct drm_i915_gem_pin
*args
= data
;
4247 struct drm_gem_object
*obj
;
4248 struct drm_i915_gem_object
*obj_priv
;
4251 mutex_lock(&dev
->struct_mutex
);
4253 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4255 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
4257 mutex_unlock(&dev
->struct_mutex
);
4260 obj_priv
= to_intel_bo(obj
);
4262 if (obj_priv
->madv
!= I915_MADV_WILLNEED
) {
4263 DRM_ERROR("Attempting to pin a purgeable buffer\n");
4264 drm_gem_object_unreference(obj
);
4265 mutex_unlock(&dev
->struct_mutex
);
4269 if (obj_priv
->pin_filp
!= NULL
&& obj_priv
->pin_filp
!= file_priv
) {
4270 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
4272 drm_gem_object_unreference(obj
);
4273 mutex_unlock(&dev
->struct_mutex
);
4277 obj_priv
->user_pin_count
++;
4278 obj_priv
->pin_filp
= file_priv
;
4279 if (obj_priv
->user_pin_count
== 1) {
4280 ret
= i915_gem_object_pin(obj
, args
->alignment
);
4282 drm_gem_object_unreference(obj
);
4283 mutex_unlock(&dev
->struct_mutex
);
4288 /* XXX - flush the CPU caches for pinned objects
4289 * as the X server doesn't manage domains yet
4291 i915_gem_object_flush_cpu_write_domain(obj
);
4292 args
->offset
= obj_priv
->gtt_offset
;
4293 drm_gem_object_unreference(obj
);
4294 mutex_unlock(&dev
->struct_mutex
);
4300 i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
4301 struct drm_file
*file_priv
)
4303 struct drm_i915_gem_pin
*args
= data
;
4304 struct drm_gem_object
*obj
;
4305 struct drm_i915_gem_object
*obj_priv
;
4307 mutex_lock(&dev
->struct_mutex
);
4309 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4311 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
4313 mutex_unlock(&dev
->struct_mutex
);
4317 obj_priv
= to_intel_bo(obj
);
4318 if (obj_priv
->pin_filp
!= file_priv
) {
4319 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4321 drm_gem_object_unreference(obj
);
4322 mutex_unlock(&dev
->struct_mutex
);
4325 obj_priv
->user_pin_count
--;
4326 if (obj_priv
->user_pin_count
== 0) {
4327 obj_priv
->pin_filp
= NULL
;
4328 i915_gem_object_unpin(obj
);
4331 drm_gem_object_unreference(obj
);
4332 mutex_unlock(&dev
->struct_mutex
);
4337 i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
4338 struct drm_file
*file_priv
)
4340 struct drm_i915_gem_busy
*args
= data
;
4341 struct drm_gem_object
*obj
;
4342 struct drm_i915_gem_object
*obj_priv
;
4343 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4345 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4347 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
4352 mutex_lock(&dev
->struct_mutex
);
4353 /* Update the active list for the hardware's current position.
4354 * Otherwise this only updates on a delayed timer or when irqs are
4355 * actually unmasked, and our working set ends up being larger than
4358 i915_gem_retire_requests(dev
, &dev_priv
->render_ring
);
4361 i915_gem_retire_requests(dev
, &dev_priv
->bsd_ring
);
4363 obj_priv
= to_intel_bo(obj
);
4364 /* Don't count being on the flushing list against the object being
4365 * done. Otherwise, a buffer left on the flushing list but not getting
4366 * flushed (because nobody's flushing that domain) won't ever return
4367 * unbusy and get reused by libdrm's bo cache. The other expected
4368 * consumer of this interface, OpenGL's occlusion queries, also specs
4369 * that the objects get unbusy "eventually" without any interference.
4371 args
->busy
= obj_priv
->active
&& obj_priv
->last_rendering_seqno
!= 0;
4373 drm_gem_object_unreference(obj
);
4374 mutex_unlock(&dev
->struct_mutex
);
4379 i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
4380 struct drm_file
*file_priv
)
4382 return i915_gem_ring_throttle(dev
, file_priv
);
4386 i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
4387 struct drm_file
*file_priv
)
4389 struct drm_i915_gem_madvise
*args
= data
;
4390 struct drm_gem_object
*obj
;
4391 struct drm_i915_gem_object
*obj_priv
;
4393 switch (args
->madv
) {
4394 case I915_MADV_DONTNEED
:
4395 case I915_MADV_WILLNEED
:
4401 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4403 DRM_ERROR("Bad handle in i915_gem_madvise_ioctl(): %d\n",
4408 mutex_lock(&dev
->struct_mutex
);
4409 obj_priv
= to_intel_bo(obj
);
4411 if (obj_priv
->pin_count
) {
4412 drm_gem_object_unreference(obj
);
4413 mutex_unlock(&dev
->struct_mutex
);
4415 DRM_ERROR("Attempted i915_gem_madvise_ioctl() on a pinned object\n");
4419 if (obj_priv
->madv
!= __I915_MADV_PURGED
)
4420 obj_priv
->madv
= args
->madv
;
4422 /* if the object is no longer bound, discard its backing storage */
4423 if (i915_gem_object_is_purgeable(obj_priv
) &&
4424 obj_priv
->gtt_space
== NULL
)
4425 i915_gem_object_truncate(obj
);
4427 args
->retained
= obj_priv
->madv
!= __I915_MADV_PURGED
;
4429 drm_gem_object_unreference(obj
);
4430 mutex_unlock(&dev
->struct_mutex
);
4435 struct drm_gem_object
* i915_gem_alloc_object(struct drm_device
*dev
,
4438 struct drm_i915_gem_object
*obj
;
4440 obj
= kzalloc(sizeof(*obj
), GFP_KERNEL
);
4444 if (drm_gem_object_init(dev
, &obj
->base
, size
) != 0) {
4449 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
4450 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
4452 obj
->agp_type
= AGP_USER_MEMORY
;
4453 obj
->base
.driver_private
= NULL
;
4454 obj
->fence_reg
= I915_FENCE_REG_NONE
;
4455 INIT_LIST_HEAD(&obj
->list
);
4456 INIT_LIST_HEAD(&obj
->gpu_write_list
);
4457 obj
->madv
= I915_MADV_WILLNEED
;
4459 trace_i915_gem_object_create(&obj
->base
);
4464 int i915_gem_init_object(struct drm_gem_object
*obj
)
4471 void i915_gem_free_object(struct drm_gem_object
*obj
)
4473 struct drm_device
*dev
= obj
->dev
;
4474 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
4476 trace_i915_gem_object_destroy(obj
);
4478 while (obj_priv
->pin_count
> 0)
4479 i915_gem_object_unpin(obj
);
4481 if (obj_priv
->phys_obj
)
4482 i915_gem_detach_phys_object(dev
, obj
);
4484 i915_gem_object_unbind(obj
);
4486 if (obj_priv
->mmap_offset
)
4487 i915_gem_free_mmap_offset(obj
);
4489 drm_gem_object_release(obj
);
4491 kfree(obj_priv
->page_cpu_valid
);
4492 kfree(obj_priv
->bit_17
);
4496 /** Unbinds all inactive objects. */
4498 i915_gem_evict_from_inactive_list(struct drm_device
*dev
)
4500 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4502 while (!list_empty(&dev_priv
->mm
.inactive_list
)) {
4503 struct drm_gem_object
*obj
;
4506 obj
= &list_first_entry(&dev_priv
->mm
.inactive_list
,
4507 struct drm_i915_gem_object
,
4510 ret
= i915_gem_object_unbind(obj
);
4512 DRM_ERROR("Error unbinding object: %d\n", ret
);
4521 i915_gem_idle(struct drm_device
*dev
)
4523 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4526 mutex_lock(&dev
->struct_mutex
);
4528 if (dev_priv
->mm
.suspended
||
4529 (dev_priv
->render_ring
.gem_object
== NULL
) ||
4531 dev_priv
->bsd_ring
.gem_object
== NULL
)) {
4532 mutex_unlock(&dev
->struct_mutex
);
4536 ret
= i915_gpu_idle(dev
);
4538 mutex_unlock(&dev
->struct_mutex
);
4542 /* Under UMS, be paranoid and evict. */
4543 if (!drm_core_check_feature(dev
, DRIVER_MODESET
)) {
4544 ret
= i915_gem_evict_from_inactive_list(dev
);
4546 mutex_unlock(&dev
->struct_mutex
);
4551 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4552 * We need to replace this with a semaphore, or something.
4553 * And not confound mm.suspended!
4555 dev_priv
->mm
.suspended
= 1;
4556 del_timer(&dev_priv
->hangcheck_timer
);
4558 i915_kernel_lost_context(dev
);
4559 i915_gem_cleanup_ringbuffer(dev
);
4561 mutex_unlock(&dev
->struct_mutex
);
4563 /* Cancel the retire work handler, which should be idle now. */
4564 cancel_delayed_work_sync(&dev_priv
->mm
.retire_work
);
4570 * 965+ support PIPE_CONTROL commands, which provide finer grained control
4571 * over cache flushing.
4574 i915_gem_init_pipe_control(struct drm_device
*dev
)
4576 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4577 struct drm_gem_object
*obj
;
4578 struct drm_i915_gem_object
*obj_priv
;
4581 obj
= i915_gem_alloc_object(dev
, 4096);
4583 DRM_ERROR("Failed to allocate seqno page\n");
4587 obj_priv
= to_intel_bo(obj
);
4588 obj_priv
->agp_type
= AGP_USER_CACHED_MEMORY
;
4590 ret
= i915_gem_object_pin(obj
, 4096);
4594 dev_priv
->seqno_gfx_addr
= obj_priv
->gtt_offset
;
4595 dev_priv
->seqno_page
= kmap(obj_priv
->pages
[0]);
4596 if (dev_priv
->seqno_page
== NULL
)
4599 dev_priv
->seqno_obj
= obj
;
4600 memset(dev_priv
->seqno_page
, 0, PAGE_SIZE
);
4605 i915_gem_object_unpin(obj
);
4607 drm_gem_object_unreference(obj
);
4614 i915_gem_cleanup_pipe_control(struct drm_device
*dev
)
4616 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4617 struct drm_gem_object
*obj
;
4618 struct drm_i915_gem_object
*obj_priv
;
4620 obj
= dev_priv
->seqno_obj
;
4621 obj_priv
= to_intel_bo(obj
);
4622 kunmap(obj_priv
->pages
[0]);
4623 i915_gem_object_unpin(obj
);
4624 drm_gem_object_unreference(obj
);
4625 dev_priv
->seqno_obj
= NULL
;
4627 dev_priv
->seqno_page
= NULL
;
4631 i915_gem_init_ringbuffer(struct drm_device
*dev
)
4633 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4636 dev_priv
->render_ring
= render_ring
;
4638 if (!I915_NEED_GFX_HWS(dev
)) {
4639 dev_priv
->render_ring
.status_page
.page_addr
4640 = dev_priv
->status_page_dmah
->vaddr
;
4641 memset(dev_priv
->render_ring
.status_page
.page_addr
,
4645 if (HAS_PIPE_CONTROL(dev
)) {
4646 ret
= i915_gem_init_pipe_control(dev
);
4651 ret
= intel_init_ring_buffer(dev
, &dev_priv
->render_ring
);
4653 goto cleanup_pipe_control
;
4656 dev_priv
->bsd_ring
= bsd_ring
;
4657 ret
= intel_init_ring_buffer(dev
, &dev_priv
->bsd_ring
);
4659 goto cleanup_render_ring
;
4664 cleanup_render_ring
:
4665 intel_cleanup_ring_buffer(dev
, &dev_priv
->render_ring
);
4666 cleanup_pipe_control
:
4667 if (HAS_PIPE_CONTROL(dev
))
4668 i915_gem_cleanup_pipe_control(dev
);
4673 i915_gem_cleanup_ringbuffer(struct drm_device
*dev
)
4675 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4677 intel_cleanup_ring_buffer(dev
, &dev_priv
->render_ring
);
4679 intel_cleanup_ring_buffer(dev
, &dev_priv
->bsd_ring
);
4680 if (HAS_PIPE_CONTROL(dev
))
4681 i915_gem_cleanup_pipe_control(dev
);
4685 i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
4686 struct drm_file
*file_priv
)
4688 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4691 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4694 if (atomic_read(&dev_priv
->mm
.wedged
)) {
4695 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4696 atomic_set(&dev_priv
->mm
.wedged
, 0);
4699 mutex_lock(&dev
->struct_mutex
);
4700 dev_priv
->mm
.suspended
= 0;
4702 ret
= i915_gem_init_ringbuffer(dev
);
4704 mutex_unlock(&dev
->struct_mutex
);
4708 spin_lock(&dev_priv
->mm
.active_list_lock
);
4709 BUG_ON(!list_empty(&dev_priv
->render_ring
.active_list
));
4710 BUG_ON(HAS_BSD(dev
) && !list_empty(&dev_priv
->bsd_ring
.active_list
));
4711 spin_unlock(&dev_priv
->mm
.active_list_lock
);
4713 BUG_ON(!list_empty(&dev_priv
->mm
.flushing_list
));
4714 BUG_ON(!list_empty(&dev_priv
->mm
.inactive_list
));
4715 BUG_ON(!list_empty(&dev_priv
->render_ring
.request_list
));
4716 BUG_ON(HAS_BSD(dev
) && !list_empty(&dev_priv
->bsd_ring
.request_list
));
4717 mutex_unlock(&dev
->struct_mutex
);
4719 drm_irq_install(dev
);
4725 i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
4726 struct drm_file
*file_priv
)
4728 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4731 drm_irq_uninstall(dev
);
4732 return i915_gem_idle(dev
);
4736 i915_gem_lastclose(struct drm_device
*dev
)
4740 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4743 ret
= i915_gem_idle(dev
);
4745 DRM_ERROR("failed to idle hardware: %d\n", ret
);
4749 i915_gem_load(struct drm_device
*dev
)
4752 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4754 spin_lock_init(&dev_priv
->mm
.active_list_lock
);
4755 INIT_LIST_HEAD(&dev_priv
->mm
.flushing_list
);
4756 INIT_LIST_HEAD(&dev_priv
->mm
.gpu_write_list
);
4757 INIT_LIST_HEAD(&dev_priv
->mm
.inactive_list
);
4758 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
4759 INIT_LIST_HEAD(&dev_priv
->render_ring
.active_list
);
4760 INIT_LIST_HEAD(&dev_priv
->render_ring
.request_list
);
4762 INIT_LIST_HEAD(&dev_priv
->bsd_ring
.active_list
);
4763 INIT_LIST_HEAD(&dev_priv
->bsd_ring
.request_list
);
4765 for (i
= 0; i
< 16; i
++)
4766 INIT_LIST_HEAD(&dev_priv
->fence_regs
[i
].lru_list
);
4767 INIT_DELAYED_WORK(&dev_priv
->mm
.retire_work
,
4768 i915_gem_retire_work_handler
);
4769 spin_lock(&shrink_list_lock
);
4770 list_add(&dev_priv
->mm
.shrink_list
, &shrink_list
);
4771 spin_unlock(&shrink_list_lock
);
4773 /* Old X drivers will take 0-2 for front, back, depth buffers */
4774 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
4775 dev_priv
->fence_reg_start
= 3;
4777 if (IS_I965G(dev
) || IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
4778 dev_priv
->num_fence_regs
= 16;
4780 dev_priv
->num_fence_regs
= 8;
4782 /* Initialize fence registers to zero */
4783 if (IS_I965G(dev
)) {
4784 for (i
= 0; i
< 16; i
++)
4785 I915_WRITE64(FENCE_REG_965_0
+ (i
* 8), 0);
4787 for (i
= 0; i
< 8; i
++)
4788 I915_WRITE(FENCE_REG_830_0
+ (i
* 4), 0);
4789 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
4790 for (i
= 0; i
< 8; i
++)
4791 I915_WRITE(FENCE_REG_945_8
+ (i
* 4), 0);
4793 i915_gem_detect_bit_6_swizzle(dev
);
4794 init_waitqueue_head(&dev_priv
->pending_flip_queue
);
4798 * Create a physically contiguous memory object for this object
4799 * e.g. for cursor + overlay regs
4801 int i915_gem_init_phys_object(struct drm_device
*dev
,
4804 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4805 struct drm_i915_gem_phys_object
*phys_obj
;
4808 if (dev_priv
->mm
.phys_objs
[id
- 1] || !size
)
4811 phys_obj
= kzalloc(sizeof(struct drm_i915_gem_phys_object
), GFP_KERNEL
);
4817 phys_obj
->handle
= drm_pci_alloc(dev
, size
, 0);
4818 if (!phys_obj
->handle
) {
4823 set_memory_wc((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
4826 dev_priv
->mm
.phys_objs
[id
- 1] = phys_obj
;
4834 void i915_gem_free_phys_object(struct drm_device
*dev
, int id
)
4836 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4837 struct drm_i915_gem_phys_object
*phys_obj
;
4839 if (!dev_priv
->mm
.phys_objs
[id
- 1])
4842 phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
4843 if (phys_obj
->cur_obj
) {
4844 i915_gem_detach_phys_object(dev
, phys_obj
->cur_obj
);
4848 set_memory_wb((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
4850 drm_pci_free(dev
, phys_obj
->handle
);
4852 dev_priv
->mm
.phys_objs
[id
- 1] = NULL
;
4855 void i915_gem_free_all_phys_object(struct drm_device
*dev
)
4859 for (i
= I915_GEM_PHYS_CURSOR_0
; i
<= I915_MAX_PHYS_OBJECT
; i
++)
4860 i915_gem_free_phys_object(dev
, i
);
4863 void i915_gem_detach_phys_object(struct drm_device
*dev
,
4864 struct drm_gem_object
*obj
)
4866 struct drm_i915_gem_object
*obj_priv
;
4871 obj_priv
= to_intel_bo(obj
);
4872 if (!obj_priv
->phys_obj
)
4875 ret
= i915_gem_object_get_pages(obj
, 0);
4879 page_count
= obj
->size
/ PAGE_SIZE
;
4881 for (i
= 0; i
< page_count
; i
++) {
4882 char *dst
= kmap_atomic(obj_priv
->pages
[i
], KM_USER0
);
4883 char *src
= obj_priv
->phys_obj
->handle
->vaddr
+ (i
* PAGE_SIZE
);
4885 memcpy(dst
, src
, PAGE_SIZE
);
4886 kunmap_atomic(dst
, KM_USER0
);
4888 drm_clflush_pages(obj_priv
->pages
, page_count
);
4889 drm_agp_chipset_flush(dev
);
4891 i915_gem_object_put_pages(obj
);
4893 obj_priv
->phys_obj
->cur_obj
= NULL
;
4894 obj_priv
->phys_obj
= NULL
;
4898 i915_gem_attach_phys_object(struct drm_device
*dev
,
4899 struct drm_gem_object
*obj
, int id
)
4901 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4902 struct drm_i915_gem_object
*obj_priv
;
4907 if (id
> I915_MAX_PHYS_OBJECT
)
4910 obj_priv
= to_intel_bo(obj
);
4912 if (obj_priv
->phys_obj
) {
4913 if (obj_priv
->phys_obj
->id
== id
)
4915 i915_gem_detach_phys_object(dev
, obj
);
4919 /* create a new object */
4920 if (!dev_priv
->mm
.phys_objs
[id
- 1]) {
4921 ret
= i915_gem_init_phys_object(dev
, id
,
4924 DRM_ERROR("failed to init phys object %d size: %zu\n", id
, obj
->size
);
4929 /* bind to the object */
4930 obj_priv
->phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
4931 obj_priv
->phys_obj
->cur_obj
= obj
;
4933 ret
= i915_gem_object_get_pages(obj
, 0);
4935 DRM_ERROR("failed to get page list\n");
4939 page_count
= obj
->size
/ PAGE_SIZE
;
4941 for (i
= 0; i
< page_count
; i
++) {
4942 char *src
= kmap_atomic(obj_priv
->pages
[i
], KM_USER0
);
4943 char *dst
= obj_priv
->phys_obj
->handle
->vaddr
+ (i
* PAGE_SIZE
);
4945 memcpy(dst
, src
, PAGE_SIZE
);
4946 kunmap_atomic(src
, KM_USER0
);
4949 i915_gem_object_put_pages(obj
);
4957 i915_gem_phys_pwrite(struct drm_device
*dev
, struct drm_gem_object
*obj
,
4958 struct drm_i915_gem_pwrite
*args
,
4959 struct drm_file
*file_priv
)
4961 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
4964 char __user
*user_data
;
4966 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
4967 obj_addr
= obj_priv
->phys_obj
->handle
->vaddr
+ args
->offset
;
4969 DRM_DEBUG_DRIVER("obj_addr %p, %lld\n", obj_addr
, args
->size
);
4970 ret
= copy_from_user(obj_addr
, user_data
, args
->size
);
4974 drm_agp_chipset_flush(dev
);
4978 void i915_gem_release(struct drm_device
* dev
, struct drm_file
*file_priv
)
4980 struct drm_i915_file_private
*i915_file_priv
= file_priv
->driver_priv
;
4982 /* Clean up our request list when the client is going away, so that
4983 * later retire_requests won't dereference our soon-to-be-gone
4986 mutex_lock(&dev
->struct_mutex
);
4987 while (!list_empty(&i915_file_priv
->mm
.request_list
))
4988 list_del_init(i915_file_priv
->mm
.request_list
.next
);
4989 mutex_unlock(&dev
->struct_mutex
);
4993 i915_gpu_is_active(struct drm_device
*dev
)
4995 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4998 spin_lock(&dev_priv
->mm
.active_list_lock
);
4999 lists_empty
= list_empty(&dev_priv
->mm
.flushing_list
) &&
5000 list_empty(&dev_priv
->render_ring
.active_list
);
5002 lists_empty
&= list_empty(&dev_priv
->bsd_ring
.active_list
);
5003 spin_unlock(&dev_priv
->mm
.active_list_lock
);
5005 return !lists_empty
;
5009 i915_gem_shrink(int nr_to_scan
, gfp_t gfp_mask
)
5011 drm_i915_private_t
*dev_priv
, *next_dev
;
5012 struct drm_i915_gem_object
*obj_priv
, *next_obj
;
5014 int would_deadlock
= 1;
5016 /* "fast-path" to count number of available objects */
5017 if (nr_to_scan
== 0) {
5018 spin_lock(&shrink_list_lock
);
5019 list_for_each_entry(dev_priv
, &shrink_list
, mm
.shrink_list
) {
5020 struct drm_device
*dev
= dev_priv
->dev
;
5022 if (mutex_trylock(&dev
->struct_mutex
)) {
5023 list_for_each_entry(obj_priv
,
5024 &dev_priv
->mm
.inactive_list
,
5027 mutex_unlock(&dev
->struct_mutex
);
5030 spin_unlock(&shrink_list_lock
);
5032 return (cnt
/ 100) * sysctl_vfs_cache_pressure
;
5035 spin_lock(&shrink_list_lock
);
5038 /* first scan for clean buffers */
5039 list_for_each_entry_safe(dev_priv
, next_dev
,
5040 &shrink_list
, mm
.shrink_list
) {
5041 struct drm_device
*dev
= dev_priv
->dev
;
5043 if (! mutex_trylock(&dev
->struct_mutex
))
5046 spin_unlock(&shrink_list_lock
);
5047 i915_gem_retire_requests(dev
, &dev_priv
->render_ring
);
5050 i915_gem_retire_requests(dev
, &dev_priv
->bsd_ring
);
5052 list_for_each_entry_safe(obj_priv
, next_obj
,
5053 &dev_priv
->mm
.inactive_list
,
5055 if (i915_gem_object_is_purgeable(obj_priv
)) {
5056 i915_gem_object_unbind(&obj_priv
->base
);
5057 if (--nr_to_scan
<= 0)
5062 spin_lock(&shrink_list_lock
);
5063 mutex_unlock(&dev
->struct_mutex
);
5067 if (nr_to_scan
<= 0)
5071 /* second pass, evict/count anything still on the inactive list */
5072 list_for_each_entry_safe(dev_priv
, next_dev
,
5073 &shrink_list
, mm
.shrink_list
) {
5074 struct drm_device
*dev
= dev_priv
->dev
;
5076 if (! mutex_trylock(&dev
->struct_mutex
))
5079 spin_unlock(&shrink_list_lock
);
5081 list_for_each_entry_safe(obj_priv
, next_obj
,
5082 &dev_priv
->mm
.inactive_list
,
5084 if (nr_to_scan
> 0) {
5085 i915_gem_object_unbind(&obj_priv
->base
);
5091 spin_lock(&shrink_list_lock
);
5092 mutex_unlock(&dev
->struct_mutex
);
5101 * We are desperate for pages, so as a last resort, wait
5102 * for the GPU to finish and discard whatever we can.
5103 * This has a dramatic impact to reduce the number of
5104 * OOM-killer events whilst running the GPU aggressively.
5106 list_for_each_entry(dev_priv
, &shrink_list
, mm
.shrink_list
) {
5107 struct drm_device
*dev
= dev_priv
->dev
;
5109 if (!mutex_trylock(&dev
->struct_mutex
))
5112 spin_unlock(&shrink_list_lock
);
5114 if (i915_gpu_is_active(dev
)) {
5119 spin_lock(&shrink_list_lock
);
5120 mutex_unlock(&dev
->struct_mutex
);
5127 spin_unlock(&shrink_list_lock
);
5132 return (cnt
/ 100) * sysctl_vfs_cache_pressure
;
5137 static struct shrinker shrinker
= {
5138 .shrink
= i915_gem_shrink
,
5139 .seeks
= DEFAULT_SEEKS
,
5143 i915_gem_shrinker_init(void)
5145 register_shrinker(&shrinker
);
5149 i915_gem_shrinker_exit(void)
5151 unregister_shrinker(&shrinker
);