2 * Copyright © 2008-2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/drm_vma_manager.h>
30 #include <drm/i915_drm.h>
32 #include "i915_vgpu.h"
33 #include "i915_trace.h"
34 #include "intel_drv.h"
35 #include "intel_mocs.h"
36 #include <linux/shmem_fs.h>
37 #include <linux/slab.h>
38 #include <linux/swap.h>
39 #include <linux/pci.h>
40 #include <linux/dma-buf.h>
42 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
);
43 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
);
45 i915_gem_object_retire__write(struct drm_i915_gem_object
*obj
);
47 i915_gem_object_retire__read(struct drm_i915_gem_object
*obj
, int ring
);
49 static bool cpu_cache_is_coherent(struct drm_device
*dev
,
50 enum i915_cache_level level
)
52 return HAS_LLC(dev
) || level
!= I915_CACHE_NONE
;
55 static bool cpu_write_needs_clflush(struct drm_i915_gem_object
*obj
)
57 if (!cpu_cache_is_coherent(obj
->base
.dev
, obj
->cache_level
))
60 return obj
->pin_display
;
64 insert_mappable_node(struct drm_i915_private
*i915
,
65 struct drm_mm_node
*node
, u32 size
)
67 memset(node
, 0, sizeof(*node
));
68 return drm_mm_insert_node_in_range_generic(&i915
->ggtt
.base
.mm
, node
,
70 i915
->ggtt
.mappable_end
,
71 DRM_MM_SEARCH_DEFAULT
,
72 DRM_MM_CREATE_DEFAULT
);
76 remove_mappable_node(struct drm_mm_node
*node
)
78 drm_mm_remove_node(node
);
81 /* some bookkeeping */
82 static void i915_gem_info_add_obj(struct drm_i915_private
*dev_priv
,
85 spin_lock(&dev_priv
->mm
.object_stat_lock
);
86 dev_priv
->mm
.object_count
++;
87 dev_priv
->mm
.object_memory
+= size
;
88 spin_unlock(&dev_priv
->mm
.object_stat_lock
);
91 static void i915_gem_info_remove_obj(struct drm_i915_private
*dev_priv
,
94 spin_lock(&dev_priv
->mm
.object_stat_lock
);
95 dev_priv
->mm
.object_count
--;
96 dev_priv
->mm
.object_memory
-= size
;
97 spin_unlock(&dev_priv
->mm
.object_stat_lock
);
101 i915_gem_wait_for_error(struct i915_gpu_error
*error
)
105 if (!i915_reset_in_progress(error
))
109 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
110 * userspace. If it takes that long something really bad is going on and
111 * we should simply try to bail out and fail as gracefully as possible.
113 ret
= wait_event_interruptible_timeout(error
->reset_queue
,
114 !i915_reset_in_progress(error
),
117 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
119 } else if (ret
< 0) {
126 int i915_mutex_lock_interruptible(struct drm_device
*dev
)
128 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
131 ret
= i915_gem_wait_for_error(&dev_priv
->gpu_error
);
135 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
139 WARN_ON(i915_verify_lists(dev
));
144 i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
145 struct drm_file
*file
)
147 struct drm_i915_private
*dev_priv
= to_i915(dev
);
148 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
149 struct drm_i915_gem_get_aperture
*args
= data
;
150 struct i915_vma
*vma
;
154 mutex_lock(&dev
->struct_mutex
);
155 list_for_each_entry(vma
, &ggtt
->base
.active_list
, vm_link
)
157 pinned
+= vma
->node
.size
;
158 list_for_each_entry(vma
, &ggtt
->base
.inactive_list
, vm_link
)
160 pinned
+= vma
->node
.size
;
161 mutex_unlock(&dev
->struct_mutex
);
163 args
->aper_size
= ggtt
->base
.total
;
164 args
->aper_available_size
= args
->aper_size
- pinned
;
170 i915_gem_object_get_pages_phys(struct drm_i915_gem_object
*obj
)
172 struct address_space
*mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
173 char *vaddr
= obj
->phys_handle
->vaddr
;
175 struct scatterlist
*sg
;
178 if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj
)))
181 for (i
= 0; i
< obj
->base
.size
/ PAGE_SIZE
; i
++) {
185 page
= shmem_read_mapping_page(mapping
, i
);
187 return PTR_ERR(page
);
189 src
= kmap_atomic(page
);
190 memcpy(vaddr
, src
, PAGE_SIZE
);
191 drm_clflush_virt_range(vaddr
, PAGE_SIZE
);
198 i915_gem_chipset_flush(to_i915(obj
->base
.dev
));
200 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
204 if (sg_alloc_table(st
, 1, GFP_KERNEL
)) {
211 sg
->length
= obj
->base
.size
;
213 sg_dma_address(sg
) = obj
->phys_handle
->busaddr
;
214 sg_dma_len(sg
) = obj
->base
.size
;
221 i915_gem_object_put_pages_phys(struct drm_i915_gem_object
*obj
)
225 BUG_ON(obj
->madv
== __I915_MADV_PURGED
);
227 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
229 /* In the event of a disaster, abandon all caches and
232 obj
->base
.read_domains
= obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
235 if (obj
->madv
== I915_MADV_DONTNEED
)
239 struct address_space
*mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
240 char *vaddr
= obj
->phys_handle
->vaddr
;
243 for (i
= 0; i
< obj
->base
.size
/ PAGE_SIZE
; i
++) {
247 page
= shmem_read_mapping_page(mapping
, i
);
251 dst
= kmap_atomic(page
);
252 drm_clflush_virt_range(vaddr
, PAGE_SIZE
);
253 memcpy(dst
, vaddr
, PAGE_SIZE
);
256 set_page_dirty(page
);
257 if (obj
->madv
== I915_MADV_WILLNEED
)
258 mark_page_accessed(page
);
265 sg_free_table(obj
->pages
);
270 i915_gem_object_release_phys(struct drm_i915_gem_object
*obj
)
272 drm_pci_free(obj
->base
.dev
, obj
->phys_handle
);
275 static const struct drm_i915_gem_object_ops i915_gem_phys_ops
= {
276 .get_pages
= i915_gem_object_get_pages_phys
,
277 .put_pages
= i915_gem_object_put_pages_phys
,
278 .release
= i915_gem_object_release_phys
,
282 drop_pages(struct drm_i915_gem_object
*obj
)
284 struct i915_vma
*vma
, *next
;
287 drm_gem_object_reference(&obj
->base
);
288 list_for_each_entry_safe(vma
, next
, &obj
->vma_list
, obj_link
)
289 if (i915_vma_unbind(vma
))
292 ret
= i915_gem_object_put_pages(obj
);
293 drm_gem_object_unreference(&obj
->base
);
299 i915_gem_object_attach_phys(struct drm_i915_gem_object
*obj
,
302 drm_dma_handle_t
*phys
;
305 if (obj
->phys_handle
) {
306 if ((unsigned long)obj
->phys_handle
->vaddr
& (align
-1))
312 if (obj
->madv
!= I915_MADV_WILLNEED
)
315 if (obj
->base
.filp
== NULL
)
318 ret
= drop_pages(obj
);
322 /* create a new object */
323 phys
= drm_pci_alloc(obj
->base
.dev
, obj
->base
.size
, align
);
327 obj
->phys_handle
= phys
;
328 obj
->ops
= &i915_gem_phys_ops
;
330 return i915_gem_object_get_pages(obj
);
334 i915_gem_phys_pwrite(struct drm_i915_gem_object
*obj
,
335 struct drm_i915_gem_pwrite
*args
,
336 struct drm_file
*file_priv
)
338 struct drm_device
*dev
= obj
->base
.dev
;
339 void *vaddr
= obj
->phys_handle
->vaddr
+ args
->offset
;
340 char __user
*user_data
= u64_to_user_ptr(args
->data_ptr
);
343 /* We manually control the domain here and pretend that it
344 * remains coherent i.e. in the GTT domain, like shmem_pwrite.
346 ret
= i915_gem_object_wait_rendering(obj
, false);
350 intel_fb_obj_invalidate(obj
, ORIGIN_CPU
);
351 if (__copy_from_user_inatomic_nocache(vaddr
, user_data
, args
->size
)) {
352 unsigned long unwritten
;
354 /* The physical object once assigned is fixed for the lifetime
355 * of the obj, so we can safely drop the lock and continue
358 mutex_unlock(&dev
->struct_mutex
);
359 unwritten
= copy_from_user(vaddr
, user_data
, args
->size
);
360 mutex_lock(&dev
->struct_mutex
);
367 drm_clflush_virt_range(vaddr
, args
->size
);
368 i915_gem_chipset_flush(to_i915(dev
));
371 intel_fb_obj_flush(obj
, false, ORIGIN_CPU
);
375 void *i915_gem_object_alloc(struct drm_device
*dev
)
377 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
378 return kmem_cache_zalloc(dev_priv
->objects
, GFP_KERNEL
);
381 void i915_gem_object_free(struct drm_i915_gem_object
*obj
)
383 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
384 kmem_cache_free(dev_priv
->objects
, obj
);
388 i915_gem_create(struct drm_file
*file
,
389 struct drm_device
*dev
,
393 struct drm_i915_gem_object
*obj
;
397 size
= roundup(size
, PAGE_SIZE
);
401 /* Allocate the new object */
402 obj
= i915_gem_object_create(dev
, size
);
406 ret
= drm_gem_handle_create(file
, &obj
->base
, &handle
);
407 /* drop reference from allocate - handle holds it now */
408 drm_gem_object_unreference_unlocked(&obj
->base
);
417 i915_gem_dumb_create(struct drm_file
*file
,
418 struct drm_device
*dev
,
419 struct drm_mode_create_dumb
*args
)
421 /* have to work out size/pitch and return them */
422 args
->pitch
= ALIGN(args
->width
* DIV_ROUND_UP(args
->bpp
, 8), 64);
423 args
->size
= args
->pitch
* args
->height
;
424 return i915_gem_create(file
, dev
,
425 args
->size
, &args
->handle
);
429 * Creates a new mm object and returns a handle to it.
430 * @dev: drm device pointer
431 * @data: ioctl data blob
432 * @file: drm file pointer
435 i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
436 struct drm_file
*file
)
438 struct drm_i915_gem_create
*args
= data
;
440 return i915_gem_create(file
, dev
,
441 args
->size
, &args
->handle
);
445 __copy_to_user_swizzled(char __user
*cpu_vaddr
,
446 const char *gpu_vaddr
, int gpu_offset
,
449 int ret
, cpu_offset
= 0;
452 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
453 int this_length
= min(cacheline_end
- gpu_offset
, length
);
454 int swizzled_gpu_offset
= gpu_offset
^ 64;
456 ret
= __copy_to_user(cpu_vaddr
+ cpu_offset
,
457 gpu_vaddr
+ swizzled_gpu_offset
,
462 cpu_offset
+= this_length
;
463 gpu_offset
+= this_length
;
464 length
-= this_length
;
471 __copy_from_user_swizzled(char *gpu_vaddr
, int gpu_offset
,
472 const char __user
*cpu_vaddr
,
475 int ret
, cpu_offset
= 0;
478 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
479 int this_length
= min(cacheline_end
- gpu_offset
, length
);
480 int swizzled_gpu_offset
= gpu_offset
^ 64;
482 ret
= __copy_from_user(gpu_vaddr
+ swizzled_gpu_offset
,
483 cpu_vaddr
+ cpu_offset
,
488 cpu_offset
+= this_length
;
489 gpu_offset
+= this_length
;
490 length
-= this_length
;
497 * Pins the specified object's pages and synchronizes the object with
498 * GPU accesses. Sets needs_clflush to non-zero if the caller should
499 * flush the object from the CPU cache.
501 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object
*obj
,
508 if (WARN_ON((obj
->ops
->flags
& I915_GEM_OBJECT_HAS_STRUCT_PAGE
) == 0))
511 if (!(obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
)) {
512 /* If we're not in the cpu read domain, set ourself into the gtt
513 * read domain and manually flush cachelines (if required). This
514 * optimizes for the case when the gpu will dirty the data
515 * anyway again before the next pread happens. */
516 *needs_clflush
= !cpu_cache_is_coherent(obj
->base
.dev
,
518 ret
= i915_gem_object_wait_rendering(obj
, true);
523 ret
= i915_gem_object_get_pages(obj
);
527 i915_gem_object_pin_pages(obj
);
532 /* Per-page copy function for the shmem pread fastpath.
533 * Flushes invalid cachelines before reading the target if
534 * needs_clflush is set. */
536 shmem_pread_fast(struct page
*page
, int shmem_page_offset
, int page_length
,
537 char __user
*user_data
,
538 bool page_do_bit17_swizzling
, bool needs_clflush
)
543 if (unlikely(page_do_bit17_swizzling
))
546 vaddr
= kmap_atomic(page
);
548 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
550 ret
= __copy_to_user_inatomic(user_data
,
551 vaddr
+ shmem_page_offset
,
553 kunmap_atomic(vaddr
);
555 return ret
? -EFAULT
: 0;
559 shmem_clflush_swizzled_range(char *addr
, unsigned long length
,
562 if (unlikely(swizzled
)) {
563 unsigned long start
= (unsigned long) addr
;
564 unsigned long end
= (unsigned long) addr
+ length
;
566 /* For swizzling simply ensure that we always flush both
567 * channels. Lame, but simple and it works. Swizzled
568 * pwrite/pread is far from a hotpath - current userspace
569 * doesn't use it at all. */
570 start
= round_down(start
, 128);
571 end
= round_up(end
, 128);
573 drm_clflush_virt_range((void *)start
, end
- start
);
575 drm_clflush_virt_range(addr
, length
);
580 /* Only difference to the fast-path function is that this can handle bit17
581 * and uses non-atomic copy and kmap functions. */
583 shmem_pread_slow(struct page
*page
, int shmem_page_offset
, int page_length
,
584 char __user
*user_data
,
585 bool page_do_bit17_swizzling
, bool needs_clflush
)
592 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
594 page_do_bit17_swizzling
);
596 if (page_do_bit17_swizzling
)
597 ret
= __copy_to_user_swizzled(user_data
,
598 vaddr
, shmem_page_offset
,
601 ret
= __copy_to_user(user_data
,
602 vaddr
+ shmem_page_offset
,
606 return ret
? - EFAULT
: 0;
610 i915_gem_shmem_pread(struct drm_device
*dev
,
611 struct drm_i915_gem_object
*obj
,
612 struct drm_i915_gem_pread
*args
,
613 struct drm_file
*file
)
615 char __user
*user_data
;
618 int shmem_page_offset
, page_length
, ret
= 0;
619 int obj_do_bit17_swizzling
, page_do_bit17_swizzling
;
621 int needs_clflush
= 0;
622 struct sg_page_iter sg_iter
;
624 user_data
= u64_to_user_ptr(args
->data_ptr
);
627 obj_do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
629 ret
= i915_gem_obj_prepare_shmem_read(obj
, &needs_clflush
);
633 offset
= args
->offset
;
635 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
,
636 offset
>> PAGE_SHIFT
) {
637 struct page
*page
= sg_page_iter_page(&sg_iter
);
642 /* Operation in this page
644 * shmem_page_offset = offset within page in shmem file
645 * page_length = bytes to copy for this page
647 shmem_page_offset
= offset_in_page(offset
);
648 page_length
= remain
;
649 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
650 page_length
= PAGE_SIZE
- shmem_page_offset
;
652 page_do_bit17_swizzling
= obj_do_bit17_swizzling
&&
653 (page_to_phys(page
) & (1 << 17)) != 0;
655 ret
= shmem_pread_fast(page
, shmem_page_offset
, page_length
,
656 user_data
, page_do_bit17_swizzling
,
661 mutex_unlock(&dev
->struct_mutex
);
663 if (likely(!i915
.prefault_disable
) && !prefaulted
) {
664 ret
= fault_in_multipages_writeable(user_data
, remain
);
665 /* Userspace is tricking us, but we've already clobbered
666 * its pages with the prefault and promised to write the
667 * data up to the first fault. Hence ignore any errors
668 * and just continue. */
673 ret
= shmem_pread_slow(page
, shmem_page_offset
, page_length
,
674 user_data
, page_do_bit17_swizzling
,
677 mutex_lock(&dev
->struct_mutex
);
683 remain
-= page_length
;
684 user_data
+= page_length
;
685 offset
+= page_length
;
689 i915_gem_object_unpin_pages(obj
);
695 * Reads data from the object referenced by handle.
696 * @dev: drm device pointer
697 * @data: ioctl data blob
698 * @file: drm file pointer
700 * On error, the contents of *data are undefined.
703 i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
704 struct drm_file
*file
)
706 struct drm_i915_gem_pread
*args
= data
;
707 struct drm_i915_gem_object
*obj
;
713 if (!access_ok(VERIFY_WRITE
,
714 u64_to_user_ptr(args
->data_ptr
),
718 ret
= i915_mutex_lock_interruptible(dev
);
722 obj
= to_intel_bo(drm_gem_object_lookup(file
, args
->handle
));
723 if (&obj
->base
== NULL
) {
728 /* Bounds check source. */
729 if (args
->offset
> obj
->base
.size
||
730 args
->size
> obj
->base
.size
- args
->offset
) {
735 /* prime objects have no backing filp to GEM pread/pwrite
738 if (!obj
->base
.filp
) {
743 trace_i915_gem_object_pread(obj
, args
->offset
, args
->size
);
745 ret
= i915_gem_shmem_pread(dev
, obj
, args
, file
);
748 drm_gem_object_unreference(&obj
->base
);
750 mutex_unlock(&dev
->struct_mutex
);
754 /* This is the fast write path which cannot handle
755 * page faults in the source data
759 fast_user_write(struct io_mapping
*mapping
,
760 loff_t page_base
, int page_offset
,
761 char __user
*user_data
,
764 void __iomem
*vaddr_atomic
;
766 unsigned long unwritten
;
768 vaddr_atomic
= io_mapping_map_atomic_wc(mapping
, page_base
);
769 /* We can use the cpu mem copy function because this is X86. */
770 vaddr
= (void __force
*)vaddr_atomic
+ page_offset
;
771 unwritten
= __copy_from_user_inatomic_nocache(vaddr
,
773 io_mapping_unmap_atomic(vaddr_atomic
);
778 * This is the fast pwrite path, where we copy the data directly from the
779 * user into the GTT, uncached.
780 * @dev: drm device pointer
781 * @obj: i915 gem object
782 * @args: pwrite arguments structure
783 * @file: drm file pointer
786 i915_gem_gtt_pwrite_fast(struct drm_i915_private
*i915
,
787 struct drm_i915_gem_object
*obj
,
788 struct drm_i915_gem_pwrite
*args
,
789 struct drm_file
*file
)
791 struct i915_ggtt
*ggtt
= &i915
->ggtt
;
792 struct drm_mm_node node
;
793 uint64_t remain
, offset
;
794 char __user
*user_data
;
797 ret
= i915_gem_obj_ggtt_pin(obj
, 0, PIN_MAPPABLE
| PIN_NONBLOCK
);
799 ret
= insert_mappable_node(i915
, &node
, PAGE_SIZE
);
803 ret
= i915_gem_object_get_pages(obj
);
805 remove_mappable_node(&node
);
809 i915_gem_object_pin_pages(obj
);
811 node
.start
= i915_gem_obj_ggtt_offset(obj
);
812 node
.allocated
= false;
815 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
819 ret
= i915_gem_object_put_fence(obj
);
823 intel_fb_obj_invalidate(obj
, ORIGIN_GTT
);
826 user_data
= u64_to_user_ptr(args
->data_ptr
);
827 offset
= args
->offset
;
830 /* Operation in this page
832 * page_base = page offset within aperture
833 * page_offset = offset within page
834 * page_length = bytes to copy for this page
836 u32 page_base
= node
.start
;
837 unsigned page_offset
= offset_in_page(offset
);
838 unsigned page_length
= PAGE_SIZE
- page_offset
;
839 page_length
= remain
< page_length
? remain
: page_length
;
840 if (node
.allocated
) {
841 wmb(); /* flush the write before we modify the GGTT */
842 ggtt
->base
.insert_page(&ggtt
->base
,
843 i915_gem_object_get_dma_address(obj
, offset
>> PAGE_SHIFT
),
844 node
.start
, I915_CACHE_NONE
, 0);
845 wmb(); /* flush modifications to the GGTT (insert_page) */
847 page_base
+= offset
& PAGE_MASK
;
849 /* If we get a fault while copying data, then (presumably) our
850 * source page isn't available. Return the error and we'll
851 * retry in the slow path.
853 if (fast_user_write(ggtt
->mappable
, page_base
,
854 page_offset
, user_data
, page_length
)) {
859 remain
-= page_length
;
860 user_data
+= page_length
;
861 offset
+= page_length
;
865 intel_fb_obj_flush(obj
, false, ORIGIN_GTT
);
867 if (node
.allocated
) {
869 ggtt
->base
.clear_range(&ggtt
->base
,
870 node
.start
, node
.size
,
872 i915_gem_object_unpin_pages(obj
);
873 remove_mappable_node(&node
);
875 i915_gem_object_ggtt_unpin(obj
);
881 /* Per-page copy function for the shmem pwrite fastpath.
882 * Flushes invalid cachelines before writing to the target if
883 * needs_clflush_before is set and flushes out any written cachelines after
884 * writing if needs_clflush is set. */
886 shmem_pwrite_fast(struct page
*page
, int shmem_page_offset
, int page_length
,
887 char __user
*user_data
,
888 bool page_do_bit17_swizzling
,
889 bool needs_clflush_before
,
890 bool needs_clflush_after
)
895 if (unlikely(page_do_bit17_swizzling
))
898 vaddr
= kmap_atomic(page
);
899 if (needs_clflush_before
)
900 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
902 ret
= __copy_from_user_inatomic(vaddr
+ shmem_page_offset
,
903 user_data
, page_length
);
904 if (needs_clflush_after
)
905 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
907 kunmap_atomic(vaddr
);
909 return ret
? -EFAULT
: 0;
912 /* Only difference to the fast-path function is that this can handle bit17
913 * and uses non-atomic copy and kmap functions. */
915 shmem_pwrite_slow(struct page
*page
, int shmem_page_offset
, int page_length
,
916 char __user
*user_data
,
917 bool page_do_bit17_swizzling
,
918 bool needs_clflush_before
,
919 bool needs_clflush_after
)
925 if (unlikely(needs_clflush_before
|| page_do_bit17_swizzling
))
926 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
928 page_do_bit17_swizzling
);
929 if (page_do_bit17_swizzling
)
930 ret
= __copy_from_user_swizzled(vaddr
, shmem_page_offset
,
934 ret
= __copy_from_user(vaddr
+ shmem_page_offset
,
937 if (needs_clflush_after
)
938 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
940 page_do_bit17_swizzling
);
943 return ret
? -EFAULT
: 0;
947 i915_gem_shmem_pwrite(struct drm_device
*dev
,
948 struct drm_i915_gem_object
*obj
,
949 struct drm_i915_gem_pwrite
*args
,
950 struct drm_file
*file
)
954 char __user
*user_data
;
955 int shmem_page_offset
, page_length
, ret
= 0;
956 int obj_do_bit17_swizzling
, page_do_bit17_swizzling
;
957 int hit_slowpath
= 0;
958 int needs_clflush_after
= 0;
959 int needs_clflush_before
= 0;
960 struct sg_page_iter sg_iter
;
962 user_data
= u64_to_user_ptr(args
->data_ptr
);
965 obj_do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
967 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
968 /* If we're not in the cpu write domain, set ourself into the gtt
969 * write domain and manually flush cachelines (if required). This
970 * optimizes for the case when the gpu will use the data
971 * right away and we therefore have to clflush anyway. */
972 needs_clflush_after
= cpu_write_needs_clflush(obj
);
973 ret
= i915_gem_object_wait_rendering(obj
, false);
977 /* Same trick applies to invalidate partially written cachelines read
979 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) == 0)
980 needs_clflush_before
=
981 !cpu_cache_is_coherent(dev
, obj
->cache_level
);
983 ret
= i915_gem_object_get_pages(obj
);
987 intel_fb_obj_invalidate(obj
, ORIGIN_CPU
);
989 i915_gem_object_pin_pages(obj
);
991 offset
= args
->offset
;
994 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
,
995 offset
>> PAGE_SHIFT
) {
996 struct page
*page
= sg_page_iter_page(&sg_iter
);
997 int partial_cacheline_write
;
1002 /* Operation in this page
1004 * shmem_page_offset = offset within page in shmem file
1005 * page_length = bytes to copy for this page
1007 shmem_page_offset
= offset_in_page(offset
);
1009 page_length
= remain
;
1010 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
1011 page_length
= PAGE_SIZE
- shmem_page_offset
;
1013 /* If we don't overwrite a cacheline completely we need to be
1014 * careful to have up-to-date data by first clflushing. Don't
1015 * overcomplicate things and flush the entire patch. */
1016 partial_cacheline_write
= needs_clflush_before
&&
1017 ((shmem_page_offset
| page_length
)
1018 & (boot_cpu_data
.x86_clflush_size
- 1));
1020 page_do_bit17_swizzling
= obj_do_bit17_swizzling
&&
1021 (page_to_phys(page
) & (1 << 17)) != 0;
1023 ret
= shmem_pwrite_fast(page
, shmem_page_offset
, page_length
,
1024 user_data
, page_do_bit17_swizzling
,
1025 partial_cacheline_write
,
1026 needs_clflush_after
);
1031 mutex_unlock(&dev
->struct_mutex
);
1032 ret
= shmem_pwrite_slow(page
, shmem_page_offset
, page_length
,
1033 user_data
, page_do_bit17_swizzling
,
1034 partial_cacheline_write
,
1035 needs_clflush_after
);
1037 mutex_lock(&dev
->struct_mutex
);
1043 remain
-= page_length
;
1044 user_data
+= page_length
;
1045 offset
+= page_length
;
1049 i915_gem_object_unpin_pages(obj
);
1053 * Fixup: Flush cpu caches in case we didn't flush the dirty
1054 * cachelines in-line while writing and the object moved
1055 * out of the cpu write domain while we've dropped the lock.
1057 if (!needs_clflush_after
&&
1058 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
1059 if (i915_gem_clflush_object(obj
, obj
->pin_display
))
1060 needs_clflush_after
= true;
1064 if (needs_clflush_after
)
1065 i915_gem_chipset_flush(to_i915(dev
));
1067 obj
->cache_dirty
= true;
1069 intel_fb_obj_flush(obj
, false, ORIGIN_CPU
);
1074 * Writes data to the object referenced by handle.
1076 * @data: ioctl data blob
1079 * On error, the contents of the buffer that were to be modified are undefined.
1082 i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
1083 struct drm_file
*file
)
1085 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1086 struct drm_i915_gem_pwrite
*args
= data
;
1087 struct drm_i915_gem_object
*obj
;
1090 if (args
->size
== 0)
1093 if (!access_ok(VERIFY_READ
,
1094 u64_to_user_ptr(args
->data_ptr
),
1098 if (likely(!i915
.prefault_disable
)) {
1099 ret
= fault_in_multipages_readable(u64_to_user_ptr(args
->data_ptr
),
1105 intel_runtime_pm_get(dev_priv
);
1107 ret
= i915_mutex_lock_interruptible(dev
);
1111 obj
= to_intel_bo(drm_gem_object_lookup(file
, args
->handle
));
1112 if (&obj
->base
== NULL
) {
1117 /* Bounds check destination. */
1118 if (args
->offset
> obj
->base
.size
||
1119 args
->size
> obj
->base
.size
- args
->offset
) {
1124 /* prime objects have no backing filp to GEM pread/pwrite
1127 if (!obj
->base
.filp
) {
1132 trace_i915_gem_object_pwrite(obj
, args
->offset
, args
->size
);
1135 /* We can only do the GTT pwrite on untiled buffers, as otherwise
1136 * it would end up going through the fenced access, and we'll get
1137 * different detiling behavior between reading and writing.
1138 * pread/pwrite currently are reading and writing from the CPU
1139 * perspective, requiring manual detiling by the client.
1141 if (obj
->tiling_mode
== I915_TILING_NONE
&&
1142 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
&&
1143 cpu_write_needs_clflush(obj
)) {
1144 ret
= i915_gem_gtt_pwrite_fast(dev_priv
, obj
, args
, file
);
1145 /* Note that the gtt paths might fail with non-page-backed user
1146 * pointers (e.g. gtt mappings when moving data between
1147 * textures). Fallback to the shmem path in that case. */
1150 if (ret
== -EFAULT
|| ret
== -ENOSPC
) {
1151 if (obj
->phys_handle
)
1152 ret
= i915_gem_phys_pwrite(obj
, args
, file
);
1154 ret
= i915_gem_shmem_pwrite(dev
, obj
, args
, file
);
1158 drm_gem_object_unreference(&obj
->base
);
1160 mutex_unlock(&dev
->struct_mutex
);
1162 intel_runtime_pm_put(dev_priv
);
1168 i915_gem_check_wedge(unsigned reset_counter
, bool interruptible
)
1170 if (__i915_terminally_wedged(reset_counter
))
1173 if (__i915_reset_in_progress(reset_counter
)) {
1174 /* Non-interruptible callers can't handle -EAGAIN, hence return
1175 * -EIO unconditionally for these. */
1185 static void fake_irq(unsigned long data
)
1187 wake_up_process((struct task_struct
*)data
);
1190 static bool missed_irq(struct drm_i915_private
*dev_priv
,
1191 struct intel_engine_cs
*engine
)
1193 return test_bit(engine
->id
, &dev_priv
->gpu_error
.missed_irq_rings
);
1196 static unsigned long local_clock_us(unsigned *cpu
)
1200 /* Cheaply and approximately convert from nanoseconds to microseconds.
1201 * The result and subsequent calculations are also defined in the same
1202 * approximate microseconds units. The principal source of timing
1203 * error here is from the simple truncation.
1205 * Note that local_clock() is only defined wrt to the current CPU;
1206 * the comparisons are no longer valid if we switch CPUs. Instead of
1207 * blocking preemption for the entire busywait, we can detect the CPU
1208 * switch and use that as indicator of system load and a reason to
1209 * stop busywaiting, see busywait_stop().
1212 t
= local_clock() >> 10;
1218 static bool busywait_stop(unsigned long timeout
, unsigned cpu
)
1222 if (time_after(local_clock_us(&this_cpu
), timeout
))
1225 return this_cpu
!= cpu
;
1228 static int __i915_spin_request(struct drm_i915_gem_request
*req
, int state
)
1230 unsigned long timeout
;
1233 /* When waiting for high frequency requests, e.g. during synchronous
1234 * rendering split between the CPU and GPU, the finite amount of time
1235 * required to set up the irq and wait upon it limits the response
1236 * rate. By busywaiting on the request completion for a short while we
1237 * can service the high frequency waits as quick as possible. However,
1238 * if it is a slow request, we want to sleep as quickly as possible.
1239 * The tradeoff between waiting and sleeping is roughly the time it
1240 * takes to sleep on a request, on the order of a microsecond.
1243 if (req
->engine
->irq_refcount
)
1246 /* Only spin if we know the GPU is processing this request */
1247 if (!i915_gem_request_started(req
, true))
1250 timeout
= local_clock_us(&cpu
) + 5;
1251 while (!need_resched()) {
1252 if (i915_gem_request_completed(req
, true))
1255 if (signal_pending_state(state
, current
))
1258 if (busywait_stop(timeout
, cpu
))
1261 cpu_relax_lowlatency();
1264 if (i915_gem_request_completed(req
, false))
1271 * __i915_wait_request - wait until execution of request has finished
1273 * @interruptible: do an interruptible wait (normally yes)
1274 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
1277 * Note: It is of utmost importance that the passed in seqno and reset_counter
1278 * values have been read by the caller in an smp safe manner. Where read-side
1279 * locks are involved, it is sufficient to read the reset_counter before
1280 * unlocking the lock that protects the seqno. For lockless tricks, the
1281 * reset_counter _must_ be read before, and an appropriate smp_rmb must be
1284 * Returns 0 if the request was found within the alloted time. Else returns the
1285 * errno with remaining time filled in timeout argument.
1287 int __i915_wait_request(struct drm_i915_gem_request
*req
,
1290 struct intel_rps_client
*rps
)
1292 struct intel_engine_cs
*engine
= i915_gem_request_get_engine(req
);
1293 struct drm_i915_private
*dev_priv
= req
->i915
;
1294 const bool irq_test_in_progress
=
1295 ACCESS_ONCE(dev_priv
->gpu_error
.test_irq_rings
) & intel_engine_flag(engine
);
1296 int state
= interruptible
? TASK_INTERRUPTIBLE
: TASK_UNINTERRUPTIBLE
;
1298 unsigned long timeout_expire
;
1299 s64 before
= 0; /* Only to silence a compiler warning. */
1302 WARN(!intel_irqs_enabled(dev_priv
), "IRQs disabled");
1304 if (list_empty(&req
->list
))
1307 if (i915_gem_request_completed(req
, true))
1312 if (WARN_ON(*timeout
< 0))
1318 timeout_expire
= jiffies
+ nsecs_to_jiffies_timeout(*timeout
);
1321 * Record current time in case interrupted by signal, or wedged.
1323 before
= ktime_get_raw_ns();
1326 if (INTEL_INFO(dev_priv
)->gen
>= 6)
1327 gen6_rps_boost(dev_priv
, rps
, req
->emitted_jiffies
);
1329 trace_i915_gem_request_wait_begin(req
);
1331 /* Optimistic spin for the next jiffie before touching IRQs */
1332 ret
= __i915_spin_request(req
, state
);
1336 if (!irq_test_in_progress
&& WARN_ON(!engine
->irq_get(engine
))) {
1342 struct timer_list timer
;
1344 prepare_to_wait(&engine
->irq_queue
, &wait
, state
);
1346 /* We need to check whether any gpu reset happened in between
1347 * the request being submitted and now. If a reset has occurred,
1348 * the request is effectively complete (we either are in the
1349 * process of or have discarded the rendering and completely
1350 * reset the GPU. The results of the request are lost and we
1351 * are free to continue on with the original operation.
1353 if (req
->reset_counter
!= i915_reset_counter(&dev_priv
->gpu_error
)) {
1358 if (i915_gem_request_completed(req
, false)) {
1363 if (signal_pending_state(state
, current
)) {
1368 if (timeout
&& time_after_eq(jiffies
, timeout_expire
)) {
1373 timer
.function
= NULL
;
1374 if (timeout
|| missed_irq(dev_priv
, engine
)) {
1375 unsigned long expire
;
1377 setup_timer_on_stack(&timer
, fake_irq
, (unsigned long)current
);
1378 expire
= missed_irq(dev_priv
, engine
) ? jiffies
+ 1 : timeout_expire
;
1379 mod_timer(&timer
, expire
);
1384 if (timer
.function
) {
1385 del_singleshot_timer_sync(&timer
);
1386 destroy_timer_on_stack(&timer
);
1389 if (!irq_test_in_progress
)
1390 engine
->irq_put(engine
);
1392 finish_wait(&engine
->irq_queue
, &wait
);
1395 trace_i915_gem_request_wait_end(req
);
1398 s64 tres
= *timeout
- (ktime_get_raw_ns() - before
);
1400 *timeout
= tres
< 0 ? 0 : tres
;
1403 * Apparently ktime isn't accurate enough and occasionally has a
1404 * bit of mismatch in the jiffies<->nsecs<->ktime loop. So patch
1405 * things up to make the test happy. We allow up to 1 jiffy.
1407 * This is a regrssion from the timespec->ktime conversion.
1409 if (ret
== -ETIME
&& *timeout
< jiffies_to_usecs(1)*1000)
1416 int i915_gem_request_add_to_client(struct drm_i915_gem_request
*req
,
1417 struct drm_file
*file
)
1419 struct drm_i915_file_private
*file_priv
;
1421 WARN_ON(!req
|| !file
|| req
->file_priv
);
1429 file_priv
= file
->driver_priv
;
1431 spin_lock(&file_priv
->mm
.lock
);
1432 req
->file_priv
= file_priv
;
1433 list_add_tail(&req
->client_list
, &file_priv
->mm
.request_list
);
1434 spin_unlock(&file_priv
->mm
.lock
);
1436 req
->pid
= get_pid(task_pid(current
));
1442 i915_gem_request_remove_from_client(struct drm_i915_gem_request
*request
)
1444 struct drm_i915_file_private
*file_priv
= request
->file_priv
;
1449 spin_lock(&file_priv
->mm
.lock
);
1450 list_del(&request
->client_list
);
1451 request
->file_priv
= NULL
;
1452 spin_unlock(&file_priv
->mm
.lock
);
1454 put_pid(request
->pid
);
1455 request
->pid
= NULL
;
1458 static void i915_gem_request_retire(struct drm_i915_gem_request
*request
)
1460 trace_i915_gem_request_retire(request
);
1462 /* We know the GPU must have read the request to have
1463 * sent us the seqno + interrupt, so use the position
1464 * of tail of the request to update the last known position
1467 * Note this requires that we are always called in request
1470 request
->ringbuf
->last_retired_head
= request
->postfix
;
1472 list_del_init(&request
->list
);
1473 i915_gem_request_remove_from_client(request
);
1475 if (request
->previous_context
) {
1476 if (i915
.enable_execlists
)
1477 intel_lr_context_unpin(request
->previous_context
,
1481 i915_gem_context_unreference(request
->ctx
);
1482 i915_gem_request_unreference(request
);
1486 __i915_gem_request_retire__upto(struct drm_i915_gem_request
*req
)
1488 struct intel_engine_cs
*engine
= req
->engine
;
1489 struct drm_i915_gem_request
*tmp
;
1491 lockdep_assert_held(&engine
->i915
->dev
->struct_mutex
);
1493 if (list_empty(&req
->list
))
1497 tmp
= list_first_entry(&engine
->request_list
,
1498 typeof(*tmp
), list
);
1500 i915_gem_request_retire(tmp
);
1501 } while (tmp
!= req
);
1503 WARN_ON(i915_verify_lists(engine
->dev
));
1507 * Waits for a request to be signaled, and cleans up the
1508 * request and object lists appropriately for that event.
1509 * @req: request to wait on
1512 i915_wait_request(struct drm_i915_gem_request
*req
)
1514 struct drm_i915_private
*dev_priv
= req
->i915
;
1518 interruptible
= dev_priv
->mm
.interruptible
;
1520 BUG_ON(!mutex_is_locked(&dev_priv
->dev
->struct_mutex
));
1522 ret
= __i915_wait_request(req
, interruptible
, NULL
, NULL
);
1526 /* If the GPU hung, we want to keep the requests to find the guilty. */
1527 if (req
->reset_counter
== i915_reset_counter(&dev_priv
->gpu_error
))
1528 __i915_gem_request_retire__upto(req
);
1534 * Ensures that all rendering to the object has completed and the object is
1535 * safe to unbind from the GTT or access from the CPU.
1536 * @obj: i915 gem object
1537 * @readonly: waiting for read access or write
1540 i915_gem_object_wait_rendering(struct drm_i915_gem_object
*obj
,
1549 if (obj
->last_write_req
!= NULL
) {
1550 ret
= i915_wait_request(obj
->last_write_req
);
1554 i
= obj
->last_write_req
->engine
->id
;
1555 if (obj
->last_read_req
[i
] == obj
->last_write_req
)
1556 i915_gem_object_retire__read(obj
, i
);
1558 i915_gem_object_retire__write(obj
);
1561 for (i
= 0; i
< I915_NUM_ENGINES
; i
++) {
1562 if (obj
->last_read_req
[i
] == NULL
)
1565 ret
= i915_wait_request(obj
->last_read_req
[i
]);
1569 i915_gem_object_retire__read(obj
, i
);
1571 GEM_BUG_ON(obj
->active
);
1578 i915_gem_object_retire_request(struct drm_i915_gem_object
*obj
,
1579 struct drm_i915_gem_request
*req
)
1581 int ring
= req
->engine
->id
;
1583 if (obj
->last_read_req
[ring
] == req
)
1584 i915_gem_object_retire__read(obj
, ring
);
1585 else if (obj
->last_write_req
== req
)
1586 i915_gem_object_retire__write(obj
);
1588 if (req
->reset_counter
== i915_reset_counter(&req
->i915
->gpu_error
))
1589 __i915_gem_request_retire__upto(req
);
1592 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1593 * as the object state may change during this call.
1595 static __must_check
int
1596 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object
*obj
,
1597 struct intel_rps_client
*rps
,
1600 struct drm_device
*dev
= obj
->base
.dev
;
1601 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1602 struct drm_i915_gem_request
*requests
[I915_NUM_ENGINES
];
1605 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
1606 BUG_ON(!dev_priv
->mm
.interruptible
);
1612 struct drm_i915_gem_request
*req
;
1614 req
= obj
->last_write_req
;
1618 requests
[n
++] = i915_gem_request_reference(req
);
1620 for (i
= 0; i
< I915_NUM_ENGINES
; i
++) {
1621 struct drm_i915_gem_request
*req
;
1623 req
= obj
->last_read_req
[i
];
1627 requests
[n
++] = i915_gem_request_reference(req
);
1631 mutex_unlock(&dev
->struct_mutex
);
1633 for (i
= 0; ret
== 0 && i
< n
; i
++)
1634 ret
= __i915_wait_request(requests
[i
], true, NULL
, rps
);
1635 mutex_lock(&dev
->struct_mutex
);
1637 for (i
= 0; i
< n
; i
++) {
1639 i915_gem_object_retire_request(obj
, requests
[i
]);
1640 i915_gem_request_unreference(requests
[i
]);
1646 static struct intel_rps_client
*to_rps_client(struct drm_file
*file
)
1648 struct drm_i915_file_private
*fpriv
= file
->driver_priv
;
1653 * Called when user space prepares to use an object with the CPU, either
1654 * through the mmap ioctl's mapping or a GTT mapping.
1656 * @data: ioctl data blob
1660 i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
1661 struct drm_file
*file
)
1663 struct drm_i915_gem_set_domain
*args
= data
;
1664 struct drm_i915_gem_object
*obj
;
1665 uint32_t read_domains
= args
->read_domains
;
1666 uint32_t write_domain
= args
->write_domain
;
1669 /* Only handle setting domains to types used by the CPU. */
1670 if (write_domain
& I915_GEM_GPU_DOMAINS
)
1673 if (read_domains
& I915_GEM_GPU_DOMAINS
)
1676 /* Having something in the write domain implies it's in the read
1677 * domain, and only that read domain. Enforce that in the request.
1679 if (write_domain
!= 0 && read_domains
!= write_domain
)
1682 ret
= i915_mutex_lock_interruptible(dev
);
1686 obj
= to_intel_bo(drm_gem_object_lookup(file
, args
->handle
));
1687 if (&obj
->base
== NULL
) {
1692 /* Try to flush the object off the GPU without holding the lock.
1693 * We will repeat the flush holding the lock in the normal manner
1694 * to catch cases where we are gazumped.
1696 ret
= i915_gem_object_wait_rendering__nonblocking(obj
,
1697 to_rps_client(file
),
1702 if (read_domains
& I915_GEM_DOMAIN_GTT
)
1703 ret
= i915_gem_object_set_to_gtt_domain(obj
, write_domain
!= 0);
1705 ret
= i915_gem_object_set_to_cpu_domain(obj
, write_domain
!= 0);
1707 if (write_domain
!= 0)
1708 intel_fb_obj_invalidate(obj
,
1709 write_domain
== I915_GEM_DOMAIN_GTT
?
1710 ORIGIN_GTT
: ORIGIN_CPU
);
1713 drm_gem_object_unreference(&obj
->base
);
1715 mutex_unlock(&dev
->struct_mutex
);
1720 * Called when user space has done writes to this buffer
1722 * @data: ioctl data blob
1726 i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1727 struct drm_file
*file
)
1729 struct drm_i915_gem_sw_finish
*args
= data
;
1730 struct drm_i915_gem_object
*obj
;
1733 ret
= i915_mutex_lock_interruptible(dev
);
1737 obj
= to_intel_bo(drm_gem_object_lookup(file
, args
->handle
));
1738 if (&obj
->base
== NULL
) {
1743 /* Pinned buffers may be scanout, so flush the cache */
1744 if (obj
->pin_display
)
1745 i915_gem_object_flush_cpu_write_domain(obj
);
1747 drm_gem_object_unreference(&obj
->base
);
1749 mutex_unlock(&dev
->struct_mutex
);
1754 * i915_gem_mmap_ioctl - Maps the contents of an object, returning the address
1757 * @data: ioctl data blob
1760 * While the mapping holds a reference on the contents of the object, it doesn't
1761 * imply a ref on the object itself.
1765 * DRM driver writers who look a this function as an example for how to do GEM
1766 * mmap support, please don't implement mmap support like here. The modern way
1767 * to implement DRM mmap support is with an mmap offset ioctl (like
1768 * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly.
1769 * That way debug tooling like valgrind will understand what's going on, hiding
1770 * the mmap call in a driver private ioctl will break that. The i915 driver only
1771 * does cpu mmaps this way because we didn't know better.
1774 i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1775 struct drm_file
*file
)
1777 struct drm_i915_gem_mmap
*args
= data
;
1778 struct drm_gem_object
*obj
;
1781 if (args
->flags
& ~(I915_MMAP_WC
))
1784 if (args
->flags
& I915_MMAP_WC
&& !boot_cpu_has(X86_FEATURE_PAT
))
1787 obj
= drm_gem_object_lookup(file
, args
->handle
);
1791 /* prime objects have no backing filp to GEM mmap
1795 drm_gem_object_unreference_unlocked(obj
);
1799 addr
= vm_mmap(obj
->filp
, 0, args
->size
,
1800 PROT_READ
| PROT_WRITE
, MAP_SHARED
,
1802 if (args
->flags
& I915_MMAP_WC
) {
1803 struct mm_struct
*mm
= current
->mm
;
1804 struct vm_area_struct
*vma
;
1806 if (down_write_killable(&mm
->mmap_sem
)) {
1807 drm_gem_object_unreference_unlocked(obj
);
1810 vma
= find_vma(mm
, addr
);
1813 pgprot_writecombine(vm_get_page_prot(vma
->vm_flags
));
1816 up_write(&mm
->mmap_sem
);
1818 drm_gem_object_unreference_unlocked(obj
);
1819 if (IS_ERR((void *)addr
))
1822 args
->addr_ptr
= (uint64_t) addr
;
1828 * i915_gem_fault - fault a page into the GTT
1829 * @vma: VMA in question
1832 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1833 * from userspace. The fault handler takes care of binding the object to
1834 * the GTT (if needed), allocating and programming a fence register (again,
1835 * only if needed based on whether the old reg is still valid or the object
1836 * is tiled) and inserting a new PTE into the faulting process.
1838 * Note that the faulting process may involve evicting existing objects
1839 * from the GTT and/or fence registers to make room. So performance may
1840 * suffer if the GTT working set is large or there are few fence registers
1843 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
)
1845 struct drm_i915_gem_object
*obj
= to_intel_bo(vma
->vm_private_data
);
1846 struct drm_device
*dev
= obj
->base
.dev
;
1847 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1848 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
1849 struct i915_ggtt_view view
= i915_ggtt_view_normal
;
1850 pgoff_t page_offset
;
1853 bool write
= !!(vmf
->flags
& FAULT_FLAG_WRITE
);
1855 intel_runtime_pm_get(dev_priv
);
1857 /* We don't use vmf->pgoff since that has the fake offset */
1858 page_offset
= ((unsigned long)vmf
->virtual_address
- vma
->vm_start
) >>
1861 ret
= i915_mutex_lock_interruptible(dev
);
1865 trace_i915_gem_object_fault(obj
, page_offset
, true, write
);
1867 /* Try to flush the object off the GPU first without holding the lock.
1868 * Upon reacquiring the lock, we will perform our sanity checks and then
1869 * repeat the flush holding the lock in the normal manner to catch cases
1870 * where we are gazumped.
1872 ret
= i915_gem_object_wait_rendering__nonblocking(obj
, NULL
, !write
);
1876 /* Access to snoopable pages through the GTT is incoherent. */
1877 if (obj
->cache_level
!= I915_CACHE_NONE
&& !HAS_LLC(dev
)) {
1882 /* Use a partial view if the object is bigger than the aperture. */
1883 if (obj
->base
.size
>= ggtt
->mappable_end
&&
1884 obj
->tiling_mode
== I915_TILING_NONE
) {
1885 static const unsigned int chunk_size
= 256; // 1 MiB
1887 memset(&view
, 0, sizeof(view
));
1888 view
.type
= I915_GGTT_VIEW_PARTIAL
;
1889 view
.params
.partial
.offset
= rounddown(page_offset
, chunk_size
);
1890 view
.params
.partial
.size
=
1893 (vma
->vm_end
- vma
->vm_start
)/PAGE_SIZE
-
1894 view
.params
.partial
.offset
);
1897 /* Now pin it into the GTT if needed */
1898 ret
= i915_gem_object_ggtt_pin(obj
, &view
, 0, PIN_MAPPABLE
);
1902 ret
= i915_gem_object_set_to_gtt_domain(obj
, write
);
1906 ret
= i915_gem_object_get_fence(obj
);
1910 /* Finally, remap it using the new GTT offset */
1911 pfn
= ggtt
->mappable_base
+
1912 i915_gem_obj_ggtt_offset_view(obj
, &view
);
1915 if (unlikely(view
.type
== I915_GGTT_VIEW_PARTIAL
)) {
1916 /* Overriding existing pages in partial view does not cause
1917 * us any trouble as TLBs are still valid because the fault
1918 * is due to userspace losing part of the mapping or never
1919 * having accessed it before (at this partials' range).
1921 unsigned long base
= vma
->vm_start
+
1922 (view
.params
.partial
.offset
<< PAGE_SHIFT
);
1925 for (i
= 0; i
< view
.params
.partial
.size
; i
++) {
1926 ret
= vm_insert_pfn(vma
, base
+ i
* PAGE_SIZE
, pfn
+ i
);
1931 obj
->fault_mappable
= true;
1933 if (!obj
->fault_mappable
) {
1934 unsigned long size
= min_t(unsigned long,
1935 vma
->vm_end
- vma
->vm_start
,
1939 for (i
= 0; i
< size
>> PAGE_SHIFT
; i
++) {
1940 ret
= vm_insert_pfn(vma
,
1941 (unsigned long)vma
->vm_start
+ i
* PAGE_SIZE
,
1947 obj
->fault_mappable
= true;
1949 ret
= vm_insert_pfn(vma
,
1950 (unsigned long)vmf
->virtual_address
,
1954 i915_gem_object_ggtt_unpin_view(obj
, &view
);
1956 mutex_unlock(&dev
->struct_mutex
);
1961 * We eat errors when the gpu is terminally wedged to avoid
1962 * userspace unduly crashing (gl has no provisions for mmaps to
1963 * fail). But any other -EIO isn't ours (e.g. swap in failure)
1964 * and so needs to be reported.
1966 if (!i915_terminally_wedged(&dev_priv
->gpu_error
)) {
1967 ret
= VM_FAULT_SIGBUS
;
1972 * EAGAIN means the gpu is hung and we'll wait for the error
1973 * handler to reset everything when re-faulting in
1974 * i915_mutex_lock_interruptible.
1981 * EBUSY is ok: this just means that another thread
1982 * already did the job.
1984 ret
= VM_FAULT_NOPAGE
;
1991 ret
= VM_FAULT_SIGBUS
;
1994 WARN_ONCE(ret
, "unhandled error in i915_gem_fault: %i\n", ret
);
1995 ret
= VM_FAULT_SIGBUS
;
1999 intel_runtime_pm_put(dev_priv
);
2004 * i915_gem_release_mmap - remove physical page mappings
2005 * @obj: obj in question
2007 * Preserve the reservation of the mmapping with the DRM core code, but
2008 * relinquish ownership of the pages back to the system.
2010 * It is vital that we remove the page mapping if we have mapped a tiled
2011 * object through the GTT and then lose the fence register due to
2012 * resource pressure. Similarly if the object has been moved out of the
2013 * aperture, than pages mapped into userspace must be revoked. Removing the
2014 * mapping will then trigger a page fault on the next user access, allowing
2015 * fixup by i915_gem_fault().
2018 i915_gem_release_mmap(struct drm_i915_gem_object
*obj
)
2020 /* Serialisation between user GTT access and our code depends upon
2021 * revoking the CPU's PTE whilst the mutex is held. The next user
2022 * pagefault then has to wait until we release the mutex.
2024 lockdep_assert_held(&obj
->base
.dev
->struct_mutex
);
2026 if (!obj
->fault_mappable
)
2029 drm_vma_node_unmap(&obj
->base
.vma_node
,
2030 obj
->base
.dev
->anon_inode
->i_mapping
);
2032 /* Ensure that the CPU's PTE are revoked and there are not outstanding
2033 * memory transactions from userspace before we return. The TLB
2034 * flushing implied above by changing the PTE above *should* be
2035 * sufficient, an extra barrier here just provides us with a bit
2036 * of paranoid documentation about our requirement to serialise
2037 * memory writes before touching registers / GSM.
2041 obj
->fault_mappable
= false;
2045 i915_gem_release_all_mmaps(struct drm_i915_private
*dev_priv
)
2047 struct drm_i915_gem_object
*obj
;
2049 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
)
2050 i915_gem_release_mmap(obj
);
2054 i915_gem_get_gtt_size(struct drm_device
*dev
, uint32_t size
, int tiling_mode
)
2058 if (INTEL_INFO(dev
)->gen
>= 4 ||
2059 tiling_mode
== I915_TILING_NONE
)
2062 /* Previous chips need a power-of-two fence region when tiling */
2064 gtt_size
= 1024*1024;
2066 gtt_size
= 512*1024;
2068 while (gtt_size
< size
)
2075 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
2077 * @size: object size
2078 * @tiling_mode: tiling mode
2079 * @fenced: is fenced alignemned required or not
2081 * Return the required GTT alignment for an object, taking into account
2082 * potential fence register mapping.
2085 i915_gem_get_gtt_alignment(struct drm_device
*dev
, uint32_t size
,
2086 int tiling_mode
, bool fenced
)
2089 * Minimum alignment is 4k (GTT page size), but might be greater
2090 * if a fence register is needed for the object.
2092 if (INTEL_INFO(dev
)->gen
>= 4 || (!fenced
&& IS_G33(dev
)) ||
2093 tiling_mode
== I915_TILING_NONE
)
2097 * Previous chips need to be aligned to the size of the smallest
2098 * fence register that can contain the object.
2100 return i915_gem_get_gtt_size(dev
, size
, tiling_mode
);
2103 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object
*obj
)
2105 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2108 dev_priv
->mm
.shrinker_no_lock_stealing
= true;
2110 ret
= drm_gem_create_mmap_offset(&obj
->base
);
2114 /* Badly fragmented mmap space? The only way we can recover
2115 * space is by destroying unwanted objects. We can't randomly release
2116 * mmap_offsets as userspace expects them to be persistent for the
2117 * lifetime of the objects. The closest we can is to release the
2118 * offsets on purgeable objects by truncating it and marking it purged,
2119 * which prevents userspace from ever using that object again.
2121 i915_gem_shrink(dev_priv
,
2122 obj
->base
.size
>> PAGE_SHIFT
,
2124 I915_SHRINK_UNBOUND
|
2125 I915_SHRINK_PURGEABLE
);
2126 ret
= drm_gem_create_mmap_offset(&obj
->base
);
2130 i915_gem_shrink_all(dev_priv
);
2131 ret
= drm_gem_create_mmap_offset(&obj
->base
);
2133 dev_priv
->mm
.shrinker_no_lock_stealing
= false;
2138 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object
*obj
)
2140 drm_gem_free_mmap_offset(&obj
->base
);
2144 i915_gem_mmap_gtt(struct drm_file
*file
,
2145 struct drm_device
*dev
,
2149 struct drm_i915_gem_object
*obj
;
2152 ret
= i915_mutex_lock_interruptible(dev
);
2156 obj
= to_intel_bo(drm_gem_object_lookup(file
, handle
));
2157 if (&obj
->base
== NULL
) {
2162 if (obj
->madv
!= I915_MADV_WILLNEED
) {
2163 DRM_DEBUG("Attempting to mmap a purgeable buffer\n");
2168 ret
= i915_gem_object_create_mmap_offset(obj
);
2172 *offset
= drm_vma_node_offset_addr(&obj
->base
.vma_node
);
2175 drm_gem_object_unreference(&obj
->base
);
2177 mutex_unlock(&dev
->struct_mutex
);
2182 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
2184 * @data: GTT mapping ioctl data
2185 * @file: GEM object info
2187 * Simply returns the fake offset to userspace so it can mmap it.
2188 * The mmap call will end up in drm_gem_mmap(), which will set things
2189 * up so we can get faults in the handler above.
2191 * The fault handler will take care of binding the object into the GTT
2192 * (since it may have been evicted to make room for something), allocating
2193 * a fence register, and mapping the appropriate aperture address into
2197 i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
2198 struct drm_file
*file
)
2200 struct drm_i915_gem_mmap_gtt
*args
= data
;
2202 return i915_gem_mmap_gtt(file
, dev
, args
->handle
, &args
->offset
);
2205 /* Immediately discard the backing storage */
2207 i915_gem_object_truncate(struct drm_i915_gem_object
*obj
)
2209 i915_gem_object_free_mmap_offset(obj
);
2211 if (obj
->base
.filp
== NULL
)
2214 /* Our goal here is to return as much of the memory as
2215 * is possible back to the system as we are called from OOM.
2216 * To do this we must instruct the shmfs to drop all of its
2217 * backing pages, *now*.
2219 shmem_truncate_range(file_inode(obj
->base
.filp
), 0, (loff_t
)-1);
2220 obj
->madv
= __I915_MADV_PURGED
;
2223 /* Try to discard unwanted pages */
2225 i915_gem_object_invalidate(struct drm_i915_gem_object
*obj
)
2227 struct address_space
*mapping
;
2229 switch (obj
->madv
) {
2230 case I915_MADV_DONTNEED
:
2231 i915_gem_object_truncate(obj
);
2232 case __I915_MADV_PURGED
:
2236 if (obj
->base
.filp
== NULL
)
2239 mapping
= file_inode(obj
->base
.filp
)->i_mapping
,
2240 invalidate_mapping_pages(mapping
, 0, (loff_t
)-1);
2244 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object
*obj
)
2246 struct sgt_iter sgt_iter
;
2250 BUG_ON(obj
->madv
== __I915_MADV_PURGED
);
2252 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
2254 /* In the event of a disaster, abandon all caches and
2255 * hope for the best.
2257 i915_gem_clflush_object(obj
, true);
2258 obj
->base
.read_domains
= obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
2261 i915_gem_gtt_finish_object(obj
);
2263 if (i915_gem_object_needs_bit17_swizzle(obj
))
2264 i915_gem_object_save_bit_17_swizzle(obj
);
2266 if (obj
->madv
== I915_MADV_DONTNEED
)
2269 for_each_sgt_page(page
, sgt_iter
, obj
->pages
) {
2271 set_page_dirty(page
);
2273 if (obj
->madv
== I915_MADV_WILLNEED
)
2274 mark_page_accessed(page
);
2280 sg_free_table(obj
->pages
);
2285 i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
)
2287 const struct drm_i915_gem_object_ops
*ops
= obj
->ops
;
2289 if (obj
->pages
== NULL
)
2292 if (obj
->pages_pin_count
)
2295 BUG_ON(i915_gem_obj_bound_any(obj
));
2297 /* ->put_pages might need to allocate memory for the bit17 swizzle
2298 * array, hence protect them from being reaped by removing them from gtt
2300 list_del(&obj
->global_list
);
2303 if (is_vmalloc_addr(obj
->mapping
))
2304 vunmap(obj
->mapping
);
2306 kunmap(kmap_to_page(obj
->mapping
));
2307 obj
->mapping
= NULL
;
2310 ops
->put_pages(obj
);
2313 i915_gem_object_invalidate(obj
);
2319 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object
*obj
)
2321 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2323 struct address_space
*mapping
;
2324 struct sg_table
*st
;
2325 struct scatterlist
*sg
;
2326 struct sgt_iter sgt_iter
;
2328 unsigned long last_pfn
= 0; /* suppress gcc warning */
2332 /* Assert that the object is not currently in any GPU domain. As it
2333 * wasn't in the GTT, there shouldn't be any way it could have been in
2336 BUG_ON(obj
->base
.read_domains
& I915_GEM_GPU_DOMAINS
);
2337 BUG_ON(obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
);
2339 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
2343 page_count
= obj
->base
.size
/ PAGE_SIZE
;
2344 if (sg_alloc_table(st
, page_count
, GFP_KERNEL
)) {
2349 /* Get the list of pages out of our struct file. They'll be pinned
2350 * at this point until we release them.
2352 * Fail silently without starting the shrinker
2354 mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
2355 gfp
= mapping_gfp_constraint(mapping
, ~(__GFP_IO
| __GFP_RECLAIM
));
2356 gfp
|= __GFP_NORETRY
| __GFP_NOWARN
;
2359 for (i
= 0; i
< page_count
; i
++) {
2360 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
2362 i915_gem_shrink(dev_priv
,
2365 I915_SHRINK_UNBOUND
|
2366 I915_SHRINK_PURGEABLE
);
2367 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
2370 /* We've tried hard to allocate the memory by reaping
2371 * our own buffer, now let the real VM do its job and
2372 * go down in flames if truly OOM.
2374 i915_gem_shrink_all(dev_priv
);
2375 page
= shmem_read_mapping_page(mapping
, i
);
2377 ret
= PTR_ERR(page
);
2381 #ifdef CONFIG_SWIOTLB
2382 if (swiotlb_nr_tbl()) {
2384 sg_set_page(sg
, page
, PAGE_SIZE
, 0);
2389 if (!i
|| page_to_pfn(page
) != last_pfn
+ 1) {
2393 sg_set_page(sg
, page
, PAGE_SIZE
, 0);
2395 sg
->length
+= PAGE_SIZE
;
2397 last_pfn
= page_to_pfn(page
);
2399 /* Check that the i965g/gm workaround works. */
2400 WARN_ON((gfp
& __GFP_DMA32
) && (last_pfn
>= 0x00100000UL
));
2402 #ifdef CONFIG_SWIOTLB
2403 if (!swiotlb_nr_tbl())
2408 ret
= i915_gem_gtt_prepare_object(obj
);
2412 if (i915_gem_object_needs_bit17_swizzle(obj
))
2413 i915_gem_object_do_bit_17_swizzle(obj
);
2415 if (obj
->tiling_mode
!= I915_TILING_NONE
&&
2416 dev_priv
->quirks
& QUIRK_PIN_SWIZZLED_PAGES
)
2417 i915_gem_object_pin_pages(obj
);
2423 for_each_sgt_page(page
, sgt_iter
, st
)
2428 /* shmemfs first checks if there is enough memory to allocate the page
2429 * and reports ENOSPC should there be insufficient, along with the usual
2430 * ENOMEM for a genuine allocation failure.
2432 * We use ENOSPC in our driver to mean that we have run out of aperture
2433 * space and so want to translate the error from shmemfs back to our
2434 * usual understanding of ENOMEM.
2442 /* Ensure that the associated pages are gathered from the backing storage
2443 * and pinned into our object. i915_gem_object_get_pages() may be called
2444 * multiple times before they are released by a single call to
2445 * i915_gem_object_put_pages() - once the pages are no longer referenced
2446 * either as a result of memory pressure (reaping pages under the shrinker)
2447 * or as the object is itself released.
2450 i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
)
2452 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2453 const struct drm_i915_gem_object_ops
*ops
= obj
->ops
;
2459 if (obj
->madv
!= I915_MADV_WILLNEED
) {
2460 DRM_DEBUG("Attempting to obtain a purgeable object\n");
2464 BUG_ON(obj
->pages_pin_count
);
2466 ret
= ops
->get_pages(obj
);
2470 list_add_tail(&obj
->global_list
, &dev_priv
->mm
.unbound_list
);
2472 obj
->get_page
.sg
= obj
->pages
->sgl
;
2473 obj
->get_page
.last
= 0;
2478 /* The 'mapping' part of i915_gem_object_pin_map() below */
2479 static void *i915_gem_object_map(const struct drm_i915_gem_object
*obj
)
2481 unsigned long n_pages
= obj
->base
.size
>> PAGE_SHIFT
;
2482 struct sg_table
*sgt
= obj
->pages
;
2483 struct sgt_iter sgt_iter
;
2485 struct page
*stack_pages
[32];
2486 struct page
**pages
= stack_pages
;
2487 unsigned long i
= 0;
2490 /* A single page can always be kmapped */
2492 return kmap(sg_page(sgt
->sgl
));
2494 if (n_pages
> ARRAY_SIZE(stack_pages
)) {
2495 /* Too big for stack -- allocate temporary array instead */
2496 pages
= drm_malloc_gfp(n_pages
, sizeof(*pages
), GFP_TEMPORARY
);
2501 for_each_sgt_page(page
, sgt_iter
, sgt
)
2504 /* Check that we have the expected number of pages */
2505 GEM_BUG_ON(i
!= n_pages
);
2507 addr
= vmap(pages
, n_pages
, 0, PAGE_KERNEL
);
2509 if (pages
!= stack_pages
)
2510 drm_free_large(pages
);
2515 /* get, pin, and map the pages of the object into kernel space */
2516 void *i915_gem_object_pin_map(struct drm_i915_gem_object
*obj
)
2520 lockdep_assert_held(&obj
->base
.dev
->struct_mutex
);
2522 ret
= i915_gem_object_get_pages(obj
);
2524 return ERR_PTR(ret
);
2526 i915_gem_object_pin_pages(obj
);
2528 if (!obj
->mapping
) {
2529 obj
->mapping
= i915_gem_object_map(obj
);
2530 if (!obj
->mapping
) {
2531 i915_gem_object_unpin_pages(obj
);
2532 return ERR_PTR(-ENOMEM
);
2536 return obj
->mapping
;
2539 void i915_vma_move_to_active(struct i915_vma
*vma
,
2540 struct drm_i915_gem_request
*req
)
2542 struct drm_i915_gem_object
*obj
= vma
->obj
;
2543 struct intel_engine_cs
*engine
;
2545 engine
= i915_gem_request_get_engine(req
);
2547 /* Add a reference if we're newly entering the active list. */
2548 if (obj
->active
== 0)
2549 drm_gem_object_reference(&obj
->base
);
2550 obj
->active
|= intel_engine_flag(engine
);
2552 list_move_tail(&obj
->engine_list
[engine
->id
], &engine
->active_list
);
2553 i915_gem_request_assign(&obj
->last_read_req
[engine
->id
], req
);
2555 list_move_tail(&vma
->vm_link
, &vma
->vm
->active_list
);
2559 i915_gem_object_retire__write(struct drm_i915_gem_object
*obj
)
2561 GEM_BUG_ON(obj
->last_write_req
== NULL
);
2562 GEM_BUG_ON(!(obj
->active
& intel_engine_flag(obj
->last_write_req
->engine
)));
2564 i915_gem_request_assign(&obj
->last_write_req
, NULL
);
2565 intel_fb_obj_flush(obj
, true, ORIGIN_CS
);
2569 i915_gem_object_retire__read(struct drm_i915_gem_object
*obj
, int ring
)
2571 struct i915_vma
*vma
;
2573 GEM_BUG_ON(obj
->last_read_req
[ring
] == NULL
);
2574 GEM_BUG_ON(!(obj
->active
& (1 << ring
)));
2576 list_del_init(&obj
->engine_list
[ring
]);
2577 i915_gem_request_assign(&obj
->last_read_req
[ring
], NULL
);
2579 if (obj
->last_write_req
&& obj
->last_write_req
->engine
->id
== ring
)
2580 i915_gem_object_retire__write(obj
);
2582 obj
->active
&= ~(1 << ring
);
2586 /* Bump our place on the bound list to keep it roughly in LRU order
2587 * so that we don't steal from recently used but inactive objects
2588 * (unless we are forced to ofc!)
2590 list_move_tail(&obj
->global_list
,
2591 &to_i915(obj
->base
.dev
)->mm
.bound_list
);
2593 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
) {
2594 if (!list_empty(&vma
->vm_link
))
2595 list_move_tail(&vma
->vm_link
, &vma
->vm
->inactive_list
);
2598 i915_gem_request_assign(&obj
->last_fenced_req
, NULL
);
2599 drm_gem_object_unreference(&obj
->base
);
2603 i915_gem_init_seqno(struct drm_i915_private
*dev_priv
, u32 seqno
)
2605 struct intel_engine_cs
*engine
;
2608 /* Carefully retire all requests without writing to the rings */
2609 for_each_engine(engine
, dev_priv
) {
2610 ret
= intel_engine_idle(engine
);
2614 i915_gem_retire_requests(dev_priv
);
2616 /* Finally reset hw state */
2617 for_each_engine(engine
, dev_priv
)
2618 intel_ring_init_seqno(engine
, seqno
);
2623 int i915_gem_set_seqno(struct drm_device
*dev
, u32 seqno
)
2625 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2631 /* HWS page needs to be set less than what we
2632 * will inject to ring
2634 ret
= i915_gem_init_seqno(dev_priv
, seqno
- 1);
2638 /* Carefully set the last_seqno value so that wrap
2639 * detection still works
2641 dev_priv
->next_seqno
= seqno
;
2642 dev_priv
->last_seqno
= seqno
- 1;
2643 if (dev_priv
->last_seqno
== 0)
2644 dev_priv
->last_seqno
--;
2650 i915_gem_get_seqno(struct drm_i915_private
*dev_priv
, u32
*seqno
)
2652 /* reserve 0 for non-seqno */
2653 if (dev_priv
->next_seqno
== 0) {
2654 int ret
= i915_gem_init_seqno(dev_priv
, 0);
2658 dev_priv
->next_seqno
= 1;
2661 *seqno
= dev_priv
->last_seqno
= dev_priv
->next_seqno
++;
2666 * NB: This function is not allowed to fail. Doing so would mean the the
2667 * request is not being tracked for completion but the work itself is
2668 * going to happen on the hardware. This would be a Bad Thing(tm).
2670 void __i915_add_request(struct drm_i915_gem_request
*request
,
2671 struct drm_i915_gem_object
*obj
,
2674 struct intel_engine_cs
*engine
;
2675 struct drm_i915_private
*dev_priv
;
2676 struct intel_ringbuffer
*ringbuf
;
2681 if (WARN_ON(request
== NULL
))
2684 engine
= request
->engine
;
2685 dev_priv
= request
->i915
;
2686 ringbuf
= request
->ringbuf
;
2689 * To ensure that this call will not fail, space for its emissions
2690 * should already have been reserved in the ring buffer. Let the ring
2691 * know that it is time to use that space up.
2693 request_start
= intel_ring_get_tail(ringbuf
);
2694 reserved_tail
= request
->reserved_space
;
2695 request
->reserved_space
= 0;
2698 * Emit any outstanding flushes - execbuf can fail to emit the flush
2699 * after having emitted the batchbuffer command. Hence we need to fix
2700 * things up similar to emitting the lazy request. The difference here
2701 * is that the flush _must_ happen before the next request, no matter
2705 if (i915
.enable_execlists
)
2706 ret
= logical_ring_flush_all_caches(request
);
2708 ret
= intel_ring_flush_all_caches(request
);
2709 /* Not allowed to fail! */
2710 WARN(ret
, "*_ring_flush_all_caches failed: %d!\n", ret
);
2713 trace_i915_gem_request_add(request
);
2715 request
->head
= request_start
;
2717 /* Whilst this request exists, batch_obj will be on the
2718 * active_list, and so will hold the active reference. Only when this
2719 * request is retired will the the batch_obj be moved onto the
2720 * inactive_list and lose its active reference. Hence we do not need
2721 * to explicitly hold another reference here.
2723 request
->batch_obj
= obj
;
2725 /* Seal the request and mark it as pending execution. Note that
2726 * we may inspect this state, without holding any locks, during
2727 * hangcheck. Hence we apply the barrier to ensure that we do not
2728 * see a more recent value in the hws than we are tracking.
2730 request
->emitted_jiffies
= jiffies
;
2731 request
->previous_seqno
= engine
->last_submitted_seqno
;
2732 smp_store_mb(engine
->last_submitted_seqno
, request
->seqno
);
2733 list_add_tail(&request
->list
, &engine
->request_list
);
2735 /* Record the position of the start of the request so that
2736 * should we detect the updated seqno part-way through the
2737 * GPU processing the request, we never over-estimate the
2738 * position of the head.
2740 request
->postfix
= intel_ring_get_tail(ringbuf
);
2742 if (i915
.enable_execlists
)
2743 ret
= engine
->emit_request(request
);
2745 ret
= engine
->add_request(request
);
2747 request
->tail
= intel_ring_get_tail(ringbuf
);
2749 /* Not allowed to fail! */
2750 WARN(ret
, "emit|add_request failed: %d!\n", ret
);
2752 i915_queue_hangcheck(engine
->i915
);
2754 queue_delayed_work(dev_priv
->wq
,
2755 &dev_priv
->mm
.retire_work
,
2756 round_jiffies_up_relative(HZ
));
2757 intel_mark_busy(dev_priv
);
2759 /* Sanity check that the reserved size was large enough. */
2760 ret
= intel_ring_get_tail(ringbuf
) - request_start
;
2762 ret
+= ringbuf
->size
;
2763 WARN_ONCE(ret
> reserved_tail
,
2764 "Not enough space reserved (%d bytes) "
2765 "for adding the request (%d bytes)\n",
2766 reserved_tail
, ret
);
2769 static bool i915_context_is_banned(struct drm_i915_private
*dev_priv
,
2770 const struct i915_gem_context
*ctx
)
2772 unsigned long elapsed
;
2774 elapsed
= get_seconds() - ctx
->hang_stats
.guilty_ts
;
2776 if (ctx
->hang_stats
.banned
)
2779 if (ctx
->hang_stats
.ban_period_seconds
&&
2780 elapsed
<= ctx
->hang_stats
.ban_period_seconds
) {
2781 if (!i915_gem_context_is_default(ctx
)) {
2782 DRM_DEBUG("context hanging too fast, banning!\n");
2784 } else if (i915_stop_ring_allow_ban(dev_priv
)) {
2785 if (i915_stop_ring_allow_warn(dev_priv
))
2786 DRM_ERROR("gpu hanging too fast, banning!\n");
2794 static void i915_set_reset_status(struct drm_i915_private
*dev_priv
,
2795 struct i915_gem_context
*ctx
,
2798 struct i915_ctx_hang_stats
*hs
;
2803 hs
= &ctx
->hang_stats
;
2806 hs
->banned
= i915_context_is_banned(dev_priv
, ctx
);
2808 hs
->guilty_ts
= get_seconds();
2810 hs
->batch_pending
++;
2814 void i915_gem_request_free(struct kref
*req_ref
)
2816 struct drm_i915_gem_request
*req
= container_of(req_ref
,
2818 kmem_cache_free(req
->i915
->requests
, req
);
2822 __i915_gem_request_alloc(struct intel_engine_cs
*engine
,
2823 struct i915_gem_context
*ctx
,
2824 struct drm_i915_gem_request
**req_out
)
2826 struct drm_i915_private
*dev_priv
= engine
->i915
;
2827 unsigned reset_counter
= i915_reset_counter(&dev_priv
->gpu_error
);
2828 struct drm_i915_gem_request
*req
;
2836 /* ABI: Before userspace accesses the GPU (e.g. execbuffer), report
2837 * EIO if the GPU is already wedged, or EAGAIN to drop the struct_mutex
2840 ret
= i915_gem_check_wedge(reset_counter
, dev_priv
->mm
.interruptible
);
2844 req
= kmem_cache_zalloc(dev_priv
->requests
, GFP_KERNEL
);
2848 ret
= i915_gem_get_seqno(engine
->i915
, &req
->seqno
);
2852 kref_init(&req
->ref
);
2853 req
->i915
= dev_priv
;
2854 req
->engine
= engine
;
2855 req
->reset_counter
= reset_counter
;
2857 i915_gem_context_reference(req
->ctx
);
2860 * Reserve space in the ring buffer for all the commands required to
2861 * eventually emit this request. This is to guarantee that the
2862 * i915_add_request() call can't fail. Note that the reserve may need
2863 * to be redone if the request is not actually submitted straight
2864 * away, e.g. because a GPU scheduler has deferred it.
2866 req
->reserved_space
= MIN_SPACE_FOR_ADD_REQUEST
;
2868 if (i915
.enable_execlists
)
2869 ret
= intel_logical_ring_alloc_request_extras(req
);
2871 ret
= intel_ring_alloc_request_extras(req
);
2879 i915_gem_context_unreference(ctx
);
2881 kmem_cache_free(dev_priv
->requests
, req
);
2886 * i915_gem_request_alloc - allocate a request structure
2888 * @engine: engine that we wish to issue the request on.
2889 * @ctx: context that the request will be associated with.
2890 * This can be NULL if the request is not directly related to
2891 * any specific user context, in which case this function will
2892 * choose an appropriate context to use.
2894 * Returns a pointer to the allocated request if successful,
2895 * or an error code if not.
2897 struct drm_i915_gem_request
*
2898 i915_gem_request_alloc(struct intel_engine_cs
*engine
,
2899 struct i915_gem_context
*ctx
)
2901 struct drm_i915_gem_request
*req
;
2905 ctx
= engine
->i915
->kernel_context
;
2906 err
= __i915_gem_request_alloc(engine
, ctx
, &req
);
2907 return err
? ERR_PTR(err
) : req
;
2910 struct drm_i915_gem_request
*
2911 i915_gem_find_active_request(struct intel_engine_cs
*engine
)
2913 struct drm_i915_gem_request
*request
;
2915 list_for_each_entry(request
, &engine
->request_list
, list
) {
2916 if (i915_gem_request_completed(request
, false))
2925 static void i915_gem_reset_engine_status(struct drm_i915_private
*dev_priv
,
2926 struct intel_engine_cs
*engine
)
2928 struct drm_i915_gem_request
*request
;
2931 request
= i915_gem_find_active_request(engine
);
2933 if (request
== NULL
)
2936 ring_hung
= engine
->hangcheck
.score
>= HANGCHECK_SCORE_RING_HUNG
;
2938 i915_set_reset_status(dev_priv
, request
->ctx
, ring_hung
);
2940 list_for_each_entry_continue(request
, &engine
->request_list
, list
)
2941 i915_set_reset_status(dev_priv
, request
->ctx
, false);
2944 static void i915_gem_reset_engine_cleanup(struct drm_i915_private
*dev_priv
,
2945 struct intel_engine_cs
*engine
)
2947 struct intel_ringbuffer
*buffer
;
2949 while (!list_empty(&engine
->active_list
)) {
2950 struct drm_i915_gem_object
*obj
;
2952 obj
= list_first_entry(&engine
->active_list
,
2953 struct drm_i915_gem_object
,
2954 engine_list
[engine
->id
]);
2956 i915_gem_object_retire__read(obj
, engine
->id
);
2960 * Clear the execlists queue up before freeing the requests, as those
2961 * are the ones that keep the context and ringbuffer backing objects
2965 if (i915
.enable_execlists
) {
2966 /* Ensure irq handler finishes or is cancelled. */
2967 tasklet_kill(&engine
->irq_tasklet
);
2969 intel_execlists_cancel_requests(engine
);
2973 * We must free the requests after all the corresponding objects have
2974 * been moved off active lists. Which is the same order as the normal
2975 * retire_requests function does. This is important if object hold
2976 * implicit references on things like e.g. ppgtt address spaces through
2979 while (!list_empty(&engine
->request_list
)) {
2980 struct drm_i915_gem_request
*request
;
2982 request
= list_first_entry(&engine
->request_list
,
2983 struct drm_i915_gem_request
,
2986 i915_gem_request_retire(request
);
2989 /* Having flushed all requests from all queues, we know that all
2990 * ringbuffers must now be empty. However, since we do not reclaim
2991 * all space when retiring the request (to prevent HEADs colliding
2992 * with rapid ringbuffer wraparound) the amount of available space
2993 * upon reset is less than when we start. Do one more pass over
2994 * all the ringbuffers to reset last_retired_head.
2996 list_for_each_entry(buffer
, &engine
->buffers
, link
) {
2997 buffer
->last_retired_head
= buffer
->tail
;
2998 intel_ring_update_space(buffer
);
3001 intel_ring_init_seqno(engine
, engine
->last_submitted_seqno
);
3004 void i915_gem_reset(struct drm_device
*dev
)
3006 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3007 struct intel_engine_cs
*engine
;
3010 * Before we free the objects from the requests, we need to inspect
3011 * them for finding the guilty party. As the requests only borrow
3012 * their reference to the objects, the inspection must be done first.
3014 for_each_engine(engine
, dev_priv
)
3015 i915_gem_reset_engine_status(dev_priv
, engine
);
3017 for_each_engine(engine
, dev_priv
)
3018 i915_gem_reset_engine_cleanup(dev_priv
, engine
);
3020 i915_gem_context_reset(dev
);
3022 i915_gem_restore_fences(dev
);
3024 WARN_ON(i915_verify_lists(dev
));
3028 * This function clears the request list as sequence numbers are passed.
3029 * @engine: engine to retire requests on
3032 i915_gem_retire_requests_ring(struct intel_engine_cs
*engine
)
3034 WARN_ON(i915_verify_lists(engine
->dev
));
3036 /* Retire requests first as we use it above for the early return.
3037 * If we retire requests last, we may use a later seqno and so clear
3038 * the requests lists without clearing the active list, leading to
3041 while (!list_empty(&engine
->request_list
)) {
3042 struct drm_i915_gem_request
*request
;
3044 request
= list_first_entry(&engine
->request_list
,
3045 struct drm_i915_gem_request
,
3048 if (!i915_gem_request_completed(request
, true))
3051 i915_gem_request_retire(request
);
3054 /* Move any buffers on the active list that are no longer referenced
3055 * by the ringbuffer to the flushing/inactive lists as appropriate,
3056 * before we free the context associated with the requests.
3058 while (!list_empty(&engine
->active_list
)) {
3059 struct drm_i915_gem_object
*obj
;
3061 obj
= list_first_entry(&engine
->active_list
,
3062 struct drm_i915_gem_object
,
3063 engine_list
[engine
->id
]);
3065 if (!list_empty(&obj
->last_read_req
[engine
->id
]->list
))
3068 i915_gem_object_retire__read(obj
, engine
->id
);
3071 if (unlikely(engine
->trace_irq_req
&&
3072 i915_gem_request_completed(engine
->trace_irq_req
, true))) {
3073 engine
->irq_put(engine
);
3074 i915_gem_request_assign(&engine
->trace_irq_req
, NULL
);
3077 WARN_ON(i915_verify_lists(engine
->dev
));
3081 i915_gem_retire_requests(struct drm_i915_private
*dev_priv
)
3083 struct intel_engine_cs
*engine
;
3086 for_each_engine(engine
, dev_priv
) {
3087 i915_gem_retire_requests_ring(engine
);
3088 idle
&= list_empty(&engine
->request_list
);
3089 if (i915
.enable_execlists
) {
3090 spin_lock_bh(&engine
->execlist_lock
);
3091 idle
&= list_empty(&engine
->execlist_queue
);
3092 spin_unlock_bh(&engine
->execlist_lock
);
3097 mod_delayed_work(dev_priv
->wq
,
3098 &dev_priv
->mm
.idle_work
,
3099 msecs_to_jiffies(100));
3105 i915_gem_retire_work_handler(struct work_struct
*work
)
3107 struct drm_i915_private
*dev_priv
=
3108 container_of(work
, typeof(*dev_priv
), mm
.retire_work
.work
);
3109 struct drm_device
*dev
= dev_priv
->dev
;
3112 /* Come back later if the device is busy... */
3114 if (mutex_trylock(&dev
->struct_mutex
)) {
3115 idle
= i915_gem_retire_requests(dev_priv
);
3116 mutex_unlock(&dev
->struct_mutex
);
3119 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
,
3120 round_jiffies_up_relative(HZ
));
3124 i915_gem_idle_work_handler(struct work_struct
*work
)
3126 struct drm_i915_private
*dev_priv
=
3127 container_of(work
, typeof(*dev_priv
), mm
.idle_work
.work
);
3128 struct drm_device
*dev
= dev_priv
->dev
;
3129 struct intel_engine_cs
*engine
;
3131 for_each_engine(engine
, dev_priv
)
3132 if (!list_empty(&engine
->request_list
))
3135 /* we probably should sync with hangcheck here, using cancel_work_sync.
3136 * Also locking seems to be fubar here, engine->request_list is protected
3137 * by dev->struct_mutex. */
3139 intel_mark_idle(dev_priv
);
3141 if (mutex_trylock(&dev
->struct_mutex
)) {
3142 for_each_engine(engine
, dev_priv
)
3143 i915_gem_batch_pool_fini(&engine
->batch_pool
);
3145 mutex_unlock(&dev
->struct_mutex
);
3150 * Ensures that an object will eventually get non-busy by flushing any required
3151 * write domains, emitting any outstanding lazy request and retiring and
3152 * completed requests.
3153 * @obj: object to flush
3156 i915_gem_object_flush_active(struct drm_i915_gem_object
*obj
)
3163 for (i
= 0; i
< I915_NUM_ENGINES
; i
++) {
3164 struct drm_i915_gem_request
*req
;
3166 req
= obj
->last_read_req
[i
];
3170 if (i915_gem_request_completed(req
, true))
3171 i915_gem_object_retire__read(obj
, i
);
3178 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
3179 * @dev: drm device pointer
3180 * @data: ioctl data blob
3181 * @file: drm file pointer
3183 * Returns 0 if successful, else an error is returned with the remaining time in
3184 * the timeout parameter.
3185 * -ETIME: object is still busy after timeout
3186 * -ERESTARTSYS: signal interrupted the wait
3187 * -ENONENT: object doesn't exist
3188 * Also possible, but rare:
3189 * -EAGAIN: GPU wedged
3191 * -ENODEV: Internal IRQ fail
3192 * -E?: The add request failed
3194 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
3195 * non-zero timeout parameter the wait ioctl will wait for the given number of
3196 * nanoseconds on an object becoming unbusy. Since the wait itself does so
3197 * without holding struct_mutex the object may become re-busied before this
3198 * function completes. A similar but shorter * race condition exists in the busy
3202 i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
, struct drm_file
*file
)
3204 struct drm_i915_gem_wait
*args
= data
;
3205 struct drm_i915_gem_object
*obj
;
3206 struct drm_i915_gem_request
*req
[I915_NUM_ENGINES
];
3210 if (args
->flags
!= 0)
3213 ret
= i915_mutex_lock_interruptible(dev
);
3217 obj
= to_intel_bo(drm_gem_object_lookup(file
, args
->bo_handle
));
3218 if (&obj
->base
== NULL
) {
3219 mutex_unlock(&dev
->struct_mutex
);
3223 /* Need to make sure the object gets inactive eventually. */
3224 ret
= i915_gem_object_flush_active(obj
);
3231 /* Do this after OLR check to make sure we make forward progress polling
3232 * on this IOCTL with a timeout == 0 (like busy ioctl)
3234 if (args
->timeout_ns
== 0) {
3239 drm_gem_object_unreference(&obj
->base
);
3241 for (i
= 0; i
< I915_NUM_ENGINES
; i
++) {
3242 if (obj
->last_read_req
[i
] == NULL
)
3245 req
[n
++] = i915_gem_request_reference(obj
->last_read_req
[i
]);
3248 mutex_unlock(&dev
->struct_mutex
);
3250 for (i
= 0; i
< n
; i
++) {
3252 ret
= __i915_wait_request(req
[i
], true,
3253 args
->timeout_ns
> 0 ? &args
->timeout_ns
: NULL
,
3254 to_rps_client(file
));
3255 i915_gem_request_unreference(req
[i
]);
3260 drm_gem_object_unreference(&obj
->base
);
3261 mutex_unlock(&dev
->struct_mutex
);
3266 __i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
3267 struct intel_engine_cs
*to
,
3268 struct drm_i915_gem_request
*from_req
,
3269 struct drm_i915_gem_request
**to_req
)
3271 struct intel_engine_cs
*from
;
3274 from
= i915_gem_request_get_engine(from_req
);
3278 if (i915_gem_request_completed(from_req
, true))
3281 if (!i915_semaphore_is_enabled(to_i915(obj
->base
.dev
))) {
3282 struct drm_i915_private
*i915
= to_i915(obj
->base
.dev
);
3283 ret
= __i915_wait_request(from_req
,
3284 i915
->mm
.interruptible
,
3286 &i915
->rps
.semaphores
);
3290 i915_gem_object_retire_request(obj
, from_req
);
3292 int idx
= intel_ring_sync_index(from
, to
);
3293 u32 seqno
= i915_gem_request_get_seqno(from_req
);
3297 if (seqno
<= from
->semaphore
.sync_seqno
[idx
])
3300 if (*to_req
== NULL
) {
3301 struct drm_i915_gem_request
*req
;
3303 req
= i915_gem_request_alloc(to
, NULL
);
3305 return PTR_ERR(req
);
3310 trace_i915_gem_ring_sync_to(*to_req
, from
, from_req
);
3311 ret
= to
->semaphore
.sync_to(*to_req
, from
, seqno
);
3315 /* We use last_read_req because sync_to()
3316 * might have just caused seqno wrap under
3319 from
->semaphore
.sync_seqno
[idx
] =
3320 i915_gem_request_get_seqno(obj
->last_read_req
[from
->id
]);
3327 * i915_gem_object_sync - sync an object to a ring.
3329 * @obj: object which may be in use on another ring.
3330 * @to: ring we wish to use the object on. May be NULL.
3331 * @to_req: request we wish to use the object for. See below.
3332 * This will be allocated and returned if a request is
3333 * required but not passed in.
3335 * This code is meant to abstract object synchronization with the GPU.
3336 * Calling with NULL implies synchronizing the object with the CPU
3337 * rather than a particular GPU ring. Conceptually we serialise writes
3338 * between engines inside the GPU. We only allow one engine to write
3339 * into a buffer at any time, but multiple readers. To ensure each has
3340 * a coherent view of memory, we must:
3342 * - If there is an outstanding write request to the object, the new
3343 * request must wait for it to complete (either CPU or in hw, requests
3344 * on the same ring will be naturally ordered).
3346 * - If we are a write request (pending_write_domain is set), the new
3347 * request must wait for outstanding read requests to complete.
3349 * For CPU synchronisation (NULL to) no request is required. For syncing with
3350 * rings to_req must be non-NULL. However, a request does not have to be
3351 * pre-allocated. If *to_req is NULL and sync commands will be emitted then a
3352 * request will be allocated automatically and returned through *to_req. Note
3353 * that it is not guaranteed that commands will be emitted (because the system
3354 * might already be idle). Hence there is no need to create a request that
3355 * might never have any work submitted. Note further that if a request is
3356 * returned in *to_req, it is the responsibility of the caller to submit
3357 * that request (after potentially adding more work to it).
3359 * Returns 0 if successful, else propagates up the lower layer error.
3362 i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
3363 struct intel_engine_cs
*to
,
3364 struct drm_i915_gem_request
**to_req
)
3366 const bool readonly
= obj
->base
.pending_write_domain
== 0;
3367 struct drm_i915_gem_request
*req
[I915_NUM_ENGINES
];
3374 return i915_gem_object_wait_rendering(obj
, readonly
);
3378 if (obj
->last_write_req
)
3379 req
[n
++] = obj
->last_write_req
;
3381 for (i
= 0; i
< I915_NUM_ENGINES
; i
++)
3382 if (obj
->last_read_req
[i
])
3383 req
[n
++] = obj
->last_read_req
[i
];
3385 for (i
= 0; i
< n
; i
++) {
3386 ret
= __i915_gem_object_sync(obj
, to
, req
[i
], to_req
);
3394 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object
*obj
)
3396 u32 old_write_domain
, old_read_domains
;
3398 /* Force a pagefault for domain tracking on next user access */
3399 i915_gem_release_mmap(obj
);
3401 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
) == 0)
3404 old_read_domains
= obj
->base
.read_domains
;
3405 old_write_domain
= obj
->base
.write_domain
;
3407 obj
->base
.read_domains
&= ~I915_GEM_DOMAIN_GTT
;
3408 obj
->base
.write_domain
&= ~I915_GEM_DOMAIN_GTT
;
3410 trace_i915_gem_object_change_domain(obj
,
3415 static void __i915_vma_iounmap(struct i915_vma
*vma
)
3417 GEM_BUG_ON(vma
->pin_count
);
3419 if (vma
->iomap
== NULL
)
3422 io_mapping_unmap(vma
->iomap
);
3426 static int __i915_vma_unbind(struct i915_vma
*vma
, bool wait
)
3428 struct drm_i915_gem_object
*obj
= vma
->obj
;
3429 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
3432 if (list_empty(&vma
->obj_link
))
3435 if (!drm_mm_node_allocated(&vma
->node
)) {
3436 i915_gem_vma_destroy(vma
);
3443 BUG_ON(obj
->pages
== NULL
);
3446 ret
= i915_gem_object_wait_rendering(obj
, false);
3451 if (vma
->is_ggtt
&& vma
->ggtt_view
.type
== I915_GGTT_VIEW_NORMAL
) {
3452 i915_gem_object_finish_gtt(obj
);
3454 /* release the fence reg _after_ flushing */
3455 ret
= i915_gem_object_put_fence(obj
);
3459 __i915_vma_iounmap(vma
);
3462 trace_i915_vma_unbind(vma
);
3464 vma
->vm
->unbind_vma(vma
);
3467 list_del_init(&vma
->vm_link
);
3469 if (vma
->ggtt_view
.type
== I915_GGTT_VIEW_NORMAL
) {
3470 obj
->map_and_fenceable
= false;
3471 } else if (vma
->ggtt_view
.pages
) {
3472 sg_free_table(vma
->ggtt_view
.pages
);
3473 kfree(vma
->ggtt_view
.pages
);
3475 vma
->ggtt_view
.pages
= NULL
;
3478 drm_mm_remove_node(&vma
->node
);
3479 i915_gem_vma_destroy(vma
);
3481 /* Since the unbound list is global, only move to that list if
3482 * no more VMAs exist. */
3483 if (list_empty(&obj
->vma_list
))
3484 list_move_tail(&obj
->global_list
, &dev_priv
->mm
.unbound_list
);
3486 /* And finally now the object is completely decoupled from this vma,
3487 * we can drop its hold on the backing storage and allow it to be
3488 * reaped by the shrinker.
3490 i915_gem_object_unpin_pages(obj
);
3495 int i915_vma_unbind(struct i915_vma
*vma
)
3497 return __i915_vma_unbind(vma
, true);
3500 int __i915_vma_unbind_no_wait(struct i915_vma
*vma
)
3502 return __i915_vma_unbind(vma
, false);
3505 int i915_gpu_idle(struct drm_device
*dev
)
3507 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3508 struct intel_engine_cs
*engine
;
3511 /* Flush everything onto the inactive list. */
3512 for_each_engine(engine
, dev_priv
) {
3513 if (!i915
.enable_execlists
) {
3514 struct drm_i915_gem_request
*req
;
3516 req
= i915_gem_request_alloc(engine
, NULL
);
3518 return PTR_ERR(req
);
3520 ret
= i915_switch_context(req
);
3521 i915_add_request_no_flush(req
);
3526 ret
= intel_engine_idle(engine
);
3531 WARN_ON(i915_verify_lists(dev
));
3535 static bool i915_gem_valid_gtt_space(struct i915_vma
*vma
,
3536 unsigned long cache_level
)
3538 struct drm_mm_node
*gtt_space
= &vma
->node
;
3539 struct drm_mm_node
*other
;
3542 * On some machines we have to be careful when putting differing types
3543 * of snoopable memory together to avoid the prefetcher crossing memory
3544 * domains and dying. During vm initialisation, we decide whether or not
3545 * these constraints apply and set the drm_mm.color_adjust
3548 if (vma
->vm
->mm
.color_adjust
== NULL
)
3551 if (!drm_mm_node_allocated(gtt_space
))
3554 if (list_empty(>t_space
->node_list
))
3557 other
= list_entry(gtt_space
->node_list
.prev
, struct drm_mm_node
, node_list
);
3558 if (other
->allocated
&& !other
->hole_follows
&& other
->color
!= cache_level
)
3561 other
= list_entry(gtt_space
->node_list
.next
, struct drm_mm_node
, node_list
);
3562 if (other
->allocated
&& !gtt_space
->hole_follows
&& other
->color
!= cache_level
)
3569 * Finds free space in the GTT aperture and binds the object or a view of it
3571 * @obj: object to bind
3572 * @vm: address space to bind into
3573 * @ggtt_view: global gtt view if applicable
3574 * @alignment: requested alignment
3575 * @flags: mask of PIN_* flags to use
3577 static struct i915_vma
*
3578 i915_gem_object_bind_to_vm(struct drm_i915_gem_object
*obj
,
3579 struct i915_address_space
*vm
,
3580 const struct i915_ggtt_view
*ggtt_view
,
3584 struct drm_device
*dev
= obj
->base
.dev
;
3585 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3586 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
3587 u32 fence_alignment
, unfenced_alignment
;
3588 u32 search_flag
, alloc_flag
;
3590 u64 size
, fence_size
;
3591 struct i915_vma
*vma
;
3594 if (i915_is_ggtt(vm
)) {
3597 if (WARN_ON(!ggtt_view
))
3598 return ERR_PTR(-EINVAL
);
3600 view_size
= i915_ggtt_view_size(obj
, ggtt_view
);
3602 fence_size
= i915_gem_get_gtt_size(dev
,
3605 fence_alignment
= i915_gem_get_gtt_alignment(dev
,
3609 unfenced_alignment
= i915_gem_get_gtt_alignment(dev
,
3613 size
= flags
& PIN_MAPPABLE
? fence_size
: view_size
;
3615 fence_size
= i915_gem_get_gtt_size(dev
,
3618 fence_alignment
= i915_gem_get_gtt_alignment(dev
,
3622 unfenced_alignment
=
3623 i915_gem_get_gtt_alignment(dev
,
3627 size
= flags
& PIN_MAPPABLE
? fence_size
: obj
->base
.size
;
3630 start
= flags
& PIN_OFFSET_BIAS
? flags
& PIN_OFFSET_MASK
: 0;
3632 if (flags
& PIN_MAPPABLE
)
3633 end
= min_t(u64
, end
, ggtt
->mappable_end
);
3634 if (flags
& PIN_ZONE_4G
)
3635 end
= min_t(u64
, end
, (1ULL << 32) - PAGE_SIZE
);
3638 alignment
= flags
& PIN_MAPPABLE
? fence_alignment
:
3640 if (flags
& PIN_MAPPABLE
&& alignment
& (fence_alignment
- 1)) {
3641 DRM_DEBUG("Invalid object (view type=%u) alignment requested %u\n",
3642 ggtt_view
? ggtt_view
->type
: 0,
3644 return ERR_PTR(-EINVAL
);
3647 /* If binding the object/GGTT view requires more space than the entire
3648 * aperture has, reject it early before evicting everything in a vain
3649 * attempt to find space.
3652 DRM_DEBUG("Attempting to bind an object (view type=%u) larger than the aperture: size=%llu > %s aperture=%llu\n",
3653 ggtt_view
? ggtt_view
->type
: 0,
3655 flags
& PIN_MAPPABLE
? "mappable" : "total",
3657 return ERR_PTR(-E2BIG
);
3660 ret
= i915_gem_object_get_pages(obj
);
3662 return ERR_PTR(ret
);
3664 i915_gem_object_pin_pages(obj
);
3666 vma
= ggtt_view
? i915_gem_obj_lookup_or_create_ggtt_vma(obj
, ggtt_view
) :
3667 i915_gem_obj_lookup_or_create_vma(obj
, vm
);
3672 if (flags
& PIN_OFFSET_FIXED
) {
3673 uint64_t offset
= flags
& PIN_OFFSET_MASK
;
3675 if (offset
& (alignment
- 1) || offset
+ size
> end
) {
3679 vma
->node
.start
= offset
;
3680 vma
->node
.size
= size
;
3681 vma
->node
.color
= obj
->cache_level
;
3682 ret
= drm_mm_reserve_node(&vm
->mm
, &vma
->node
);
3684 ret
= i915_gem_evict_for_vma(vma
);
3686 ret
= drm_mm_reserve_node(&vm
->mm
, &vma
->node
);
3691 if (flags
& PIN_HIGH
) {
3692 search_flag
= DRM_MM_SEARCH_BELOW
;
3693 alloc_flag
= DRM_MM_CREATE_TOP
;
3695 search_flag
= DRM_MM_SEARCH_DEFAULT
;
3696 alloc_flag
= DRM_MM_CREATE_DEFAULT
;
3700 ret
= drm_mm_insert_node_in_range_generic(&vm
->mm
, &vma
->node
,
3707 ret
= i915_gem_evict_something(dev
, vm
, size
, alignment
,
3717 if (WARN_ON(!i915_gem_valid_gtt_space(vma
, obj
->cache_level
))) {
3719 goto err_remove_node
;
3722 trace_i915_vma_bind(vma
, flags
);
3723 ret
= i915_vma_bind(vma
, obj
->cache_level
, flags
);
3725 goto err_remove_node
;
3727 list_move_tail(&obj
->global_list
, &dev_priv
->mm
.bound_list
);
3728 list_add_tail(&vma
->vm_link
, &vm
->inactive_list
);
3733 drm_mm_remove_node(&vma
->node
);
3735 i915_gem_vma_destroy(vma
);
3738 i915_gem_object_unpin_pages(obj
);
3743 i915_gem_clflush_object(struct drm_i915_gem_object
*obj
,
3746 /* If we don't have a page list set up, then we're not pinned
3747 * to GPU, and we can ignore the cache flush because it'll happen
3748 * again at bind time.
3750 if (obj
->pages
== NULL
)
3754 * Stolen memory is always coherent with the GPU as it is explicitly
3755 * marked as wc by the system, or the system is cache-coherent.
3757 if (obj
->stolen
|| obj
->phys_handle
)
3760 /* If the GPU is snooping the contents of the CPU cache,
3761 * we do not need to manually clear the CPU cache lines. However,
3762 * the caches are only snooped when the render cache is
3763 * flushed/invalidated. As we always have to emit invalidations
3764 * and flushes when moving into and out of the RENDER domain, correct
3765 * snooping behaviour occurs naturally as the result of our domain
3768 if (!force
&& cpu_cache_is_coherent(obj
->base
.dev
, obj
->cache_level
)) {
3769 obj
->cache_dirty
= true;
3773 trace_i915_gem_object_clflush(obj
);
3774 drm_clflush_sg(obj
->pages
);
3775 obj
->cache_dirty
= false;
3780 /** Flushes the GTT write domain for the object if it's dirty. */
3782 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
)
3784 uint32_t old_write_domain
;
3786 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_GTT
)
3789 /* No actual flushing is required for the GTT write domain. Writes
3790 * to it immediately go to main memory as far as we know, so there's
3791 * no chipset flush. It also doesn't land in render cache.
3793 * However, we do have to enforce the order so that all writes through
3794 * the GTT land before any writes to the device, such as updates to
3799 old_write_domain
= obj
->base
.write_domain
;
3800 obj
->base
.write_domain
= 0;
3802 intel_fb_obj_flush(obj
, false, ORIGIN_GTT
);
3804 trace_i915_gem_object_change_domain(obj
,
3805 obj
->base
.read_domains
,
3809 /** Flushes the CPU write domain for the object if it's dirty. */
3811 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
)
3813 uint32_t old_write_domain
;
3815 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
)
3818 if (i915_gem_clflush_object(obj
, obj
->pin_display
))
3819 i915_gem_chipset_flush(to_i915(obj
->base
.dev
));
3821 old_write_domain
= obj
->base
.write_domain
;
3822 obj
->base
.write_domain
= 0;
3824 intel_fb_obj_flush(obj
, false, ORIGIN_CPU
);
3826 trace_i915_gem_object_change_domain(obj
,
3827 obj
->base
.read_domains
,
3832 * Moves a single object to the GTT read, and possibly write domain.
3833 * @obj: object to act on
3834 * @write: ask for write access or read only
3836 * This function returns when the move is complete, including waiting on
3840 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
, bool write
)
3842 struct drm_device
*dev
= obj
->base
.dev
;
3843 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3844 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
3845 uint32_t old_write_domain
, old_read_domains
;
3846 struct i915_vma
*vma
;
3849 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_GTT
)
3852 ret
= i915_gem_object_wait_rendering(obj
, !write
);
3856 /* Flush and acquire obj->pages so that we are coherent through
3857 * direct access in memory with previous cached writes through
3858 * shmemfs and that our cache domain tracking remains valid.
3859 * For example, if the obj->filp was moved to swap without us
3860 * being notified and releasing the pages, we would mistakenly
3861 * continue to assume that the obj remained out of the CPU cached
3864 ret
= i915_gem_object_get_pages(obj
);
3868 i915_gem_object_flush_cpu_write_domain(obj
);
3870 /* Serialise direct access to this object with the barriers for
3871 * coherent writes from the GPU, by effectively invalidating the
3872 * GTT domain upon first access.
3874 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
) == 0)
3877 old_write_domain
= obj
->base
.write_domain
;
3878 old_read_domains
= obj
->base
.read_domains
;
3880 /* It should now be out of any other write domains, and we can update
3881 * the domain values for our changes.
3883 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
3884 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
3886 obj
->base
.read_domains
= I915_GEM_DOMAIN_GTT
;
3887 obj
->base
.write_domain
= I915_GEM_DOMAIN_GTT
;
3891 trace_i915_gem_object_change_domain(obj
,
3895 /* And bump the LRU for this access */
3896 vma
= i915_gem_obj_to_ggtt(obj
);
3897 if (vma
&& drm_mm_node_allocated(&vma
->node
) && !obj
->active
)
3898 list_move_tail(&vma
->vm_link
,
3899 &ggtt
->base
.inactive_list
);
3905 * Changes the cache-level of an object across all VMA.
3906 * @obj: object to act on
3907 * @cache_level: new cache level to set for the object
3909 * After this function returns, the object will be in the new cache-level
3910 * across all GTT and the contents of the backing storage will be coherent,
3911 * with respect to the new cache-level. In order to keep the backing storage
3912 * coherent for all users, we only allow a single cache level to be set
3913 * globally on the object and prevent it from being changed whilst the
3914 * hardware is reading from the object. That is if the object is currently
3915 * on the scanout it will be set to uncached (or equivalent display
3916 * cache coherency) and all non-MOCS GPU access will also be uncached so
3917 * that all direct access to the scanout remains coherent.
3919 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
3920 enum i915_cache_level cache_level
)
3922 struct drm_device
*dev
= obj
->base
.dev
;
3923 struct i915_vma
*vma
, *next
;
3927 if (obj
->cache_level
== cache_level
)
3930 /* Inspect the list of currently bound VMA and unbind any that would
3931 * be invalid given the new cache-level. This is principally to
3932 * catch the issue of the CS prefetch crossing page boundaries and
3933 * reading an invalid PTE on older architectures.
3935 list_for_each_entry_safe(vma
, next
, &obj
->vma_list
, obj_link
) {
3936 if (!drm_mm_node_allocated(&vma
->node
))
3939 if (vma
->pin_count
) {
3940 DRM_DEBUG("can not change the cache level of pinned objects\n");
3944 if (!i915_gem_valid_gtt_space(vma
, cache_level
)) {
3945 ret
= i915_vma_unbind(vma
);
3952 /* We can reuse the existing drm_mm nodes but need to change the
3953 * cache-level on the PTE. We could simply unbind them all and
3954 * rebind with the correct cache-level on next use. However since
3955 * we already have a valid slot, dma mapping, pages etc, we may as
3956 * rewrite the PTE in the belief that doing so tramples upon less
3957 * state and so involves less work.
3960 /* Before we change the PTE, the GPU must not be accessing it.
3961 * If we wait upon the object, we know that all the bound
3962 * VMA are no longer active.
3964 ret
= i915_gem_object_wait_rendering(obj
, false);
3968 if (!HAS_LLC(dev
) && cache_level
!= I915_CACHE_NONE
) {
3969 /* Access to snoopable pages through the GTT is
3970 * incoherent and on some machines causes a hard
3971 * lockup. Relinquish the CPU mmaping to force
3972 * userspace to refault in the pages and we can
3973 * then double check if the GTT mapping is still
3974 * valid for that pointer access.
3976 i915_gem_release_mmap(obj
);
3978 /* As we no longer need a fence for GTT access,
3979 * we can relinquish it now (and so prevent having
3980 * to steal a fence from someone else on the next
3981 * fence request). Note GPU activity would have
3982 * dropped the fence as all snoopable access is
3983 * supposed to be linear.
3985 ret
= i915_gem_object_put_fence(obj
);
3989 /* We either have incoherent backing store and
3990 * so no GTT access or the architecture is fully
3991 * coherent. In such cases, existing GTT mmaps
3992 * ignore the cache bit in the PTE and we can
3993 * rewrite it without confusing the GPU or having
3994 * to force userspace to fault back in its mmaps.
3998 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
) {
3999 if (!drm_mm_node_allocated(&vma
->node
))
4002 ret
= i915_vma_bind(vma
, cache_level
, PIN_UPDATE
);
4008 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
)
4009 vma
->node
.color
= cache_level
;
4010 obj
->cache_level
= cache_level
;
4013 /* Flush the dirty CPU caches to the backing storage so that the
4014 * object is now coherent at its new cache level (with respect
4015 * to the access domain).
4017 if (obj
->cache_dirty
&&
4018 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
&&
4019 cpu_write_needs_clflush(obj
)) {
4020 if (i915_gem_clflush_object(obj
, true))
4021 i915_gem_chipset_flush(to_i915(obj
->base
.dev
));
4027 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
4028 struct drm_file
*file
)
4030 struct drm_i915_gem_caching
*args
= data
;
4031 struct drm_i915_gem_object
*obj
;
4033 obj
= to_intel_bo(drm_gem_object_lookup(file
, args
->handle
));
4034 if (&obj
->base
== NULL
)
4037 switch (obj
->cache_level
) {
4038 case I915_CACHE_LLC
:
4039 case I915_CACHE_L3_LLC
:
4040 args
->caching
= I915_CACHING_CACHED
;
4044 args
->caching
= I915_CACHING_DISPLAY
;
4048 args
->caching
= I915_CACHING_NONE
;
4052 drm_gem_object_unreference_unlocked(&obj
->base
);
4056 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
4057 struct drm_file
*file
)
4059 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4060 struct drm_i915_gem_caching
*args
= data
;
4061 struct drm_i915_gem_object
*obj
;
4062 enum i915_cache_level level
;
4065 switch (args
->caching
) {
4066 case I915_CACHING_NONE
:
4067 level
= I915_CACHE_NONE
;
4069 case I915_CACHING_CACHED
:
4071 * Due to a HW issue on BXT A stepping, GPU stores via a
4072 * snooped mapping may leave stale data in a corresponding CPU
4073 * cacheline, whereas normally such cachelines would get
4076 if (!HAS_LLC(dev
) && !HAS_SNOOP(dev
))
4079 level
= I915_CACHE_LLC
;
4081 case I915_CACHING_DISPLAY
:
4082 level
= HAS_WT(dev
) ? I915_CACHE_WT
: I915_CACHE_NONE
;
4088 intel_runtime_pm_get(dev_priv
);
4090 ret
= i915_mutex_lock_interruptible(dev
);
4094 obj
= to_intel_bo(drm_gem_object_lookup(file
, args
->handle
));
4095 if (&obj
->base
== NULL
) {
4100 ret
= i915_gem_object_set_cache_level(obj
, level
);
4102 drm_gem_object_unreference(&obj
->base
);
4104 mutex_unlock(&dev
->struct_mutex
);
4106 intel_runtime_pm_put(dev_priv
);
4112 * Prepare buffer for display plane (scanout, cursors, etc).
4113 * Can be called from an uninterruptible phase (modesetting) and allows
4114 * any flushes to be pipelined (for pageflips).
4117 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
4119 const struct i915_ggtt_view
*view
)
4121 u32 old_read_domains
, old_write_domain
;
4124 /* Mark the pin_display early so that we account for the
4125 * display coherency whilst setting up the cache domains.
4129 /* The display engine is not coherent with the LLC cache on gen6. As
4130 * a result, we make sure that the pinning that is about to occur is
4131 * done with uncached PTEs. This is lowest common denominator for all
4134 * However for gen6+, we could do better by using the GFDT bit instead
4135 * of uncaching, which would allow us to flush all the LLC-cached data
4136 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
4138 ret
= i915_gem_object_set_cache_level(obj
,
4139 HAS_WT(obj
->base
.dev
) ? I915_CACHE_WT
: I915_CACHE_NONE
);
4141 goto err_unpin_display
;
4143 /* As the user may map the buffer once pinned in the display plane
4144 * (e.g. libkms for the bootup splash), we have to ensure that we
4145 * always use map_and_fenceable for all scanout buffers.
4147 ret
= i915_gem_object_ggtt_pin(obj
, view
, alignment
,
4148 view
->type
== I915_GGTT_VIEW_NORMAL
?
4151 goto err_unpin_display
;
4153 i915_gem_object_flush_cpu_write_domain(obj
);
4155 old_write_domain
= obj
->base
.write_domain
;
4156 old_read_domains
= obj
->base
.read_domains
;
4158 /* It should now be out of any other write domains, and we can update
4159 * the domain values for our changes.
4161 obj
->base
.write_domain
= 0;
4162 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
4164 trace_i915_gem_object_change_domain(obj
,
4176 i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object
*obj
,
4177 const struct i915_ggtt_view
*view
)
4179 if (WARN_ON(obj
->pin_display
== 0))
4182 i915_gem_object_ggtt_unpin_view(obj
, view
);
4188 * Moves a single object to the CPU read, and possibly write domain.
4189 * @obj: object to act on
4190 * @write: requesting write or read-only access
4192 * This function returns when the move is complete, including waiting on
4196 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
)
4198 uint32_t old_write_domain
, old_read_domains
;
4201 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_CPU
)
4204 ret
= i915_gem_object_wait_rendering(obj
, !write
);
4208 i915_gem_object_flush_gtt_write_domain(obj
);
4210 old_write_domain
= obj
->base
.write_domain
;
4211 old_read_domains
= obj
->base
.read_domains
;
4213 /* Flush the CPU cache if it's still invalid. */
4214 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) == 0) {
4215 i915_gem_clflush_object(obj
, false);
4217 obj
->base
.read_domains
|= I915_GEM_DOMAIN_CPU
;
4220 /* It should now be out of any other write domains, and we can update
4221 * the domain values for our changes.
4223 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
4225 /* If we're writing through the CPU, then the GPU read domains will
4226 * need to be invalidated at next use.
4229 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
4230 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
4233 trace_i915_gem_object_change_domain(obj
,
4240 /* Throttle our rendering by waiting until the ring has completed our requests
4241 * emitted over 20 msec ago.
4243 * Note that if we were to use the current jiffies each time around the loop,
4244 * we wouldn't escape the function with any frames outstanding if the time to
4245 * render a frame was over 20ms.
4247 * This should get us reasonable parallelism between CPU and GPU but also
4248 * relatively low latency when blocking on a particular request to finish.
4251 i915_gem_ring_throttle(struct drm_device
*dev
, struct drm_file
*file
)
4253 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4254 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
4255 unsigned long recent_enough
= jiffies
- DRM_I915_THROTTLE_JIFFIES
;
4256 struct drm_i915_gem_request
*request
, *target
= NULL
;
4259 ret
= i915_gem_wait_for_error(&dev_priv
->gpu_error
);
4263 /* ABI: return -EIO if already wedged */
4264 if (i915_terminally_wedged(&dev_priv
->gpu_error
))
4267 spin_lock(&file_priv
->mm
.lock
);
4268 list_for_each_entry(request
, &file_priv
->mm
.request_list
, client_list
) {
4269 if (time_after_eq(request
->emitted_jiffies
, recent_enough
))
4273 * Note that the request might not have been submitted yet.
4274 * In which case emitted_jiffies will be zero.
4276 if (!request
->emitted_jiffies
)
4282 i915_gem_request_reference(target
);
4283 spin_unlock(&file_priv
->mm
.lock
);
4288 ret
= __i915_wait_request(target
, true, NULL
, NULL
);
4290 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, 0);
4292 i915_gem_request_unreference(target
);
4298 i915_vma_misplaced(struct i915_vma
*vma
, uint32_t alignment
, uint64_t flags
)
4300 struct drm_i915_gem_object
*obj
= vma
->obj
;
4303 vma
->node
.start
& (alignment
- 1))
4306 if (flags
& PIN_MAPPABLE
&& !obj
->map_and_fenceable
)
4309 if (flags
& PIN_OFFSET_BIAS
&&
4310 vma
->node
.start
< (flags
& PIN_OFFSET_MASK
))
4313 if (flags
& PIN_OFFSET_FIXED
&&
4314 vma
->node
.start
!= (flags
& PIN_OFFSET_MASK
))
4320 void __i915_vma_set_map_and_fenceable(struct i915_vma
*vma
)
4322 struct drm_i915_gem_object
*obj
= vma
->obj
;
4323 bool mappable
, fenceable
;
4324 u32 fence_size
, fence_alignment
;
4326 fence_size
= i915_gem_get_gtt_size(obj
->base
.dev
,
4329 fence_alignment
= i915_gem_get_gtt_alignment(obj
->base
.dev
,
4334 fenceable
= (vma
->node
.size
== fence_size
&&
4335 (vma
->node
.start
& (fence_alignment
- 1)) == 0);
4337 mappable
= (vma
->node
.start
+ fence_size
<=
4338 to_i915(obj
->base
.dev
)->ggtt
.mappable_end
);
4340 obj
->map_and_fenceable
= mappable
&& fenceable
;
4344 i915_gem_object_do_pin(struct drm_i915_gem_object
*obj
,
4345 struct i915_address_space
*vm
,
4346 const struct i915_ggtt_view
*ggtt_view
,
4350 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
4351 struct i915_vma
*vma
;
4355 if (WARN_ON(vm
== &dev_priv
->mm
.aliasing_ppgtt
->base
))
4358 if (WARN_ON(flags
& (PIN_GLOBAL
| PIN_MAPPABLE
) && !i915_is_ggtt(vm
)))
4361 if (WARN_ON((flags
& (PIN_MAPPABLE
| PIN_GLOBAL
)) == PIN_MAPPABLE
))
4364 if (WARN_ON(i915_is_ggtt(vm
) != !!ggtt_view
))
4367 vma
= ggtt_view
? i915_gem_obj_to_ggtt_view(obj
, ggtt_view
) :
4368 i915_gem_obj_to_vma(obj
, vm
);
4371 if (WARN_ON(vma
->pin_count
== DRM_I915_GEM_OBJECT_MAX_PIN_COUNT
))
4374 if (i915_vma_misplaced(vma
, alignment
, flags
)) {
4375 WARN(vma
->pin_count
,
4376 "bo is already pinned in %s with incorrect alignment:"
4377 " offset=%08x %08x, req.alignment=%x, req.map_and_fenceable=%d,"
4378 " obj->map_and_fenceable=%d\n",
4379 ggtt_view
? "ggtt" : "ppgtt",
4380 upper_32_bits(vma
->node
.start
),
4381 lower_32_bits(vma
->node
.start
),
4383 !!(flags
& PIN_MAPPABLE
),
4384 obj
->map_and_fenceable
);
4385 ret
= i915_vma_unbind(vma
);
4393 bound
= vma
? vma
->bound
: 0;
4394 if (vma
== NULL
|| !drm_mm_node_allocated(&vma
->node
)) {
4395 vma
= i915_gem_object_bind_to_vm(obj
, vm
, ggtt_view
, alignment
,
4398 return PTR_ERR(vma
);
4400 ret
= i915_vma_bind(vma
, obj
->cache_level
, flags
);
4405 if (ggtt_view
&& ggtt_view
->type
== I915_GGTT_VIEW_NORMAL
&&
4406 (bound
^ vma
->bound
) & GLOBAL_BIND
) {
4407 __i915_vma_set_map_and_fenceable(vma
);
4408 WARN_ON(flags
& PIN_MAPPABLE
&& !obj
->map_and_fenceable
);
4416 i915_gem_object_pin(struct drm_i915_gem_object
*obj
,
4417 struct i915_address_space
*vm
,
4421 return i915_gem_object_do_pin(obj
, vm
,
4422 i915_is_ggtt(vm
) ? &i915_ggtt_view_normal
: NULL
,
4427 i915_gem_object_ggtt_pin(struct drm_i915_gem_object
*obj
,
4428 const struct i915_ggtt_view
*view
,
4432 struct drm_device
*dev
= obj
->base
.dev
;
4433 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4434 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
4438 return i915_gem_object_do_pin(obj
, &ggtt
->base
, view
,
4439 alignment
, flags
| PIN_GLOBAL
);
4443 i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object
*obj
,
4444 const struct i915_ggtt_view
*view
)
4446 struct i915_vma
*vma
= i915_gem_obj_to_ggtt_view(obj
, view
);
4448 WARN_ON(vma
->pin_count
== 0);
4449 WARN_ON(!i915_gem_obj_ggtt_bound_view(obj
, view
));
4455 i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
4456 struct drm_file
*file
)
4458 struct drm_i915_gem_busy
*args
= data
;
4459 struct drm_i915_gem_object
*obj
;
4462 ret
= i915_mutex_lock_interruptible(dev
);
4466 obj
= to_intel_bo(drm_gem_object_lookup(file
, args
->handle
));
4467 if (&obj
->base
== NULL
) {
4472 /* Count all active objects as busy, even if they are currently not used
4473 * by the gpu. Users of this interface expect objects to eventually
4474 * become non-busy without any further actions, therefore emit any
4475 * necessary flushes here.
4477 ret
= i915_gem_object_flush_active(obj
);
4485 for (i
= 0; i
< I915_NUM_ENGINES
; i
++) {
4486 struct drm_i915_gem_request
*req
;
4488 req
= obj
->last_read_req
[i
];
4490 args
->busy
|= 1 << (16 + req
->engine
->exec_id
);
4492 if (obj
->last_write_req
)
4493 args
->busy
|= obj
->last_write_req
->engine
->exec_id
;
4497 drm_gem_object_unreference(&obj
->base
);
4499 mutex_unlock(&dev
->struct_mutex
);
4504 i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
4505 struct drm_file
*file_priv
)
4507 return i915_gem_ring_throttle(dev
, file_priv
);
4511 i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
4512 struct drm_file
*file_priv
)
4514 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4515 struct drm_i915_gem_madvise
*args
= data
;
4516 struct drm_i915_gem_object
*obj
;
4519 switch (args
->madv
) {
4520 case I915_MADV_DONTNEED
:
4521 case I915_MADV_WILLNEED
:
4527 ret
= i915_mutex_lock_interruptible(dev
);
4531 obj
= to_intel_bo(drm_gem_object_lookup(file_priv
, args
->handle
));
4532 if (&obj
->base
== NULL
) {
4537 if (i915_gem_obj_is_pinned(obj
)) {
4543 obj
->tiling_mode
!= I915_TILING_NONE
&&
4544 dev_priv
->quirks
& QUIRK_PIN_SWIZZLED_PAGES
) {
4545 if (obj
->madv
== I915_MADV_WILLNEED
)
4546 i915_gem_object_unpin_pages(obj
);
4547 if (args
->madv
== I915_MADV_WILLNEED
)
4548 i915_gem_object_pin_pages(obj
);
4551 if (obj
->madv
!= __I915_MADV_PURGED
)
4552 obj
->madv
= args
->madv
;
4554 /* if the object is no longer attached, discard its backing storage */
4555 if (obj
->madv
== I915_MADV_DONTNEED
&& obj
->pages
== NULL
)
4556 i915_gem_object_truncate(obj
);
4558 args
->retained
= obj
->madv
!= __I915_MADV_PURGED
;
4561 drm_gem_object_unreference(&obj
->base
);
4563 mutex_unlock(&dev
->struct_mutex
);
4567 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
4568 const struct drm_i915_gem_object_ops
*ops
)
4572 INIT_LIST_HEAD(&obj
->global_list
);
4573 for (i
= 0; i
< I915_NUM_ENGINES
; i
++)
4574 INIT_LIST_HEAD(&obj
->engine_list
[i
]);
4575 INIT_LIST_HEAD(&obj
->obj_exec_link
);
4576 INIT_LIST_HEAD(&obj
->vma_list
);
4577 INIT_LIST_HEAD(&obj
->batch_pool_link
);
4581 obj
->fence_reg
= I915_FENCE_REG_NONE
;
4582 obj
->madv
= I915_MADV_WILLNEED
;
4584 i915_gem_info_add_obj(obj
->base
.dev
->dev_private
, obj
->base
.size
);
4587 static const struct drm_i915_gem_object_ops i915_gem_object_ops
= {
4588 .flags
= I915_GEM_OBJECT_HAS_STRUCT_PAGE
,
4589 .get_pages
= i915_gem_object_get_pages_gtt
,
4590 .put_pages
= i915_gem_object_put_pages_gtt
,
4593 struct drm_i915_gem_object
*i915_gem_object_create(struct drm_device
*dev
,
4596 struct drm_i915_gem_object
*obj
;
4597 struct address_space
*mapping
;
4601 obj
= i915_gem_object_alloc(dev
);
4603 return ERR_PTR(-ENOMEM
);
4605 ret
= drm_gem_object_init(dev
, &obj
->base
, size
);
4609 mask
= GFP_HIGHUSER
| __GFP_RECLAIMABLE
;
4610 if (IS_CRESTLINE(dev
) || IS_BROADWATER(dev
)) {
4611 /* 965gm cannot relocate objects above 4GiB. */
4612 mask
&= ~__GFP_HIGHMEM
;
4613 mask
|= __GFP_DMA32
;
4616 mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
4617 mapping_set_gfp_mask(mapping
, mask
);
4619 i915_gem_object_init(obj
, &i915_gem_object_ops
);
4621 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
4622 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
4625 /* On some devices, we can have the GPU use the LLC (the CPU
4626 * cache) for about a 10% performance improvement
4627 * compared to uncached. Graphics requests other than
4628 * display scanout are coherent with the CPU in
4629 * accessing this cache. This means in this mode we
4630 * don't need to clflush on the CPU side, and on the
4631 * GPU side we only need to flush internal caches to
4632 * get data visible to the CPU.
4634 * However, we maintain the display planes as UC, and so
4635 * need to rebind when first used as such.
4637 obj
->cache_level
= I915_CACHE_LLC
;
4639 obj
->cache_level
= I915_CACHE_NONE
;
4641 trace_i915_gem_object_create(obj
);
4646 i915_gem_object_free(obj
);
4648 return ERR_PTR(ret
);
4651 static bool discard_backing_storage(struct drm_i915_gem_object
*obj
)
4653 /* If we are the last user of the backing storage (be it shmemfs
4654 * pages or stolen etc), we know that the pages are going to be
4655 * immediately released. In this case, we can then skip copying
4656 * back the contents from the GPU.
4659 if (obj
->madv
!= I915_MADV_WILLNEED
)
4662 if (obj
->base
.filp
== NULL
)
4665 /* At first glance, this looks racy, but then again so would be
4666 * userspace racing mmap against close. However, the first external
4667 * reference to the filp can only be obtained through the
4668 * i915_gem_mmap_ioctl() which safeguards us against the user
4669 * acquiring such a reference whilst we are in the middle of
4670 * freeing the object.
4672 return atomic_long_read(&obj
->base
.filp
->f_count
) == 1;
4675 void i915_gem_free_object(struct drm_gem_object
*gem_obj
)
4677 struct drm_i915_gem_object
*obj
= to_intel_bo(gem_obj
);
4678 struct drm_device
*dev
= obj
->base
.dev
;
4679 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4680 struct i915_vma
*vma
, *next
;
4682 intel_runtime_pm_get(dev_priv
);
4684 trace_i915_gem_object_destroy(obj
);
4686 list_for_each_entry_safe(vma
, next
, &obj
->vma_list
, obj_link
) {
4690 ret
= i915_vma_unbind(vma
);
4691 if (WARN_ON(ret
== -ERESTARTSYS
)) {
4692 bool was_interruptible
;
4694 was_interruptible
= dev_priv
->mm
.interruptible
;
4695 dev_priv
->mm
.interruptible
= false;
4697 WARN_ON(i915_vma_unbind(vma
));
4699 dev_priv
->mm
.interruptible
= was_interruptible
;
4703 /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
4704 * before progressing. */
4706 i915_gem_object_unpin_pages(obj
);
4708 WARN_ON(obj
->frontbuffer_bits
);
4710 if (obj
->pages
&& obj
->madv
== I915_MADV_WILLNEED
&&
4711 dev_priv
->quirks
& QUIRK_PIN_SWIZZLED_PAGES
&&
4712 obj
->tiling_mode
!= I915_TILING_NONE
)
4713 i915_gem_object_unpin_pages(obj
);
4715 if (WARN_ON(obj
->pages_pin_count
))
4716 obj
->pages_pin_count
= 0;
4717 if (discard_backing_storage(obj
))
4718 obj
->madv
= I915_MADV_DONTNEED
;
4719 i915_gem_object_put_pages(obj
);
4720 i915_gem_object_free_mmap_offset(obj
);
4724 if (obj
->base
.import_attach
)
4725 drm_prime_gem_destroy(&obj
->base
, NULL
);
4727 if (obj
->ops
->release
)
4728 obj
->ops
->release(obj
);
4730 drm_gem_object_release(&obj
->base
);
4731 i915_gem_info_remove_obj(dev_priv
, obj
->base
.size
);
4734 i915_gem_object_free(obj
);
4736 intel_runtime_pm_put(dev_priv
);
4739 struct i915_vma
*i915_gem_obj_to_vma(struct drm_i915_gem_object
*obj
,
4740 struct i915_address_space
*vm
)
4742 struct i915_vma
*vma
;
4743 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
) {
4744 if (vma
->ggtt_view
.type
== I915_GGTT_VIEW_NORMAL
&&
4751 struct i915_vma
*i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object
*obj
,
4752 const struct i915_ggtt_view
*view
)
4754 struct i915_vma
*vma
;
4758 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
)
4759 if (vma
->is_ggtt
&& i915_ggtt_view_equal(&vma
->ggtt_view
, view
))
4764 void i915_gem_vma_destroy(struct i915_vma
*vma
)
4766 WARN_ON(vma
->node
.allocated
);
4768 /* Keep the vma as a placeholder in the execbuffer reservation lists */
4769 if (!list_empty(&vma
->exec_list
))
4773 i915_ppgtt_put(i915_vm_to_ppgtt(vma
->vm
));
4775 list_del(&vma
->obj_link
);
4777 kmem_cache_free(to_i915(vma
->obj
->base
.dev
)->vmas
, vma
);
4781 i915_gem_stop_engines(struct drm_device
*dev
)
4783 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4784 struct intel_engine_cs
*engine
;
4786 for_each_engine(engine
, dev_priv
)
4787 dev_priv
->gt
.stop_engine(engine
);
4791 i915_gem_suspend(struct drm_device
*dev
)
4793 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4796 mutex_lock(&dev
->struct_mutex
);
4797 ret
= i915_gpu_idle(dev
);
4801 i915_gem_retire_requests(dev_priv
);
4803 i915_gem_stop_engines(dev
);
4804 i915_gem_context_lost(dev_priv
);
4805 mutex_unlock(&dev
->struct_mutex
);
4807 cancel_delayed_work_sync(&dev_priv
->gpu_error
.hangcheck_work
);
4808 cancel_delayed_work_sync(&dev_priv
->mm
.retire_work
);
4809 flush_delayed_work(&dev_priv
->mm
.idle_work
);
4811 /* Assert that we sucessfully flushed all the work and
4812 * reset the GPU back to its idle, low power state.
4814 WARN_ON(dev_priv
->mm
.busy
);
4819 mutex_unlock(&dev
->struct_mutex
);
4823 void i915_gem_init_swizzling(struct drm_device
*dev
)
4825 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4827 if (INTEL_INFO(dev
)->gen
< 5 ||
4828 dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_NONE
)
4831 I915_WRITE(DISP_ARB_CTL
, I915_READ(DISP_ARB_CTL
) |
4832 DISP_TILE_SURFACE_SWIZZLING
);
4837 I915_WRITE(TILECTL
, I915_READ(TILECTL
) | TILECTL_SWZCTL
);
4839 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB
));
4840 else if (IS_GEN7(dev
))
4841 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB
));
4842 else if (IS_GEN8(dev
))
4843 I915_WRITE(GAMTARBMODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW
));
4848 static void init_unused_ring(struct drm_device
*dev
, u32 base
)
4850 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4852 I915_WRITE(RING_CTL(base
), 0);
4853 I915_WRITE(RING_HEAD(base
), 0);
4854 I915_WRITE(RING_TAIL(base
), 0);
4855 I915_WRITE(RING_START(base
), 0);
4858 static void init_unused_rings(struct drm_device
*dev
)
4861 init_unused_ring(dev
, PRB1_BASE
);
4862 init_unused_ring(dev
, SRB0_BASE
);
4863 init_unused_ring(dev
, SRB1_BASE
);
4864 init_unused_ring(dev
, SRB2_BASE
);
4865 init_unused_ring(dev
, SRB3_BASE
);
4866 } else if (IS_GEN2(dev
)) {
4867 init_unused_ring(dev
, SRB0_BASE
);
4868 init_unused_ring(dev
, SRB1_BASE
);
4869 } else if (IS_GEN3(dev
)) {
4870 init_unused_ring(dev
, PRB1_BASE
);
4871 init_unused_ring(dev
, PRB2_BASE
);
4875 int i915_gem_init_engines(struct drm_device
*dev
)
4877 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4880 ret
= intel_init_render_ring_buffer(dev
);
4885 ret
= intel_init_bsd_ring_buffer(dev
);
4887 goto cleanup_render_ring
;
4891 ret
= intel_init_blt_ring_buffer(dev
);
4893 goto cleanup_bsd_ring
;
4896 if (HAS_VEBOX(dev
)) {
4897 ret
= intel_init_vebox_ring_buffer(dev
);
4899 goto cleanup_blt_ring
;
4902 if (HAS_BSD2(dev
)) {
4903 ret
= intel_init_bsd2_ring_buffer(dev
);
4905 goto cleanup_vebox_ring
;
4911 intel_cleanup_engine(&dev_priv
->engine
[VECS
]);
4913 intel_cleanup_engine(&dev_priv
->engine
[BCS
]);
4915 intel_cleanup_engine(&dev_priv
->engine
[VCS
]);
4916 cleanup_render_ring
:
4917 intel_cleanup_engine(&dev_priv
->engine
[RCS
]);
4923 i915_gem_init_hw(struct drm_device
*dev
)
4925 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4926 struct intel_engine_cs
*engine
;
4929 /* Double layer security blanket, see i915_gem_init() */
4930 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
4932 if (HAS_EDRAM(dev
) && INTEL_GEN(dev_priv
) < 9)
4933 I915_WRITE(HSW_IDICR
, I915_READ(HSW_IDICR
) | IDIHASHMSK(0xf));
4935 if (IS_HASWELL(dev
))
4936 I915_WRITE(MI_PREDICATE_RESULT_2
, IS_HSW_GT3(dev
) ?
4937 LOWER_SLICE_ENABLED
: LOWER_SLICE_DISABLED
);
4939 if (HAS_PCH_NOP(dev
)) {
4940 if (IS_IVYBRIDGE(dev
)) {
4941 u32 temp
= I915_READ(GEN7_MSG_CTL
);
4942 temp
&= ~(WAIT_FOR_PCH_FLR_ACK
| WAIT_FOR_PCH_RESET_ACK
);
4943 I915_WRITE(GEN7_MSG_CTL
, temp
);
4944 } else if (INTEL_INFO(dev
)->gen
>= 7) {
4945 u32 temp
= I915_READ(HSW_NDE_RSTWRN_OPT
);
4946 temp
&= ~RESET_PCH_HANDSHAKE_ENABLE
;
4947 I915_WRITE(HSW_NDE_RSTWRN_OPT
, temp
);
4951 i915_gem_init_swizzling(dev
);
4954 * At least 830 can leave some of the unused rings
4955 * "active" (ie. head != tail) after resume which
4956 * will prevent c3 entry. Makes sure all unused rings
4959 init_unused_rings(dev
);
4961 BUG_ON(!dev_priv
->kernel_context
);
4963 ret
= i915_ppgtt_init_hw(dev
);
4965 DRM_ERROR("PPGTT enable HW failed %d\n", ret
);
4969 /* Need to do basic initialisation of all rings first: */
4970 for_each_engine(engine
, dev_priv
) {
4971 ret
= engine
->init_hw(engine
);
4976 intel_mocs_init_l3cc_table(dev
);
4978 /* We can't enable contexts until all firmware is loaded */
4979 ret
= intel_guc_setup(dev
);
4984 * Increment the next seqno by 0x100 so we have a visible break
4985 * on re-initialisation
4987 ret
= i915_gem_set_seqno(dev
, dev_priv
->next_seqno
+0x100);
4990 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
4994 int i915_gem_init(struct drm_device
*dev
)
4996 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4999 mutex_lock(&dev
->struct_mutex
);
5001 if (!i915
.enable_execlists
) {
5002 dev_priv
->gt
.execbuf_submit
= i915_gem_ringbuffer_submission
;
5003 dev_priv
->gt
.init_engines
= i915_gem_init_engines
;
5004 dev_priv
->gt
.cleanup_engine
= intel_cleanup_engine
;
5005 dev_priv
->gt
.stop_engine
= intel_stop_engine
;
5007 dev_priv
->gt
.execbuf_submit
= intel_execlists_submission
;
5008 dev_priv
->gt
.init_engines
= intel_logical_rings_init
;
5009 dev_priv
->gt
.cleanup_engine
= intel_logical_ring_cleanup
;
5010 dev_priv
->gt
.stop_engine
= intel_logical_ring_stop
;
5013 /* This is just a security blanket to placate dragons.
5014 * On some systems, we very sporadically observe that the first TLBs
5015 * used by the CS may be stale, despite us poking the TLB reset. If
5016 * we hold the forcewake during initialisation these problems
5017 * just magically go away.
5019 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
5021 i915_gem_init_userptr(dev_priv
);
5022 i915_gem_init_ggtt(dev
);
5024 ret
= i915_gem_context_init(dev
);
5028 ret
= dev_priv
->gt
.init_engines(dev
);
5032 ret
= i915_gem_init_hw(dev
);
5034 /* Allow ring initialisation to fail by marking the GPU as
5035 * wedged. But we only want to do this where the GPU is angry,
5036 * for all other failure, such as an allocation failure, bail.
5038 DRM_ERROR("Failed to initialize GPU, declaring it wedged\n");
5039 atomic_or(I915_WEDGED
, &dev_priv
->gpu_error
.reset_counter
);
5044 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
5045 mutex_unlock(&dev
->struct_mutex
);
5051 i915_gem_cleanup_engines(struct drm_device
*dev
)
5053 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5054 struct intel_engine_cs
*engine
;
5056 for_each_engine(engine
, dev_priv
)
5057 dev_priv
->gt
.cleanup_engine(engine
);
5061 init_engine_lists(struct intel_engine_cs
*engine
)
5063 INIT_LIST_HEAD(&engine
->active_list
);
5064 INIT_LIST_HEAD(&engine
->request_list
);
5068 i915_gem_load_init_fences(struct drm_i915_private
*dev_priv
)
5070 struct drm_device
*dev
= dev_priv
->dev
;
5072 if (INTEL_INFO(dev_priv
)->gen
>= 7 && !IS_VALLEYVIEW(dev_priv
) &&
5073 !IS_CHERRYVIEW(dev_priv
))
5074 dev_priv
->num_fence_regs
= 32;
5075 else if (INTEL_INFO(dev_priv
)->gen
>= 4 || IS_I945G(dev_priv
) ||
5076 IS_I945GM(dev_priv
) || IS_G33(dev_priv
))
5077 dev_priv
->num_fence_regs
= 16;
5079 dev_priv
->num_fence_regs
= 8;
5081 if (intel_vgpu_active(dev_priv
))
5082 dev_priv
->num_fence_regs
=
5083 I915_READ(vgtif_reg(avail_rs
.fence_num
));
5085 /* Initialize fence registers to zero */
5086 i915_gem_restore_fences(dev
);
5088 i915_gem_detect_bit_6_swizzle(dev
);
5092 i915_gem_load_init(struct drm_device
*dev
)
5094 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5098 kmem_cache_create("i915_gem_object",
5099 sizeof(struct drm_i915_gem_object
), 0,
5103 kmem_cache_create("i915_gem_vma",
5104 sizeof(struct i915_vma
), 0,
5107 dev_priv
->requests
=
5108 kmem_cache_create("i915_gem_request",
5109 sizeof(struct drm_i915_gem_request
), 0,
5113 INIT_LIST_HEAD(&dev_priv
->vm_list
);
5114 INIT_LIST_HEAD(&dev_priv
->context_list
);
5115 INIT_LIST_HEAD(&dev_priv
->mm
.unbound_list
);
5116 INIT_LIST_HEAD(&dev_priv
->mm
.bound_list
);
5117 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
5118 for (i
= 0; i
< I915_NUM_ENGINES
; i
++)
5119 init_engine_lists(&dev_priv
->engine
[i
]);
5120 for (i
= 0; i
< I915_MAX_NUM_FENCES
; i
++)
5121 INIT_LIST_HEAD(&dev_priv
->fence_regs
[i
].lru_list
);
5122 INIT_DELAYED_WORK(&dev_priv
->mm
.retire_work
,
5123 i915_gem_retire_work_handler
);
5124 INIT_DELAYED_WORK(&dev_priv
->mm
.idle_work
,
5125 i915_gem_idle_work_handler
);
5126 init_waitqueue_head(&dev_priv
->gpu_error
.reset_queue
);
5128 dev_priv
->relative_constants_mode
= I915_EXEC_CONSTANTS_REL_GENERAL
;
5131 * Set initial sequence number for requests.
5132 * Using this number allows the wraparound to happen early,
5133 * catching any obvious problems.
5135 dev_priv
->next_seqno
= ((u32
)~0 - 0x1100);
5136 dev_priv
->last_seqno
= ((u32
)~0 - 0x1101);
5138 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
5140 init_waitqueue_head(&dev_priv
->pending_flip_queue
);
5142 dev_priv
->mm
.interruptible
= true;
5144 mutex_init(&dev_priv
->fb_tracking
.lock
);
5147 void i915_gem_load_cleanup(struct drm_device
*dev
)
5149 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5151 kmem_cache_destroy(dev_priv
->requests
);
5152 kmem_cache_destroy(dev_priv
->vmas
);
5153 kmem_cache_destroy(dev_priv
->objects
);
5156 int i915_gem_freeze_late(struct drm_i915_private
*dev_priv
)
5158 struct drm_i915_gem_object
*obj
;
5160 /* Called just before we write the hibernation image.
5162 * We need to update the domain tracking to reflect that the CPU
5163 * will be accessing all the pages to create and restore from the
5164 * hibernation, and so upon restoration those pages will be in the
5167 * To make sure the hibernation image contains the latest state,
5168 * we update that state just before writing out the image.
5171 list_for_each_entry(obj
, &dev_priv
->mm
.unbound_list
, global_list
) {
5172 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
5173 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
5176 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
5177 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
5178 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
5184 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
)
5186 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
5188 /* Clean up our request list when the client is going away, so that
5189 * later retire_requests won't dereference our soon-to-be-gone
5192 spin_lock(&file_priv
->mm
.lock
);
5193 while (!list_empty(&file_priv
->mm
.request_list
)) {
5194 struct drm_i915_gem_request
*request
;
5196 request
= list_first_entry(&file_priv
->mm
.request_list
,
5197 struct drm_i915_gem_request
,
5199 list_del(&request
->client_list
);
5200 request
->file_priv
= NULL
;
5202 spin_unlock(&file_priv
->mm
.lock
);
5204 if (!list_empty(&file_priv
->rps
.link
)) {
5205 spin_lock(&to_i915(dev
)->rps
.client_lock
);
5206 list_del(&file_priv
->rps
.link
);
5207 spin_unlock(&to_i915(dev
)->rps
.client_lock
);
5211 int i915_gem_open(struct drm_device
*dev
, struct drm_file
*file
)
5213 struct drm_i915_file_private
*file_priv
;
5216 DRM_DEBUG_DRIVER("\n");
5218 file_priv
= kzalloc(sizeof(*file_priv
), GFP_KERNEL
);
5222 file
->driver_priv
= file_priv
;
5223 file_priv
->dev_priv
= dev
->dev_private
;
5224 file_priv
->file
= file
;
5225 INIT_LIST_HEAD(&file_priv
->rps
.link
);
5227 spin_lock_init(&file_priv
->mm
.lock
);
5228 INIT_LIST_HEAD(&file_priv
->mm
.request_list
);
5230 file_priv
->bsd_ring
= -1;
5232 ret
= i915_gem_context_open(dev
, file
);
5240 * i915_gem_track_fb - update frontbuffer tracking
5241 * @old: current GEM buffer for the frontbuffer slots
5242 * @new: new GEM buffer for the frontbuffer slots
5243 * @frontbuffer_bits: bitmask of frontbuffer slots
5245 * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them
5246 * from @old and setting them in @new. Both @old and @new can be NULL.
5248 void i915_gem_track_fb(struct drm_i915_gem_object
*old
,
5249 struct drm_i915_gem_object
*new,
5250 unsigned frontbuffer_bits
)
5253 WARN_ON(!mutex_is_locked(&old
->base
.dev
->struct_mutex
));
5254 WARN_ON(!(old
->frontbuffer_bits
& frontbuffer_bits
));
5255 old
->frontbuffer_bits
&= ~frontbuffer_bits
;
5259 WARN_ON(!mutex_is_locked(&new->base
.dev
->struct_mutex
));
5260 WARN_ON(new->frontbuffer_bits
& frontbuffer_bits
);
5261 new->frontbuffer_bits
|= frontbuffer_bits
;
5265 /* All the new VM stuff */
5266 u64
i915_gem_obj_offset(struct drm_i915_gem_object
*o
,
5267 struct i915_address_space
*vm
)
5269 struct drm_i915_private
*dev_priv
= o
->base
.dev
->dev_private
;
5270 struct i915_vma
*vma
;
5272 WARN_ON(vm
== &dev_priv
->mm
.aliasing_ppgtt
->base
);
5274 list_for_each_entry(vma
, &o
->vma_list
, obj_link
) {
5276 vma
->ggtt_view
.type
!= I915_GGTT_VIEW_NORMAL
)
5279 return vma
->node
.start
;
5282 WARN(1, "%s vma for this object not found.\n",
5283 i915_is_ggtt(vm
) ? "global" : "ppgtt");
5287 u64
i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object
*o
,
5288 const struct i915_ggtt_view
*view
)
5290 struct i915_vma
*vma
;
5292 list_for_each_entry(vma
, &o
->vma_list
, obj_link
)
5293 if (vma
->is_ggtt
&& i915_ggtt_view_equal(&vma
->ggtt_view
, view
))
5294 return vma
->node
.start
;
5296 WARN(1, "global vma for this object not found. (view=%u)\n", view
->type
);
5300 bool i915_gem_obj_bound(struct drm_i915_gem_object
*o
,
5301 struct i915_address_space
*vm
)
5303 struct i915_vma
*vma
;
5305 list_for_each_entry(vma
, &o
->vma_list
, obj_link
) {
5307 vma
->ggtt_view
.type
!= I915_GGTT_VIEW_NORMAL
)
5309 if (vma
->vm
== vm
&& drm_mm_node_allocated(&vma
->node
))
5316 bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object
*o
,
5317 const struct i915_ggtt_view
*view
)
5319 struct i915_vma
*vma
;
5321 list_for_each_entry(vma
, &o
->vma_list
, obj_link
)
5323 i915_ggtt_view_equal(&vma
->ggtt_view
, view
) &&
5324 drm_mm_node_allocated(&vma
->node
))
5330 bool i915_gem_obj_bound_any(struct drm_i915_gem_object
*o
)
5332 struct i915_vma
*vma
;
5334 list_for_each_entry(vma
, &o
->vma_list
, obj_link
)
5335 if (drm_mm_node_allocated(&vma
->node
))
5341 unsigned long i915_gem_obj_ggtt_size(struct drm_i915_gem_object
*o
)
5343 struct i915_vma
*vma
;
5345 GEM_BUG_ON(list_empty(&o
->vma_list
));
5347 list_for_each_entry(vma
, &o
->vma_list
, obj_link
) {
5349 vma
->ggtt_view
.type
== I915_GGTT_VIEW_NORMAL
)
5350 return vma
->node
.size
;
5356 bool i915_gem_obj_is_pinned(struct drm_i915_gem_object
*obj
)
5358 struct i915_vma
*vma
;
5359 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
)
5360 if (vma
->pin_count
> 0)
5366 /* Like i915_gem_object_get_page(), but mark the returned page dirty */
5368 i915_gem_object_get_dirty_page(struct drm_i915_gem_object
*obj
, int n
)
5372 /* Only default objects have per-page dirty tracking */
5373 if (WARN_ON((obj
->ops
->flags
& I915_GEM_OBJECT_HAS_STRUCT_PAGE
) == 0))
5376 page
= i915_gem_object_get_page(obj
, n
);
5377 set_page_dirty(page
);
5381 /* Allocate a new GEM object and fill it with the supplied data */
5382 struct drm_i915_gem_object
*
5383 i915_gem_object_create_from_data(struct drm_device
*dev
,
5384 const void *data
, size_t size
)
5386 struct drm_i915_gem_object
*obj
;
5387 struct sg_table
*sg
;
5391 obj
= i915_gem_object_create(dev
, round_up(size
, PAGE_SIZE
));
5395 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
5399 ret
= i915_gem_object_get_pages(obj
);
5403 i915_gem_object_pin_pages(obj
);
5405 bytes
= sg_copy_from_buffer(sg
->sgl
, sg
->nents
, (void *)data
, size
);
5406 obj
->dirty
= 1; /* Backing store is now out of date */
5407 i915_gem_object_unpin_pages(obj
);
5409 if (WARN_ON(bytes
!= size
)) {
5410 DRM_ERROR("Incomplete copy, wrote %zu of %zu", bytes
, size
);
5418 drm_gem_object_unreference(&obj
->base
);
5419 return ERR_PTR(ret
);