2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/i915_drm.h>
31 #include "i915_trace.h"
32 #include "intel_drv.h"
33 #include <linux/shmem_fs.h>
34 #include <linux/slab.h>
35 #include <linux/swap.h>
36 #include <linux/pci.h>
37 #include <linux/dma-buf.h>
39 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
);
40 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
);
41 static __must_check
int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object
*obj
,
43 bool map_and_fenceable
,
45 static int i915_gem_phys_pwrite(struct drm_device
*dev
,
46 struct drm_i915_gem_object
*obj
,
47 struct drm_i915_gem_pwrite
*args
,
48 struct drm_file
*file
);
50 static void i915_gem_write_fence(struct drm_device
*dev
, int reg
,
51 struct drm_i915_gem_object
*obj
);
52 static void i915_gem_object_update_fence(struct drm_i915_gem_object
*obj
,
53 struct drm_i915_fence_reg
*fence
,
56 static int i915_gem_inactive_shrink(struct shrinker
*shrinker
,
57 struct shrink_control
*sc
);
58 static long i915_gem_purge(struct drm_i915_private
*dev_priv
, long target
);
59 static void i915_gem_shrink_all(struct drm_i915_private
*dev_priv
);
60 static void i915_gem_object_truncate(struct drm_i915_gem_object
*obj
);
62 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object
*obj
)
65 i915_gem_release_mmap(obj
);
67 /* As we do not have an associated fence register, we will force
68 * a tiling change if we ever need to acquire one.
70 obj
->fence_dirty
= false;
71 obj
->fence_reg
= I915_FENCE_REG_NONE
;
74 /* some bookkeeping */
75 static void i915_gem_info_add_obj(struct drm_i915_private
*dev_priv
,
78 dev_priv
->mm
.object_count
++;
79 dev_priv
->mm
.object_memory
+= size
;
82 static void i915_gem_info_remove_obj(struct drm_i915_private
*dev_priv
,
85 dev_priv
->mm
.object_count
--;
86 dev_priv
->mm
.object_memory
-= size
;
90 i915_gem_wait_for_error(struct i915_gpu_error
*error
)
94 #define EXIT_COND (!i915_reset_in_progress(error))
98 /* GPU is already declared terminally dead, give up. */
99 if (i915_terminally_wedged(error
))
103 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
104 * userspace. If it takes that long something really bad is going on and
105 * we should simply try to bail out and fail as gracefully as possible.
107 ret
= wait_event_interruptible_timeout(error
->reset_queue
,
111 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
113 } else if (ret
< 0) {
121 int i915_mutex_lock_interruptible(struct drm_device
*dev
)
123 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
126 ret
= i915_gem_wait_for_error(&dev_priv
->gpu_error
);
130 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
134 WARN_ON(i915_verify_lists(dev
));
139 i915_gem_object_is_inactive(struct drm_i915_gem_object
*obj
)
141 return obj
->gtt_space
&& !obj
->active
;
145 i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
146 struct drm_file
*file
)
148 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
149 struct drm_i915_gem_init
*args
= data
;
151 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
154 if (args
->gtt_start
>= args
->gtt_end
||
155 (args
->gtt_end
| args
->gtt_start
) & (PAGE_SIZE
- 1))
158 /* GEM with user mode setting was never supported on ilk and later. */
159 if (INTEL_INFO(dev
)->gen
>= 5)
162 mutex_lock(&dev
->struct_mutex
);
163 i915_gem_setup_global_gtt(dev
, args
->gtt_start
, args
->gtt_end
,
165 dev_priv
->gtt
.mappable_end
= args
->gtt_end
;
166 mutex_unlock(&dev
->struct_mutex
);
172 i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
173 struct drm_file
*file
)
175 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
176 struct drm_i915_gem_get_aperture
*args
= data
;
177 struct drm_i915_gem_object
*obj
;
181 mutex_lock(&dev
->struct_mutex
);
182 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, gtt_list
)
184 pinned
+= obj
->gtt_space
->size
;
185 mutex_unlock(&dev
->struct_mutex
);
187 args
->aper_size
= dev_priv
->gtt
.total
;
188 args
->aper_available_size
= args
->aper_size
- pinned
;
193 void *i915_gem_object_alloc(struct drm_device
*dev
)
195 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
196 return kmem_cache_alloc(dev_priv
->slab
, GFP_KERNEL
| __GFP_ZERO
);
199 void i915_gem_object_free(struct drm_i915_gem_object
*obj
)
201 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
202 kmem_cache_free(dev_priv
->slab
, obj
);
206 i915_gem_create(struct drm_file
*file
,
207 struct drm_device
*dev
,
211 struct drm_i915_gem_object
*obj
;
215 size
= roundup(size
, PAGE_SIZE
);
219 /* Allocate the new object */
220 obj
= i915_gem_alloc_object(dev
, size
);
224 ret
= drm_gem_handle_create(file
, &obj
->base
, &handle
);
226 drm_gem_object_release(&obj
->base
);
227 i915_gem_info_remove_obj(dev
->dev_private
, obj
->base
.size
);
228 i915_gem_object_free(obj
);
232 /* drop reference from allocate - handle holds it now */
233 drm_gem_object_unreference(&obj
->base
);
234 trace_i915_gem_object_create(obj
);
241 i915_gem_dumb_create(struct drm_file
*file
,
242 struct drm_device
*dev
,
243 struct drm_mode_create_dumb
*args
)
245 /* have to work out size/pitch and return them */
246 args
->pitch
= ALIGN(args
->width
* ((args
->bpp
+ 7) / 8), 64);
247 args
->size
= args
->pitch
* args
->height
;
248 return i915_gem_create(file
, dev
,
249 args
->size
, &args
->handle
);
252 int i915_gem_dumb_destroy(struct drm_file
*file
,
253 struct drm_device
*dev
,
256 return drm_gem_handle_delete(file
, handle
);
260 * Creates a new mm object and returns a handle to it.
263 i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
264 struct drm_file
*file
)
266 struct drm_i915_gem_create
*args
= data
;
268 return i915_gem_create(file
, dev
,
269 args
->size
, &args
->handle
);
273 __copy_to_user_swizzled(char __user
*cpu_vaddr
,
274 const char *gpu_vaddr
, int gpu_offset
,
277 int ret
, cpu_offset
= 0;
280 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
281 int this_length
= min(cacheline_end
- gpu_offset
, length
);
282 int swizzled_gpu_offset
= gpu_offset
^ 64;
284 ret
= __copy_to_user(cpu_vaddr
+ cpu_offset
,
285 gpu_vaddr
+ swizzled_gpu_offset
,
290 cpu_offset
+= this_length
;
291 gpu_offset
+= this_length
;
292 length
-= this_length
;
299 __copy_from_user_swizzled(char *gpu_vaddr
, int gpu_offset
,
300 const char __user
*cpu_vaddr
,
303 int ret
, cpu_offset
= 0;
306 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
307 int this_length
= min(cacheline_end
- gpu_offset
, length
);
308 int swizzled_gpu_offset
= gpu_offset
^ 64;
310 ret
= __copy_from_user(gpu_vaddr
+ swizzled_gpu_offset
,
311 cpu_vaddr
+ cpu_offset
,
316 cpu_offset
+= this_length
;
317 gpu_offset
+= this_length
;
318 length
-= this_length
;
324 /* Per-page copy function for the shmem pread fastpath.
325 * Flushes invalid cachelines before reading the target if
326 * needs_clflush is set. */
328 shmem_pread_fast(struct page
*page
, int shmem_page_offset
, int page_length
,
329 char __user
*user_data
,
330 bool page_do_bit17_swizzling
, bool needs_clflush
)
335 if (unlikely(page_do_bit17_swizzling
))
338 vaddr
= kmap_atomic(page
);
340 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
342 ret
= __copy_to_user_inatomic(user_data
,
343 vaddr
+ shmem_page_offset
,
345 kunmap_atomic(vaddr
);
347 return ret
? -EFAULT
: 0;
351 shmem_clflush_swizzled_range(char *addr
, unsigned long length
,
354 if (unlikely(swizzled
)) {
355 unsigned long start
= (unsigned long) addr
;
356 unsigned long end
= (unsigned long) addr
+ length
;
358 /* For swizzling simply ensure that we always flush both
359 * channels. Lame, but simple and it works. Swizzled
360 * pwrite/pread is far from a hotpath - current userspace
361 * doesn't use it at all. */
362 start
= round_down(start
, 128);
363 end
= round_up(end
, 128);
365 drm_clflush_virt_range((void *)start
, end
- start
);
367 drm_clflush_virt_range(addr
, length
);
372 /* Only difference to the fast-path function is that this can handle bit17
373 * and uses non-atomic copy and kmap functions. */
375 shmem_pread_slow(struct page
*page
, int shmem_page_offset
, int page_length
,
376 char __user
*user_data
,
377 bool page_do_bit17_swizzling
, bool needs_clflush
)
384 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
386 page_do_bit17_swizzling
);
388 if (page_do_bit17_swizzling
)
389 ret
= __copy_to_user_swizzled(user_data
,
390 vaddr
, shmem_page_offset
,
393 ret
= __copy_to_user(user_data
,
394 vaddr
+ shmem_page_offset
,
398 return ret
? - EFAULT
: 0;
402 i915_gem_shmem_pread(struct drm_device
*dev
,
403 struct drm_i915_gem_object
*obj
,
404 struct drm_i915_gem_pread
*args
,
405 struct drm_file
*file
)
407 char __user
*user_data
;
410 int shmem_page_offset
, page_length
, ret
= 0;
411 int obj_do_bit17_swizzling
, page_do_bit17_swizzling
;
413 int needs_clflush
= 0;
414 struct scatterlist
*sg
;
417 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
420 obj_do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
422 if (!(obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
)) {
423 /* If we're not in the cpu read domain, set ourself into the gtt
424 * read domain and manually flush cachelines (if required). This
425 * optimizes for the case when the gpu will dirty the data
426 * anyway again before the next pread happens. */
427 if (obj
->cache_level
== I915_CACHE_NONE
)
429 if (obj
->gtt_space
) {
430 ret
= i915_gem_object_set_to_gtt_domain(obj
, false);
436 ret
= i915_gem_object_get_pages(obj
);
440 i915_gem_object_pin_pages(obj
);
442 offset
= args
->offset
;
444 for_each_sg(obj
->pages
->sgl
, sg
, obj
->pages
->nents
, i
) {
447 if (i
< offset
>> PAGE_SHIFT
)
453 /* Operation in this page
455 * shmem_page_offset = offset within page in shmem file
456 * page_length = bytes to copy for this page
458 shmem_page_offset
= offset_in_page(offset
);
459 page_length
= remain
;
460 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
461 page_length
= PAGE_SIZE
- shmem_page_offset
;
464 page_do_bit17_swizzling
= obj_do_bit17_swizzling
&&
465 (page_to_phys(page
) & (1 << 17)) != 0;
467 ret
= shmem_pread_fast(page
, shmem_page_offset
, page_length
,
468 user_data
, page_do_bit17_swizzling
,
473 mutex_unlock(&dev
->struct_mutex
);
476 ret
= fault_in_multipages_writeable(user_data
, remain
);
477 /* Userspace is tricking us, but we've already clobbered
478 * its pages with the prefault and promised to write the
479 * data up to the first fault. Hence ignore any errors
480 * and just continue. */
485 ret
= shmem_pread_slow(page
, shmem_page_offset
, page_length
,
486 user_data
, page_do_bit17_swizzling
,
489 mutex_lock(&dev
->struct_mutex
);
492 mark_page_accessed(page
);
497 remain
-= page_length
;
498 user_data
+= page_length
;
499 offset
+= page_length
;
503 i915_gem_object_unpin_pages(obj
);
509 * Reads data from the object referenced by handle.
511 * On error, the contents of *data are undefined.
514 i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
515 struct drm_file
*file
)
517 struct drm_i915_gem_pread
*args
= data
;
518 struct drm_i915_gem_object
*obj
;
524 if (!access_ok(VERIFY_WRITE
,
525 (char __user
*)(uintptr_t)args
->data_ptr
,
529 ret
= i915_mutex_lock_interruptible(dev
);
533 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
534 if (&obj
->base
== NULL
) {
539 /* Bounds check source. */
540 if (args
->offset
> obj
->base
.size
||
541 args
->size
> obj
->base
.size
- args
->offset
) {
546 /* prime objects have no backing filp to GEM pread/pwrite
549 if (!obj
->base
.filp
) {
554 trace_i915_gem_object_pread(obj
, args
->offset
, args
->size
);
556 ret
= i915_gem_shmem_pread(dev
, obj
, args
, file
);
559 drm_gem_object_unreference(&obj
->base
);
561 mutex_unlock(&dev
->struct_mutex
);
565 /* This is the fast write path which cannot handle
566 * page faults in the source data
570 fast_user_write(struct io_mapping
*mapping
,
571 loff_t page_base
, int page_offset
,
572 char __user
*user_data
,
575 void __iomem
*vaddr_atomic
;
577 unsigned long unwritten
;
579 vaddr_atomic
= io_mapping_map_atomic_wc(mapping
, page_base
);
580 /* We can use the cpu mem copy function because this is X86. */
581 vaddr
= (void __force
*)vaddr_atomic
+ page_offset
;
582 unwritten
= __copy_from_user_inatomic_nocache(vaddr
,
584 io_mapping_unmap_atomic(vaddr_atomic
);
589 * This is the fast pwrite path, where we copy the data directly from the
590 * user into the GTT, uncached.
593 i915_gem_gtt_pwrite_fast(struct drm_device
*dev
,
594 struct drm_i915_gem_object
*obj
,
595 struct drm_i915_gem_pwrite
*args
,
596 struct drm_file
*file
)
598 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
600 loff_t offset
, page_base
;
601 char __user
*user_data
;
602 int page_offset
, page_length
, ret
;
604 ret
= i915_gem_object_pin(obj
, 0, true, true);
608 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
612 ret
= i915_gem_object_put_fence(obj
);
616 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
619 offset
= obj
->gtt_offset
+ args
->offset
;
622 /* Operation in this page
624 * page_base = page offset within aperture
625 * page_offset = offset within page
626 * page_length = bytes to copy for this page
628 page_base
= offset
& PAGE_MASK
;
629 page_offset
= offset_in_page(offset
);
630 page_length
= remain
;
631 if ((page_offset
+ remain
) > PAGE_SIZE
)
632 page_length
= PAGE_SIZE
- page_offset
;
634 /* If we get a fault while copying data, then (presumably) our
635 * source page isn't available. Return the error and we'll
636 * retry in the slow path.
638 if (fast_user_write(dev_priv
->gtt
.mappable
, page_base
,
639 page_offset
, user_data
, page_length
)) {
644 remain
-= page_length
;
645 user_data
+= page_length
;
646 offset
+= page_length
;
650 i915_gem_object_unpin(obj
);
655 /* Per-page copy function for the shmem pwrite fastpath.
656 * Flushes invalid cachelines before writing to the target if
657 * needs_clflush_before is set and flushes out any written cachelines after
658 * writing if needs_clflush is set. */
660 shmem_pwrite_fast(struct page
*page
, int shmem_page_offset
, int page_length
,
661 char __user
*user_data
,
662 bool page_do_bit17_swizzling
,
663 bool needs_clflush_before
,
664 bool needs_clflush_after
)
669 if (unlikely(page_do_bit17_swizzling
))
672 vaddr
= kmap_atomic(page
);
673 if (needs_clflush_before
)
674 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
676 ret
= __copy_from_user_inatomic_nocache(vaddr
+ shmem_page_offset
,
679 if (needs_clflush_after
)
680 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
682 kunmap_atomic(vaddr
);
684 return ret
? -EFAULT
: 0;
687 /* Only difference to the fast-path function is that this can handle bit17
688 * and uses non-atomic copy and kmap functions. */
690 shmem_pwrite_slow(struct page
*page
, int shmem_page_offset
, int page_length
,
691 char __user
*user_data
,
692 bool page_do_bit17_swizzling
,
693 bool needs_clflush_before
,
694 bool needs_clflush_after
)
700 if (unlikely(needs_clflush_before
|| page_do_bit17_swizzling
))
701 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
703 page_do_bit17_swizzling
);
704 if (page_do_bit17_swizzling
)
705 ret
= __copy_from_user_swizzled(vaddr
, shmem_page_offset
,
709 ret
= __copy_from_user(vaddr
+ shmem_page_offset
,
712 if (needs_clflush_after
)
713 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
715 page_do_bit17_swizzling
);
718 return ret
? -EFAULT
: 0;
722 i915_gem_shmem_pwrite(struct drm_device
*dev
,
723 struct drm_i915_gem_object
*obj
,
724 struct drm_i915_gem_pwrite
*args
,
725 struct drm_file
*file
)
729 char __user
*user_data
;
730 int shmem_page_offset
, page_length
, ret
= 0;
731 int obj_do_bit17_swizzling
, page_do_bit17_swizzling
;
732 int hit_slowpath
= 0;
733 int needs_clflush_after
= 0;
734 int needs_clflush_before
= 0;
736 struct scatterlist
*sg
;
738 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
741 obj_do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
743 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
744 /* If we're not in the cpu write domain, set ourself into the gtt
745 * write domain and manually flush cachelines (if required). This
746 * optimizes for the case when the gpu will use the data
747 * right away and we therefore have to clflush anyway. */
748 if (obj
->cache_level
== I915_CACHE_NONE
)
749 needs_clflush_after
= 1;
750 if (obj
->gtt_space
) {
751 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
756 /* Same trick applies for invalidate partially written cachelines before
758 if (!(obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
)
759 && obj
->cache_level
== I915_CACHE_NONE
)
760 needs_clflush_before
= 1;
762 ret
= i915_gem_object_get_pages(obj
);
766 i915_gem_object_pin_pages(obj
);
768 offset
= args
->offset
;
771 for_each_sg(obj
->pages
->sgl
, sg
, obj
->pages
->nents
, i
) {
773 int partial_cacheline_write
;
775 if (i
< offset
>> PAGE_SHIFT
)
781 /* Operation in this page
783 * shmem_page_offset = offset within page in shmem file
784 * page_length = bytes to copy for this page
786 shmem_page_offset
= offset_in_page(offset
);
788 page_length
= remain
;
789 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
790 page_length
= PAGE_SIZE
- shmem_page_offset
;
792 /* If we don't overwrite a cacheline completely we need to be
793 * careful to have up-to-date data by first clflushing. Don't
794 * overcomplicate things and flush the entire patch. */
795 partial_cacheline_write
= needs_clflush_before
&&
796 ((shmem_page_offset
| page_length
)
797 & (boot_cpu_data
.x86_clflush_size
- 1));
800 page_do_bit17_swizzling
= obj_do_bit17_swizzling
&&
801 (page_to_phys(page
) & (1 << 17)) != 0;
803 ret
= shmem_pwrite_fast(page
, shmem_page_offset
, page_length
,
804 user_data
, page_do_bit17_swizzling
,
805 partial_cacheline_write
,
806 needs_clflush_after
);
811 mutex_unlock(&dev
->struct_mutex
);
812 ret
= shmem_pwrite_slow(page
, shmem_page_offset
, page_length
,
813 user_data
, page_do_bit17_swizzling
,
814 partial_cacheline_write
,
815 needs_clflush_after
);
817 mutex_lock(&dev
->struct_mutex
);
820 set_page_dirty(page
);
821 mark_page_accessed(page
);
826 remain
-= page_length
;
827 user_data
+= page_length
;
828 offset
+= page_length
;
832 i915_gem_object_unpin_pages(obj
);
836 * Fixup: Flush cpu caches in case we didn't flush the dirty
837 * cachelines in-line while writing and the object moved
838 * out of the cpu write domain while we've dropped the lock.
840 if (!needs_clflush_after
&&
841 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
842 i915_gem_clflush_object(obj
);
843 i915_gem_chipset_flush(dev
);
847 if (needs_clflush_after
)
848 i915_gem_chipset_flush(dev
);
854 * Writes data to the object referenced by handle.
856 * On error, the contents of the buffer that were to be modified are undefined.
859 i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
860 struct drm_file
*file
)
862 struct drm_i915_gem_pwrite
*args
= data
;
863 struct drm_i915_gem_object
*obj
;
869 if (!access_ok(VERIFY_READ
,
870 (char __user
*)(uintptr_t)args
->data_ptr
,
874 ret
= fault_in_multipages_readable((char __user
*)(uintptr_t)args
->data_ptr
,
879 ret
= i915_mutex_lock_interruptible(dev
);
883 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
884 if (&obj
->base
== NULL
) {
889 /* Bounds check destination. */
890 if (args
->offset
> obj
->base
.size
||
891 args
->size
> obj
->base
.size
- args
->offset
) {
896 /* prime objects have no backing filp to GEM pread/pwrite
899 if (!obj
->base
.filp
) {
904 trace_i915_gem_object_pwrite(obj
, args
->offset
, args
->size
);
907 /* We can only do the GTT pwrite on untiled buffers, as otherwise
908 * it would end up going through the fenced access, and we'll get
909 * different detiling behavior between reading and writing.
910 * pread/pwrite currently are reading and writing from the CPU
911 * perspective, requiring manual detiling by the client.
914 ret
= i915_gem_phys_pwrite(dev
, obj
, args
, file
);
918 if (obj
->cache_level
== I915_CACHE_NONE
&&
919 obj
->tiling_mode
== I915_TILING_NONE
&&
920 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
921 ret
= i915_gem_gtt_pwrite_fast(dev
, obj
, args
, file
);
922 /* Note that the gtt paths might fail with non-page-backed user
923 * pointers (e.g. gtt mappings when moving data between
924 * textures). Fallback to the shmem path in that case. */
927 if (ret
== -EFAULT
|| ret
== -ENOSPC
)
928 ret
= i915_gem_shmem_pwrite(dev
, obj
, args
, file
);
931 drm_gem_object_unreference(&obj
->base
);
933 mutex_unlock(&dev
->struct_mutex
);
938 i915_gem_check_wedge(struct i915_gpu_error
*error
,
941 if (i915_reset_in_progress(error
)) {
942 /* Non-interruptible callers can't handle -EAGAIN, hence return
943 * -EIO unconditionally for these. */
947 /* Recovery complete, but the reset failed ... */
948 if (i915_terminally_wedged(error
))
958 * Compare seqno against outstanding lazy request. Emit a request if they are
962 i915_gem_check_olr(struct intel_ring_buffer
*ring
, u32 seqno
)
966 BUG_ON(!mutex_is_locked(&ring
->dev
->struct_mutex
));
969 if (seqno
== ring
->outstanding_lazy_request
)
970 ret
= i915_add_request(ring
, NULL
, NULL
);
976 * __wait_seqno - wait until execution of seqno has finished
977 * @ring: the ring expected to report seqno
979 * @interruptible: do an interruptible wait (normally yes)
980 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
982 * Returns 0 if the seqno was found within the alloted time. Else returns the
983 * errno with remaining time filled in timeout argument.
985 static int __wait_seqno(struct intel_ring_buffer
*ring
, u32 seqno
,
986 bool interruptible
, struct timespec
*timeout
)
988 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
989 struct timespec before
, now
, wait_time
={1,0};
990 unsigned long timeout_jiffies
;
992 bool wait_forever
= true;
995 if (i915_seqno_passed(ring
->get_seqno(ring
, true), seqno
))
998 trace_i915_gem_request_wait_begin(ring
, seqno
);
1000 if (timeout
!= NULL
) {
1001 wait_time
= *timeout
;
1002 wait_forever
= false;
1005 timeout_jiffies
= timespec_to_jiffies(&wait_time
);
1007 if (WARN_ON(!ring
->irq_get(ring
)))
1010 /* Record current time in case interrupted by signal, or wedged * */
1011 getrawmonotonic(&before
);
1014 (i915_seqno_passed(ring->get_seqno(ring, false), seqno) || \
1015 i915_reset_in_progress(&dev_priv->gpu_error))
1018 end
= wait_event_interruptible_timeout(ring
->irq_queue
,
1022 end
= wait_event_timeout(ring
->irq_queue
, EXIT_COND
,
1025 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, interruptible
);
1028 } while (end
== 0 && wait_forever
);
1030 getrawmonotonic(&now
);
1032 ring
->irq_put(ring
);
1033 trace_i915_gem_request_wait_end(ring
, seqno
);
1037 struct timespec sleep_time
= timespec_sub(now
, before
);
1038 *timeout
= timespec_sub(*timeout
, sleep_time
);
1043 case -EAGAIN
: /* Wedged */
1044 case -ERESTARTSYS
: /* Signal */
1046 case 0: /* Timeout */
1048 set_normalized_timespec(timeout
, 0, 0);
1050 default: /* Completed */
1051 WARN_ON(end
< 0); /* We're not aware of other errors */
1057 * Waits for a sequence number to be signaled, and cleans up the
1058 * request and object lists appropriately for that event.
1061 i915_wait_seqno(struct intel_ring_buffer
*ring
, uint32_t seqno
)
1063 struct drm_device
*dev
= ring
->dev
;
1064 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1065 bool interruptible
= dev_priv
->mm
.interruptible
;
1068 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
1071 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, interruptible
);
1075 ret
= i915_gem_check_olr(ring
, seqno
);
1079 return __wait_seqno(ring
, seqno
, interruptible
, NULL
);
1083 * Ensures that all rendering to the object has completed and the object is
1084 * safe to unbind from the GTT or access from the CPU.
1086 static __must_check
int
1087 i915_gem_object_wait_rendering(struct drm_i915_gem_object
*obj
,
1090 struct intel_ring_buffer
*ring
= obj
->ring
;
1094 seqno
= readonly
? obj
->last_write_seqno
: obj
->last_read_seqno
;
1098 ret
= i915_wait_seqno(ring
, seqno
);
1102 i915_gem_retire_requests_ring(ring
);
1104 /* Manually manage the write flush as we may have not yet
1105 * retired the buffer.
1107 if (obj
->last_write_seqno
&&
1108 i915_seqno_passed(seqno
, obj
->last_write_seqno
)) {
1109 obj
->last_write_seqno
= 0;
1110 obj
->base
.write_domain
&= ~I915_GEM_GPU_DOMAINS
;
1116 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1117 * as the object state may change during this call.
1119 static __must_check
int
1120 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object
*obj
,
1123 struct drm_device
*dev
= obj
->base
.dev
;
1124 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1125 struct intel_ring_buffer
*ring
= obj
->ring
;
1129 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
1130 BUG_ON(!dev_priv
->mm
.interruptible
);
1132 seqno
= readonly
? obj
->last_write_seqno
: obj
->last_read_seqno
;
1136 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, true);
1140 ret
= i915_gem_check_olr(ring
, seqno
);
1144 mutex_unlock(&dev
->struct_mutex
);
1145 ret
= __wait_seqno(ring
, seqno
, true, NULL
);
1146 mutex_lock(&dev
->struct_mutex
);
1148 i915_gem_retire_requests_ring(ring
);
1150 /* Manually manage the write flush as we may have not yet
1151 * retired the buffer.
1153 if (obj
->last_write_seqno
&&
1154 i915_seqno_passed(seqno
, obj
->last_write_seqno
)) {
1155 obj
->last_write_seqno
= 0;
1156 obj
->base
.write_domain
&= ~I915_GEM_GPU_DOMAINS
;
1163 * Called when user space prepares to use an object with the CPU, either
1164 * through the mmap ioctl's mapping or a GTT mapping.
1167 i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
1168 struct drm_file
*file
)
1170 struct drm_i915_gem_set_domain
*args
= data
;
1171 struct drm_i915_gem_object
*obj
;
1172 uint32_t read_domains
= args
->read_domains
;
1173 uint32_t write_domain
= args
->write_domain
;
1176 /* Only handle setting domains to types used by the CPU. */
1177 if (write_domain
& I915_GEM_GPU_DOMAINS
)
1180 if (read_domains
& I915_GEM_GPU_DOMAINS
)
1183 /* Having something in the write domain implies it's in the read
1184 * domain, and only that read domain. Enforce that in the request.
1186 if (write_domain
!= 0 && read_domains
!= write_domain
)
1189 ret
= i915_mutex_lock_interruptible(dev
);
1193 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1194 if (&obj
->base
== NULL
) {
1199 /* Try to flush the object off the GPU without holding the lock.
1200 * We will repeat the flush holding the lock in the normal manner
1201 * to catch cases where we are gazumped.
1203 ret
= i915_gem_object_wait_rendering__nonblocking(obj
, !write_domain
);
1207 if (read_domains
& I915_GEM_DOMAIN_GTT
) {
1208 ret
= i915_gem_object_set_to_gtt_domain(obj
, write_domain
!= 0);
1210 /* Silently promote "you're not bound, there was nothing to do"
1211 * to success, since the client was just asking us to
1212 * make sure everything was done.
1217 ret
= i915_gem_object_set_to_cpu_domain(obj
, write_domain
!= 0);
1221 drm_gem_object_unreference(&obj
->base
);
1223 mutex_unlock(&dev
->struct_mutex
);
1228 * Called when user space has done writes to this buffer
1231 i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1232 struct drm_file
*file
)
1234 struct drm_i915_gem_sw_finish
*args
= data
;
1235 struct drm_i915_gem_object
*obj
;
1238 ret
= i915_mutex_lock_interruptible(dev
);
1242 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1243 if (&obj
->base
== NULL
) {
1248 /* Pinned buffers may be scanout, so flush the cache */
1250 i915_gem_object_flush_cpu_write_domain(obj
);
1252 drm_gem_object_unreference(&obj
->base
);
1254 mutex_unlock(&dev
->struct_mutex
);
1259 * Maps the contents of an object, returning the address it is mapped
1262 * While the mapping holds a reference on the contents of the object, it doesn't
1263 * imply a ref on the object itself.
1266 i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1267 struct drm_file
*file
)
1269 struct drm_i915_gem_mmap
*args
= data
;
1270 struct drm_gem_object
*obj
;
1273 obj
= drm_gem_object_lookup(dev
, file
, args
->handle
);
1277 /* prime objects have no backing filp to GEM mmap
1281 drm_gem_object_unreference_unlocked(obj
);
1285 addr
= vm_mmap(obj
->filp
, 0, args
->size
,
1286 PROT_READ
| PROT_WRITE
, MAP_SHARED
,
1288 drm_gem_object_unreference_unlocked(obj
);
1289 if (IS_ERR((void *)addr
))
1292 args
->addr_ptr
= (uint64_t) addr
;
1298 * i915_gem_fault - fault a page into the GTT
1299 * vma: VMA in question
1302 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1303 * from userspace. The fault handler takes care of binding the object to
1304 * the GTT (if needed), allocating and programming a fence register (again,
1305 * only if needed based on whether the old reg is still valid or the object
1306 * is tiled) and inserting a new PTE into the faulting process.
1308 * Note that the faulting process may involve evicting existing objects
1309 * from the GTT and/or fence registers to make room. So performance may
1310 * suffer if the GTT working set is large or there are few fence registers
1313 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
)
1315 struct drm_i915_gem_object
*obj
= to_intel_bo(vma
->vm_private_data
);
1316 struct drm_device
*dev
= obj
->base
.dev
;
1317 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1318 pgoff_t page_offset
;
1321 bool write
= !!(vmf
->flags
& FAULT_FLAG_WRITE
);
1323 /* We don't use vmf->pgoff since that has the fake offset */
1324 page_offset
= ((unsigned long)vmf
->virtual_address
- vma
->vm_start
) >>
1327 ret
= i915_mutex_lock_interruptible(dev
);
1331 trace_i915_gem_object_fault(obj
, page_offset
, true, write
);
1333 /* Access to snoopable pages through the GTT is incoherent. */
1334 if (obj
->cache_level
!= I915_CACHE_NONE
&& !HAS_LLC(dev
)) {
1339 /* Now bind it into the GTT if needed */
1340 ret
= i915_gem_object_pin(obj
, 0, true, false);
1344 ret
= i915_gem_object_set_to_gtt_domain(obj
, write
);
1348 ret
= i915_gem_object_get_fence(obj
);
1352 obj
->fault_mappable
= true;
1354 pfn
= ((dev_priv
->gtt
.mappable_base
+ obj
->gtt_offset
) >> PAGE_SHIFT
) +
1357 /* Finally, remap it using the new GTT offset */
1358 ret
= vm_insert_pfn(vma
, (unsigned long)vmf
->virtual_address
, pfn
);
1360 i915_gem_object_unpin(obj
);
1362 mutex_unlock(&dev
->struct_mutex
);
1366 /* If this -EIO is due to a gpu hang, give the reset code a
1367 * chance to clean up the mess. Otherwise return the proper
1369 if (i915_terminally_wedged(&dev_priv
->gpu_error
))
1370 return VM_FAULT_SIGBUS
;
1372 /* Give the error handler a chance to run and move the
1373 * objects off the GPU active list. Next time we service the
1374 * fault, we should be able to transition the page into the
1375 * GTT without touching the GPU (and so avoid further
1376 * EIO/EGAIN). If the GPU is wedged, then there is no issue
1377 * with coherency, just lost writes.
1385 * EBUSY is ok: this just means that another thread
1386 * already did the job.
1388 return VM_FAULT_NOPAGE
;
1390 return VM_FAULT_OOM
;
1392 return VM_FAULT_SIGBUS
;
1394 WARN_ONCE(ret
, "unhandled error in i915_gem_fault: %i\n", ret
);
1395 return VM_FAULT_SIGBUS
;
1400 * i915_gem_release_mmap - remove physical page mappings
1401 * @obj: obj in question
1403 * Preserve the reservation of the mmapping with the DRM core code, but
1404 * relinquish ownership of the pages back to the system.
1406 * It is vital that we remove the page mapping if we have mapped a tiled
1407 * object through the GTT and then lose the fence register due to
1408 * resource pressure. Similarly if the object has been moved out of the
1409 * aperture, than pages mapped into userspace must be revoked. Removing the
1410 * mapping will then trigger a page fault on the next user access, allowing
1411 * fixup by i915_gem_fault().
1414 i915_gem_release_mmap(struct drm_i915_gem_object
*obj
)
1416 if (!obj
->fault_mappable
)
1419 if (obj
->base
.dev
->dev_mapping
)
1420 unmap_mapping_range(obj
->base
.dev
->dev_mapping
,
1421 (loff_t
)obj
->base
.map_list
.hash
.key
<<PAGE_SHIFT
,
1424 obj
->fault_mappable
= false;
1428 i915_gem_get_gtt_size(struct drm_device
*dev
, uint32_t size
, int tiling_mode
)
1432 if (INTEL_INFO(dev
)->gen
>= 4 ||
1433 tiling_mode
== I915_TILING_NONE
)
1436 /* Previous chips need a power-of-two fence region when tiling */
1437 if (INTEL_INFO(dev
)->gen
== 3)
1438 gtt_size
= 1024*1024;
1440 gtt_size
= 512*1024;
1442 while (gtt_size
< size
)
1449 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1450 * @obj: object to check
1452 * Return the required GTT alignment for an object, taking into account
1453 * potential fence register mapping.
1456 i915_gem_get_gtt_alignment(struct drm_device
*dev
, uint32_t size
,
1457 int tiling_mode
, bool fenced
)
1460 * Minimum alignment is 4k (GTT page size), but might be greater
1461 * if a fence register is needed for the object.
1463 if (INTEL_INFO(dev
)->gen
>= 4 || (!fenced
&& IS_G33(dev
)) ||
1464 tiling_mode
== I915_TILING_NONE
)
1468 * Previous chips need to be aligned to the size of the smallest
1469 * fence register that can contain the object.
1471 return i915_gem_get_gtt_size(dev
, size
, tiling_mode
);
1474 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object
*obj
)
1476 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
1479 if (obj
->base
.map_list
.map
)
1482 dev_priv
->mm
.shrinker_no_lock_stealing
= true;
1484 ret
= drm_gem_create_mmap_offset(&obj
->base
);
1488 /* Badly fragmented mmap space? The only way we can recover
1489 * space is by destroying unwanted objects. We can't randomly release
1490 * mmap_offsets as userspace expects them to be persistent for the
1491 * lifetime of the objects. The closest we can is to release the
1492 * offsets on purgeable objects by truncating it and marking it purged,
1493 * which prevents userspace from ever using that object again.
1495 i915_gem_purge(dev_priv
, obj
->base
.size
>> PAGE_SHIFT
);
1496 ret
= drm_gem_create_mmap_offset(&obj
->base
);
1500 i915_gem_shrink_all(dev_priv
);
1501 ret
= drm_gem_create_mmap_offset(&obj
->base
);
1503 dev_priv
->mm
.shrinker_no_lock_stealing
= false;
1508 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object
*obj
)
1510 if (!obj
->base
.map_list
.map
)
1513 drm_gem_free_mmap_offset(&obj
->base
);
1517 i915_gem_mmap_gtt(struct drm_file
*file
,
1518 struct drm_device
*dev
,
1522 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1523 struct drm_i915_gem_object
*obj
;
1526 ret
= i915_mutex_lock_interruptible(dev
);
1530 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, handle
));
1531 if (&obj
->base
== NULL
) {
1536 if (obj
->base
.size
> dev_priv
->gtt
.mappable_end
) {
1541 if (obj
->madv
!= I915_MADV_WILLNEED
) {
1542 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1547 ret
= i915_gem_object_create_mmap_offset(obj
);
1551 *offset
= (u64
)obj
->base
.map_list
.hash
.key
<< PAGE_SHIFT
;
1554 drm_gem_object_unreference(&obj
->base
);
1556 mutex_unlock(&dev
->struct_mutex
);
1561 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1563 * @data: GTT mapping ioctl data
1564 * @file: GEM object info
1566 * Simply returns the fake offset to userspace so it can mmap it.
1567 * The mmap call will end up in drm_gem_mmap(), which will set things
1568 * up so we can get faults in the handler above.
1570 * The fault handler will take care of binding the object into the GTT
1571 * (since it may have been evicted to make room for something), allocating
1572 * a fence register, and mapping the appropriate aperture address into
1576 i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
1577 struct drm_file
*file
)
1579 struct drm_i915_gem_mmap_gtt
*args
= data
;
1581 return i915_gem_mmap_gtt(file
, dev
, args
->handle
, &args
->offset
);
1584 /* Immediately discard the backing storage */
1586 i915_gem_object_truncate(struct drm_i915_gem_object
*obj
)
1588 struct inode
*inode
;
1590 i915_gem_object_free_mmap_offset(obj
);
1592 if (obj
->base
.filp
== NULL
)
1595 /* Our goal here is to return as much of the memory as
1596 * is possible back to the system as we are called from OOM.
1597 * To do this we must instruct the shmfs to drop all of its
1598 * backing pages, *now*.
1600 inode
= obj
->base
.filp
->f_path
.dentry
->d_inode
;
1601 shmem_truncate_range(inode
, 0, (loff_t
)-1);
1603 obj
->madv
= __I915_MADV_PURGED
;
1607 i915_gem_object_is_purgeable(struct drm_i915_gem_object
*obj
)
1609 return obj
->madv
== I915_MADV_DONTNEED
;
1613 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object
*obj
)
1615 int page_count
= obj
->base
.size
/ PAGE_SIZE
;
1616 struct scatterlist
*sg
;
1619 BUG_ON(obj
->madv
== __I915_MADV_PURGED
);
1621 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
1623 /* In the event of a disaster, abandon all caches and
1624 * hope for the best.
1626 WARN_ON(ret
!= -EIO
);
1627 i915_gem_clflush_object(obj
);
1628 obj
->base
.read_domains
= obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
1631 if (i915_gem_object_needs_bit17_swizzle(obj
))
1632 i915_gem_object_save_bit_17_swizzle(obj
);
1634 if (obj
->madv
== I915_MADV_DONTNEED
)
1637 for_each_sg(obj
->pages
->sgl
, sg
, page_count
, i
) {
1638 struct page
*page
= sg_page(sg
);
1641 set_page_dirty(page
);
1643 if (obj
->madv
== I915_MADV_WILLNEED
)
1644 mark_page_accessed(page
);
1646 page_cache_release(page
);
1650 sg_free_table(obj
->pages
);
1655 i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
)
1657 const struct drm_i915_gem_object_ops
*ops
= obj
->ops
;
1659 if (obj
->pages
== NULL
)
1662 BUG_ON(obj
->gtt_space
);
1664 if (obj
->pages_pin_count
)
1667 /* ->put_pages might need to allocate memory for the bit17 swizzle
1668 * array, hence protect them from being reaped by removing them from gtt
1670 list_del(&obj
->gtt_list
);
1672 ops
->put_pages(obj
);
1675 if (i915_gem_object_is_purgeable(obj
))
1676 i915_gem_object_truncate(obj
);
1682 i915_gem_purge(struct drm_i915_private
*dev_priv
, long target
)
1684 struct drm_i915_gem_object
*obj
, *next
;
1687 list_for_each_entry_safe(obj
, next
,
1688 &dev_priv
->mm
.unbound_list
,
1690 if (i915_gem_object_is_purgeable(obj
) &&
1691 i915_gem_object_put_pages(obj
) == 0) {
1692 count
+= obj
->base
.size
>> PAGE_SHIFT
;
1693 if (count
>= target
)
1698 list_for_each_entry_safe(obj
, next
,
1699 &dev_priv
->mm
.inactive_list
,
1701 if (i915_gem_object_is_purgeable(obj
) &&
1702 i915_gem_object_unbind(obj
) == 0 &&
1703 i915_gem_object_put_pages(obj
) == 0) {
1704 count
+= obj
->base
.size
>> PAGE_SHIFT
;
1705 if (count
>= target
)
1714 i915_gem_shrink_all(struct drm_i915_private
*dev_priv
)
1716 struct drm_i915_gem_object
*obj
, *next
;
1718 i915_gem_evict_everything(dev_priv
->dev
);
1720 list_for_each_entry_safe(obj
, next
, &dev_priv
->mm
.unbound_list
, gtt_list
)
1721 i915_gem_object_put_pages(obj
);
1725 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object
*obj
)
1727 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
1729 struct address_space
*mapping
;
1730 struct sg_table
*st
;
1731 struct scatterlist
*sg
;
1735 /* Assert that the object is not currently in any GPU domain. As it
1736 * wasn't in the GTT, there shouldn't be any way it could have been in
1739 BUG_ON(obj
->base
.read_domains
& I915_GEM_GPU_DOMAINS
);
1740 BUG_ON(obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
);
1742 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
1746 page_count
= obj
->base
.size
/ PAGE_SIZE
;
1747 if (sg_alloc_table(st
, page_count
, GFP_KERNEL
)) {
1753 /* Get the list of pages out of our struct file. They'll be pinned
1754 * at this point until we release them.
1756 * Fail silently without starting the shrinker
1758 mapping
= obj
->base
.filp
->f_path
.dentry
->d_inode
->i_mapping
;
1759 gfp
= mapping_gfp_mask(mapping
);
1760 gfp
|= __GFP_NORETRY
| __GFP_NOWARN
| __GFP_NO_KSWAPD
;
1761 gfp
&= ~(__GFP_IO
| __GFP_WAIT
);
1762 for_each_sg(st
->sgl
, sg
, page_count
, i
) {
1763 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
1765 i915_gem_purge(dev_priv
, page_count
);
1766 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
1769 /* We've tried hard to allocate the memory by reaping
1770 * our own buffer, now let the real VM do its job and
1771 * go down in flames if truly OOM.
1773 gfp
&= ~(__GFP_NORETRY
| __GFP_NOWARN
| __GFP_NO_KSWAPD
);
1774 gfp
|= __GFP_IO
| __GFP_WAIT
;
1776 i915_gem_shrink_all(dev_priv
);
1777 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
1781 gfp
|= __GFP_NORETRY
| __GFP_NOWARN
| __GFP_NO_KSWAPD
;
1782 gfp
&= ~(__GFP_IO
| __GFP_WAIT
);
1785 sg_set_page(sg
, page
, PAGE_SIZE
, 0);
1790 if (i915_gem_object_needs_bit17_swizzle(obj
))
1791 i915_gem_object_do_bit_17_swizzle(obj
);
1796 for_each_sg(st
->sgl
, sg
, i
, page_count
)
1797 page_cache_release(sg_page(sg
));
1800 return PTR_ERR(page
);
1803 /* Ensure that the associated pages are gathered from the backing storage
1804 * and pinned into our object. i915_gem_object_get_pages() may be called
1805 * multiple times before they are released by a single call to
1806 * i915_gem_object_put_pages() - once the pages are no longer referenced
1807 * either as a result of memory pressure (reaping pages under the shrinker)
1808 * or as the object is itself released.
1811 i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
)
1813 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
1814 const struct drm_i915_gem_object_ops
*ops
= obj
->ops
;
1820 if (obj
->madv
!= I915_MADV_WILLNEED
) {
1821 DRM_ERROR("Attempting to obtain a purgeable object\n");
1825 BUG_ON(obj
->pages_pin_count
);
1827 ret
= ops
->get_pages(obj
);
1831 list_add_tail(&obj
->gtt_list
, &dev_priv
->mm
.unbound_list
);
1836 i915_gem_object_move_to_active(struct drm_i915_gem_object
*obj
,
1837 struct intel_ring_buffer
*ring
)
1839 struct drm_device
*dev
= obj
->base
.dev
;
1840 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1841 u32 seqno
= intel_ring_get_seqno(ring
);
1843 BUG_ON(ring
== NULL
);
1846 /* Add a reference if we're newly entering the active list. */
1848 drm_gem_object_reference(&obj
->base
);
1852 /* Move from whatever list we were on to the tail of execution. */
1853 list_move_tail(&obj
->mm_list
, &dev_priv
->mm
.active_list
);
1854 list_move_tail(&obj
->ring_list
, &ring
->active_list
);
1856 obj
->last_read_seqno
= seqno
;
1858 if (obj
->fenced_gpu_access
) {
1859 obj
->last_fenced_seqno
= seqno
;
1861 /* Bump MRU to take account of the delayed flush */
1862 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
1863 struct drm_i915_fence_reg
*reg
;
1865 reg
= &dev_priv
->fence_regs
[obj
->fence_reg
];
1866 list_move_tail(®
->lru_list
,
1867 &dev_priv
->mm
.fence_list
);
1873 i915_gem_object_move_to_inactive(struct drm_i915_gem_object
*obj
)
1875 struct drm_device
*dev
= obj
->base
.dev
;
1876 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1878 BUG_ON(obj
->base
.write_domain
& ~I915_GEM_GPU_DOMAINS
);
1879 BUG_ON(!obj
->active
);
1881 if (obj
->pin_count
) /* are we a framebuffer? */
1882 intel_mark_fb_idle(obj
);
1884 list_move_tail(&obj
->mm_list
, &dev_priv
->mm
.inactive_list
);
1886 list_del_init(&obj
->ring_list
);
1889 obj
->last_read_seqno
= 0;
1890 obj
->last_write_seqno
= 0;
1891 obj
->base
.write_domain
= 0;
1893 obj
->last_fenced_seqno
= 0;
1894 obj
->fenced_gpu_access
= false;
1897 drm_gem_object_unreference(&obj
->base
);
1899 WARN_ON(i915_verify_lists(dev
));
1903 i915_gem_init_seqno(struct drm_device
*dev
, u32 seqno
)
1905 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1906 struct intel_ring_buffer
*ring
;
1909 /* Carefully retire all requests without writing to the rings */
1910 for_each_ring(ring
, dev_priv
, i
) {
1911 ret
= intel_ring_idle(ring
);
1915 i915_gem_retire_requests(dev
);
1917 /* Finally reset hw state */
1918 for_each_ring(ring
, dev_priv
, i
) {
1919 intel_ring_init_seqno(ring
, seqno
);
1921 for (j
= 0; j
< ARRAY_SIZE(ring
->sync_seqno
); j
++)
1922 ring
->sync_seqno
[j
] = 0;
1928 int i915_gem_set_seqno(struct drm_device
*dev
, u32 seqno
)
1930 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1936 /* HWS page needs to be set less than what we
1937 * will inject to ring
1939 ret
= i915_gem_init_seqno(dev
, seqno
- 1);
1943 /* Carefully set the last_seqno value so that wrap
1944 * detection still works
1946 dev_priv
->next_seqno
= seqno
;
1947 dev_priv
->last_seqno
= seqno
- 1;
1948 if (dev_priv
->last_seqno
== 0)
1949 dev_priv
->last_seqno
--;
1955 i915_gem_get_seqno(struct drm_device
*dev
, u32
*seqno
)
1957 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1959 /* reserve 0 for non-seqno */
1960 if (dev_priv
->next_seqno
== 0) {
1961 int ret
= i915_gem_init_seqno(dev
, 0);
1965 dev_priv
->next_seqno
= 1;
1968 *seqno
= dev_priv
->last_seqno
= dev_priv
->next_seqno
++;
1973 i915_add_request(struct intel_ring_buffer
*ring
,
1974 struct drm_file
*file
,
1977 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
1978 struct drm_i915_gem_request
*request
;
1979 u32 request_ring_position
;
1984 * Emit any outstanding flushes - execbuf can fail to emit the flush
1985 * after having emitted the batchbuffer command. Hence we need to fix
1986 * things up similar to emitting the lazy request. The difference here
1987 * is that the flush _must_ happen before the next request, no matter
1990 ret
= intel_ring_flush_all_caches(ring
);
1994 request
= kmalloc(sizeof(*request
), GFP_KERNEL
);
1995 if (request
== NULL
)
1999 /* Record the position of the start of the request so that
2000 * should we detect the updated seqno part-way through the
2001 * GPU processing the request, we never over-estimate the
2002 * position of the head.
2004 request_ring_position
= intel_ring_get_tail(ring
);
2006 ret
= ring
->add_request(ring
);
2012 request
->seqno
= intel_ring_get_seqno(ring
);
2013 request
->ring
= ring
;
2014 request
->tail
= request_ring_position
;
2015 request
->emitted_jiffies
= jiffies
;
2016 was_empty
= list_empty(&ring
->request_list
);
2017 list_add_tail(&request
->list
, &ring
->request_list
);
2018 request
->file_priv
= NULL
;
2021 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
2023 spin_lock(&file_priv
->mm
.lock
);
2024 request
->file_priv
= file_priv
;
2025 list_add_tail(&request
->client_list
,
2026 &file_priv
->mm
.request_list
);
2027 spin_unlock(&file_priv
->mm
.lock
);
2030 trace_i915_gem_request_add(ring
, request
->seqno
);
2031 ring
->outstanding_lazy_request
= 0;
2033 if (!dev_priv
->mm
.suspended
) {
2034 if (i915_enable_hangcheck
) {
2035 mod_timer(&dev_priv
->gpu_error
.hangcheck_timer
,
2036 round_jiffies_up(jiffies
+ DRM_I915_HANGCHECK_JIFFIES
));
2039 queue_delayed_work(dev_priv
->wq
,
2040 &dev_priv
->mm
.retire_work
,
2041 round_jiffies_up_relative(HZ
));
2042 intel_mark_busy(dev_priv
->dev
);
2047 *out_seqno
= request
->seqno
;
2052 i915_gem_request_remove_from_client(struct drm_i915_gem_request
*request
)
2054 struct drm_i915_file_private
*file_priv
= request
->file_priv
;
2059 spin_lock(&file_priv
->mm
.lock
);
2060 if (request
->file_priv
) {
2061 list_del(&request
->client_list
);
2062 request
->file_priv
= NULL
;
2064 spin_unlock(&file_priv
->mm
.lock
);
2067 static void i915_gem_reset_ring_lists(struct drm_i915_private
*dev_priv
,
2068 struct intel_ring_buffer
*ring
)
2070 while (!list_empty(&ring
->request_list
)) {
2071 struct drm_i915_gem_request
*request
;
2073 request
= list_first_entry(&ring
->request_list
,
2074 struct drm_i915_gem_request
,
2077 list_del(&request
->list
);
2078 i915_gem_request_remove_from_client(request
);
2082 while (!list_empty(&ring
->active_list
)) {
2083 struct drm_i915_gem_object
*obj
;
2085 obj
= list_first_entry(&ring
->active_list
,
2086 struct drm_i915_gem_object
,
2089 i915_gem_object_move_to_inactive(obj
);
2093 static void i915_gem_reset_fences(struct drm_device
*dev
)
2095 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2098 for (i
= 0; i
< dev_priv
->num_fence_regs
; i
++) {
2099 struct drm_i915_fence_reg
*reg
= &dev_priv
->fence_regs
[i
];
2101 i915_gem_write_fence(dev
, i
, NULL
);
2104 i915_gem_object_fence_lost(reg
->obj
);
2108 INIT_LIST_HEAD(®
->lru_list
);
2111 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
2114 void i915_gem_reset(struct drm_device
*dev
)
2116 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2117 struct drm_i915_gem_object
*obj
;
2118 struct intel_ring_buffer
*ring
;
2121 for_each_ring(ring
, dev_priv
, i
)
2122 i915_gem_reset_ring_lists(dev_priv
, ring
);
2124 /* Move everything out of the GPU domains to ensure we do any
2125 * necessary invalidation upon reuse.
2127 list_for_each_entry(obj
,
2128 &dev_priv
->mm
.inactive_list
,
2131 obj
->base
.read_domains
&= ~I915_GEM_GPU_DOMAINS
;
2134 /* The fence registers are invalidated so clear them out */
2135 i915_gem_reset_fences(dev
);
2139 * This function clears the request list as sequence numbers are passed.
2142 i915_gem_retire_requests_ring(struct intel_ring_buffer
*ring
)
2146 if (list_empty(&ring
->request_list
))
2149 WARN_ON(i915_verify_lists(ring
->dev
));
2151 seqno
= ring
->get_seqno(ring
, true);
2153 while (!list_empty(&ring
->request_list
)) {
2154 struct drm_i915_gem_request
*request
;
2156 request
= list_first_entry(&ring
->request_list
,
2157 struct drm_i915_gem_request
,
2160 if (!i915_seqno_passed(seqno
, request
->seqno
))
2163 trace_i915_gem_request_retire(ring
, request
->seqno
);
2164 /* We know the GPU must have read the request to have
2165 * sent us the seqno + interrupt, so use the position
2166 * of tail of the request to update the last known position
2169 ring
->last_retired_head
= request
->tail
;
2171 list_del(&request
->list
);
2172 i915_gem_request_remove_from_client(request
);
2176 /* Move any buffers on the active list that are no longer referenced
2177 * by the ringbuffer to the flushing/inactive lists as appropriate.
2179 while (!list_empty(&ring
->active_list
)) {
2180 struct drm_i915_gem_object
*obj
;
2182 obj
= list_first_entry(&ring
->active_list
,
2183 struct drm_i915_gem_object
,
2186 if (!i915_seqno_passed(seqno
, obj
->last_read_seqno
))
2189 i915_gem_object_move_to_inactive(obj
);
2192 if (unlikely(ring
->trace_irq_seqno
&&
2193 i915_seqno_passed(seqno
, ring
->trace_irq_seqno
))) {
2194 ring
->irq_put(ring
);
2195 ring
->trace_irq_seqno
= 0;
2198 WARN_ON(i915_verify_lists(ring
->dev
));
2202 i915_gem_retire_requests(struct drm_device
*dev
)
2204 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2205 struct intel_ring_buffer
*ring
;
2208 for_each_ring(ring
, dev_priv
, i
)
2209 i915_gem_retire_requests_ring(ring
);
2213 i915_gem_retire_work_handler(struct work_struct
*work
)
2215 drm_i915_private_t
*dev_priv
;
2216 struct drm_device
*dev
;
2217 struct intel_ring_buffer
*ring
;
2221 dev_priv
= container_of(work
, drm_i915_private_t
,
2222 mm
.retire_work
.work
);
2223 dev
= dev_priv
->dev
;
2225 /* Come back later if the device is busy... */
2226 if (!mutex_trylock(&dev
->struct_mutex
)) {
2227 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
,
2228 round_jiffies_up_relative(HZ
));
2232 i915_gem_retire_requests(dev
);
2234 /* Send a periodic flush down the ring so we don't hold onto GEM
2235 * objects indefinitely.
2238 for_each_ring(ring
, dev_priv
, i
) {
2239 if (ring
->gpu_caches_dirty
)
2240 i915_add_request(ring
, NULL
, NULL
);
2242 idle
&= list_empty(&ring
->request_list
);
2245 if (!dev_priv
->mm
.suspended
&& !idle
)
2246 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
,
2247 round_jiffies_up_relative(HZ
));
2249 intel_mark_idle(dev
);
2251 mutex_unlock(&dev
->struct_mutex
);
2255 * Ensures that an object will eventually get non-busy by flushing any required
2256 * write domains, emitting any outstanding lazy request and retiring and
2257 * completed requests.
2260 i915_gem_object_flush_active(struct drm_i915_gem_object
*obj
)
2265 ret
= i915_gem_check_olr(obj
->ring
, obj
->last_read_seqno
);
2269 i915_gem_retire_requests_ring(obj
->ring
);
2276 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2277 * @DRM_IOCTL_ARGS: standard ioctl arguments
2279 * Returns 0 if successful, else an error is returned with the remaining time in
2280 * the timeout parameter.
2281 * -ETIME: object is still busy after timeout
2282 * -ERESTARTSYS: signal interrupted the wait
2283 * -ENONENT: object doesn't exist
2284 * Also possible, but rare:
2285 * -EAGAIN: GPU wedged
2287 * -ENODEV: Internal IRQ fail
2288 * -E?: The add request failed
2290 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2291 * non-zero timeout parameter the wait ioctl will wait for the given number of
2292 * nanoseconds on an object becoming unbusy. Since the wait itself does so
2293 * without holding struct_mutex the object may become re-busied before this
2294 * function completes. A similar but shorter * race condition exists in the busy
2298 i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
, struct drm_file
*file
)
2300 struct drm_i915_gem_wait
*args
= data
;
2301 struct drm_i915_gem_object
*obj
;
2302 struct intel_ring_buffer
*ring
= NULL
;
2303 struct timespec timeout_stack
, *timeout
= NULL
;
2307 if (args
->timeout_ns
>= 0) {
2308 timeout_stack
= ns_to_timespec(args
->timeout_ns
);
2309 timeout
= &timeout_stack
;
2312 ret
= i915_mutex_lock_interruptible(dev
);
2316 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->bo_handle
));
2317 if (&obj
->base
== NULL
) {
2318 mutex_unlock(&dev
->struct_mutex
);
2322 /* Need to make sure the object gets inactive eventually. */
2323 ret
= i915_gem_object_flush_active(obj
);
2328 seqno
= obj
->last_read_seqno
;
2335 /* Do this after OLR check to make sure we make forward progress polling
2336 * on this IOCTL with a 0 timeout (like busy ioctl)
2338 if (!args
->timeout_ns
) {
2343 drm_gem_object_unreference(&obj
->base
);
2344 mutex_unlock(&dev
->struct_mutex
);
2346 ret
= __wait_seqno(ring
, seqno
, true, timeout
);
2348 WARN_ON(!timespec_valid(timeout
));
2349 args
->timeout_ns
= timespec_to_ns(timeout
);
2354 drm_gem_object_unreference(&obj
->base
);
2355 mutex_unlock(&dev
->struct_mutex
);
2360 * i915_gem_object_sync - sync an object to a ring.
2362 * @obj: object which may be in use on another ring.
2363 * @to: ring we wish to use the object on. May be NULL.
2365 * This code is meant to abstract object synchronization with the GPU.
2366 * Calling with NULL implies synchronizing the object with the CPU
2367 * rather than a particular GPU ring.
2369 * Returns 0 if successful, else propagates up the lower layer error.
2372 i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
2373 struct intel_ring_buffer
*to
)
2375 struct intel_ring_buffer
*from
= obj
->ring
;
2379 if (from
== NULL
|| to
== from
)
2382 if (to
== NULL
|| !i915_semaphore_is_enabled(obj
->base
.dev
))
2383 return i915_gem_object_wait_rendering(obj
, false);
2385 idx
= intel_ring_sync_index(from
, to
);
2387 seqno
= obj
->last_read_seqno
;
2388 if (seqno
<= from
->sync_seqno
[idx
])
2391 ret
= i915_gem_check_olr(obj
->ring
, seqno
);
2395 ret
= to
->sync_to(to
, from
, seqno
);
2397 /* We use last_read_seqno because sync_to()
2398 * might have just caused seqno wrap under
2401 from
->sync_seqno
[idx
] = obj
->last_read_seqno
;
2406 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object
*obj
)
2408 u32 old_write_domain
, old_read_domains
;
2410 /* Force a pagefault for domain tracking on next user access */
2411 i915_gem_release_mmap(obj
);
2413 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
) == 0)
2416 /* Wait for any direct GTT access to complete */
2419 old_read_domains
= obj
->base
.read_domains
;
2420 old_write_domain
= obj
->base
.write_domain
;
2422 obj
->base
.read_domains
&= ~I915_GEM_DOMAIN_GTT
;
2423 obj
->base
.write_domain
&= ~I915_GEM_DOMAIN_GTT
;
2425 trace_i915_gem_object_change_domain(obj
,
2431 * Unbinds an object from the GTT aperture.
2434 i915_gem_object_unbind(struct drm_i915_gem_object
*obj
)
2436 drm_i915_private_t
*dev_priv
= obj
->base
.dev
->dev_private
;
2439 if (obj
->gtt_space
== NULL
)
2445 BUG_ON(obj
->pages
== NULL
);
2447 ret
= i915_gem_object_finish_gpu(obj
);
2450 /* Continue on if we fail due to EIO, the GPU is hung so we
2451 * should be safe and we need to cleanup or else we might
2452 * cause memory corruption through use-after-free.
2455 i915_gem_object_finish_gtt(obj
);
2457 /* release the fence reg _after_ flushing */
2458 ret
= i915_gem_object_put_fence(obj
);
2462 trace_i915_gem_object_unbind(obj
);
2464 if (obj
->has_global_gtt_mapping
)
2465 i915_gem_gtt_unbind_object(obj
);
2466 if (obj
->has_aliasing_ppgtt_mapping
) {
2467 i915_ppgtt_unbind_object(dev_priv
->mm
.aliasing_ppgtt
, obj
);
2468 obj
->has_aliasing_ppgtt_mapping
= 0;
2470 i915_gem_gtt_finish_object(obj
);
2472 list_del(&obj
->mm_list
);
2473 list_move_tail(&obj
->gtt_list
, &dev_priv
->mm
.unbound_list
);
2474 /* Avoid an unnecessary call to unbind on rebind. */
2475 obj
->map_and_fenceable
= true;
2477 drm_mm_put_block(obj
->gtt_space
);
2478 obj
->gtt_space
= NULL
;
2479 obj
->gtt_offset
= 0;
2484 int i915_gpu_idle(struct drm_device
*dev
)
2486 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2487 struct intel_ring_buffer
*ring
;
2490 /* Flush everything onto the inactive list. */
2491 for_each_ring(ring
, dev_priv
, i
) {
2492 ret
= i915_switch_context(ring
, NULL
, DEFAULT_CONTEXT_ID
);
2496 ret
= intel_ring_idle(ring
);
2504 static void i965_write_fence_reg(struct drm_device
*dev
, int reg
,
2505 struct drm_i915_gem_object
*obj
)
2507 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2509 int fence_pitch_shift
;
2512 if (INTEL_INFO(dev
)->gen
>= 6) {
2513 fence_reg
= FENCE_REG_SANDYBRIDGE_0
;
2514 fence_pitch_shift
= SANDYBRIDGE_FENCE_PITCH_SHIFT
;
2516 fence_reg
= FENCE_REG_965_0
;
2517 fence_pitch_shift
= I965_FENCE_PITCH_SHIFT
;
2521 u32 size
= obj
->gtt_space
->size
;
2523 val
= (uint64_t)((obj
->gtt_offset
+ size
- 4096) &
2525 val
|= obj
->gtt_offset
& 0xfffff000;
2526 val
|= (uint64_t)((obj
->stride
/ 128) - 1) << fence_pitch_shift
;
2527 if (obj
->tiling_mode
== I915_TILING_Y
)
2528 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
2529 val
|= I965_FENCE_REG_VALID
;
2533 fence_reg
+= reg
* 8;
2534 I915_WRITE64(fence_reg
, val
);
2535 POSTING_READ(fence_reg
);
2538 static void i915_write_fence_reg(struct drm_device
*dev
, int reg
,
2539 struct drm_i915_gem_object
*obj
)
2541 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2545 u32 size
= obj
->gtt_space
->size
;
2549 WARN((obj
->gtt_offset
& ~I915_FENCE_START_MASK
) ||
2550 (size
& -size
) != size
||
2551 (obj
->gtt_offset
& (size
- 1)),
2552 "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2553 obj
->gtt_offset
, obj
->map_and_fenceable
, size
);
2555 if (obj
->tiling_mode
== I915_TILING_Y
&& HAS_128_BYTE_Y_TILING(dev
))
2560 /* Note: pitch better be a power of two tile widths */
2561 pitch_val
= obj
->stride
/ tile_width
;
2562 pitch_val
= ffs(pitch_val
) - 1;
2564 val
= obj
->gtt_offset
;
2565 if (obj
->tiling_mode
== I915_TILING_Y
)
2566 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2567 val
|= I915_FENCE_SIZE_BITS(size
);
2568 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2569 val
|= I830_FENCE_REG_VALID
;
2574 reg
= FENCE_REG_830_0
+ reg
* 4;
2576 reg
= FENCE_REG_945_8
+ (reg
- 8) * 4;
2578 I915_WRITE(reg
, val
);
2582 static void i830_write_fence_reg(struct drm_device
*dev
, int reg
,
2583 struct drm_i915_gem_object
*obj
)
2585 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2589 u32 size
= obj
->gtt_space
->size
;
2592 WARN((obj
->gtt_offset
& ~I830_FENCE_START_MASK
) ||
2593 (size
& -size
) != size
||
2594 (obj
->gtt_offset
& (size
- 1)),
2595 "object 0x%08x not 512K or pot-size 0x%08x aligned\n",
2596 obj
->gtt_offset
, size
);
2598 pitch_val
= obj
->stride
/ 128;
2599 pitch_val
= ffs(pitch_val
) - 1;
2601 val
= obj
->gtt_offset
;
2602 if (obj
->tiling_mode
== I915_TILING_Y
)
2603 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2604 val
|= I830_FENCE_SIZE_BITS(size
);
2605 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2606 val
|= I830_FENCE_REG_VALID
;
2610 I915_WRITE(FENCE_REG_830_0
+ reg
* 4, val
);
2611 POSTING_READ(FENCE_REG_830_0
+ reg
* 4);
2614 inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object
*obj
)
2616 return obj
&& obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
;
2619 static void i915_gem_write_fence(struct drm_device
*dev
, int reg
,
2620 struct drm_i915_gem_object
*obj
)
2622 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2624 /* Ensure that all CPU reads are completed before installing a fence
2625 * and all writes before removing the fence.
2627 if (i915_gem_object_needs_mb(dev_priv
->fence_regs
[reg
].obj
))
2630 switch (INTEL_INFO(dev
)->gen
) {
2634 case 4: i965_write_fence_reg(dev
, reg
, obj
); break;
2635 case 3: i915_write_fence_reg(dev
, reg
, obj
); break;
2636 case 2: i830_write_fence_reg(dev
, reg
, obj
); break;
2640 /* And similarly be paranoid that no direct access to this region
2641 * is reordered to before the fence is installed.
2643 if (i915_gem_object_needs_mb(obj
))
2647 static inline int fence_number(struct drm_i915_private
*dev_priv
,
2648 struct drm_i915_fence_reg
*fence
)
2650 return fence
- dev_priv
->fence_regs
;
2653 static void i915_gem_object_update_fence(struct drm_i915_gem_object
*obj
,
2654 struct drm_i915_fence_reg
*fence
,
2657 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2658 int reg
= fence_number(dev_priv
, fence
);
2660 i915_gem_write_fence(obj
->base
.dev
, reg
, enable
? obj
: NULL
);
2663 obj
->fence_reg
= reg
;
2665 list_move_tail(&fence
->lru_list
, &dev_priv
->mm
.fence_list
);
2667 obj
->fence_reg
= I915_FENCE_REG_NONE
;
2669 list_del_init(&fence
->lru_list
);
2674 i915_gem_object_wait_fence(struct drm_i915_gem_object
*obj
)
2676 if (obj
->last_fenced_seqno
) {
2677 int ret
= i915_wait_seqno(obj
->ring
, obj
->last_fenced_seqno
);
2681 obj
->last_fenced_seqno
= 0;
2684 obj
->fenced_gpu_access
= false;
2689 i915_gem_object_put_fence(struct drm_i915_gem_object
*obj
)
2691 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2694 ret
= i915_gem_object_wait_fence(obj
);
2698 if (obj
->fence_reg
== I915_FENCE_REG_NONE
)
2701 i915_gem_object_update_fence(obj
,
2702 &dev_priv
->fence_regs
[obj
->fence_reg
],
2704 i915_gem_object_fence_lost(obj
);
2709 static struct drm_i915_fence_reg
*
2710 i915_find_fence_reg(struct drm_device
*dev
)
2712 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2713 struct drm_i915_fence_reg
*reg
, *avail
;
2716 /* First try to find a free reg */
2718 for (i
= dev_priv
->fence_reg_start
; i
< dev_priv
->num_fence_regs
; i
++) {
2719 reg
= &dev_priv
->fence_regs
[i
];
2723 if (!reg
->pin_count
)
2730 /* None available, try to steal one or wait for a user to finish */
2731 list_for_each_entry(reg
, &dev_priv
->mm
.fence_list
, lru_list
) {
2742 * i915_gem_object_get_fence - set up fencing for an object
2743 * @obj: object to map through a fence reg
2745 * When mapping objects through the GTT, userspace wants to be able to write
2746 * to them without having to worry about swizzling if the object is tiled.
2747 * This function walks the fence regs looking for a free one for @obj,
2748 * stealing one if it can't find any.
2750 * It then sets up the reg based on the object's properties: address, pitch
2751 * and tiling format.
2753 * For an untiled surface, this removes any existing fence.
2756 i915_gem_object_get_fence(struct drm_i915_gem_object
*obj
)
2758 struct drm_device
*dev
= obj
->base
.dev
;
2759 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2760 bool enable
= obj
->tiling_mode
!= I915_TILING_NONE
;
2761 struct drm_i915_fence_reg
*reg
;
2764 /* Have we updated the tiling parameters upon the object and so
2765 * will need to serialise the write to the associated fence register?
2767 if (obj
->fence_dirty
) {
2768 ret
= i915_gem_object_wait_fence(obj
);
2773 /* Just update our place in the LRU if our fence is getting reused. */
2774 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
2775 reg
= &dev_priv
->fence_regs
[obj
->fence_reg
];
2776 if (!obj
->fence_dirty
) {
2777 list_move_tail(®
->lru_list
,
2778 &dev_priv
->mm
.fence_list
);
2781 } else if (enable
) {
2782 reg
= i915_find_fence_reg(dev
);
2787 struct drm_i915_gem_object
*old
= reg
->obj
;
2789 ret
= i915_gem_object_wait_fence(old
);
2793 i915_gem_object_fence_lost(old
);
2798 i915_gem_object_update_fence(obj
, reg
, enable
);
2799 obj
->fence_dirty
= false;
2804 static bool i915_gem_valid_gtt_space(struct drm_device
*dev
,
2805 struct drm_mm_node
*gtt_space
,
2806 unsigned long cache_level
)
2808 struct drm_mm_node
*other
;
2810 /* On non-LLC machines we have to be careful when putting differing
2811 * types of snoopable memory together to avoid the prefetcher
2812 * crossing memory domains and dying.
2817 if (gtt_space
== NULL
)
2820 if (list_empty(>t_space
->node_list
))
2823 other
= list_entry(gtt_space
->node_list
.prev
, struct drm_mm_node
, node_list
);
2824 if (other
->allocated
&& !other
->hole_follows
&& other
->color
!= cache_level
)
2827 other
= list_entry(gtt_space
->node_list
.next
, struct drm_mm_node
, node_list
);
2828 if (other
->allocated
&& !gtt_space
->hole_follows
&& other
->color
!= cache_level
)
2834 static void i915_gem_verify_gtt(struct drm_device
*dev
)
2837 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2838 struct drm_i915_gem_object
*obj
;
2841 list_for_each_entry(obj
, &dev_priv
->mm
.gtt_list
, gtt_list
) {
2842 if (obj
->gtt_space
== NULL
) {
2843 printk(KERN_ERR
"object found on GTT list with no space reserved\n");
2848 if (obj
->cache_level
!= obj
->gtt_space
->color
) {
2849 printk(KERN_ERR
"object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n",
2850 obj
->gtt_space
->start
,
2851 obj
->gtt_space
->start
+ obj
->gtt_space
->size
,
2853 obj
->gtt_space
->color
);
2858 if (!i915_gem_valid_gtt_space(dev
,
2860 obj
->cache_level
)) {
2861 printk(KERN_ERR
"invalid GTT space found at [%08lx, %08lx] - color=%x\n",
2862 obj
->gtt_space
->start
,
2863 obj
->gtt_space
->start
+ obj
->gtt_space
->size
,
2875 * Finds free space in the GTT aperture and binds the object there.
2878 i915_gem_object_bind_to_gtt(struct drm_i915_gem_object
*obj
,
2880 bool map_and_fenceable
,
2883 struct drm_device
*dev
= obj
->base
.dev
;
2884 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2885 struct drm_mm_node
*node
;
2886 u32 size
, fence_size
, fence_alignment
, unfenced_alignment
;
2887 bool mappable
, fenceable
;
2890 fence_size
= i915_gem_get_gtt_size(dev
,
2893 fence_alignment
= i915_gem_get_gtt_alignment(dev
,
2895 obj
->tiling_mode
, true);
2896 unfenced_alignment
=
2897 i915_gem_get_gtt_alignment(dev
,
2899 obj
->tiling_mode
, false);
2902 alignment
= map_and_fenceable
? fence_alignment
:
2904 if (map_and_fenceable
&& alignment
& (fence_alignment
- 1)) {
2905 DRM_ERROR("Invalid object alignment requested %u\n", alignment
);
2909 size
= map_and_fenceable
? fence_size
: obj
->base
.size
;
2911 /* If the object is bigger than the entire aperture, reject it early
2912 * before evicting everything in a vain attempt to find space.
2914 if (obj
->base
.size
>
2915 (map_and_fenceable
? dev_priv
->gtt
.mappable_end
: dev_priv
->gtt
.total
)) {
2916 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2920 ret
= i915_gem_object_get_pages(obj
);
2924 i915_gem_object_pin_pages(obj
);
2926 node
= kzalloc(sizeof(*node
), GFP_KERNEL
);
2928 i915_gem_object_unpin_pages(obj
);
2933 if (map_and_fenceable
)
2934 ret
= drm_mm_insert_node_in_range_generic(&dev_priv
->mm
.gtt_space
, node
,
2935 size
, alignment
, obj
->cache_level
,
2936 0, dev_priv
->gtt
.mappable_end
);
2938 ret
= drm_mm_insert_node_generic(&dev_priv
->mm
.gtt_space
, node
,
2939 size
, alignment
, obj
->cache_level
);
2941 ret
= i915_gem_evict_something(dev
, size
, alignment
,
2948 i915_gem_object_unpin_pages(obj
);
2952 if (WARN_ON(!i915_gem_valid_gtt_space(dev
, node
, obj
->cache_level
))) {
2953 i915_gem_object_unpin_pages(obj
);
2954 drm_mm_put_block(node
);
2958 ret
= i915_gem_gtt_prepare_object(obj
);
2960 i915_gem_object_unpin_pages(obj
);
2961 drm_mm_put_block(node
);
2965 list_move_tail(&obj
->gtt_list
, &dev_priv
->mm
.bound_list
);
2966 list_add_tail(&obj
->mm_list
, &dev_priv
->mm
.inactive_list
);
2968 obj
->gtt_space
= node
;
2969 obj
->gtt_offset
= node
->start
;
2972 node
->size
== fence_size
&&
2973 (node
->start
& (fence_alignment
- 1)) == 0;
2976 obj
->gtt_offset
+ obj
->base
.size
<= dev_priv
->gtt
.mappable_end
;
2978 obj
->map_and_fenceable
= mappable
&& fenceable
;
2980 i915_gem_object_unpin_pages(obj
);
2981 trace_i915_gem_object_bind(obj
, map_and_fenceable
);
2982 i915_gem_verify_gtt(dev
);
2987 i915_gem_clflush_object(struct drm_i915_gem_object
*obj
)
2989 /* If we don't have a page list set up, then we're not pinned
2990 * to GPU, and we can ignore the cache flush because it'll happen
2991 * again at bind time.
2993 if (obj
->pages
== NULL
)
2996 /* If the GPU is snooping the contents of the CPU cache,
2997 * we do not need to manually clear the CPU cache lines. However,
2998 * the caches are only snooped when the render cache is
2999 * flushed/invalidated. As we always have to emit invalidations
3000 * and flushes when moving into and out of the RENDER domain, correct
3001 * snooping behaviour occurs naturally as the result of our domain
3004 if (obj
->cache_level
!= I915_CACHE_NONE
)
3007 trace_i915_gem_object_clflush(obj
);
3009 drm_clflush_sg(obj
->pages
);
3012 /** Flushes the GTT write domain for the object if it's dirty. */
3014 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
)
3016 uint32_t old_write_domain
;
3018 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_GTT
)
3021 /* No actual flushing is required for the GTT write domain. Writes
3022 * to it immediately go to main memory as far as we know, so there's
3023 * no chipset flush. It also doesn't land in render cache.
3025 * However, we do have to enforce the order so that all writes through
3026 * the GTT land before any writes to the device, such as updates to
3031 old_write_domain
= obj
->base
.write_domain
;
3032 obj
->base
.write_domain
= 0;
3034 trace_i915_gem_object_change_domain(obj
,
3035 obj
->base
.read_domains
,
3039 /** Flushes the CPU write domain for the object if it's dirty. */
3041 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
)
3043 uint32_t old_write_domain
;
3045 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
)
3048 i915_gem_clflush_object(obj
);
3049 i915_gem_chipset_flush(obj
->base
.dev
);
3050 old_write_domain
= obj
->base
.write_domain
;
3051 obj
->base
.write_domain
= 0;
3053 trace_i915_gem_object_change_domain(obj
,
3054 obj
->base
.read_domains
,
3059 * Moves a single object to the GTT read, and possibly write domain.
3061 * This function returns when the move is complete, including waiting on
3065 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
, bool write
)
3067 drm_i915_private_t
*dev_priv
= obj
->base
.dev
->dev_private
;
3068 uint32_t old_write_domain
, old_read_domains
;
3071 /* Not valid to be called on unbound objects. */
3072 if (obj
->gtt_space
== NULL
)
3075 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_GTT
)
3078 ret
= i915_gem_object_wait_rendering(obj
, !write
);
3082 i915_gem_object_flush_cpu_write_domain(obj
);
3084 /* Serialise direct access to this object with the barriers for
3085 * coherent writes from the GPU, by effectively invalidating the
3086 * GTT domain upon first access.
3088 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
) == 0)
3091 old_write_domain
= obj
->base
.write_domain
;
3092 old_read_domains
= obj
->base
.read_domains
;
3094 /* It should now be out of any other write domains, and we can update
3095 * the domain values for our changes.
3097 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
3098 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
3100 obj
->base
.read_domains
= I915_GEM_DOMAIN_GTT
;
3101 obj
->base
.write_domain
= I915_GEM_DOMAIN_GTT
;
3105 trace_i915_gem_object_change_domain(obj
,
3109 /* And bump the LRU for this access */
3110 if (i915_gem_object_is_inactive(obj
))
3111 list_move_tail(&obj
->mm_list
, &dev_priv
->mm
.inactive_list
);
3116 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
3117 enum i915_cache_level cache_level
)
3119 struct drm_device
*dev
= obj
->base
.dev
;
3120 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3123 if (obj
->cache_level
== cache_level
)
3126 if (obj
->pin_count
) {
3127 DRM_DEBUG("can not change the cache level of pinned objects\n");
3131 if (!i915_gem_valid_gtt_space(dev
, obj
->gtt_space
, cache_level
)) {
3132 ret
= i915_gem_object_unbind(obj
);
3137 if (obj
->gtt_space
) {
3138 ret
= i915_gem_object_finish_gpu(obj
);
3142 i915_gem_object_finish_gtt(obj
);
3144 /* Before SandyBridge, you could not use tiling or fence
3145 * registers with snooped memory, so relinquish any fences
3146 * currently pointing to our region in the aperture.
3148 if (INTEL_INFO(dev
)->gen
< 6) {
3149 ret
= i915_gem_object_put_fence(obj
);
3154 if (obj
->has_global_gtt_mapping
)
3155 i915_gem_gtt_bind_object(obj
, cache_level
);
3156 if (obj
->has_aliasing_ppgtt_mapping
)
3157 i915_ppgtt_bind_object(dev_priv
->mm
.aliasing_ppgtt
,
3160 obj
->gtt_space
->color
= cache_level
;
3163 if (cache_level
== I915_CACHE_NONE
) {
3164 u32 old_read_domains
, old_write_domain
;
3166 /* If we're coming from LLC cached, then we haven't
3167 * actually been tracking whether the data is in the
3168 * CPU cache or not, since we only allow one bit set
3169 * in obj->write_domain and have been skipping the clflushes.
3170 * Just set it to the CPU cache for now.
3172 WARN_ON(obj
->base
.write_domain
& ~I915_GEM_DOMAIN_CPU
);
3173 WARN_ON(obj
->base
.read_domains
& ~I915_GEM_DOMAIN_CPU
);
3175 old_read_domains
= obj
->base
.read_domains
;
3176 old_write_domain
= obj
->base
.write_domain
;
3178 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
3179 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
3181 trace_i915_gem_object_change_domain(obj
,
3186 obj
->cache_level
= cache_level
;
3187 i915_gem_verify_gtt(dev
);
3191 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
3192 struct drm_file
*file
)
3194 struct drm_i915_gem_caching
*args
= data
;
3195 struct drm_i915_gem_object
*obj
;
3198 ret
= i915_mutex_lock_interruptible(dev
);
3202 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3203 if (&obj
->base
== NULL
) {
3208 args
->caching
= obj
->cache_level
!= I915_CACHE_NONE
;
3210 drm_gem_object_unreference(&obj
->base
);
3212 mutex_unlock(&dev
->struct_mutex
);
3216 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
3217 struct drm_file
*file
)
3219 struct drm_i915_gem_caching
*args
= data
;
3220 struct drm_i915_gem_object
*obj
;
3221 enum i915_cache_level level
;
3224 switch (args
->caching
) {
3225 case I915_CACHING_NONE
:
3226 level
= I915_CACHE_NONE
;
3228 case I915_CACHING_CACHED
:
3229 level
= I915_CACHE_LLC
;
3235 ret
= i915_mutex_lock_interruptible(dev
);
3239 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3240 if (&obj
->base
== NULL
) {
3245 ret
= i915_gem_object_set_cache_level(obj
, level
);
3247 drm_gem_object_unreference(&obj
->base
);
3249 mutex_unlock(&dev
->struct_mutex
);
3254 * Prepare buffer for display plane (scanout, cursors, etc).
3255 * Can be called from an uninterruptible phase (modesetting) and allows
3256 * any flushes to be pipelined (for pageflips).
3259 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
3261 struct intel_ring_buffer
*pipelined
)
3263 u32 old_read_domains
, old_write_domain
;
3266 if (pipelined
!= obj
->ring
) {
3267 ret
= i915_gem_object_sync(obj
, pipelined
);
3272 /* The display engine is not coherent with the LLC cache on gen6. As
3273 * a result, we make sure that the pinning that is about to occur is
3274 * done with uncached PTEs. This is lowest common denominator for all
3277 * However for gen6+, we could do better by using the GFDT bit instead
3278 * of uncaching, which would allow us to flush all the LLC-cached data
3279 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3281 ret
= i915_gem_object_set_cache_level(obj
, I915_CACHE_NONE
);
3285 /* As the user may map the buffer once pinned in the display plane
3286 * (e.g. libkms for the bootup splash), we have to ensure that we
3287 * always use map_and_fenceable for all scanout buffers.
3289 ret
= i915_gem_object_pin(obj
, alignment
, true, false);
3293 i915_gem_object_flush_cpu_write_domain(obj
);
3295 old_write_domain
= obj
->base
.write_domain
;
3296 old_read_domains
= obj
->base
.read_domains
;
3298 /* It should now be out of any other write domains, and we can update
3299 * the domain values for our changes.
3301 obj
->base
.write_domain
= 0;
3302 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
3304 trace_i915_gem_object_change_domain(obj
,
3312 i915_gem_object_finish_gpu(struct drm_i915_gem_object
*obj
)
3316 if ((obj
->base
.read_domains
& I915_GEM_GPU_DOMAINS
) == 0)
3319 ret
= i915_gem_object_wait_rendering(obj
, false);
3323 /* Ensure that we invalidate the GPU's caches and TLBs. */
3324 obj
->base
.read_domains
&= ~I915_GEM_GPU_DOMAINS
;
3329 * Moves a single object to the CPU read, and possibly write domain.
3331 * This function returns when the move is complete, including waiting on
3335 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
)
3337 uint32_t old_write_domain
, old_read_domains
;
3340 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_CPU
)
3343 ret
= i915_gem_object_wait_rendering(obj
, !write
);
3347 i915_gem_object_flush_gtt_write_domain(obj
);
3349 old_write_domain
= obj
->base
.write_domain
;
3350 old_read_domains
= obj
->base
.read_domains
;
3352 /* Flush the CPU cache if it's still invalid. */
3353 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) == 0) {
3354 i915_gem_clflush_object(obj
);
3356 obj
->base
.read_domains
|= I915_GEM_DOMAIN_CPU
;
3359 /* It should now be out of any other write domains, and we can update
3360 * the domain values for our changes.
3362 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
3364 /* If we're writing through the CPU, then the GPU read domains will
3365 * need to be invalidated at next use.
3368 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
3369 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
3372 trace_i915_gem_object_change_domain(obj
,
3379 /* Throttle our rendering by waiting until the ring has completed our requests
3380 * emitted over 20 msec ago.
3382 * Note that if we were to use the current jiffies each time around the loop,
3383 * we wouldn't escape the function with any frames outstanding if the time to
3384 * render a frame was over 20ms.
3386 * This should get us reasonable parallelism between CPU and GPU but also
3387 * relatively low latency when blocking on a particular request to finish.
3390 i915_gem_ring_throttle(struct drm_device
*dev
, struct drm_file
*file
)
3392 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3393 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
3394 unsigned long recent_enough
= jiffies
- msecs_to_jiffies(20);
3395 struct drm_i915_gem_request
*request
;
3396 struct intel_ring_buffer
*ring
= NULL
;
3400 ret
= i915_gem_wait_for_error(&dev_priv
->gpu_error
);
3404 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, false);
3408 spin_lock(&file_priv
->mm
.lock
);
3409 list_for_each_entry(request
, &file_priv
->mm
.request_list
, client_list
) {
3410 if (time_after_eq(request
->emitted_jiffies
, recent_enough
))
3413 ring
= request
->ring
;
3414 seqno
= request
->seqno
;
3416 spin_unlock(&file_priv
->mm
.lock
);
3421 ret
= __wait_seqno(ring
, seqno
, true, NULL
);
3423 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, 0);
3429 i915_gem_object_pin(struct drm_i915_gem_object
*obj
,
3431 bool map_and_fenceable
,
3436 if (WARN_ON(obj
->pin_count
== DRM_I915_GEM_OBJECT_MAX_PIN_COUNT
))
3439 if (obj
->gtt_space
!= NULL
) {
3440 if ((alignment
&& obj
->gtt_offset
& (alignment
- 1)) ||
3441 (map_and_fenceable
&& !obj
->map_and_fenceable
)) {
3442 WARN(obj
->pin_count
,
3443 "bo is already pinned with incorrect alignment:"
3444 " offset=%x, req.alignment=%x, req.map_and_fenceable=%d,"
3445 " obj->map_and_fenceable=%d\n",
3446 obj
->gtt_offset
, alignment
,
3448 obj
->map_and_fenceable
);
3449 ret
= i915_gem_object_unbind(obj
);
3455 if (obj
->gtt_space
== NULL
) {
3456 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
3458 ret
= i915_gem_object_bind_to_gtt(obj
, alignment
,
3464 if (!dev_priv
->mm
.aliasing_ppgtt
)
3465 i915_gem_gtt_bind_object(obj
, obj
->cache_level
);
3468 if (!obj
->has_global_gtt_mapping
&& map_and_fenceable
)
3469 i915_gem_gtt_bind_object(obj
, obj
->cache_level
);
3472 obj
->pin_mappable
|= map_and_fenceable
;
3478 i915_gem_object_unpin(struct drm_i915_gem_object
*obj
)
3480 BUG_ON(obj
->pin_count
== 0);
3481 BUG_ON(obj
->gtt_space
== NULL
);
3483 if (--obj
->pin_count
== 0)
3484 obj
->pin_mappable
= false;
3488 i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
3489 struct drm_file
*file
)
3491 struct drm_i915_gem_pin
*args
= data
;
3492 struct drm_i915_gem_object
*obj
;
3495 ret
= i915_mutex_lock_interruptible(dev
);
3499 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3500 if (&obj
->base
== NULL
) {
3505 if (obj
->madv
!= I915_MADV_WILLNEED
) {
3506 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3511 if (obj
->pin_filp
!= NULL
&& obj
->pin_filp
!= file
) {
3512 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3518 obj
->user_pin_count
++;
3519 obj
->pin_filp
= file
;
3520 if (obj
->user_pin_count
== 1) {
3521 ret
= i915_gem_object_pin(obj
, args
->alignment
, true, false);
3526 /* XXX - flush the CPU caches for pinned objects
3527 * as the X server doesn't manage domains yet
3529 i915_gem_object_flush_cpu_write_domain(obj
);
3530 args
->offset
= obj
->gtt_offset
;
3532 drm_gem_object_unreference(&obj
->base
);
3534 mutex_unlock(&dev
->struct_mutex
);
3539 i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
3540 struct drm_file
*file
)
3542 struct drm_i915_gem_pin
*args
= data
;
3543 struct drm_i915_gem_object
*obj
;
3546 ret
= i915_mutex_lock_interruptible(dev
);
3550 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3551 if (&obj
->base
== NULL
) {
3556 if (obj
->pin_filp
!= file
) {
3557 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3562 obj
->user_pin_count
--;
3563 if (obj
->user_pin_count
== 0) {
3564 obj
->pin_filp
= NULL
;
3565 i915_gem_object_unpin(obj
);
3569 drm_gem_object_unreference(&obj
->base
);
3571 mutex_unlock(&dev
->struct_mutex
);
3576 i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
3577 struct drm_file
*file
)
3579 struct drm_i915_gem_busy
*args
= data
;
3580 struct drm_i915_gem_object
*obj
;
3583 ret
= i915_mutex_lock_interruptible(dev
);
3587 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3588 if (&obj
->base
== NULL
) {
3593 /* Count all active objects as busy, even if they are currently not used
3594 * by the gpu. Users of this interface expect objects to eventually
3595 * become non-busy without any further actions, therefore emit any
3596 * necessary flushes here.
3598 ret
= i915_gem_object_flush_active(obj
);
3600 args
->busy
= obj
->active
;
3602 BUILD_BUG_ON(I915_NUM_RINGS
> 16);
3603 args
->busy
|= intel_ring_flag(obj
->ring
) << 16;
3606 drm_gem_object_unreference(&obj
->base
);
3608 mutex_unlock(&dev
->struct_mutex
);
3613 i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
3614 struct drm_file
*file_priv
)
3616 return i915_gem_ring_throttle(dev
, file_priv
);
3620 i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
3621 struct drm_file
*file_priv
)
3623 struct drm_i915_gem_madvise
*args
= data
;
3624 struct drm_i915_gem_object
*obj
;
3627 switch (args
->madv
) {
3628 case I915_MADV_DONTNEED
:
3629 case I915_MADV_WILLNEED
:
3635 ret
= i915_mutex_lock_interruptible(dev
);
3639 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file_priv
, args
->handle
));
3640 if (&obj
->base
== NULL
) {
3645 if (obj
->pin_count
) {
3650 if (obj
->madv
!= __I915_MADV_PURGED
)
3651 obj
->madv
= args
->madv
;
3653 /* if the object is no longer attached, discard its backing storage */
3654 if (i915_gem_object_is_purgeable(obj
) && obj
->pages
== NULL
)
3655 i915_gem_object_truncate(obj
);
3657 args
->retained
= obj
->madv
!= __I915_MADV_PURGED
;
3660 drm_gem_object_unreference(&obj
->base
);
3662 mutex_unlock(&dev
->struct_mutex
);
3666 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
3667 const struct drm_i915_gem_object_ops
*ops
)
3669 INIT_LIST_HEAD(&obj
->mm_list
);
3670 INIT_LIST_HEAD(&obj
->gtt_list
);
3671 INIT_LIST_HEAD(&obj
->ring_list
);
3672 INIT_LIST_HEAD(&obj
->exec_list
);
3676 obj
->fence_reg
= I915_FENCE_REG_NONE
;
3677 obj
->madv
= I915_MADV_WILLNEED
;
3678 /* Avoid an unnecessary call to unbind on the first bind. */
3679 obj
->map_and_fenceable
= true;
3681 i915_gem_info_add_obj(obj
->base
.dev
->dev_private
, obj
->base
.size
);
3684 static const struct drm_i915_gem_object_ops i915_gem_object_ops
= {
3685 .get_pages
= i915_gem_object_get_pages_gtt
,
3686 .put_pages
= i915_gem_object_put_pages_gtt
,
3689 struct drm_i915_gem_object
*i915_gem_alloc_object(struct drm_device
*dev
,
3692 struct drm_i915_gem_object
*obj
;
3693 struct address_space
*mapping
;
3696 obj
= i915_gem_object_alloc(dev
);
3700 if (drm_gem_object_init(dev
, &obj
->base
, size
) != 0) {
3701 i915_gem_object_free(obj
);
3705 mask
= GFP_HIGHUSER
| __GFP_RECLAIMABLE
;
3706 if (IS_CRESTLINE(dev
) || IS_BROADWATER(dev
)) {
3707 /* 965gm cannot relocate objects above 4GiB. */
3708 mask
&= ~__GFP_HIGHMEM
;
3709 mask
|= __GFP_DMA32
;
3712 mapping
= obj
->base
.filp
->f_path
.dentry
->d_inode
->i_mapping
;
3713 mapping_set_gfp_mask(mapping
, mask
);
3715 i915_gem_object_init(obj
, &i915_gem_object_ops
);
3717 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
3718 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
3721 /* On some devices, we can have the GPU use the LLC (the CPU
3722 * cache) for about a 10% performance improvement
3723 * compared to uncached. Graphics requests other than
3724 * display scanout are coherent with the CPU in
3725 * accessing this cache. This means in this mode we
3726 * don't need to clflush on the CPU side, and on the
3727 * GPU side we only need to flush internal caches to
3728 * get data visible to the CPU.
3730 * However, we maintain the display planes as UC, and so
3731 * need to rebind when first used as such.
3733 obj
->cache_level
= I915_CACHE_LLC
;
3735 obj
->cache_level
= I915_CACHE_NONE
;
3740 int i915_gem_init_object(struct drm_gem_object
*obj
)
3747 void i915_gem_free_object(struct drm_gem_object
*gem_obj
)
3749 struct drm_i915_gem_object
*obj
= to_intel_bo(gem_obj
);
3750 struct drm_device
*dev
= obj
->base
.dev
;
3751 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3753 trace_i915_gem_object_destroy(obj
);
3756 i915_gem_detach_phys_object(dev
, obj
);
3759 if (WARN_ON(i915_gem_object_unbind(obj
) == -ERESTARTSYS
)) {
3760 bool was_interruptible
;
3762 was_interruptible
= dev_priv
->mm
.interruptible
;
3763 dev_priv
->mm
.interruptible
= false;
3765 WARN_ON(i915_gem_object_unbind(obj
));
3767 dev_priv
->mm
.interruptible
= was_interruptible
;
3770 obj
->pages_pin_count
= 0;
3771 i915_gem_object_put_pages(obj
);
3772 i915_gem_object_free_mmap_offset(obj
);
3773 i915_gem_object_release_stolen(obj
);
3777 if (obj
->base
.import_attach
)
3778 drm_prime_gem_destroy(&obj
->base
, NULL
);
3780 drm_gem_object_release(&obj
->base
);
3781 i915_gem_info_remove_obj(dev_priv
, obj
->base
.size
);
3784 i915_gem_object_free(obj
);
3788 i915_gem_idle(struct drm_device
*dev
)
3790 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3793 mutex_lock(&dev
->struct_mutex
);
3795 if (dev_priv
->mm
.suspended
) {
3796 mutex_unlock(&dev
->struct_mutex
);
3800 ret
= i915_gpu_idle(dev
);
3802 mutex_unlock(&dev
->struct_mutex
);
3805 i915_gem_retire_requests(dev
);
3807 /* Under UMS, be paranoid and evict. */
3808 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
3809 i915_gem_evict_everything(dev
);
3811 i915_gem_reset_fences(dev
);
3813 /* Hack! Don't let anybody do execbuf while we don't control the chip.
3814 * We need to replace this with a semaphore, or something.
3815 * And not confound mm.suspended!
3817 dev_priv
->mm
.suspended
= 1;
3818 del_timer_sync(&dev_priv
->gpu_error
.hangcheck_timer
);
3820 i915_kernel_lost_context(dev
);
3821 i915_gem_cleanup_ringbuffer(dev
);
3823 mutex_unlock(&dev
->struct_mutex
);
3825 /* Cancel the retire work handler, which should be idle now. */
3826 cancel_delayed_work_sync(&dev_priv
->mm
.retire_work
);
3831 void i915_gem_l3_remap(struct drm_device
*dev
)
3833 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3837 if (!IS_IVYBRIDGE(dev
))
3840 if (!dev_priv
->l3_parity
.remap_info
)
3843 misccpctl
= I915_READ(GEN7_MISCCPCTL
);
3844 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
& ~GEN7_DOP_CLOCK_GATE_ENABLE
);
3845 POSTING_READ(GEN7_MISCCPCTL
);
3847 for (i
= 0; i
< GEN7_L3LOG_SIZE
; i
+= 4) {
3848 u32 remap
= I915_READ(GEN7_L3LOG_BASE
+ i
);
3849 if (remap
&& remap
!= dev_priv
->l3_parity
.remap_info
[i
/4])
3850 DRM_DEBUG("0x%x was already programmed to %x\n",
3851 GEN7_L3LOG_BASE
+ i
, remap
);
3852 if (remap
&& !dev_priv
->l3_parity
.remap_info
[i
/4])
3853 DRM_DEBUG_DRIVER("Clearing remapped register\n");
3854 I915_WRITE(GEN7_L3LOG_BASE
+ i
, dev_priv
->l3_parity
.remap_info
[i
/4]);
3857 /* Make sure all the writes land before disabling dop clock gating */
3858 POSTING_READ(GEN7_L3LOG_BASE
);
3860 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
);
3863 void i915_gem_init_swizzling(struct drm_device
*dev
)
3865 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3867 if (INTEL_INFO(dev
)->gen
< 5 ||
3868 dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_NONE
)
3871 I915_WRITE(DISP_ARB_CTL
, I915_READ(DISP_ARB_CTL
) |
3872 DISP_TILE_SURFACE_SWIZZLING
);
3877 I915_WRITE(TILECTL
, I915_READ(TILECTL
) | TILECTL_SWZCTL
);
3879 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB
));
3880 else if (IS_GEN7(dev
))
3881 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB
));
3887 intel_enable_blt(struct drm_device
*dev
)
3892 /* The blitter was dysfunctional on early prototypes */
3893 if (IS_GEN6(dev
) && dev
->pdev
->revision
< 8) {
3894 DRM_INFO("BLT not supported on this pre-production hardware;"
3895 " graphics performance will be degraded.\n");
3903 i915_gem_init_hw(struct drm_device
*dev
)
3905 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3908 if (INTEL_INFO(dev
)->gen
< 6 && !intel_enable_gtt())
3911 if (IS_HASWELL(dev
) && (I915_READ(0x120010) == 1))
3912 I915_WRITE(0x9008, I915_READ(0x9008) | 0xf0000);
3914 i915_gem_l3_remap(dev
);
3916 i915_gem_init_swizzling(dev
);
3918 dev_priv
->next_seqno
= dev_priv
->last_seqno
= (u32
)~0 - 0x1000;
3920 ret
= intel_init_render_ring_buffer(dev
);
3925 ret
= intel_init_bsd_ring_buffer(dev
);
3927 goto cleanup_render_ring
;
3930 if (intel_enable_blt(dev
)) {
3931 ret
= intel_init_blt_ring_buffer(dev
);
3933 goto cleanup_bsd_ring
;
3937 * XXX: There was some w/a described somewhere suggesting loading
3938 * contexts before PPGTT.
3940 i915_gem_context_init(dev
);
3941 i915_gem_init_ppgtt(dev
);
3946 intel_cleanup_ring_buffer(&dev_priv
->ring
[VCS
]);
3947 cleanup_render_ring
:
3948 intel_cleanup_ring_buffer(&dev_priv
->ring
[RCS
]);
3952 int i915_gem_init(struct drm_device
*dev
)
3954 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3957 mutex_lock(&dev
->struct_mutex
);
3958 i915_gem_init_global_gtt(dev
);
3959 ret
= i915_gem_init_hw(dev
);
3960 mutex_unlock(&dev
->struct_mutex
);
3962 i915_gem_cleanup_aliasing_ppgtt(dev
);
3966 /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */
3967 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
3968 dev_priv
->dri1
.allow_batchbuffer
= 1;
3973 i915_gem_cleanup_ringbuffer(struct drm_device
*dev
)
3975 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3976 struct intel_ring_buffer
*ring
;
3979 for_each_ring(ring
, dev_priv
, i
)
3980 intel_cleanup_ring_buffer(ring
);
3984 i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
3985 struct drm_file
*file_priv
)
3987 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3990 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
3993 if (i915_reset_in_progress(&dev_priv
->gpu_error
)) {
3994 DRM_ERROR("Reenabling wedged hardware, good luck\n");
3995 atomic_set(&dev_priv
->gpu_error
.reset_counter
, 0);
3998 mutex_lock(&dev
->struct_mutex
);
3999 dev_priv
->mm
.suspended
= 0;
4001 ret
= i915_gem_init_hw(dev
);
4003 mutex_unlock(&dev
->struct_mutex
);
4007 BUG_ON(!list_empty(&dev_priv
->mm
.active_list
));
4008 mutex_unlock(&dev
->struct_mutex
);
4010 ret
= drm_irq_install(dev
);
4012 goto cleanup_ringbuffer
;
4017 mutex_lock(&dev
->struct_mutex
);
4018 i915_gem_cleanup_ringbuffer(dev
);
4019 dev_priv
->mm
.suspended
= 1;
4020 mutex_unlock(&dev
->struct_mutex
);
4026 i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
4027 struct drm_file
*file_priv
)
4029 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4032 drm_irq_uninstall(dev
);
4033 return i915_gem_idle(dev
);
4037 i915_gem_lastclose(struct drm_device
*dev
)
4041 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4044 ret
= i915_gem_idle(dev
);
4046 DRM_ERROR("failed to idle hardware: %d\n", ret
);
4050 init_ring_lists(struct intel_ring_buffer
*ring
)
4052 INIT_LIST_HEAD(&ring
->active_list
);
4053 INIT_LIST_HEAD(&ring
->request_list
);
4057 i915_gem_load(struct drm_device
*dev
)
4059 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4063 kmem_cache_create("i915_gem_object",
4064 sizeof(struct drm_i915_gem_object
), 0,
4068 INIT_LIST_HEAD(&dev_priv
->mm
.active_list
);
4069 INIT_LIST_HEAD(&dev_priv
->mm
.inactive_list
);
4070 INIT_LIST_HEAD(&dev_priv
->mm
.unbound_list
);
4071 INIT_LIST_HEAD(&dev_priv
->mm
.bound_list
);
4072 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
4073 for (i
= 0; i
< I915_NUM_RINGS
; i
++)
4074 init_ring_lists(&dev_priv
->ring
[i
]);
4075 for (i
= 0; i
< I915_MAX_NUM_FENCES
; i
++)
4076 INIT_LIST_HEAD(&dev_priv
->fence_regs
[i
].lru_list
);
4077 INIT_DELAYED_WORK(&dev_priv
->mm
.retire_work
,
4078 i915_gem_retire_work_handler
);
4079 init_waitqueue_head(&dev_priv
->gpu_error
.reset_queue
);
4081 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4083 I915_WRITE(MI_ARB_STATE
,
4084 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE
));
4087 dev_priv
->relative_constants_mode
= I915_EXEC_CONSTANTS_REL_GENERAL
;
4089 /* Old X drivers will take 0-2 for front, back, depth buffers */
4090 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
4091 dev_priv
->fence_reg_start
= 3;
4093 if (INTEL_INFO(dev
)->gen
>= 4 || IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
4094 dev_priv
->num_fence_regs
= 16;
4096 dev_priv
->num_fence_regs
= 8;
4098 /* Initialize fence registers to zero */
4099 i915_gem_reset_fences(dev
);
4101 i915_gem_detect_bit_6_swizzle(dev
);
4102 init_waitqueue_head(&dev_priv
->pending_flip_queue
);
4104 dev_priv
->mm
.interruptible
= true;
4106 dev_priv
->mm
.inactive_shrinker
.shrink
= i915_gem_inactive_shrink
;
4107 dev_priv
->mm
.inactive_shrinker
.seeks
= DEFAULT_SEEKS
;
4108 register_shrinker(&dev_priv
->mm
.inactive_shrinker
);
4112 * Create a physically contiguous memory object for this object
4113 * e.g. for cursor + overlay regs
4115 static int i915_gem_init_phys_object(struct drm_device
*dev
,
4116 int id
, int size
, int align
)
4118 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4119 struct drm_i915_gem_phys_object
*phys_obj
;
4122 if (dev_priv
->mm
.phys_objs
[id
- 1] || !size
)
4125 phys_obj
= kzalloc(sizeof(struct drm_i915_gem_phys_object
), GFP_KERNEL
);
4131 phys_obj
->handle
= drm_pci_alloc(dev
, size
, align
);
4132 if (!phys_obj
->handle
) {
4137 set_memory_wc((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
4140 dev_priv
->mm
.phys_objs
[id
- 1] = phys_obj
;
4148 static void i915_gem_free_phys_object(struct drm_device
*dev
, int id
)
4150 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4151 struct drm_i915_gem_phys_object
*phys_obj
;
4153 if (!dev_priv
->mm
.phys_objs
[id
- 1])
4156 phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
4157 if (phys_obj
->cur_obj
) {
4158 i915_gem_detach_phys_object(dev
, phys_obj
->cur_obj
);
4162 set_memory_wb((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
4164 drm_pci_free(dev
, phys_obj
->handle
);
4166 dev_priv
->mm
.phys_objs
[id
- 1] = NULL
;
4169 void i915_gem_free_all_phys_object(struct drm_device
*dev
)
4173 for (i
= I915_GEM_PHYS_CURSOR_0
; i
<= I915_MAX_PHYS_OBJECT
; i
++)
4174 i915_gem_free_phys_object(dev
, i
);
4177 void i915_gem_detach_phys_object(struct drm_device
*dev
,
4178 struct drm_i915_gem_object
*obj
)
4180 struct address_space
*mapping
= obj
->base
.filp
->f_path
.dentry
->d_inode
->i_mapping
;
4187 vaddr
= obj
->phys_obj
->handle
->vaddr
;
4189 page_count
= obj
->base
.size
/ PAGE_SIZE
;
4190 for (i
= 0; i
< page_count
; i
++) {
4191 struct page
*page
= shmem_read_mapping_page(mapping
, i
);
4192 if (!IS_ERR(page
)) {
4193 char *dst
= kmap_atomic(page
);
4194 memcpy(dst
, vaddr
+ i
*PAGE_SIZE
, PAGE_SIZE
);
4197 drm_clflush_pages(&page
, 1);
4199 set_page_dirty(page
);
4200 mark_page_accessed(page
);
4201 page_cache_release(page
);
4204 i915_gem_chipset_flush(dev
);
4206 obj
->phys_obj
->cur_obj
= NULL
;
4207 obj
->phys_obj
= NULL
;
4211 i915_gem_attach_phys_object(struct drm_device
*dev
,
4212 struct drm_i915_gem_object
*obj
,
4216 struct address_space
*mapping
= obj
->base
.filp
->f_path
.dentry
->d_inode
->i_mapping
;
4217 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4222 if (id
> I915_MAX_PHYS_OBJECT
)
4225 if (obj
->phys_obj
) {
4226 if (obj
->phys_obj
->id
== id
)
4228 i915_gem_detach_phys_object(dev
, obj
);
4231 /* create a new object */
4232 if (!dev_priv
->mm
.phys_objs
[id
- 1]) {
4233 ret
= i915_gem_init_phys_object(dev
, id
,
4234 obj
->base
.size
, align
);
4236 DRM_ERROR("failed to init phys object %d size: %zu\n",
4237 id
, obj
->base
.size
);
4242 /* bind to the object */
4243 obj
->phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
4244 obj
->phys_obj
->cur_obj
= obj
;
4246 page_count
= obj
->base
.size
/ PAGE_SIZE
;
4248 for (i
= 0; i
< page_count
; i
++) {
4252 page
= shmem_read_mapping_page(mapping
, i
);
4254 return PTR_ERR(page
);
4256 src
= kmap_atomic(page
);
4257 dst
= obj
->phys_obj
->handle
->vaddr
+ (i
* PAGE_SIZE
);
4258 memcpy(dst
, src
, PAGE_SIZE
);
4261 mark_page_accessed(page
);
4262 page_cache_release(page
);
4269 i915_gem_phys_pwrite(struct drm_device
*dev
,
4270 struct drm_i915_gem_object
*obj
,
4271 struct drm_i915_gem_pwrite
*args
,
4272 struct drm_file
*file_priv
)
4274 void *vaddr
= obj
->phys_obj
->handle
->vaddr
+ args
->offset
;
4275 char __user
*user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
4277 if (__copy_from_user_inatomic_nocache(vaddr
, user_data
, args
->size
)) {
4278 unsigned long unwritten
;
4280 /* The physical object once assigned is fixed for the lifetime
4281 * of the obj, so we can safely drop the lock and continue
4284 mutex_unlock(&dev
->struct_mutex
);
4285 unwritten
= copy_from_user(vaddr
, user_data
, args
->size
);
4286 mutex_lock(&dev
->struct_mutex
);
4291 i915_gem_chipset_flush(dev
);
4295 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
)
4297 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
4299 /* Clean up our request list when the client is going away, so that
4300 * later retire_requests won't dereference our soon-to-be-gone
4303 spin_lock(&file_priv
->mm
.lock
);
4304 while (!list_empty(&file_priv
->mm
.request_list
)) {
4305 struct drm_i915_gem_request
*request
;
4307 request
= list_first_entry(&file_priv
->mm
.request_list
,
4308 struct drm_i915_gem_request
,
4310 list_del(&request
->client_list
);
4311 request
->file_priv
= NULL
;
4313 spin_unlock(&file_priv
->mm
.lock
);
4316 static bool mutex_is_locked_by(struct mutex
*mutex
, struct task_struct
*task
)
4318 if (!mutex_is_locked(mutex
))
4321 #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES)
4322 return mutex
->owner
== task
;
4324 /* Since UP may be pre-empted, we cannot assume that we own the lock */
4330 i915_gem_inactive_shrink(struct shrinker
*shrinker
, struct shrink_control
*sc
)
4332 struct drm_i915_private
*dev_priv
=
4333 container_of(shrinker
,
4334 struct drm_i915_private
,
4335 mm
.inactive_shrinker
);
4336 struct drm_device
*dev
= dev_priv
->dev
;
4337 struct drm_i915_gem_object
*obj
;
4338 int nr_to_scan
= sc
->nr_to_scan
;
4342 if (!mutex_trylock(&dev
->struct_mutex
)) {
4343 if (!mutex_is_locked_by(&dev
->struct_mutex
, current
))
4346 if (dev_priv
->mm
.shrinker_no_lock_stealing
)
4353 nr_to_scan
-= i915_gem_purge(dev_priv
, nr_to_scan
);
4355 i915_gem_shrink_all(dev_priv
);
4359 list_for_each_entry(obj
, &dev_priv
->mm
.unbound_list
, gtt_list
)
4360 if (obj
->pages_pin_count
== 0)
4361 cnt
+= obj
->base
.size
>> PAGE_SHIFT
;
4362 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, gtt_list
)
4363 if (obj
->pin_count
== 0 && obj
->pages_pin_count
== 0)
4364 cnt
+= obj
->base
.size
>> PAGE_SHIFT
;
4367 mutex_unlock(&dev
->struct_mutex
);