2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/i915_drm.h>
31 #include "i915_trace.h"
32 #include "intel_drv.h"
33 #include <linux/shmem_fs.h>
34 #include <linux/slab.h>
35 #include <linux/swap.h>
36 #include <linux/pci.h>
37 #include <linux/dma-buf.h>
39 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
);
40 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
);
41 static __must_check
int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object
*obj
,
43 bool map_and_fenceable
,
45 static int i915_gem_phys_pwrite(struct drm_device
*dev
,
46 struct drm_i915_gem_object
*obj
,
47 struct drm_i915_gem_pwrite
*args
,
48 struct drm_file
*file
);
50 static void i915_gem_write_fence(struct drm_device
*dev
, int reg
,
51 struct drm_i915_gem_object
*obj
);
52 static void i915_gem_object_update_fence(struct drm_i915_gem_object
*obj
,
53 struct drm_i915_fence_reg
*fence
,
56 static int i915_gem_inactive_shrink(struct shrinker
*shrinker
,
57 struct shrink_control
*sc
);
58 static long i915_gem_purge(struct drm_i915_private
*dev_priv
, long target
);
59 static void i915_gem_shrink_all(struct drm_i915_private
*dev_priv
);
60 static void i915_gem_object_truncate(struct drm_i915_gem_object
*obj
);
62 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object
*obj
)
65 i915_gem_release_mmap(obj
);
67 /* As we do not have an associated fence register, we will force
68 * a tiling change if we ever need to acquire one.
70 obj
->fence_dirty
= false;
71 obj
->fence_reg
= I915_FENCE_REG_NONE
;
74 /* some bookkeeping */
75 static void i915_gem_info_add_obj(struct drm_i915_private
*dev_priv
,
78 dev_priv
->mm
.object_count
++;
79 dev_priv
->mm
.object_memory
+= size
;
82 static void i915_gem_info_remove_obj(struct drm_i915_private
*dev_priv
,
85 dev_priv
->mm
.object_count
--;
86 dev_priv
->mm
.object_memory
-= size
;
90 i915_gem_wait_for_error(struct i915_gpu_error
*error
)
94 #define EXIT_COND (!i915_reset_in_progress(error))
98 /* GPU is already declared terminally dead, give up. */
99 if (i915_terminally_wedged(error
))
103 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
104 * userspace. If it takes that long something really bad is going on and
105 * we should simply try to bail out and fail as gracefully as possible.
107 ret
= wait_event_interruptible_timeout(error
->reset_queue
,
111 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
113 } else if (ret
< 0) {
121 int i915_mutex_lock_interruptible(struct drm_device
*dev
)
123 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
126 ret
= i915_gem_wait_for_error(&dev_priv
->gpu_error
);
130 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
134 WARN_ON(i915_verify_lists(dev
));
139 i915_gem_object_is_inactive(struct drm_i915_gem_object
*obj
)
141 return obj
->gtt_space
&& !obj
->active
;
145 i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
146 struct drm_file
*file
)
148 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
149 struct drm_i915_gem_init
*args
= data
;
151 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
154 if (args
->gtt_start
>= args
->gtt_end
||
155 (args
->gtt_end
| args
->gtt_start
) & (PAGE_SIZE
- 1))
158 /* GEM with user mode setting was never supported on ilk and later. */
159 if (INTEL_INFO(dev
)->gen
>= 5)
162 mutex_lock(&dev
->struct_mutex
);
163 i915_gem_setup_global_gtt(dev
, args
->gtt_start
, args
->gtt_end
,
165 dev_priv
->gtt
.mappable_end
= args
->gtt_end
;
166 mutex_unlock(&dev
->struct_mutex
);
172 i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
173 struct drm_file
*file
)
175 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
176 struct drm_i915_gem_get_aperture
*args
= data
;
177 struct drm_i915_gem_object
*obj
;
181 mutex_lock(&dev
->struct_mutex
);
182 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, gtt_list
)
184 pinned
+= obj
->gtt_space
->size
;
185 mutex_unlock(&dev
->struct_mutex
);
187 args
->aper_size
= dev_priv
->gtt
.total
;
188 args
->aper_available_size
= args
->aper_size
- pinned
;
193 void *i915_gem_object_alloc(struct drm_device
*dev
)
195 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
196 return kmem_cache_alloc(dev_priv
->slab
, GFP_KERNEL
| __GFP_ZERO
);
199 void i915_gem_object_free(struct drm_i915_gem_object
*obj
)
201 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
202 kmem_cache_free(dev_priv
->slab
, obj
);
206 i915_gem_create(struct drm_file
*file
,
207 struct drm_device
*dev
,
211 struct drm_i915_gem_object
*obj
;
215 size
= roundup(size
, PAGE_SIZE
);
219 /* Allocate the new object */
220 obj
= i915_gem_alloc_object(dev
, size
);
224 ret
= drm_gem_handle_create(file
, &obj
->base
, &handle
);
226 drm_gem_object_release(&obj
->base
);
227 i915_gem_info_remove_obj(dev
->dev_private
, obj
->base
.size
);
228 i915_gem_object_free(obj
);
232 /* drop reference from allocate - handle holds it now */
233 drm_gem_object_unreference(&obj
->base
);
234 trace_i915_gem_object_create(obj
);
241 i915_gem_dumb_create(struct drm_file
*file
,
242 struct drm_device
*dev
,
243 struct drm_mode_create_dumb
*args
)
245 /* have to work out size/pitch and return them */
246 args
->pitch
= ALIGN(args
->width
* ((args
->bpp
+ 7) / 8), 64);
247 args
->size
= args
->pitch
* args
->height
;
248 return i915_gem_create(file
, dev
,
249 args
->size
, &args
->handle
);
252 int i915_gem_dumb_destroy(struct drm_file
*file
,
253 struct drm_device
*dev
,
256 return drm_gem_handle_delete(file
, handle
);
260 * Creates a new mm object and returns a handle to it.
263 i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
264 struct drm_file
*file
)
266 struct drm_i915_gem_create
*args
= data
;
268 return i915_gem_create(file
, dev
,
269 args
->size
, &args
->handle
);
273 __copy_to_user_swizzled(char __user
*cpu_vaddr
,
274 const char *gpu_vaddr
, int gpu_offset
,
277 int ret
, cpu_offset
= 0;
280 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
281 int this_length
= min(cacheline_end
- gpu_offset
, length
);
282 int swizzled_gpu_offset
= gpu_offset
^ 64;
284 ret
= __copy_to_user(cpu_vaddr
+ cpu_offset
,
285 gpu_vaddr
+ swizzled_gpu_offset
,
290 cpu_offset
+= this_length
;
291 gpu_offset
+= this_length
;
292 length
-= this_length
;
299 __copy_from_user_swizzled(char *gpu_vaddr
, int gpu_offset
,
300 const char __user
*cpu_vaddr
,
303 int ret
, cpu_offset
= 0;
306 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
307 int this_length
= min(cacheline_end
- gpu_offset
, length
);
308 int swizzled_gpu_offset
= gpu_offset
^ 64;
310 ret
= __copy_from_user(gpu_vaddr
+ swizzled_gpu_offset
,
311 cpu_vaddr
+ cpu_offset
,
316 cpu_offset
+= this_length
;
317 gpu_offset
+= this_length
;
318 length
-= this_length
;
324 /* Per-page copy function for the shmem pread fastpath.
325 * Flushes invalid cachelines before reading the target if
326 * needs_clflush is set. */
328 shmem_pread_fast(struct page
*page
, int shmem_page_offset
, int page_length
,
329 char __user
*user_data
,
330 bool page_do_bit17_swizzling
, bool needs_clflush
)
335 if (unlikely(page_do_bit17_swizzling
))
338 vaddr
= kmap_atomic(page
);
340 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
342 ret
= __copy_to_user_inatomic(user_data
,
343 vaddr
+ shmem_page_offset
,
345 kunmap_atomic(vaddr
);
347 return ret
? -EFAULT
: 0;
351 shmem_clflush_swizzled_range(char *addr
, unsigned long length
,
354 if (unlikely(swizzled
)) {
355 unsigned long start
= (unsigned long) addr
;
356 unsigned long end
= (unsigned long) addr
+ length
;
358 /* For swizzling simply ensure that we always flush both
359 * channels. Lame, but simple and it works. Swizzled
360 * pwrite/pread is far from a hotpath - current userspace
361 * doesn't use it at all. */
362 start
= round_down(start
, 128);
363 end
= round_up(end
, 128);
365 drm_clflush_virt_range((void *)start
, end
- start
);
367 drm_clflush_virt_range(addr
, length
);
372 /* Only difference to the fast-path function is that this can handle bit17
373 * and uses non-atomic copy and kmap functions. */
375 shmem_pread_slow(struct page
*page
, int shmem_page_offset
, int page_length
,
376 char __user
*user_data
,
377 bool page_do_bit17_swizzling
, bool needs_clflush
)
384 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
386 page_do_bit17_swizzling
);
388 if (page_do_bit17_swizzling
)
389 ret
= __copy_to_user_swizzled(user_data
,
390 vaddr
, shmem_page_offset
,
393 ret
= __copy_to_user(user_data
,
394 vaddr
+ shmem_page_offset
,
398 return ret
? - EFAULT
: 0;
402 i915_gem_shmem_pread(struct drm_device
*dev
,
403 struct drm_i915_gem_object
*obj
,
404 struct drm_i915_gem_pread
*args
,
405 struct drm_file
*file
)
407 char __user
*user_data
;
410 int shmem_page_offset
, page_length
, ret
= 0;
411 int obj_do_bit17_swizzling
, page_do_bit17_swizzling
;
413 int needs_clflush
= 0;
414 struct sg_page_iter sg_iter
;
416 user_data
= to_user_ptr(args
->data_ptr
);
419 obj_do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
421 if (!(obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
)) {
422 /* If we're not in the cpu read domain, set ourself into the gtt
423 * read domain and manually flush cachelines (if required). This
424 * optimizes for the case when the gpu will dirty the data
425 * anyway again before the next pread happens. */
426 if (obj
->cache_level
== I915_CACHE_NONE
)
428 if (obj
->gtt_space
) {
429 ret
= i915_gem_object_set_to_gtt_domain(obj
, false);
435 ret
= i915_gem_object_get_pages(obj
);
439 i915_gem_object_pin_pages(obj
);
441 offset
= args
->offset
;
443 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
,
444 offset
>> PAGE_SHIFT
) {
445 struct page
*page
= sg_page_iter_page(&sg_iter
);
450 /* Operation in this page
452 * shmem_page_offset = offset within page in shmem file
453 * page_length = bytes to copy for this page
455 shmem_page_offset
= offset_in_page(offset
);
456 page_length
= remain
;
457 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
458 page_length
= PAGE_SIZE
- shmem_page_offset
;
460 page_do_bit17_swizzling
= obj_do_bit17_swizzling
&&
461 (page_to_phys(page
) & (1 << 17)) != 0;
463 ret
= shmem_pread_fast(page
, shmem_page_offset
, page_length
,
464 user_data
, page_do_bit17_swizzling
,
469 mutex_unlock(&dev
->struct_mutex
);
472 ret
= fault_in_multipages_writeable(user_data
, remain
);
473 /* Userspace is tricking us, but we've already clobbered
474 * its pages with the prefault and promised to write the
475 * data up to the first fault. Hence ignore any errors
476 * and just continue. */
481 ret
= shmem_pread_slow(page
, shmem_page_offset
, page_length
,
482 user_data
, page_do_bit17_swizzling
,
485 mutex_lock(&dev
->struct_mutex
);
488 mark_page_accessed(page
);
493 remain
-= page_length
;
494 user_data
+= page_length
;
495 offset
+= page_length
;
499 i915_gem_object_unpin_pages(obj
);
505 * Reads data from the object referenced by handle.
507 * On error, the contents of *data are undefined.
510 i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
511 struct drm_file
*file
)
513 struct drm_i915_gem_pread
*args
= data
;
514 struct drm_i915_gem_object
*obj
;
520 if (!access_ok(VERIFY_WRITE
,
521 to_user_ptr(args
->data_ptr
),
525 ret
= i915_mutex_lock_interruptible(dev
);
529 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
530 if (&obj
->base
== NULL
) {
535 /* Bounds check source. */
536 if (args
->offset
> obj
->base
.size
||
537 args
->size
> obj
->base
.size
- args
->offset
) {
542 /* prime objects have no backing filp to GEM pread/pwrite
545 if (!obj
->base
.filp
) {
550 trace_i915_gem_object_pread(obj
, args
->offset
, args
->size
);
552 ret
= i915_gem_shmem_pread(dev
, obj
, args
, file
);
555 drm_gem_object_unreference(&obj
->base
);
557 mutex_unlock(&dev
->struct_mutex
);
561 /* This is the fast write path which cannot handle
562 * page faults in the source data
566 fast_user_write(struct io_mapping
*mapping
,
567 loff_t page_base
, int page_offset
,
568 char __user
*user_data
,
571 void __iomem
*vaddr_atomic
;
573 unsigned long unwritten
;
575 vaddr_atomic
= io_mapping_map_atomic_wc(mapping
, page_base
);
576 /* We can use the cpu mem copy function because this is X86. */
577 vaddr
= (void __force
*)vaddr_atomic
+ page_offset
;
578 unwritten
= __copy_from_user_inatomic_nocache(vaddr
,
580 io_mapping_unmap_atomic(vaddr_atomic
);
585 * This is the fast pwrite path, where we copy the data directly from the
586 * user into the GTT, uncached.
589 i915_gem_gtt_pwrite_fast(struct drm_device
*dev
,
590 struct drm_i915_gem_object
*obj
,
591 struct drm_i915_gem_pwrite
*args
,
592 struct drm_file
*file
)
594 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
596 loff_t offset
, page_base
;
597 char __user
*user_data
;
598 int page_offset
, page_length
, ret
;
600 ret
= i915_gem_object_pin(obj
, 0, true, true);
604 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
608 ret
= i915_gem_object_put_fence(obj
);
612 user_data
= to_user_ptr(args
->data_ptr
);
615 offset
= obj
->gtt_offset
+ args
->offset
;
618 /* Operation in this page
620 * page_base = page offset within aperture
621 * page_offset = offset within page
622 * page_length = bytes to copy for this page
624 page_base
= offset
& PAGE_MASK
;
625 page_offset
= offset_in_page(offset
);
626 page_length
= remain
;
627 if ((page_offset
+ remain
) > PAGE_SIZE
)
628 page_length
= PAGE_SIZE
- page_offset
;
630 /* If we get a fault while copying data, then (presumably) our
631 * source page isn't available. Return the error and we'll
632 * retry in the slow path.
634 if (fast_user_write(dev_priv
->gtt
.mappable
, page_base
,
635 page_offset
, user_data
, page_length
)) {
640 remain
-= page_length
;
641 user_data
+= page_length
;
642 offset
+= page_length
;
646 i915_gem_object_unpin(obj
);
651 /* Per-page copy function for the shmem pwrite fastpath.
652 * Flushes invalid cachelines before writing to the target if
653 * needs_clflush_before is set and flushes out any written cachelines after
654 * writing if needs_clflush is set. */
656 shmem_pwrite_fast(struct page
*page
, int shmem_page_offset
, int page_length
,
657 char __user
*user_data
,
658 bool page_do_bit17_swizzling
,
659 bool needs_clflush_before
,
660 bool needs_clflush_after
)
665 if (unlikely(page_do_bit17_swizzling
))
668 vaddr
= kmap_atomic(page
);
669 if (needs_clflush_before
)
670 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
672 ret
= __copy_from_user_inatomic_nocache(vaddr
+ shmem_page_offset
,
675 if (needs_clflush_after
)
676 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
678 kunmap_atomic(vaddr
);
680 return ret
? -EFAULT
: 0;
683 /* Only difference to the fast-path function is that this can handle bit17
684 * and uses non-atomic copy and kmap functions. */
686 shmem_pwrite_slow(struct page
*page
, int shmem_page_offset
, int page_length
,
687 char __user
*user_data
,
688 bool page_do_bit17_swizzling
,
689 bool needs_clflush_before
,
690 bool needs_clflush_after
)
696 if (unlikely(needs_clflush_before
|| page_do_bit17_swizzling
))
697 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
699 page_do_bit17_swizzling
);
700 if (page_do_bit17_swizzling
)
701 ret
= __copy_from_user_swizzled(vaddr
, shmem_page_offset
,
705 ret
= __copy_from_user(vaddr
+ shmem_page_offset
,
708 if (needs_clflush_after
)
709 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
711 page_do_bit17_swizzling
);
714 return ret
? -EFAULT
: 0;
718 i915_gem_shmem_pwrite(struct drm_device
*dev
,
719 struct drm_i915_gem_object
*obj
,
720 struct drm_i915_gem_pwrite
*args
,
721 struct drm_file
*file
)
725 char __user
*user_data
;
726 int shmem_page_offset
, page_length
, ret
= 0;
727 int obj_do_bit17_swizzling
, page_do_bit17_swizzling
;
728 int hit_slowpath
= 0;
729 int needs_clflush_after
= 0;
730 int needs_clflush_before
= 0;
731 struct sg_page_iter sg_iter
;
733 user_data
= to_user_ptr(args
->data_ptr
);
736 obj_do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
738 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
739 /* If we're not in the cpu write domain, set ourself into the gtt
740 * write domain and manually flush cachelines (if required). This
741 * optimizes for the case when the gpu will use the data
742 * right away and we therefore have to clflush anyway. */
743 if (obj
->cache_level
== I915_CACHE_NONE
)
744 needs_clflush_after
= 1;
745 if (obj
->gtt_space
) {
746 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
751 /* Same trick applies for invalidate partially written cachelines before
753 if (!(obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
)
754 && obj
->cache_level
== I915_CACHE_NONE
)
755 needs_clflush_before
= 1;
757 ret
= i915_gem_object_get_pages(obj
);
761 i915_gem_object_pin_pages(obj
);
763 offset
= args
->offset
;
766 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
,
767 offset
>> PAGE_SHIFT
) {
768 struct page
*page
= sg_page_iter_page(&sg_iter
);
769 int partial_cacheline_write
;
774 /* Operation in this page
776 * shmem_page_offset = offset within page in shmem file
777 * page_length = bytes to copy for this page
779 shmem_page_offset
= offset_in_page(offset
);
781 page_length
= remain
;
782 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
783 page_length
= PAGE_SIZE
- shmem_page_offset
;
785 /* If we don't overwrite a cacheline completely we need to be
786 * careful to have up-to-date data by first clflushing. Don't
787 * overcomplicate things and flush the entire patch. */
788 partial_cacheline_write
= needs_clflush_before
&&
789 ((shmem_page_offset
| page_length
)
790 & (boot_cpu_data
.x86_clflush_size
- 1));
792 page_do_bit17_swizzling
= obj_do_bit17_swizzling
&&
793 (page_to_phys(page
) & (1 << 17)) != 0;
795 ret
= shmem_pwrite_fast(page
, shmem_page_offset
, page_length
,
796 user_data
, page_do_bit17_swizzling
,
797 partial_cacheline_write
,
798 needs_clflush_after
);
803 mutex_unlock(&dev
->struct_mutex
);
804 ret
= shmem_pwrite_slow(page
, shmem_page_offset
, page_length
,
805 user_data
, page_do_bit17_swizzling
,
806 partial_cacheline_write
,
807 needs_clflush_after
);
809 mutex_lock(&dev
->struct_mutex
);
812 set_page_dirty(page
);
813 mark_page_accessed(page
);
818 remain
-= page_length
;
819 user_data
+= page_length
;
820 offset
+= page_length
;
824 i915_gem_object_unpin_pages(obj
);
828 * Fixup: Flush cpu caches in case we didn't flush the dirty
829 * cachelines in-line while writing and the object moved
830 * out of the cpu write domain while we've dropped the lock.
832 if (!needs_clflush_after
&&
833 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
834 i915_gem_clflush_object(obj
);
835 i915_gem_chipset_flush(dev
);
839 if (needs_clflush_after
)
840 i915_gem_chipset_flush(dev
);
846 * Writes data to the object referenced by handle.
848 * On error, the contents of the buffer that were to be modified are undefined.
851 i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
852 struct drm_file
*file
)
854 struct drm_i915_gem_pwrite
*args
= data
;
855 struct drm_i915_gem_object
*obj
;
861 if (!access_ok(VERIFY_READ
,
862 to_user_ptr(args
->data_ptr
),
866 ret
= fault_in_multipages_readable(to_user_ptr(args
->data_ptr
),
871 ret
= i915_mutex_lock_interruptible(dev
);
875 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
876 if (&obj
->base
== NULL
) {
881 /* Bounds check destination. */
882 if (args
->offset
> obj
->base
.size
||
883 args
->size
> obj
->base
.size
- args
->offset
) {
888 /* prime objects have no backing filp to GEM pread/pwrite
891 if (!obj
->base
.filp
) {
896 trace_i915_gem_object_pwrite(obj
, args
->offset
, args
->size
);
899 /* We can only do the GTT pwrite on untiled buffers, as otherwise
900 * it would end up going through the fenced access, and we'll get
901 * different detiling behavior between reading and writing.
902 * pread/pwrite currently are reading and writing from the CPU
903 * perspective, requiring manual detiling by the client.
906 ret
= i915_gem_phys_pwrite(dev
, obj
, args
, file
);
910 if (obj
->cache_level
== I915_CACHE_NONE
&&
911 obj
->tiling_mode
== I915_TILING_NONE
&&
912 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
913 ret
= i915_gem_gtt_pwrite_fast(dev
, obj
, args
, file
);
914 /* Note that the gtt paths might fail with non-page-backed user
915 * pointers (e.g. gtt mappings when moving data between
916 * textures). Fallback to the shmem path in that case. */
919 if (ret
== -EFAULT
|| ret
== -ENOSPC
)
920 ret
= i915_gem_shmem_pwrite(dev
, obj
, args
, file
);
923 drm_gem_object_unreference(&obj
->base
);
925 mutex_unlock(&dev
->struct_mutex
);
930 i915_gem_check_wedge(struct i915_gpu_error
*error
,
933 if (i915_reset_in_progress(error
)) {
934 /* Non-interruptible callers can't handle -EAGAIN, hence return
935 * -EIO unconditionally for these. */
939 /* Recovery complete, but the reset failed ... */
940 if (i915_terminally_wedged(error
))
950 * Compare seqno against outstanding lazy request. Emit a request if they are
954 i915_gem_check_olr(struct intel_ring_buffer
*ring
, u32 seqno
)
958 BUG_ON(!mutex_is_locked(&ring
->dev
->struct_mutex
));
961 if (seqno
== ring
->outstanding_lazy_request
)
962 ret
= i915_add_request(ring
, NULL
, NULL
);
968 * __wait_seqno - wait until execution of seqno has finished
969 * @ring: the ring expected to report seqno
971 * @reset_counter: reset sequence associated with the given seqno
972 * @interruptible: do an interruptible wait (normally yes)
973 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
975 * Note: It is of utmost importance that the passed in seqno and reset_counter
976 * values have been read by the caller in an smp safe manner. Where read-side
977 * locks are involved, it is sufficient to read the reset_counter before
978 * unlocking the lock that protects the seqno. For lockless tricks, the
979 * reset_counter _must_ be read before, and an appropriate smp_rmb must be
982 * Returns 0 if the seqno was found within the alloted time. Else returns the
983 * errno with remaining time filled in timeout argument.
985 static int __wait_seqno(struct intel_ring_buffer
*ring
, u32 seqno
,
986 unsigned reset_counter
,
987 bool interruptible
, struct timespec
*timeout
)
989 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
990 struct timespec before
, now
, wait_time
={1,0};
991 unsigned long timeout_jiffies
;
993 bool wait_forever
= true;
996 if (i915_seqno_passed(ring
->get_seqno(ring
, true), seqno
))
999 trace_i915_gem_request_wait_begin(ring
, seqno
);
1001 if (timeout
!= NULL
) {
1002 wait_time
= *timeout
;
1003 wait_forever
= false;
1006 timeout_jiffies
= timespec_to_jiffies(&wait_time
);
1008 if (WARN_ON(!ring
->irq_get(ring
)))
1011 /* Record current time in case interrupted by signal, or wedged * */
1012 getrawmonotonic(&before
);
1015 (i915_seqno_passed(ring->get_seqno(ring, false), seqno) || \
1016 i915_reset_in_progress(&dev_priv->gpu_error) || \
1017 reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
1020 end
= wait_event_interruptible_timeout(ring
->irq_queue
,
1024 end
= wait_event_timeout(ring
->irq_queue
, EXIT_COND
,
1027 /* We need to check whether any gpu reset happened in between
1028 * the caller grabbing the seqno and now ... */
1029 if (reset_counter
!= atomic_read(&dev_priv
->gpu_error
.reset_counter
))
1032 /* ... but upgrade the -EGAIN to an -EIO if the gpu is truely
1034 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, interruptible
);
1037 } while (end
== 0 && wait_forever
);
1039 getrawmonotonic(&now
);
1041 ring
->irq_put(ring
);
1042 trace_i915_gem_request_wait_end(ring
, seqno
);
1046 struct timespec sleep_time
= timespec_sub(now
, before
);
1047 *timeout
= timespec_sub(*timeout
, sleep_time
);
1052 case -EAGAIN
: /* Wedged */
1053 case -ERESTARTSYS
: /* Signal */
1055 case 0: /* Timeout */
1057 set_normalized_timespec(timeout
, 0, 0);
1059 default: /* Completed */
1060 WARN_ON(end
< 0); /* We're not aware of other errors */
1066 * Waits for a sequence number to be signaled, and cleans up the
1067 * request and object lists appropriately for that event.
1070 i915_wait_seqno(struct intel_ring_buffer
*ring
, uint32_t seqno
)
1072 struct drm_device
*dev
= ring
->dev
;
1073 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1074 bool interruptible
= dev_priv
->mm
.interruptible
;
1077 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
1080 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, interruptible
);
1084 ret
= i915_gem_check_olr(ring
, seqno
);
1088 return __wait_seqno(ring
, seqno
,
1089 atomic_read(&dev_priv
->gpu_error
.reset_counter
),
1090 interruptible
, NULL
);
1094 * Ensures that all rendering to the object has completed and the object is
1095 * safe to unbind from the GTT or access from the CPU.
1097 static __must_check
int
1098 i915_gem_object_wait_rendering(struct drm_i915_gem_object
*obj
,
1101 struct intel_ring_buffer
*ring
= obj
->ring
;
1105 seqno
= readonly
? obj
->last_write_seqno
: obj
->last_read_seqno
;
1109 ret
= i915_wait_seqno(ring
, seqno
);
1113 i915_gem_retire_requests_ring(ring
);
1115 /* Manually manage the write flush as we may have not yet
1116 * retired the buffer.
1118 if (obj
->last_write_seqno
&&
1119 i915_seqno_passed(seqno
, obj
->last_write_seqno
)) {
1120 obj
->last_write_seqno
= 0;
1121 obj
->base
.write_domain
&= ~I915_GEM_GPU_DOMAINS
;
1127 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1128 * as the object state may change during this call.
1130 static __must_check
int
1131 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object
*obj
,
1134 struct drm_device
*dev
= obj
->base
.dev
;
1135 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1136 struct intel_ring_buffer
*ring
= obj
->ring
;
1137 unsigned reset_counter
;
1141 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
1142 BUG_ON(!dev_priv
->mm
.interruptible
);
1144 seqno
= readonly
? obj
->last_write_seqno
: obj
->last_read_seqno
;
1148 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, true);
1152 ret
= i915_gem_check_olr(ring
, seqno
);
1156 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
1157 mutex_unlock(&dev
->struct_mutex
);
1158 ret
= __wait_seqno(ring
, seqno
, reset_counter
, true, NULL
);
1159 mutex_lock(&dev
->struct_mutex
);
1161 i915_gem_retire_requests_ring(ring
);
1163 /* Manually manage the write flush as we may have not yet
1164 * retired the buffer.
1166 if (obj
->last_write_seqno
&&
1167 i915_seqno_passed(seqno
, obj
->last_write_seqno
)) {
1168 obj
->last_write_seqno
= 0;
1169 obj
->base
.write_domain
&= ~I915_GEM_GPU_DOMAINS
;
1176 * Called when user space prepares to use an object with the CPU, either
1177 * through the mmap ioctl's mapping or a GTT mapping.
1180 i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
1181 struct drm_file
*file
)
1183 struct drm_i915_gem_set_domain
*args
= data
;
1184 struct drm_i915_gem_object
*obj
;
1185 uint32_t read_domains
= args
->read_domains
;
1186 uint32_t write_domain
= args
->write_domain
;
1189 /* Only handle setting domains to types used by the CPU. */
1190 if (write_domain
& I915_GEM_GPU_DOMAINS
)
1193 if (read_domains
& I915_GEM_GPU_DOMAINS
)
1196 /* Having something in the write domain implies it's in the read
1197 * domain, and only that read domain. Enforce that in the request.
1199 if (write_domain
!= 0 && read_domains
!= write_domain
)
1202 ret
= i915_mutex_lock_interruptible(dev
);
1206 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1207 if (&obj
->base
== NULL
) {
1212 /* Try to flush the object off the GPU without holding the lock.
1213 * We will repeat the flush holding the lock in the normal manner
1214 * to catch cases where we are gazumped.
1216 ret
= i915_gem_object_wait_rendering__nonblocking(obj
, !write_domain
);
1220 if (read_domains
& I915_GEM_DOMAIN_GTT
) {
1221 ret
= i915_gem_object_set_to_gtt_domain(obj
, write_domain
!= 0);
1223 /* Silently promote "you're not bound, there was nothing to do"
1224 * to success, since the client was just asking us to
1225 * make sure everything was done.
1230 ret
= i915_gem_object_set_to_cpu_domain(obj
, write_domain
!= 0);
1234 drm_gem_object_unreference(&obj
->base
);
1236 mutex_unlock(&dev
->struct_mutex
);
1241 * Called when user space has done writes to this buffer
1244 i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1245 struct drm_file
*file
)
1247 struct drm_i915_gem_sw_finish
*args
= data
;
1248 struct drm_i915_gem_object
*obj
;
1251 ret
= i915_mutex_lock_interruptible(dev
);
1255 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1256 if (&obj
->base
== NULL
) {
1261 /* Pinned buffers may be scanout, so flush the cache */
1263 i915_gem_object_flush_cpu_write_domain(obj
);
1265 drm_gem_object_unreference(&obj
->base
);
1267 mutex_unlock(&dev
->struct_mutex
);
1272 * Maps the contents of an object, returning the address it is mapped
1275 * While the mapping holds a reference on the contents of the object, it doesn't
1276 * imply a ref on the object itself.
1279 i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1280 struct drm_file
*file
)
1282 struct drm_i915_gem_mmap
*args
= data
;
1283 struct drm_gem_object
*obj
;
1286 obj
= drm_gem_object_lookup(dev
, file
, args
->handle
);
1290 /* prime objects have no backing filp to GEM mmap
1294 drm_gem_object_unreference_unlocked(obj
);
1298 addr
= vm_mmap(obj
->filp
, 0, args
->size
,
1299 PROT_READ
| PROT_WRITE
, MAP_SHARED
,
1301 drm_gem_object_unreference_unlocked(obj
);
1302 if (IS_ERR((void *)addr
))
1305 args
->addr_ptr
= (uint64_t) addr
;
1311 * i915_gem_fault - fault a page into the GTT
1312 * vma: VMA in question
1315 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1316 * from userspace. The fault handler takes care of binding the object to
1317 * the GTT (if needed), allocating and programming a fence register (again,
1318 * only if needed based on whether the old reg is still valid or the object
1319 * is tiled) and inserting a new PTE into the faulting process.
1321 * Note that the faulting process may involve evicting existing objects
1322 * from the GTT and/or fence registers to make room. So performance may
1323 * suffer if the GTT working set is large or there are few fence registers
1326 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
)
1328 struct drm_i915_gem_object
*obj
= to_intel_bo(vma
->vm_private_data
);
1329 struct drm_device
*dev
= obj
->base
.dev
;
1330 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1331 pgoff_t page_offset
;
1334 bool write
= !!(vmf
->flags
& FAULT_FLAG_WRITE
);
1336 /* We don't use vmf->pgoff since that has the fake offset */
1337 page_offset
= ((unsigned long)vmf
->virtual_address
- vma
->vm_start
) >>
1340 ret
= i915_mutex_lock_interruptible(dev
);
1344 trace_i915_gem_object_fault(obj
, page_offset
, true, write
);
1346 /* Access to snoopable pages through the GTT is incoherent. */
1347 if (obj
->cache_level
!= I915_CACHE_NONE
&& !HAS_LLC(dev
)) {
1352 /* Now bind it into the GTT if needed */
1353 ret
= i915_gem_object_pin(obj
, 0, true, false);
1357 ret
= i915_gem_object_set_to_gtt_domain(obj
, write
);
1361 ret
= i915_gem_object_get_fence(obj
);
1365 obj
->fault_mappable
= true;
1367 pfn
= ((dev_priv
->gtt
.mappable_base
+ obj
->gtt_offset
) >> PAGE_SHIFT
) +
1370 /* Finally, remap it using the new GTT offset */
1371 ret
= vm_insert_pfn(vma
, (unsigned long)vmf
->virtual_address
, pfn
);
1373 i915_gem_object_unpin(obj
);
1375 mutex_unlock(&dev
->struct_mutex
);
1379 /* If this -EIO is due to a gpu hang, give the reset code a
1380 * chance to clean up the mess. Otherwise return the proper
1382 if (i915_terminally_wedged(&dev_priv
->gpu_error
))
1383 return VM_FAULT_SIGBUS
;
1385 /* Give the error handler a chance to run and move the
1386 * objects off the GPU active list. Next time we service the
1387 * fault, we should be able to transition the page into the
1388 * GTT without touching the GPU (and so avoid further
1389 * EIO/EGAIN). If the GPU is wedged, then there is no issue
1390 * with coherency, just lost writes.
1398 * EBUSY is ok: this just means that another thread
1399 * already did the job.
1401 return VM_FAULT_NOPAGE
;
1403 return VM_FAULT_OOM
;
1405 return VM_FAULT_SIGBUS
;
1407 WARN_ONCE(ret
, "unhandled error in i915_gem_fault: %i\n", ret
);
1408 return VM_FAULT_SIGBUS
;
1413 * i915_gem_release_mmap - remove physical page mappings
1414 * @obj: obj in question
1416 * Preserve the reservation of the mmapping with the DRM core code, but
1417 * relinquish ownership of the pages back to the system.
1419 * It is vital that we remove the page mapping if we have mapped a tiled
1420 * object through the GTT and then lose the fence register due to
1421 * resource pressure. Similarly if the object has been moved out of the
1422 * aperture, than pages mapped into userspace must be revoked. Removing the
1423 * mapping will then trigger a page fault on the next user access, allowing
1424 * fixup by i915_gem_fault().
1427 i915_gem_release_mmap(struct drm_i915_gem_object
*obj
)
1429 if (!obj
->fault_mappable
)
1432 if (obj
->base
.dev
->dev_mapping
)
1433 unmap_mapping_range(obj
->base
.dev
->dev_mapping
,
1434 (loff_t
)obj
->base
.map_list
.hash
.key
<<PAGE_SHIFT
,
1437 obj
->fault_mappable
= false;
1441 i915_gem_get_gtt_size(struct drm_device
*dev
, uint32_t size
, int tiling_mode
)
1445 if (INTEL_INFO(dev
)->gen
>= 4 ||
1446 tiling_mode
== I915_TILING_NONE
)
1449 /* Previous chips need a power-of-two fence region when tiling */
1450 if (INTEL_INFO(dev
)->gen
== 3)
1451 gtt_size
= 1024*1024;
1453 gtt_size
= 512*1024;
1455 while (gtt_size
< size
)
1462 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1463 * @obj: object to check
1465 * Return the required GTT alignment for an object, taking into account
1466 * potential fence register mapping.
1469 i915_gem_get_gtt_alignment(struct drm_device
*dev
, uint32_t size
,
1470 int tiling_mode
, bool fenced
)
1473 * Minimum alignment is 4k (GTT page size), but might be greater
1474 * if a fence register is needed for the object.
1476 if (INTEL_INFO(dev
)->gen
>= 4 || (!fenced
&& IS_G33(dev
)) ||
1477 tiling_mode
== I915_TILING_NONE
)
1481 * Previous chips need to be aligned to the size of the smallest
1482 * fence register that can contain the object.
1484 return i915_gem_get_gtt_size(dev
, size
, tiling_mode
);
1487 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object
*obj
)
1489 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
1492 if (obj
->base
.map_list
.map
)
1495 dev_priv
->mm
.shrinker_no_lock_stealing
= true;
1497 ret
= drm_gem_create_mmap_offset(&obj
->base
);
1501 /* Badly fragmented mmap space? The only way we can recover
1502 * space is by destroying unwanted objects. We can't randomly release
1503 * mmap_offsets as userspace expects them to be persistent for the
1504 * lifetime of the objects. The closest we can is to release the
1505 * offsets on purgeable objects by truncating it and marking it purged,
1506 * which prevents userspace from ever using that object again.
1508 i915_gem_purge(dev_priv
, obj
->base
.size
>> PAGE_SHIFT
);
1509 ret
= drm_gem_create_mmap_offset(&obj
->base
);
1513 i915_gem_shrink_all(dev_priv
);
1514 ret
= drm_gem_create_mmap_offset(&obj
->base
);
1516 dev_priv
->mm
.shrinker_no_lock_stealing
= false;
1521 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object
*obj
)
1523 if (!obj
->base
.map_list
.map
)
1526 drm_gem_free_mmap_offset(&obj
->base
);
1530 i915_gem_mmap_gtt(struct drm_file
*file
,
1531 struct drm_device
*dev
,
1535 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1536 struct drm_i915_gem_object
*obj
;
1539 ret
= i915_mutex_lock_interruptible(dev
);
1543 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, handle
));
1544 if (&obj
->base
== NULL
) {
1549 if (obj
->base
.size
> dev_priv
->gtt
.mappable_end
) {
1554 if (obj
->madv
!= I915_MADV_WILLNEED
) {
1555 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1560 ret
= i915_gem_object_create_mmap_offset(obj
);
1564 *offset
= (u64
)obj
->base
.map_list
.hash
.key
<< PAGE_SHIFT
;
1567 drm_gem_object_unreference(&obj
->base
);
1569 mutex_unlock(&dev
->struct_mutex
);
1574 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1576 * @data: GTT mapping ioctl data
1577 * @file: GEM object info
1579 * Simply returns the fake offset to userspace so it can mmap it.
1580 * The mmap call will end up in drm_gem_mmap(), which will set things
1581 * up so we can get faults in the handler above.
1583 * The fault handler will take care of binding the object into the GTT
1584 * (since it may have been evicted to make room for something), allocating
1585 * a fence register, and mapping the appropriate aperture address into
1589 i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
1590 struct drm_file
*file
)
1592 struct drm_i915_gem_mmap_gtt
*args
= data
;
1594 return i915_gem_mmap_gtt(file
, dev
, args
->handle
, &args
->offset
);
1597 /* Immediately discard the backing storage */
1599 i915_gem_object_truncate(struct drm_i915_gem_object
*obj
)
1601 struct inode
*inode
;
1603 i915_gem_object_free_mmap_offset(obj
);
1605 if (obj
->base
.filp
== NULL
)
1608 /* Our goal here is to return as much of the memory as
1609 * is possible back to the system as we are called from OOM.
1610 * To do this we must instruct the shmfs to drop all of its
1611 * backing pages, *now*.
1613 inode
= file_inode(obj
->base
.filp
);
1614 shmem_truncate_range(inode
, 0, (loff_t
)-1);
1616 obj
->madv
= __I915_MADV_PURGED
;
1620 i915_gem_object_is_purgeable(struct drm_i915_gem_object
*obj
)
1622 return obj
->madv
== I915_MADV_DONTNEED
;
1626 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object
*obj
)
1628 struct sg_page_iter sg_iter
;
1631 BUG_ON(obj
->madv
== __I915_MADV_PURGED
);
1633 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
1635 /* In the event of a disaster, abandon all caches and
1636 * hope for the best.
1638 WARN_ON(ret
!= -EIO
);
1639 i915_gem_clflush_object(obj
);
1640 obj
->base
.read_domains
= obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
1643 if (i915_gem_object_needs_bit17_swizzle(obj
))
1644 i915_gem_object_save_bit_17_swizzle(obj
);
1646 if (obj
->madv
== I915_MADV_DONTNEED
)
1649 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
, 0) {
1650 struct page
*page
= sg_page_iter_page(&sg_iter
);
1653 set_page_dirty(page
);
1655 if (obj
->madv
== I915_MADV_WILLNEED
)
1656 mark_page_accessed(page
);
1658 page_cache_release(page
);
1662 sg_free_table(obj
->pages
);
1667 i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
)
1669 const struct drm_i915_gem_object_ops
*ops
= obj
->ops
;
1671 if (obj
->pages
== NULL
)
1674 BUG_ON(obj
->gtt_space
);
1676 if (obj
->pages_pin_count
)
1679 /* ->put_pages might need to allocate memory for the bit17 swizzle
1680 * array, hence protect them from being reaped by removing them from gtt
1682 list_del(&obj
->gtt_list
);
1684 ops
->put_pages(obj
);
1687 if (i915_gem_object_is_purgeable(obj
))
1688 i915_gem_object_truncate(obj
);
1694 __i915_gem_shrink(struct drm_i915_private
*dev_priv
, long target
,
1695 bool purgeable_only
)
1697 struct drm_i915_gem_object
*obj
, *next
;
1700 list_for_each_entry_safe(obj
, next
,
1701 &dev_priv
->mm
.unbound_list
,
1703 if ((i915_gem_object_is_purgeable(obj
) || !purgeable_only
) &&
1704 i915_gem_object_put_pages(obj
) == 0) {
1705 count
+= obj
->base
.size
>> PAGE_SHIFT
;
1706 if (count
>= target
)
1711 list_for_each_entry_safe(obj
, next
,
1712 &dev_priv
->mm
.inactive_list
,
1714 if ((i915_gem_object_is_purgeable(obj
) || !purgeable_only
) &&
1715 i915_gem_object_unbind(obj
) == 0 &&
1716 i915_gem_object_put_pages(obj
) == 0) {
1717 count
+= obj
->base
.size
>> PAGE_SHIFT
;
1718 if (count
>= target
)
1727 i915_gem_purge(struct drm_i915_private
*dev_priv
, long target
)
1729 return __i915_gem_shrink(dev_priv
, target
, true);
1733 i915_gem_shrink_all(struct drm_i915_private
*dev_priv
)
1735 struct drm_i915_gem_object
*obj
, *next
;
1737 i915_gem_evict_everything(dev_priv
->dev
);
1739 list_for_each_entry_safe(obj
, next
, &dev_priv
->mm
.unbound_list
, gtt_list
)
1740 i915_gem_object_put_pages(obj
);
1744 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object
*obj
)
1746 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
1748 struct address_space
*mapping
;
1749 struct sg_table
*st
;
1750 struct scatterlist
*sg
;
1751 struct sg_page_iter sg_iter
;
1753 unsigned long last_pfn
= 0; /* suppress gcc warning */
1756 /* Assert that the object is not currently in any GPU domain. As it
1757 * wasn't in the GTT, there shouldn't be any way it could have been in
1760 BUG_ON(obj
->base
.read_domains
& I915_GEM_GPU_DOMAINS
);
1761 BUG_ON(obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
);
1763 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
1767 page_count
= obj
->base
.size
/ PAGE_SIZE
;
1768 if (sg_alloc_table(st
, page_count
, GFP_KERNEL
)) {
1774 /* Get the list of pages out of our struct file. They'll be pinned
1775 * at this point until we release them.
1777 * Fail silently without starting the shrinker
1779 mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
1780 gfp
= mapping_gfp_mask(mapping
);
1781 gfp
|= __GFP_NORETRY
| __GFP_NOWARN
| __GFP_NO_KSWAPD
;
1782 gfp
&= ~(__GFP_IO
| __GFP_WAIT
);
1785 for (i
= 0; i
< page_count
; i
++) {
1786 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
1788 i915_gem_purge(dev_priv
, page_count
);
1789 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
1792 /* We've tried hard to allocate the memory by reaping
1793 * our own buffer, now let the real VM do its job and
1794 * go down in flames if truly OOM.
1796 gfp
&= ~(__GFP_NORETRY
| __GFP_NOWARN
| __GFP_NO_KSWAPD
);
1797 gfp
|= __GFP_IO
| __GFP_WAIT
;
1799 i915_gem_shrink_all(dev_priv
);
1800 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
1804 gfp
|= __GFP_NORETRY
| __GFP_NOWARN
| __GFP_NO_KSWAPD
;
1805 gfp
&= ~(__GFP_IO
| __GFP_WAIT
);
1808 if (!i
|| page_to_pfn(page
) != last_pfn
+ 1) {
1812 sg_set_page(sg
, page
, PAGE_SIZE
, 0);
1814 sg
->length
+= PAGE_SIZE
;
1816 last_pfn
= page_to_pfn(page
);
1822 if (i915_gem_object_needs_bit17_swizzle(obj
))
1823 i915_gem_object_do_bit_17_swizzle(obj
);
1829 for_each_sg_page(st
->sgl
, &sg_iter
, st
->nents
, 0)
1830 page_cache_release(sg_page_iter_page(&sg_iter
));
1833 return PTR_ERR(page
);
1836 /* Ensure that the associated pages are gathered from the backing storage
1837 * and pinned into our object. i915_gem_object_get_pages() may be called
1838 * multiple times before they are released by a single call to
1839 * i915_gem_object_put_pages() - once the pages are no longer referenced
1840 * either as a result of memory pressure (reaping pages under the shrinker)
1841 * or as the object is itself released.
1844 i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
)
1846 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
1847 const struct drm_i915_gem_object_ops
*ops
= obj
->ops
;
1853 if (obj
->madv
!= I915_MADV_WILLNEED
) {
1854 DRM_ERROR("Attempting to obtain a purgeable object\n");
1858 BUG_ON(obj
->pages_pin_count
);
1860 ret
= ops
->get_pages(obj
);
1864 list_add_tail(&obj
->gtt_list
, &dev_priv
->mm
.unbound_list
);
1869 i915_gem_object_move_to_active(struct drm_i915_gem_object
*obj
,
1870 struct intel_ring_buffer
*ring
)
1872 struct drm_device
*dev
= obj
->base
.dev
;
1873 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1874 u32 seqno
= intel_ring_get_seqno(ring
);
1876 BUG_ON(ring
== NULL
);
1879 /* Add a reference if we're newly entering the active list. */
1881 drm_gem_object_reference(&obj
->base
);
1885 /* Move from whatever list we were on to the tail of execution. */
1886 list_move_tail(&obj
->mm_list
, &dev_priv
->mm
.active_list
);
1887 list_move_tail(&obj
->ring_list
, &ring
->active_list
);
1889 obj
->last_read_seqno
= seqno
;
1891 if (obj
->fenced_gpu_access
) {
1892 obj
->last_fenced_seqno
= seqno
;
1894 /* Bump MRU to take account of the delayed flush */
1895 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
1896 struct drm_i915_fence_reg
*reg
;
1898 reg
= &dev_priv
->fence_regs
[obj
->fence_reg
];
1899 list_move_tail(®
->lru_list
,
1900 &dev_priv
->mm
.fence_list
);
1906 i915_gem_object_move_to_inactive(struct drm_i915_gem_object
*obj
)
1908 struct drm_device
*dev
= obj
->base
.dev
;
1909 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1911 BUG_ON(obj
->base
.write_domain
& ~I915_GEM_GPU_DOMAINS
);
1912 BUG_ON(!obj
->active
);
1914 list_move_tail(&obj
->mm_list
, &dev_priv
->mm
.inactive_list
);
1916 list_del_init(&obj
->ring_list
);
1919 obj
->last_read_seqno
= 0;
1920 obj
->last_write_seqno
= 0;
1921 obj
->base
.write_domain
= 0;
1923 obj
->last_fenced_seqno
= 0;
1924 obj
->fenced_gpu_access
= false;
1927 drm_gem_object_unreference(&obj
->base
);
1929 WARN_ON(i915_verify_lists(dev
));
1933 i915_gem_init_seqno(struct drm_device
*dev
, u32 seqno
)
1935 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1936 struct intel_ring_buffer
*ring
;
1939 /* Carefully retire all requests without writing to the rings */
1940 for_each_ring(ring
, dev_priv
, i
) {
1941 ret
= intel_ring_idle(ring
);
1945 i915_gem_retire_requests(dev
);
1947 /* Finally reset hw state */
1948 for_each_ring(ring
, dev_priv
, i
) {
1949 intel_ring_init_seqno(ring
, seqno
);
1951 for (j
= 0; j
< ARRAY_SIZE(ring
->sync_seqno
); j
++)
1952 ring
->sync_seqno
[j
] = 0;
1958 int i915_gem_set_seqno(struct drm_device
*dev
, u32 seqno
)
1960 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1966 /* HWS page needs to be set less than what we
1967 * will inject to ring
1969 ret
= i915_gem_init_seqno(dev
, seqno
- 1);
1973 /* Carefully set the last_seqno value so that wrap
1974 * detection still works
1976 dev_priv
->next_seqno
= seqno
;
1977 dev_priv
->last_seqno
= seqno
- 1;
1978 if (dev_priv
->last_seqno
== 0)
1979 dev_priv
->last_seqno
--;
1985 i915_gem_get_seqno(struct drm_device
*dev
, u32
*seqno
)
1987 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1989 /* reserve 0 for non-seqno */
1990 if (dev_priv
->next_seqno
== 0) {
1991 int ret
= i915_gem_init_seqno(dev
, 0);
1995 dev_priv
->next_seqno
= 1;
1998 *seqno
= dev_priv
->last_seqno
= dev_priv
->next_seqno
++;
2003 i915_add_request(struct intel_ring_buffer
*ring
,
2004 struct drm_file
*file
,
2007 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
2008 struct drm_i915_gem_request
*request
;
2009 u32 request_ring_position
;
2014 * Emit any outstanding flushes - execbuf can fail to emit the flush
2015 * after having emitted the batchbuffer command. Hence we need to fix
2016 * things up similar to emitting the lazy request. The difference here
2017 * is that the flush _must_ happen before the next request, no matter
2020 ret
= intel_ring_flush_all_caches(ring
);
2024 request
= kmalloc(sizeof(*request
), GFP_KERNEL
);
2025 if (request
== NULL
)
2029 /* Record the position of the start of the request so that
2030 * should we detect the updated seqno part-way through the
2031 * GPU processing the request, we never over-estimate the
2032 * position of the head.
2034 request_ring_position
= intel_ring_get_tail(ring
);
2036 ret
= ring
->add_request(ring
);
2042 request
->seqno
= intel_ring_get_seqno(ring
);
2043 request
->ring
= ring
;
2044 request
->tail
= request_ring_position
;
2045 request
->emitted_jiffies
= jiffies
;
2046 was_empty
= list_empty(&ring
->request_list
);
2047 list_add_tail(&request
->list
, &ring
->request_list
);
2048 request
->file_priv
= NULL
;
2051 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
2053 spin_lock(&file_priv
->mm
.lock
);
2054 request
->file_priv
= file_priv
;
2055 list_add_tail(&request
->client_list
,
2056 &file_priv
->mm
.request_list
);
2057 spin_unlock(&file_priv
->mm
.lock
);
2060 trace_i915_gem_request_add(ring
, request
->seqno
);
2061 ring
->outstanding_lazy_request
= 0;
2063 if (!dev_priv
->mm
.suspended
) {
2064 if (i915_enable_hangcheck
) {
2065 mod_timer(&dev_priv
->gpu_error
.hangcheck_timer
,
2066 round_jiffies_up(jiffies
+ DRM_I915_HANGCHECK_JIFFIES
));
2069 queue_delayed_work(dev_priv
->wq
,
2070 &dev_priv
->mm
.retire_work
,
2071 round_jiffies_up_relative(HZ
));
2072 intel_mark_busy(dev_priv
->dev
);
2077 *out_seqno
= request
->seqno
;
2082 i915_gem_request_remove_from_client(struct drm_i915_gem_request
*request
)
2084 struct drm_i915_file_private
*file_priv
= request
->file_priv
;
2089 spin_lock(&file_priv
->mm
.lock
);
2090 if (request
->file_priv
) {
2091 list_del(&request
->client_list
);
2092 request
->file_priv
= NULL
;
2094 spin_unlock(&file_priv
->mm
.lock
);
2097 static void i915_gem_reset_ring_lists(struct drm_i915_private
*dev_priv
,
2098 struct intel_ring_buffer
*ring
)
2100 while (!list_empty(&ring
->request_list
)) {
2101 struct drm_i915_gem_request
*request
;
2103 request
= list_first_entry(&ring
->request_list
,
2104 struct drm_i915_gem_request
,
2107 list_del(&request
->list
);
2108 i915_gem_request_remove_from_client(request
);
2112 while (!list_empty(&ring
->active_list
)) {
2113 struct drm_i915_gem_object
*obj
;
2115 obj
= list_first_entry(&ring
->active_list
,
2116 struct drm_i915_gem_object
,
2119 i915_gem_object_move_to_inactive(obj
);
2123 static void i915_gem_reset_fences(struct drm_device
*dev
)
2125 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2128 for (i
= 0; i
< dev_priv
->num_fence_regs
; i
++) {
2129 struct drm_i915_fence_reg
*reg
= &dev_priv
->fence_regs
[i
];
2132 i915_gem_object_fence_lost(reg
->obj
);
2134 i915_gem_write_fence(dev
, i
, NULL
);
2138 INIT_LIST_HEAD(®
->lru_list
);
2141 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
2144 void i915_gem_reset(struct drm_device
*dev
)
2146 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2147 struct drm_i915_gem_object
*obj
;
2148 struct intel_ring_buffer
*ring
;
2151 for_each_ring(ring
, dev_priv
, i
)
2152 i915_gem_reset_ring_lists(dev_priv
, ring
);
2154 /* Move everything out of the GPU domains to ensure we do any
2155 * necessary invalidation upon reuse.
2157 list_for_each_entry(obj
,
2158 &dev_priv
->mm
.inactive_list
,
2161 obj
->base
.read_domains
&= ~I915_GEM_GPU_DOMAINS
;
2164 /* The fence registers are invalidated so clear them out */
2165 i915_gem_reset_fences(dev
);
2169 * This function clears the request list as sequence numbers are passed.
2172 i915_gem_retire_requests_ring(struct intel_ring_buffer
*ring
)
2176 if (list_empty(&ring
->request_list
))
2179 WARN_ON(i915_verify_lists(ring
->dev
));
2181 seqno
= ring
->get_seqno(ring
, true);
2183 while (!list_empty(&ring
->request_list
)) {
2184 struct drm_i915_gem_request
*request
;
2186 request
= list_first_entry(&ring
->request_list
,
2187 struct drm_i915_gem_request
,
2190 if (!i915_seqno_passed(seqno
, request
->seqno
))
2193 trace_i915_gem_request_retire(ring
, request
->seqno
);
2194 /* We know the GPU must have read the request to have
2195 * sent us the seqno + interrupt, so use the position
2196 * of tail of the request to update the last known position
2199 ring
->last_retired_head
= request
->tail
;
2201 list_del(&request
->list
);
2202 i915_gem_request_remove_from_client(request
);
2206 /* Move any buffers on the active list that are no longer referenced
2207 * by the ringbuffer to the flushing/inactive lists as appropriate.
2209 while (!list_empty(&ring
->active_list
)) {
2210 struct drm_i915_gem_object
*obj
;
2212 obj
= list_first_entry(&ring
->active_list
,
2213 struct drm_i915_gem_object
,
2216 if (!i915_seqno_passed(seqno
, obj
->last_read_seqno
))
2219 i915_gem_object_move_to_inactive(obj
);
2222 if (unlikely(ring
->trace_irq_seqno
&&
2223 i915_seqno_passed(seqno
, ring
->trace_irq_seqno
))) {
2224 ring
->irq_put(ring
);
2225 ring
->trace_irq_seqno
= 0;
2228 WARN_ON(i915_verify_lists(ring
->dev
));
2232 i915_gem_retire_requests(struct drm_device
*dev
)
2234 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2235 struct intel_ring_buffer
*ring
;
2238 for_each_ring(ring
, dev_priv
, i
)
2239 i915_gem_retire_requests_ring(ring
);
2243 i915_gem_retire_work_handler(struct work_struct
*work
)
2245 drm_i915_private_t
*dev_priv
;
2246 struct drm_device
*dev
;
2247 struct intel_ring_buffer
*ring
;
2251 dev_priv
= container_of(work
, drm_i915_private_t
,
2252 mm
.retire_work
.work
);
2253 dev
= dev_priv
->dev
;
2255 /* Come back later if the device is busy... */
2256 if (!mutex_trylock(&dev
->struct_mutex
)) {
2257 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
,
2258 round_jiffies_up_relative(HZ
));
2262 i915_gem_retire_requests(dev
);
2264 /* Send a periodic flush down the ring so we don't hold onto GEM
2265 * objects indefinitely.
2268 for_each_ring(ring
, dev_priv
, i
) {
2269 if (ring
->gpu_caches_dirty
)
2270 i915_add_request(ring
, NULL
, NULL
);
2272 idle
&= list_empty(&ring
->request_list
);
2275 if (!dev_priv
->mm
.suspended
&& !idle
)
2276 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
,
2277 round_jiffies_up_relative(HZ
));
2279 intel_mark_idle(dev
);
2281 mutex_unlock(&dev
->struct_mutex
);
2285 * Ensures that an object will eventually get non-busy by flushing any required
2286 * write domains, emitting any outstanding lazy request and retiring and
2287 * completed requests.
2290 i915_gem_object_flush_active(struct drm_i915_gem_object
*obj
)
2295 ret
= i915_gem_check_olr(obj
->ring
, obj
->last_read_seqno
);
2299 i915_gem_retire_requests_ring(obj
->ring
);
2306 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2307 * @DRM_IOCTL_ARGS: standard ioctl arguments
2309 * Returns 0 if successful, else an error is returned with the remaining time in
2310 * the timeout parameter.
2311 * -ETIME: object is still busy after timeout
2312 * -ERESTARTSYS: signal interrupted the wait
2313 * -ENONENT: object doesn't exist
2314 * Also possible, but rare:
2315 * -EAGAIN: GPU wedged
2317 * -ENODEV: Internal IRQ fail
2318 * -E?: The add request failed
2320 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2321 * non-zero timeout parameter the wait ioctl will wait for the given number of
2322 * nanoseconds on an object becoming unbusy. Since the wait itself does so
2323 * without holding struct_mutex the object may become re-busied before this
2324 * function completes. A similar but shorter * race condition exists in the busy
2328 i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
, struct drm_file
*file
)
2330 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2331 struct drm_i915_gem_wait
*args
= data
;
2332 struct drm_i915_gem_object
*obj
;
2333 struct intel_ring_buffer
*ring
= NULL
;
2334 struct timespec timeout_stack
, *timeout
= NULL
;
2335 unsigned reset_counter
;
2339 if (args
->timeout_ns
>= 0) {
2340 timeout_stack
= ns_to_timespec(args
->timeout_ns
);
2341 timeout
= &timeout_stack
;
2344 ret
= i915_mutex_lock_interruptible(dev
);
2348 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->bo_handle
));
2349 if (&obj
->base
== NULL
) {
2350 mutex_unlock(&dev
->struct_mutex
);
2354 /* Need to make sure the object gets inactive eventually. */
2355 ret
= i915_gem_object_flush_active(obj
);
2360 seqno
= obj
->last_read_seqno
;
2367 /* Do this after OLR check to make sure we make forward progress polling
2368 * on this IOCTL with a 0 timeout (like busy ioctl)
2370 if (!args
->timeout_ns
) {
2375 drm_gem_object_unreference(&obj
->base
);
2376 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
2377 mutex_unlock(&dev
->struct_mutex
);
2379 ret
= __wait_seqno(ring
, seqno
, reset_counter
, true, timeout
);
2381 WARN_ON(!timespec_valid(timeout
));
2382 args
->timeout_ns
= timespec_to_ns(timeout
);
2387 drm_gem_object_unreference(&obj
->base
);
2388 mutex_unlock(&dev
->struct_mutex
);
2393 * i915_gem_object_sync - sync an object to a ring.
2395 * @obj: object which may be in use on another ring.
2396 * @to: ring we wish to use the object on. May be NULL.
2398 * This code is meant to abstract object synchronization with the GPU.
2399 * Calling with NULL implies synchronizing the object with the CPU
2400 * rather than a particular GPU ring.
2402 * Returns 0 if successful, else propagates up the lower layer error.
2405 i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
2406 struct intel_ring_buffer
*to
)
2408 struct intel_ring_buffer
*from
= obj
->ring
;
2412 if (from
== NULL
|| to
== from
)
2415 if (to
== NULL
|| !i915_semaphore_is_enabled(obj
->base
.dev
))
2416 return i915_gem_object_wait_rendering(obj
, false);
2418 idx
= intel_ring_sync_index(from
, to
);
2420 seqno
= obj
->last_read_seqno
;
2421 if (seqno
<= from
->sync_seqno
[idx
])
2424 ret
= i915_gem_check_olr(obj
->ring
, seqno
);
2428 ret
= to
->sync_to(to
, from
, seqno
);
2430 /* We use last_read_seqno because sync_to()
2431 * might have just caused seqno wrap under
2434 from
->sync_seqno
[idx
] = obj
->last_read_seqno
;
2439 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object
*obj
)
2441 u32 old_write_domain
, old_read_domains
;
2443 /* Force a pagefault for domain tracking on next user access */
2444 i915_gem_release_mmap(obj
);
2446 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
) == 0)
2449 /* Wait for any direct GTT access to complete */
2452 old_read_domains
= obj
->base
.read_domains
;
2453 old_write_domain
= obj
->base
.write_domain
;
2455 obj
->base
.read_domains
&= ~I915_GEM_DOMAIN_GTT
;
2456 obj
->base
.write_domain
&= ~I915_GEM_DOMAIN_GTT
;
2458 trace_i915_gem_object_change_domain(obj
,
2464 * Unbinds an object from the GTT aperture.
2467 i915_gem_object_unbind(struct drm_i915_gem_object
*obj
)
2469 drm_i915_private_t
*dev_priv
= obj
->base
.dev
->dev_private
;
2472 if (obj
->gtt_space
== NULL
)
2478 BUG_ON(obj
->pages
== NULL
);
2480 ret
= i915_gem_object_finish_gpu(obj
);
2483 /* Continue on if we fail due to EIO, the GPU is hung so we
2484 * should be safe and we need to cleanup or else we might
2485 * cause memory corruption through use-after-free.
2488 i915_gem_object_finish_gtt(obj
);
2490 /* release the fence reg _after_ flushing */
2491 ret
= i915_gem_object_put_fence(obj
);
2495 trace_i915_gem_object_unbind(obj
);
2497 if (obj
->has_global_gtt_mapping
)
2498 i915_gem_gtt_unbind_object(obj
);
2499 if (obj
->has_aliasing_ppgtt_mapping
) {
2500 i915_ppgtt_unbind_object(dev_priv
->mm
.aliasing_ppgtt
, obj
);
2501 obj
->has_aliasing_ppgtt_mapping
= 0;
2503 i915_gem_gtt_finish_object(obj
);
2505 list_del(&obj
->mm_list
);
2506 list_move_tail(&obj
->gtt_list
, &dev_priv
->mm
.unbound_list
);
2507 /* Avoid an unnecessary call to unbind on rebind. */
2508 obj
->map_and_fenceable
= true;
2510 drm_mm_put_block(obj
->gtt_space
);
2511 obj
->gtt_space
= NULL
;
2512 obj
->gtt_offset
= 0;
2517 int i915_gpu_idle(struct drm_device
*dev
)
2519 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2520 struct intel_ring_buffer
*ring
;
2523 /* Flush everything onto the inactive list. */
2524 for_each_ring(ring
, dev_priv
, i
) {
2525 ret
= i915_switch_context(ring
, NULL
, DEFAULT_CONTEXT_ID
);
2529 ret
= intel_ring_idle(ring
);
2537 static void i965_write_fence_reg(struct drm_device
*dev
, int reg
,
2538 struct drm_i915_gem_object
*obj
)
2540 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2542 int fence_pitch_shift
;
2545 if (INTEL_INFO(dev
)->gen
>= 6) {
2546 fence_reg
= FENCE_REG_SANDYBRIDGE_0
;
2547 fence_pitch_shift
= SANDYBRIDGE_FENCE_PITCH_SHIFT
;
2549 fence_reg
= FENCE_REG_965_0
;
2550 fence_pitch_shift
= I965_FENCE_PITCH_SHIFT
;
2554 u32 size
= obj
->gtt_space
->size
;
2556 val
= (uint64_t)((obj
->gtt_offset
+ size
- 4096) &
2558 val
|= obj
->gtt_offset
& 0xfffff000;
2559 val
|= (uint64_t)((obj
->stride
/ 128) - 1) << fence_pitch_shift
;
2560 if (obj
->tiling_mode
== I915_TILING_Y
)
2561 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
2562 val
|= I965_FENCE_REG_VALID
;
2566 fence_reg
+= reg
* 8;
2567 I915_WRITE64(fence_reg
, val
);
2568 POSTING_READ(fence_reg
);
2571 static void i915_write_fence_reg(struct drm_device
*dev
, int reg
,
2572 struct drm_i915_gem_object
*obj
)
2574 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2578 u32 size
= obj
->gtt_space
->size
;
2582 WARN((obj
->gtt_offset
& ~I915_FENCE_START_MASK
) ||
2583 (size
& -size
) != size
||
2584 (obj
->gtt_offset
& (size
- 1)),
2585 "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2586 obj
->gtt_offset
, obj
->map_and_fenceable
, size
);
2588 if (obj
->tiling_mode
== I915_TILING_Y
&& HAS_128_BYTE_Y_TILING(dev
))
2593 /* Note: pitch better be a power of two tile widths */
2594 pitch_val
= obj
->stride
/ tile_width
;
2595 pitch_val
= ffs(pitch_val
) - 1;
2597 val
= obj
->gtt_offset
;
2598 if (obj
->tiling_mode
== I915_TILING_Y
)
2599 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2600 val
|= I915_FENCE_SIZE_BITS(size
);
2601 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2602 val
|= I830_FENCE_REG_VALID
;
2607 reg
= FENCE_REG_830_0
+ reg
* 4;
2609 reg
= FENCE_REG_945_8
+ (reg
- 8) * 4;
2611 I915_WRITE(reg
, val
);
2615 static void i830_write_fence_reg(struct drm_device
*dev
, int reg
,
2616 struct drm_i915_gem_object
*obj
)
2618 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2622 u32 size
= obj
->gtt_space
->size
;
2625 WARN((obj
->gtt_offset
& ~I830_FENCE_START_MASK
) ||
2626 (size
& -size
) != size
||
2627 (obj
->gtt_offset
& (size
- 1)),
2628 "object 0x%08x not 512K or pot-size 0x%08x aligned\n",
2629 obj
->gtt_offset
, size
);
2631 pitch_val
= obj
->stride
/ 128;
2632 pitch_val
= ffs(pitch_val
) - 1;
2634 val
= obj
->gtt_offset
;
2635 if (obj
->tiling_mode
== I915_TILING_Y
)
2636 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2637 val
|= I830_FENCE_SIZE_BITS(size
);
2638 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2639 val
|= I830_FENCE_REG_VALID
;
2643 I915_WRITE(FENCE_REG_830_0
+ reg
* 4, val
);
2644 POSTING_READ(FENCE_REG_830_0
+ reg
* 4);
2647 inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object
*obj
)
2649 return obj
&& obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
;
2652 static void i915_gem_write_fence(struct drm_device
*dev
, int reg
,
2653 struct drm_i915_gem_object
*obj
)
2655 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2657 /* Ensure that all CPU reads are completed before installing a fence
2658 * and all writes before removing the fence.
2660 if (i915_gem_object_needs_mb(dev_priv
->fence_regs
[reg
].obj
))
2663 switch (INTEL_INFO(dev
)->gen
) {
2667 case 4: i965_write_fence_reg(dev
, reg
, obj
); break;
2668 case 3: i915_write_fence_reg(dev
, reg
, obj
); break;
2669 case 2: i830_write_fence_reg(dev
, reg
, obj
); break;
2673 /* And similarly be paranoid that no direct access to this region
2674 * is reordered to before the fence is installed.
2676 if (i915_gem_object_needs_mb(obj
))
2680 static inline int fence_number(struct drm_i915_private
*dev_priv
,
2681 struct drm_i915_fence_reg
*fence
)
2683 return fence
- dev_priv
->fence_regs
;
2686 static void i915_gem_write_fence__ipi(void *data
)
2691 static void i915_gem_object_update_fence(struct drm_i915_gem_object
*obj
,
2692 struct drm_i915_fence_reg
*fence
,
2695 struct drm_device
*dev
= obj
->base
.dev
;
2696 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2697 int fence_reg
= fence_number(dev_priv
, fence
);
2699 /* In order to fully serialize access to the fenced region and
2700 * the update to the fence register we need to take extreme
2701 * measures on SNB+. In theory, the write to the fence register
2702 * flushes all memory transactions before, and coupled with the
2703 * mb() placed around the register write we serialise all memory
2704 * operations with respect to the changes in the tiler. Yet, on
2705 * SNB+ we need to take a step further and emit an explicit wbinvd()
2706 * on each processor in order to manually flush all memory
2707 * transactions before updating the fence register.
2709 if (HAS_LLC(obj
->base
.dev
))
2710 on_each_cpu(i915_gem_write_fence__ipi
, NULL
, 1);
2711 i915_gem_write_fence(dev
, fence_reg
, enable
? obj
: NULL
);
2714 obj
->fence_reg
= fence_reg
;
2716 list_move_tail(&fence
->lru_list
, &dev_priv
->mm
.fence_list
);
2718 obj
->fence_reg
= I915_FENCE_REG_NONE
;
2720 list_del_init(&fence
->lru_list
);
2725 i915_gem_object_wait_fence(struct drm_i915_gem_object
*obj
)
2727 if (obj
->last_fenced_seqno
) {
2728 int ret
= i915_wait_seqno(obj
->ring
, obj
->last_fenced_seqno
);
2732 obj
->last_fenced_seqno
= 0;
2735 obj
->fenced_gpu_access
= false;
2740 i915_gem_object_put_fence(struct drm_i915_gem_object
*obj
)
2742 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2743 struct drm_i915_fence_reg
*fence
;
2746 ret
= i915_gem_object_wait_fence(obj
);
2750 if (obj
->fence_reg
== I915_FENCE_REG_NONE
)
2753 fence
= &dev_priv
->fence_regs
[obj
->fence_reg
];
2755 i915_gem_object_fence_lost(obj
);
2756 i915_gem_object_update_fence(obj
, fence
, false);
2761 static struct drm_i915_fence_reg
*
2762 i915_find_fence_reg(struct drm_device
*dev
)
2764 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2765 struct drm_i915_fence_reg
*reg
, *avail
;
2768 /* First try to find a free reg */
2770 for (i
= dev_priv
->fence_reg_start
; i
< dev_priv
->num_fence_regs
; i
++) {
2771 reg
= &dev_priv
->fence_regs
[i
];
2775 if (!reg
->pin_count
)
2782 /* None available, try to steal one or wait for a user to finish */
2783 list_for_each_entry(reg
, &dev_priv
->mm
.fence_list
, lru_list
) {
2794 * i915_gem_object_get_fence - set up fencing for an object
2795 * @obj: object to map through a fence reg
2797 * When mapping objects through the GTT, userspace wants to be able to write
2798 * to them without having to worry about swizzling if the object is tiled.
2799 * This function walks the fence regs looking for a free one for @obj,
2800 * stealing one if it can't find any.
2802 * It then sets up the reg based on the object's properties: address, pitch
2803 * and tiling format.
2805 * For an untiled surface, this removes any existing fence.
2808 i915_gem_object_get_fence(struct drm_i915_gem_object
*obj
)
2810 struct drm_device
*dev
= obj
->base
.dev
;
2811 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2812 bool enable
= obj
->tiling_mode
!= I915_TILING_NONE
;
2813 struct drm_i915_fence_reg
*reg
;
2816 /* Have we updated the tiling parameters upon the object and so
2817 * will need to serialise the write to the associated fence register?
2819 if (obj
->fence_dirty
) {
2820 ret
= i915_gem_object_wait_fence(obj
);
2825 /* Just update our place in the LRU if our fence is getting reused. */
2826 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
2827 reg
= &dev_priv
->fence_regs
[obj
->fence_reg
];
2828 if (!obj
->fence_dirty
) {
2829 list_move_tail(®
->lru_list
,
2830 &dev_priv
->mm
.fence_list
);
2833 } else if (enable
) {
2834 reg
= i915_find_fence_reg(dev
);
2839 struct drm_i915_gem_object
*old
= reg
->obj
;
2841 ret
= i915_gem_object_wait_fence(old
);
2845 i915_gem_object_fence_lost(old
);
2850 i915_gem_object_update_fence(obj
, reg
, enable
);
2851 obj
->fence_dirty
= false;
2856 static bool i915_gem_valid_gtt_space(struct drm_device
*dev
,
2857 struct drm_mm_node
*gtt_space
,
2858 unsigned long cache_level
)
2860 struct drm_mm_node
*other
;
2862 /* On non-LLC machines we have to be careful when putting differing
2863 * types of snoopable memory together to avoid the prefetcher
2864 * crossing memory domains and dying.
2869 if (gtt_space
== NULL
)
2872 if (list_empty(>t_space
->node_list
))
2875 other
= list_entry(gtt_space
->node_list
.prev
, struct drm_mm_node
, node_list
);
2876 if (other
->allocated
&& !other
->hole_follows
&& other
->color
!= cache_level
)
2879 other
= list_entry(gtt_space
->node_list
.next
, struct drm_mm_node
, node_list
);
2880 if (other
->allocated
&& !gtt_space
->hole_follows
&& other
->color
!= cache_level
)
2886 static void i915_gem_verify_gtt(struct drm_device
*dev
)
2889 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2890 struct drm_i915_gem_object
*obj
;
2893 list_for_each_entry(obj
, &dev_priv
->mm
.gtt_list
, gtt_list
) {
2894 if (obj
->gtt_space
== NULL
) {
2895 printk(KERN_ERR
"object found on GTT list with no space reserved\n");
2900 if (obj
->cache_level
!= obj
->gtt_space
->color
) {
2901 printk(KERN_ERR
"object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n",
2902 obj
->gtt_space
->start
,
2903 obj
->gtt_space
->start
+ obj
->gtt_space
->size
,
2905 obj
->gtt_space
->color
);
2910 if (!i915_gem_valid_gtt_space(dev
,
2912 obj
->cache_level
)) {
2913 printk(KERN_ERR
"invalid GTT space found at [%08lx, %08lx] - color=%x\n",
2914 obj
->gtt_space
->start
,
2915 obj
->gtt_space
->start
+ obj
->gtt_space
->size
,
2927 * Finds free space in the GTT aperture and binds the object there.
2930 i915_gem_object_bind_to_gtt(struct drm_i915_gem_object
*obj
,
2932 bool map_and_fenceable
,
2935 struct drm_device
*dev
= obj
->base
.dev
;
2936 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2937 struct drm_mm_node
*node
;
2938 u32 size
, fence_size
, fence_alignment
, unfenced_alignment
;
2939 bool mappable
, fenceable
;
2942 fence_size
= i915_gem_get_gtt_size(dev
,
2945 fence_alignment
= i915_gem_get_gtt_alignment(dev
,
2947 obj
->tiling_mode
, true);
2948 unfenced_alignment
=
2949 i915_gem_get_gtt_alignment(dev
,
2951 obj
->tiling_mode
, false);
2954 alignment
= map_and_fenceable
? fence_alignment
:
2956 if (map_and_fenceable
&& alignment
& (fence_alignment
- 1)) {
2957 DRM_ERROR("Invalid object alignment requested %u\n", alignment
);
2961 size
= map_and_fenceable
? fence_size
: obj
->base
.size
;
2963 /* If the object is bigger than the entire aperture, reject it early
2964 * before evicting everything in a vain attempt to find space.
2966 if (obj
->base
.size
>
2967 (map_and_fenceable
? dev_priv
->gtt
.mappable_end
: dev_priv
->gtt
.total
)) {
2968 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2972 ret
= i915_gem_object_get_pages(obj
);
2976 i915_gem_object_pin_pages(obj
);
2978 node
= kzalloc(sizeof(*node
), GFP_KERNEL
);
2980 i915_gem_object_unpin_pages(obj
);
2985 if (map_and_fenceable
)
2986 ret
= drm_mm_insert_node_in_range_generic(&dev_priv
->mm
.gtt_space
, node
,
2987 size
, alignment
, obj
->cache_level
,
2988 0, dev_priv
->gtt
.mappable_end
);
2990 ret
= drm_mm_insert_node_generic(&dev_priv
->mm
.gtt_space
, node
,
2991 size
, alignment
, obj
->cache_level
);
2993 ret
= i915_gem_evict_something(dev
, size
, alignment
,
3000 i915_gem_object_unpin_pages(obj
);
3004 if (WARN_ON(!i915_gem_valid_gtt_space(dev
, node
, obj
->cache_level
))) {
3005 i915_gem_object_unpin_pages(obj
);
3006 drm_mm_put_block(node
);
3010 ret
= i915_gem_gtt_prepare_object(obj
);
3012 i915_gem_object_unpin_pages(obj
);
3013 drm_mm_put_block(node
);
3017 list_move_tail(&obj
->gtt_list
, &dev_priv
->mm
.bound_list
);
3018 list_add_tail(&obj
->mm_list
, &dev_priv
->mm
.inactive_list
);
3020 obj
->gtt_space
= node
;
3021 obj
->gtt_offset
= node
->start
;
3024 node
->size
== fence_size
&&
3025 (node
->start
& (fence_alignment
- 1)) == 0;
3028 obj
->gtt_offset
+ obj
->base
.size
<= dev_priv
->gtt
.mappable_end
;
3030 obj
->map_and_fenceable
= mappable
&& fenceable
;
3032 i915_gem_object_unpin_pages(obj
);
3033 trace_i915_gem_object_bind(obj
, map_and_fenceable
);
3034 i915_gem_verify_gtt(dev
);
3039 i915_gem_clflush_object(struct drm_i915_gem_object
*obj
)
3041 /* If we don't have a page list set up, then we're not pinned
3042 * to GPU, and we can ignore the cache flush because it'll happen
3043 * again at bind time.
3045 if (obj
->pages
== NULL
)
3049 * Stolen memory is always coherent with the GPU as it is explicitly
3050 * marked as wc by the system, or the system is cache-coherent.
3055 /* If the GPU is snooping the contents of the CPU cache,
3056 * we do not need to manually clear the CPU cache lines. However,
3057 * the caches are only snooped when the render cache is
3058 * flushed/invalidated. As we always have to emit invalidations
3059 * and flushes when moving into and out of the RENDER domain, correct
3060 * snooping behaviour occurs naturally as the result of our domain
3063 if (obj
->cache_level
!= I915_CACHE_NONE
)
3066 trace_i915_gem_object_clflush(obj
);
3068 drm_clflush_sg(obj
->pages
);
3071 /** Flushes the GTT write domain for the object if it's dirty. */
3073 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
)
3075 uint32_t old_write_domain
;
3077 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_GTT
)
3080 /* No actual flushing is required for the GTT write domain. Writes
3081 * to it immediately go to main memory as far as we know, so there's
3082 * no chipset flush. It also doesn't land in render cache.
3084 * However, we do have to enforce the order so that all writes through
3085 * the GTT land before any writes to the device, such as updates to
3090 old_write_domain
= obj
->base
.write_domain
;
3091 obj
->base
.write_domain
= 0;
3093 trace_i915_gem_object_change_domain(obj
,
3094 obj
->base
.read_domains
,
3098 /** Flushes the CPU write domain for the object if it's dirty. */
3100 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
)
3102 uint32_t old_write_domain
;
3104 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
)
3107 i915_gem_clflush_object(obj
);
3108 i915_gem_chipset_flush(obj
->base
.dev
);
3109 old_write_domain
= obj
->base
.write_domain
;
3110 obj
->base
.write_domain
= 0;
3112 trace_i915_gem_object_change_domain(obj
,
3113 obj
->base
.read_domains
,
3118 * Moves a single object to the GTT read, and possibly write domain.
3120 * This function returns when the move is complete, including waiting on
3124 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
, bool write
)
3126 drm_i915_private_t
*dev_priv
= obj
->base
.dev
->dev_private
;
3127 uint32_t old_write_domain
, old_read_domains
;
3130 /* Not valid to be called on unbound objects. */
3131 if (obj
->gtt_space
== NULL
)
3134 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_GTT
)
3137 ret
= i915_gem_object_wait_rendering(obj
, !write
);
3141 i915_gem_object_flush_cpu_write_domain(obj
);
3143 /* Serialise direct access to this object with the barriers for
3144 * coherent writes from the GPU, by effectively invalidating the
3145 * GTT domain upon first access.
3147 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
) == 0)
3150 old_write_domain
= obj
->base
.write_domain
;
3151 old_read_domains
= obj
->base
.read_domains
;
3153 /* It should now be out of any other write domains, and we can update
3154 * the domain values for our changes.
3156 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
3157 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
3159 obj
->base
.read_domains
= I915_GEM_DOMAIN_GTT
;
3160 obj
->base
.write_domain
= I915_GEM_DOMAIN_GTT
;
3164 trace_i915_gem_object_change_domain(obj
,
3168 /* And bump the LRU for this access */
3169 if (i915_gem_object_is_inactive(obj
))
3170 list_move_tail(&obj
->mm_list
, &dev_priv
->mm
.inactive_list
);
3175 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
3176 enum i915_cache_level cache_level
)
3178 struct drm_device
*dev
= obj
->base
.dev
;
3179 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3182 if (obj
->cache_level
== cache_level
)
3185 if (obj
->pin_count
) {
3186 DRM_DEBUG("can not change the cache level of pinned objects\n");
3190 if (!i915_gem_valid_gtt_space(dev
, obj
->gtt_space
, cache_level
)) {
3191 ret
= i915_gem_object_unbind(obj
);
3196 if (obj
->gtt_space
) {
3197 ret
= i915_gem_object_finish_gpu(obj
);
3201 i915_gem_object_finish_gtt(obj
);
3203 /* Before SandyBridge, you could not use tiling or fence
3204 * registers with snooped memory, so relinquish any fences
3205 * currently pointing to our region in the aperture.
3207 if (INTEL_INFO(dev
)->gen
< 6) {
3208 ret
= i915_gem_object_put_fence(obj
);
3213 if (obj
->has_global_gtt_mapping
)
3214 i915_gem_gtt_bind_object(obj
, cache_level
);
3215 if (obj
->has_aliasing_ppgtt_mapping
)
3216 i915_ppgtt_bind_object(dev_priv
->mm
.aliasing_ppgtt
,
3219 obj
->gtt_space
->color
= cache_level
;
3222 if (cache_level
== I915_CACHE_NONE
) {
3223 u32 old_read_domains
, old_write_domain
;
3225 /* If we're coming from LLC cached, then we haven't
3226 * actually been tracking whether the data is in the
3227 * CPU cache or not, since we only allow one bit set
3228 * in obj->write_domain and have been skipping the clflushes.
3229 * Just set it to the CPU cache for now.
3231 WARN_ON(obj
->base
.write_domain
& ~I915_GEM_DOMAIN_CPU
);
3232 WARN_ON(obj
->base
.read_domains
& ~I915_GEM_DOMAIN_CPU
);
3234 old_read_domains
= obj
->base
.read_domains
;
3235 old_write_domain
= obj
->base
.write_domain
;
3237 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
3238 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
3240 trace_i915_gem_object_change_domain(obj
,
3245 obj
->cache_level
= cache_level
;
3246 i915_gem_verify_gtt(dev
);
3250 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
3251 struct drm_file
*file
)
3253 struct drm_i915_gem_caching
*args
= data
;
3254 struct drm_i915_gem_object
*obj
;
3257 ret
= i915_mutex_lock_interruptible(dev
);
3261 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3262 if (&obj
->base
== NULL
) {
3267 args
->caching
= obj
->cache_level
!= I915_CACHE_NONE
;
3269 drm_gem_object_unreference(&obj
->base
);
3271 mutex_unlock(&dev
->struct_mutex
);
3275 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
3276 struct drm_file
*file
)
3278 struct drm_i915_gem_caching
*args
= data
;
3279 struct drm_i915_gem_object
*obj
;
3280 enum i915_cache_level level
;
3283 switch (args
->caching
) {
3284 case I915_CACHING_NONE
:
3285 level
= I915_CACHE_NONE
;
3287 case I915_CACHING_CACHED
:
3288 level
= I915_CACHE_LLC
;
3294 ret
= i915_mutex_lock_interruptible(dev
);
3298 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3299 if (&obj
->base
== NULL
) {
3304 ret
= i915_gem_object_set_cache_level(obj
, level
);
3306 drm_gem_object_unreference(&obj
->base
);
3308 mutex_unlock(&dev
->struct_mutex
);
3313 * Prepare buffer for display plane (scanout, cursors, etc).
3314 * Can be called from an uninterruptible phase (modesetting) and allows
3315 * any flushes to be pipelined (for pageflips).
3318 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
3320 struct intel_ring_buffer
*pipelined
)
3322 u32 old_read_domains
, old_write_domain
;
3325 if (pipelined
!= obj
->ring
) {
3326 ret
= i915_gem_object_sync(obj
, pipelined
);
3331 /* The display engine is not coherent with the LLC cache on gen6. As
3332 * a result, we make sure that the pinning that is about to occur is
3333 * done with uncached PTEs. This is lowest common denominator for all
3336 * However for gen6+, we could do better by using the GFDT bit instead
3337 * of uncaching, which would allow us to flush all the LLC-cached data
3338 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3340 ret
= i915_gem_object_set_cache_level(obj
, I915_CACHE_NONE
);
3344 /* As the user may map the buffer once pinned in the display plane
3345 * (e.g. libkms for the bootup splash), we have to ensure that we
3346 * always use map_and_fenceable for all scanout buffers.
3348 ret
= i915_gem_object_pin(obj
, alignment
, true, false);
3352 i915_gem_object_flush_cpu_write_domain(obj
);
3354 old_write_domain
= obj
->base
.write_domain
;
3355 old_read_domains
= obj
->base
.read_domains
;
3357 /* It should now be out of any other write domains, and we can update
3358 * the domain values for our changes.
3360 obj
->base
.write_domain
= 0;
3361 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
3363 trace_i915_gem_object_change_domain(obj
,
3371 i915_gem_object_finish_gpu(struct drm_i915_gem_object
*obj
)
3375 if ((obj
->base
.read_domains
& I915_GEM_GPU_DOMAINS
) == 0)
3378 ret
= i915_gem_object_wait_rendering(obj
, false);
3382 /* Ensure that we invalidate the GPU's caches and TLBs. */
3383 obj
->base
.read_domains
&= ~I915_GEM_GPU_DOMAINS
;
3388 * Moves a single object to the CPU read, and possibly write domain.
3390 * This function returns when the move is complete, including waiting on
3394 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
)
3396 uint32_t old_write_domain
, old_read_domains
;
3399 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_CPU
)
3402 ret
= i915_gem_object_wait_rendering(obj
, !write
);
3406 i915_gem_object_flush_gtt_write_domain(obj
);
3408 old_write_domain
= obj
->base
.write_domain
;
3409 old_read_domains
= obj
->base
.read_domains
;
3411 /* Flush the CPU cache if it's still invalid. */
3412 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) == 0) {
3413 i915_gem_clflush_object(obj
);
3415 obj
->base
.read_domains
|= I915_GEM_DOMAIN_CPU
;
3418 /* It should now be out of any other write domains, and we can update
3419 * the domain values for our changes.
3421 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
3423 /* If we're writing through the CPU, then the GPU read domains will
3424 * need to be invalidated at next use.
3427 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
3428 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
3431 trace_i915_gem_object_change_domain(obj
,
3438 /* Throttle our rendering by waiting until the ring has completed our requests
3439 * emitted over 20 msec ago.
3441 * Note that if we were to use the current jiffies each time around the loop,
3442 * we wouldn't escape the function with any frames outstanding if the time to
3443 * render a frame was over 20ms.
3445 * This should get us reasonable parallelism between CPU and GPU but also
3446 * relatively low latency when blocking on a particular request to finish.
3449 i915_gem_ring_throttle(struct drm_device
*dev
, struct drm_file
*file
)
3451 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3452 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
3453 unsigned long recent_enough
= jiffies
- msecs_to_jiffies(20);
3454 struct drm_i915_gem_request
*request
;
3455 struct intel_ring_buffer
*ring
= NULL
;
3456 unsigned reset_counter
;
3460 ret
= i915_gem_wait_for_error(&dev_priv
->gpu_error
);
3464 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, false);
3468 spin_lock(&file_priv
->mm
.lock
);
3469 list_for_each_entry(request
, &file_priv
->mm
.request_list
, client_list
) {
3470 if (time_after_eq(request
->emitted_jiffies
, recent_enough
))
3473 ring
= request
->ring
;
3474 seqno
= request
->seqno
;
3476 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
3477 spin_unlock(&file_priv
->mm
.lock
);
3482 ret
= __wait_seqno(ring
, seqno
, reset_counter
, true, NULL
);
3484 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, 0);
3490 i915_gem_object_pin(struct drm_i915_gem_object
*obj
,
3492 bool map_and_fenceable
,
3497 if (WARN_ON(obj
->pin_count
== DRM_I915_GEM_OBJECT_MAX_PIN_COUNT
))
3500 if (obj
->gtt_space
!= NULL
) {
3501 if ((alignment
&& obj
->gtt_offset
& (alignment
- 1)) ||
3502 (map_and_fenceable
&& !obj
->map_and_fenceable
)) {
3503 WARN(obj
->pin_count
,
3504 "bo is already pinned with incorrect alignment:"
3505 " offset=%x, req.alignment=%x, req.map_and_fenceable=%d,"
3506 " obj->map_and_fenceable=%d\n",
3507 obj
->gtt_offset
, alignment
,
3509 obj
->map_and_fenceable
);
3510 ret
= i915_gem_object_unbind(obj
);
3516 if (obj
->gtt_space
== NULL
) {
3517 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
3519 ret
= i915_gem_object_bind_to_gtt(obj
, alignment
,
3525 if (!dev_priv
->mm
.aliasing_ppgtt
)
3526 i915_gem_gtt_bind_object(obj
, obj
->cache_level
);
3529 if (!obj
->has_global_gtt_mapping
&& map_and_fenceable
)
3530 i915_gem_gtt_bind_object(obj
, obj
->cache_level
);
3533 obj
->pin_mappable
|= map_and_fenceable
;
3539 i915_gem_object_unpin(struct drm_i915_gem_object
*obj
)
3541 BUG_ON(obj
->pin_count
== 0);
3542 BUG_ON(obj
->gtt_space
== NULL
);
3544 if (--obj
->pin_count
== 0)
3545 obj
->pin_mappable
= false;
3549 i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
3550 struct drm_file
*file
)
3552 struct drm_i915_gem_pin
*args
= data
;
3553 struct drm_i915_gem_object
*obj
;
3556 ret
= i915_mutex_lock_interruptible(dev
);
3560 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3561 if (&obj
->base
== NULL
) {
3566 if (obj
->madv
!= I915_MADV_WILLNEED
) {
3567 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3572 if (obj
->pin_filp
!= NULL
&& obj
->pin_filp
!= file
) {
3573 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3579 if (obj
->user_pin_count
== 0) {
3580 ret
= i915_gem_object_pin(obj
, args
->alignment
, true, false);
3585 obj
->user_pin_count
++;
3586 obj
->pin_filp
= file
;
3588 /* XXX - flush the CPU caches for pinned objects
3589 * as the X server doesn't manage domains yet
3591 i915_gem_object_flush_cpu_write_domain(obj
);
3592 args
->offset
= obj
->gtt_offset
;
3594 drm_gem_object_unreference(&obj
->base
);
3596 mutex_unlock(&dev
->struct_mutex
);
3601 i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
3602 struct drm_file
*file
)
3604 struct drm_i915_gem_pin
*args
= data
;
3605 struct drm_i915_gem_object
*obj
;
3608 ret
= i915_mutex_lock_interruptible(dev
);
3612 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3613 if (&obj
->base
== NULL
) {
3618 if (obj
->pin_filp
!= file
) {
3619 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3624 obj
->user_pin_count
--;
3625 if (obj
->user_pin_count
== 0) {
3626 obj
->pin_filp
= NULL
;
3627 i915_gem_object_unpin(obj
);
3631 drm_gem_object_unreference(&obj
->base
);
3633 mutex_unlock(&dev
->struct_mutex
);
3638 i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
3639 struct drm_file
*file
)
3641 struct drm_i915_gem_busy
*args
= data
;
3642 struct drm_i915_gem_object
*obj
;
3645 ret
= i915_mutex_lock_interruptible(dev
);
3649 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3650 if (&obj
->base
== NULL
) {
3655 /* Count all active objects as busy, even if they are currently not used
3656 * by the gpu. Users of this interface expect objects to eventually
3657 * become non-busy without any further actions, therefore emit any
3658 * necessary flushes here.
3660 ret
= i915_gem_object_flush_active(obj
);
3662 args
->busy
= obj
->active
;
3664 BUILD_BUG_ON(I915_NUM_RINGS
> 16);
3665 args
->busy
|= intel_ring_flag(obj
->ring
) << 16;
3668 drm_gem_object_unreference(&obj
->base
);
3670 mutex_unlock(&dev
->struct_mutex
);
3675 i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
3676 struct drm_file
*file_priv
)
3678 return i915_gem_ring_throttle(dev
, file_priv
);
3682 i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
3683 struct drm_file
*file_priv
)
3685 struct drm_i915_gem_madvise
*args
= data
;
3686 struct drm_i915_gem_object
*obj
;
3689 switch (args
->madv
) {
3690 case I915_MADV_DONTNEED
:
3691 case I915_MADV_WILLNEED
:
3697 ret
= i915_mutex_lock_interruptible(dev
);
3701 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file_priv
, args
->handle
));
3702 if (&obj
->base
== NULL
) {
3707 if (obj
->pin_count
) {
3712 if (obj
->madv
!= __I915_MADV_PURGED
)
3713 obj
->madv
= args
->madv
;
3715 /* if the object is no longer attached, discard its backing storage */
3716 if (i915_gem_object_is_purgeable(obj
) && obj
->pages
== NULL
)
3717 i915_gem_object_truncate(obj
);
3719 args
->retained
= obj
->madv
!= __I915_MADV_PURGED
;
3722 drm_gem_object_unreference(&obj
->base
);
3724 mutex_unlock(&dev
->struct_mutex
);
3728 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
3729 const struct drm_i915_gem_object_ops
*ops
)
3731 INIT_LIST_HEAD(&obj
->mm_list
);
3732 INIT_LIST_HEAD(&obj
->gtt_list
);
3733 INIT_LIST_HEAD(&obj
->ring_list
);
3734 INIT_LIST_HEAD(&obj
->exec_list
);
3738 obj
->fence_reg
= I915_FENCE_REG_NONE
;
3739 obj
->madv
= I915_MADV_WILLNEED
;
3740 /* Avoid an unnecessary call to unbind on the first bind. */
3741 obj
->map_and_fenceable
= true;
3743 i915_gem_info_add_obj(obj
->base
.dev
->dev_private
, obj
->base
.size
);
3746 static const struct drm_i915_gem_object_ops i915_gem_object_ops
= {
3747 .get_pages
= i915_gem_object_get_pages_gtt
,
3748 .put_pages
= i915_gem_object_put_pages_gtt
,
3751 struct drm_i915_gem_object
*i915_gem_alloc_object(struct drm_device
*dev
,
3754 struct drm_i915_gem_object
*obj
;
3755 struct address_space
*mapping
;
3758 obj
= i915_gem_object_alloc(dev
);
3762 if (drm_gem_object_init(dev
, &obj
->base
, size
) != 0) {
3763 i915_gem_object_free(obj
);
3767 mask
= GFP_HIGHUSER
| __GFP_RECLAIMABLE
;
3768 if (IS_CRESTLINE(dev
) || IS_BROADWATER(dev
)) {
3769 /* 965gm cannot relocate objects above 4GiB. */
3770 mask
&= ~__GFP_HIGHMEM
;
3771 mask
|= __GFP_DMA32
;
3774 mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
3775 mapping_set_gfp_mask(mapping
, mask
);
3777 i915_gem_object_init(obj
, &i915_gem_object_ops
);
3779 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
3780 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
3783 /* On some devices, we can have the GPU use the LLC (the CPU
3784 * cache) for about a 10% performance improvement
3785 * compared to uncached. Graphics requests other than
3786 * display scanout are coherent with the CPU in
3787 * accessing this cache. This means in this mode we
3788 * don't need to clflush on the CPU side, and on the
3789 * GPU side we only need to flush internal caches to
3790 * get data visible to the CPU.
3792 * However, we maintain the display planes as UC, and so
3793 * need to rebind when first used as such.
3795 obj
->cache_level
= I915_CACHE_LLC
;
3797 obj
->cache_level
= I915_CACHE_NONE
;
3802 int i915_gem_init_object(struct drm_gem_object
*obj
)
3809 void i915_gem_free_object(struct drm_gem_object
*gem_obj
)
3811 struct drm_i915_gem_object
*obj
= to_intel_bo(gem_obj
);
3812 struct drm_device
*dev
= obj
->base
.dev
;
3813 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3815 trace_i915_gem_object_destroy(obj
);
3818 i915_gem_detach_phys_object(dev
, obj
);
3821 if (WARN_ON(i915_gem_object_unbind(obj
) == -ERESTARTSYS
)) {
3822 bool was_interruptible
;
3824 was_interruptible
= dev_priv
->mm
.interruptible
;
3825 dev_priv
->mm
.interruptible
= false;
3827 WARN_ON(i915_gem_object_unbind(obj
));
3829 dev_priv
->mm
.interruptible
= was_interruptible
;
3832 obj
->pages_pin_count
= 0;
3833 i915_gem_object_put_pages(obj
);
3834 i915_gem_object_free_mmap_offset(obj
);
3835 i915_gem_object_release_stolen(obj
);
3839 if (obj
->base
.import_attach
)
3840 drm_prime_gem_destroy(&obj
->base
, NULL
);
3842 drm_gem_object_release(&obj
->base
);
3843 i915_gem_info_remove_obj(dev_priv
, obj
->base
.size
);
3846 i915_gem_object_free(obj
);
3850 i915_gem_idle(struct drm_device
*dev
)
3852 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3855 mutex_lock(&dev
->struct_mutex
);
3857 if (dev_priv
->mm
.suspended
) {
3858 mutex_unlock(&dev
->struct_mutex
);
3862 ret
= i915_gpu_idle(dev
);
3864 mutex_unlock(&dev
->struct_mutex
);
3867 i915_gem_retire_requests(dev
);
3869 /* Under UMS, be paranoid and evict. */
3870 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
3871 i915_gem_evict_everything(dev
);
3873 i915_gem_reset_fences(dev
);
3875 /* Hack! Don't let anybody do execbuf while we don't control the chip.
3876 * We need to replace this with a semaphore, or something.
3877 * And not confound mm.suspended!
3879 dev_priv
->mm
.suspended
= 1;
3880 del_timer_sync(&dev_priv
->gpu_error
.hangcheck_timer
);
3882 i915_kernel_lost_context(dev
);
3883 i915_gem_cleanup_ringbuffer(dev
);
3885 mutex_unlock(&dev
->struct_mutex
);
3887 /* Cancel the retire work handler, which should be idle now. */
3888 cancel_delayed_work_sync(&dev_priv
->mm
.retire_work
);
3893 void i915_gem_l3_remap(struct drm_device
*dev
)
3895 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3899 if (!HAS_L3_GPU_CACHE(dev
))
3902 if (!dev_priv
->l3_parity
.remap_info
)
3905 misccpctl
= I915_READ(GEN7_MISCCPCTL
);
3906 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
& ~GEN7_DOP_CLOCK_GATE_ENABLE
);
3907 POSTING_READ(GEN7_MISCCPCTL
);
3909 for (i
= 0; i
< GEN7_L3LOG_SIZE
; i
+= 4) {
3910 u32 remap
= I915_READ(GEN7_L3LOG_BASE
+ i
);
3911 if (remap
&& remap
!= dev_priv
->l3_parity
.remap_info
[i
/4])
3912 DRM_DEBUG("0x%x was already programmed to %x\n",
3913 GEN7_L3LOG_BASE
+ i
, remap
);
3914 if (remap
&& !dev_priv
->l3_parity
.remap_info
[i
/4])
3915 DRM_DEBUG_DRIVER("Clearing remapped register\n");
3916 I915_WRITE(GEN7_L3LOG_BASE
+ i
, dev_priv
->l3_parity
.remap_info
[i
/4]);
3919 /* Make sure all the writes land before disabling dop clock gating */
3920 POSTING_READ(GEN7_L3LOG_BASE
);
3922 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
);
3925 void i915_gem_init_swizzling(struct drm_device
*dev
)
3927 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3929 if (INTEL_INFO(dev
)->gen
< 5 ||
3930 dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_NONE
)
3933 I915_WRITE(DISP_ARB_CTL
, I915_READ(DISP_ARB_CTL
) |
3934 DISP_TILE_SURFACE_SWIZZLING
);
3939 I915_WRITE(TILECTL
, I915_READ(TILECTL
) | TILECTL_SWZCTL
);
3941 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB
));
3942 else if (IS_GEN7(dev
))
3943 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB
));
3949 intel_enable_blt(struct drm_device
*dev
)
3954 /* The blitter was dysfunctional on early prototypes */
3955 if (IS_GEN6(dev
) && dev
->pdev
->revision
< 8) {
3956 DRM_INFO("BLT not supported on this pre-production hardware;"
3957 " graphics performance will be degraded.\n");
3964 static int i915_gem_init_rings(struct drm_device
*dev
)
3966 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3969 ret
= intel_init_render_ring_buffer(dev
);
3974 ret
= intel_init_bsd_ring_buffer(dev
);
3976 goto cleanup_render_ring
;
3979 if (intel_enable_blt(dev
)) {
3980 ret
= intel_init_blt_ring_buffer(dev
);
3982 goto cleanup_bsd_ring
;
3985 ret
= i915_gem_set_seqno(dev
, ((u32
)~0 - 0x1000));
3987 goto cleanup_blt_ring
;
3992 intel_cleanup_ring_buffer(&dev_priv
->ring
[BCS
]);
3994 intel_cleanup_ring_buffer(&dev_priv
->ring
[VCS
]);
3995 cleanup_render_ring
:
3996 intel_cleanup_ring_buffer(&dev_priv
->ring
[RCS
]);
4002 i915_gem_init_hw(struct drm_device
*dev
)
4004 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4007 if (INTEL_INFO(dev
)->gen
< 6 && !intel_enable_gtt())
4010 if (IS_HASWELL(dev
) && (I915_READ(0x120010) == 1))
4011 I915_WRITE(0x9008, I915_READ(0x9008) | 0xf0000);
4013 if (HAS_PCH_NOP(dev
)) {
4014 u32 temp
= I915_READ(GEN7_MSG_CTL
);
4015 temp
&= ~(WAIT_FOR_PCH_FLR_ACK
| WAIT_FOR_PCH_RESET_ACK
);
4016 I915_WRITE(GEN7_MSG_CTL
, temp
);
4019 i915_gem_l3_remap(dev
);
4021 i915_gem_init_swizzling(dev
);
4023 ret
= i915_gem_init_rings(dev
);
4028 * XXX: There was some w/a described somewhere suggesting loading
4029 * contexts before PPGTT.
4031 i915_gem_context_init(dev
);
4032 if (dev_priv
->mm
.aliasing_ppgtt
) {
4033 ret
= dev_priv
->mm
.aliasing_ppgtt
->enable(dev
);
4035 i915_gem_cleanup_aliasing_ppgtt(dev
);
4036 DRM_INFO("PPGTT enable failed. This is not fatal, but unexpected\n");
4043 int i915_gem_init(struct drm_device
*dev
)
4045 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4048 mutex_lock(&dev
->struct_mutex
);
4050 if (IS_VALLEYVIEW(dev
)) {
4051 /* VLVA0 (potential hack), BIOS isn't actually waking us */
4052 I915_WRITE(VLV_GTLC_WAKE_CTRL
, 1);
4053 if (wait_for((I915_READ(VLV_GTLC_PW_STATUS
) & 1) == 1, 10))
4054 DRM_DEBUG_DRIVER("allow wake ack timed out\n");
4057 i915_gem_init_global_gtt(dev
);
4059 ret
= i915_gem_init_hw(dev
);
4060 mutex_unlock(&dev
->struct_mutex
);
4062 i915_gem_cleanup_aliasing_ppgtt(dev
);
4066 /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */
4067 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
4068 dev_priv
->dri1
.allow_batchbuffer
= 1;
4073 i915_gem_cleanup_ringbuffer(struct drm_device
*dev
)
4075 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4076 struct intel_ring_buffer
*ring
;
4079 for_each_ring(ring
, dev_priv
, i
)
4080 intel_cleanup_ring_buffer(ring
);
4084 i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
4085 struct drm_file
*file_priv
)
4087 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4090 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4093 if (i915_reset_in_progress(&dev_priv
->gpu_error
)) {
4094 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4095 atomic_set(&dev_priv
->gpu_error
.reset_counter
, 0);
4098 mutex_lock(&dev
->struct_mutex
);
4099 dev_priv
->mm
.suspended
= 0;
4101 ret
= i915_gem_init_hw(dev
);
4103 mutex_unlock(&dev
->struct_mutex
);
4107 BUG_ON(!list_empty(&dev_priv
->mm
.active_list
));
4108 mutex_unlock(&dev
->struct_mutex
);
4110 ret
= drm_irq_install(dev
);
4112 goto cleanup_ringbuffer
;
4117 mutex_lock(&dev
->struct_mutex
);
4118 i915_gem_cleanup_ringbuffer(dev
);
4119 dev_priv
->mm
.suspended
= 1;
4120 mutex_unlock(&dev
->struct_mutex
);
4126 i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
4127 struct drm_file
*file_priv
)
4129 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4132 drm_irq_uninstall(dev
);
4133 return i915_gem_idle(dev
);
4137 i915_gem_lastclose(struct drm_device
*dev
)
4141 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4144 ret
= i915_gem_idle(dev
);
4146 DRM_ERROR("failed to idle hardware: %d\n", ret
);
4150 init_ring_lists(struct intel_ring_buffer
*ring
)
4152 INIT_LIST_HEAD(&ring
->active_list
);
4153 INIT_LIST_HEAD(&ring
->request_list
);
4157 i915_gem_load(struct drm_device
*dev
)
4159 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4163 kmem_cache_create("i915_gem_object",
4164 sizeof(struct drm_i915_gem_object
), 0,
4168 INIT_LIST_HEAD(&dev_priv
->mm
.active_list
);
4169 INIT_LIST_HEAD(&dev_priv
->mm
.inactive_list
);
4170 INIT_LIST_HEAD(&dev_priv
->mm
.unbound_list
);
4171 INIT_LIST_HEAD(&dev_priv
->mm
.bound_list
);
4172 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
4173 for (i
= 0; i
< I915_NUM_RINGS
; i
++)
4174 init_ring_lists(&dev_priv
->ring
[i
]);
4175 for (i
= 0; i
< I915_MAX_NUM_FENCES
; i
++)
4176 INIT_LIST_HEAD(&dev_priv
->fence_regs
[i
].lru_list
);
4177 INIT_DELAYED_WORK(&dev_priv
->mm
.retire_work
,
4178 i915_gem_retire_work_handler
);
4179 init_waitqueue_head(&dev_priv
->gpu_error
.reset_queue
);
4181 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4183 I915_WRITE(MI_ARB_STATE
,
4184 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE
));
4187 dev_priv
->relative_constants_mode
= I915_EXEC_CONSTANTS_REL_GENERAL
;
4189 /* Old X drivers will take 0-2 for front, back, depth buffers */
4190 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
4191 dev_priv
->fence_reg_start
= 3;
4193 if (INTEL_INFO(dev
)->gen
>= 7 && !IS_VALLEYVIEW(dev
))
4194 dev_priv
->num_fence_regs
= 32;
4195 else if (INTEL_INFO(dev
)->gen
>= 4 || IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
4196 dev_priv
->num_fence_regs
= 16;
4198 dev_priv
->num_fence_regs
= 8;
4200 /* Initialize fence registers to zero */
4201 i915_gem_reset_fences(dev
);
4203 i915_gem_detect_bit_6_swizzle(dev
);
4204 init_waitqueue_head(&dev_priv
->pending_flip_queue
);
4206 dev_priv
->mm
.interruptible
= true;
4208 dev_priv
->mm
.inactive_shrinker
.shrink
= i915_gem_inactive_shrink
;
4209 dev_priv
->mm
.inactive_shrinker
.seeks
= DEFAULT_SEEKS
;
4210 register_shrinker(&dev_priv
->mm
.inactive_shrinker
);
4214 * Create a physically contiguous memory object for this object
4215 * e.g. for cursor + overlay regs
4217 static int i915_gem_init_phys_object(struct drm_device
*dev
,
4218 int id
, int size
, int align
)
4220 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4221 struct drm_i915_gem_phys_object
*phys_obj
;
4224 if (dev_priv
->mm
.phys_objs
[id
- 1] || !size
)
4227 phys_obj
= kzalloc(sizeof(struct drm_i915_gem_phys_object
), GFP_KERNEL
);
4233 phys_obj
->handle
= drm_pci_alloc(dev
, size
, align
);
4234 if (!phys_obj
->handle
) {
4239 set_memory_wc((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
4242 dev_priv
->mm
.phys_objs
[id
- 1] = phys_obj
;
4250 static void i915_gem_free_phys_object(struct drm_device
*dev
, int id
)
4252 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4253 struct drm_i915_gem_phys_object
*phys_obj
;
4255 if (!dev_priv
->mm
.phys_objs
[id
- 1])
4258 phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
4259 if (phys_obj
->cur_obj
) {
4260 i915_gem_detach_phys_object(dev
, phys_obj
->cur_obj
);
4264 set_memory_wb((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
4266 drm_pci_free(dev
, phys_obj
->handle
);
4268 dev_priv
->mm
.phys_objs
[id
- 1] = NULL
;
4271 void i915_gem_free_all_phys_object(struct drm_device
*dev
)
4275 for (i
= I915_GEM_PHYS_CURSOR_0
; i
<= I915_MAX_PHYS_OBJECT
; i
++)
4276 i915_gem_free_phys_object(dev
, i
);
4279 void i915_gem_detach_phys_object(struct drm_device
*dev
,
4280 struct drm_i915_gem_object
*obj
)
4282 struct address_space
*mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
4289 vaddr
= obj
->phys_obj
->handle
->vaddr
;
4291 page_count
= obj
->base
.size
/ PAGE_SIZE
;
4292 for (i
= 0; i
< page_count
; i
++) {
4293 struct page
*page
= shmem_read_mapping_page(mapping
, i
);
4294 if (!IS_ERR(page
)) {
4295 char *dst
= kmap_atomic(page
);
4296 memcpy(dst
, vaddr
+ i
*PAGE_SIZE
, PAGE_SIZE
);
4299 drm_clflush_pages(&page
, 1);
4301 set_page_dirty(page
);
4302 mark_page_accessed(page
);
4303 page_cache_release(page
);
4306 i915_gem_chipset_flush(dev
);
4308 obj
->phys_obj
->cur_obj
= NULL
;
4309 obj
->phys_obj
= NULL
;
4313 i915_gem_attach_phys_object(struct drm_device
*dev
,
4314 struct drm_i915_gem_object
*obj
,
4318 struct address_space
*mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
4319 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4324 if (id
> I915_MAX_PHYS_OBJECT
)
4327 if (obj
->phys_obj
) {
4328 if (obj
->phys_obj
->id
== id
)
4330 i915_gem_detach_phys_object(dev
, obj
);
4333 /* create a new object */
4334 if (!dev_priv
->mm
.phys_objs
[id
- 1]) {
4335 ret
= i915_gem_init_phys_object(dev
, id
,
4336 obj
->base
.size
, align
);
4338 DRM_ERROR("failed to init phys object %d size: %zu\n",
4339 id
, obj
->base
.size
);
4344 /* bind to the object */
4345 obj
->phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
4346 obj
->phys_obj
->cur_obj
= obj
;
4348 page_count
= obj
->base
.size
/ PAGE_SIZE
;
4350 for (i
= 0; i
< page_count
; i
++) {
4354 page
= shmem_read_mapping_page(mapping
, i
);
4356 return PTR_ERR(page
);
4358 src
= kmap_atomic(page
);
4359 dst
= obj
->phys_obj
->handle
->vaddr
+ (i
* PAGE_SIZE
);
4360 memcpy(dst
, src
, PAGE_SIZE
);
4363 mark_page_accessed(page
);
4364 page_cache_release(page
);
4371 i915_gem_phys_pwrite(struct drm_device
*dev
,
4372 struct drm_i915_gem_object
*obj
,
4373 struct drm_i915_gem_pwrite
*args
,
4374 struct drm_file
*file_priv
)
4376 void *vaddr
= obj
->phys_obj
->handle
->vaddr
+ args
->offset
;
4377 char __user
*user_data
= to_user_ptr(args
->data_ptr
);
4379 if (__copy_from_user_inatomic_nocache(vaddr
, user_data
, args
->size
)) {
4380 unsigned long unwritten
;
4382 /* The physical object once assigned is fixed for the lifetime
4383 * of the obj, so we can safely drop the lock and continue
4386 mutex_unlock(&dev
->struct_mutex
);
4387 unwritten
= copy_from_user(vaddr
, user_data
, args
->size
);
4388 mutex_lock(&dev
->struct_mutex
);
4393 i915_gem_chipset_flush(dev
);
4397 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
)
4399 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
4401 /* Clean up our request list when the client is going away, so that
4402 * later retire_requests won't dereference our soon-to-be-gone
4405 spin_lock(&file_priv
->mm
.lock
);
4406 while (!list_empty(&file_priv
->mm
.request_list
)) {
4407 struct drm_i915_gem_request
*request
;
4409 request
= list_first_entry(&file_priv
->mm
.request_list
,
4410 struct drm_i915_gem_request
,
4412 list_del(&request
->client_list
);
4413 request
->file_priv
= NULL
;
4415 spin_unlock(&file_priv
->mm
.lock
);
4418 static bool mutex_is_locked_by(struct mutex
*mutex
, struct task_struct
*task
)
4420 if (!mutex_is_locked(mutex
))
4423 #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES)
4424 return mutex
->owner
== task
;
4426 /* Since UP may be pre-empted, we cannot assume that we own the lock */
4432 i915_gem_inactive_shrink(struct shrinker
*shrinker
, struct shrink_control
*sc
)
4434 struct drm_i915_private
*dev_priv
=
4435 container_of(shrinker
,
4436 struct drm_i915_private
,
4437 mm
.inactive_shrinker
);
4438 struct drm_device
*dev
= dev_priv
->dev
;
4439 struct drm_i915_gem_object
*obj
;
4440 int nr_to_scan
= sc
->nr_to_scan
;
4444 if (!mutex_trylock(&dev
->struct_mutex
)) {
4445 if (!mutex_is_locked_by(&dev
->struct_mutex
, current
))
4448 if (dev_priv
->mm
.shrinker_no_lock_stealing
)
4455 nr_to_scan
-= i915_gem_purge(dev_priv
, nr_to_scan
);
4457 nr_to_scan
-= __i915_gem_shrink(dev_priv
, nr_to_scan
,
4460 i915_gem_shrink_all(dev_priv
);
4464 list_for_each_entry(obj
, &dev_priv
->mm
.unbound_list
, gtt_list
)
4465 if (obj
->pages_pin_count
== 0)
4466 cnt
+= obj
->base
.size
>> PAGE_SHIFT
;
4467 list_for_each_entry(obj
, &dev_priv
->mm
.inactive_list
, gtt_list
)
4468 if (obj
->pin_count
== 0 && obj
->pages_pin_count
== 0)
4469 cnt
+= obj
->base
.size
>> PAGE_SHIFT
;
4472 mutex_unlock(&dev
->struct_mutex
);