2 * Copyright © 2008-2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/drm_vma_manager.h>
30 #include <drm/i915_drm.h>
32 #include "i915_vgpu.h"
33 #include "i915_trace.h"
34 #include "intel_drv.h"
35 #include "intel_mocs.h"
36 #include <linux/shmem_fs.h>
37 #include <linux/slab.h>
38 #include <linux/swap.h>
39 #include <linux/pci.h>
40 #include <linux/dma-buf.h>
42 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
);
43 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
);
45 i915_gem_object_retire__write(struct drm_i915_gem_object
*obj
);
47 i915_gem_object_retire__read(struct drm_i915_gem_object
*obj
, int ring
);
49 static bool cpu_cache_is_coherent(struct drm_device
*dev
,
50 enum i915_cache_level level
)
52 return HAS_LLC(dev
) || level
!= I915_CACHE_NONE
;
55 static bool cpu_write_needs_clflush(struct drm_i915_gem_object
*obj
)
57 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_CPU
)
60 if (!cpu_cache_is_coherent(obj
->base
.dev
, obj
->cache_level
))
63 return obj
->pin_display
;
67 insert_mappable_node(struct drm_i915_private
*i915
,
68 struct drm_mm_node
*node
, u32 size
)
70 memset(node
, 0, sizeof(*node
));
71 return drm_mm_insert_node_in_range_generic(&i915
->ggtt
.base
.mm
, node
,
73 i915
->ggtt
.mappable_end
,
74 DRM_MM_SEARCH_DEFAULT
,
75 DRM_MM_CREATE_DEFAULT
);
79 remove_mappable_node(struct drm_mm_node
*node
)
81 drm_mm_remove_node(node
);
84 /* some bookkeeping */
85 static void i915_gem_info_add_obj(struct drm_i915_private
*dev_priv
,
88 spin_lock(&dev_priv
->mm
.object_stat_lock
);
89 dev_priv
->mm
.object_count
++;
90 dev_priv
->mm
.object_memory
+= size
;
91 spin_unlock(&dev_priv
->mm
.object_stat_lock
);
94 static void i915_gem_info_remove_obj(struct drm_i915_private
*dev_priv
,
97 spin_lock(&dev_priv
->mm
.object_stat_lock
);
98 dev_priv
->mm
.object_count
--;
99 dev_priv
->mm
.object_memory
-= size
;
100 spin_unlock(&dev_priv
->mm
.object_stat_lock
);
104 i915_gem_wait_for_error(struct i915_gpu_error
*error
)
108 if (!i915_reset_in_progress(error
))
112 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
113 * userspace. If it takes that long something really bad is going on and
114 * we should simply try to bail out and fail as gracefully as possible.
116 ret
= wait_event_interruptible_timeout(error
->reset_queue
,
117 !i915_reset_in_progress(error
),
120 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
122 } else if (ret
< 0) {
129 int i915_mutex_lock_interruptible(struct drm_device
*dev
)
131 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
134 ret
= i915_gem_wait_for_error(&dev_priv
->gpu_error
);
138 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
142 WARN_ON(i915_verify_lists(dev
));
147 i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
148 struct drm_file
*file
)
150 struct drm_i915_private
*dev_priv
= to_i915(dev
);
151 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
152 struct drm_i915_gem_get_aperture
*args
= data
;
153 struct i915_vma
*vma
;
157 mutex_lock(&dev
->struct_mutex
);
158 list_for_each_entry(vma
, &ggtt
->base
.active_list
, vm_link
)
160 pinned
+= vma
->node
.size
;
161 list_for_each_entry(vma
, &ggtt
->base
.inactive_list
, vm_link
)
163 pinned
+= vma
->node
.size
;
164 mutex_unlock(&dev
->struct_mutex
);
166 args
->aper_size
= ggtt
->base
.total
;
167 args
->aper_available_size
= args
->aper_size
- pinned
;
173 i915_gem_object_get_pages_phys(struct drm_i915_gem_object
*obj
)
175 struct address_space
*mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
176 char *vaddr
= obj
->phys_handle
->vaddr
;
178 struct scatterlist
*sg
;
181 if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj
)))
184 for (i
= 0; i
< obj
->base
.size
/ PAGE_SIZE
; i
++) {
188 page
= shmem_read_mapping_page(mapping
, i
);
190 return PTR_ERR(page
);
192 src
= kmap_atomic(page
);
193 memcpy(vaddr
, src
, PAGE_SIZE
);
194 drm_clflush_virt_range(vaddr
, PAGE_SIZE
);
201 i915_gem_chipset_flush(to_i915(obj
->base
.dev
));
203 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
207 if (sg_alloc_table(st
, 1, GFP_KERNEL
)) {
214 sg
->length
= obj
->base
.size
;
216 sg_dma_address(sg
) = obj
->phys_handle
->busaddr
;
217 sg_dma_len(sg
) = obj
->base
.size
;
224 i915_gem_object_put_pages_phys(struct drm_i915_gem_object
*obj
)
228 BUG_ON(obj
->madv
== __I915_MADV_PURGED
);
230 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
232 /* In the event of a disaster, abandon all caches and
235 obj
->base
.read_domains
= obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
238 if (obj
->madv
== I915_MADV_DONTNEED
)
242 struct address_space
*mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
243 char *vaddr
= obj
->phys_handle
->vaddr
;
246 for (i
= 0; i
< obj
->base
.size
/ PAGE_SIZE
; i
++) {
250 page
= shmem_read_mapping_page(mapping
, i
);
254 dst
= kmap_atomic(page
);
255 drm_clflush_virt_range(vaddr
, PAGE_SIZE
);
256 memcpy(dst
, vaddr
, PAGE_SIZE
);
259 set_page_dirty(page
);
260 if (obj
->madv
== I915_MADV_WILLNEED
)
261 mark_page_accessed(page
);
268 sg_free_table(obj
->pages
);
273 i915_gem_object_release_phys(struct drm_i915_gem_object
*obj
)
275 drm_pci_free(obj
->base
.dev
, obj
->phys_handle
);
278 static const struct drm_i915_gem_object_ops i915_gem_phys_ops
= {
279 .get_pages
= i915_gem_object_get_pages_phys
,
280 .put_pages
= i915_gem_object_put_pages_phys
,
281 .release
= i915_gem_object_release_phys
,
285 drop_pages(struct drm_i915_gem_object
*obj
)
287 struct i915_vma
*vma
, *next
;
290 drm_gem_object_reference(&obj
->base
);
291 list_for_each_entry_safe(vma
, next
, &obj
->vma_list
, obj_link
)
292 if (i915_vma_unbind(vma
))
295 ret
= i915_gem_object_put_pages(obj
);
296 drm_gem_object_unreference(&obj
->base
);
302 i915_gem_object_attach_phys(struct drm_i915_gem_object
*obj
,
305 drm_dma_handle_t
*phys
;
308 if (obj
->phys_handle
) {
309 if ((unsigned long)obj
->phys_handle
->vaddr
& (align
-1))
315 if (obj
->madv
!= I915_MADV_WILLNEED
)
318 if (obj
->base
.filp
== NULL
)
321 ret
= drop_pages(obj
);
325 /* create a new object */
326 phys
= drm_pci_alloc(obj
->base
.dev
, obj
->base
.size
, align
);
330 obj
->phys_handle
= phys
;
331 obj
->ops
= &i915_gem_phys_ops
;
333 return i915_gem_object_get_pages(obj
);
337 i915_gem_phys_pwrite(struct drm_i915_gem_object
*obj
,
338 struct drm_i915_gem_pwrite
*args
,
339 struct drm_file
*file_priv
)
341 struct drm_device
*dev
= obj
->base
.dev
;
342 void *vaddr
= obj
->phys_handle
->vaddr
+ args
->offset
;
343 char __user
*user_data
= u64_to_user_ptr(args
->data_ptr
);
346 /* We manually control the domain here and pretend that it
347 * remains coherent i.e. in the GTT domain, like shmem_pwrite.
349 ret
= i915_gem_object_wait_rendering(obj
, false);
353 intel_fb_obj_invalidate(obj
, ORIGIN_CPU
);
354 if (__copy_from_user_inatomic_nocache(vaddr
, user_data
, args
->size
)) {
355 unsigned long unwritten
;
357 /* The physical object once assigned is fixed for the lifetime
358 * of the obj, so we can safely drop the lock and continue
361 mutex_unlock(&dev
->struct_mutex
);
362 unwritten
= copy_from_user(vaddr
, user_data
, args
->size
);
363 mutex_lock(&dev
->struct_mutex
);
370 drm_clflush_virt_range(vaddr
, args
->size
);
371 i915_gem_chipset_flush(to_i915(dev
));
374 intel_fb_obj_flush(obj
, false, ORIGIN_CPU
);
378 void *i915_gem_object_alloc(struct drm_device
*dev
)
380 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
381 return kmem_cache_zalloc(dev_priv
->objects
, GFP_KERNEL
);
384 void i915_gem_object_free(struct drm_i915_gem_object
*obj
)
386 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
387 kmem_cache_free(dev_priv
->objects
, obj
);
391 i915_gem_create(struct drm_file
*file
,
392 struct drm_device
*dev
,
396 struct drm_i915_gem_object
*obj
;
400 size
= roundup(size
, PAGE_SIZE
);
404 /* Allocate the new object */
405 obj
= i915_gem_object_create(dev
, size
);
409 ret
= drm_gem_handle_create(file
, &obj
->base
, &handle
);
410 /* drop reference from allocate - handle holds it now */
411 drm_gem_object_unreference_unlocked(&obj
->base
);
420 i915_gem_dumb_create(struct drm_file
*file
,
421 struct drm_device
*dev
,
422 struct drm_mode_create_dumb
*args
)
424 /* have to work out size/pitch and return them */
425 args
->pitch
= ALIGN(args
->width
* DIV_ROUND_UP(args
->bpp
, 8), 64);
426 args
->size
= args
->pitch
* args
->height
;
427 return i915_gem_create(file
, dev
,
428 args
->size
, &args
->handle
);
432 * Creates a new mm object and returns a handle to it.
433 * @dev: drm device pointer
434 * @data: ioctl data blob
435 * @file: drm file pointer
438 i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
439 struct drm_file
*file
)
441 struct drm_i915_gem_create
*args
= data
;
443 return i915_gem_create(file
, dev
,
444 args
->size
, &args
->handle
);
448 __copy_to_user_swizzled(char __user
*cpu_vaddr
,
449 const char *gpu_vaddr
, int gpu_offset
,
452 int ret
, cpu_offset
= 0;
455 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
456 int this_length
= min(cacheline_end
- gpu_offset
, length
);
457 int swizzled_gpu_offset
= gpu_offset
^ 64;
459 ret
= __copy_to_user(cpu_vaddr
+ cpu_offset
,
460 gpu_vaddr
+ swizzled_gpu_offset
,
465 cpu_offset
+= this_length
;
466 gpu_offset
+= this_length
;
467 length
-= this_length
;
474 __copy_from_user_swizzled(char *gpu_vaddr
, int gpu_offset
,
475 const char __user
*cpu_vaddr
,
478 int ret
, cpu_offset
= 0;
481 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
482 int this_length
= min(cacheline_end
- gpu_offset
, length
);
483 int swizzled_gpu_offset
= gpu_offset
^ 64;
485 ret
= __copy_from_user(gpu_vaddr
+ swizzled_gpu_offset
,
486 cpu_vaddr
+ cpu_offset
,
491 cpu_offset
+= this_length
;
492 gpu_offset
+= this_length
;
493 length
-= this_length
;
500 * Pins the specified object's pages and synchronizes the object with
501 * GPU accesses. Sets needs_clflush to non-zero if the caller should
502 * flush the object from the CPU cache.
504 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object
*obj
,
511 if (WARN_ON(!i915_gem_object_has_struct_page(obj
)))
514 if (!(obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
)) {
515 /* If we're not in the cpu read domain, set ourself into the gtt
516 * read domain and manually flush cachelines (if required). This
517 * optimizes for the case when the gpu will dirty the data
518 * anyway again before the next pread happens. */
519 *needs_clflush
= !cpu_cache_is_coherent(obj
->base
.dev
,
521 ret
= i915_gem_object_wait_rendering(obj
, true);
526 ret
= i915_gem_object_get_pages(obj
);
530 i915_gem_object_pin_pages(obj
);
535 /* Per-page copy function for the shmem pread fastpath.
536 * Flushes invalid cachelines before reading the target if
537 * needs_clflush is set. */
539 shmem_pread_fast(struct page
*page
, int shmem_page_offset
, int page_length
,
540 char __user
*user_data
,
541 bool page_do_bit17_swizzling
, bool needs_clflush
)
546 if (unlikely(page_do_bit17_swizzling
))
549 vaddr
= kmap_atomic(page
);
551 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
553 ret
= __copy_to_user_inatomic(user_data
,
554 vaddr
+ shmem_page_offset
,
556 kunmap_atomic(vaddr
);
558 return ret
? -EFAULT
: 0;
562 shmem_clflush_swizzled_range(char *addr
, unsigned long length
,
565 if (unlikely(swizzled
)) {
566 unsigned long start
= (unsigned long) addr
;
567 unsigned long end
= (unsigned long) addr
+ length
;
569 /* For swizzling simply ensure that we always flush both
570 * channels. Lame, but simple and it works. Swizzled
571 * pwrite/pread is far from a hotpath - current userspace
572 * doesn't use it at all. */
573 start
= round_down(start
, 128);
574 end
= round_up(end
, 128);
576 drm_clflush_virt_range((void *)start
, end
- start
);
578 drm_clflush_virt_range(addr
, length
);
583 /* Only difference to the fast-path function is that this can handle bit17
584 * and uses non-atomic copy and kmap functions. */
586 shmem_pread_slow(struct page
*page
, int shmem_page_offset
, int page_length
,
587 char __user
*user_data
,
588 bool page_do_bit17_swizzling
, bool needs_clflush
)
595 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
597 page_do_bit17_swizzling
);
599 if (page_do_bit17_swizzling
)
600 ret
= __copy_to_user_swizzled(user_data
,
601 vaddr
, shmem_page_offset
,
604 ret
= __copy_to_user(user_data
,
605 vaddr
+ shmem_page_offset
,
609 return ret
? - EFAULT
: 0;
612 static inline unsigned long
613 slow_user_access(struct io_mapping
*mapping
,
614 uint64_t page_base
, int page_offset
,
615 char __user
*user_data
,
616 unsigned long length
, bool pwrite
)
618 void __iomem
*ioaddr
;
622 ioaddr
= io_mapping_map_wc(mapping
, page_base
, PAGE_SIZE
);
623 /* We can use the cpu mem copy function because this is X86. */
624 vaddr
= (void __force
*)ioaddr
+ page_offset
;
626 unwritten
= __copy_from_user(vaddr
, user_data
, length
);
628 unwritten
= __copy_to_user(user_data
, vaddr
, length
);
630 io_mapping_unmap(ioaddr
);
635 i915_gem_gtt_pread(struct drm_device
*dev
,
636 struct drm_i915_gem_object
*obj
, uint64_t size
,
637 uint64_t data_offset
, uint64_t data_ptr
)
639 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
640 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
641 struct drm_mm_node node
;
642 char __user
*user_data
;
647 ret
= i915_gem_obj_ggtt_pin(obj
, 0, PIN_MAPPABLE
);
649 ret
= insert_mappable_node(dev_priv
, &node
, PAGE_SIZE
);
653 ret
= i915_gem_object_get_pages(obj
);
655 remove_mappable_node(&node
);
659 i915_gem_object_pin_pages(obj
);
661 node
.start
= i915_gem_obj_ggtt_offset(obj
);
662 node
.allocated
= false;
663 ret
= i915_gem_object_put_fence(obj
);
668 ret
= i915_gem_object_set_to_gtt_domain(obj
, false);
672 user_data
= u64_to_user_ptr(data_ptr
);
674 offset
= data_offset
;
676 mutex_unlock(&dev
->struct_mutex
);
677 if (likely(!i915
.prefault_disable
)) {
678 ret
= fault_in_multipages_writeable(user_data
, remain
);
680 mutex_lock(&dev
->struct_mutex
);
686 /* Operation in this page
688 * page_base = page offset within aperture
689 * page_offset = offset within page
690 * page_length = bytes to copy for this page
692 u32 page_base
= node
.start
;
693 unsigned page_offset
= offset_in_page(offset
);
694 unsigned page_length
= PAGE_SIZE
- page_offset
;
695 page_length
= remain
< page_length
? remain
: page_length
;
696 if (node
.allocated
) {
698 ggtt
->base
.insert_page(&ggtt
->base
,
699 i915_gem_object_get_dma_address(obj
, offset
>> PAGE_SHIFT
),
704 page_base
+= offset
& PAGE_MASK
;
706 /* This is a slow read/write as it tries to read from
707 * and write to user memory which may result into page
708 * faults, and so we cannot perform this under struct_mutex.
710 if (slow_user_access(ggtt
->mappable
, page_base
,
711 page_offset
, user_data
,
712 page_length
, false)) {
717 remain
-= page_length
;
718 user_data
+= page_length
;
719 offset
+= page_length
;
722 mutex_lock(&dev
->struct_mutex
);
723 if (ret
== 0 && (obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
) == 0) {
724 /* The user has modified the object whilst we tried
725 * reading from it, and we now have no idea what domain
726 * the pages should be in. As we have just been touching
727 * them directly, flush everything back to the GTT
730 ret
= i915_gem_object_set_to_gtt_domain(obj
, false);
734 if (node
.allocated
) {
736 ggtt
->base
.clear_range(&ggtt
->base
,
737 node
.start
, node
.size
,
739 i915_gem_object_unpin_pages(obj
);
740 remove_mappable_node(&node
);
742 i915_gem_object_ggtt_unpin(obj
);
749 i915_gem_shmem_pread(struct drm_device
*dev
,
750 struct drm_i915_gem_object
*obj
,
751 struct drm_i915_gem_pread
*args
,
752 struct drm_file
*file
)
754 char __user
*user_data
;
757 int shmem_page_offset
, page_length
, ret
= 0;
758 int obj_do_bit17_swizzling
, page_do_bit17_swizzling
;
760 int needs_clflush
= 0;
761 struct sg_page_iter sg_iter
;
766 user_data
= u64_to_user_ptr(args
->data_ptr
);
769 obj_do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
771 ret
= i915_gem_obj_prepare_shmem_read(obj
, &needs_clflush
);
775 offset
= args
->offset
;
777 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
,
778 offset
>> PAGE_SHIFT
) {
779 struct page
*page
= sg_page_iter_page(&sg_iter
);
784 /* Operation in this page
786 * shmem_page_offset = offset within page in shmem file
787 * page_length = bytes to copy for this page
789 shmem_page_offset
= offset_in_page(offset
);
790 page_length
= remain
;
791 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
792 page_length
= PAGE_SIZE
- shmem_page_offset
;
794 page_do_bit17_swizzling
= obj_do_bit17_swizzling
&&
795 (page_to_phys(page
) & (1 << 17)) != 0;
797 ret
= shmem_pread_fast(page
, shmem_page_offset
, page_length
,
798 user_data
, page_do_bit17_swizzling
,
803 mutex_unlock(&dev
->struct_mutex
);
805 if (likely(!i915
.prefault_disable
) && !prefaulted
) {
806 ret
= fault_in_multipages_writeable(user_data
, remain
);
807 /* Userspace is tricking us, but we've already clobbered
808 * its pages with the prefault and promised to write the
809 * data up to the first fault. Hence ignore any errors
810 * and just continue. */
815 ret
= shmem_pread_slow(page
, shmem_page_offset
, page_length
,
816 user_data
, page_do_bit17_swizzling
,
819 mutex_lock(&dev
->struct_mutex
);
825 remain
-= page_length
;
826 user_data
+= page_length
;
827 offset
+= page_length
;
831 i915_gem_object_unpin_pages(obj
);
837 * Reads data from the object referenced by handle.
838 * @dev: drm device pointer
839 * @data: ioctl data blob
840 * @file: drm file pointer
842 * On error, the contents of *data are undefined.
845 i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
846 struct drm_file
*file
)
848 struct drm_i915_gem_pread
*args
= data
;
849 struct drm_i915_gem_object
*obj
;
855 if (!access_ok(VERIFY_WRITE
,
856 u64_to_user_ptr(args
->data_ptr
),
860 ret
= i915_mutex_lock_interruptible(dev
);
864 obj
= to_intel_bo(drm_gem_object_lookup(file
, args
->handle
));
865 if (&obj
->base
== NULL
) {
870 /* Bounds check source. */
871 if (args
->offset
> obj
->base
.size
||
872 args
->size
> obj
->base
.size
- args
->offset
) {
877 trace_i915_gem_object_pread(obj
, args
->offset
, args
->size
);
879 ret
= i915_gem_shmem_pread(dev
, obj
, args
, file
);
881 /* pread for non shmem backed objects */
882 if (ret
== -EFAULT
|| ret
== -ENODEV
)
883 ret
= i915_gem_gtt_pread(dev
, obj
, args
->size
,
884 args
->offset
, args
->data_ptr
);
887 drm_gem_object_unreference(&obj
->base
);
889 mutex_unlock(&dev
->struct_mutex
);
893 /* This is the fast write path which cannot handle
894 * page faults in the source data
898 fast_user_write(struct io_mapping
*mapping
,
899 loff_t page_base
, int page_offset
,
900 char __user
*user_data
,
903 void __iomem
*vaddr_atomic
;
905 unsigned long unwritten
;
907 vaddr_atomic
= io_mapping_map_atomic_wc(mapping
, page_base
);
908 /* We can use the cpu mem copy function because this is X86. */
909 vaddr
= (void __force
*)vaddr_atomic
+ page_offset
;
910 unwritten
= __copy_from_user_inatomic_nocache(vaddr
,
912 io_mapping_unmap_atomic(vaddr_atomic
);
917 * This is the fast pwrite path, where we copy the data directly from the
918 * user into the GTT, uncached.
919 * @dev: drm device pointer
920 * @obj: i915 gem object
921 * @args: pwrite arguments structure
922 * @file: drm file pointer
925 i915_gem_gtt_pwrite_fast(struct drm_i915_private
*i915
,
926 struct drm_i915_gem_object
*obj
,
927 struct drm_i915_gem_pwrite
*args
,
928 struct drm_file
*file
)
930 struct i915_ggtt
*ggtt
= &i915
->ggtt
;
931 struct drm_device
*dev
= obj
->base
.dev
;
932 struct drm_mm_node node
;
933 uint64_t remain
, offset
;
934 char __user
*user_data
;
936 bool hit_slow_path
= false;
938 if (obj
->tiling_mode
!= I915_TILING_NONE
)
941 ret
= i915_gem_obj_ggtt_pin(obj
, 0, PIN_MAPPABLE
| PIN_NONBLOCK
);
943 ret
= insert_mappable_node(i915
, &node
, PAGE_SIZE
);
947 ret
= i915_gem_object_get_pages(obj
);
949 remove_mappable_node(&node
);
953 i915_gem_object_pin_pages(obj
);
955 node
.start
= i915_gem_obj_ggtt_offset(obj
);
956 node
.allocated
= false;
957 ret
= i915_gem_object_put_fence(obj
);
962 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
966 intel_fb_obj_invalidate(obj
, ORIGIN_GTT
);
969 user_data
= u64_to_user_ptr(args
->data_ptr
);
970 offset
= args
->offset
;
973 /* Operation in this page
975 * page_base = page offset within aperture
976 * page_offset = offset within page
977 * page_length = bytes to copy for this page
979 u32 page_base
= node
.start
;
980 unsigned page_offset
= offset_in_page(offset
);
981 unsigned page_length
= PAGE_SIZE
- page_offset
;
982 page_length
= remain
< page_length
? remain
: page_length
;
983 if (node
.allocated
) {
984 wmb(); /* flush the write before we modify the GGTT */
985 ggtt
->base
.insert_page(&ggtt
->base
,
986 i915_gem_object_get_dma_address(obj
, offset
>> PAGE_SHIFT
),
987 node
.start
, I915_CACHE_NONE
, 0);
988 wmb(); /* flush modifications to the GGTT (insert_page) */
990 page_base
+= offset
& PAGE_MASK
;
992 /* If we get a fault while copying data, then (presumably) our
993 * source page isn't available. Return the error and we'll
994 * retry in the slow path.
995 * If the object is non-shmem backed, we retry again with the
996 * path that handles page fault.
998 if (fast_user_write(ggtt
->mappable
, page_base
,
999 page_offset
, user_data
, page_length
)) {
1000 hit_slow_path
= true;
1001 mutex_unlock(&dev
->struct_mutex
);
1002 if (slow_user_access(ggtt
->mappable
,
1004 page_offset
, user_data
,
1005 page_length
, true)) {
1007 mutex_lock(&dev
->struct_mutex
);
1011 mutex_lock(&dev
->struct_mutex
);
1014 remain
-= page_length
;
1015 user_data
+= page_length
;
1016 offset
+= page_length
;
1020 if (hit_slow_path
) {
1022 (obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
) == 0) {
1023 /* The user has modified the object whilst we tried
1024 * reading from it, and we now have no idea what domain
1025 * the pages should be in. As we have just been touching
1026 * them directly, flush everything back to the GTT
1029 ret
= i915_gem_object_set_to_gtt_domain(obj
, false);
1033 intel_fb_obj_flush(obj
, false, ORIGIN_GTT
);
1035 if (node
.allocated
) {
1037 ggtt
->base
.clear_range(&ggtt
->base
,
1038 node
.start
, node
.size
,
1040 i915_gem_object_unpin_pages(obj
);
1041 remove_mappable_node(&node
);
1043 i915_gem_object_ggtt_unpin(obj
);
1049 /* Per-page copy function for the shmem pwrite fastpath.
1050 * Flushes invalid cachelines before writing to the target if
1051 * needs_clflush_before is set and flushes out any written cachelines after
1052 * writing if needs_clflush is set. */
1054 shmem_pwrite_fast(struct page
*page
, int shmem_page_offset
, int page_length
,
1055 char __user
*user_data
,
1056 bool page_do_bit17_swizzling
,
1057 bool needs_clflush_before
,
1058 bool needs_clflush_after
)
1063 if (unlikely(page_do_bit17_swizzling
))
1066 vaddr
= kmap_atomic(page
);
1067 if (needs_clflush_before
)
1068 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
1070 ret
= __copy_from_user_inatomic(vaddr
+ shmem_page_offset
,
1071 user_data
, page_length
);
1072 if (needs_clflush_after
)
1073 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
1075 kunmap_atomic(vaddr
);
1077 return ret
? -EFAULT
: 0;
1080 /* Only difference to the fast-path function is that this can handle bit17
1081 * and uses non-atomic copy and kmap functions. */
1083 shmem_pwrite_slow(struct page
*page
, int shmem_page_offset
, int page_length
,
1084 char __user
*user_data
,
1085 bool page_do_bit17_swizzling
,
1086 bool needs_clflush_before
,
1087 bool needs_clflush_after
)
1093 if (unlikely(needs_clflush_before
|| page_do_bit17_swizzling
))
1094 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
1096 page_do_bit17_swizzling
);
1097 if (page_do_bit17_swizzling
)
1098 ret
= __copy_from_user_swizzled(vaddr
, shmem_page_offset
,
1102 ret
= __copy_from_user(vaddr
+ shmem_page_offset
,
1105 if (needs_clflush_after
)
1106 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
1108 page_do_bit17_swizzling
);
1111 return ret
? -EFAULT
: 0;
1115 i915_gem_shmem_pwrite(struct drm_device
*dev
,
1116 struct drm_i915_gem_object
*obj
,
1117 struct drm_i915_gem_pwrite
*args
,
1118 struct drm_file
*file
)
1122 char __user
*user_data
;
1123 int shmem_page_offset
, page_length
, ret
= 0;
1124 int obj_do_bit17_swizzling
, page_do_bit17_swizzling
;
1125 int hit_slowpath
= 0;
1126 int needs_clflush_after
= 0;
1127 int needs_clflush_before
= 0;
1128 struct sg_page_iter sg_iter
;
1130 user_data
= u64_to_user_ptr(args
->data_ptr
);
1131 remain
= args
->size
;
1133 obj_do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
1135 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
1136 /* If we're not in the cpu write domain, set ourself into the gtt
1137 * write domain and manually flush cachelines (if required). This
1138 * optimizes for the case when the gpu will use the data
1139 * right away and we therefore have to clflush anyway. */
1140 needs_clflush_after
= cpu_write_needs_clflush(obj
);
1141 ret
= i915_gem_object_wait_rendering(obj
, false);
1145 /* Same trick applies to invalidate partially written cachelines read
1146 * before writing. */
1147 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) == 0)
1148 needs_clflush_before
=
1149 !cpu_cache_is_coherent(dev
, obj
->cache_level
);
1151 ret
= i915_gem_object_get_pages(obj
);
1155 intel_fb_obj_invalidate(obj
, ORIGIN_CPU
);
1157 i915_gem_object_pin_pages(obj
);
1159 offset
= args
->offset
;
1162 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
,
1163 offset
>> PAGE_SHIFT
) {
1164 struct page
*page
= sg_page_iter_page(&sg_iter
);
1165 int partial_cacheline_write
;
1170 /* Operation in this page
1172 * shmem_page_offset = offset within page in shmem file
1173 * page_length = bytes to copy for this page
1175 shmem_page_offset
= offset_in_page(offset
);
1177 page_length
= remain
;
1178 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
1179 page_length
= PAGE_SIZE
- shmem_page_offset
;
1181 /* If we don't overwrite a cacheline completely we need to be
1182 * careful to have up-to-date data by first clflushing. Don't
1183 * overcomplicate things and flush the entire patch. */
1184 partial_cacheline_write
= needs_clflush_before
&&
1185 ((shmem_page_offset
| page_length
)
1186 & (boot_cpu_data
.x86_clflush_size
- 1));
1188 page_do_bit17_swizzling
= obj_do_bit17_swizzling
&&
1189 (page_to_phys(page
) & (1 << 17)) != 0;
1191 ret
= shmem_pwrite_fast(page
, shmem_page_offset
, page_length
,
1192 user_data
, page_do_bit17_swizzling
,
1193 partial_cacheline_write
,
1194 needs_clflush_after
);
1199 mutex_unlock(&dev
->struct_mutex
);
1200 ret
= shmem_pwrite_slow(page
, shmem_page_offset
, page_length
,
1201 user_data
, page_do_bit17_swizzling
,
1202 partial_cacheline_write
,
1203 needs_clflush_after
);
1205 mutex_lock(&dev
->struct_mutex
);
1211 remain
-= page_length
;
1212 user_data
+= page_length
;
1213 offset
+= page_length
;
1217 i915_gem_object_unpin_pages(obj
);
1221 * Fixup: Flush cpu caches in case we didn't flush the dirty
1222 * cachelines in-line while writing and the object moved
1223 * out of the cpu write domain while we've dropped the lock.
1225 if (!needs_clflush_after
&&
1226 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
1227 if (i915_gem_clflush_object(obj
, obj
->pin_display
))
1228 needs_clflush_after
= true;
1232 if (needs_clflush_after
)
1233 i915_gem_chipset_flush(to_i915(dev
));
1235 obj
->cache_dirty
= true;
1237 intel_fb_obj_flush(obj
, false, ORIGIN_CPU
);
1242 * Writes data to the object referenced by handle.
1244 * @data: ioctl data blob
1247 * On error, the contents of the buffer that were to be modified are undefined.
1250 i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
1251 struct drm_file
*file
)
1253 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1254 struct drm_i915_gem_pwrite
*args
= data
;
1255 struct drm_i915_gem_object
*obj
;
1258 if (args
->size
== 0)
1261 if (!access_ok(VERIFY_READ
,
1262 u64_to_user_ptr(args
->data_ptr
),
1266 if (likely(!i915
.prefault_disable
)) {
1267 ret
= fault_in_multipages_readable(u64_to_user_ptr(args
->data_ptr
),
1273 intel_runtime_pm_get(dev_priv
);
1275 ret
= i915_mutex_lock_interruptible(dev
);
1279 obj
= to_intel_bo(drm_gem_object_lookup(file
, args
->handle
));
1280 if (&obj
->base
== NULL
) {
1285 /* Bounds check destination. */
1286 if (args
->offset
> obj
->base
.size
||
1287 args
->size
> obj
->base
.size
- args
->offset
) {
1292 trace_i915_gem_object_pwrite(obj
, args
->offset
, args
->size
);
1295 /* We can only do the GTT pwrite on untiled buffers, as otherwise
1296 * it would end up going through the fenced access, and we'll get
1297 * different detiling behavior between reading and writing.
1298 * pread/pwrite currently are reading and writing from the CPU
1299 * perspective, requiring manual detiling by the client.
1301 if (!obj
->base
.filp
|| cpu_write_needs_clflush(obj
)) {
1302 ret
= i915_gem_gtt_pwrite_fast(dev_priv
, obj
, args
, file
);
1303 /* Note that the gtt paths might fail with non-page-backed user
1304 * pointers (e.g. gtt mappings when moving data between
1305 * textures). Fallback to the shmem path in that case. */
1308 if (ret
== -EFAULT
) {
1309 if (obj
->phys_handle
)
1310 ret
= i915_gem_phys_pwrite(obj
, args
, file
);
1311 else if (obj
->base
.filp
)
1312 ret
= i915_gem_shmem_pwrite(dev
, obj
, args
, file
);
1318 drm_gem_object_unreference(&obj
->base
);
1320 mutex_unlock(&dev
->struct_mutex
);
1322 intel_runtime_pm_put(dev_priv
);
1328 i915_gem_check_wedge(unsigned reset_counter
, bool interruptible
)
1330 if (__i915_terminally_wedged(reset_counter
))
1333 if (__i915_reset_in_progress(reset_counter
)) {
1334 /* Non-interruptible callers can't handle -EAGAIN, hence return
1335 * -EIO unconditionally for these. */
1345 static void fake_irq(unsigned long data
)
1347 wake_up_process((struct task_struct
*)data
);
1350 static bool missed_irq(struct drm_i915_private
*dev_priv
,
1351 struct intel_engine_cs
*engine
)
1353 return test_bit(engine
->id
, &dev_priv
->gpu_error
.missed_irq_rings
);
1356 static unsigned long local_clock_us(unsigned *cpu
)
1360 /* Cheaply and approximately convert from nanoseconds to microseconds.
1361 * The result and subsequent calculations are also defined in the same
1362 * approximate microseconds units. The principal source of timing
1363 * error here is from the simple truncation.
1365 * Note that local_clock() is only defined wrt to the current CPU;
1366 * the comparisons are no longer valid if we switch CPUs. Instead of
1367 * blocking preemption for the entire busywait, we can detect the CPU
1368 * switch and use that as indicator of system load and a reason to
1369 * stop busywaiting, see busywait_stop().
1372 t
= local_clock() >> 10;
1378 static bool busywait_stop(unsigned long timeout
, unsigned cpu
)
1382 if (time_after(local_clock_us(&this_cpu
), timeout
))
1385 return this_cpu
!= cpu
;
1388 static int __i915_spin_request(struct drm_i915_gem_request
*req
, int state
)
1390 unsigned long timeout
;
1393 /* When waiting for high frequency requests, e.g. during synchronous
1394 * rendering split between the CPU and GPU, the finite amount of time
1395 * required to set up the irq and wait upon it limits the response
1396 * rate. By busywaiting on the request completion for a short while we
1397 * can service the high frequency waits as quick as possible. However,
1398 * if it is a slow request, we want to sleep as quickly as possible.
1399 * The tradeoff between waiting and sleeping is roughly the time it
1400 * takes to sleep on a request, on the order of a microsecond.
1403 if (req
->engine
->irq_refcount
)
1406 /* Only spin if we know the GPU is processing this request */
1407 if (!i915_gem_request_started(req
, true))
1410 timeout
= local_clock_us(&cpu
) + 5;
1411 while (!need_resched()) {
1412 if (i915_gem_request_completed(req
, true))
1415 if (signal_pending_state(state
, current
))
1418 if (busywait_stop(timeout
, cpu
))
1421 cpu_relax_lowlatency();
1424 if (i915_gem_request_completed(req
, false))
1431 * __i915_wait_request - wait until execution of request has finished
1433 * @interruptible: do an interruptible wait (normally yes)
1434 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
1437 * Note: It is of utmost importance that the passed in seqno and reset_counter
1438 * values have been read by the caller in an smp safe manner. Where read-side
1439 * locks are involved, it is sufficient to read the reset_counter before
1440 * unlocking the lock that protects the seqno. For lockless tricks, the
1441 * reset_counter _must_ be read before, and an appropriate smp_rmb must be
1444 * Returns 0 if the request was found within the alloted time. Else returns the
1445 * errno with remaining time filled in timeout argument.
1447 int __i915_wait_request(struct drm_i915_gem_request
*req
,
1450 struct intel_rps_client
*rps
)
1452 struct intel_engine_cs
*engine
= i915_gem_request_get_engine(req
);
1453 struct drm_i915_private
*dev_priv
= req
->i915
;
1454 const bool irq_test_in_progress
=
1455 ACCESS_ONCE(dev_priv
->gpu_error
.test_irq_rings
) & intel_engine_flag(engine
);
1456 int state
= interruptible
? TASK_INTERRUPTIBLE
: TASK_UNINTERRUPTIBLE
;
1458 unsigned long timeout_expire
;
1459 s64 before
= 0; /* Only to silence a compiler warning. */
1462 WARN(!intel_irqs_enabled(dev_priv
), "IRQs disabled");
1464 if (list_empty(&req
->list
))
1467 if (i915_gem_request_completed(req
, true))
1472 if (WARN_ON(*timeout
< 0))
1478 timeout_expire
= jiffies
+ nsecs_to_jiffies_timeout(*timeout
);
1481 * Record current time in case interrupted by signal, or wedged.
1483 before
= ktime_get_raw_ns();
1486 if (INTEL_INFO(dev_priv
)->gen
>= 6)
1487 gen6_rps_boost(dev_priv
, rps
, req
->emitted_jiffies
);
1489 trace_i915_gem_request_wait_begin(req
);
1491 /* Optimistic spin for the next jiffie before touching IRQs */
1492 ret
= __i915_spin_request(req
, state
);
1496 if (!irq_test_in_progress
&& WARN_ON(!engine
->irq_get(engine
))) {
1502 struct timer_list timer
;
1504 prepare_to_wait(&engine
->irq_queue
, &wait
, state
);
1506 /* We need to check whether any gpu reset happened in between
1507 * the request being submitted and now. If a reset has occurred,
1508 * the request is effectively complete (we either are in the
1509 * process of or have discarded the rendering and completely
1510 * reset the GPU. The results of the request are lost and we
1511 * are free to continue on with the original operation.
1513 if (req
->reset_counter
!= i915_reset_counter(&dev_priv
->gpu_error
)) {
1518 if (i915_gem_request_completed(req
, false)) {
1523 if (signal_pending_state(state
, current
)) {
1528 if (timeout
&& time_after_eq(jiffies
, timeout_expire
)) {
1533 timer
.function
= NULL
;
1534 if (timeout
|| missed_irq(dev_priv
, engine
)) {
1535 unsigned long expire
;
1537 setup_timer_on_stack(&timer
, fake_irq
, (unsigned long)current
);
1538 expire
= missed_irq(dev_priv
, engine
) ? jiffies
+ 1 : timeout_expire
;
1539 mod_timer(&timer
, expire
);
1544 if (timer
.function
) {
1545 del_singleshot_timer_sync(&timer
);
1546 destroy_timer_on_stack(&timer
);
1549 if (!irq_test_in_progress
)
1550 engine
->irq_put(engine
);
1552 finish_wait(&engine
->irq_queue
, &wait
);
1555 trace_i915_gem_request_wait_end(req
);
1558 s64 tres
= *timeout
- (ktime_get_raw_ns() - before
);
1560 *timeout
= tres
< 0 ? 0 : tres
;
1563 * Apparently ktime isn't accurate enough and occasionally has a
1564 * bit of mismatch in the jiffies<->nsecs<->ktime loop. So patch
1565 * things up to make the test happy. We allow up to 1 jiffy.
1567 * This is a regrssion from the timespec->ktime conversion.
1569 if (ret
== -ETIME
&& *timeout
< jiffies_to_usecs(1)*1000)
1576 int i915_gem_request_add_to_client(struct drm_i915_gem_request
*req
,
1577 struct drm_file
*file
)
1579 struct drm_i915_file_private
*file_priv
;
1581 WARN_ON(!req
|| !file
|| req
->file_priv
);
1589 file_priv
= file
->driver_priv
;
1591 spin_lock(&file_priv
->mm
.lock
);
1592 req
->file_priv
= file_priv
;
1593 list_add_tail(&req
->client_list
, &file_priv
->mm
.request_list
);
1594 spin_unlock(&file_priv
->mm
.lock
);
1596 req
->pid
= get_pid(task_pid(current
));
1602 i915_gem_request_remove_from_client(struct drm_i915_gem_request
*request
)
1604 struct drm_i915_file_private
*file_priv
= request
->file_priv
;
1609 spin_lock(&file_priv
->mm
.lock
);
1610 list_del(&request
->client_list
);
1611 request
->file_priv
= NULL
;
1612 spin_unlock(&file_priv
->mm
.lock
);
1614 put_pid(request
->pid
);
1615 request
->pid
= NULL
;
1618 static void i915_gem_request_retire(struct drm_i915_gem_request
*request
)
1620 trace_i915_gem_request_retire(request
);
1622 /* We know the GPU must have read the request to have
1623 * sent us the seqno + interrupt, so use the position
1624 * of tail of the request to update the last known position
1627 * Note this requires that we are always called in request
1630 request
->ringbuf
->last_retired_head
= request
->postfix
;
1632 list_del_init(&request
->list
);
1633 i915_gem_request_remove_from_client(request
);
1635 if (request
->previous_context
) {
1636 if (i915
.enable_execlists
)
1637 intel_lr_context_unpin(request
->previous_context
,
1641 i915_gem_context_unreference(request
->ctx
);
1642 i915_gem_request_unreference(request
);
1646 __i915_gem_request_retire__upto(struct drm_i915_gem_request
*req
)
1648 struct intel_engine_cs
*engine
= req
->engine
;
1649 struct drm_i915_gem_request
*tmp
;
1651 lockdep_assert_held(&engine
->i915
->dev
->struct_mutex
);
1653 if (list_empty(&req
->list
))
1657 tmp
= list_first_entry(&engine
->request_list
,
1658 typeof(*tmp
), list
);
1660 i915_gem_request_retire(tmp
);
1661 } while (tmp
!= req
);
1663 WARN_ON(i915_verify_lists(engine
->dev
));
1667 * Waits for a request to be signaled, and cleans up the
1668 * request and object lists appropriately for that event.
1669 * @req: request to wait on
1672 i915_wait_request(struct drm_i915_gem_request
*req
)
1674 struct drm_i915_private
*dev_priv
= req
->i915
;
1678 interruptible
= dev_priv
->mm
.interruptible
;
1680 BUG_ON(!mutex_is_locked(&dev_priv
->dev
->struct_mutex
));
1682 ret
= __i915_wait_request(req
, interruptible
, NULL
, NULL
);
1686 /* If the GPU hung, we want to keep the requests to find the guilty. */
1687 if (req
->reset_counter
== i915_reset_counter(&dev_priv
->gpu_error
))
1688 __i915_gem_request_retire__upto(req
);
1694 * Ensures that all rendering to the object has completed and the object is
1695 * safe to unbind from the GTT or access from the CPU.
1696 * @obj: i915 gem object
1697 * @readonly: waiting for read access or write
1700 i915_gem_object_wait_rendering(struct drm_i915_gem_object
*obj
,
1709 if (obj
->last_write_req
!= NULL
) {
1710 ret
= i915_wait_request(obj
->last_write_req
);
1714 i
= obj
->last_write_req
->engine
->id
;
1715 if (obj
->last_read_req
[i
] == obj
->last_write_req
)
1716 i915_gem_object_retire__read(obj
, i
);
1718 i915_gem_object_retire__write(obj
);
1721 for (i
= 0; i
< I915_NUM_ENGINES
; i
++) {
1722 if (obj
->last_read_req
[i
] == NULL
)
1725 ret
= i915_wait_request(obj
->last_read_req
[i
]);
1729 i915_gem_object_retire__read(obj
, i
);
1731 GEM_BUG_ON(obj
->active
);
1738 i915_gem_object_retire_request(struct drm_i915_gem_object
*obj
,
1739 struct drm_i915_gem_request
*req
)
1741 int ring
= req
->engine
->id
;
1743 if (obj
->last_read_req
[ring
] == req
)
1744 i915_gem_object_retire__read(obj
, ring
);
1745 else if (obj
->last_write_req
== req
)
1746 i915_gem_object_retire__write(obj
);
1748 if (req
->reset_counter
== i915_reset_counter(&req
->i915
->gpu_error
))
1749 __i915_gem_request_retire__upto(req
);
1752 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1753 * as the object state may change during this call.
1755 static __must_check
int
1756 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object
*obj
,
1757 struct intel_rps_client
*rps
,
1760 struct drm_device
*dev
= obj
->base
.dev
;
1761 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1762 struct drm_i915_gem_request
*requests
[I915_NUM_ENGINES
];
1765 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
1766 BUG_ON(!dev_priv
->mm
.interruptible
);
1772 struct drm_i915_gem_request
*req
;
1774 req
= obj
->last_write_req
;
1778 requests
[n
++] = i915_gem_request_reference(req
);
1780 for (i
= 0; i
< I915_NUM_ENGINES
; i
++) {
1781 struct drm_i915_gem_request
*req
;
1783 req
= obj
->last_read_req
[i
];
1787 requests
[n
++] = i915_gem_request_reference(req
);
1791 mutex_unlock(&dev
->struct_mutex
);
1793 for (i
= 0; ret
== 0 && i
< n
; i
++)
1794 ret
= __i915_wait_request(requests
[i
], true, NULL
, rps
);
1795 mutex_lock(&dev
->struct_mutex
);
1797 for (i
= 0; i
< n
; i
++) {
1799 i915_gem_object_retire_request(obj
, requests
[i
]);
1800 i915_gem_request_unreference(requests
[i
]);
1806 static struct intel_rps_client
*to_rps_client(struct drm_file
*file
)
1808 struct drm_i915_file_private
*fpriv
= file
->driver_priv
;
1813 * Called when user space prepares to use an object with the CPU, either
1814 * through the mmap ioctl's mapping or a GTT mapping.
1816 * @data: ioctl data blob
1820 i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
1821 struct drm_file
*file
)
1823 struct drm_i915_gem_set_domain
*args
= data
;
1824 struct drm_i915_gem_object
*obj
;
1825 uint32_t read_domains
= args
->read_domains
;
1826 uint32_t write_domain
= args
->write_domain
;
1829 /* Only handle setting domains to types used by the CPU. */
1830 if (write_domain
& I915_GEM_GPU_DOMAINS
)
1833 if (read_domains
& I915_GEM_GPU_DOMAINS
)
1836 /* Having something in the write domain implies it's in the read
1837 * domain, and only that read domain. Enforce that in the request.
1839 if (write_domain
!= 0 && read_domains
!= write_domain
)
1842 ret
= i915_mutex_lock_interruptible(dev
);
1846 obj
= to_intel_bo(drm_gem_object_lookup(file
, args
->handle
));
1847 if (&obj
->base
== NULL
) {
1852 /* Try to flush the object off the GPU without holding the lock.
1853 * We will repeat the flush holding the lock in the normal manner
1854 * to catch cases where we are gazumped.
1856 ret
= i915_gem_object_wait_rendering__nonblocking(obj
,
1857 to_rps_client(file
),
1862 if (read_domains
& I915_GEM_DOMAIN_GTT
)
1863 ret
= i915_gem_object_set_to_gtt_domain(obj
, write_domain
!= 0);
1865 ret
= i915_gem_object_set_to_cpu_domain(obj
, write_domain
!= 0);
1867 if (write_domain
!= 0)
1868 intel_fb_obj_invalidate(obj
,
1869 write_domain
== I915_GEM_DOMAIN_GTT
?
1870 ORIGIN_GTT
: ORIGIN_CPU
);
1873 drm_gem_object_unreference(&obj
->base
);
1875 mutex_unlock(&dev
->struct_mutex
);
1880 * Called when user space has done writes to this buffer
1882 * @data: ioctl data blob
1886 i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1887 struct drm_file
*file
)
1889 struct drm_i915_gem_sw_finish
*args
= data
;
1890 struct drm_i915_gem_object
*obj
;
1893 ret
= i915_mutex_lock_interruptible(dev
);
1897 obj
= to_intel_bo(drm_gem_object_lookup(file
, args
->handle
));
1898 if (&obj
->base
== NULL
) {
1903 /* Pinned buffers may be scanout, so flush the cache */
1904 if (obj
->pin_display
)
1905 i915_gem_object_flush_cpu_write_domain(obj
);
1907 drm_gem_object_unreference(&obj
->base
);
1909 mutex_unlock(&dev
->struct_mutex
);
1914 * i915_gem_mmap_ioctl - Maps the contents of an object, returning the address
1917 * @data: ioctl data blob
1920 * While the mapping holds a reference on the contents of the object, it doesn't
1921 * imply a ref on the object itself.
1925 * DRM driver writers who look a this function as an example for how to do GEM
1926 * mmap support, please don't implement mmap support like here. The modern way
1927 * to implement DRM mmap support is with an mmap offset ioctl (like
1928 * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly.
1929 * That way debug tooling like valgrind will understand what's going on, hiding
1930 * the mmap call in a driver private ioctl will break that. The i915 driver only
1931 * does cpu mmaps this way because we didn't know better.
1934 i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1935 struct drm_file
*file
)
1937 struct drm_i915_gem_mmap
*args
= data
;
1938 struct drm_gem_object
*obj
;
1941 if (args
->flags
& ~(I915_MMAP_WC
))
1944 if (args
->flags
& I915_MMAP_WC
&& !boot_cpu_has(X86_FEATURE_PAT
))
1947 obj
= drm_gem_object_lookup(file
, args
->handle
);
1951 /* prime objects have no backing filp to GEM mmap
1955 drm_gem_object_unreference_unlocked(obj
);
1959 addr
= vm_mmap(obj
->filp
, 0, args
->size
,
1960 PROT_READ
| PROT_WRITE
, MAP_SHARED
,
1962 if (args
->flags
& I915_MMAP_WC
) {
1963 struct mm_struct
*mm
= current
->mm
;
1964 struct vm_area_struct
*vma
;
1966 if (down_write_killable(&mm
->mmap_sem
)) {
1967 drm_gem_object_unreference_unlocked(obj
);
1970 vma
= find_vma(mm
, addr
);
1973 pgprot_writecombine(vm_get_page_prot(vma
->vm_flags
));
1976 up_write(&mm
->mmap_sem
);
1978 drm_gem_object_unreference_unlocked(obj
);
1979 if (IS_ERR((void *)addr
))
1982 args
->addr_ptr
= (uint64_t) addr
;
1988 * i915_gem_fault - fault a page into the GTT
1989 * @vma: VMA in question
1992 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1993 * from userspace. The fault handler takes care of binding the object to
1994 * the GTT (if needed), allocating and programming a fence register (again,
1995 * only if needed based on whether the old reg is still valid or the object
1996 * is tiled) and inserting a new PTE into the faulting process.
1998 * Note that the faulting process may involve evicting existing objects
1999 * from the GTT and/or fence registers to make room. So performance may
2000 * suffer if the GTT working set is large or there are few fence registers
2003 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
)
2005 struct drm_i915_gem_object
*obj
= to_intel_bo(vma
->vm_private_data
);
2006 struct drm_device
*dev
= obj
->base
.dev
;
2007 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2008 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
2009 struct i915_ggtt_view view
= i915_ggtt_view_normal
;
2010 pgoff_t page_offset
;
2013 bool write
= !!(vmf
->flags
& FAULT_FLAG_WRITE
);
2015 intel_runtime_pm_get(dev_priv
);
2017 /* We don't use vmf->pgoff since that has the fake offset */
2018 page_offset
= ((unsigned long)vmf
->virtual_address
- vma
->vm_start
) >>
2021 ret
= i915_mutex_lock_interruptible(dev
);
2025 trace_i915_gem_object_fault(obj
, page_offset
, true, write
);
2027 /* Try to flush the object off the GPU first without holding the lock.
2028 * Upon reacquiring the lock, we will perform our sanity checks and then
2029 * repeat the flush holding the lock in the normal manner to catch cases
2030 * where we are gazumped.
2032 ret
= i915_gem_object_wait_rendering__nonblocking(obj
, NULL
, !write
);
2036 /* Access to snoopable pages through the GTT is incoherent. */
2037 if (obj
->cache_level
!= I915_CACHE_NONE
&& !HAS_LLC(dev
)) {
2042 /* Use a partial view if the object is bigger than the aperture. */
2043 if (obj
->base
.size
>= ggtt
->mappable_end
&&
2044 obj
->tiling_mode
== I915_TILING_NONE
) {
2045 static const unsigned int chunk_size
= 256; // 1 MiB
2047 memset(&view
, 0, sizeof(view
));
2048 view
.type
= I915_GGTT_VIEW_PARTIAL
;
2049 view
.params
.partial
.offset
= rounddown(page_offset
, chunk_size
);
2050 view
.params
.partial
.size
=
2053 (vma
->vm_end
- vma
->vm_start
)/PAGE_SIZE
-
2054 view
.params
.partial
.offset
);
2057 /* Now pin it into the GTT if needed */
2058 ret
= i915_gem_object_ggtt_pin(obj
, &view
, 0, PIN_MAPPABLE
);
2062 ret
= i915_gem_object_set_to_gtt_domain(obj
, write
);
2066 ret
= i915_gem_object_get_fence(obj
);
2070 /* Finally, remap it using the new GTT offset */
2071 pfn
= ggtt
->mappable_base
+
2072 i915_gem_obj_ggtt_offset_view(obj
, &view
);
2075 if (unlikely(view
.type
== I915_GGTT_VIEW_PARTIAL
)) {
2076 /* Overriding existing pages in partial view does not cause
2077 * us any trouble as TLBs are still valid because the fault
2078 * is due to userspace losing part of the mapping or never
2079 * having accessed it before (at this partials' range).
2081 unsigned long base
= vma
->vm_start
+
2082 (view
.params
.partial
.offset
<< PAGE_SHIFT
);
2085 for (i
= 0; i
< view
.params
.partial
.size
; i
++) {
2086 ret
= vm_insert_pfn(vma
, base
+ i
* PAGE_SIZE
, pfn
+ i
);
2091 obj
->fault_mappable
= true;
2093 if (!obj
->fault_mappable
) {
2094 unsigned long size
= min_t(unsigned long,
2095 vma
->vm_end
- vma
->vm_start
,
2099 for (i
= 0; i
< size
>> PAGE_SHIFT
; i
++) {
2100 ret
= vm_insert_pfn(vma
,
2101 (unsigned long)vma
->vm_start
+ i
* PAGE_SIZE
,
2107 obj
->fault_mappable
= true;
2109 ret
= vm_insert_pfn(vma
,
2110 (unsigned long)vmf
->virtual_address
,
2114 i915_gem_object_ggtt_unpin_view(obj
, &view
);
2116 mutex_unlock(&dev
->struct_mutex
);
2121 * We eat errors when the gpu is terminally wedged to avoid
2122 * userspace unduly crashing (gl has no provisions for mmaps to
2123 * fail). But any other -EIO isn't ours (e.g. swap in failure)
2124 * and so needs to be reported.
2126 if (!i915_terminally_wedged(&dev_priv
->gpu_error
)) {
2127 ret
= VM_FAULT_SIGBUS
;
2132 * EAGAIN means the gpu is hung and we'll wait for the error
2133 * handler to reset everything when re-faulting in
2134 * i915_mutex_lock_interruptible.
2141 * EBUSY is ok: this just means that another thread
2142 * already did the job.
2144 ret
= VM_FAULT_NOPAGE
;
2151 ret
= VM_FAULT_SIGBUS
;
2154 WARN_ONCE(ret
, "unhandled error in i915_gem_fault: %i\n", ret
);
2155 ret
= VM_FAULT_SIGBUS
;
2159 intel_runtime_pm_put(dev_priv
);
2164 * i915_gem_release_mmap - remove physical page mappings
2165 * @obj: obj in question
2167 * Preserve the reservation of the mmapping with the DRM core code, but
2168 * relinquish ownership of the pages back to the system.
2170 * It is vital that we remove the page mapping if we have mapped a tiled
2171 * object through the GTT and then lose the fence register due to
2172 * resource pressure. Similarly if the object has been moved out of the
2173 * aperture, than pages mapped into userspace must be revoked. Removing the
2174 * mapping will then trigger a page fault on the next user access, allowing
2175 * fixup by i915_gem_fault().
2178 i915_gem_release_mmap(struct drm_i915_gem_object
*obj
)
2180 /* Serialisation between user GTT access and our code depends upon
2181 * revoking the CPU's PTE whilst the mutex is held. The next user
2182 * pagefault then has to wait until we release the mutex.
2184 lockdep_assert_held(&obj
->base
.dev
->struct_mutex
);
2186 if (!obj
->fault_mappable
)
2189 drm_vma_node_unmap(&obj
->base
.vma_node
,
2190 obj
->base
.dev
->anon_inode
->i_mapping
);
2192 /* Ensure that the CPU's PTE are revoked and there are not outstanding
2193 * memory transactions from userspace before we return. The TLB
2194 * flushing implied above by changing the PTE above *should* be
2195 * sufficient, an extra barrier here just provides us with a bit
2196 * of paranoid documentation about our requirement to serialise
2197 * memory writes before touching registers / GSM.
2201 obj
->fault_mappable
= false;
2205 i915_gem_release_all_mmaps(struct drm_i915_private
*dev_priv
)
2207 struct drm_i915_gem_object
*obj
;
2209 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
)
2210 i915_gem_release_mmap(obj
);
2214 i915_gem_get_gtt_size(struct drm_device
*dev
, uint32_t size
, int tiling_mode
)
2218 if (INTEL_INFO(dev
)->gen
>= 4 ||
2219 tiling_mode
== I915_TILING_NONE
)
2222 /* Previous chips need a power-of-two fence region when tiling */
2224 gtt_size
= 1024*1024;
2226 gtt_size
= 512*1024;
2228 while (gtt_size
< size
)
2235 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
2237 * @size: object size
2238 * @tiling_mode: tiling mode
2239 * @fenced: is fenced alignemned required or not
2241 * Return the required GTT alignment for an object, taking into account
2242 * potential fence register mapping.
2245 i915_gem_get_gtt_alignment(struct drm_device
*dev
, uint32_t size
,
2246 int tiling_mode
, bool fenced
)
2249 * Minimum alignment is 4k (GTT page size), but might be greater
2250 * if a fence register is needed for the object.
2252 if (INTEL_INFO(dev
)->gen
>= 4 || (!fenced
&& IS_G33(dev
)) ||
2253 tiling_mode
== I915_TILING_NONE
)
2257 * Previous chips need to be aligned to the size of the smallest
2258 * fence register that can contain the object.
2260 return i915_gem_get_gtt_size(dev
, size
, tiling_mode
);
2263 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object
*obj
)
2265 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2268 dev_priv
->mm
.shrinker_no_lock_stealing
= true;
2270 ret
= drm_gem_create_mmap_offset(&obj
->base
);
2274 /* Badly fragmented mmap space? The only way we can recover
2275 * space is by destroying unwanted objects. We can't randomly release
2276 * mmap_offsets as userspace expects them to be persistent for the
2277 * lifetime of the objects. The closest we can is to release the
2278 * offsets on purgeable objects by truncating it and marking it purged,
2279 * which prevents userspace from ever using that object again.
2281 i915_gem_shrink(dev_priv
,
2282 obj
->base
.size
>> PAGE_SHIFT
,
2284 I915_SHRINK_UNBOUND
|
2285 I915_SHRINK_PURGEABLE
);
2286 ret
= drm_gem_create_mmap_offset(&obj
->base
);
2290 i915_gem_shrink_all(dev_priv
);
2291 ret
= drm_gem_create_mmap_offset(&obj
->base
);
2293 dev_priv
->mm
.shrinker_no_lock_stealing
= false;
2298 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object
*obj
)
2300 drm_gem_free_mmap_offset(&obj
->base
);
2304 i915_gem_mmap_gtt(struct drm_file
*file
,
2305 struct drm_device
*dev
,
2309 struct drm_i915_gem_object
*obj
;
2312 ret
= i915_mutex_lock_interruptible(dev
);
2316 obj
= to_intel_bo(drm_gem_object_lookup(file
, handle
));
2317 if (&obj
->base
== NULL
) {
2322 if (obj
->madv
!= I915_MADV_WILLNEED
) {
2323 DRM_DEBUG("Attempting to mmap a purgeable buffer\n");
2328 ret
= i915_gem_object_create_mmap_offset(obj
);
2332 *offset
= drm_vma_node_offset_addr(&obj
->base
.vma_node
);
2335 drm_gem_object_unreference(&obj
->base
);
2337 mutex_unlock(&dev
->struct_mutex
);
2342 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
2344 * @data: GTT mapping ioctl data
2345 * @file: GEM object info
2347 * Simply returns the fake offset to userspace so it can mmap it.
2348 * The mmap call will end up in drm_gem_mmap(), which will set things
2349 * up so we can get faults in the handler above.
2351 * The fault handler will take care of binding the object into the GTT
2352 * (since it may have been evicted to make room for something), allocating
2353 * a fence register, and mapping the appropriate aperture address into
2357 i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
2358 struct drm_file
*file
)
2360 struct drm_i915_gem_mmap_gtt
*args
= data
;
2362 return i915_gem_mmap_gtt(file
, dev
, args
->handle
, &args
->offset
);
2365 /* Immediately discard the backing storage */
2367 i915_gem_object_truncate(struct drm_i915_gem_object
*obj
)
2369 i915_gem_object_free_mmap_offset(obj
);
2371 if (obj
->base
.filp
== NULL
)
2374 /* Our goal here is to return as much of the memory as
2375 * is possible back to the system as we are called from OOM.
2376 * To do this we must instruct the shmfs to drop all of its
2377 * backing pages, *now*.
2379 shmem_truncate_range(file_inode(obj
->base
.filp
), 0, (loff_t
)-1);
2380 obj
->madv
= __I915_MADV_PURGED
;
2383 /* Try to discard unwanted pages */
2385 i915_gem_object_invalidate(struct drm_i915_gem_object
*obj
)
2387 struct address_space
*mapping
;
2389 switch (obj
->madv
) {
2390 case I915_MADV_DONTNEED
:
2391 i915_gem_object_truncate(obj
);
2392 case __I915_MADV_PURGED
:
2396 if (obj
->base
.filp
== NULL
)
2399 mapping
= file_inode(obj
->base
.filp
)->i_mapping
,
2400 invalidate_mapping_pages(mapping
, 0, (loff_t
)-1);
2404 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object
*obj
)
2406 struct sgt_iter sgt_iter
;
2410 BUG_ON(obj
->madv
== __I915_MADV_PURGED
);
2412 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
2414 /* In the event of a disaster, abandon all caches and
2415 * hope for the best.
2417 i915_gem_clflush_object(obj
, true);
2418 obj
->base
.read_domains
= obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
2421 i915_gem_gtt_finish_object(obj
);
2423 if (i915_gem_object_needs_bit17_swizzle(obj
))
2424 i915_gem_object_save_bit_17_swizzle(obj
);
2426 if (obj
->madv
== I915_MADV_DONTNEED
)
2429 for_each_sgt_page(page
, sgt_iter
, obj
->pages
) {
2431 set_page_dirty(page
);
2433 if (obj
->madv
== I915_MADV_WILLNEED
)
2434 mark_page_accessed(page
);
2440 sg_free_table(obj
->pages
);
2445 i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
)
2447 const struct drm_i915_gem_object_ops
*ops
= obj
->ops
;
2449 if (obj
->pages
== NULL
)
2452 if (obj
->pages_pin_count
)
2455 BUG_ON(i915_gem_obj_bound_any(obj
));
2457 /* ->put_pages might need to allocate memory for the bit17 swizzle
2458 * array, hence protect them from being reaped by removing them from gtt
2460 list_del(&obj
->global_list
);
2463 if (is_vmalloc_addr(obj
->mapping
))
2464 vunmap(obj
->mapping
);
2466 kunmap(kmap_to_page(obj
->mapping
));
2467 obj
->mapping
= NULL
;
2470 ops
->put_pages(obj
);
2473 i915_gem_object_invalidate(obj
);
2479 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object
*obj
)
2481 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2483 struct address_space
*mapping
;
2484 struct sg_table
*st
;
2485 struct scatterlist
*sg
;
2486 struct sgt_iter sgt_iter
;
2488 unsigned long last_pfn
= 0; /* suppress gcc warning */
2492 /* Assert that the object is not currently in any GPU domain. As it
2493 * wasn't in the GTT, there shouldn't be any way it could have been in
2496 BUG_ON(obj
->base
.read_domains
& I915_GEM_GPU_DOMAINS
);
2497 BUG_ON(obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
);
2499 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
2503 page_count
= obj
->base
.size
/ PAGE_SIZE
;
2504 if (sg_alloc_table(st
, page_count
, GFP_KERNEL
)) {
2509 /* Get the list of pages out of our struct file. They'll be pinned
2510 * at this point until we release them.
2512 * Fail silently without starting the shrinker
2514 mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
2515 gfp
= mapping_gfp_constraint(mapping
, ~(__GFP_IO
| __GFP_RECLAIM
));
2516 gfp
|= __GFP_NORETRY
| __GFP_NOWARN
;
2519 for (i
= 0; i
< page_count
; i
++) {
2520 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
2522 i915_gem_shrink(dev_priv
,
2525 I915_SHRINK_UNBOUND
|
2526 I915_SHRINK_PURGEABLE
);
2527 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
2530 /* We've tried hard to allocate the memory by reaping
2531 * our own buffer, now let the real VM do its job and
2532 * go down in flames if truly OOM.
2534 i915_gem_shrink_all(dev_priv
);
2535 page
= shmem_read_mapping_page(mapping
, i
);
2537 ret
= PTR_ERR(page
);
2541 #ifdef CONFIG_SWIOTLB
2542 if (swiotlb_nr_tbl()) {
2544 sg_set_page(sg
, page
, PAGE_SIZE
, 0);
2549 if (!i
|| page_to_pfn(page
) != last_pfn
+ 1) {
2553 sg_set_page(sg
, page
, PAGE_SIZE
, 0);
2555 sg
->length
+= PAGE_SIZE
;
2557 last_pfn
= page_to_pfn(page
);
2559 /* Check that the i965g/gm workaround works. */
2560 WARN_ON((gfp
& __GFP_DMA32
) && (last_pfn
>= 0x00100000UL
));
2562 #ifdef CONFIG_SWIOTLB
2563 if (!swiotlb_nr_tbl())
2568 ret
= i915_gem_gtt_prepare_object(obj
);
2572 if (i915_gem_object_needs_bit17_swizzle(obj
))
2573 i915_gem_object_do_bit_17_swizzle(obj
);
2575 if (obj
->tiling_mode
!= I915_TILING_NONE
&&
2576 dev_priv
->quirks
& QUIRK_PIN_SWIZZLED_PAGES
)
2577 i915_gem_object_pin_pages(obj
);
2583 for_each_sgt_page(page
, sgt_iter
, st
)
2588 /* shmemfs first checks if there is enough memory to allocate the page
2589 * and reports ENOSPC should there be insufficient, along with the usual
2590 * ENOMEM for a genuine allocation failure.
2592 * We use ENOSPC in our driver to mean that we have run out of aperture
2593 * space and so want to translate the error from shmemfs back to our
2594 * usual understanding of ENOMEM.
2602 /* Ensure that the associated pages are gathered from the backing storage
2603 * and pinned into our object. i915_gem_object_get_pages() may be called
2604 * multiple times before they are released by a single call to
2605 * i915_gem_object_put_pages() - once the pages are no longer referenced
2606 * either as a result of memory pressure (reaping pages under the shrinker)
2607 * or as the object is itself released.
2610 i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
)
2612 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2613 const struct drm_i915_gem_object_ops
*ops
= obj
->ops
;
2619 if (obj
->madv
!= I915_MADV_WILLNEED
) {
2620 DRM_DEBUG("Attempting to obtain a purgeable object\n");
2624 BUG_ON(obj
->pages_pin_count
);
2626 ret
= ops
->get_pages(obj
);
2630 list_add_tail(&obj
->global_list
, &dev_priv
->mm
.unbound_list
);
2632 obj
->get_page
.sg
= obj
->pages
->sgl
;
2633 obj
->get_page
.last
= 0;
2638 /* The 'mapping' part of i915_gem_object_pin_map() below */
2639 static void *i915_gem_object_map(const struct drm_i915_gem_object
*obj
)
2641 unsigned long n_pages
= obj
->base
.size
>> PAGE_SHIFT
;
2642 struct sg_table
*sgt
= obj
->pages
;
2643 struct sgt_iter sgt_iter
;
2645 struct page
*stack_pages
[32];
2646 struct page
**pages
= stack_pages
;
2647 unsigned long i
= 0;
2650 /* A single page can always be kmapped */
2652 return kmap(sg_page(sgt
->sgl
));
2654 if (n_pages
> ARRAY_SIZE(stack_pages
)) {
2655 /* Too big for stack -- allocate temporary array instead */
2656 pages
= drm_malloc_gfp(n_pages
, sizeof(*pages
), GFP_TEMPORARY
);
2661 for_each_sgt_page(page
, sgt_iter
, sgt
)
2664 /* Check that we have the expected number of pages */
2665 GEM_BUG_ON(i
!= n_pages
);
2667 addr
= vmap(pages
, n_pages
, 0, PAGE_KERNEL
);
2669 if (pages
!= stack_pages
)
2670 drm_free_large(pages
);
2675 /* get, pin, and map the pages of the object into kernel space */
2676 void *i915_gem_object_pin_map(struct drm_i915_gem_object
*obj
)
2680 lockdep_assert_held(&obj
->base
.dev
->struct_mutex
);
2682 ret
= i915_gem_object_get_pages(obj
);
2684 return ERR_PTR(ret
);
2686 i915_gem_object_pin_pages(obj
);
2688 if (!obj
->mapping
) {
2689 obj
->mapping
= i915_gem_object_map(obj
);
2690 if (!obj
->mapping
) {
2691 i915_gem_object_unpin_pages(obj
);
2692 return ERR_PTR(-ENOMEM
);
2696 return obj
->mapping
;
2699 void i915_vma_move_to_active(struct i915_vma
*vma
,
2700 struct drm_i915_gem_request
*req
)
2702 struct drm_i915_gem_object
*obj
= vma
->obj
;
2703 struct intel_engine_cs
*engine
;
2705 engine
= i915_gem_request_get_engine(req
);
2707 /* Add a reference if we're newly entering the active list. */
2708 if (obj
->active
== 0)
2709 drm_gem_object_reference(&obj
->base
);
2710 obj
->active
|= intel_engine_flag(engine
);
2712 list_move_tail(&obj
->engine_list
[engine
->id
], &engine
->active_list
);
2713 i915_gem_request_assign(&obj
->last_read_req
[engine
->id
], req
);
2715 list_move_tail(&vma
->vm_link
, &vma
->vm
->active_list
);
2719 i915_gem_object_retire__write(struct drm_i915_gem_object
*obj
)
2721 GEM_BUG_ON(obj
->last_write_req
== NULL
);
2722 GEM_BUG_ON(!(obj
->active
& intel_engine_flag(obj
->last_write_req
->engine
)));
2724 i915_gem_request_assign(&obj
->last_write_req
, NULL
);
2725 intel_fb_obj_flush(obj
, true, ORIGIN_CS
);
2729 i915_gem_object_retire__read(struct drm_i915_gem_object
*obj
, int ring
)
2731 struct i915_vma
*vma
;
2733 GEM_BUG_ON(obj
->last_read_req
[ring
] == NULL
);
2734 GEM_BUG_ON(!(obj
->active
& (1 << ring
)));
2736 list_del_init(&obj
->engine_list
[ring
]);
2737 i915_gem_request_assign(&obj
->last_read_req
[ring
], NULL
);
2739 if (obj
->last_write_req
&& obj
->last_write_req
->engine
->id
== ring
)
2740 i915_gem_object_retire__write(obj
);
2742 obj
->active
&= ~(1 << ring
);
2746 /* Bump our place on the bound list to keep it roughly in LRU order
2747 * so that we don't steal from recently used but inactive objects
2748 * (unless we are forced to ofc!)
2750 list_move_tail(&obj
->global_list
,
2751 &to_i915(obj
->base
.dev
)->mm
.bound_list
);
2753 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
) {
2754 if (!list_empty(&vma
->vm_link
))
2755 list_move_tail(&vma
->vm_link
, &vma
->vm
->inactive_list
);
2758 i915_gem_request_assign(&obj
->last_fenced_req
, NULL
);
2759 drm_gem_object_unreference(&obj
->base
);
2763 i915_gem_init_seqno(struct drm_i915_private
*dev_priv
, u32 seqno
)
2765 struct intel_engine_cs
*engine
;
2768 /* Carefully retire all requests without writing to the rings */
2769 for_each_engine(engine
, dev_priv
) {
2770 ret
= intel_engine_idle(engine
);
2774 i915_gem_retire_requests(dev_priv
);
2776 /* Finally reset hw state */
2777 for_each_engine(engine
, dev_priv
)
2778 intel_ring_init_seqno(engine
, seqno
);
2783 int i915_gem_set_seqno(struct drm_device
*dev
, u32 seqno
)
2785 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2791 /* HWS page needs to be set less than what we
2792 * will inject to ring
2794 ret
= i915_gem_init_seqno(dev_priv
, seqno
- 1);
2798 /* Carefully set the last_seqno value so that wrap
2799 * detection still works
2801 dev_priv
->next_seqno
= seqno
;
2802 dev_priv
->last_seqno
= seqno
- 1;
2803 if (dev_priv
->last_seqno
== 0)
2804 dev_priv
->last_seqno
--;
2810 i915_gem_get_seqno(struct drm_i915_private
*dev_priv
, u32
*seqno
)
2812 /* reserve 0 for non-seqno */
2813 if (dev_priv
->next_seqno
== 0) {
2814 int ret
= i915_gem_init_seqno(dev_priv
, 0);
2818 dev_priv
->next_seqno
= 1;
2821 *seqno
= dev_priv
->last_seqno
= dev_priv
->next_seqno
++;
2826 * NB: This function is not allowed to fail. Doing so would mean the the
2827 * request is not being tracked for completion but the work itself is
2828 * going to happen on the hardware. This would be a Bad Thing(tm).
2830 void __i915_add_request(struct drm_i915_gem_request
*request
,
2831 struct drm_i915_gem_object
*obj
,
2834 struct intel_engine_cs
*engine
;
2835 struct drm_i915_private
*dev_priv
;
2836 struct intel_ringbuffer
*ringbuf
;
2841 if (WARN_ON(request
== NULL
))
2844 engine
= request
->engine
;
2845 dev_priv
= request
->i915
;
2846 ringbuf
= request
->ringbuf
;
2849 * To ensure that this call will not fail, space for its emissions
2850 * should already have been reserved in the ring buffer. Let the ring
2851 * know that it is time to use that space up.
2853 request_start
= intel_ring_get_tail(ringbuf
);
2854 reserved_tail
= request
->reserved_space
;
2855 request
->reserved_space
= 0;
2858 * Emit any outstanding flushes - execbuf can fail to emit the flush
2859 * after having emitted the batchbuffer command. Hence we need to fix
2860 * things up similar to emitting the lazy request. The difference here
2861 * is that the flush _must_ happen before the next request, no matter
2865 if (i915
.enable_execlists
)
2866 ret
= logical_ring_flush_all_caches(request
);
2868 ret
= intel_ring_flush_all_caches(request
);
2869 /* Not allowed to fail! */
2870 WARN(ret
, "*_ring_flush_all_caches failed: %d!\n", ret
);
2873 trace_i915_gem_request_add(request
);
2875 request
->head
= request_start
;
2877 /* Whilst this request exists, batch_obj will be on the
2878 * active_list, and so will hold the active reference. Only when this
2879 * request is retired will the the batch_obj be moved onto the
2880 * inactive_list and lose its active reference. Hence we do not need
2881 * to explicitly hold another reference here.
2883 request
->batch_obj
= obj
;
2885 /* Seal the request and mark it as pending execution. Note that
2886 * we may inspect this state, without holding any locks, during
2887 * hangcheck. Hence we apply the barrier to ensure that we do not
2888 * see a more recent value in the hws than we are tracking.
2890 request
->emitted_jiffies
= jiffies
;
2891 request
->previous_seqno
= engine
->last_submitted_seqno
;
2892 smp_store_mb(engine
->last_submitted_seqno
, request
->seqno
);
2893 list_add_tail(&request
->list
, &engine
->request_list
);
2895 /* Record the position of the start of the request so that
2896 * should we detect the updated seqno part-way through the
2897 * GPU processing the request, we never over-estimate the
2898 * position of the head.
2900 request
->postfix
= intel_ring_get_tail(ringbuf
);
2902 if (i915
.enable_execlists
)
2903 ret
= engine
->emit_request(request
);
2905 ret
= engine
->add_request(request
);
2907 request
->tail
= intel_ring_get_tail(ringbuf
);
2909 /* Not allowed to fail! */
2910 WARN(ret
, "emit|add_request failed: %d!\n", ret
);
2912 i915_queue_hangcheck(engine
->i915
);
2914 queue_delayed_work(dev_priv
->wq
,
2915 &dev_priv
->mm
.retire_work
,
2916 round_jiffies_up_relative(HZ
));
2917 intel_mark_busy(dev_priv
);
2919 /* Sanity check that the reserved size was large enough. */
2920 ret
= intel_ring_get_tail(ringbuf
) - request_start
;
2922 ret
+= ringbuf
->size
;
2923 WARN_ONCE(ret
> reserved_tail
,
2924 "Not enough space reserved (%d bytes) "
2925 "for adding the request (%d bytes)\n",
2926 reserved_tail
, ret
);
2929 static bool i915_context_is_banned(struct drm_i915_private
*dev_priv
,
2930 const struct i915_gem_context
*ctx
)
2932 unsigned long elapsed
;
2934 elapsed
= get_seconds() - ctx
->hang_stats
.guilty_ts
;
2936 if (ctx
->hang_stats
.banned
)
2939 if (ctx
->hang_stats
.ban_period_seconds
&&
2940 elapsed
<= ctx
->hang_stats
.ban_period_seconds
) {
2941 if (!i915_gem_context_is_default(ctx
)) {
2942 DRM_DEBUG("context hanging too fast, banning!\n");
2944 } else if (i915_stop_ring_allow_ban(dev_priv
)) {
2945 if (i915_stop_ring_allow_warn(dev_priv
))
2946 DRM_ERROR("gpu hanging too fast, banning!\n");
2954 static void i915_set_reset_status(struct drm_i915_private
*dev_priv
,
2955 struct i915_gem_context
*ctx
,
2958 struct i915_ctx_hang_stats
*hs
;
2963 hs
= &ctx
->hang_stats
;
2966 hs
->banned
= i915_context_is_banned(dev_priv
, ctx
);
2968 hs
->guilty_ts
= get_seconds();
2970 hs
->batch_pending
++;
2974 void i915_gem_request_free(struct kref
*req_ref
)
2976 struct drm_i915_gem_request
*req
= container_of(req_ref
,
2978 kmem_cache_free(req
->i915
->requests
, req
);
2982 __i915_gem_request_alloc(struct intel_engine_cs
*engine
,
2983 struct i915_gem_context
*ctx
,
2984 struct drm_i915_gem_request
**req_out
)
2986 struct drm_i915_private
*dev_priv
= engine
->i915
;
2987 unsigned reset_counter
= i915_reset_counter(&dev_priv
->gpu_error
);
2988 struct drm_i915_gem_request
*req
;
2996 /* ABI: Before userspace accesses the GPU (e.g. execbuffer), report
2997 * EIO if the GPU is already wedged, or EAGAIN to drop the struct_mutex
3000 ret
= i915_gem_check_wedge(reset_counter
, dev_priv
->mm
.interruptible
);
3004 req
= kmem_cache_zalloc(dev_priv
->requests
, GFP_KERNEL
);
3008 ret
= i915_gem_get_seqno(engine
->i915
, &req
->seqno
);
3012 kref_init(&req
->ref
);
3013 req
->i915
= dev_priv
;
3014 req
->engine
= engine
;
3015 req
->reset_counter
= reset_counter
;
3017 i915_gem_context_reference(req
->ctx
);
3020 * Reserve space in the ring buffer for all the commands required to
3021 * eventually emit this request. This is to guarantee that the
3022 * i915_add_request() call can't fail. Note that the reserve may need
3023 * to be redone if the request is not actually submitted straight
3024 * away, e.g. because a GPU scheduler has deferred it.
3026 req
->reserved_space
= MIN_SPACE_FOR_ADD_REQUEST
;
3028 if (i915
.enable_execlists
)
3029 ret
= intel_logical_ring_alloc_request_extras(req
);
3031 ret
= intel_ring_alloc_request_extras(req
);
3039 i915_gem_context_unreference(ctx
);
3041 kmem_cache_free(dev_priv
->requests
, req
);
3046 * i915_gem_request_alloc - allocate a request structure
3048 * @engine: engine that we wish to issue the request on.
3049 * @ctx: context that the request will be associated with.
3050 * This can be NULL if the request is not directly related to
3051 * any specific user context, in which case this function will
3052 * choose an appropriate context to use.
3054 * Returns a pointer to the allocated request if successful,
3055 * or an error code if not.
3057 struct drm_i915_gem_request
*
3058 i915_gem_request_alloc(struct intel_engine_cs
*engine
,
3059 struct i915_gem_context
*ctx
)
3061 struct drm_i915_gem_request
*req
;
3065 ctx
= engine
->i915
->kernel_context
;
3066 err
= __i915_gem_request_alloc(engine
, ctx
, &req
);
3067 return err
? ERR_PTR(err
) : req
;
3070 struct drm_i915_gem_request
*
3071 i915_gem_find_active_request(struct intel_engine_cs
*engine
)
3073 struct drm_i915_gem_request
*request
;
3075 list_for_each_entry(request
, &engine
->request_list
, list
) {
3076 if (i915_gem_request_completed(request
, false))
3085 static void i915_gem_reset_engine_status(struct drm_i915_private
*dev_priv
,
3086 struct intel_engine_cs
*engine
)
3088 struct drm_i915_gem_request
*request
;
3091 request
= i915_gem_find_active_request(engine
);
3093 if (request
== NULL
)
3096 ring_hung
= engine
->hangcheck
.score
>= HANGCHECK_SCORE_RING_HUNG
;
3098 i915_set_reset_status(dev_priv
, request
->ctx
, ring_hung
);
3100 list_for_each_entry_continue(request
, &engine
->request_list
, list
)
3101 i915_set_reset_status(dev_priv
, request
->ctx
, false);
3104 static void i915_gem_reset_engine_cleanup(struct drm_i915_private
*dev_priv
,
3105 struct intel_engine_cs
*engine
)
3107 struct intel_ringbuffer
*buffer
;
3109 while (!list_empty(&engine
->active_list
)) {
3110 struct drm_i915_gem_object
*obj
;
3112 obj
= list_first_entry(&engine
->active_list
,
3113 struct drm_i915_gem_object
,
3114 engine_list
[engine
->id
]);
3116 i915_gem_object_retire__read(obj
, engine
->id
);
3120 * Clear the execlists queue up before freeing the requests, as those
3121 * are the ones that keep the context and ringbuffer backing objects
3125 if (i915
.enable_execlists
) {
3126 /* Ensure irq handler finishes or is cancelled. */
3127 tasklet_kill(&engine
->irq_tasklet
);
3129 intel_execlists_cancel_requests(engine
);
3133 * We must free the requests after all the corresponding objects have
3134 * been moved off active lists. Which is the same order as the normal
3135 * retire_requests function does. This is important if object hold
3136 * implicit references on things like e.g. ppgtt address spaces through
3139 while (!list_empty(&engine
->request_list
)) {
3140 struct drm_i915_gem_request
*request
;
3142 request
= list_first_entry(&engine
->request_list
,
3143 struct drm_i915_gem_request
,
3146 i915_gem_request_retire(request
);
3149 /* Having flushed all requests from all queues, we know that all
3150 * ringbuffers must now be empty. However, since we do not reclaim
3151 * all space when retiring the request (to prevent HEADs colliding
3152 * with rapid ringbuffer wraparound) the amount of available space
3153 * upon reset is less than when we start. Do one more pass over
3154 * all the ringbuffers to reset last_retired_head.
3156 list_for_each_entry(buffer
, &engine
->buffers
, link
) {
3157 buffer
->last_retired_head
= buffer
->tail
;
3158 intel_ring_update_space(buffer
);
3161 intel_ring_init_seqno(engine
, engine
->last_submitted_seqno
);
3164 void i915_gem_reset(struct drm_device
*dev
)
3166 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3167 struct intel_engine_cs
*engine
;
3170 * Before we free the objects from the requests, we need to inspect
3171 * them for finding the guilty party. As the requests only borrow
3172 * their reference to the objects, the inspection must be done first.
3174 for_each_engine(engine
, dev_priv
)
3175 i915_gem_reset_engine_status(dev_priv
, engine
);
3177 for_each_engine(engine
, dev_priv
)
3178 i915_gem_reset_engine_cleanup(dev_priv
, engine
);
3180 i915_gem_context_reset(dev
);
3182 i915_gem_restore_fences(dev
);
3184 WARN_ON(i915_verify_lists(dev
));
3188 * This function clears the request list as sequence numbers are passed.
3189 * @engine: engine to retire requests on
3192 i915_gem_retire_requests_ring(struct intel_engine_cs
*engine
)
3194 WARN_ON(i915_verify_lists(engine
->dev
));
3196 /* Retire requests first as we use it above for the early return.
3197 * If we retire requests last, we may use a later seqno and so clear
3198 * the requests lists without clearing the active list, leading to
3201 while (!list_empty(&engine
->request_list
)) {
3202 struct drm_i915_gem_request
*request
;
3204 request
= list_first_entry(&engine
->request_list
,
3205 struct drm_i915_gem_request
,
3208 if (!i915_gem_request_completed(request
, true))
3211 i915_gem_request_retire(request
);
3214 /* Move any buffers on the active list that are no longer referenced
3215 * by the ringbuffer to the flushing/inactive lists as appropriate,
3216 * before we free the context associated with the requests.
3218 while (!list_empty(&engine
->active_list
)) {
3219 struct drm_i915_gem_object
*obj
;
3221 obj
= list_first_entry(&engine
->active_list
,
3222 struct drm_i915_gem_object
,
3223 engine_list
[engine
->id
]);
3225 if (!list_empty(&obj
->last_read_req
[engine
->id
]->list
))
3228 i915_gem_object_retire__read(obj
, engine
->id
);
3231 if (unlikely(engine
->trace_irq_req
&&
3232 i915_gem_request_completed(engine
->trace_irq_req
, true))) {
3233 engine
->irq_put(engine
);
3234 i915_gem_request_assign(&engine
->trace_irq_req
, NULL
);
3237 WARN_ON(i915_verify_lists(engine
->dev
));
3241 i915_gem_retire_requests(struct drm_i915_private
*dev_priv
)
3243 struct intel_engine_cs
*engine
;
3246 for_each_engine(engine
, dev_priv
) {
3247 i915_gem_retire_requests_ring(engine
);
3248 idle
&= list_empty(&engine
->request_list
);
3249 if (i915
.enable_execlists
) {
3250 spin_lock_bh(&engine
->execlist_lock
);
3251 idle
&= list_empty(&engine
->execlist_queue
);
3252 spin_unlock_bh(&engine
->execlist_lock
);
3257 mod_delayed_work(dev_priv
->wq
,
3258 &dev_priv
->mm
.idle_work
,
3259 msecs_to_jiffies(100));
3265 i915_gem_retire_work_handler(struct work_struct
*work
)
3267 struct drm_i915_private
*dev_priv
=
3268 container_of(work
, typeof(*dev_priv
), mm
.retire_work
.work
);
3269 struct drm_device
*dev
= dev_priv
->dev
;
3272 /* Come back later if the device is busy... */
3274 if (mutex_trylock(&dev
->struct_mutex
)) {
3275 idle
= i915_gem_retire_requests(dev_priv
);
3276 mutex_unlock(&dev
->struct_mutex
);
3279 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
,
3280 round_jiffies_up_relative(HZ
));
3284 i915_gem_idle_work_handler(struct work_struct
*work
)
3286 struct drm_i915_private
*dev_priv
=
3287 container_of(work
, typeof(*dev_priv
), mm
.idle_work
.work
);
3288 struct drm_device
*dev
= dev_priv
->dev
;
3289 struct intel_engine_cs
*engine
;
3291 for_each_engine(engine
, dev_priv
)
3292 if (!list_empty(&engine
->request_list
))
3295 /* we probably should sync with hangcheck here, using cancel_work_sync.
3296 * Also locking seems to be fubar here, engine->request_list is protected
3297 * by dev->struct_mutex. */
3299 intel_mark_idle(dev_priv
);
3301 if (mutex_trylock(&dev
->struct_mutex
)) {
3302 for_each_engine(engine
, dev_priv
)
3303 i915_gem_batch_pool_fini(&engine
->batch_pool
);
3305 mutex_unlock(&dev
->struct_mutex
);
3310 * Ensures that an object will eventually get non-busy by flushing any required
3311 * write domains, emitting any outstanding lazy request and retiring and
3312 * completed requests.
3313 * @obj: object to flush
3316 i915_gem_object_flush_active(struct drm_i915_gem_object
*obj
)
3323 for (i
= 0; i
< I915_NUM_ENGINES
; i
++) {
3324 struct drm_i915_gem_request
*req
;
3326 req
= obj
->last_read_req
[i
];
3330 if (i915_gem_request_completed(req
, true))
3331 i915_gem_object_retire__read(obj
, i
);
3338 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
3339 * @dev: drm device pointer
3340 * @data: ioctl data blob
3341 * @file: drm file pointer
3343 * Returns 0 if successful, else an error is returned with the remaining time in
3344 * the timeout parameter.
3345 * -ETIME: object is still busy after timeout
3346 * -ERESTARTSYS: signal interrupted the wait
3347 * -ENONENT: object doesn't exist
3348 * Also possible, but rare:
3349 * -EAGAIN: GPU wedged
3351 * -ENODEV: Internal IRQ fail
3352 * -E?: The add request failed
3354 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
3355 * non-zero timeout parameter the wait ioctl will wait for the given number of
3356 * nanoseconds on an object becoming unbusy. Since the wait itself does so
3357 * without holding struct_mutex the object may become re-busied before this
3358 * function completes. A similar but shorter * race condition exists in the busy
3362 i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
, struct drm_file
*file
)
3364 struct drm_i915_gem_wait
*args
= data
;
3365 struct drm_i915_gem_object
*obj
;
3366 struct drm_i915_gem_request
*req
[I915_NUM_ENGINES
];
3370 if (args
->flags
!= 0)
3373 ret
= i915_mutex_lock_interruptible(dev
);
3377 obj
= to_intel_bo(drm_gem_object_lookup(file
, args
->bo_handle
));
3378 if (&obj
->base
== NULL
) {
3379 mutex_unlock(&dev
->struct_mutex
);
3383 /* Need to make sure the object gets inactive eventually. */
3384 ret
= i915_gem_object_flush_active(obj
);
3391 /* Do this after OLR check to make sure we make forward progress polling
3392 * on this IOCTL with a timeout == 0 (like busy ioctl)
3394 if (args
->timeout_ns
== 0) {
3399 drm_gem_object_unreference(&obj
->base
);
3401 for (i
= 0; i
< I915_NUM_ENGINES
; i
++) {
3402 if (obj
->last_read_req
[i
] == NULL
)
3405 req
[n
++] = i915_gem_request_reference(obj
->last_read_req
[i
]);
3408 mutex_unlock(&dev
->struct_mutex
);
3410 for (i
= 0; i
< n
; i
++) {
3412 ret
= __i915_wait_request(req
[i
], true,
3413 args
->timeout_ns
> 0 ? &args
->timeout_ns
: NULL
,
3414 to_rps_client(file
));
3415 i915_gem_request_unreference(req
[i
]);
3420 drm_gem_object_unreference(&obj
->base
);
3421 mutex_unlock(&dev
->struct_mutex
);
3426 __i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
3427 struct intel_engine_cs
*to
,
3428 struct drm_i915_gem_request
*from_req
,
3429 struct drm_i915_gem_request
**to_req
)
3431 struct intel_engine_cs
*from
;
3434 from
= i915_gem_request_get_engine(from_req
);
3438 if (i915_gem_request_completed(from_req
, true))
3441 if (!i915_semaphore_is_enabled(to_i915(obj
->base
.dev
))) {
3442 struct drm_i915_private
*i915
= to_i915(obj
->base
.dev
);
3443 ret
= __i915_wait_request(from_req
,
3444 i915
->mm
.interruptible
,
3446 &i915
->rps
.semaphores
);
3450 i915_gem_object_retire_request(obj
, from_req
);
3452 int idx
= intel_ring_sync_index(from
, to
);
3453 u32 seqno
= i915_gem_request_get_seqno(from_req
);
3457 if (seqno
<= from
->semaphore
.sync_seqno
[idx
])
3460 if (*to_req
== NULL
) {
3461 struct drm_i915_gem_request
*req
;
3463 req
= i915_gem_request_alloc(to
, NULL
);
3465 return PTR_ERR(req
);
3470 trace_i915_gem_ring_sync_to(*to_req
, from
, from_req
);
3471 ret
= to
->semaphore
.sync_to(*to_req
, from
, seqno
);
3475 /* We use last_read_req because sync_to()
3476 * might have just caused seqno wrap under
3479 from
->semaphore
.sync_seqno
[idx
] =
3480 i915_gem_request_get_seqno(obj
->last_read_req
[from
->id
]);
3487 * i915_gem_object_sync - sync an object to a ring.
3489 * @obj: object which may be in use on another ring.
3490 * @to: ring we wish to use the object on. May be NULL.
3491 * @to_req: request we wish to use the object for. See below.
3492 * This will be allocated and returned if a request is
3493 * required but not passed in.
3495 * This code is meant to abstract object synchronization with the GPU.
3496 * Calling with NULL implies synchronizing the object with the CPU
3497 * rather than a particular GPU ring. Conceptually we serialise writes
3498 * between engines inside the GPU. We only allow one engine to write
3499 * into a buffer at any time, but multiple readers. To ensure each has
3500 * a coherent view of memory, we must:
3502 * - If there is an outstanding write request to the object, the new
3503 * request must wait for it to complete (either CPU or in hw, requests
3504 * on the same ring will be naturally ordered).
3506 * - If we are a write request (pending_write_domain is set), the new
3507 * request must wait for outstanding read requests to complete.
3509 * For CPU synchronisation (NULL to) no request is required. For syncing with
3510 * rings to_req must be non-NULL. However, a request does not have to be
3511 * pre-allocated. If *to_req is NULL and sync commands will be emitted then a
3512 * request will be allocated automatically and returned through *to_req. Note
3513 * that it is not guaranteed that commands will be emitted (because the system
3514 * might already be idle). Hence there is no need to create a request that
3515 * might never have any work submitted. Note further that if a request is
3516 * returned in *to_req, it is the responsibility of the caller to submit
3517 * that request (after potentially adding more work to it).
3519 * Returns 0 if successful, else propagates up the lower layer error.
3522 i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
3523 struct intel_engine_cs
*to
,
3524 struct drm_i915_gem_request
**to_req
)
3526 const bool readonly
= obj
->base
.pending_write_domain
== 0;
3527 struct drm_i915_gem_request
*req
[I915_NUM_ENGINES
];
3534 return i915_gem_object_wait_rendering(obj
, readonly
);
3538 if (obj
->last_write_req
)
3539 req
[n
++] = obj
->last_write_req
;
3541 for (i
= 0; i
< I915_NUM_ENGINES
; i
++)
3542 if (obj
->last_read_req
[i
])
3543 req
[n
++] = obj
->last_read_req
[i
];
3545 for (i
= 0; i
< n
; i
++) {
3546 ret
= __i915_gem_object_sync(obj
, to
, req
[i
], to_req
);
3554 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object
*obj
)
3556 u32 old_write_domain
, old_read_domains
;
3558 /* Force a pagefault for domain tracking on next user access */
3559 i915_gem_release_mmap(obj
);
3561 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
) == 0)
3564 old_read_domains
= obj
->base
.read_domains
;
3565 old_write_domain
= obj
->base
.write_domain
;
3567 obj
->base
.read_domains
&= ~I915_GEM_DOMAIN_GTT
;
3568 obj
->base
.write_domain
&= ~I915_GEM_DOMAIN_GTT
;
3570 trace_i915_gem_object_change_domain(obj
,
3575 static void __i915_vma_iounmap(struct i915_vma
*vma
)
3577 GEM_BUG_ON(vma
->pin_count
);
3579 if (vma
->iomap
== NULL
)
3582 io_mapping_unmap(vma
->iomap
);
3586 static int __i915_vma_unbind(struct i915_vma
*vma
, bool wait
)
3588 struct drm_i915_gem_object
*obj
= vma
->obj
;
3589 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
3592 if (list_empty(&vma
->obj_link
))
3595 if (!drm_mm_node_allocated(&vma
->node
)) {
3596 i915_gem_vma_destroy(vma
);
3603 BUG_ON(obj
->pages
== NULL
);
3606 ret
= i915_gem_object_wait_rendering(obj
, false);
3611 if (vma
->is_ggtt
&& vma
->ggtt_view
.type
== I915_GGTT_VIEW_NORMAL
) {
3612 i915_gem_object_finish_gtt(obj
);
3614 /* release the fence reg _after_ flushing */
3615 ret
= i915_gem_object_put_fence(obj
);
3619 __i915_vma_iounmap(vma
);
3622 trace_i915_vma_unbind(vma
);
3624 vma
->vm
->unbind_vma(vma
);
3627 list_del_init(&vma
->vm_link
);
3629 if (vma
->ggtt_view
.type
== I915_GGTT_VIEW_NORMAL
) {
3630 obj
->map_and_fenceable
= false;
3631 } else if (vma
->ggtt_view
.pages
) {
3632 sg_free_table(vma
->ggtt_view
.pages
);
3633 kfree(vma
->ggtt_view
.pages
);
3635 vma
->ggtt_view
.pages
= NULL
;
3638 drm_mm_remove_node(&vma
->node
);
3639 i915_gem_vma_destroy(vma
);
3641 /* Since the unbound list is global, only move to that list if
3642 * no more VMAs exist. */
3643 if (list_empty(&obj
->vma_list
))
3644 list_move_tail(&obj
->global_list
, &dev_priv
->mm
.unbound_list
);
3646 /* And finally now the object is completely decoupled from this vma,
3647 * we can drop its hold on the backing storage and allow it to be
3648 * reaped by the shrinker.
3650 i915_gem_object_unpin_pages(obj
);
3655 int i915_vma_unbind(struct i915_vma
*vma
)
3657 return __i915_vma_unbind(vma
, true);
3660 int __i915_vma_unbind_no_wait(struct i915_vma
*vma
)
3662 return __i915_vma_unbind(vma
, false);
3665 int i915_gpu_idle(struct drm_device
*dev
)
3667 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3668 struct intel_engine_cs
*engine
;
3671 /* Flush everything onto the inactive list. */
3672 for_each_engine(engine
, dev_priv
) {
3673 if (!i915
.enable_execlists
) {
3674 struct drm_i915_gem_request
*req
;
3676 req
= i915_gem_request_alloc(engine
, NULL
);
3678 return PTR_ERR(req
);
3680 ret
= i915_switch_context(req
);
3681 i915_add_request_no_flush(req
);
3686 ret
= intel_engine_idle(engine
);
3691 WARN_ON(i915_verify_lists(dev
));
3695 static bool i915_gem_valid_gtt_space(struct i915_vma
*vma
,
3696 unsigned long cache_level
)
3698 struct drm_mm_node
*gtt_space
= &vma
->node
;
3699 struct drm_mm_node
*other
;
3702 * On some machines we have to be careful when putting differing types
3703 * of snoopable memory together to avoid the prefetcher crossing memory
3704 * domains and dying. During vm initialisation, we decide whether or not
3705 * these constraints apply and set the drm_mm.color_adjust
3708 if (vma
->vm
->mm
.color_adjust
== NULL
)
3711 if (!drm_mm_node_allocated(gtt_space
))
3714 if (list_empty(>t_space
->node_list
))
3717 other
= list_entry(gtt_space
->node_list
.prev
, struct drm_mm_node
, node_list
);
3718 if (other
->allocated
&& !other
->hole_follows
&& other
->color
!= cache_level
)
3721 other
= list_entry(gtt_space
->node_list
.next
, struct drm_mm_node
, node_list
);
3722 if (other
->allocated
&& !gtt_space
->hole_follows
&& other
->color
!= cache_level
)
3729 * Finds free space in the GTT aperture and binds the object or a view of it
3731 * @obj: object to bind
3732 * @vm: address space to bind into
3733 * @ggtt_view: global gtt view if applicable
3734 * @alignment: requested alignment
3735 * @flags: mask of PIN_* flags to use
3737 static struct i915_vma
*
3738 i915_gem_object_bind_to_vm(struct drm_i915_gem_object
*obj
,
3739 struct i915_address_space
*vm
,
3740 const struct i915_ggtt_view
*ggtt_view
,
3744 struct drm_device
*dev
= obj
->base
.dev
;
3745 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3746 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
3747 u32 fence_alignment
, unfenced_alignment
;
3748 u32 search_flag
, alloc_flag
;
3750 u64 size
, fence_size
;
3751 struct i915_vma
*vma
;
3754 if (i915_is_ggtt(vm
)) {
3757 if (WARN_ON(!ggtt_view
))
3758 return ERR_PTR(-EINVAL
);
3760 view_size
= i915_ggtt_view_size(obj
, ggtt_view
);
3762 fence_size
= i915_gem_get_gtt_size(dev
,
3765 fence_alignment
= i915_gem_get_gtt_alignment(dev
,
3769 unfenced_alignment
= i915_gem_get_gtt_alignment(dev
,
3773 size
= flags
& PIN_MAPPABLE
? fence_size
: view_size
;
3775 fence_size
= i915_gem_get_gtt_size(dev
,
3778 fence_alignment
= i915_gem_get_gtt_alignment(dev
,
3782 unfenced_alignment
=
3783 i915_gem_get_gtt_alignment(dev
,
3787 size
= flags
& PIN_MAPPABLE
? fence_size
: obj
->base
.size
;
3790 start
= flags
& PIN_OFFSET_BIAS
? flags
& PIN_OFFSET_MASK
: 0;
3792 if (flags
& PIN_MAPPABLE
)
3793 end
= min_t(u64
, end
, ggtt
->mappable_end
);
3794 if (flags
& PIN_ZONE_4G
)
3795 end
= min_t(u64
, end
, (1ULL << 32) - PAGE_SIZE
);
3798 alignment
= flags
& PIN_MAPPABLE
? fence_alignment
:
3800 if (flags
& PIN_MAPPABLE
&& alignment
& (fence_alignment
- 1)) {
3801 DRM_DEBUG("Invalid object (view type=%u) alignment requested %u\n",
3802 ggtt_view
? ggtt_view
->type
: 0,
3804 return ERR_PTR(-EINVAL
);
3807 /* If binding the object/GGTT view requires more space than the entire
3808 * aperture has, reject it early before evicting everything in a vain
3809 * attempt to find space.
3812 DRM_DEBUG("Attempting to bind an object (view type=%u) larger than the aperture: size=%llu > %s aperture=%llu\n",
3813 ggtt_view
? ggtt_view
->type
: 0,
3815 flags
& PIN_MAPPABLE
? "mappable" : "total",
3817 return ERR_PTR(-E2BIG
);
3820 ret
= i915_gem_object_get_pages(obj
);
3822 return ERR_PTR(ret
);
3824 i915_gem_object_pin_pages(obj
);
3826 vma
= ggtt_view
? i915_gem_obj_lookup_or_create_ggtt_vma(obj
, ggtt_view
) :
3827 i915_gem_obj_lookup_or_create_vma(obj
, vm
);
3832 if (flags
& PIN_OFFSET_FIXED
) {
3833 uint64_t offset
= flags
& PIN_OFFSET_MASK
;
3835 if (offset
& (alignment
- 1) || offset
+ size
> end
) {
3839 vma
->node
.start
= offset
;
3840 vma
->node
.size
= size
;
3841 vma
->node
.color
= obj
->cache_level
;
3842 ret
= drm_mm_reserve_node(&vm
->mm
, &vma
->node
);
3844 ret
= i915_gem_evict_for_vma(vma
);
3846 ret
= drm_mm_reserve_node(&vm
->mm
, &vma
->node
);
3851 if (flags
& PIN_HIGH
) {
3852 search_flag
= DRM_MM_SEARCH_BELOW
;
3853 alloc_flag
= DRM_MM_CREATE_TOP
;
3855 search_flag
= DRM_MM_SEARCH_DEFAULT
;
3856 alloc_flag
= DRM_MM_CREATE_DEFAULT
;
3860 ret
= drm_mm_insert_node_in_range_generic(&vm
->mm
, &vma
->node
,
3867 ret
= i915_gem_evict_something(dev
, vm
, size
, alignment
,
3877 if (WARN_ON(!i915_gem_valid_gtt_space(vma
, obj
->cache_level
))) {
3879 goto err_remove_node
;
3882 trace_i915_vma_bind(vma
, flags
);
3883 ret
= i915_vma_bind(vma
, obj
->cache_level
, flags
);
3885 goto err_remove_node
;
3887 list_move_tail(&obj
->global_list
, &dev_priv
->mm
.bound_list
);
3888 list_add_tail(&vma
->vm_link
, &vm
->inactive_list
);
3893 drm_mm_remove_node(&vma
->node
);
3895 i915_gem_vma_destroy(vma
);
3898 i915_gem_object_unpin_pages(obj
);
3903 i915_gem_clflush_object(struct drm_i915_gem_object
*obj
,
3906 /* If we don't have a page list set up, then we're not pinned
3907 * to GPU, and we can ignore the cache flush because it'll happen
3908 * again at bind time.
3910 if (obj
->pages
== NULL
)
3914 * Stolen memory is always coherent with the GPU as it is explicitly
3915 * marked as wc by the system, or the system is cache-coherent.
3917 if (obj
->stolen
|| obj
->phys_handle
)
3920 /* If the GPU is snooping the contents of the CPU cache,
3921 * we do not need to manually clear the CPU cache lines. However,
3922 * the caches are only snooped when the render cache is
3923 * flushed/invalidated. As we always have to emit invalidations
3924 * and flushes when moving into and out of the RENDER domain, correct
3925 * snooping behaviour occurs naturally as the result of our domain
3928 if (!force
&& cpu_cache_is_coherent(obj
->base
.dev
, obj
->cache_level
)) {
3929 obj
->cache_dirty
= true;
3933 trace_i915_gem_object_clflush(obj
);
3934 drm_clflush_sg(obj
->pages
);
3935 obj
->cache_dirty
= false;
3940 /** Flushes the GTT write domain for the object if it's dirty. */
3942 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
)
3944 uint32_t old_write_domain
;
3946 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_GTT
)
3949 /* No actual flushing is required for the GTT write domain. Writes
3950 * to it immediately go to main memory as far as we know, so there's
3951 * no chipset flush. It also doesn't land in render cache.
3953 * However, we do have to enforce the order so that all writes through
3954 * the GTT land before any writes to the device, such as updates to
3959 old_write_domain
= obj
->base
.write_domain
;
3960 obj
->base
.write_domain
= 0;
3962 intel_fb_obj_flush(obj
, false, ORIGIN_GTT
);
3964 trace_i915_gem_object_change_domain(obj
,
3965 obj
->base
.read_domains
,
3969 /** Flushes the CPU write domain for the object if it's dirty. */
3971 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
)
3973 uint32_t old_write_domain
;
3975 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
)
3978 if (i915_gem_clflush_object(obj
, obj
->pin_display
))
3979 i915_gem_chipset_flush(to_i915(obj
->base
.dev
));
3981 old_write_domain
= obj
->base
.write_domain
;
3982 obj
->base
.write_domain
= 0;
3984 intel_fb_obj_flush(obj
, false, ORIGIN_CPU
);
3986 trace_i915_gem_object_change_domain(obj
,
3987 obj
->base
.read_domains
,
3992 * Moves a single object to the GTT read, and possibly write domain.
3993 * @obj: object to act on
3994 * @write: ask for write access or read only
3996 * This function returns when the move is complete, including waiting on
4000 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
, bool write
)
4002 struct drm_device
*dev
= obj
->base
.dev
;
4003 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4004 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
4005 uint32_t old_write_domain
, old_read_domains
;
4006 struct i915_vma
*vma
;
4009 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_GTT
)
4012 ret
= i915_gem_object_wait_rendering(obj
, !write
);
4016 /* Flush and acquire obj->pages so that we are coherent through
4017 * direct access in memory with previous cached writes through
4018 * shmemfs and that our cache domain tracking remains valid.
4019 * For example, if the obj->filp was moved to swap without us
4020 * being notified and releasing the pages, we would mistakenly
4021 * continue to assume that the obj remained out of the CPU cached
4024 ret
= i915_gem_object_get_pages(obj
);
4028 i915_gem_object_flush_cpu_write_domain(obj
);
4030 /* Serialise direct access to this object with the barriers for
4031 * coherent writes from the GPU, by effectively invalidating the
4032 * GTT domain upon first access.
4034 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
) == 0)
4037 old_write_domain
= obj
->base
.write_domain
;
4038 old_read_domains
= obj
->base
.read_domains
;
4040 /* It should now be out of any other write domains, and we can update
4041 * the domain values for our changes.
4043 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
4044 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
4046 obj
->base
.read_domains
= I915_GEM_DOMAIN_GTT
;
4047 obj
->base
.write_domain
= I915_GEM_DOMAIN_GTT
;
4051 trace_i915_gem_object_change_domain(obj
,
4055 /* And bump the LRU for this access */
4056 vma
= i915_gem_obj_to_ggtt(obj
);
4057 if (vma
&& drm_mm_node_allocated(&vma
->node
) && !obj
->active
)
4058 list_move_tail(&vma
->vm_link
,
4059 &ggtt
->base
.inactive_list
);
4065 * Changes the cache-level of an object across all VMA.
4066 * @obj: object to act on
4067 * @cache_level: new cache level to set for the object
4069 * After this function returns, the object will be in the new cache-level
4070 * across all GTT and the contents of the backing storage will be coherent,
4071 * with respect to the new cache-level. In order to keep the backing storage
4072 * coherent for all users, we only allow a single cache level to be set
4073 * globally on the object and prevent it from being changed whilst the
4074 * hardware is reading from the object. That is if the object is currently
4075 * on the scanout it will be set to uncached (or equivalent display
4076 * cache coherency) and all non-MOCS GPU access will also be uncached so
4077 * that all direct access to the scanout remains coherent.
4079 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
4080 enum i915_cache_level cache_level
)
4082 struct drm_device
*dev
= obj
->base
.dev
;
4083 struct i915_vma
*vma
, *next
;
4087 if (obj
->cache_level
== cache_level
)
4090 /* Inspect the list of currently bound VMA and unbind any that would
4091 * be invalid given the new cache-level. This is principally to
4092 * catch the issue of the CS prefetch crossing page boundaries and
4093 * reading an invalid PTE on older architectures.
4095 list_for_each_entry_safe(vma
, next
, &obj
->vma_list
, obj_link
) {
4096 if (!drm_mm_node_allocated(&vma
->node
))
4099 if (vma
->pin_count
) {
4100 DRM_DEBUG("can not change the cache level of pinned objects\n");
4104 if (!i915_gem_valid_gtt_space(vma
, cache_level
)) {
4105 ret
= i915_vma_unbind(vma
);
4112 /* We can reuse the existing drm_mm nodes but need to change the
4113 * cache-level on the PTE. We could simply unbind them all and
4114 * rebind with the correct cache-level on next use. However since
4115 * we already have a valid slot, dma mapping, pages etc, we may as
4116 * rewrite the PTE in the belief that doing so tramples upon less
4117 * state and so involves less work.
4120 /* Before we change the PTE, the GPU must not be accessing it.
4121 * If we wait upon the object, we know that all the bound
4122 * VMA are no longer active.
4124 ret
= i915_gem_object_wait_rendering(obj
, false);
4128 if (!HAS_LLC(dev
) && cache_level
!= I915_CACHE_NONE
) {
4129 /* Access to snoopable pages through the GTT is
4130 * incoherent and on some machines causes a hard
4131 * lockup. Relinquish the CPU mmaping to force
4132 * userspace to refault in the pages and we can
4133 * then double check if the GTT mapping is still
4134 * valid for that pointer access.
4136 i915_gem_release_mmap(obj
);
4138 /* As we no longer need a fence for GTT access,
4139 * we can relinquish it now (and so prevent having
4140 * to steal a fence from someone else on the next
4141 * fence request). Note GPU activity would have
4142 * dropped the fence as all snoopable access is
4143 * supposed to be linear.
4145 ret
= i915_gem_object_put_fence(obj
);
4149 /* We either have incoherent backing store and
4150 * so no GTT access or the architecture is fully
4151 * coherent. In such cases, existing GTT mmaps
4152 * ignore the cache bit in the PTE and we can
4153 * rewrite it without confusing the GPU or having
4154 * to force userspace to fault back in its mmaps.
4158 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
) {
4159 if (!drm_mm_node_allocated(&vma
->node
))
4162 ret
= i915_vma_bind(vma
, cache_level
, PIN_UPDATE
);
4168 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
)
4169 vma
->node
.color
= cache_level
;
4170 obj
->cache_level
= cache_level
;
4173 /* Flush the dirty CPU caches to the backing storage so that the
4174 * object is now coherent at its new cache level (with respect
4175 * to the access domain).
4177 if (obj
->cache_dirty
&& cpu_write_needs_clflush(obj
)) {
4178 if (i915_gem_clflush_object(obj
, true))
4179 i915_gem_chipset_flush(to_i915(obj
->base
.dev
));
4185 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
4186 struct drm_file
*file
)
4188 struct drm_i915_gem_caching
*args
= data
;
4189 struct drm_i915_gem_object
*obj
;
4191 obj
= to_intel_bo(drm_gem_object_lookup(file
, args
->handle
));
4192 if (&obj
->base
== NULL
)
4195 switch (obj
->cache_level
) {
4196 case I915_CACHE_LLC
:
4197 case I915_CACHE_L3_LLC
:
4198 args
->caching
= I915_CACHING_CACHED
;
4202 args
->caching
= I915_CACHING_DISPLAY
;
4206 args
->caching
= I915_CACHING_NONE
;
4210 drm_gem_object_unreference_unlocked(&obj
->base
);
4214 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
4215 struct drm_file
*file
)
4217 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4218 struct drm_i915_gem_caching
*args
= data
;
4219 struct drm_i915_gem_object
*obj
;
4220 enum i915_cache_level level
;
4223 switch (args
->caching
) {
4224 case I915_CACHING_NONE
:
4225 level
= I915_CACHE_NONE
;
4227 case I915_CACHING_CACHED
:
4229 * Due to a HW issue on BXT A stepping, GPU stores via a
4230 * snooped mapping may leave stale data in a corresponding CPU
4231 * cacheline, whereas normally such cachelines would get
4234 if (!HAS_LLC(dev
) && !HAS_SNOOP(dev
))
4237 level
= I915_CACHE_LLC
;
4239 case I915_CACHING_DISPLAY
:
4240 level
= HAS_WT(dev
) ? I915_CACHE_WT
: I915_CACHE_NONE
;
4246 intel_runtime_pm_get(dev_priv
);
4248 ret
= i915_mutex_lock_interruptible(dev
);
4252 obj
= to_intel_bo(drm_gem_object_lookup(file
, args
->handle
));
4253 if (&obj
->base
== NULL
) {
4258 ret
= i915_gem_object_set_cache_level(obj
, level
);
4260 drm_gem_object_unreference(&obj
->base
);
4262 mutex_unlock(&dev
->struct_mutex
);
4264 intel_runtime_pm_put(dev_priv
);
4270 * Prepare buffer for display plane (scanout, cursors, etc).
4271 * Can be called from an uninterruptible phase (modesetting) and allows
4272 * any flushes to be pipelined (for pageflips).
4275 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
4277 const struct i915_ggtt_view
*view
)
4279 u32 old_read_domains
, old_write_domain
;
4282 /* Mark the pin_display early so that we account for the
4283 * display coherency whilst setting up the cache domains.
4287 /* The display engine is not coherent with the LLC cache on gen6. As
4288 * a result, we make sure that the pinning that is about to occur is
4289 * done with uncached PTEs. This is lowest common denominator for all
4292 * However for gen6+, we could do better by using the GFDT bit instead
4293 * of uncaching, which would allow us to flush all the LLC-cached data
4294 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
4296 ret
= i915_gem_object_set_cache_level(obj
,
4297 HAS_WT(obj
->base
.dev
) ? I915_CACHE_WT
: I915_CACHE_NONE
);
4299 goto err_unpin_display
;
4301 /* As the user may map the buffer once pinned in the display plane
4302 * (e.g. libkms for the bootup splash), we have to ensure that we
4303 * always use map_and_fenceable for all scanout buffers.
4305 ret
= i915_gem_object_ggtt_pin(obj
, view
, alignment
,
4306 view
->type
== I915_GGTT_VIEW_NORMAL
?
4309 goto err_unpin_display
;
4311 i915_gem_object_flush_cpu_write_domain(obj
);
4313 old_write_domain
= obj
->base
.write_domain
;
4314 old_read_domains
= obj
->base
.read_domains
;
4316 /* It should now be out of any other write domains, and we can update
4317 * the domain values for our changes.
4319 obj
->base
.write_domain
= 0;
4320 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
4322 trace_i915_gem_object_change_domain(obj
,
4334 i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object
*obj
,
4335 const struct i915_ggtt_view
*view
)
4337 if (WARN_ON(obj
->pin_display
== 0))
4340 i915_gem_object_ggtt_unpin_view(obj
, view
);
4346 * Moves a single object to the CPU read, and possibly write domain.
4347 * @obj: object to act on
4348 * @write: requesting write or read-only access
4350 * This function returns when the move is complete, including waiting on
4354 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
)
4356 uint32_t old_write_domain
, old_read_domains
;
4359 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_CPU
)
4362 ret
= i915_gem_object_wait_rendering(obj
, !write
);
4366 i915_gem_object_flush_gtt_write_domain(obj
);
4368 old_write_domain
= obj
->base
.write_domain
;
4369 old_read_domains
= obj
->base
.read_domains
;
4371 /* Flush the CPU cache if it's still invalid. */
4372 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) == 0) {
4373 i915_gem_clflush_object(obj
, false);
4375 obj
->base
.read_domains
|= I915_GEM_DOMAIN_CPU
;
4378 /* It should now be out of any other write domains, and we can update
4379 * the domain values for our changes.
4381 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
4383 /* If we're writing through the CPU, then the GPU read domains will
4384 * need to be invalidated at next use.
4387 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
4388 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
4391 trace_i915_gem_object_change_domain(obj
,
4398 /* Throttle our rendering by waiting until the ring has completed our requests
4399 * emitted over 20 msec ago.
4401 * Note that if we were to use the current jiffies each time around the loop,
4402 * we wouldn't escape the function with any frames outstanding if the time to
4403 * render a frame was over 20ms.
4405 * This should get us reasonable parallelism between CPU and GPU but also
4406 * relatively low latency when blocking on a particular request to finish.
4409 i915_gem_ring_throttle(struct drm_device
*dev
, struct drm_file
*file
)
4411 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4412 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
4413 unsigned long recent_enough
= jiffies
- DRM_I915_THROTTLE_JIFFIES
;
4414 struct drm_i915_gem_request
*request
, *target
= NULL
;
4417 ret
= i915_gem_wait_for_error(&dev_priv
->gpu_error
);
4421 /* ABI: return -EIO if already wedged */
4422 if (i915_terminally_wedged(&dev_priv
->gpu_error
))
4425 spin_lock(&file_priv
->mm
.lock
);
4426 list_for_each_entry(request
, &file_priv
->mm
.request_list
, client_list
) {
4427 if (time_after_eq(request
->emitted_jiffies
, recent_enough
))
4431 * Note that the request might not have been submitted yet.
4432 * In which case emitted_jiffies will be zero.
4434 if (!request
->emitted_jiffies
)
4440 i915_gem_request_reference(target
);
4441 spin_unlock(&file_priv
->mm
.lock
);
4446 ret
= __i915_wait_request(target
, true, NULL
, NULL
);
4448 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, 0);
4450 i915_gem_request_unreference(target
);
4456 i915_vma_misplaced(struct i915_vma
*vma
, uint32_t alignment
, uint64_t flags
)
4458 struct drm_i915_gem_object
*obj
= vma
->obj
;
4461 vma
->node
.start
& (alignment
- 1))
4464 if (flags
& PIN_MAPPABLE
&& !obj
->map_and_fenceable
)
4467 if (flags
& PIN_OFFSET_BIAS
&&
4468 vma
->node
.start
< (flags
& PIN_OFFSET_MASK
))
4471 if (flags
& PIN_OFFSET_FIXED
&&
4472 vma
->node
.start
!= (flags
& PIN_OFFSET_MASK
))
4478 void __i915_vma_set_map_and_fenceable(struct i915_vma
*vma
)
4480 struct drm_i915_gem_object
*obj
= vma
->obj
;
4481 bool mappable
, fenceable
;
4482 u32 fence_size
, fence_alignment
;
4484 fence_size
= i915_gem_get_gtt_size(obj
->base
.dev
,
4487 fence_alignment
= i915_gem_get_gtt_alignment(obj
->base
.dev
,
4492 fenceable
= (vma
->node
.size
== fence_size
&&
4493 (vma
->node
.start
& (fence_alignment
- 1)) == 0);
4495 mappable
= (vma
->node
.start
+ fence_size
<=
4496 to_i915(obj
->base
.dev
)->ggtt
.mappable_end
);
4498 obj
->map_and_fenceable
= mappable
&& fenceable
;
4502 i915_gem_object_do_pin(struct drm_i915_gem_object
*obj
,
4503 struct i915_address_space
*vm
,
4504 const struct i915_ggtt_view
*ggtt_view
,
4508 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
4509 struct i915_vma
*vma
;
4513 if (WARN_ON(vm
== &dev_priv
->mm
.aliasing_ppgtt
->base
))
4516 if (WARN_ON(flags
& (PIN_GLOBAL
| PIN_MAPPABLE
) && !i915_is_ggtt(vm
)))
4519 if (WARN_ON((flags
& (PIN_MAPPABLE
| PIN_GLOBAL
)) == PIN_MAPPABLE
))
4522 if (WARN_ON(i915_is_ggtt(vm
) != !!ggtt_view
))
4525 vma
= ggtt_view
? i915_gem_obj_to_ggtt_view(obj
, ggtt_view
) :
4526 i915_gem_obj_to_vma(obj
, vm
);
4529 if (WARN_ON(vma
->pin_count
== DRM_I915_GEM_OBJECT_MAX_PIN_COUNT
))
4532 if (i915_vma_misplaced(vma
, alignment
, flags
)) {
4533 WARN(vma
->pin_count
,
4534 "bo is already pinned in %s with incorrect alignment:"
4535 " offset=%08x %08x, req.alignment=%x, req.map_and_fenceable=%d,"
4536 " obj->map_and_fenceable=%d\n",
4537 ggtt_view
? "ggtt" : "ppgtt",
4538 upper_32_bits(vma
->node
.start
),
4539 lower_32_bits(vma
->node
.start
),
4541 !!(flags
& PIN_MAPPABLE
),
4542 obj
->map_and_fenceable
);
4543 ret
= i915_vma_unbind(vma
);
4551 bound
= vma
? vma
->bound
: 0;
4552 if (vma
== NULL
|| !drm_mm_node_allocated(&vma
->node
)) {
4553 vma
= i915_gem_object_bind_to_vm(obj
, vm
, ggtt_view
, alignment
,
4556 return PTR_ERR(vma
);
4558 ret
= i915_vma_bind(vma
, obj
->cache_level
, flags
);
4563 if (ggtt_view
&& ggtt_view
->type
== I915_GGTT_VIEW_NORMAL
&&
4564 (bound
^ vma
->bound
) & GLOBAL_BIND
) {
4565 __i915_vma_set_map_and_fenceable(vma
);
4566 WARN_ON(flags
& PIN_MAPPABLE
&& !obj
->map_and_fenceable
);
4574 i915_gem_object_pin(struct drm_i915_gem_object
*obj
,
4575 struct i915_address_space
*vm
,
4579 return i915_gem_object_do_pin(obj
, vm
,
4580 i915_is_ggtt(vm
) ? &i915_ggtt_view_normal
: NULL
,
4585 i915_gem_object_ggtt_pin(struct drm_i915_gem_object
*obj
,
4586 const struct i915_ggtt_view
*view
,
4590 struct drm_device
*dev
= obj
->base
.dev
;
4591 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4592 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
4596 return i915_gem_object_do_pin(obj
, &ggtt
->base
, view
,
4597 alignment
, flags
| PIN_GLOBAL
);
4601 i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object
*obj
,
4602 const struct i915_ggtt_view
*view
)
4604 struct i915_vma
*vma
= i915_gem_obj_to_ggtt_view(obj
, view
);
4606 WARN_ON(vma
->pin_count
== 0);
4607 WARN_ON(!i915_gem_obj_ggtt_bound_view(obj
, view
));
4613 i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
4614 struct drm_file
*file
)
4616 struct drm_i915_gem_busy
*args
= data
;
4617 struct drm_i915_gem_object
*obj
;
4620 ret
= i915_mutex_lock_interruptible(dev
);
4624 obj
= to_intel_bo(drm_gem_object_lookup(file
, args
->handle
));
4625 if (&obj
->base
== NULL
) {
4630 /* Count all active objects as busy, even if they are currently not used
4631 * by the gpu. Users of this interface expect objects to eventually
4632 * become non-busy without any further actions, therefore emit any
4633 * necessary flushes here.
4635 ret
= i915_gem_object_flush_active(obj
);
4643 for (i
= 0; i
< I915_NUM_ENGINES
; i
++) {
4644 struct drm_i915_gem_request
*req
;
4646 req
= obj
->last_read_req
[i
];
4648 args
->busy
|= 1 << (16 + req
->engine
->exec_id
);
4650 if (obj
->last_write_req
)
4651 args
->busy
|= obj
->last_write_req
->engine
->exec_id
;
4655 drm_gem_object_unreference(&obj
->base
);
4657 mutex_unlock(&dev
->struct_mutex
);
4662 i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
4663 struct drm_file
*file_priv
)
4665 return i915_gem_ring_throttle(dev
, file_priv
);
4669 i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
4670 struct drm_file
*file_priv
)
4672 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4673 struct drm_i915_gem_madvise
*args
= data
;
4674 struct drm_i915_gem_object
*obj
;
4677 switch (args
->madv
) {
4678 case I915_MADV_DONTNEED
:
4679 case I915_MADV_WILLNEED
:
4685 ret
= i915_mutex_lock_interruptible(dev
);
4689 obj
= to_intel_bo(drm_gem_object_lookup(file_priv
, args
->handle
));
4690 if (&obj
->base
== NULL
) {
4695 if (i915_gem_obj_is_pinned(obj
)) {
4701 obj
->tiling_mode
!= I915_TILING_NONE
&&
4702 dev_priv
->quirks
& QUIRK_PIN_SWIZZLED_PAGES
) {
4703 if (obj
->madv
== I915_MADV_WILLNEED
)
4704 i915_gem_object_unpin_pages(obj
);
4705 if (args
->madv
== I915_MADV_WILLNEED
)
4706 i915_gem_object_pin_pages(obj
);
4709 if (obj
->madv
!= __I915_MADV_PURGED
)
4710 obj
->madv
= args
->madv
;
4712 /* if the object is no longer attached, discard its backing storage */
4713 if (obj
->madv
== I915_MADV_DONTNEED
&& obj
->pages
== NULL
)
4714 i915_gem_object_truncate(obj
);
4716 args
->retained
= obj
->madv
!= __I915_MADV_PURGED
;
4719 drm_gem_object_unreference(&obj
->base
);
4721 mutex_unlock(&dev
->struct_mutex
);
4725 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
4726 const struct drm_i915_gem_object_ops
*ops
)
4730 INIT_LIST_HEAD(&obj
->global_list
);
4731 for (i
= 0; i
< I915_NUM_ENGINES
; i
++)
4732 INIT_LIST_HEAD(&obj
->engine_list
[i
]);
4733 INIT_LIST_HEAD(&obj
->obj_exec_link
);
4734 INIT_LIST_HEAD(&obj
->vma_list
);
4735 INIT_LIST_HEAD(&obj
->batch_pool_link
);
4739 obj
->fence_reg
= I915_FENCE_REG_NONE
;
4740 obj
->madv
= I915_MADV_WILLNEED
;
4742 i915_gem_info_add_obj(obj
->base
.dev
->dev_private
, obj
->base
.size
);
4745 static const struct drm_i915_gem_object_ops i915_gem_object_ops
= {
4746 .flags
= I915_GEM_OBJECT_HAS_STRUCT_PAGE
,
4747 .get_pages
= i915_gem_object_get_pages_gtt
,
4748 .put_pages
= i915_gem_object_put_pages_gtt
,
4751 struct drm_i915_gem_object
*i915_gem_object_create(struct drm_device
*dev
,
4754 struct drm_i915_gem_object
*obj
;
4755 struct address_space
*mapping
;
4759 obj
= i915_gem_object_alloc(dev
);
4761 return ERR_PTR(-ENOMEM
);
4763 ret
= drm_gem_object_init(dev
, &obj
->base
, size
);
4767 mask
= GFP_HIGHUSER
| __GFP_RECLAIMABLE
;
4768 if (IS_CRESTLINE(dev
) || IS_BROADWATER(dev
)) {
4769 /* 965gm cannot relocate objects above 4GiB. */
4770 mask
&= ~__GFP_HIGHMEM
;
4771 mask
|= __GFP_DMA32
;
4774 mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
4775 mapping_set_gfp_mask(mapping
, mask
);
4777 i915_gem_object_init(obj
, &i915_gem_object_ops
);
4779 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
4780 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
4783 /* On some devices, we can have the GPU use the LLC (the CPU
4784 * cache) for about a 10% performance improvement
4785 * compared to uncached. Graphics requests other than
4786 * display scanout are coherent with the CPU in
4787 * accessing this cache. This means in this mode we
4788 * don't need to clflush on the CPU side, and on the
4789 * GPU side we only need to flush internal caches to
4790 * get data visible to the CPU.
4792 * However, we maintain the display planes as UC, and so
4793 * need to rebind when first used as such.
4795 obj
->cache_level
= I915_CACHE_LLC
;
4797 obj
->cache_level
= I915_CACHE_NONE
;
4799 trace_i915_gem_object_create(obj
);
4804 i915_gem_object_free(obj
);
4806 return ERR_PTR(ret
);
4809 static bool discard_backing_storage(struct drm_i915_gem_object
*obj
)
4811 /* If we are the last user of the backing storage (be it shmemfs
4812 * pages or stolen etc), we know that the pages are going to be
4813 * immediately released. In this case, we can then skip copying
4814 * back the contents from the GPU.
4817 if (obj
->madv
!= I915_MADV_WILLNEED
)
4820 if (obj
->base
.filp
== NULL
)
4823 /* At first glance, this looks racy, but then again so would be
4824 * userspace racing mmap against close. However, the first external
4825 * reference to the filp can only be obtained through the
4826 * i915_gem_mmap_ioctl() which safeguards us against the user
4827 * acquiring such a reference whilst we are in the middle of
4828 * freeing the object.
4830 return atomic_long_read(&obj
->base
.filp
->f_count
) == 1;
4833 void i915_gem_free_object(struct drm_gem_object
*gem_obj
)
4835 struct drm_i915_gem_object
*obj
= to_intel_bo(gem_obj
);
4836 struct drm_device
*dev
= obj
->base
.dev
;
4837 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4838 struct i915_vma
*vma
, *next
;
4840 intel_runtime_pm_get(dev_priv
);
4842 trace_i915_gem_object_destroy(obj
);
4844 list_for_each_entry_safe(vma
, next
, &obj
->vma_list
, obj_link
) {
4848 ret
= i915_vma_unbind(vma
);
4849 if (WARN_ON(ret
== -ERESTARTSYS
)) {
4850 bool was_interruptible
;
4852 was_interruptible
= dev_priv
->mm
.interruptible
;
4853 dev_priv
->mm
.interruptible
= false;
4855 WARN_ON(i915_vma_unbind(vma
));
4857 dev_priv
->mm
.interruptible
= was_interruptible
;
4861 /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
4862 * before progressing. */
4864 i915_gem_object_unpin_pages(obj
);
4866 WARN_ON(obj
->frontbuffer_bits
);
4868 if (obj
->pages
&& obj
->madv
== I915_MADV_WILLNEED
&&
4869 dev_priv
->quirks
& QUIRK_PIN_SWIZZLED_PAGES
&&
4870 obj
->tiling_mode
!= I915_TILING_NONE
)
4871 i915_gem_object_unpin_pages(obj
);
4873 if (WARN_ON(obj
->pages_pin_count
))
4874 obj
->pages_pin_count
= 0;
4875 if (discard_backing_storage(obj
))
4876 obj
->madv
= I915_MADV_DONTNEED
;
4877 i915_gem_object_put_pages(obj
);
4878 i915_gem_object_free_mmap_offset(obj
);
4882 if (obj
->base
.import_attach
)
4883 drm_prime_gem_destroy(&obj
->base
, NULL
);
4885 if (obj
->ops
->release
)
4886 obj
->ops
->release(obj
);
4888 drm_gem_object_release(&obj
->base
);
4889 i915_gem_info_remove_obj(dev_priv
, obj
->base
.size
);
4892 i915_gem_object_free(obj
);
4894 intel_runtime_pm_put(dev_priv
);
4897 struct i915_vma
*i915_gem_obj_to_vma(struct drm_i915_gem_object
*obj
,
4898 struct i915_address_space
*vm
)
4900 struct i915_vma
*vma
;
4901 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
) {
4902 if (vma
->ggtt_view
.type
== I915_GGTT_VIEW_NORMAL
&&
4909 struct i915_vma
*i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object
*obj
,
4910 const struct i915_ggtt_view
*view
)
4912 struct i915_vma
*vma
;
4916 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
)
4917 if (vma
->is_ggtt
&& i915_ggtt_view_equal(&vma
->ggtt_view
, view
))
4922 void i915_gem_vma_destroy(struct i915_vma
*vma
)
4924 WARN_ON(vma
->node
.allocated
);
4926 /* Keep the vma as a placeholder in the execbuffer reservation lists */
4927 if (!list_empty(&vma
->exec_list
))
4931 i915_ppgtt_put(i915_vm_to_ppgtt(vma
->vm
));
4933 list_del(&vma
->obj_link
);
4935 kmem_cache_free(to_i915(vma
->obj
->base
.dev
)->vmas
, vma
);
4939 i915_gem_stop_engines(struct drm_device
*dev
)
4941 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4942 struct intel_engine_cs
*engine
;
4944 for_each_engine(engine
, dev_priv
)
4945 dev_priv
->gt
.stop_engine(engine
);
4949 i915_gem_suspend(struct drm_device
*dev
)
4951 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4954 mutex_lock(&dev
->struct_mutex
);
4955 ret
= i915_gpu_idle(dev
);
4959 i915_gem_retire_requests(dev_priv
);
4961 i915_gem_stop_engines(dev
);
4962 i915_gem_context_lost(dev_priv
);
4963 mutex_unlock(&dev
->struct_mutex
);
4965 cancel_delayed_work_sync(&dev_priv
->gpu_error
.hangcheck_work
);
4966 cancel_delayed_work_sync(&dev_priv
->mm
.retire_work
);
4967 flush_delayed_work(&dev_priv
->mm
.idle_work
);
4969 /* Assert that we sucessfully flushed all the work and
4970 * reset the GPU back to its idle, low power state.
4972 WARN_ON(dev_priv
->mm
.busy
);
4977 mutex_unlock(&dev
->struct_mutex
);
4981 void i915_gem_init_swizzling(struct drm_device
*dev
)
4983 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4985 if (INTEL_INFO(dev
)->gen
< 5 ||
4986 dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_NONE
)
4989 I915_WRITE(DISP_ARB_CTL
, I915_READ(DISP_ARB_CTL
) |
4990 DISP_TILE_SURFACE_SWIZZLING
);
4995 I915_WRITE(TILECTL
, I915_READ(TILECTL
) | TILECTL_SWZCTL
);
4997 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB
));
4998 else if (IS_GEN7(dev
))
4999 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB
));
5000 else if (IS_GEN8(dev
))
5001 I915_WRITE(GAMTARBMODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW
));
5006 static void init_unused_ring(struct drm_device
*dev
, u32 base
)
5008 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5010 I915_WRITE(RING_CTL(base
), 0);
5011 I915_WRITE(RING_HEAD(base
), 0);
5012 I915_WRITE(RING_TAIL(base
), 0);
5013 I915_WRITE(RING_START(base
), 0);
5016 static void init_unused_rings(struct drm_device
*dev
)
5019 init_unused_ring(dev
, PRB1_BASE
);
5020 init_unused_ring(dev
, SRB0_BASE
);
5021 init_unused_ring(dev
, SRB1_BASE
);
5022 init_unused_ring(dev
, SRB2_BASE
);
5023 init_unused_ring(dev
, SRB3_BASE
);
5024 } else if (IS_GEN2(dev
)) {
5025 init_unused_ring(dev
, SRB0_BASE
);
5026 init_unused_ring(dev
, SRB1_BASE
);
5027 } else if (IS_GEN3(dev
)) {
5028 init_unused_ring(dev
, PRB1_BASE
);
5029 init_unused_ring(dev
, PRB2_BASE
);
5033 int i915_gem_init_engines(struct drm_device
*dev
)
5035 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5038 ret
= intel_init_render_ring_buffer(dev
);
5043 ret
= intel_init_bsd_ring_buffer(dev
);
5045 goto cleanup_render_ring
;
5049 ret
= intel_init_blt_ring_buffer(dev
);
5051 goto cleanup_bsd_ring
;
5054 if (HAS_VEBOX(dev
)) {
5055 ret
= intel_init_vebox_ring_buffer(dev
);
5057 goto cleanup_blt_ring
;
5060 if (HAS_BSD2(dev
)) {
5061 ret
= intel_init_bsd2_ring_buffer(dev
);
5063 goto cleanup_vebox_ring
;
5069 intel_cleanup_engine(&dev_priv
->engine
[VECS
]);
5071 intel_cleanup_engine(&dev_priv
->engine
[BCS
]);
5073 intel_cleanup_engine(&dev_priv
->engine
[VCS
]);
5074 cleanup_render_ring
:
5075 intel_cleanup_engine(&dev_priv
->engine
[RCS
]);
5081 i915_gem_init_hw(struct drm_device
*dev
)
5083 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5084 struct intel_engine_cs
*engine
;
5087 /* Double layer security blanket, see i915_gem_init() */
5088 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
5090 if (HAS_EDRAM(dev
) && INTEL_GEN(dev_priv
) < 9)
5091 I915_WRITE(HSW_IDICR
, I915_READ(HSW_IDICR
) | IDIHASHMSK(0xf));
5093 if (IS_HASWELL(dev
))
5094 I915_WRITE(MI_PREDICATE_RESULT_2
, IS_HSW_GT3(dev
) ?
5095 LOWER_SLICE_ENABLED
: LOWER_SLICE_DISABLED
);
5097 if (HAS_PCH_NOP(dev
)) {
5098 if (IS_IVYBRIDGE(dev
)) {
5099 u32 temp
= I915_READ(GEN7_MSG_CTL
);
5100 temp
&= ~(WAIT_FOR_PCH_FLR_ACK
| WAIT_FOR_PCH_RESET_ACK
);
5101 I915_WRITE(GEN7_MSG_CTL
, temp
);
5102 } else if (INTEL_INFO(dev
)->gen
>= 7) {
5103 u32 temp
= I915_READ(HSW_NDE_RSTWRN_OPT
);
5104 temp
&= ~RESET_PCH_HANDSHAKE_ENABLE
;
5105 I915_WRITE(HSW_NDE_RSTWRN_OPT
, temp
);
5109 i915_gem_init_swizzling(dev
);
5112 * At least 830 can leave some of the unused rings
5113 * "active" (ie. head != tail) after resume which
5114 * will prevent c3 entry. Makes sure all unused rings
5117 init_unused_rings(dev
);
5119 BUG_ON(!dev_priv
->kernel_context
);
5121 ret
= i915_ppgtt_init_hw(dev
);
5123 DRM_ERROR("PPGTT enable HW failed %d\n", ret
);
5127 /* Need to do basic initialisation of all rings first: */
5128 for_each_engine(engine
, dev_priv
) {
5129 ret
= engine
->init_hw(engine
);
5134 intel_mocs_init_l3cc_table(dev
);
5136 /* We can't enable contexts until all firmware is loaded */
5137 ret
= intel_guc_setup(dev
);
5142 * Increment the next seqno by 0x100 so we have a visible break
5143 * on re-initialisation
5145 ret
= i915_gem_set_seqno(dev
, dev_priv
->next_seqno
+0x100);
5148 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
5152 int i915_gem_init(struct drm_device
*dev
)
5154 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5157 mutex_lock(&dev
->struct_mutex
);
5159 if (!i915
.enable_execlists
) {
5160 dev_priv
->gt
.execbuf_submit
= i915_gem_ringbuffer_submission
;
5161 dev_priv
->gt
.init_engines
= i915_gem_init_engines
;
5162 dev_priv
->gt
.cleanup_engine
= intel_cleanup_engine
;
5163 dev_priv
->gt
.stop_engine
= intel_stop_engine
;
5165 dev_priv
->gt
.execbuf_submit
= intel_execlists_submission
;
5166 dev_priv
->gt
.init_engines
= intel_logical_rings_init
;
5167 dev_priv
->gt
.cleanup_engine
= intel_logical_ring_cleanup
;
5168 dev_priv
->gt
.stop_engine
= intel_logical_ring_stop
;
5171 /* This is just a security blanket to placate dragons.
5172 * On some systems, we very sporadically observe that the first TLBs
5173 * used by the CS may be stale, despite us poking the TLB reset. If
5174 * we hold the forcewake during initialisation these problems
5175 * just magically go away.
5177 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
5179 i915_gem_init_userptr(dev_priv
);
5180 i915_gem_init_ggtt(dev
);
5182 ret
= i915_gem_context_init(dev
);
5186 ret
= dev_priv
->gt
.init_engines(dev
);
5190 ret
= i915_gem_init_hw(dev
);
5192 /* Allow ring initialisation to fail by marking the GPU as
5193 * wedged. But we only want to do this where the GPU is angry,
5194 * for all other failure, such as an allocation failure, bail.
5196 DRM_ERROR("Failed to initialize GPU, declaring it wedged\n");
5197 atomic_or(I915_WEDGED
, &dev_priv
->gpu_error
.reset_counter
);
5202 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
5203 mutex_unlock(&dev
->struct_mutex
);
5209 i915_gem_cleanup_engines(struct drm_device
*dev
)
5211 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5212 struct intel_engine_cs
*engine
;
5214 for_each_engine(engine
, dev_priv
)
5215 dev_priv
->gt
.cleanup_engine(engine
);
5219 init_engine_lists(struct intel_engine_cs
*engine
)
5221 INIT_LIST_HEAD(&engine
->active_list
);
5222 INIT_LIST_HEAD(&engine
->request_list
);
5226 i915_gem_load_init_fences(struct drm_i915_private
*dev_priv
)
5228 struct drm_device
*dev
= dev_priv
->dev
;
5230 if (INTEL_INFO(dev_priv
)->gen
>= 7 && !IS_VALLEYVIEW(dev_priv
) &&
5231 !IS_CHERRYVIEW(dev_priv
))
5232 dev_priv
->num_fence_regs
= 32;
5233 else if (INTEL_INFO(dev_priv
)->gen
>= 4 || IS_I945G(dev_priv
) ||
5234 IS_I945GM(dev_priv
) || IS_G33(dev_priv
))
5235 dev_priv
->num_fence_regs
= 16;
5237 dev_priv
->num_fence_regs
= 8;
5239 if (intel_vgpu_active(dev_priv
))
5240 dev_priv
->num_fence_regs
=
5241 I915_READ(vgtif_reg(avail_rs
.fence_num
));
5243 /* Initialize fence registers to zero */
5244 i915_gem_restore_fences(dev
);
5246 i915_gem_detect_bit_6_swizzle(dev
);
5250 i915_gem_load_init(struct drm_device
*dev
)
5252 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5256 kmem_cache_create("i915_gem_object",
5257 sizeof(struct drm_i915_gem_object
), 0,
5261 kmem_cache_create("i915_gem_vma",
5262 sizeof(struct i915_vma
), 0,
5265 dev_priv
->requests
=
5266 kmem_cache_create("i915_gem_request",
5267 sizeof(struct drm_i915_gem_request
), 0,
5271 INIT_LIST_HEAD(&dev_priv
->vm_list
);
5272 INIT_LIST_HEAD(&dev_priv
->context_list
);
5273 INIT_LIST_HEAD(&dev_priv
->mm
.unbound_list
);
5274 INIT_LIST_HEAD(&dev_priv
->mm
.bound_list
);
5275 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
5276 for (i
= 0; i
< I915_NUM_ENGINES
; i
++)
5277 init_engine_lists(&dev_priv
->engine
[i
]);
5278 for (i
= 0; i
< I915_MAX_NUM_FENCES
; i
++)
5279 INIT_LIST_HEAD(&dev_priv
->fence_regs
[i
].lru_list
);
5280 INIT_DELAYED_WORK(&dev_priv
->mm
.retire_work
,
5281 i915_gem_retire_work_handler
);
5282 INIT_DELAYED_WORK(&dev_priv
->mm
.idle_work
,
5283 i915_gem_idle_work_handler
);
5284 init_waitqueue_head(&dev_priv
->gpu_error
.reset_queue
);
5286 dev_priv
->relative_constants_mode
= I915_EXEC_CONSTANTS_REL_GENERAL
;
5289 * Set initial sequence number for requests.
5290 * Using this number allows the wraparound to happen early,
5291 * catching any obvious problems.
5293 dev_priv
->next_seqno
= ((u32
)~0 - 0x1100);
5294 dev_priv
->last_seqno
= ((u32
)~0 - 0x1101);
5296 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
5298 init_waitqueue_head(&dev_priv
->pending_flip_queue
);
5300 dev_priv
->mm
.interruptible
= true;
5302 mutex_init(&dev_priv
->fb_tracking
.lock
);
5305 void i915_gem_load_cleanup(struct drm_device
*dev
)
5307 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5309 kmem_cache_destroy(dev_priv
->requests
);
5310 kmem_cache_destroy(dev_priv
->vmas
);
5311 kmem_cache_destroy(dev_priv
->objects
);
5314 int i915_gem_freeze_late(struct drm_i915_private
*dev_priv
)
5316 struct drm_i915_gem_object
*obj
;
5318 /* Called just before we write the hibernation image.
5320 * We need to update the domain tracking to reflect that the CPU
5321 * will be accessing all the pages to create and restore from the
5322 * hibernation, and so upon restoration those pages will be in the
5325 * To make sure the hibernation image contains the latest state,
5326 * we update that state just before writing out the image.
5329 list_for_each_entry(obj
, &dev_priv
->mm
.unbound_list
, global_list
) {
5330 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
5331 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
5334 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
5335 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
5336 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
5342 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
)
5344 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
5346 /* Clean up our request list when the client is going away, so that
5347 * later retire_requests won't dereference our soon-to-be-gone
5350 spin_lock(&file_priv
->mm
.lock
);
5351 while (!list_empty(&file_priv
->mm
.request_list
)) {
5352 struct drm_i915_gem_request
*request
;
5354 request
= list_first_entry(&file_priv
->mm
.request_list
,
5355 struct drm_i915_gem_request
,
5357 list_del(&request
->client_list
);
5358 request
->file_priv
= NULL
;
5360 spin_unlock(&file_priv
->mm
.lock
);
5362 if (!list_empty(&file_priv
->rps
.link
)) {
5363 spin_lock(&to_i915(dev
)->rps
.client_lock
);
5364 list_del(&file_priv
->rps
.link
);
5365 spin_unlock(&to_i915(dev
)->rps
.client_lock
);
5369 int i915_gem_open(struct drm_device
*dev
, struct drm_file
*file
)
5371 struct drm_i915_file_private
*file_priv
;
5374 DRM_DEBUG_DRIVER("\n");
5376 file_priv
= kzalloc(sizeof(*file_priv
), GFP_KERNEL
);
5380 file
->driver_priv
= file_priv
;
5381 file_priv
->dev_priv
= dev
->dev_private
;
5382 file_priv
->file
= file
;
5383 INIT_LIST_HEAD(&file_priv
->rps
.link
);
5385 spin_lock_init(&file_priv
->mm
.lock
);
5386 INIT_LIST_HEAD(&file_priv
->mm
.request_list
);
5388 file_priv
->bsd_ring
= -1;
5390 ret
= i915_gem_context_open(dev
, file
);
5398 * i915_gem_track_fb - update frontbuffer tracking
5399 * @old: current GEM buffer for the frontbuffer slots
5400 * @new: new GEM buffer for the frontbuffer slots
5401 * @frontbuffer_bits: bitmask of frontbuffer slots
5403 * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them
5404 * from @old and setting them in @new. Both @old and @new can be NULL.
5406 void i915_gem_track_fb(struct drm_i915_gem_object
*old
,
5407 struct drm_i915_gem_object
*new,
5408 unsigned frontbuffer_bits
)
5411 WARN_ON(!mutex_is_locked(&old
->base
.dev
->struct_mutex
));
5412 WARN_ON(!(old
->frontbuffer_bits
& frontbuffer_bits
));
5413 old
->frontbuffer_bits
&= ~frontbuffer_bits
;
5417 WARN_ON(!mutex_is_locked(&new->base
.dev
->struct_mutex
));
5418 WARN_ON(new->frontbuffer_bits
& frontbuffer_bits
);
5419 new->frontbuffer_bits
|= frontbuffer_bits
;
5423 /* All the new VM stuff */
5424 u64
i915_gem_obj_offset(struct drm_i915_gem_object
*o
,
5425 struct i915_address_space
*vm
)
5427 struct drm_i915_private
*dev_priv
= o
->base
.dev
->dev_private
;
5428 struct i915_vma
*vma
;
5430 WARN_ON(vm
== &dev_priv
->mm
.aliasing_ppgtt
->base
);
5432 list_for_each_entry(vma
, &o
->vma_list
, obj_link
) {
5434 vma
->ggtt_view
.type
!= I915_GGTT_VIEW_NORMAL
)
5437 return vma
->node
.start
;
5440 WARN(1, "%s vma for this object not found.\n",
5441 i915_is_ggtt(vm
) ? "global" : "ppgtt");
5445 u64
i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object
*o
,
5446 const struct i915_ggtt_view
*view
)
5448 struct i915_vma
*vma
;
5450 list_for_each_entry(vma
, &o
->vma_list
, obj_link
)
5451 if (vma
->is_ggtt
&& i915_ggtt_view_equal(&vma
->ggtt_view
, view
))
5452 return vma
->node
.start
;
5454 WARN(1, "global vma for this object not found. (view=%u)\n", view
->type
);
5458 bool i915_gem_obj_bound(struct drm_i915_gem_object
*o
,
5459 struct i915_address_space
*vm
)
5461 struct i915_vma
*vma
;
5463 list_for_each_entry(vma
, &o
->vma_list
, obj_link
) {
5465 vma
->ggtt_view
.type
!= I915_GGTT_VIEW_NORMAL
)
5467 if (vma
->vm
== vm
&& drm_mm_node_allocated(&vma
->node
))
5474 bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object
*o
,
5475 const struct i915_ggtt_view
*view
)
5477 struct i915_vma
*vma
;
5479 list_for_each_entry(vma
, &o
->vma_list
, obj_link
)
5481 i915_ggtt_view_equal(&vma
->ggtt_view
, view
) &&
5482 drm_mm_node_allocated(&vma
->node
))
5488 bool i915_gem_obj_bound_any(struct drm_i915_gem_object
*o
)
5490 struct i915_vma
*vma
;
5492 list_for_each_entry(vma
, &o
->vma_list
, obj_link
)
5493 if (drm_mm_node_allocated(&vma
->node
))
5499 unsigned long i915_gem_obj_ggtt_size(struct drm_i915_gem_object
*o
)
5501 struct i915_vma
*vma
;
5503 GEM_BUG_ON(list_empty(&o
->vma_list
));
5505 list_for_each_entry(vma
, &o
->vma_list
, obj_link
) {
5507 vma
->ggtt_view
.type
== I915_GGTT_VIEW_NORMAL
)
5508 return vma
->node
.size
;
5514 bool i915_gem_obj_is_pinned(struct drm_i915_gem_object
*obj
)
5516 struct i915_vma
*vma
;
5517 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
)
5518 if (vma
->pin_count
> 0)
5524 /* Like i915_gem_object_get_page(), but mark the returned page dirty */
5526 i915_gem_object_get_dirty_page(struct drm_i915_gem_object
*obj
, int n
)
5530 /* Only default objects have per-page dirty tracking */
5531 if (WARN_ON(!i915_gem_object_has_struct_page(obj
)))
5534 page
= i915_gem_object_get_page(obj
, n
);
5535 set_page_dirty(page
);
5539 /* Allocate a new GEM object and fill it with the supplied data */
5540 struct drm_i915_gem_object
*
5541 i915_gem_object_create_from_data(struct drm_device
*dev
,
5542 const void *data
, size_t size
)
5544 struct drm_i915_gem_object
*obj
;
5545 struct sg_table
*sg
;
5549 obj
= i915_gem_object_create(dev
, round_up(size
, PAGE_SIZE
));
5553 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
5557 ret
= i915_gem_object_get_pages(obj
);
5561 i915_gem_object_pin_pages(obj
);
5563 bytes
= sg_copy_from_buffer(sg
->sgl
, sg
->nents
, (void *)data
, size
);
5564 obj
->dirty
= 1; /* Backing store is now out of date */
5565 i915_gem_object_unpin_pages(obj
);
5567 if (WARN_ON(bytes
!= size
)) {
5568 DRM_ERROR("Incomplete copy, wrote %zu of %zu", bytes
, size
);
5576 drm_gem_object_unreference(&obj
->base
);
5577 return ERR_PTR(ret
);