2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/drm_vma_manager.h>
30 #include <drm/i915_drm.h>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/oom.h>
35 #include <linux/shmem_fs.h>
36 #include <linux/slab.h>
37 #include <linux/swap.h>
38 #include <linux/pci.h>
39 #include <linux/dma-buf.h>
41 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
);
42 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
,
44 static __must_check
int
45 i915_gem_object_wait_rendering(struct drm_i915_gem_object
*obj
,
48 i915_gem_object_retire(struct drm_i915_gem_object
*obj
);
50 static void i915_gem_write_fence(struct drm_device
*dev
, int reg
,
51 struct drm_i915_gem_object
*obj
);
52 static void i915_gem_object_update_fence(struct drm_i915_gem_object
*obj
,
53 struct drm_i915_fence_reg
*fence
,
56 static unsigned long i915_gem_shrinker_count(struct shrinker
*shrinker
,
57 struct shrink_control
*sc
);
58 static unsigned long i915_gem_shrinker_scan(struct shrinker
*shrinker
,
59 struct shrink_control
*sc
);
60 static int i915_gem_shrinker_oom(struct notifier_block
*nb
,
63 static unsigned long i915_gem_shrink_all(struct drm_i915_private
*dev_priv
);
65 static bool cpu_cache_is_coherent(struct drm_device
*dev
,
66 enum i915_cache_level level
)
68 return HAS_LLC(dev
) || level
!= I915_CACHE_NONE
;
71 static bool cpu_write_needs_clflush(struct drm_i915_gem_object
*obj
)
73 if (!cpu_cache_is_coherent(obj
->base
.dev
, obj
->cache_level
))
76 return obj
->pin_display
;
79 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object
*obj
)
82 i915_gem_release_mmap(obj
);
84 /* As we do not have an associated fence register, we will force
85 * a tiling change if we ever need to acquire one.
87 obj
->fence_dirty
= false;
88 obj
->fence_reg
= I915_FENCE_REG_NONE
;
91 /* some bookkeeping */
92 static void i915_gem_info_add_obj(struct drm_i915_private
*dev_priv
,
95 spin_lock(&dev_priv
->mm
.object_stat_lock
);
96 dev_priv
->mm
.object_count
++;
97 dev_priv
->mm
.object_memory
+= size
;
98 spin_unlock(&dev_priv
->mm
.object_stat_lock
);
101 static void i915_gem_info_remove_obj(struct drm_i915_private
*dev_priv
,
104 spin_lock(&dev_priv
->mm
.object_stat_lock
);
105 dev_priv
->mm
.object_count
--;
106 dev_priv
->mm
.object_memory
-= size
;
107 spin_unlock(&dev_priv
->mm
.object_stat_lock
);
111 i915_gem_wait_for_error(struct i915_gpu_error
*error
)
115 #define EXIT_COND (!i915_reset_in_progress(error) || \
116 i915_terminally_wedged(error))
121 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
122 * userspace. If it takes that long something really bad is going on and
123 * we should simply try to bail out and fail as gracefully as possible.
125 ret
= wait_event_interruptible_timeout(error
->reset_queue
,
129 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
131 } else if (ret
< 0) {
139 int i915_mutex_lock_interruptible(struct drm_device
*dev
)
141 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
144 ret
= i915_gem_wait_for_error(&dev_priv
->gpu_error
);
148 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
152 WARN_ON(i915_verify_lists(dev
));
157 i915_gem_object_is_inactive(struct drm_i915_gem_object
*obj
)
159 return i915_gem_obj_bound_any(obj
) && !obj
->active
;
163 i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
164 struct drm_file
*file
)
166 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
167 struct drm_i915_gem_init
*args
= data
;
169 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
172 if (args
->gtt_start
>= args
->gtt_end
||
173 (args
->gtt_end
| args
->gtt_start
) & (PAGE_SIZE
- 1))
176 /* GEM with user mode setting was never supported on ilk and later. */
177 if (INTEL_INFO(dev
)->gen
>= 5)
180 mutex_lock(&dev
->struct_mutex
);
181 i915_gem_setup_global_gtt(dev
, args
->gtt_start
, args
->gtt_end
,
183 dev_priv
->gtt
.mappable_end
= args
->gtt_end
;
184 mutex_unlock(&dev
->struct_mutex
);
190 i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
191 struct drm_file
*file
)
193 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
194 struct drm_i915_gem_get_aperture
*args
= data
;
195 struct drm_i915_gem_object
*obj
;
199 mutex_lock(&dev
->struct_mutex
);
200 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
)
201 if (i915_gem_obj_is_pinned(obj
))
202 pinned
+= i915_gem_obj_ggtt_size(obj
);
203 mutex_unlock(&dev
->struct_mutex
);
205 args
->aper_size
= dev_priv
->gtt
.base
.total
;
206 args
->aper_available_size
= args
->aper_size
- pinned
;
212 i915_gem_object_get_pages_phys(struct drm_i915_gem_object
*obj
)
214 struct address_space
*mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
215 char *vaddr
= obj
->phys_handle
->vaddr
;
217 struct scatterlist
*sg
;
220 if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj
)))
223 for (i
= 0; i
< obj
->base
.size
/ PAGE_SIZE
; i
++) {
227 page
= shmem_read_mapping_page(mapping
, i
);
229 return PTR_ERR(page
);
231 src
= kmap_atomic(page
);
232 memcpy(vaddr
, src
, PAGE_SIZE
);
233 drm_clflush_virt_range(vaddr
, PAGE_SIZE
);
236 page_cache_release(page
);
240 i915_gem_chipset_flush(obj
->base
.dev
);
242 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
246 if (sg_alloc_table(st
, 1, GFP_KERNEL
)) {
253 sg
->length
= obj
->base
.size
;
255 sg_dma_address(sg
) = obj
->phys_handle
->busaddr
;
256 sg_dma_len(sg
) = obj
->base
.size
;
259 obj
->has_dma_mapping
= true;
264 i915_gem_object_put_pages_phys(struct drm_i915_gem_object
*obj
)
268 BUG_ON(obj
->madv
== __I915_MADV_PURGED
);
270 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
272 /* In the event of a disaster, abandon all caches and
275 WARN_ON(ret
!= -EIO
);
276 obj
->base
.read_domains
= obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
279 if (obj
->madv
== I915_MADV_DONTNEED
)
283 struct address_space
*mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
284 char *vaddr
= obj
->phys_handle
->vaddr
;
287 for (i
= 0; i
< obj
->base
.size
/ PAGE_SIZE
; i
++) {
291 page
= shmem_read_mapping_page(mapping
, i
);
295 dst
= kmap_atomic(page
);
296 drm_clflush_virt_range(vaddr
, PAGE_SIZE
);
297 memcpy(dst
, vaddr
, PAGE_SIZE
);
300 set_page_dirty(page
);
301 if (obj
->madv
== I915_MADV_WILLNEED
)
302 mark_page_accessed(page
);
303 page_cache_release(page
);
309 sg_free_table(obj
->pages
);
312 obj
->has_dma_mapping
= false;
316 i915_gem_object_release_phys(struct drm_i915_gem_object
*obj
)
318 drm_pci_free(obj
->base
.dev
, obj
->phys_handle
);
321 static const struct drm_i915_gem_object_ops i915_gem_phys_ops
= {
322 .get_pages
= i915_gem_object_get_pages_phys
,
323 .put_pages
= i915_gem_object_put_pages_phys
,
324 .release
= i915_gem_object_release_phys
,
328 drop_pages(struct drm_i915_gem_object
*obj
)
330 struct i915_vma
*vma
, *next
;
333 drm_gem_object_reference(&obj
->base
);
334 list_for_each_entry_safe(vma
, next
, &obj
->vma_list
, vma_link
)
335 if (i915_vma_unbind(vma
))
338 ret
= i915_gem_object_put_pages(obj
);
339 drm_gem_object_unreference(&obj
->base
);
345 i915_gem_object_attach_phys(struct drm_i915_gem_object
*obj
,
348 drm_dma_handle_t
*phys
;
351 if (obj
->phys_handle
) {
352 if ((unsigned long)obj
->phys_handle
->vaddr
& (align
-1))
358 if (obj
->madv
!= I915_MADV_WILLNEED
)
361 if (obj
->base
.filp
== NULL
)
364 ret
= drop_pages(obj
);
368 /* create a new object */
369 phys
= drm_pci_alloc(obj
->base
.dev
, obj
->base
.size
, align
);
373 obj
->phys_handle
= phys
;
374 obj
->ops
= &i915_gem_phys_ops
;
376 return i915_gem_object_get_pages(obj
);
380 i915_gem_phys_pwrite(struct drm_i915_gem_object
*obj
,
381 struct drm_i915_gem_pwrite
*args
,
382 struct drm_file
*file_priv
)
384 struct drm_device
*dev
= obj
->base
.dev
;
385 void *vaddr
= obj
->phys_handle
->vaddr
+ args
->offset
;
386 char __user
*user_data
= to_user_ptr(args
->data_ptr
);
389 /* We manually control the domain here and pretend that it
390 * remains coherent i.e. in the GTT domain, like shmem_pwrite.
392 ret
= i915_gem_object_wait_rendering(obj
, false);
396 if (__copy_from_user_inatomic_nocache(vaddr
, user_data
, args
->size
)) {
397 unsigned long unwritten
;
399 /* The physical object once assigned is fixed for the lifetime
400 * of the obj, so we can safely drop the lock and continue
403 mutex_unlock(&dev
->struct_mutex
);
404 unwritten
= copy_from_user(vaddr
, user_data
, args
->size
);
405 mutex_lock(&dev
->struct_mutex
);
410 drm_clflush_virt_range(vaddr
, args
->size
);
411 i915_gem_chipset_flush(dev
);
415 void *i915_gem_object_alloc(struct drm_device
*dev
)
417 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
418 return kmem_cache_zalloc(dev_priv
->slab
, GFP_KERNEL
);
421 void i915_gem_object_free(struct drm_i915_gem_object
*obj
)
423 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
424 kmem_cache_free(dev_priv
->slab
, obj
);
428 i915_gem_create(struct drm_file
*file
,
429 struct drm_device
*dev
,
433 struct drm_i915_gem_object
*obj
;
437 size
= roundup(size
, PAGE_SIZE
);
441 /* Allocate the new object */
442 obj
= i915_gem_alloc_object(dev
, size
);
446 ret
= drm_gem_handle_create(file
, &obj
->base
, &handle
);
447 /* drop reference from allocate - handle holds it now */
448 drm_gem_object_unreference_unlocked(&obj
->base
);
457 i915_gem_dumb_create(struct drm_file
*file
,
458 struct drm_device
*dev
,
459 struct drm_mode_create_dumb
*args
)
461 /* have to work out size/pitch and return them */
462 args
->pitch
= ALIGN(args
->width
* DIV_ROUND_UP(args
->bpp
, 8), 64);
463 args
->size
= args
->pitch
* args
->height
;
464 return i915_gem_create(file
, dev
,
465 args
->size
, &args
->handle
);
469 * Creates a new mm object and returns a handle to it.
472 i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
473 struct drm_file
*file
)
475 struct drm_i915_gem_create
*args
= data
;
477 return i915_gem_create(file
, dev
,
478 args
->size
, &args
->handle
);
482 __copy_to_user_swizzled(char __user
*cpu_vaddr
,
483 const char *gpu_vaddr
, int gpu_offset
,
486 int ret
, cpu_offset
= 0;
489 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
490 int this_length
= min(cacheline_end
- gpu_offset
, length
);
491 int swizzled_gpu_offset
= gpu_offset
^ 64;
493 ret
= __copy_to_user(cpu_vaddr
+ cpu_offset
,
494 gpu_vaddr
+ swizzled_gpu_offset
,
499 cpu_offset
+= this_length
;
500 gpu_offset
+= this_length
;
501 length
-= this_length
;
508 __copy_from_user_swizzled(char *gpu_vaddr
, int gpu_offset
,
509 const char __user
*cpu_vaddr
,
512 int ret
, cpu_offset
= 0;
515 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
516 int this_length
= min(cacheline_end
- gpu_offset
, length
);
517 int swizzled_gpu_offset
= gpu_offset
^ 64;
519 ret
= __copy_from_user(gpu_vaddr
+ swizzled_gpu_offset
,
520 cpu_vaddr
+ cpu_offset
,
525 cpu_offset
+= this_length
;
526 gpu_offset
+= this_length
;
527 length
-= this_length
;
534 * Pins the specified object's pages and synchronizes the object with
535 * GPU accesses. Sets needs_clflush to non-zero if the caller should
536 * flush the object from the CPU cache.
538 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object
*obj
,
548 if (!(obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
)) {
549 /* If we're not in the cpu read domain, set ourself into the gtt
550 * read domain and manually flush cachelines (if required). This
551 * optimizes for the case when the gpu will dirty the data
552 * anyway again before the next pread happens. */
553 *needs_clflush
= !cpu_cache_is_coherent(obj
->base
.dev
,
555 ret
= i915_gem_object_wait_rendering(obj
, true);
559 i915_gem_object_retire(obj
);
562 ret
= i915_gem_object_get_pages(obj
);
566 i915_gem_object_pin_pages(obj
);
571 /* Per-page copy function for the shmem pread fastpath.
572 * Flushes invalid cachelines before reading the target if
573 * needs_clflush is set. */
575 shmem_pread_fast(struct page
*page
, int shmem_page_offset
, int page_length
,
576 char __user
*user_data
,
577 bool page_do_bit17_swizzling
, bool needs_clflush
)
582 if (unlikely(page_do_bit17_swizzling
))
585 vaddr
= kmap_atomic(page
);
587 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
589 ret
= __copy_to_user_inatomic(user_data
,
590 vaddr
+ shmem_page_offset
,
592 kunmap_atomic(vaddr
);
594 return ret
? -EFAULT
: 0;
598 shmem_clflush_swizzled_range(char *addr
, unsigned long length
,
601 if (unlikely(swizzled
)) {
602 unsigned long start
= (unsigned long) addr
;
603 unsigned long end
= (unsigned long) addr
+ length
;
605 /* For swizzling simply ensure that we always flush both
606 * channels. Lame, but simple and it works. Swizzled
607 * pwrite/pread is far from a hotpath - current userspace
608 * doesn't use it at all. */
609 start
= round_down(start
, 128);
610 end
= round_up(end
, 128);
612 drm_clflush_virt_range((void *)start
, end
- start
);
614 drm_clflush_virt_range(addr
, length
);
619 /* Only difference to the fast-path function is that this can handle bit17
620 * and uses non-atomic copy and kmap functions. */
622 shmem_pread_slow(struct page
*page
, int shmem_page_offset
, int page_length
,
623 char __user
*user_data
,
624 bool page_do_bit17_swizzling
, bool needs_clflush
)
631 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
633 page_do_bit17_swizzling
);
635 if (page_do_bit17_swizzling
)
636 ret
= __copy_to_user_swizzled(user_data
,
637 vaddr
, shmem_page_offset
,
640 ret
= __copy_to_user(user_data
,
641 vaddr
+ shmem_page_offset
,
645 return ret
? - EFAULT
: 0;
649 i915_gem_shmem_pread(struct drm_device
*dev
,
650 struct drm_i915_gem_object
*obj
,
651 struct drm_i915_gem_pread
*args
,
652 struct drm_file
*file
)
654 char __user
*user_data
;
657 int shmem_page_offset
, page_length
, ret
= 0;
658 int obj_do_bit17_swizzling
, page_do_bit17_swizzling
;
660 int needs_clflush
= 0;
661 struct sg_page_iter sg_iter
;
663 user_data
= to_user_ptr(args
->data_ptr
);
666 obj_do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
668 ret
= i915_gem_obj_prepare_shmem_read(obj
, &needs_clflush
);
672 offset
= args
->offset
;
674 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
,
675 offset
>> PAGE_SHIFT
) {
676 struct page
*page
= sg_page_iter_page(&sg_iter
);
681 /* Operation in this page
683 * shmem_page_offset = offset within page in shmem file
684 * page_length = bytes to copy for this page
686 shmem_page_offset
= offset_in_page(offset
);
687 page_length
= remain
;
688 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
689 page_length
= PAGE_SIZE
- shmem_page_offset
;
691 page_do_bit17_swizzling
= obj_do_bit17_swizzling
&&
692 (page_to_phys(page
) & (1 << 17)) != 0;
694 ret
= shmem_pread_fast(page
, shmem_page_offset
, page_length
,
695 user_data
, page_do_bit17_swizzling
,
700 mutex_unlock(&dev
->struct_mutex
);
702 if (likely(!i915
.prefault_disable
) && !prefaulted
) {
703 ret
= fault_in_multipages_writeable(user_data
, remain
);
704 /* Userspace is tricking us, but we've already clobbered
705 * its pages with the prefault and promised to write the
706 * data up to the first fault. Hence ignore any errors
707 * and just continue. */
712 ret
= shmem_pread_slow(page
, shmem_page_offset
, page_length
,
713 user_data
, page_do_bit17_swizzling
,
716 mutex_lock(&dev
->struct_mutex
);
722 remain
-= page_length
;
723 user_data
+= page_length
;
724 offset
+= page_length
;
728 i915_gem_object_unpin_pages(obj
);
734 * Reads data from the object referenced by handle.
736 * On error, the contents of *data are undefined.
739 i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
740 struct drm_file
*file
)
742 struct drm_i915_gem_pread
*args
= data
;
743 struct drm_i915_gem_object
*obj
;
749 if (!access_ok(VERIFY_WRITE
,
750 to_user_ptr(args
->data_ptr
),
754 ret
= i915_mutex_lock_interruptible(dev
);
758 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
759 if (&obj
->base
== NULL
) {
764 /* Bounds check source. */
765 if (args
->offset
> obj
->base
.size
||
766 args
->size
> obj
->base
.size
- args
->offset
) {
771 /* prime objects have no backing filp to GEM pread/pwrite
774 if (!obj
->base
.filp
) {
779 trace_i915_gem_object_pread(obj
, args
->offset
, args
->size
);
781 ret
= i915_gem_shmem_pread(dev
, obj
, args
, file
);
784 drm_gem_object_unreference(&obj
->base
);
786 mutex_unlock(&dev
->struct_mutex
);
790 /* This is the fast write path which cannot handle
791 * page faults in the source data
795 fast_user_write(struct io_mapping
*mapping
,
796 loff_t page_base
, int page_offset
,
797 char __user
*user_data
,
800 void __iomem
*vaddr_atomic
;
802 unsigned long unwritten
;
804 vaddr_atomic
= io_mapping_map_atomic_wc(mapping
, page_base
);
805 /* We can use the cpu mem copy function because this is X86. */
806 vaddr
= (void __force
*)vaddr_atomic
+ page_offset
;
807 unwritten
= __copy_from_user_inatomic_nocache(vaddr
,
809 io_mapping_unmap_atomic(vaddr_atomic
);
814 * This is the fast pwrite path, where we copy the data directly from the
815 * user into the GTT, uncached.
818 i915_gem_gtt_pwrite_fast(struct drm_device
*dev
,
819 struct drm_i915_gem_object
*obj
,
820 struct drm_i915_gem_pwrite
*args
,
821 struct drm_file
*file
)
823 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
825 loff_t offset
, page_base
;
826 char __user
*user_data
;
827 int page_offset
, page_length
, ret
;
829 ret
= i915_gem_obj_ggtt_pin(obj
, 0, PIN_MAPPABLE
| PIN_NONBLOCK
);
833 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
837 ret
= i915_gem_object_put_fence(obj
);
841 user_data
= to_user_ptr(args
->data_ptr
);
844 offset
= i915_gem_obj_ggtt_offset(obj
) + args
->offset
;
847 /* Operation in this page
849 * page_base = page offset within aperture
850 * page_offset = offset within page
851 * page_length = bytes to copy for this page
853 page_base
= offset
& PAGE_MASK
;
854 page_offset
= offset_in_page(offset
);
855 page_length
= remain
;
856 if ((page_offset
+ remain
) > PAGE_SIZE
)
857 page_length
= PAGE_SIZE
- page_offset
;
859 /* If we get a fault while copying data, then (presumably) our
860 * source page isn't available. Return the error and we'll
861 * retry in the slow path.
863 if (fast_user_write(dev_priv
->gtt
.mappable
, page_base
,
864 page_offset
, user_data
, page_length
)) {
869 remain
-= page_length
;
870 user_data
+= page_length
;
871 offset
+= page_length
;
875 i915_gem_object_ggtt_unpin(obj
);
880 /* Per-page copy function for the shmem pwrite fastpath.
881 * Flushes invalid cachelines before writing to the target if
882 * needs_clflush_before is set and flushes out any written cachelines after
883 * writing if needs_clflush is set. */
885 shmem_pwrite_fast(struct page
*page
, int shmem_page_offset
, int page_length
,
886 char __user
*user_data
,
887 bool page_do_bit17_swizzling
,
888 bool needs_clflush_before
,
889 bool needs_clflush_after
)
894 if (unlikely(page_do_bit17_swizzling
))
897 vaddr
= kmap_atomic(page
);
898 if (needs_clflush_before
)
899 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
901 ret
= __copy_from_user_inatomic(vaddr
+ shmem_page_offset
,
902 user_data
, page_length
);
903 if (needs_clflush_after
)
904 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
906 kunmap_atomic(vaddr
);
908 return ret
? -EFAULT
: 0;
911 /* Only difference to the fast-path function is that this can handle bit17
912 * and uses non-atomic copy and kmap functions. */
914 shmem_pwrite_slow(struct page
*page
, int shmem_page_offset
, int page_length
,
915 char __user
*user_data
,
916 bool page_do_bit17_swizzling
,
917 bool needs_clflush_before
,
918 bool needs_clflush_after
)
924 if (unlikely(needs_clflush_before
|| page_do_bit17_swizzling
))
925 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
927 page_do_bit17_swizzling
);
928 if (page_do_bit17_swizzling
)
929 ret
= __copy_from_user_swizzled(vaddr
, shmem_page_offset
,
933 ret
= __copy_from_user(vaddr
+ shmem_page_offset
,
936 if (needs_clflush_after
)
937 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
939 page_do_bit17_swizzling
);
942 return ret
? -EFAULT
: 0;
946 i915_gem_shmem_pwrite(struct drm_device
*dev
,
947 struct drm_i915_gem_object
*obj
,
948 struct drm_i915_gem_pwrite
*args
,
949 struct drm_file
*file
)
953 char __user
*user_data
;
954 int shmem_page_offset
, page_length
, ret
= 0;
955 int obj_do_bit17_swizzling
, page_do_bit17_swizzling
;
956 int hit_slowpath
= 0;
957 int needs_clflush_after
= 0;
958 int needs_clflush_before
= 0;
959 struct sg_page_iter sg_iter
;
961 user_data
= to_user_ptr(args
->data_ptr
);
964 obj_do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
966 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
967 /* If we're not in the cpu write domain, set ourself into the gtt
968 * write domain and manually flush cachelines (if required). This
969 * optimizes for the case when the gpu will use the data
970 * right away and we therefore have to clflush anyway. */
971 needs_clflush_after
= cpu_write_needs_clflush(obj
);
972 ret
= i915_gem_object_wait_rendering(obj
, false);
976 i915_gem_object_retire(obj
);
978 /* Same trick applies to invalidate partially written cachelines read
980 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) == 0)
981 needs_clflush_before
=
982 !cpu_cache_is_coherent(dev
, obj
->cache_level
);
984 ret
= i915_gem_object_get_pages(obj
);
988 i915_gem_object_pin_pages(obj
);
990 offset
= args
->offset
;
993 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
,
994 offset
>> PAGE_SHIFT
) {
995 struct page
*page
= sg_page_iter_page(&sg_iter
);
996 int partial_cacheline_write
;
1001 /* Operation in this page
1003 * shmem_page_offset = offset within page in shmem file
1004 * page_length = bytes to copy for this page
1006 shmem_page_offset
= offset_in_page(offset
);
1008 page_length
= remain
;
1009 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
1010 page_length
= PAGE_SIZE
- shmem_page_offset
;
1012 /* If we don't overwrite a cacheline completely we need to be
1013 * careful to have up-to-date data by first clflushing. Don't
1014 * overcomplicate things and flush the entire patch. */
1015 partial_cacheline_write
= needs_clflush_before
&&
1016 ((shmem_page_offset
| page_length
)
1017 & (boot_cpu_data
.x86_clflush_size
- 1));
1019 page_do_bit17_swizzling
= obj_do_bit17_swizzling
&&
1020 (page_to_phys(page
) & (1 << 17)) != 0;
1022 ret
= shmem_pwrite_fast(page
, shmem_page_offset
, page_length
,
1023 user_data
, page_do_bit17_swizzling
,
1024 partial_cacheline_write
,
1025 needs_clflush_after
);
1030 mutex_unlock(&dev
->struct_mutex
);
1031 ret
= shmem_pwrite_slow(page
, shmem_page_offset
, page_length
,
1032 user_data
, page_do_bit17_swizzling
,
1033 partial_cacheline_write
,
1034 needs_clflush_after
);
1036 mutex_lock(&dev
->struct_mutex
);
1042 remain
-= page_length
;
1043 user_data
+= page_length
;
1044 offset
+= page_length
;
1048 i915_gem_object_unpin_pages(obj
);
1052 * Fixup: Flush cpu caches in case we didn't flush the dirty
1053 * cachelines in-line while writing and the object moved
1054 * out of the cpu write domain while we've dropped the lock.
1056 if (!needs_clflush_after
&&
1057 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
1058 if (i915_gem_clflush_object(obj
, obj
->pin_display
))
1059 i915_gem_chipset_flush(dev
);
1063 if (needs_clflush_after
)
1064 i915_gem_chipset_flush(dev
);
1070 * Writes data to the object referenced by handle.
1072 * On error, the contents of the buffer that were to be modified are undefined.
1075 i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
1076 struct drm_file
*file
)
1078 struct drm_i915_gem_pwrite
*args
= data
;
1079 struct drm_i915_gem_object
*obj
;
1082 if (args
->size
== 0)
1085 if (!access_ok(VERIFY_READ
,
1086 to_user_ptr(args
->data_ptr
),
1090 if (likely(!i915
.prefault_disable
)) {
1091 ret
= fault_in_multipages_readable(to_user_ptr(args
->data_ptr
),
1097 ret
= i915_mutex_lock_interruptible(dev
);
1101 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1102 if (&obj
->base
== NULL
) {
1107 /* Bounds check destination. */
1108 if (args
->offset
> obj
->base
.size
||
1109 args
->size
> obj
->base
.size
- args
->offset
) {
1114 /* prime objects have no backing filp to GEM pread/pwrite
1117 if (!obj
->base
.filp
) {
1122 trace_i915_gem_object_pwrite(obj
, args
->offset
, args
->size
);
1125 /* We can only do the GTT pwrite on untiled buffers, as otherwise
1126 * it would end up going through the fenced access, and we'll get
1127 * different detiling behavior between reading and writing.
1128 * pread/pwrite currently are reading and writing from the CPU
1129 * perspective, requiring manual detiling by the client.
1131 if (obj
->tiling_mode
== I915_TILING_NONE
&&
1132 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
&&
1133 cpu_write_needs_clflush(obj
)) {
1134 ret
= i915_gem_gtt_pwrite_fast(dev
, obj
, args
, file
);
1135 /* Note that the gtt paths might fail with non-page-backed user
1136 * pointers (e.g. gtt mappings when moving data between
1137 * textures). Fallback to the shmem path in that case. */
1140 if (ret
== -EFAULT
|| ret
== -ENOSPC
) {
1141 if (obj
->phys_handle
)
1142 ret
= i915_gem_phys_pwrite(obj
, args
, file
);
1144 ret
= i915_gem_shmem_pwrite(dev
, obj
, args
, file
);
1148 drm_gem_object_unreference(&obj
->base
);
1150 mutex_unlock(&dev
->struct_mutex
);
1155 i915_gem_check_wedge(struct i915_gpu_error
*error
,
1158 if (i915_reset_in_progress(error
)) {
1159 /* Non-interruptible callers can't handle -EAGAIN, hence return
1160 * -EIO unconditionally for these. */
1164 /* Recovery complete, but the reset failed ... */
1165 if (i915_terminally_wedged(error
))
1169 * Check if GPU Reset is in progress - we need intel_ring_begin
1170 * to work properly to reinit the hw state while the gpu is
1171 * still marked as reset-in-progress. Handle this with a flag.
1173 if (!error
->reload_in_reset
)
1181 * Compare seqno against outstanding lazy request. Emit a request if they are
1185 i915_gem_check_olr(struct intel_engine_cs
*ring
, u32 seqno
)
1189 BUG_ON(!mutex_is_locked(&ring
->dev
->struct_mutex
));
1192 if (seqno
== ring
->outstanding_lazy_seqno
)
1193 ret
= i915_add_request(ring
, NULL
);
1198 static void fake_irq(unsigned long data
)
1200 wake_up_process((struct task_struct
*)data
);
1203 static bool missed_irq(struct drm_i915_private
*dev_priv
,
1204 struct intel_engine_cs
*ring
)
1206 return test_bit(ring
->id
, &dev_priv
->gpu_error
.missed_irq_rings
);
1209 static bool can_wait_boost(struct drm_i915_file_private
*file_priv
)
1211 if (file_priv
== NULL
)
1214 return !atomic_xchg(&file_priv
->rps_wait_boost
, true);
1218 * __i915_wait_seqno - wait until execution of seqno has finished
1219 * @ring: the ring expected to report seqno
1221 * @reset_counter: reset sequence associated with the given seqno
1222 * @interruptible: do an interruptible wait (normally yes)
1223 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
1225 * Note: It is of utmost importance that the passed in seqno and reset_counter
1226 * values have been read by the caller in an smp safe manner. Where read-side
1227 * locks are involved, it is sufficient to read the reset_counter before
1228 * unlocking the lock that protects the seqno. For lockless tricks, the
1229 * reset_counter _must_ be read before, and an appropriate smp_rmb must be
1232 * Returns 0 if the seqno was found within the alloted time. Else returns the
1233 * errno with remaining time filled in timeout argument.
1235 int __i915_wait_seqno(struct intel_engine_cs
*ring
, u32 seqno
,
1236 unsigned reset_counter
,
1239 struct drm_i915_file_private
*file_priv
)
1241 struct drm_device
*dev
= ring
->dev
;
1242 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1243 const bool irq_test_in_progress
=
1244 ACCESS_ONCE(dev_priv
->gpu_error
.test_irq_rings
) & intel_ring_flag(ring
);
1246 unsigned long timeout_expire
;
1250 WARN(!intel_irqs_enabled(dev_priv
), "IRQs disabled");
1252 if (i915_seqno_passed(ring
->get_seqno(ring
, true), seqno
))
1255 timeout_expire
= timeout
? jiffies
+ nsecs_to_jiffies((u64
)*timeout
) : 0;
1257 if (INTEL_INFO(dev
)->gen
>= 6 && ring
->id
== RCS
&& can_wait_boost(file_priv
)) {
1258 gen6_rps_boost(dev_priv
);
1260 mod_delayed_work(dev_priv
->wq
,
1261 &file_priv
->mm
.idle_work
,
1262 msecs_to_jiffies(100));
1265 if (!irq_test_in_progress
&& WARN_ON(!ring
->irq_get(ring
)))
1268 /* Record current time in case interrupted by signal, or wedged */
1269 trace_i915_gem_request_wait_begin(ring
, seqno
);
1270 before
= ktime_get_raw_ns();
1272 struct timer_list timer
;
1274 prepare_to_wait(&ring
->irq_queue
, &wait
,
1275 interruptible
? TASK_INTERRUPTIBLE
: TASK_UNINTERRUPTIBLE
);
1277 /* We need to check whether any gpu reset happened in between
1278 * the caller grabbing the seqno and now ... */
1279 if (reset_counter
!= atomic_read(&dev_priv
->gpu_error
.reset_counter
)) {
1280 /* ... but upgrade the -EAGAIN to an -EIO if the gpu
1281 * is truely gone. */
1282 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, interruptible
);
1288 if (i915_seqno_passed(ring
->get_seqno(ring
, false), seqno
)) {
1293 if (interruptible
&& signal_pending(current
)) {
1298 if (timeout
&& time_after_eq(jiffies
, timeout_expire
)) {
1303 timer
.function
= NULL
;
1304 if (timeout
|| missed_irq(dev_priv
, ring
)) {
1305 unsigned long expire
;
1307 setup_timer_on_stack(&timer
, fake_irq
, (unsigned long)current
);
1308 expire
= missed_irq(dev_priv
, ring
) ? jiffies
+ 1 : timeout_expire
;
1309 mod_timer(&timer
, expire
);
1314 if (timer
.function
) {
1315 del_singleshot_timer_sync(&timer
);
1316 destroy_timer_on_stack(&timer
);
1319 now
= ktime_get_raw_ns();
1320 trace_i915_gem_request_wait_end(ring
, seqno
);
1322 if (!irq_test_in_progress
)
1323 ring
->irq_put(ring
);
1325 finish_wait(&ring
->irq_queue
, &wait
);
1328 s64 tres
= *timeout
- (now
- before
);
1330 *timeout
= tres
< 0 ? 0 : tres
;
1337 * Waits for a sequence number to be signaled, and cleans up the
1338 * request and object lists appropriately for that event.
1341 i915_wait_seqno(struct intel_engine_cs
*ring
, uint32_t seqno
)
1343 struct drm_device
*dev
= ring
->dev
;
1344 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1345 bool interruptible
= dev_priv
->mm
.interruptible
;
1346 unsigned reset_counter
;
1349 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
1352 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, interruptible
);
1356 ret
= i915_gem_check_olr(ring
, seqno
);
1360 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
1361 return __i915_wait_seqno(ring
, seqno
, reset_counter
, interruptible
,
1366 i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object
*obj
)
1371 /* Manually manage the write flush as we may have not yet
1372 * retired the buffer.
1374 * Note that the last_write_seqno is always the earlier of
1375 * the two (read/write) seqno, so if we haved successfully waited,
1376 * we know we have passed the last write.
1378 obj
->last_write_seqno
= 0;
1384 * Ensures that all rendering to the object has completed and the object is
1385 * safe to unbind from the GTT or access from the CPU.
1387 static __must_check
int
1388 i915_gem_object_wait_rendering(struct drm_i915_gem_object
*obj
,
1391 struct intel_engine_cs
*ring
= obj
->ring
;
1395 seqno
= readonly
? obj
->last_write_seqno
: obj
->last_read_seqno
;
1399 ret
= i915_wait_seqno(ring
, seqno
);
1403 return i915_gem_object_wait_rendering__tail(obj
);
1406 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1407 * as the object state may change during this call.
1409 static __must_check
int
1410 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object
*obj
,
1411 struct drm_i915_file_private
*file_priv
,
1414 struct drm_device
*dev
= obj
->base
.dev
;
1415 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1416 struct intel_engine_cs
*ring
= obj
->ring
;
1417 unsigned reset_counter
;
1421 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
1422 BUG_ON(!dev_priv
->mm
.interruptible
);
1424 seqno
= readonly
? obj
->last_write_seqno
: obj
->last_read_seqno
;
1428 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, true);
1432 ret
= i915_gem_check_olr(ring
, seqno
);
1436 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
1437 mutex_unlock(&dev
->struct_mutex
);
1438 ret
= __i915_wait_seqno(ring
, seqno
, reset_counter
, true, NULL
,
1440 mutex_lock(&dev
->struct_mutex
);
1444 return i915_gem_object_wait_rendering__tail(obj
);
1448 * Called when user space prepares to use an object with the CPU, either
1449 * through the mmap ioctl's mapping or a GTT mapping.
1452 i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
1453 struct drm_file
*file
)
1455 struct drm_i915_gem_set_domain
*args
= data
;
1456 struct drm_i915_gem_object
*obj
;
1457 uint32_t read_domains
= args
->read_domains
;
1458 uint32_t write_domain
= args
->write_domain
;
1461 /* Only handle setting domains to types used by the CPU. */
1462 if (write_domain
& I915_GEM_GPU_DOMAINS
)
1465 if (read_domains
& I915_GEM_GPU_DOMAINS
)
1468 /* Having something in the write domain implies it's in the read
1469 * domain, and only that read domain. Enforce that in the request.
1471 if (write_domain
!= 0 && read_domains
!= write_domain
)
1474 ret
= i915_mutex_lock_interruptible(dev
);
1478 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1479 if (&obj
->base
== NULL
) {
1484 /* Try to flush the object off the GPU without holding the lock.
1485 * We will repeat the flush holding the lock in the normal manner
1486 * to catch cases where we are gazumped.
1488 ret
= i915_gem_object_wait_rendering__nonblocking(obj
,
1494 if (read_domains
& I915_GEM_DOMAIN_GTT
) {
1495 ret
= i915_gem_object_set_to_gtt_domain(obj
, write_domain
!= 0);
1497 /* Silently promote "you're not bound, there was nothing to do"
1498 * to success, since the client was just asking us to
1499 * make sure everything was done.
1504 ret
= i915_gem_object_set_to_cpu_domain(obj
, write_domain
!= 0);
1508 drm_gem_object_unreference(&obj
->base
);
1510 mutex_unlock(&dev
->struct_mutex
);
1515 * Called when user space has done writes to this buffer
1518 i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1519 struct drm_file
*file
)
1521 struct drm_i915_gem_sw_finish
*args
= data
;
1522 struct drm_i915_gem_object
*obj
;
1525 ret
= i915_mutex_lock_interruptible(dev
);
1529 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1530 if (&obj
->base
== NULL
) {
1535 /* Pinned buffers may be scanout, so flush the cache */
1536 if (obj
->pin_display
)
1537 i915_gem_object_flush_cpu_write_domain(obj
, true);
1539 drm_gem_object_unreference(&obj
->base
);
1541 mutex_unlock(&dev
->struct_mutex
);
1546 * Maps the contents of an object, returning the address it is mapped
1549 * While the mapping holds a reference on the contents of the object, it doesn't
1550 * imply a ref on the object itself.
1554 * DRM driver writers who look a this function as an example for how to do GEM
1555 * mmap support, please don't implement mmap support like here. The modern way
1556 * to implement DRM mmap support is with an mmap offset ioctl (like
1557 * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly.
1558 * That way debug tooling like valgrind will understand what's going on, hiding
1559 * the mmap call in a driver private ioctl will break that. The i915 driver only
1560 * does cpu mmaps this way because we didn't know better.
1563 i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1564 struct drm_file
*file
)
1566 struct drm_i915_gem_mmap
*args
= data
;
1567 struct drm_gem_object
*obj
;
1570 obj
= drm_gem_object_lookup(dev
, file
, args
->handle
);
1574 /* prime objects have no backing filp to GEM mmap
1578 drm_gem_object_unreference_unlocked(obj
);
1582 addr
= vm_mmap(obj
->filp
, 0, args
->size
,
1583 PROT_READ
| PROT_WRITE
, MAP_SHARED
,
1585 drm_gem_object_unreference_unlocked(obj
);
1586 if (IS_ERR((void *)addr
))
1589 args
->addr_ptr
= (uint64_t) addr
;
1595 * i915_gem_fault - fault a page into the GTT
1596 * vma: VMA in question
1599 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1600 * from userspace. The fault handler takes care of binding the object to
1601 * the GTT (if needed), allocating and programming a fence register (again,
1602 * only if needed based on whether the old reg is still valid or the object
1603 * is tiled) and inserting a new PTE into the faulting process.
1605 * Note that the faulting process may involve evicting existing objects
1606 * from the GTT and/or fence registers to make room. So performance may
1607 * suffer if the GTT working set is large or there are few fence registers
1610 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
)
1612 struct drm_i915_gem_object
*obj
= to_intel_bo(vma
->vm_private_data
);
1613 struct drm_device
*dev
= obj
->base
.dev
;
1614 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1615 pgoff_t page_offset
;
1618 bool write
= !!(vmf
->flags
& FAULT_FLAG_WRITE
);
1620 intel_runtime_pm_get(dev_priv
);
1622 /* We don't use vmf->pgoff since that has the fake offset */
1623 page_offset
= ((unsigned long)vmf
->virtual_address
- vma
->vm_start
) >>
1626 ret
= i915_mutex_lock_interruptible(dev
);
1630 trace_i915_gem_object_fault(obj
, page_offset
, true, write
);
1632 /* Try to flush the object off the GPU first without holding the lock.
1633 * Upon reacquiring the lock, we will perform our sanity checks and then
1634 * repeat the flush holding the lock in the normal manner to catch cases
1635 * where we are gazumped.
1637 ret
= i915_gem_object_wait_rendering__nonblocking(obj
, NULL
, !write
);
1641 /* Access to snoopable pages through the GTT is incoherent. */
1642 if (obj
->cache_level
!= I915_CACHE_NONE
&& !HAS_LLC(dev
)) {
1647 /* Now bind it into the GTT if needed */
1648 ret
= i915_gem_obj_ggtt_pin(obj
, 0, PIN_MAPPABLE
);
1652 ret
= i915_gem_object_set_to_gtt_domain(obj
, write
);
1656 ret
= i915_gem_object_get_fence(obj
);
1660 /* Finally, remap it using the new GTT offset */
1661 pfn
= dev_priv
->gtt
.mappable_base
+ i915_gem_obj_ggtt_offset(obj
);
1664 if (!obj
->fault_mappable
) {
1665 unsigned long size
= min_t(unsigned long,
1666 vma
->vm_end
- vma
->vm_start
,
1670 for (i
= 0; i
< size
>> PAGE_SHIFT
; i
++) {
1671 ret
= vm_insert_pfn(vma
,
1672 (unsigned long)vma
->vm_start
+ i
* PAGE_SIZE
,
1678 obj
->fault_mappable
= true;
1680 ret
= vm_insert_pfn(vma
,
1681 (unsigned long)vmf
->virtual_address
,
1684 i915_gem_object_ggtt_unpin(obj
);
1686 mutex_unlock(&dev
->struct_mutex
);
1691 * We eat errors when the gpu is terminally wedged to avoid
1692 * userspace unduly crashing (gl has no provisions for mmaps to
1693 * fail). But any other -EIO isn't ours (e.g. swap in failure)
1694 * and so needs to be reported.
1696 if (!i915_terminally_wedged(&dev_priv
->gpu_error
)) {
1697 ret
= VM_FAULT_SIGBUS
;
1702 * EAGAIN means the gpu is hung and we'll wait for the error
1703 * handler to reset everything when re-faulting in
1704 * i915_mutex_lock_interruptible.
1711 * EBUSY is ok: this just means that another thread
1712 * already did the job.
1714 ret
= VM_FAULT_NOPAGE
;
1721 ret
= VM_FAULT_SIGBUS
;
1724 WARN_ONCE(ret
, "unhandled error in i915_gem_fault: %i\n", ret
);
1725 ret
= VM_FAULT_SIGBUS
;
1729 intel_runtime_pm_put(dev_priv
);
1734 * i915_gem_release_mmap - remove physical page mappings
1735 * @obj: obj in question
1737 * Preserve the reservation of the mmapping with the DRM core code, but
1738 * relinquish ownership of the pages back to the system.
1740 * It is vital that we remove the page mapping if we have mapped a tiled
1741 * object through the GTT and then lose the fence register due to
1742 * resource pressure. Similarly if the object has been moved out of the
1743 * aperture, than pages mapped into userspace must be revoked. Removing the
1744 * mapping will then trigger a page fault on the next user access, allowing
1745 * fixup by i915_gem_fault().
1748 i915_gem_release_mmap(struct drm_i915_gem_object
*obj
)
1750 if (!obj
->fault_mappable
)
1753 drm_vma_node_unmap(&obj
->base
.vma_node
,
1754 obj
->base
.dev
->anon_inode
->i_mapping
);
1755 obj
->fault_mappable
= false;
1759 i915_gem_release_all_mmaps(struct drm_i915_private
*dev_priv
)
1761 struct drm_i915_gem_object
*obj
;
1763 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
)
1764 i915_gem_release_mmap(obj
);
1768 i915_gem_get_gtt_size(struct drm_device
*dev
, uint32_t size
, int tiling_mode
)
1772 if (INTEL_INFO(dev
)->gen
>= 4 ||
1773 tiling_mode
== I915_TILING_NONE
)
1776 /* Previous chips need a power-of-two fence region when tiling */
1777 if (INTEL_INFO(dev
)->gen
== 3)
1778 gtt_size
= 1024*1024;
1780 gtt_size
= 512*1024;
1782 while (gtt_size
< size
)
1789 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1790 * @obj: object to check
1792 * Return the required GTT alignment for an object, taking into account
1793 * potential fence register mapping.
1796 i915_gem_get_gtt_alignment(struct drm_device
*dev
, uint32_t size
,
1797 int tiling_mode
, bool fenced
)
1800 * Minimum alignment is 4k (GTT page size), but might be greater
1801 * if a fence register is needed for the object.
1803 if (INTEL_INFO(dev
)->gen
>= 4 || (!fenced
&& IS_G33(dev
)) ||
1804 tiling_mode
== I915_TILING_NONE
)
1808 * Previous chips need to be aligned to the size of the smallest
1809 * fence register that can contain the object.
1811 return i915_gem_get_gtt_size(dev
, size
, tiling_mode
);
1814 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object
*obj
)
1816 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
1819 if (drm_vma_node_has_offset(&obj
->base
.vma_node
))
1822 dev_priv
->mm
.shrinker_no_lock_stealing
= true;
1824 ret
= drm_gem_create_mmap_offset(&obj
->base
);
1828 /* Badly fragmented mmap space? The only way we can recover
1829 * space is by destroying unwanted objects. We can't randomly release
1830 * mmap_offsets as userspace expects them to be persistent for the
1831 * lifetime of the objects. The closest we can is to release the
1832 * offsets on purgeable objects by truncating it and marking it purged,
1833 * which prevents userspace from ever using that object again.
1835 i915_gem_shrink(dev_priv
,
1836 obj
->base
.size
>> PAGE_SHIFT
,
1838 I915_SHRINK_UNBOUND
|
1839 I915_SHRINK_PURGEABLE
);
1840 ret
= drm_gem_create_mmap_offset(&obj
->base
);
1844 i915_gem_shrink_all(dev_priv
);
1845 ret
= drm_gem_create_mmap_offset(&obj
->base
);
1847 dev_priv
->mm
.shrinker_no_lock_stealing
= false;
1852 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object
*obj
)
1854 drm_gem_free_mmap_offset(&obj
->base
);
1858 i915_gem_mmap_gtt(struct drm_file
*file
,
1859 struct drm_device
*dev
,
1863 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1864 struct drm_i915_gem_object
*obj
;
1867 ret
= i915_mutex_lock_interruptible(dev
);
1871 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, handle
));
1872 if (&obj
->base
== NULL
) {
1877 if (obj
->base
.size
> dev_priv
->gtt
.mappable_end
) {
1882 if (obj
->madv
!= I915_MADV_WILLNEED
) {
1883 DRM_DEBUG("Attempting to mmap a purgeable buffer\n");
1888 ret
= i915_gem_object_create_mmap_offset(obj
);
1892 *offset
= drm_vma_node_offset_addr(&obj
->base
.vma_node
);
1895 drm_gem_object_unreference(&obj
->base
);
1897 mutex_unlock(&dev
->struct_mutex
);
1902 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1904 * @data: GTT mapping ioctl data
1905 * @file: GEM object info
1907 * Simply returns the fake offset to userspace so it can mmap it.
1908 * The mmap call will end up in drm_gem_mmap(), which will set things
1909 * up so we can get faults in the handler above.
1911 * The fault handler will take care of binding the object into the GTT
1912 * (since it may have been evicted to make room for something), allocating
1913 * a fence register, and mapping the appropriate aperture address into
1917 i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
1918 struct drm_file
*file
)
1920 struct drm_i915_gem_mmap_gtt
*args
= data
;
1922 return i915_gem_mmap_gtt(file
, dev
, args
->handle
, &args
->offset
);
1926 i915_gem_object_is_purgeable(struct drm_i915_gem_object
*obj
)
1928 return obj
->madv
== I915_MADV_DONTNEED
;
1931 /* Immediately discard the backing storage */
1933 i915_gem_object_truncate(struct drm_i915_gem_object
*obj
)
1935 i915_gem_object_free_mmap_offset(obj
);
1937 if (obj
->base
.filp
== NULL
)
1940 /* Our goal here is to return as much of the memory as
1941 * is possible back to the system as we are called from OOM.
1942 * To do this we must instruct the shmfs to drop all of its
1943 * backing pages, *now*.
1945 shmem_truncate_range(file_inode(obj
->base
.filp
), 0, (loff_t
)-1);
1946 obj
->madv
= __I915_MADV_PURGED
;
1949 /* Try to discard unwanted pages */
1951 i915_gem_object_invalidate(struct drm_i915_gem_object
*obj
)
1953 struct address_space
*mapping
;
1955 switch (obj
->madv
) {
1956 case I915_MADV_DONTNEED
:
1957 i915_gem_object_truncate(obj
);
1958 case __I915_MADV_PURGED
:
1962 if (obj
->base
.filp
== NULL
)
1965 mapping
= file_inode(obj
->base
.filp
)->i_mapping
,
1966 invalidate_mapping_pages(mapping
, 0, (loff_t
)-1);
1970 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object
*obj
)
1972 struct sg_page_iter sg_iter
;
1975 BUG_ON(obj
->madv
== __I915_MADV_PURGED
);
1977 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
1979 /* In the event of a disaster, abandon all caches and
1980 * hope for the best.
1982 WARN_ON(ret
!= -EIO
);
1983 i915_gem_clflush_object(obj
, true);
1984 obj
->base
.read_domains
= obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
1987 if (i915_gem_object_needs_bit17_swizzle(obj
))
1988 i915_gem_object_save_bit_17_swizzle(obj
);
1990 if (obj
->madv
== I915_MADV_DONTNEED
)
1993 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
, 0) {
1994 struct page
*page
= sg_page_iter_page(&sg_iter
);
1997 set_page_dirty(page
);
1999 if (obj
->madv
== I915_MADV_WILLNEED
)
2000 mark_page_accessed(page
);
2002 page_cache_release(page
);
2006 sg_free_table(obj
->pages
);
2011 i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
)
2013 const struct drm_i915_gem_object_ops
*ops
= obj
->ops
;
2015 if (obj
->pages
== NULL
)
2018 if (obj
->pages_pin_count
)
2021 BUG_ON(i915_gem_obj_bound_any(obj
));
2023 /* ->put_pages might need to allocate memory for the bit17 swizzle
2024 * array, hence protect them from being reaped by removing them from gtt
2026 list_del(&obj
->global_list
);
2028 ops
->put_pages(obj
);
2031 i915_gem_object_invalidate(obj
);
2037 i915_gem_shrink(struct drm_i915_private
*dev_priv
,
2038 long target
, unsigned flags
)
2041 struct list_head
*list
;
2044 { &dev_priv
->mm
.unbound_list
, I915_SHRINK_UNBOUND
},
2045 { &dev_priv
->mm
.bound_list
, I915_SHRINK_BOUND
},
2048 unsigned long count
= 0;
2051 * As we may completely rewrite the (un)bound list whilst unbinding
2052 * (due to retiring requests) we have to strictly process only
2053 * one element of the list at the time, and recheck the list
2054 * on every iteration.
2056 * In particular, we must hold a reference whilst removing the
2057 * object as we may end up waiting for and/or retiring the objects.
2058 * This might release the final reference (held by the active list)
2059 * and result in the object being freed from under us. This is
2060 * similar to the precautions the eviction code must take whilst
2063 * Also note that although these lists do not hold a reference to
2064 * the object we can safely grab one here: The final object
2065 * unreferencing and the bound_list are both protected by the
2066 * dev->struct_mutex and so we won't ever be able to observe an
2067 * object on the bound_list with a reference count equals 0.
2069 for (phase
= phases
; phase
->list
; phase
++) {
2070 struct list_head still_in_list
;
2072 if ((flags
& phase
->bit
) == 0)
2075 INIT_LIST_HEAD(&still_in_list
);
2076 while (count
< target
&& !list_empty(phase
->list
)) {
2077 struct drm_i915_gem_object
*obj
;
2078 struct i915_vma
*vma
, *v
;
2080 obj
= list_first_entry(phase
->list
,
2081 typeof(*obj
), global_list
);
2082 list_move_tail(&obj
->global_list
, &still_in_list
);
2084 if (flags
& I915_SHRINK_PURGEABLE
&&
2085 !i915_gem_object_is_purgeable(obj
))
2088 drm_gem_object_reference(&obj
->base
);
2090 /* For the unbound phase, this should be a no-op! */
2091 list_for_each_entry_safe(vma
, v
,
2092 &obj
->vma_list
, vma_link
)
2093 if (i915_vma_unbind(vma
))
2096 if (i915_gem_object_put_pages(obj
) == 0)
2097 count
+= obj
->base
.size
>> PAGE_SHIFT
;
2099 drm_gem_object_unreference(&obj
->base
);
2101 list_splice(&still_in_list
, phase
->list
);
2107 static unsigned long
2108 i915_gem_shrink_all(struct drm_i915_private
*dev_priv
)
2110 i915_gem_evict_everything(dev_priv
->dev
);
2111 return i915_gem_shrink(dev_priv
, LONG_MAX
,
2112 I915_SHRINK_BOUND
| I915_SHRINK_UNBOUND
);
2116 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object
*obj
)
2118 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2120 struct address_space
*mapping
;
2121 struct sg_table
*st
;
2122 struct scatterlist
*sg
;
2123 struct sg_page_iter sg_iter
;
2125 unsigned long last_pfn
= 0; /* suppress gcc warning */
2128 /* Assert that the object is not currently in any GPU domain. As it
2129 * wasn't in the GTT, there shouldn't be any way it could have been in
2132 BUG_ON(obj
->base
.read_domains
& I915_GEM_GPU_DOMAINS
);
2133 BUG_ON(obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
);
2135 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
2139 page_count
= obj
->base
.size
/ PAGE_SIZE
;
2140 if (sg_alloc_table(st
, page_count
, GFP_KERNEL
)) {
2145 /* Get the list of pages out of our struct file. They'll be pinned
2146 * at this point until we release them.
2148 * Fail silently without starting the shrinker
2150 mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
2151 gfp
= mapping_gfp_mask(mapping
);
2152 gfp
|= __GFP_NORETRY
| __GFP_NOWARN
| __GFP_NO_KSWAPD
;
2153 gfp
&= ~(__GFP_IO
| __GFP_WAIT
);
2156 for (i
= 0; i
< page_count
; i
++) {
2157 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
2159 i915_gem_shrink(dev_priv
,
2162 I915_SHRINK_UNBOUND
|
2163 I915_SHRINK_PURGEABLE
);
2164 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
2167 /* We've tried hard to allocate the memory by reaping
2168 * our own buffer, now let the real VM do its job and
2169 * go down in flames if truly OOM.
2171 i915_gem_shrink_all(dev_priv
);
2172 page
= shmem_read_mapping_page(mapping
, i
);
2176 #ifdef CONFIG_SWIOTLB
2177 if (swiotlb_nr_tbl()) {
2179 sg_set_page(sg
, page
, PAGE_SIZE
, 0);
2184 if (!i
|| page_to_pfn(page
) != last_pfn
+ 1) {
2188 sg_set_page(sg
, page
, PAGE_SIZE
, 0);
2190 sg
->length
+= PAGE_SIZE
;
2192 last_pfn
= page_to_pfn(page
);
2194 /* Check that the i965g/gm workaround works. */
2195 WARN_ON((gfp
& __GFP_DMA32
) && (last_pfn
>= 0x00100000UL
));
2197 #ifdef CONFIG_SWIOTLB
2198 if (!swiotlb_nr_tbl())
2203 if (i915_gem_object_needs_bit17_swizzle(obj
))
2204 i915_gem_object_do_bit_17_swizzle(obj
);
2210 for_each_sg_page(st
->sgl
, &sg_iter
, st
->nents
, 0)
2211 page_cache_release(sg_page_iter_page(&sg_iter
));
2215 /* shmemfs first checks if there is enough memory to allocate the page
2216 * and reports ENOSPC should there be insufficient, along with the usual
2217 * ENOMEM for a genuine allocation failure.
2219 * We use ENOSPC in our driver to mean that we have run out of aperture
2220 * space and so want to translate the error from shmemfs back to our
2221 * usual understanding of ENOMEM.
2223 if (PTR_ERR(page
) == -ENOSPC
)
2226 return PTR_ERR(page
);
2229 /* Ensure that the associated pages are gathered from the backing storage
2230 * and pinned into our object. i915_gem_object_get_pages() may be called
2231 * multiple times before they are released by a single call to
2232 * i915_gem_object_put_pages() - once the pages are no longer referenced
2233 * either as a result of memory pressure (reaping pages under the shrinker)
2234 * or as the object is itself released.
2237 i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
)
2239 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2240 const struct drm_i915_gem_object_ops
*ops
= obj
->ops
;
2246 if (obj
->madv
!= I915_MADV_WILLNEED
) {
2247 DRM_DEBUG("Attempting to obtain a purgeable object\n");
2251 BUG_ON(obj
->pages_pin_count
);
2253 ret
= ops
->get_pages(obj
);
2257 list_add_tail(&obj
->global_list
, &dev_priv
->mm
.unbound_list
);
2262 i915_gem_object_move_to_active(struct drm_i915_gem_object
*obj
,
2263 struct intel_engine_cs
*ring
)
2265 u32 seqno
= intel_ring_get_seqno(ring
);
2267 BUG_ON(ring
== NULL
);
2268 if (obj
->ring
!= ring
&& obj
->last_write_seqno
) {
2269 /* Keep the seqno relative to the current ring */
2270 obj
->last_write_seqno
= seqno
;
2274 /* Add a reference if we're newly entering the active list. */
2276 drm_gem_object_reference(&obj
->base
);
2280 list_move_tail(&obj
->ring_list
, &ring
->active_list
);
2282 obj
->last_read_seqno
= seqno
;
2285 void i915_vma_move_to_active(struct i915_vma
*vma
,
2286 struct intel_engine_cs
*ring
)
2288 list_move_tail(&vma
->mm_list
, &vma
->vm
->active_list
);
2289 return i915_gem_object_move_to_active(vma
->obj
, ring
);
2293 i915_gem_object_move_to_inactive(struct drm_i915_gem_object
*obj
)
2295 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2296 struct i915_address_space
*vm
;
2297 struct i915_vma
*vma
;
2299 BUG_ON(obj
->base
.write_domain
& ~I915_GEM_GPU_DOMAINS
);
2300 BUG_ON(!obj
->active
);
2302 list_for_each_entry(vm
, &dev_priv
->vm_list
, global_link
) {
2303 vma
= i915_gem_obj_to_vma(obj
, vm
);
2304 if (vma
&& !list_empty(&vma
->mm_list
))
2305 list_move_tail(&vma
->mm_list
, &vm
->inactive_list
);
2308 intel_fb_obj_flush(obj
, true);
2310 list_del_init(&obj
->ring_list
);
2313 obj
->last_read_seqno
= 0;
2314 obj
->last_write_seqno
= 0;
2315 obj
->base
.write_domain
= 0;
2317 obj
->last_fenced_seqno
= 0;
2320 drm_gem_object_unreference(&obj
->base
);
2322 WARN_ON(i915_verify_lists(dev
));
2326 i915_gem_object_retire(struct drm_i915_gem_object
*obj
)
2328 struct intel_engine_cs
*ring
= obj
->ring
;
2333 if (i915_seqno_passed(ring
->get_seqno(ring
, true),
2334 obj
->last_read_seqno
))
2335 i915_gem_object_move_to_inactive(obj
);
2339 i915_gem_init_seqno(struct drm_device
*dev
, u32 seqno
)
2341 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2342 struct intel_engine_cs
*ring
;
2345 /* Carefully retire all requests without writing to the rings */
2346 for_each_ring(ring
, dev_priv
, i
) {
2347 ret
= intel_ring_idle(ring
);
2351 i915_gem_retire_requests(dev
);
2353 /* Finally reset hw state */
2354 for_each_ring(ring
, dev_priv
, i
) {
2355 intel_ring_init_seqno(ring
, seqno
);
2357 for (j
= 0; j
< ARRAY_SIZE(ring
->semaphore
.sync_seqno
); j
++)
2358 ring
->semaphore
.sync_seqno
[j
] = 0;
2364 int i915_gem_set_seqno(struct drm_device
*dev
, u32 seqno
)
2366 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2372 /* HWS page needs to be set less than what we
2373 * will inject to ring
2375 ret
= i915_gem_init_seqno(dev
, seqno
- 1);
2379 /* Carefully set the last_seqno value so that wrap
2380 * detection still works
2382 dev_priv
->next_seqno
= seqno
;
2383 dev_priv
->last_seqno
= seqno
- 1;
2384 if (dev_priv
->last_seqno
== 0)
2385 dev_priv
->last_seqno
--;
2391 i915_gem_get_seqno(struct drm_device
*dev
, u32
*seqno
)
2393 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2395 /* reserve 0 for non-seqno */
2396 if (dev_priv
->next_seqno
== 0) {
2397 int ret
= i915_gem_init_seqno(dev
, 0);
2401 dev_priv
->next_seqno
= 1;
2404 *seqno
= dev_priv
->last_seqno
= dev_priv
->next_seqno
++;
2408 int __i915_add_request(struct intel_engine_cs
*ring
,
2409 struct drm_file
*file
,
2410 struct drm_i915_gem_object
*obj
,
2413 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
2414 struct drm_i915_gem_request
*request
;
2415 struct intel_ringbuffer
*ringbuf
;
2416 u32 request_ring_position
, request_start
;
2419 request
= ring
->preallocated_lazy_request
;
2420 if (WARN_ON(request
== NULL
))
2423 if (i915
.enable_execlists
) {
2424 struct intel_context
*ctx
= request
->ctx
;
2425 ringbuf
= ctx
->engine
[ring
->id
].ringbuf
;
2427 ringbuf
= ring
->buffer
;
2429 request_start
= intel_ring_get_tail(ringbuf
);
2431 * Emit any outstanding flushes - execbuf can fail to emit the flush
2432 * after having emitted the batchbuffer command. Hence we need to fix
2433 * things up similar to emitting the lazy request. The difference here
2434 * is that the flush _must_ happen before the next request, no matter
2437 if (i915
.enable_execlists
) {
2438 ret
= logical_ring_flush_all_caches(ringbuf
);
2442 ret
= intel_ring_flush_all_caches(ring
);
2447 /* Record the position of the start of the request so that
2448 * should we detect the updated seqno part-way through the
2449 * GPU processing the request, we never over-estimate the
2450 * position of the head.
2452 request_ring_position
= intel_ring_get_tail(ringbuf
);
2454 if (i915
.enable_execlists
) {
2455 ret
= ring
->emit_request(ringbuf
);
2459 ret
= ring
->add_request(ring
);
2464 request
->seqno
= intel_ring_get_seqno(ring
);
2465 request
->ring
= ring
;
2466 request
->head
= request_start
;
2467 request
->tail
= request_ring_position
;
2469 /* Whilst this request exists, batch_obj will be on the
2470 * active_list, and so will hold the active reference. Only when this
2471 * request is retired will the the batch_obj be moved onto the
2472 * inactive_list and lose its active reference. Hence we do not need
2473 * to explicitly hold another reference here.
2475 request
->batch_obj
= obj
;
2477 if (!i915
.enable_execlists
) {
2478 /* Hold a reference to the current context so that we can inspect
2479 * it later in case a hangcheck error event fires.
2481 request
->ctx
= ring
->last_context
;
2483 i915_gem_context_reference(request
->ctx
);
2486 request
->emitted_jiffies
= jiffies
;
2487 list_add_tail(&request
->list
, &ring
->request_list
);
2488 request
->file_priv
= NULL
;
2491 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
2493 spin_lock(&file_priv
->mm
.lock
);
2494 request
->file_priv
= file_priv
;
2495 list_add_tail(&request
->client_list
,
2496 &file_priv
->mm
.request_list
);
2497 spin_unlock(&file_priv
->mm
.lock
);
2500 trace_i915_gem_request_add(ring
, request
->seqno
);
2501 ring
->outstanding_lazy_seqno
= 0;
2502 ring
->preallocated_lazy_request
= NULL
;
2504 if (!dev_priv
->ums
.mm_suspended
) {
2505 i915_queue_hangcheck(ring
->dev
);
2507 cancel_delayed_work_sync(&dev_priv
->mm
.idle_work
);
2508 queue_delayed_work(dev_priv
->wq
,
2509 &dev_priv
->mm
.retire_work
,
2510 round_jiffies_up_relative(HZ
));
2511 intel_mark_busy(dev_priv
->dev
);
2515 *out_seqno
= request
->seqno
;
2520 i915_gem_request_remove_from_client(struct drm_i915_gem_request
*request
)
2522 struct drm_i915_file_private
*file_priv
= request
->file_priv
;
2527 spin_lock(&file_priv
->mm
.lock
);
2528 list_del(&request
->client_list
);
2529 request
->file_priv
= NULL
;
2530 spin_unlock(&file_priv
->mm
.lock
);
2533 static bool i915_context_is_banned(struct drm_i915_private
*dev_priv
,
2534 const struct intel_context
*ctx
)
2536 unsigned long elapsed
;
2538 elapsed
= get_seconds() - ctx
->hang_stats
.guilty_ts
;
2540 if (ctx
->hang_stats
.banned
)
2543 if (elapsed
<= DRM_I915_CTX_BAN_PERIOD
) {
2544 if (!i915_gem_context_is_default(ctx
)) {
2545 DRM_DEBUG("context hanging too fast, banning!\n");
2547 } else if (i915_stop_ring_allow_ban(dev_priv
)) {
2548 if (i915_stop_ring_allow_warn(dev_priv
))
2549 DRM_ERROR("gpu hanging too fast, banning!\n");
2557 static void i915_set_reset_status(struct drm_i915_private
*dev_priv
,
2558 struct intel_context
*ctx
,
2561 struct i915_ctx_hang_stats
*hs
;
2566 hs
= &ctx
->hang_stats
;
2569 hs
->banned
= i915_context_is_banned(dev_priv
, ctx
);
2571 hs
->guilty_ts
= get_seconds();
2573 hs
->batch_pending
++;
2577 static void i915_gem_free_request(struct drm_i915_gem_request
*request
)
2579 struct intel_context
*ctx
= request
->ctx
;
2581 list_del(&request
->list
);
2582 i915_gem_request_remove_from_client(request
);
2584 if (i915
.enable_execlists
&& ctx
) {
2585 struct intel_engine_cs
*ring
= request
->ring
;
2587 if (ctx
!= ring
->default_context
)
2588 intel_lr_context_unpin(ring
, ctx
);
2589 i915_gem_context_unreference(ctx
);
2594 struct drm_i915_gem_request
*
2595 i915_gem_find_active_request(struct intel_engine_cs
*ring
)
2597 struct drm_i915_gem_request
*request
;
2598 u32 completed_seqno
;
2600 completed_seqno
= ring
->get_seqno(ring
, false);
2602 list_for_each_entry(request
, &ring
->request_list
, list
) {
2603 if (i915_seqno_passed(completed_seqno
, request
->seqno
))
2612 static void i915_gem_reset_ring_status(struct drm_i915_private
*dev_priv
,
2613 struct intel_engine_cs
*ring
)
2615 struct drm_i915_gem_request
*request
;
2618 request
= i915_gem_find_active_request(ring
);
2620 if (request
== NULL
)
2623 ring_hung
= ring
->hangcheck
.score
>= HANGCHECK_SCORE_RING_HUNG
;
2625 i915_set_reset_status(dev_priv
, request
->ctx
, ring_hung
);
2627 list_for_each_entry_continue(request
, &ring
->request_list
, list
)
2628 i915_set_reset_status(dev_priv
, request
->ctx
, false);
2631 static void i915_gem_reset_ring_cleanup(struct drm_i915_private
*dev_priv
,
2632 struct intel_engine_cs
*ring
)
2634 while (!list_empty(&ring
->active_list
)) {
2635 struct drm_i915_gem_object
*obj
;
2637 obj
= list_first_entry(&ring
->active_list
,
2638 struct drm_i915_gem_object
,
2641 i915_gem_object_move_to_inactive(obj
);
2645 * Clear the execlists queue up before freeing the requests, as those
2646 * are the ones that keep the context and ringbuffer backing objects
2649 while (!list_empty(&ring
->execlist_queue
)) {
2650 struct intel_ctx_submit_request
*submit_req
;
2652 submit_req
= list_first_entry(&ring
->execlist_queue
,
2653 struct intel_ctx_submit_request
,
2655 list_del(&submit_req
->execlist_link
);
2656 intel_runtime_pm_put(dev_priv
);
2657 i915_gem_context_unreference(submit_req
->ctx
);
2662 * We must free the requests after all the corresponding objects have
2663 * been moved off active lists. Which is the same order as the normal
2664 * retire_requests function does. This is important if object hold
2665 * implicit references on things like e.g. ppgtt address spaces through
2668 while (!list_empty(&ring
->request_list
)) {
2669 struct drm_i915_gem_request
*request
;
2671 request
= list_first_entry(&ring
->request_list
,
2672 struct drm_i915_gem_request
,
2675 i915_gem_free_request(request
);
2678 /* These may not have been flush before the reset, do so now */
2679 kfree(ring
->preallocated_lazy_request
);
2680 ring
->preallocated_lazy_request
= NULL
;
2681 ring
->outstanding_lazy_seqno
= 0;
2684 void i915_gem_restore_fences(struct drm_device
*dev
)
2686 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2689 for (i
= 0; i
< dev_priv
->num_fence_regs
; i
++) {
2690 struct drm_i915_fence_reg
*reg
= &dev_priv
->fence_regs
[i
];
2693 * Commit delayed tiling changes if we have an object still
2694 * attached to the fence, otherwise just clear the fence.
2697 i915_gem_object_update_fence(reg
->obj
, reg
,
2698 reg
->obj
->tiling_mode
);
2700 i915_gem_write_fence(dev
, i
, NULL
);
2705 void i915_gem_reset(struct drm_device
*dev
)
2707 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2708 struct intel_engine_cs
*ring
;
2712 * Before we free the objects from the requests, we need to inspect
2713 * them for finding the guilty party. As the requests only borrow
2714 * their reference to the objects, the inspection must be done first.
2716 for_each_ring(ring
, dev_priv
, i
)
2717 i915_gem_reset_ring_status(dev_priv
, ring
);
2719 for_each_ring(ring
, dev_priv
, i
)
2720 i915_gem_reset_ring_cleanup(dev_priv
, ring
);
2722 i915_gem_context_reset(dev
);
2724 i915_gem_restore_fences(dev
);
2728 * This function clears the request list as sequence numbers are passed.
2731 i915_gem_retire_requests_ring(struct intel_engine_cs
*ring
)
2735 if (list_empty(&ring
->request_list
))
2738 WARN_ON(i915_verify_lists(ring
->dev
));
2740 seqno
= ring
->get_seqno(ring
, true);
2742 /* Move any buffers on the active list that are no longer referenced
2743 * by the ringbuffer to the flushing/inactive lists as appropriate,
2744 * before we free the context associated with the requests.
2746 while (!list_empty(&ring
->active_list
)) {
2747 struct drm_i915_gem_object
*obj
;
2749 obj
= list_first_entry(&ring
->active_list
,
2750 struct drm_i915_gem_object
,
2753 if (!i915_seqno_passed(seqno
, obj
->last_read_seqno
))
2756 i915_gem_object_move_to_inactive(obj
);
2760 while (!list_empty(&ring
->request_list
)) {
2761 struct drm_i915_gem_request
*request
;
2762 struct intel_ringbuffer
*ringbuf
;
2764 request
= list_first_entry(&ring
->request_list
,
2765 struct drm_i915_gem_request
,
2768 if (!i915_seqno_passed(seqno
, request
->seqno
))
2771 trace_i915_gem_request_retire(ring
, request
->seqno
);
2773 /* This is one of the few common intersection points
2774 * between legacy ringbuffer submission and execlists:
2775 * we need to tell them apart in order to find the correct
2776 * ringbuffer to which the request belongs to.
2778 if (i915
.enable_execlists
) {
2779 struct intel_context
*ctx
= request
->ctx
;
2780 ringbuf
= ctx
->engine
[ring
->id
].ringbuf
;
2782 ringbuf
= ring
->buffer
;
2784 /* We know the GPU must have read the request to have
2785 * sent us the seqno + interrupt, so use the position
2786 * of tail of the request to update the last known position
2789 ringbuf
->last_retired_head
= request
->tail
;
2791 i915_gem_free_request(request
);
2794 if (unlikely(ring
->trace_irq_seqno
&&
2795 i915_seqno_passed(seqno
, ring
->trace_irq_seqno
))) {
2796 ring
->irq_put(ring
);
2797 ring
->trace_irq_seqno
= 0;
2800 WARN_ON(i915_verify_lists(ring
->dev
));
2804 i915_gem_retire_requests(struct drm_device
*dev
)
2806 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2807 struct intel_engine_cs
*ring
;
2811 for_each_ring(ring
, dev_priv
, i
) {
2812 i915_gem_retire_requests_ring(ring
);
2813 idle
&= list_empty(&ring
->request_list
);
2814 if (i915
.enable_execlists
) {
2815 unsigned long flags
;
2817 spin_lock_irqsave(&ring
->execlist_lock
, flags
);
2818 idle
&= list_empty(&ring
->execlist_queue
);
2819 spin_unlock_irqrestore(&ring
->execlist_lock
, flags
);
2821 intel_execlists_retire_requests(ring
);
2826 mod_delayed_work(dev_priv
->wq
,
2827 &dev_priv
->mm
.idle_work
,
2828 msecs_to_jiffies(100));
2834 i915_gem_retire_work_handler(struct work_struct
*work
)
2836 struct drm_i915_private
*dev_priv
=
2837 container_of(work
, typeof(*dev_priv
), mm
.retire_work
.work
);
2838 struct drm_device
*dev
= dev_priv
->dev
;
2841 /* Come back later if the device is busy... */
2843 if (mutex_trylock(&dev
->struct_mutex
)) {
2844 idle
= i915_gem_retire_requests(dev
);
2845 mutex_unlock(&dev
->struct_mutex
);
2848 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
,
2849 round_jiffies_up_relative(HZ
));
2853 i915_gem_idle_work_handler(struct work_struct
*work
)
2855 struct drm_i915_private
*dev_priv
=
2856 container_of(work
, typeof(*dev_priv
), mm
.idle_work
.work
);
2858 intel_mark_idle(dev_priv
->dev
);
2862 * Ensures that an object will eventually get non-busy by flushing any required
2863 * write domains, emitting any outstanding lazy request and retiring and
2864 * completed requests.
2867 i915_gem_object_flush_active(struct drm_i915_gem_object
*obj
)
2872 ret
= i915_gem_check_olr(obj
->ring
, obj
->last_read_seqno
);
2876 i915_gem_retire_requests_ring(obj
->ring
);
2883 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2884 * @DRM_IOCTL_ARGS: standard ioctl arguments
2886 * Returns 0 if successful, else an error is returned with the remaining time in
2887 * the timeout parameter.
2888 * -ETIME: object is still busy after timeout
2889 * -ERESTARTSYS: signal interrupted the wait
2890 * -ENONENT: object doesn't exist
2891 * Also possible, but rare:
2892 * -EAGAIN: GPU wedged
2894 * -ENODEV: Internal IRQ fail
2895 * -E?: The add request failed
2897 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2898 * non-zero timeout parameter the wait ioctl will wait for the given number of
2899 * nanoseconds on an object becoming unbusy. Since the wait itself does so
2900 * without holding struct_mutex the object may become re-busied before this
2901 * function completes. A similar but shorter * race condition exists in the busy
2905 i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
, struct drm_file
*file
)
2907 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2908 struct drm_i915_gem_wait
*args
= data
;
2909 struct drm_i915_gem_object
*obj
;
2910 struct intel_engine_cs
*ring
= NULL
;
2911 unsigned reset_counter
;
2915 if (args
->flags
!= 0)
2918 ret
= i915_mutex_lock_interruptible(dev
);
2922 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->bo_handle
));
2923 if (&obj
->base
== NULL
) {
2924 mutex_unlock(&dev
->struct_mutex
);
2928 /* Need to make sure the object gets inactive eventually. */
2929 ret
= i915_gem_object_flush_active(obj
);
2934 seqno
= obj
->last_read_seqno
;
2941 /* Do this after OLR check to make sure we make forward progress polling
2942 * on this IOCTL with a timeout <=0 (like busy ioctl)
2944 if (args
->timeout_ns
<= 0) {
2949 drm_gem_object_unreference(&obj
->base
);
2950 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
2951 mutex_unlock(&dev
->struct_mutex
);
2953 return __i915_wait_seqno(ring
, seqno
, reset_counter
, true,
2954 &args
->timeout_ns
, file
->driver_priv
);
2957 drm_gem_object_unreference(&obj
->base
);
2958 mutex_unlock(&dev
->struct_mutex
);
2963 * i915_gem_object_sync - sync an object to a ring.
2965 * @obj: object which may be in use on another ring.
2966 * @to: ring we wish to use the object on. May be NULL.
2968 * This code is meant to abstract object synchronization with the GPU.
2969 * Calling with NULL implies synchronizing the object with the CPU
2970 * rather than a particular GPU ring.
2972 * Returns 0 if successful, else propagates up the lower layer error.
2975 i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
2976 struct intel_engine_cs
*to
)
2978 struct intel_engine_cs
*from
= obj
->ring
;
2982 if (from
== NULL
|| to
== from
)
2985 if (to
== NULL
|| !i915_semaphore_is_enabled(obj
->base
.dev
))
2986 return i915_gem_object_wait_rendering(obj
, false);
2988 idx
= intel_ring_sync_index(from
, to
);
2990 seqno
= obj
->last_read_seqno
;
2991 /* Optimization: Avoid semaphore sync when we are sure we already
2992 * waited for an object with higher seqno */
2993 if (seqno
<= from
->semaphore
.sync_seqno
[idx
])
2996 ret
= i915_gem_check_olr(obj
->ring
, seqno
);
3000 trace_i915_gem_ring_sync_to(from
, to
, seqno
);
3001 ret
= to
->semaphore
.sync_to(to
, from
, seqno
);
3003 /* We use last_read_seqno because sync_to()
3004 * might have just caused seqno wrap under
3007 from
->semaphore
.sync_seqno
[idx
] = obj
->last_read_seqno
;
3012 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object
*obj
)
3014 u32 old_write_domain
, old_read_domains
;
3016 /* Force a pagefault for domain tracking on next user access */
3017 i915_gem_release_mmap(obj
);
3019 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
) == 0)
3022 /* Wait for any direct GTT access to complete */
3025 old_read_domains
= obj
->base
.read_domains
;
3026 old_write_domain
= obj
->base
.write_domain
;
3028 obj
->base
.read_domains
&= ~I915_GEM_DOMAIN_GTT
;
3029 obj
->base
.write_domain
&= ~I915_GEM_DOMAIN_GTT
;
3031 trace_i915_gem_object_change_domain(obj
,
3036 int i915_vma_unbind(struct i915_vma
*vma
)
3038 struct drm_i915_gem_object
*obj
= vma
->obj
;
3039 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
3042 if (list_empty(&vma
->vma_link
))
3045 if (!drm_mm_node_allocated(&vma
->node
)) {
3046 i915_gem_vma_destroy(vma
);
3053 BUG_ON(obj
->pages
== NULL
);
3055 ret
= i915_gem_object_finish_gpu(obj
);
3058 /* Continue on if we fail due to EIO, the GPU is hung so we
3059 * should be safe and we need to cleanup or else we might
3060 * cause memory corruption through use-after-free.
3063 /* Throw away the active reference before moving to the unbound list */
3064 i915_gem_object_retire(obj
);
3066 if (i915_is_ggtt(vma
->vm
)) {
3067 i915_gem_object_finish_gtt(obj
);
3069 /* release the fence reg _after_ flushing */
3070 ret
= i915_gem_object_put_fence(obj
);
3075 trace_i915_vma_unbind(vma
);
3077 vma
->unbind_vma(vma
);
3079 list_del_init(&vma
->mm_list
);
3080 if (i915_is_ggtt(vma
->vm
))
3081 obj
->map_and_fenceable
= false;
3083 drm_mm_remove_node(&vma
->node
);
3084 i915_gem_vma_destroy(vma
);
3086 /* Since the unbound list is global, only move to that list if
3087 * no more VMAs exist. */
3088 if (list_empty(&obj
->vma_list
)) {
3089 i915_gem_gtt_finish_object(obj
);
3090 list_move_tail(&obj
->global_list
, &dev_priv
->mm
.unbound_list
);
3093 /* And finally now the object is completely decoupled from this vma,
3094 * we can drop its hold on the backing storage and allow it to be
3095 * reaped by the shrinker.
3097 i915_gem_object_unpin_pages(obj
);
3102 int i915_gpu_idle(struct drm_device
*dev
)
3104 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3105 struct intel_engine_cs
*ring
;
3108 /* Flush everything onto the inactive list. */
3109 for_each_ring(ring
, dev_priv
, i
) {
3110 if (!i915
.enable_execlists
) {
3111 ret
= i915_switch_context(ring
, ring
->default_context
);
3116 ret
= intel_ring_idle(ring
);
3124 static void i965_write_fence_reg(struct drm_device
*dev
, int reg
,
3125 struct drm_i915_gem_object
*obj
)
3127 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3129 int fence_pitch_shift
;
3131 if (INTEL_INFO(dev
)->gen
>= 6) {
3132 fence_reg
= FENCE_REG_SANDYBRIDGE_0
;
3133 fence_pitch_shift
= SANDYBRIDGE_FENCE_PITCH_SHIFT
;
3135 fence_reg
= FENCE_REG_965_0
;
3136 fence_pitch_shift
= I965_FENCE_PITCH_SHIFT
;
3139 fence_reg
+= reg
* 8;
3141 /* To w/a incoherency with non-atomic 64-bit register updates,
3142 * we split the 64-bit update into two 32-bit writes. In order
3143 * for a partial fence not to be evaluated between writes, we
3144 * precede the update with write to turn off the fence register,
3145 * and only enable the fence as the last step.
3147 * For extra levels of paranoia, we make sure each step lands
3148 * before applying the next step.
3150 I915_WRITE(fence_reg
, 0);
3151 POSTING_READ(fence_reg
);
3154 u32 size
= i915_gem_obj_ggtt_size(obj
);
3157 val
= (uint64_t)((i915_gem_obj_ggtt_offset(obj
) + size
- 4096) &
3159 val
|= i915_gem_obj_ggtt_offset(obj
) & 0xfffff000;
3160 val
|= (uint64_t)((obj
->stride
/ 128) - 1) << fence_pitch_shift
;
3161 if (obj
->tiling_mode
== I915_TILING_Y
)
3162 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
3163 val
|= I965_FENCE_REG_VALID
;
3165 I915_WRITE(fence_reg
+ 4, val
>> 32);
3166 POSTING_READ(fence_reg
+ 4);
3168 I915_WRITE(fence_reg
+ 0, val
);
3169 POSTING_READ(fence_reg
);
3171 I915_WRITE(fence_reg
+ 4, 0);
3172 POSTING_READ(fence_reg
+ 4);
3176 static void i915_write_fence_reg(struct drm_device
*dev
, int reg
,
3177 struct drm_i915_gem_object
*obj
)
3179 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3183 u32 size
= i915_gem_obj_ggtt_size(obj
);
3187 WARN((i915_gem_obj_ggtt_offset(obj
) & ~I915_FENCE_START_MASK
) ||
3188 (size
& -size
) != size
||
3189 (i915_gem_obj_ggtt_offset(obj
) & (size
- 1)),
3190 "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
3191 i915_gem_obj_ggtt_offset(obj
), obj
->map_and_fenceable
, size
);
3193 if (obj
->tiling_mode
== I915_TILING_Y
&& HAS_128_BYTE_Y_TILING(dev
))
3198 /* Note: pitch better be a power of two tile widths */
3199 pitch_val
= obj
->stride
/ tile_width
;
3200 pitch_val
= ffs(pitch_val
) - 1;
3202 val
= i915_gem_obj_ggtt_offset(obj
);
3203 if (obj
->tiling_mode
== I915_TILING_Y
)
3204 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
3205 val
|= I915_FENCE_SIZE_BITS(size
);
3206 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
3207 val
|= I830_FENCE_REG_VALID
;
3212 reg
= FENCE_REG_830_0
+ reg
* 4;
3214 reg
= FENCE_REG_945_8
+ (reg
- 8) * 4;
3216 I915_WRITE(reg
, val
);
3220 static void i830_write_fence_reg(struct drm_device
*dev
, int reg
,
3221 struct drm_i915_gem_object
*obj
)
3223 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3227 u32 size
= i915_gem_obj_ggtt_size(obj
);
3230 WARN((i915_gem_obj_ggtt_offset(obj
) & ~I830_FENCE_START_MASK
) ||
3231 (size
& -size
) != size
||
3232 (i915_gem_obj_ggtt_offset(obj
) & (size
- 1)),
3233 "object 0x%08lx not 512K or pot-size 0x%08x aligned\n",
3234 i915_gem_obj_ggtt_offset(obj
), size
);
3236 pitch_val
= obj
->stride
/ 128;
3237 pitch_val
= ffs(pitch_val
) - 1;
3239 val
= i915_gem_obj_ggtt_offset(obj
);
3240 if (obj
->tiling_mode
== I915_TILING_Y
)
3241 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
3242 val
|= I830_FENCE_SIZE_BITS(size
);
3243 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
3244 val
|= I830_FENCE_REG_VALID
;
3248 I915_WRITE(FENCE_REG_830_0
+ reg
* 4, val
);
3249 POSTING_READ(FENCE_REG_830_0
+ reg
* 4);
3252 inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object
*obj
)
3254 return obj
&& obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
;
3257 static void i915_gem_write_fence(struct drm_device
*dev
, int reg
,
3258 struct drm_i915_gem_object
*obj
)
3260 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3262 /* Ensure that all CPU reads are completed before installing a fence
3263 * and all writes before removing the fence.
3265 if (i915_gem_object_needs_mb(dev_priv
->fence_regs
[reg
].obj
))
3268 WARN(obj
&& (!obj
->stride
|| !obj
->tiling_mode
),
3269 "bogus fence setup with stride: 0x%x, tiling mode: %i\n",
3270 obj
->stride
, obj
->tiling_mode
);
3272 switch (INTEL_INFO(dev
)->gen
) {
3278 case 4: i965_write_fence_reg(dev
, reg
, obj
); break;
3279 case 3: i915_write_fence_reg(dev
, reg
, obj
); break;
3280 case 2: i830_write_fence_reg(dev
, reg
, obj
); break;
3284 /* And similarly be paranoid that no direct access to this region
3285 * is reordered to before the fence is installed.
3287 if (i915_gem_object_needs_mb(obj
))
3291 static inline int fence_number(struct drm_i915_private
*dev_priv
,
3292 struct drm_i915_fence_reg
*fence
)
3294 return fence
- dev_priv
->fence_regs
;
3297 static void i915_gem_object_update_fence(struct drm_i915_gem_object
*obj
,
3298 struct drm_i915_fence_reg
*fence
,
3301 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
3302 int reg
= fence_number(dev_priv
, fence
);
3304 i915_gem_write_fence(obj
->base
.dev
, reg
, enable
? obj
: NULL
);
3307 obj
->fence_reg
= reg
;
3309 list_move_tail(&fence
->lru_list
, &dev_priv
->mm
.fence_list
);
3311 obj
->fence_reg
= I915_FENCE_REG_NONE
;
3313 list_del_init(&fence
->lru_list
);
3315 obj
->fence_dirty
= false;
3319 i915_gem_object_wait_fence(struct drm_i915_gem_object
*obj
)
3321 if (obj
->last_fenced_seqno
) {
3322 int ret
= i915_wait_seqno(obj
->ring
, obj
->last_fenced_seqno
);
3326 obj
->last_fenced_seqno
= 0;
3333 i915_gem_object_put_fence(struct drm_i915_gem_object
*obj
)
3335 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
3336 struct drm_i915_fence_reg
*fence
;
3339 ret
= i915_gem_object_wait_fence(obj
);
3343 if (obj
->fence_reg
== I915_FENCE_REG_NONE
)
3346 fence
= &dev_priv
->fence_regs
[obj
->fence_reg
];
3348 if (WARN_ON(fence
->pin_count
))
3351 i915_gem_object_fence_lost(obj
);
3352 i915_gem_object_update_fence(obj
, fence
, false);
3357 static struct drm_i915_fence_reg
*
3358 i915_find_fence_reg(struct drm_device
*dev
)
3360 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3361 struct drm_i915_fence_reg
*reg
, *avail
;
3364 /* First try to find a free reg */
3366 for (i
= dev_priv
->fence_reg_start
; i
< dev_priv
->num_fence_regs
; i
++) {
3367 reg
= &dev_priv
->fence_regs
[i
];
3371 if (!reg
->pin_count
)
3378 /* None available, try to steal one or wait for a user to finish */
3379 list_for_each_entry(reg
, &dev_priv
->mm
.fence_list
, lru_list
) {
3387 /* Wait for completion of pending flips which consume fences */
3388 if (intel_has_pending_fb_unpin(dev
))
3389 return ERR_PTR(-EAGAIN
);
3391 return ERR_PTR(-EDEADLK
);
3395 * i915_gem_object_get_fence - set up fencing for an object
3396 * @obj: object to map through a fence reg
3398 * When mapping objects through the GTT, userspace wants to be able to write
3399 * to them without having to worry about swizzling if the object is tiled.
3400 * This function walks the fence regs looking for a free one for @obj,
3401 * stealing one if it can't find any.
3403 * It then sets up the reg based on the object's properties: address, pitch
3404 * and tiling format.
3406 * For an untiled surface, this removes any existing fence.
3409 i915_gem_object_get_fence(struct drm_i915_gem_object
*obj
)
3411 struct drm_device
*dev
= obj
->base
.dev
;
3412 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3413 bool enable
= obj
->tiling_mode
!= I915_TILING_NONE
;
3414 struct drm_i915_fence_reg
*reg
;
3417 /* Have we updated the tiling parameters upon the object and so
3418 * will need to serialise the write to the associated fence register?
3420 if (obj
->fence_dirty
) {
3421 ret
= i915_gem_object_wait_fence(obj
);
3426 /* Just update our place in the LRU if our fence is getting reused. */
3427 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
3428 reg
= &dev_priv
->fence_regs
[obj
->fence_reg
];
3429 if (!obj
->fence_dirty
) {
3430 list_move_tail(®
->lru_list
,
3431 &dev_priv
->mm
.fence_list
);
3434 } else if (enable
) {
3435 if (WARN_ON(!obj
->map_and_fenceable
))
3438 reg
= i915_find_fence_reg(dev
);
3440 return PTR_ERR(reg
);
3443 struct drm_i915_gem_object
*old
= reg
->obj
;
3445 ret
= i915_gem_object_wait_fence(old
);
3449 i915_gem_object_fence_lost(old
);
3454 i915_gem_object_update_fence(obj
, reg
, enable
);
3459 static bool i915_gem_valid_gtt_space(struct i915_vma
*vma
,
3460 unsigned long cache_level
)
3462 struct drm_mm_node
*gtt_space
= &vma
->node
;
3463 struct drm_mm_node
*other
;
3466 * On some machines we have to be careful when putting differing types
3467 * of snoopable memory together to avoid the prefetcher crossing memory
3468 * domains and dying. During vm initialisation, we decide whether or not
3469 * these constraints apply and set the drm_mm.color_adjust
3472 if (vma
->vm
->mm
.color_adjust
== NULL
)
3475 if (!drm_mm_node_allocated(gtt_space
))
3478 if (list_empty(>t_space
->node_list
))
3481 other
= list_entry(gtt_space
->node_list
.prev
, struct drm_mm_node
, node_list
);
3482 if (other
->allocated
&& !other
->hole_follows
&& other
->color
!= cache_level
)
3485 other
= list_entry(gtt_space
->node_list
.next
, struct drm_mm_node
, node_list
);
3486 if (other
->allocated
&& !gtt_space
->hole_follows
&& other
->color
!= cache_level
)
3493 * Finds free space in the GTT aperture and binds the object there.
3495 static struct i915_vma
*
3496 i915_gem_object_bind_to_vm(struct drm_i915_gem_object
*obj
,
3497 struct i915_address_space
*vm
,
3501 struct drm_device
*dev
= obj
->base
.dev
;
3502 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3503 u32 size
, fence_size
, fence_alignment
, unfenced_alignment
;
3504 unsigned long start
=
3505 flags
& PIN_OFFSET_BIAS
? flags
& PIN_OFFSET_MASK
: 0;
3507 flags
& PIN_MAPPABLE
? dev_priv
->gtt
.mappable_end
: vm
->total
;
3508 struct i915_vma
*vma
;
3511 fence_size
= i915_gem_get_gtt_size(dev
,
3514 fence_alignment
= i915_gem_get_gtt_alignment(dev
,
3516 obj
->tiling_mode
, true);
3517 unfenced_alignment
=
3518 i915_gem_get_gtt_alignment(dev
,
3520 obj
->tiling_mode
, false);
3523 alignment
= flags
& PIN_MAPPABLE
? fence_alignment
:
3525 if (flags
& PIN_MAPPABLE
&& alignment
& (fence_alignment
- 1)) {
3526 DRM_DEBUG("Invalid object alignment requested %u\n", alignment
);
3527 return ERR_PTR(-EINVAL
);
3530 size
= flags
& PIN_MAPPABLE
? fence_size
: obj
->base
.size
;
3532 /* If the object is bigger than the entire aperture, reject it early
3533 * before evicting everything in a vain attempt to find space.
3535 if (obj
->base
.size
> end
) {
3536 DRM_DEBUG("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%lu\n",
3538 flags
& PIN_MAPPABLE
? "mappable" : "total",
3540 return ERR_PTR(-E2BIG
);
3543 ret
= i915_gem_object_get_pages(obj
);
3545 return ERR_PTR(ret
);
3547 i915_gem_object_pin_pages(obj
);
3549 vma
= i915_gem_obj_lookup_or_create_vma(obj
, vm
);
3554 ret
= drm_mm_insert_node_in_range_generic(&vm
->mm
, &vma
->node
,
3558 DRM_MM_SEARCH_DEFAULT
,
3559 DRM_MM_CREATE_DEFAULT
);
3561 ret
= i915_gem_evict_something(dev
, vm
, size
, alignment
,
3570 if (WARN_ON(!i915_gem_valid_gtt_space(vma
, obj
->cache_level
))) {
3572 goto err_remove_node
;
3575 ret
= i915_gem_gtt_prepare_object(obj
);
3577 goto err_remove_node
;
3579 list_move_tail(&obj
->global_list
, &dev_priv
->mm
.bound_list
);
3580 list_add_tail(&vma
->mm_list
, &vm
->inactive_list
);
3582 trace_i915_vma_bind(vma
, flags
);
3583 vma
->bind_vma(vma
, obj
->cache_level
,
3584 flags
& PIN_GLOBAL
? GLOBAL_BIND
: 0);
3589 drm_mm_remove_node(&vma
->node
);
3591 i915_gem_vma_destroy(vma
);
3594 i915_gem_object_unpin_pages(obj
);
3599 i915_gem_clflush_object(struct drm_i915_gem_object
*obj
,
3602 /* If we don't have a page list set up, then we're not pinned
3603 * to GPU, and we can ignore the cache flush because it'll happen
3604 * again at bind time.
3606 if (obj
->pages
== NULL
)
3610 * Stolen memory is always coherent with the GPU as it is explicitly
3611 * marked as wc by the system, or the system is cache-coherent.
3613 if (obj
->stolen
|| obj
->phys_handle
)
3616 /* If the GPU is snooping the contents of the CPU cache,
3617 * we do not need to manually clear the CPU cache lines. However,
3618 * the caches are only snooped when the render cache is
3619 * flushed/invalidated. As we always have to emit invalidations
3620 * and flushes when moving into and out of the RENDER domain, correct
3621 * snooping behaviour occurs naturally as the result of our domain
3624 if (!force
&& cpu_cache_is_coherent(obj
->base
.dev
, obj
->cache_level
))
3627 trace_i915_gem_object_clflush(obj
);
3628 drm_clflush_sg(obj
->pages
);
3633 /** Flushes the GTT write domain for the object if it's dirty. */
3635 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
)
3637 uint32_t old_write_domain
;
3639 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_GTT
)
3642 /* No actual flushing is required for the GTT write domain. Writes
3643 * to it immediately go to main memory as far as we know, so there's
3644 * no chipset flush. It also doesn't land in render cache.
3646 * However, we do have to enforce the order so that all writes through
3647 * the GTT land before any writes to the device, such as updates to
3652 old_write_domain
= obj
->base
.write_domain
;
3653 obj
->base
.write_domain
= 0;
3655 intel_fb_obj_flush(obj
, false);
3657 trace_i915_gem_object_change_domain(obj
,
3658 obj
->base
.read_domains
,
3662 /** Flushes the CPU write domain for the object if it's dirty. */
3664 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
,
3667 uint32_t old_write_domain
;
3669 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
)
3672 if (i915_gem_clflush_object(obj
, force
))
3673 i915_gem_chipset_flush(obj
->base
.dev
);
3675 old_write_domain
= obj
->base
.write_domain
;
3676 obj
->base
.write_domain
= 0;
3678 intel_fb_obj_flush(obj
, false);
3680 trace_i915_gem_object_change_domain(obj
,
3681 obj
->base
.read_domains
,
3686 * Moves a single object to the GTT read, and possibly write domain.
3688 * This function returns when the move is complete, including waiting on
3692 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
, bool write
)
3694 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
3695 struct i915_vma
*vma
= i915_gem_obj_to_ggtt(obj
);
3696 uint32_t old_write_domain
, old_read_domains
;
3699 /* Not valid to be called on unbound objects. */
3703 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_GTT
)
3706 ret
= i915_gem_object_wait_rendering(obj
, !write
);
3710 i915_gem_object_retire(obj
);
3711 i915_gem_object_flush_cpu_write_domain(obj
, false);
3713 /* Serialise direct access to this object with the barriers for
3714 * coherent writes from the GPU, by effectively invalidating the
3715 * GTT domain upon first access.
3717 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
) == 0)
3720 old_write_domain
= obj
->base
.write_domain
;
3721 old_read_domains
= obj
->base
.read_domains
;
3723 /* It should now be out of any other write domains, and we can update
3724 * the domain values for our changes.
3726 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
3727 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
3729 obj
->base
.read_domains
= I915_GEM_DOMAIN_GTT
;
3730 obj
->base
.write_domain
= I915_GEM_DOMAIN_GTT
;
3735 intel_fb_obj_invalidate(obj
, NULL
);
3737 trace_i915_gem_object_change_domain(obj
,
3741 /* And bump the LRU for this access */
3742 if (i915_gem_object_is_inactive(obj
))
3743 list_move_tail(&vma
->mm_list
,
3744 &dev_priv
->gtt
.base
.inactive_list
);
3749 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
3750 enum i915_cache_level cache_level
)
3752 struct drm_device
*dev
= obj
->base
.dev
;
3753 struct i915_vma
*vma
, *next
;
3756 if (obj
->cache_level
== cache_level
)
3759 if (i915_gem_obj_is_pinned(obj
)) {
3760 DRM_DEBUG("can not change the cache level of pinned objects\n");
3764 list_for_each_entry_safe(vma
, next
, &obj
->vma_list
, vma_link
) {
3765 if (!i915_gem_valid_gtt_space(vma
, cache_level
)) {
3766 ret
= i915_vma_unbind(vma
);
3772 if (i915_gem_obj_bound_any(obj
)) {
3773 ret
= i915_gem_object_finish_gpu(obj
);
3777 i915_gem_object_finish_gtt(obj
);
3779 /* Before SandyBridge, you could not use tiling or fence
3780 * registers with snooped memory, so relinquish any fences
3781 * currently pointing to our region in the aperture.
3783 if (INTEL_INFO(dev
)->gen
< 6) {
3784 ret
= i915_gem_object_put_fence(obj
);
3789 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
3790 if (drm_mm_node_allocated(&vma
->node
))
3791 vma
->bind_vma(vma
, cache_level
,
3792 vma
->bound
& GLOBAL_BIND
);
3795 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
3796 vma
->node
.color
= cache_level
;
3797 obj
->cache_level
= cache_level
;
3799 if (cpu_write_needs_clflush(obj
)) {
3800 u32 old_read_domains
, old_write_domain
;
3802 /* If we're coming from LLC cached, then we haven't
3803 * actually been tracking whether the data is in the
3804 * CPU cache or not, since we only allow one bit set
3805 * in obj->write_domain and have been skipping the clflushes.
3806 * Just set it to the CPU cache for now.
3808 i915_gem_object_retire(obj
);
3809 WARN_ON(obj
->base
.write_domain
& ~I915_GEM_DOMAIN_CPU
);
3811 old_read_domains
= obj
->base
.read_domains
;
3812 old_write_domain
= obj
->base
.write_domain
;
3814 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
3815 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
3817 trace_i915_gem_object_change_domain(obj
,
3825 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
3826 struct drm_file
*file
)
3828 struct drm_i915_gem_caching
*args
= data
;
3829 struct drm_i915_gem_object
*obj
;
3832 ret
= i915_mutex_lock_interruptible(dev
);
3836 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3837 if (&obj
->base
== NULL
) {
3842 switch (obj
->cache_level
) {
3843 case I915_CACHE_LLC
:
3844 case I915_CACHE_L3_LLC
:
3845 args
->caching
= I915_CACHING_CACHED
;
3849 args
->caching
= I915_CACHING_DISPLAY
;
3853 args
->caching
= I915_CACHING_NONE
;
3857 drm_gem_object_unreference(&obj
->base
);
3859 mutex_unlock(&dev
->struct_mutex
);
3863 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
3864 struct drm_file
*file
)
3866 struct drm_i915_gem_caching
*args
= data
;
3867 struct drm_i915_gem_object
*obj
;
3868 enum i915_cache_level level
;
3871 switch (args
->caching
) {
3872 case I915_CACHING_NONE
:
3873 level
= I915_CACHE_NONE
;
3875 case I915_CACHING_CACHED
:
3876 level
= I915_CACHE_LLC
;
3878 case I915_CACHING_DISPLAY
:
3879 level
= HAS_WT(dev
) ? I915_CACHE_WT
: I915_CACHE_NONE
;
3885 ret
= i915_mutex_lock_interruptible(dev
);
3889 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3890 if (&obj
->base
== NULL
) {
3895 ret
= i915_gem_object_set_cache_level(obj
, level
);
3897 drm_gem_object_unreference(&obj
->base
);
3899 mutex_unlock(&dev
->struct_mutex
);
3903 static bool is_pin_display(struct drm_i915_gem_object
*obj
)
3905 struct i915_vma
*vma
;
3907 vma
= i915_gem_obj_to_ggtt(obj
);
3911 /* There are 3 sources that pin objects:
3912 * 1. The display engine (scanouts, sprites, cursors);
3913 * 2. Reservations for execbuffer;
3916 * We can ignore reservations as we hold the struct_mutex and
3917 * are only called outside of the reservation path. The user
3918 * can only increment pin_count once, and so if after
3919 * subtracting the potential reference by the user, any pin_count
3920 * remains, it must be due to another use by the display engine.
3922 return vma
->pin_count
- !!obj
->user_pin_count
;
3926 * Prepare buffer for display plane (scanout, cursors, etc).
3927 * Can be called from an uninterruptible phase (modesetting) and allows
3928 * any flushes to be pipelined (for pageflips).
3931 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
3933 struct intel_engine_cs
*pipelined
)
3935 u32 old_read_domains
, old_write_domain
;
3936 bool was_pin_display
;
3939 if (pipelined
!= obj
->ring
) {
3940 ret
= i915_gem_object_sync(obj
, pipelined
);
3945 /* Mark the pin_display early so that we account for the
3946 * display coherency whilst setting up the cache domains.
3948 was_pin_display
= obj
->pin_display
;
3949 obj
->pin_display
= true;
3951 /* The display engine is not coherent with the LLC cache on gen6. As
3952 * a result, we make sure that the pinning that is about to occur is
3953 * done with uncached PTEs. This is lowest common denominator for all
3956 * However for gen6+, we could do better by using the GFDT bit instead
3957 * of uncaching, which would allow us to flush all the LLC-cached data
3958 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3960 ret
= i915_gem_object_set_cache_level(obj
,
3961 HAS_WT(obj
->base
.dev
) ? I915_CACHE_WT
: I915_CACHE_NONE
);
3963 goto err_unpin_display
;
3965 /* As the user may map the buffer once pinned in the display plane
3966 * (e.g. libkms for the bootup splash), we have to ensure that we
3967 * always use map_and_fenceable for all scanout buffers.
3969 ret
= i915_gem_obj_ggtt_pin(obj
, alignment
, PIN_MAPPABLE
);
3971 goto err_unpin_display
;
3973 i915_gem_object_flush_cpu_write_domain(obj
, true);
3975 old_write_domain
= obj
->base
.write_domain
;
3976 old_read_domains
= obj
->base
.read_domains
;
3978 /* It should now be out of any other write domains, and we can update
3979 * the domain values for our changes.
3981 obj
->base
.write_domain
= 0;
3982 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
3984 trace_i915_gem_object_change_domain(obj
,
3991 WARN_ON(was_pin_display
!= is_pin_display(obj
));
3992 obj
->pin_display
= was_pin_display
;
3997 i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object
*obj
)
3999 i915_gem_object_ggtt_unpin(obj
);
4000 obj
->pin_display
= is_pin_display(obj
);
4004 i915_gem_object_finish_gpu(struct drm_i915_gem_object
*obj
)
4008 if ((obj
->base
.read_domains
& I915_GEM_GPU_DOMAINS
) == 0)
4011 ret
= i915_gem_object_wait_rendering(obj
, false);
4015 /* Ensure that we invalidate the GPU's caches and TLBs. */
4016 obj
->base
.read_domains
&= ~I915_GEM_GPU_DOMAINS
;
4021 * Moves a single object to the CPU read, and possibly write domain.
4023 * This function returns when the move is complete, including waiting on
4027 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
)
4029 uint32_t old_write_domain
, old_read_domains
;
4032 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_CPU
)
4035 ret
= i915_gem_object_wait_rendering(obj
, !write
);
4039 i915_gem_object_retire(obj
);
4040 i915_gem_object_flush_gtt_write_domain(obj
);
4042 old_write_domain
= obj
->base
.write_domain
;
4043 old_read_domains
= obj
->base
.read_domains
;
4045 /* Flush the CPU cache if it's still invalid. */
4046 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) == 0) {
4047 i915_gem_clflush_object(obj
, false);
4049 obj
->base
.read_domains
|= I915_GEM_DOMAIN_CPU
;
4052 /* It should now be out of any other write domains, and we can update
4053 * the domain values for our changes.
4055 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
4057 /* If we're writing through the CPU, then the GPU read domains will
4058 * need to be invalidated at next use.
4061 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
4062 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
4066 intel_fb_obj_invalidate(obj
, NULL
);
4068 trace_i915_gem_object_change_domain(obj
,
4075 /* Throttle our rendering by waiting until the ring has completed our requests
4076 * emitted over 20 msec ago.
4078 * Note that if we were to use the current jiffies each time around the loop,
4079 * we wouldn't escape the function with any frames outstanding if the time to
4080 * render a frame was over 20ms.
4082 * This should get us reasonable parallelism between CPU and GPU but also
4083 * relatively low latency when blocking on a particular request to finish.
4086 i915_gem_ring_throttle(struct drm_device
*dev
, struct drm_file
*file
)
4088 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4089 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
4090 unsigned long recent_enough
= jiffies
- msecs_to_jiffies(20);
4091 struct drm_i915_gem_request
*request
;
4092 struct intel_engine_cs
*ring
= NULL
;
4093 unsigned reset_counter
;
4097 ret
= i915_gem_wait_for_error(&dev_priv
->gpu_error
);
4101 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, false);
4105 spin_lock(&file_priv
->mm
.lock
);
4106 list_for_each_entry(request
, &file_priv
->mm
.request_list
, client_list
) {
4107 if (time_after_eq(request
->emitted_jiffies
, recent_enough
))
4110 ring
= request
->ring
;
4111 seqno
= request
->seqno
;
4113 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
4114 spin_unlock(&file_priv
->mm
.lock
);
4119 ret
= __i915_wait_seqno(ring
, seqno
, reset_counter
, true, NULL
, NULL
);
4121 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, 0);
4127 i915_vma_misplaced(struct i915_vma
*vma
, uint32_t alignment
, uint64_t flags
)
4129 struct drm_i915_gem_object
*obj
= vma
->obj
;
4132 vma
->node
.start
& (alignment
- 1))
4135 if (flags
& PIN_MAPPABLE
&& !obj
->map_and_fenceable
)
4138 if (flags
& PIN_OFFSET_BIAS
&&
4139 vma
->node
.start
< (flags
& PIN_OFFSET_MASK
))
4146 i915_gem_object_pin(struct drm_i915_gem_object
*obj
,
4147 struct i915_address_space
*vm
,
4151 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
4152 struct i915_vma
*vma
;
4156 if (WARN_ON(vm
== &dev_priv
->mm
.aliasing_ppgtt
->base
))
4159 if (WARN_ON(flags
& (PIN_GLOBAL
| PIN_MAPPABLE
) && !i915_is_ggtt(vm
)))
4162 if (WARN_ON((flags
& (PIN_MAPPABLE
| PIN_GLOBAL
)) == PIN_MAPPABLE
))
4165 vma
= i915_gem_obj_to_vma(obj
, vm
);
4167 if (WARN_ON(vma
->pin_count
== DRM_I915_GEM_OBJECT_MAX_PIN_COUNT
))
4170 if (i915_vma_misplaced(vma
, alignment
, flags
)) {
4171 WARN(vma
->pin_count
,
4172 "bo is already pinned with incorrect alignment:"
4173 " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d,"
4174 " obj->map_and_fenceable=%d\n",
4175 i915_gem_obj_offset(obj
, vm
), alignment
,
4176 !!(flags
& PIN_MAPPABLE
),
4177 obj
->map_and_fenceable
);
4178 ret
= i915_vma_unbind(vma
);
4186 bound
= vma
? vma
->bound
: 0;
4187 if (vma
== NULL
|| !drm_mm_node_allocated(&vma
->node
)) {
4188 vma
= i915_gem_object_bind_to_vm(obj
, vm
, alignment
, flags
);
4190 return PTR_ERR(vma
);
4193 if (flags
& PIN_GLOBAL
&& !(vma
->bound
& GLOBAL_BIND
))
4194 vma
->bind_vma(vma
, obj
->cache_level
, GLOBAL_BIND
);
4196 if ((bound
^ vma
->bound
) & GLOBAL_BIND
) {
4197 bool mappable
, fenceable
;
4198 u32 fence_size
, fence_alignment
;
4200 fence_size
= i915_gem_get_gtt_size(obj
->base
.dev
,
4203 fence_alignment
= i915_gem_get_gtt_alignment(obj
->base
.dev
,
4208 fenceable
= (vma
->node
.size
== fence_size
&&
4209 (vma
->node
.start
& (fence_alignment
- 1)) == 0);
4211 mappable
= (vma
->node
.start
+ obj
->base
.size
<=
4212 dev_priv
->gtt
.mappable_end
);
4214 obj
->map_and_fenceable
= mappable
&& fenceable
;
4217 WARN_ON(flags
& PIN_MAPPABLE
&& !obj
->map_and_fenceable
);
4220 if (flags
& PIN_MAPPABLE
)
4221 obj
->pin_mappable
|= true;
4227 i915_gem_object_ggtt_unpin(struct drm_i915_gem_object
*obj
)
4229 struct i915_vma
*vma
= i915_gem_obj_to_ggtt(obj
);
4232 BUG_ON(vma
->pin_count
== 0);
4233 BUG_ON(!i915_gem_obj_ggtt_bound(obj
));
4235 if (--vma
->pin_count
== 0)
4236 obj
->pin_mappable
= false;
4240 i915_gem_object_pin_fence(struct drm_i915_gem_object
*obj
)
4242 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
4243 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
4244 struct i915_vma
*ggtt_vma
= i915_gem_obj_to_ggtt(obj
);
4246 WARN_ON(!ggtt_vma
||
4247 dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
>
4248 ggtt_vma
->pin_count
);
4249 dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
++;
4256 i915_gem_object_unpin_fence(struct drm_i915_gem_object
*obj
)
4258 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
4259 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
4260 WARN_ON(dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
<= 0);
4261 dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
--;
4266 i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
4267 struct drm_file
*file
)
4269 struct drm_i915_gem_pin
*args
= data
;
4270 struct drm_i915_gem_object
*obj
;
4273 if (INTEL_INFO(dev
)->gen
>= 6)
4276 ret
= i915_mutex_lock_interruptible(dev
);
4280 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
4281 if (&obj
->base
== NULL
) {
4286 if (obj
->madv
!= I915_MADV_WILLNEED
) {
4287 DRM_DEBUG("Attempting to pin a purgeable buffer\n");
4292 if (obj
->pin_filp
!= NULL
&& obj
->pin_filp
!= file
) {
4293 DRM_DEBUG("Already pinned in i915_gem_pin_ioctl(): %d\n",
4299 if (obj
->user_pin_count
== ULONG_MAX
) {
4304 if (obj
->user_pin_count
== 0) {
4305 ret
= i915_gem_obj_ggtt_pin(obj
, args
->alignment
, PIN_MAPPABLE
);
4310 obj
->user_pin_count
++;
4311 obj
->pin_filp
= file
;
4313 args
->offset
= i915_gem_obj_ggtt_offset(obj
);
4315 drm_gem_object_unreference(&obj
->base
);
4317 mutex_unlock(&dev
->struct_mutex
);
4322 i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
4323 struct drm_file
*file
)
4325 struct drm_i915_gem_pin
*args
= data
;
4326 struct drm_i915_gem_object
*obj
;
4329 ret
= i915_mutex_lock_interruptible(dev
);
4333 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
4334 if (&obj
->base
== NULL
) {
4339 if (obj
->pin_filp
!= file
) {
4340 DRM_DEBUG("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4345 obj
->user_pin_count
--;
4346 if (obj
->user_pin_count
== 0) {
4347 obj
->pin_filp
= NULL
;
4348 i915_gem_object_ggtt_unpin(obj
);
4352 drm_gem_object_unreference(&obj
->base
);
4354 mutex_unlock(&dev
->struct_mutex
);
4359 i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
4360 struct drm_file
*file
)
4362 struct drm_i915_gem_busy
*args
= data
;
4363 struct drm_i915_gem_object
*obj
;
4366 ret
= i915_mutex_lock_interruptible(dev
);
4370 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
4371 if (&obj
->base
== NULL
) {
4376 /* Count all active objects as busy, even if they are currently not used
4377 * by the gpu. Users of this interface expect objects to eventually
4378 * become non-busy without any further actions, therefore emit any
4379 * necessary flushes here.
4381 ret
= i915_gem_object_flush_active(obj
);
4383 args
->busy
= obj
->active
;
4385 BUILD_BUG_ON(I915_NUM_RINGS
> 16);
4386 args
->busy
|= intel_ring_flag(obj
->ring
) << 16;
4389 drm_gem_object_unreference(&obj
->base
);
4391 mutex_unlock(&dev
->struct_mutex
);
4396 i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
4397 struct drm_file
*file_priv
)
4399 return i915_gem_ring_throttle(dev
, file_priv
);
4403 i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
4404 struct drm_file
*file_priv
)
4406 struct drm_i915_gem_madvise
*args
= data
;
4407 struct drm_i915_gem_object
*obj
;
4410 switch (args
->madv
) {
4411 case I915_MADV_DONTNEED
:
4412 case I915_MADV_WILLNEED
:
4418 ret
= i915_mutex_lock_interruptible(dev
);
4422 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file_priv
, args
->handle
));
4423 if (&obj
->base
== NULL
) {
4428 if (i915_gem_obj_is_pinned(obj
)) {
4433 if (obj
->madv
!= __I915_MADV_PURGED
)
4434 obj
->madv
= args
->madv
;
4436 /* if the object is no longer attached, discard its backing storage */
4437 if (i915_gem_object_is_purgeable(obj
) && obj
->pages
== NULL
)
4438 i915_gem_object_truncate(obj
);
4440 args
->retained
= obj
->madv
!= __I915_MADV_PURGED
;
4443 drm_gem_object_unreference(&obj
->base
);
4445 mutex_unlock(&dev
->struct_mutex
);
4449 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
4450 const struct drm_i915_gem_object_ops
*ops
)
4452 INIT_LIST_HEAD(&obj
->global_list
);
4453 INIT_LIST_HEAD(&obj
->ring_list
);
4454 INIT_LIST_HEAD(&obj
->obj_exec_link
);
4455 INIT_LIST_HEAD(&obj
->vma_list
);
4459 obj
->fence_reg
= I915_FENCE_REG_NONE
;
4460 obj
->madv
= I915_MADV_WILLNEED
;
4462 i915_gem_info_add_obj(obj
->base
.dev
->dev_private
, obj
->base
.size
);
4465 static const struct drm_i915_gem_object_ops i915_gem_object_ops
= {
4466 .get_pages
= i915_gem_object_get_pages_gtt
,
4467 .put_pages
= i915_gem_object_put_pages_gtt
,
4470 struct drm_i915_gem_object
*i915_gem_alloc_object(struct drm_device
*dev
,
4473 struct drm_i915_gem_object
*obj
;
4474 struct address_space
*mapping
;
4477 obj
= i915_gem_object_alloc(dev
);
4481 if (drm_gem_object_init(dev
, &obj
->base
, size
) != 0) {
4482 i915_gem_object_free(obj
);
4486 mask
= GFP_HIGHUSER
| __GFP_RECLAIMABLE
;
4487 if (IS_CRESTLINE(dev
) || IS_BROADWATER(dev
)) {
4488 /* 965gm cannot relocate objects above 4GiB. */
4489 mask
&= ~__GFP_HIGHMEM
;
4490 mask
|= __GFP_DMA32
;
4493 mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
4494 mapping_set_gfp_mask(mapping
, mask
);
4496 i915_gem_object_init(obj
, &i915_gem_object_ops
);
4498 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
4499 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
4502 /* On some devices, we can have the GPU use the LLC (the CPU
4503 * cache) for about a 10% performance improvement
4504 * compared to uncached. Graphics requests other than
4505 * display scanout are coherent with the CPU in
4506 * accessing this cache. This means in this mode we
4507 * don't need to clflush on the CPU side, and on the
4508 * GPU side we only need to flush internal caches to
4509 * get data visible to the CPU.
4511 * However, we maintain the display planes as UC, and so
4512 * need to rebind when first used as such.
4514 obj
->cache_level
= I915_CACHE_LLC
;
4516 obj
->cache_level
= I915_CACHE_NONE
;
4518 trace_i915_gem_object_create(obj
);
4523 static bool discard_backing_storage(struct drm_i915_gem_object
*obj
)
4525 /* If we are the last user of the backing storage (be it shmemfs
4526 * pages or stolen etc), we know that the pages are going to be
4527 * immediately released. In this case, we can then skip copying
4528 * back the contents from the GPU.
4531 if (obj
->madv
!= I915_MADV_WILLNEED
)
4534 if (obj
->base
.filp
== NULL
)
4537 /* At first glance, this looks racy, but then again so would be
4538 * userspace racing mmap against close. However, the first external
4539 * reference to the filp can only be obtained through the
4540 * i915_gem_mmap_ioctl() which safeguards us against the user
4541 * acquiring such a reference whilst we are in the middle of
4542 * freeing the object.
4544 return atomic_long_read(&obj
->base
.filp
->f_count
) == 1;
4547 void i915_gem_free_object(struct drm_gem_object
*gem_obj
)
4549 struct drm_i915_gem_object
*obj
= to_intel_bo(gem_obj
);
4550 struct drm_device
*dev
= obj
->base
.dev
;
4551 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4552 struct i915_vma
*vma
, *next
;
4554 intel_runtime_pm_get(dev_priv
);
4556 trace_i915_gem_object_destroy(obj
);
4558 list_for_each_entry_safe(vma
, next
, &obj
->vma_list
, vma_link
) {
4562 ret
= i915_vma_unbind(vma
);
4563 if (WARN_ON(ret
== -ERESTARTSYS
)) {
4564 bool was_interruptible
;
4566 was_interruptible
= dev_priv
->mm
.interruptible
;
4567 dev_priv
->mm
.interruptible
= false;
4569 WARN_ON(i915_vma_unbind(vma
));
4571 dev_priv
->mm
.interruptible
= was_interruptible
;
4575 /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
4576 * before progressing. */
4578 i915_gem_object_unpin_pages(obj
);
4580 WARN_ON(obj
->frontbuffer_bits
);
4582 if (WARN_ON(obj
->pages_pin_count
))
4583 obj
->pages_pin_count
= 0;
4584 if (discard_backing_storage(obj
))
4585 obj
->madv
= I915_MADV_DONTNEED
;
4586 i915_gem_object_put_pages(obj
);
4587 i915_gem_object_free_mmap_offset(obj
);
4591 if (obj
->base
.import_attach
)
4592 drm_prime_gem_destroy(&obj
->base
, NULL
);
4594 if (obj
->ops
->release
)
4595 obj
->ops
->release(obj
);
4597 drm_gem_object_release(&obj
->base
);
4598 i915_gem_info_remove_obj(dev_priv
, obj
->base
.size
);
4601 i915_gem_object_free(obj
);
4603 intel_runtime_pm_put(dev_priv
);
4606 struct i915_vma
*i915_gem_obj_to_vma(struct drm_i915_gem_object
*obj
,
4607 struct i915_address_space
*vm
)
4609 struct i915_vma
*vma
;
4610 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
4617 void i915_gem_vma_destroy(struct i915_vma
*vma
)
4619 struct i915_address_space
*vm
= NULL
;
4620 WARN_ON(vma
->node
.allocated
);
4622 /* Keep the vma as a placeholder in the execbuffer reservation lists */
4623 if (!list_empty(&vma
->exec_list
))
4628 if (!i915_is_ggtt(vm
))
4629 i915_ppgtt_put(i915_vm_to_ppgtt(vm
));
4631 list_del(&vma
->vma_link
);
4637 i915_gem_stop_ringbuffers(struct drm_device
*dev
)
4639 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4640 struct intel_engine_cs
*ring
;
4643 for_each_ring(ring
, dev_priv
, i
)
4644 dev_priv
->gt
.stop_ring(ring
);
4648 i915_gem_suspend(struct drm_device
*dev
)
4650 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4653 mutex_lock(&dev
->struct_mutex
);
4654 if (dev_priv
->ums
.mm_suspended
)
4657 ret
= i915_gpu_idle(dev
);
4661 i915_gem_retire_requests(dev
);
4663 /* Under UMS, be paranoid and evict. */
4664 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
4665 i915_gem_evict_everything(dev
);
4667 i915_kernel_lost_context(dev
);
4668 i915_gem_stop_ringbuffers(dev
);
4670 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4671 * We need to replace this with a semaphore, or something.
4672 * And not confound ums.mm_suspended!
4674 dev_priv
->ums
.mm_suspended
= !drm_core_check_feature(dev
,
4676 mutex_unlock(&dev
->struct_mutex
);
4678 del_timer_sync(&dev_priv
->gpu_error
.hangcheck_timer
);
4679 cancel_delayed_work_sync(&dev_priv
->mm
.retire_work
);
4680 flush_delayed_work(&dev_priv
->mm
.idle_work
);
4685 mutex_unlock(&dev
->struct_mutex
);
4689 int i915_gem_l3_remap(struct intel_engine_cs
*ring
, int slice
)
4691 struct drm_device
*dev
= ring
->dev
;
4692 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4693 u32 reg_base
= GEN7_L3LOG_BASE
+ (slice
* 0x200);
4694 u32
*remap_info
= dev_priv
->l3_parity
.remap_info
[slice
];
4697 if (!HAS_L3_DPF(dev
) || !remap_info
)
4700 ret
= intel_ring_begin(ring
, GEN7_L3LOG_SIZE
/ 4 * 3);
4705 * Note: We do not worry about the concurrent register cacheline hang
4706 * here because no other code should access these registers other than
4707 * at initialization time.
4709 for (i
= 0; i
< GEN7_L3LOG_SIZE
; i
+= 4) {
4710 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
4711 intel_ring_emit(ring
, reg_base
+ i
);
4712 intel_ring_emit(ring
, remap_info
[i
/4]);
4715 intel_ring_advance(ring
);
4720 void i915_gem_init_swizzling(struct drm_device
*dev
)
4722 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4724 if (INTEL_INFO(dev
)->gen
< 5 ||
4725 dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_NONE
)
4728 I915_WRITE(DISP_ARB_CTL
, I915_READ(DISP_ARB_CTL
) |
4729 DISP_TILE_SURFACE_SWIZZLING
);
4734 I915_WRITE(TILECTL
, I915_READ(TILECTL
) | TILECTL_SWZCTL
);
4736 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB
));
4737 else if (IS_GEN7(dev
))
4738 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB
));
4739 else if (IS_GEN8(dev
))
4740 I915_WRITE(GAMTARBMODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW
));
4746 intel_enable_blt(struct drm_device
*dev
)
4751 /* The blitter was dysfunctional on early prototypes */
4752 if (IS_GEN6(dev
) && dev
->pdev
->revision
< 8) {
4753 DRM_INFO("BLT not supported on this pre-production hardware;"
4754 " graphics performance will be degraded.\n");
4761 static void init_unused_ring(struct drm_device
*dev
, u32 base
)
4763 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4765 I915_WRITE(RING_CTL(base
), 0);
4766 I915_WRITE(RING_HEAD(base
), 0);
4767 I915_WRITE(RING_TAIL(base
), 0);
4768 I915_WRITE(RING_START(base
), 0);
4771 static void init_unused_rings(struct drm_device
*dev
)
4774 init_unused_ring(dev
, PRB1_BASE
);
4775 init_unused_ring(dev
, SRB0_BASE
);
4776 init_unused_ring(dev
, SRB1_BASE
);
4777 init_unused_ring(dev
, SRB2_BASE
);
4778 init_unused_ring(dev
, SRB3_BASE
);
4779 } else if (IS_GEN2(dev
)) {
4780 init_unused_ring(dev
, SRB0_BASE
);
4781 init_unused_ring(dev
, SRB1_BASE
);
4782 } else if (IS_GEN3(dev
)) {
4783 init_unused_ring(dev
, PRB1_BASE
);
4784 init_unused_ring(dev
, PRB2_BASE
);
4788 int i915_gem_init_rings(struct drm_device
*dev
)
4790 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4794 * At least 830 can leave some of the unused rings
4795 * "active" (ie. head != tail) after resume which
4796 * will prevent c3 entry. Makes sure all unused rings
4799 init_unused_rings(dev
);
4801 ret
= intel_init_render_ring_buffer(dev
);
4806 ret
= intel_init_bsd_ring_buffer(dev
);
4808 goto cleanup_render_ring
;
4811 if (intel_enable_blt(dev
)) {
4812 ret
= intel_init_blt_ring_buffer(dev
);
4814 goto cleanup_bsd_ring
;
4817 if (HAS_VEBOX(dev
)) {
4818 ret
= intel_init_vebox_ring_buffer(dev
);
4820 goto cleanup_blt_ring
;
4823 if (HAS_BSD2(dev
)) {
4824 ret
= intel_init_bsd2_ring_buffer(dev
);
4826 goto cleanup_vebox_ring
;
4829 ret
= i915_gem_set_seqno(dev
, ((u32
)~0 - 0x1000));
4831 goto cleanup_bsd2_ring
;
4836 intel_cleanup_ring_buffer(&dev_priv
->ring
[VCS2
]);
4838 intel_cleanup_ring_buffer(&dev_priv
->ring
[VECS
]);
4840 intel_cleanup_ring_buffer(&dev_priv
->ring
[BCS
]);
4842 intel_cleanup_ring_buffer(&dev_priv
->ring
[VCS
]);
4843 cleanup_render_ring
:
4844 intel_cleanup_ring_buffer(&dev_priv
->ring
[RCS
]);
4850 i915_gem_init_hw(struct drm_device
*dev
)
4852 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4855 if (INTEL_INFO(dev
)->gen
< 6 && !intel_enable_gtt())
4858 if (dev_priv
->ellc_size
)
4859 I915_WRITE(HSW_IDICR
, I915_READ(HSW_IDICR
) | IDIHASHMSK(0xf));
4861 if (IS_HASWELL(dev
))
4862 I915_WRITE(MI_PREDICATE_RESULT_2
, IS_HSW_GT3(dev
) ?
4863 LOWER_SLICE_ENABLED
: LOWER_SLICE_DISABLED
);
4865 if (HAS_PCH_NOP(dev
)) {
4866 if (IS_IVYBRIDGE(dev
)) {
4867 u32 temp
= I915_READ(GEN7_MSG_CTL
);
4868 temp
&= ~(WAIT_FOR_PCH_FLR_ACK
| WAIT_FOR_PCH_RESET_ACK
);
4869 I915_WRITE(GEN7_MSG_CTL
, temp
);
4870 } else if (INTEL_INFO(dev
)->gen
>= 7) {
4871 u32 temp
= I915_READ(HSW_NDE_RSTWRN_OPT
);
4872 temp
&= ~RESET_PCH_HANDSHAKE_ENABLE
;
4873 I915_WRITE(HSW_NDE_RSTWRN_OPT
, temp
);
4877 i915_gem_init_swizzling(dev
);
4879 ret
= dev_priv
->gt
.init_rings(dev
);
4883 for (i
= 0; i
< NUM_L3_SLICES(dev
); i
++)
4884 i915_gem_l3_remap(&dev_priv
->ring
[RCS
], i
);
4887 * XXX: Contexts should only be initialized once. Doing a switch to the
4888 * default context switch however is something we'd like to do after
4889 * reset or thaw (the latter may not actually be necessary for HW, but
4890 * goes with our code better). Context switching requires rings (for
4891 * the do_switch), but before enabling PPGTT. So don't move this.
4893 ret
= i915_gem_context_enable(dev_priv
);
4894 if (ret
&& ret
!= -EIO
) {
4895 DRM_ERROR("Context enable failed %d\n", ret
);
4896 i915_gem_cleanup_ringbuffer(dev
);
4901 ret
= i915_ppgtt_init_hw(dev
);
4902 if (ret
&& ret
!= -EIO
) {
4903 DRM_ERROR("PPGTT enable failed %d\n", ret
);
4904 i915_gem_cleanup_ringbuffer(dev
);
4910 int i915_gem_init(struct drm_device
*dev
)
4912 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4915 i915
.enable_execlists
= intel_sanitize_enable_execlists(dev
,
4916 i915
.enable_execlists
);
4918 mutex_lock(&dev
->struct_mutex
);
4920 if (IS_VALLEYVIEW(dev
)) {
4921 /* VLVA0 (potential hack), BIOS isn't actually waking us */
4922 I915_WRITE(VLV_GTLC_WAKE_CTRL
, VLV_GTLC_ALLOWWAKEREQ
);
4923 if (wait_for((I915_READ(VLV_GTLC_PW_STATUS
) &
4924 VLV_GTLC_ALLOWWAKEACK
), 10))
4925 DRM_DEBUG_DRIVER("allow wake ack timed out\n");
4928 if (!i915
.enable_execlists
) {
4929 dev_priv
->gt
.do_execbuf
= i915_gem_ringbuffer_submission
;
4930 dev_priv
->gt
.init_rings
= i915_gem_init_rings
;
4931 dev_priv
->gt
.cleanup_ring
= intel_cleanup_ring_buffer
;
4932 dev_priv
->gt
.stop_ring
= intel_stop_ring_buffer
;
4934 dev_priv
->gt
.do_execbuf
= intel_execlists_submission
;
4935 dev_priv
->gt
.init_rings
= intel_logical_rings_init
;
4936 dev_priv
->gt
.cleanup_ring
= intel_logical_ring_cleanup
;
4937 dev_priv
->gt
.stop_ring
= intel_logical_ring_stop
;
4940 ret
= i915_gem_init_userptr(dev
);
4942 mutex_unlock(&dev
->struct_mutex
);
4946 i915_gem_init_global_gtt(dev
);
4948 ret
= i915_gem_context_init(dev
);
4950 mutex_unlock(&dev
->struct_mutex
);
4954 ret
= i915_gem_init_hw(dev
);
4956 /* Allow ring initialisation to fail by marking the GPU as
4957 * wedged. But we only want to do this where the GPU is angry,
4958 * for all other failure, such as an allocation failure, bail.
4960 DRM_ERROR("Failed to initialize GPU, declaring it wedged\n");
4961 atomic_set_mask(I915_WEDGED
, &dev_priv
->gpu_error
.reset_counter
);
4964 mutex_unlock(&dev
->struct_mutex
);
4966 /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */
4967 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
4968 dev_priv
->dri1
.allow_batchbuffer
= 1;
4973 i915_gem_cleanup_ringbuffer(struct drm_device
*dev
)
4975 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4976 struct intel_engine_cs
*ring
;
4979 for_each_ring(ring
, dev_priv
, i
)
4980 dev_priv
->gt
.cleanup_ring(ring
);
4984 i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
4985 struct drm_file
*file_priv
)
4987 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4990 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4993 if (i915_reset_in_progress(&dev_priv
->gpu_error
)) {
4994 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4995 atomic_set(&dev_priv
->gpu_error
.reset_counter
, 0);
4998 mutex_lock(&dev
->struct_mutex
);
4999 dev_priv
->ums
.mm_suspended
= 0;
5001 ret
= i915_gem_init_hw(dev
);
5003 mutex_unlock(&dev
->struct_mutex
);
5007 BUG_ON(!list_empty(&dev_priv
->gtt
.base
.active_list
));
5009 ret
= drm_irq_install(dev
, dev
->pdev
->irq
);
5011 goto cleanup_ringbuffer
;
5012 mutex_unlock(&dev
->struct_mutex
);
5017 i915_gem_cleanup_ringbuffer(dev
);
5018 dev_priv
->ums
.mm_suspended
= 1;
5019 mutex_unlock(&dev
->struct_mutex
);
5025 i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
5026 struct drm_file
*file_priv
)
5028 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
5031 mutex_lock(&dev
->struct_mutex
);
5032 drm_irq_uninstall(dev
);
5033 mutex_unlock(&dev
->struct_mutex
);
5035 return i915_gem_suspend(dev
);
5039 i915_gem_lastclose(struct drm_device
*dev
)
5043 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
5046 ret
= i915_gem_suspend(dev
);
5048 DRM_ERROR("failed to idle hardware: %d\n", ret
);
5052 init_ring_lists(struct intel_engine_cs
*ring
)
5054 INIT_LIST_HEAD(&ring
->active_list
);
5055 INIT_LIST_HEAD(&ring
->request_list
);
5058 void i915_init_vm(struct drm_i915_private
*dev_priv
,
5059 struct i915_address_space
*vm
)
5061 if (!i915_is_ggtt(vm
))
5062 drm_mm_init(&vm
->mm
, vm
->start
, vm
->total
);
5063 vm
->dev
= dev_priv
->dev
;
5064 INIT_LIST_HEAD(&vm
->active_list
);
5065 INIT_LIST_HEAD(&vm
->inactive_list
);
5066 INIT_LIST_HEAD(&vm
->global_link
);
5067 list_add_tail(&vm
->global_link
, &dev_priv
->vm_list
);
5071 i915_gem_load(struct drm_device
*dev
)
5073 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5077 kmem_cache_create("i915_gem_object",
5078 sizeof(struct drm_i915_gem_object
), 0,
5082 INIT_LIST_HEAD(&dev_priv
->vm_list
);
5083 i915_init_vm(dev_priv
, &dev_priv
->gtt
.base
);
5085 INIT_LIST_HEAD(&dev_priv
->context_list
);
5086 INIT_LIST_HEAD(&dev_priv
->mm
.unbound_list
);
5087 INIT_LIST_HEAD(&dev_priv
->mm
.bound_list
);
5088 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
5089 for (i
= 0; i
< I915_NUM_RINGS
; i
++)
5090 init_ring_lists(&dev_priv
->ring
[i
]);
5091 for (i
= 0; i
< I915_MAX_NUM_FENCES
; i
++)
5092 INIT_LIST_HEAD(&dev_priv
->fence_regs
[i
].lru_list
);
5093 INIT_DELAYED_WORK(&dev_priv
->mm
.retire_work
,
5094 i915_gem_retire_work_handler
);
5095 INIT_DELAYED_WORK(&dev_priv
->mm
.idle_work
,
5096 i915_gem_idle_work_handler
);
5097 init_waitqueue_head(&dev_priv
->gpu_error
.reset_queue
);
5099 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
5100 if (!drm_core_check_feature(dev
, DRIVER_MODESET
) && IS_GEN3(dev
)) {
5101 I915_WRITE(MI_ARB_STATE
,
5102 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE
));
5105 dev_priv
->relative_constants_mode
= I915_EXEC_CONSTANTS_REL_GENERAL
;
5107 /* Old X drivers will take 0-2 for front, back, depth buffers */
5108 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
5109 dev_priv
->fence_reg_start
= 3;
5111 if (INTEL_INFO(dev
)->gen
>= 7 && !IS_VALLEYVIEW(dev
))
5112 dev_priv
->num_fence_regs
= 32;
5113 else if (INTEL_INFO(dev
)->gen
>= 4 || IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
5114 dev_priv
->num_fence_regs
= 16;
5116 dev_priv
->num_fence_regs
= 8;
5118 /* Initialize fence registers to zero */
5119 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
5120 i915_gem_restore_fences(dev
);
5122 i915_gem_detect_bit_6_swizzle(dev
);
5123 init_waitqueue_head(&dev_priv
->pending_flip_queue
);
5125 dev_priv
->mm
.interruptible
= true;
5127 dev_priv
->mm
.shrinker
.scan_objects
= i915_gem_shrinker_scan
;
5128 dev_priv
->mm
.shrinker
.count_objects
= i915_gem_shrinker_count
;
5129 dev_priv
->mm
.shrinker
.seeks
= DEFAULT_SEEKS
;
5130 register_shrinker(&dev_priv
->mm
.shrinker
);
5132 dev_priv
->mm
.oom_notifier
.notifier_call
= i915_gem_shrinker_oom
;
5133 register_oom_notifier(&dev_priv
->mm
.oom_notifier
);
5135 mutex_init(&dev_priv
->fb_tracking
.lock
);
5138 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
)
5140 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
5142 cancel_delayed_work_sync(&file_priv
->mm
.idle_work
);
5144 /* Clean up our request list when the client is going away, so that
5145 * later retire_requests won't dereference our soon-to-be-gone
5148 spin_lock(&file_priv
->mm
.lock
);
5149 while (!list_empty(&file_priv
->mm
.request_list
)) {
5150 struct drm_i915_gem_request
*request
;
5152 request
= list_first_entry(&file_priv
->mm
.request_list
,
5153 struct drm_i915_gem_request
,
5155 list_del(&request
->client_list
);
5156 request
->file_priv
= NULL
;
5158 spin_unlock(&file_priv
->mm
.lock
);
5162 i915_gem_file_idle_work_handler(struct work_struct
*work
)
5164 struct drm_i915_file_private
*file_priv
=
5165 container_of(work
, typeof(*file_priv
), mm
.idle_work
.work
);
5167 atomic_set(&file_priv
->rps_wait_boost
, false);
5170 int i915_gem_open(struct drm_device
*dev
, struct drm_file
*file
)
5172 struct drm_i915_file_private
*file_priv
;
5175 DRM_DEBUG_DRIVER("\n");
5177 file_priv
= kzalloc(sizeof(*file_priv
), GFP_KERNEL
);
5181 file
->driver_priv
= file_priv
;
5182 file_priv
->dev_priv
= dev
->dev_private
;
5183 file_priv
->file
= file
;
5185 spin_lock_init(&file_priv
->mm
.lock
);
5186 INIT_LIST_HEAD(&file_priv
->mm
.request_list
);
5187 INIT_DELAYED_WORK(&file_priv
->mm
.idle_work
,
5188 i915_gem_file_idle_work_handler
);
5190 ret
= i915_gem_context_open(dev
, file
);
5198 * i915_gem_track_fb - update frontbuffer tracking
5199 * old: current GEM buffer for the frontbuffer slots
5200 * new: new GEM buffer for the frontbuffer slots
5201 * frontbuffer_bits: bitmask of frontbuffer slots
5203 * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them
5204 * from @old and setting them in @new. Both @old and @new can be NULL.
5206 void i915_gem_track_fb(struct drm_i915_gem_object
*old
,
5207 struct drm_i915_gem_object
*new,
5208 unsigned frontbuffer_bits
)
5211 WARN_ON(!mutex_is_locked(&old
->base
.dev
->struct_mutex
));
5212 WARN_ON(!(old
->frontbuffer_bits
& frontbuffer_bits
));
5213 old
->frontbuffer_bits
&= ~frontbuffer_bits
;
5217 WARN_ON(!mutex_is_locked(&new->base
.dev
->struct_mutex
));
5218 WARN_ON(new->frontbuffer_bits
& frontbuffer_bits
);
5219 new->frontbuffer_bits
|= frontbuffer_bits
;
5223 static bool mutex_is_locked_by(struct mutex
*mutex
, struct task_struct
*task
)
5225 if (!mutex_is_locked(mutex
))
5228 #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES)
5229 return mutex
->owner
== task
;
5231 /* Since UP may be pre-empted, we cannot assume that we own the lock */
5236 static bool i915_gem_shrinker_lock(struct drm_device
*dev
, bool *unlock
)
5238 if (!mutex_trylock(&dev
->struct_mutex
)) {
5239 if (!mutex_is_locked_by(&dev
->struct_mutex
, current
))
5242 if (to_i915(dev
)->mm
.shrinker_no_lock_stealing
)
5252 static int num_vma_bound(struct drm_i915_gem_object
*obj
)
5254 struct i915_vma
*vma
;
5257 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
5258 if (drm_mm_node_allocated(&vma
->node
))
5264 static unsigned long
5265 i915_gem_shrinker_count(struct shrinker
*shrinker
, struct shrink_control
*sc
)
5267 struct drm_i915_private
*dev_priv
=
5268 container_of(shrinker
, struct drm_i915_private
, mm
.shrinker
);
5269 struct drm_device
*dev
= dev_priv
->dev
;
5270 struct drm_i915_gem_object
*obj
;
5271 unsigned long count
;
5274 if (!i915_gem_shrinker_lock(dev
, &unlock
))
5278 list_for_each_entry(obj
, &dev_priv
->mm
.unbound_list
, global_list
)
5279 if (obj
->pages_pin_count
== 0)
5280 count
+= obj
->base
.size
>> PAGE_SHIFT
;
5282 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
5283 if (!i915_gem_obj_is_pinned(obj
) &&
5284 obj
->pages_pin_count
== num_vma_bound(obj
))
5285 count
+= obj
->base
.size
>> PAGE_SHIFT
;
5289 mutex_unlock(&dev
->struct_mutex
);
5294 /* All the new VM stuff */
5295 unsigned long i915_gem_obj_offset(struct drm_i915_gem_object
*o
,
5296 struct i915_address_space
*vm
)
5298 struct drm_i915_private
*dev_priv
= o
->base
.dev
->dev_private
;
5299 struct i915_vma
*vma
;
5301 WARN_ON(vm
== &dev_priv
->mm
.aliasing_ppgtt
->base
);
5303 list_for_each_entry(vma
, &o
->vma_list
, vma_link
) {
5305 return vma
->node
.start
;
5308 WARN(1, "%s vma for this object not found.\n",
5309 i915_is_ggtt(vm
) ? "global" : "ppgtt");
5313 bool i915_gem_obj_bound(struct drm_i915_gem_object
*o
,
5314 struct i915_address_space
*vm
)
5316 struct i915_vma
*vma
;
5318 list_for_each_entry(vma
, &o
->vma_list
, vma_link
)
5319 if (vma
->vm
== vm
&& drm_mm_node_allocated(&vma
->node
))
5325 bool i915_gem_obj_bound_any(struct drm_i915_gem_object
*o
)
5327 struct i915_vma
*vma
;
5329 list_for_each_entry(vma
, &o
->vma_list
, vma_link
)
5330 if (drm_mm_node_allocated(&vma
->node
))
5336 unsigned long i915_gem_obj_size(struct drm_i915_gem_object
*o
,
5337 struct i915_address_space
*vm
)
5339 struct drm_i915_private
*dev_priv
= o
->base
.dev
->dev_private
;
5340 struct i915_vma
*vma
;
5342 WARN_ON(vm
== &dev_priv
->mm
.aliasing_ppgtt
->base
);
5344 BUG_ON(list_empty(&o
->vma_list
));
5346 list_for_each_entry(vma
, &o
->vma_list
, vma_link
)
5348 return vma
->node
.size
;
5353 static unsigned long
5354 i915_gem_shrinker_scan(struct shrinker
*shrinker
, struct shrink_control
*sc
)
5356 struct drm_i915_private
*dev_priv
=
5357 container_of(shrinker
, struct drm_i915_private
, mm
.shrinker
);
5358 struct drm_device
*dev
= dev_priv
->dev
;
5359 unsigned long freed
;
5362 if (!i915_gem_shrinker_lock(dev
, &unlock
))
5365 freed
= i915_gem_shrink(dev_priv
,
5368 I915_SHRINK_UNBOUND
|
5369 I915_SHRINK_PURGEABLE
);
5370 if (freed
< sc
->nr_to_scan
)
5371 freed
+= i915_gem_shrink(dev_priv
,
5372 sc
->nr_to_scan
- freed
,
5374 I915_SHRINK_UNBOUND
);
5376 mutex_unlock(&dev
->struct_mutex
);
5382 i915_gem_shrinker_oom(struct notifier_block
*nb
, unsigned long event
, void *ptr
)
5384 struct drm_i915_private
*dev_priv
=
5385 container_of(nb
, struct drm_i915_private
, mm
.oom_notifier
);
5386 struct drm_device
*dev
= dev_priv
->dev
;
5387 struct drm_i915_gem_object
*obj
;
5388 unsigned long timeout
= msecs_to_jiffies(5000) + 1;
5389 unsigned long pinned
, bound
, unbound
, freed_pages
;
5390 bool was_interruptible
;
5393 while (!i915_gem_shrinker_lock(dev
, &unlock
) && --timeout
) {
5394 schedule_timeout_killable(1);
5395 if (fatal_signal_pending(current
))
5399 pr_err("Unable to purge GPU memory due lock contention.\n");
5403 was_interruptible
= dev_priv
->mm
.interruptible
;
5404 dev_priv
->mm
.interruptible
= false;
5406 freed_pages
= i915_gem_shrink_all(dev_priv
);
5408 dev_priv
->mm
.interruptible
= was_interruptible
;
5410 /* Because we may be allocating inside our own driver, we cannot
5411 * assert that there are no objects with pinned pages that are not
5412 * being pointed to by hardware.
5414 unbound
= bound
= pinned
= 0;
5415 list_for_each_entry(obj
, &dev_priv
->mm
.unbound_list
, global_list
) {
5416 if (!obj
->base
.filp
) /* not backed by a freeable object */
5419 if (obj
->pages_pin_count
)
5420 pinned
+= obj
->base
.size
;
5422 unbound
+= obj
->base
.size
;
5424 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
5425 if (!obj
->base
.filp
)
5428 if (obj
->pages_pin_count
)
5429 pinned
+= obj
->base
.size
;
5431 bound
+= obj
->base
.size
;
5435 mutex_unlock(&dev
->struct_mutex
);
5437 if (freed_pages
|| unbound
|| bound
)
5438 pr_info("Purging GPU memory, %lu bytes freed, %lu bytes still pinned.\n",
5439 freed_pages
<< PAGE_SHIFT
, pinned
);
5440 if (unbound
|| bound
)
5441 pr_err("%lu and %lu bytes still available in the "
5442 "bound and unbound GPU page lists.\n",
5445 *(unsigned long *)ptr
+= freed_pages
;
5449 struct i915_vma
*i915_gem_obj_to_ggtt(struct drm_i915_gem_object
*obj
)
5451 struct i915_vma
*vma
;
5453 vma
= list_first_entry(&obj
->vma_list
, typeof(*vma
), vma_link
);
5454 if (vma
->vm
!= i915_obj_to_ggtt(obj
))