2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/drm_vma_manager.h>
30 #include <drm/i915_drm.h>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/shmem_fs.h>
35 #include <linux/slab.h>
36 #include <linux/swap.h>
37 #include <linux/pci.h>
38 #include <linux/dma-buf.h>
40 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
);
41 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
);
42 static __must_check
int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object
*obj
,
44 bool map_and_fenceable
,
46 static int i915_gem_phys_pwrite(struct drm_device
*dev
,
47 struct drm_i915_gem_object
*obj
,
48 struct drm_i915_gem_pwrite
*args
,
49 struct drm_file
*file
);
51 static void i915_gem_write_fence(struct drm_device
*dev
, int reg
,
52 struct drm_i915_gem_object
*obj
);
53 static void i915_gem_object_update_fence(struct drm_i915_gem_object
*obj
,
54 struct drm_i915_fence_reg
*fence
,
57 static int i915_gem_inactive_shrink(struct shrinker
*shrinker
,
58 struct shrink_control
*sc
);
59 static long i915_gem_purge(struct drm_i915_private
*dev_priv
, long target
);
60 static void i915_gem_shrink_all(struct drm_i915_private
*dev_priv
);
61 static void i915_gem_object_truncate(struct drm_i915_gem_object
*obj
);
63 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object
*obj
)
66 i915_gem_release_mmap(obj
);
68 /* As we do not have an associated fence register, we will force
69 * a tiling change if we ever need to acquire one.
71 obj
->fence_dirty
= false;
72 obj
->fence_reg
= I915_FENCE_REG_NONE
;
75 /* some bookkeeping */
76 static void i915_gem_info_add_obj(struct drm_i915_private
*dev_priv
,
79 dev_priv
->mm
.object_count
++;
80 dev_priv
->mm
.object_memory
+= size
;
83 static void i915_gem_info_remove_obj(struct drm_i915_private
*dev_priv
,
86 dev_priv
->mm
.object_count
--;
87 dev_priv
->mm
.object_memory
-= size
;
91 i915_gem_wait_for_error(struct i915_gpu_error
*error
)
95 #define EXIT_COND (!i915_reset_in_progress(error) || \
96 i915_terminally_wedged(error))
101 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
102 * userspace. If it takes that long something really bad is going on and
103 * we should simply try to bail out and fail as gracefully as possible.
105 ret
= wait_event_interruptible_timeout(error
->reset_queue
,
109 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
111 } else if (ret
< 0) {
119 int i915_mutex_lock_interruptible(struct drm_device
*dev
)
121 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
124 ret
= i915_gem_wait_for_error(&dev_priv
->gpu_error
);
128 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
132 WARN_ON(i915_verify_lists(dev
));
137 i915_gem_object_is_inactive(struct drm_i915_gem_object
*obj
)
139 return i915_gem_obj_ggtt_bound(obj
) && !obj
->active
;
143 i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
144 struct drm_file
*file
)
146 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
147 struct drm_i915_gem_init
*args
= data
;
149 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
152 if (args
->gtt_start
>= args
->gtt_end
||
153 (args
->gtt_end
| args
->gtt_start
) & (PAGE_SIZE
- 1))
156 /* GEM with user mode setting was never supported on ilk and later. */
157 if (INTEL_INFO(dev
)->gen
>= 5)
160 mutex_lock(&dev
->struct_mutex
);
161 i915_gem_setup_global_gtt(dev
, args
->gtt_start
, args
->gtt_end
,
163 dev_priv
->gtt
.mappable_end
= args
->gtt_end
;
164 mutex_unlock(&dev
->struct_mutex
);
170 i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
171 struct drm_file
*file
)
173 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
174 struct drm_i915_gem_get_aperture
*args
= data
;
175 struct drm_i915_gem_object
*obj
;
179 mutex_lock(&dev
->struct_mutex
);
180 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
)
182 pinned
+= i915_gem_obj_ggtt_size(obj
);
183 mutex_unlock(&dev
->struct_mutex
);
185 args
->aper_size
= dev_priv
->gtt
.total
;
186 args
->aper_available_size
= args
->aper_size
- pinned
;
191 void *i915_gem_object_alloc(struct drm_device
*dev
)
193 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
194 return kmem_cache_alloc(dev_priv
->slab
, GFP_KERNEL
| __GFP_ZERO
);
197 void i915_gem_object_free(struct drm_i915_gem_object
*obj
)
199 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
200 kmem_cache_free(dev_priv
->slab
, obj
);
204 i915_gem_create(struct drm_file
*file
,
205 struct drm_device
*dev
,
209 struct drm_i915_gem_object
*obj
;
213 size
= roundup(size
, PAGE_SIZE
);
217 /* Allocate the new object */
218 obj
= i915_gem_alloc_object(dev
, size
);
222 ret
= drm_gem_handle_create(file
, &obj
->base
, &handle
);
224 drm_gem_object_release(&obj
->base
);
225 i915_gem_info_remove_obj(dev
->dev_private
, obj
->base
.size
);
226 i915_gem_object_free(obj
);
230 /* drop reference from allocate - handle holds it now */
231 drm_gem_object_unreference(&obj
->base
);
232 trace_i915_gem_object_create(obj
);
239 i915_gem_dumb_create(struct drm_file
*file
,
240 struct drm_device
*dev
,
241 struct drm_mode_create_dumb
*args
)
243 /* have to work out size/pitch and return them */
244 args
->pitch
= ALIGN(args
->width
* ((args
->bpp
+ 7) / 8), 64);
245 args
->size
= args
->pitch
* args
->height
;
246 return i915_gem_create(file
, dev
,
247 args
->size
, &args
->handle
);
250 int i915_gem_dumb_destroy(struct drm_file
*file
,
251 struct drm_device
*dev
,
254 return drm_gem_handle_delete(file
, handle
);
258 * Creates a new mm object and returns a handle to it.
261 i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
262 struct drm_file
*file
)
264 struct drm_i915_gem_create
*args
= data
;
266 return i915_gem_create(file
, dev
,
267 args
->size
, &args
->handle
);
271 __copy_to_user_swizzled(char __user
*cpu_vaddr
,
272 const char *gpu_vaddr
, int gpu_offset
,
275 int ret
, cpu_offset
= 0;
278 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
279 int this_length
= min(cacheline_end
- gpu_offset
, length
);
280 int swizzled_gpu_offset
= gpu_offset
^ 64;
282 ret
= __copy_to_user(cpu_vaddr
+ cpu_offset
,
283 gpu_vaddr
+ swizzled_gpu_offset
,
288 cpu_offset
+= this_length
;
289 gpu_offset
+= this_length
;
290 length
-= this_length
;
297 __copy_from_user_swizzled(char *gpu_vaddr
, int gpu_offset
,
298 const char __user
*cpu_vaddr
,
301 int ret
, cpu_offset
= 0;
304 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
305 int this_length
= min(cacheline_end
- gpu_offset
, length
);
306 int swizzled_gpu_offset
= gpu_offset
^ 64;
308 ret
= __copy_from_user(gpu_vaddr
+ swizzled_gpu_offset
,
309 cpu_vaddr
+ cpu_offset
,
314 cpu_offset
+= this_length
;
315 gpu_offset
+= this_length
;
316 length
-= this_length
;
322 /* Per-page copy function for the shmem pread fastpath.
323 * Flushes invalid cachelines before reading the target if
324 * needs_clflush is set. */
326 shmem_pread_fast(struct page
*page
, int shmem_page_offset
, int page_length
,
327 char __user
*user_data
,
328 bool page_do_bit17_swizzling
, bool needs_clflush
)
333 if (unlikely(page_do_bit17_swizzling
))
336 vaddr
= kmap_atomic(page
);
338 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
340 ret
= __copy_to_user_inatomic(user_data
,
341 vaddr
+ shmem_page_offset
,
343 kunmap_atomic(vaddr
);
345 return ret
? -EFAULT
: 0;
349 shmem_clflush_swizzled_range(char *addr
, unsigned long length
,
352 if (unlikely(swizzled
)) {
353 unsigned long start
= (unsigned long) addr
;
354 unsigned long end
= (unsigned long) addr
+ length
;
356 /* For swizzling simply ensure that we always flush both
357 * channels. Lame, but simple and it works. Swizzled
358 * pwrite/pread is far from a hotpath - current userspace
359 * doesn't use it at all. */
360 start
= round_down(start
, 128);
361 end
= round_up(end
, 128);
363 drm_clflush_virt_range((void *)start
, end
- start
);
365 drm_clflush_virt_range(addr
, length
);
370 /* Only difference to the fast-path function is that this can handle bit17
371 * and uses non-atomic copy and kmap functions. */
373 shmem_pread_slow(struct page
*page
, int shmem_page_offset
, int page_length
,
374 char __user
*user_data
,
375 bool page_do_bit17_swizzling
, bool needs_clflush
)
382 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
384 page_do_bit17_swizzling
);
386 if (page_do_bit17_swizzling
)
387 ret
= __copy_to_user_swizzled(user_data
,
388 vaddr
, shmem_page_offset
,
391 ret
= __copy_to_user(user_data
,
392 vaddr
+ shmem_page_offset
,
396 return ret
? - EFAULT
: 0;
400 i915_gem_shmem_pread(struct drm_device
*dev
,
401 struct drm_i915_gem_object
*obj
,
402 struct drm_i915_gem_pread
*args
,
403 struct drm_file
*file
)
405 char __user
*user_data
;
408 int shmem_page_offset
, page_length
, ret
= 0;
409 int obj_do_bit17_swizzling
, page_do_bit17_swizzling
;
411 int needs_clflush
= 0;
412 struct sg_page_iter sg_iter
;
414 user_data
= to_user_ptr(args
->data_ptr
);
417 obj_do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
419 if (!(obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
)) {
420 /* If we're not in the cpu read domain, set ourself into the gtt
421 * read domain and manually flush cachelines (if required). This
422 * optimizes for the case when the gpu will dirty the data
423 * anyway again before the next pread happens. */
424 if (obj
->cache_level
== I915_CACHE_NONE
)
426 if (i915_gem_obj_ggtt_bound(obj
)) {
427 ret
= i915_gem_object_set_to_gtt_domain(obj
, false);
433 ret
= i915_gem_object_get_pages(obj
);
437 i915_gem_object_pin_pages(obj
);
439 offset
= args
->offset
;
441 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
,
442 offset
>> PAGE_SHIFT
) {
443 struct page
*page
= sg_page_iter_page(&sg_iter
);
448 /* Operation in this page
450 * shmem_page_offset = offset within page in shmem file
451 * page_length = bytes to copy for this page
453 shmem_page_offset
= offset_in_page(offset
);
454 page_length
= remain
;
455 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
456 page_length
= PAGE_SIZE
- shmem_page_offset
;
458 page_do_bit17_swizzling
= obj_do_bit17_swizzling
&&
459 (page_to_phys(page
) & (1 << 17)) != 0;
461 ret
= shmem_pread_fast(page
, shmem_page_offset
, page_length
,
462 user_data
, page_do_bit17_swizzling
,
467 mutex_unlock(&dev
->struct_mutex
);
470 ret
= fault_in_multipages_writeable(user_data
, remain
);
471 /* Userspace is tricking us, but we've already clobbered
472 * its pages with the prefault and promised to write the
473 * data up to the first fault. Hence ignore any errors
474 * and just continue. */
479 ret
= shmem_pread_slow(page
, shmem_page_offset
, page_length
,
480 user_data
, page_do_bit17_swizzling
,
483 mutex_lock(&dev
->struct_mutex
);
486 mark_page_accessed(page
);
491 remain
-= page_length
;
492 user_data
+= page_length
;
493 offset
+= page_length
;
497 i915_gem_object_unpin_pages(obj
);
503 * Reads data from the object referenced by handle.
505 * On error, the contents of *data are undefined.
508 i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
509 struct drm_file
*file
)
511 struct drm_i915_gem_pread
*args
= data
;
512 struct drm_i915_gem_object
*obj
;
518 if (!access_ok(VERIFY_WRITE
,
519 to_user_ptr(args
->data_ptr
),
523 ret
= i915_mutex_lock_interruptible(dev
);
527 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
528 if (&obj
->base
== NULL
) {
533 /* Bounds check source. */
534 if (args
->offset
> obj
->base
.size
||
535 args
->size
> obj
->base
.size
- args
->offset
) {
540 /* prime objects have no backing filp to GEM pread/pwrite
543 if (!obj
->base
.filp
) {
548 trace_i915_gem_object_pread(obj
, args
->offset
, args
->size
);
550 ret
= i915_gem_shmem_pread(dev
, obj
, args
, file
);
553 drm_gem_object_unreference(&obj
->base
);
555 mutex_unlock(&dev
->struct_mutex
);
559 /* This is the fast write path which cannot handle
560 * page faults in the source data
564 fast_user_write(struct io_mapping
*mapping
,
565 loff_t page_base
, int page_offset
,
566 char __user
*user_data
,
569 void __iomem
*vaddr_atomic
;
571 unsigned long unwritten
;
573 vaddr_atomic
= io_mapping_map_atomic_wc(mapping
, page_base
);
574 /* We can use the cpu mem copy function because this is X86. */
575 vaddr
= (void __force
*)vaddr_atomic
+ page_offset
;
576 unwritten
= __copy_from_user_inatomic_nocache(vaddr
,
578 io_mapping_unmap_atomic(vaddr_atomic
);
583 * This is the fast pwrite path, where we copy the data directly from the
584 * user into the GTT, uncached.
587 i915_gem_gtt_pwrite_fast(struct drm_device
*dev
,
588 struct drm_i915_gem_object
*obj
,
589 struct drm_i915_gem_pwrite
*args
,
590 struct drm_file
*file
)
592 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
594 loff_t offset
, page_base
;
595 char __user
*user_data
;
596 int page_offset
, page_length
, ret
;
598 ret
= i915_gem_object_pin(obj
, 0, true, true);
602 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
606 ret
= i915_gem_object_put_fence(obj
);
610 user_data
= to_user_ptr(args
->data_ptr
);
613 offset
= i915_gem_obj_ggtt_offset(obj
) + args
->offset
;
616 /* Operation in this page
618 * page_base = page offset within aperture
619 * page_offset = offset within page
620 * page_length = bytes to copy for this page
622 page_base
= offset
& PAGE_MASK
;
623 page_offset
= offset_in_page(offset
);
624 page_length
= remain
;
625 if ((page_offset
+ remain
) > PAGE_SIZE
)
626 page_length
= PAGE_SIZE
- page_offset
;
628 /* If we get a fault while copying data, then (presumably) our
629 * source page isn't available. Return the error and we'll
630 * retry in the slow path.
632 if (fast_user_write(dev_priv
->gtt
.mappable
, page_base
,
633 page_offset
, user_data
, page_length
)) {
638 remain
-= page_length
;
639 user_data
+= page_length
;
640 offset
+= page_length
;
644 i915_gem_object_unpin(obj
);
649 /* Per-page copy function for the shmem pwrite fastpath.
650 * Flushes invalid cachelines before writing to the target if
651 * needs_clflush_before is set and flushes out any written cachelines after
652 * writing if needs_clflush is set. */
654 shmem_pwrite_fast(struct page
*page
, int shmem_page_offset
, int page_length
,
655 char __user
*user_data
,
656 bool page_do_bit17_swizzling
,
657 bool needs_clflush_before
,
658 bool needs_clflush_after
)
663 if (unlikely(page_do_bit17_swizzling
))
666 vaddr
= kmap_atomic(page
);
667 if (needs_clflush_before
)
668 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
670 ret
= __copy_from_user_inatomic_nocache(vaddr
+ shmem_page_offset
,
673 if (needs_clflush_after
)
674 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
676 kunmap_atomic(vaddr
);
678 return ret
? -EFAULT
: 0;
681 /* Only difference to the fast-path function is that this can handle bit17
682 * and uses non-atomic copy and kmap functions. */
684 shmem_pwrite_slow(struct page
*page
, int shmem_page_offset
, int page_length
,
685 char __user
*user_data
,
686 bool page_do_bit17_swizzling
,
687 bool needs_clflush_before
,
688 bool needs_clflush_after
)
694 if (unlikely(needs_clflush_before
|| page_do_bit17_swizzling
))
695 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
697 page_do_bit17_swizzling
);
698 if (page_do_bit17_swizzling
)
699 ret
= __copy_from_user_swizzled(vaddr
, shmem_page_offset
,
703 ret
= __copy_from_user(vaddr
+ shmem_page_offset
,
706 if (needs_clflush_after
)
707 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
709 page_do_bit17_swizzling
);
712 return ret
? -EFAULT
: 0;
716 i915_gem_shmem_pwrite(struct drm_device
*dev
,
717 struct drm_i915_gem_object
*obj
,
718 struct drm_i915_gem_pwrite
*args
,
719 struct drm_file
*file
)
723 char __user
*user_data
;
724 int shmem_page_offset
, page_length
, ret
= 0;
725 int obj_do_bit17_swizzling
, page_do_bit17_swizzling
;
726 int hit_slowpath
= 0;
727 int needs_clflush_after
= 0;
728 int needs_clflush_before
= 0;
729 struct sg_page_iter sg_iter
;
731 user_data
= to_user_ptr(args
->data_ptr
);
734 obj_do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
736 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
737 /* If we're not in the cpu write domain, set ourself into the gtt
738 * write domain and manually flush cachelines (if required). This
739 * optimizes for the case when the gpu will use the data
740 * right away and we therefore have to clflush anyway. */
741 if (obj
->cache_level
== I915_CACHE_NONE
)
742 needs_clflush_after
= 1;
743 if (i915_gem_obj_ggtt_bound(obj
)) {
744 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
749 /* Same trick applies for invalidate partially written cachelines before
751 if (!(obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
)
752 && obj
->cache_level
== I915_CACHE_NONE
)
753 needs_clflush_before
= 1;
755 ret
= i915_gem_object_get_pages(obj
);
759 i915_gem_object_pin_pages(obj
);
761 offset
= args
->offset
;
764 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
,
765 offset
>> PAGE_SHIFT
) {
766 struct page
*page
= sg_page_iter_page(&sg_iter
);
767 int partial_cacheline_write
;
772 /* Operation in this page
774 * shmem_page_offset = offset within page in shmem file
775 * page_length = bytes to copy for this page
777 shmem_page_offset
= offset_in_page(offset
);
779 page_length
= remain
;
780 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
781 page_length
= PAGE_SIZE
- shmem_page_offset
;
783 /* If we don't overwrite a cacheline completely we need to be
784 * careful to have up-to-date data by first clflushing. Don't
785 * overcomplicate things and flush the entire patch. */
786 partial_cacheline_write
= needs_clflush_before
&&
787 ((shmem_page_offset
| page_length
)
788 & (boot_cpu_data
.x86_clflush_size
- 1));
790 page_do_bit17_swizzling
= obj_do_bit17_swizzling
&&
791 (page_to_phys(page
) & (1 << 17)) != 0;
793 ret
= shmem_pwrite_fast(page
, shmem_page_offset
, page_length
,
794 user_data
, page_do_bit17_swizzling
,
795 partial_cacheline_write
,
796 needs_clflush_after
);
801 mutex_unlock(&dev
->struct_mutex
);
802 ret
= shmem_pwrite_slow(page
, shmem_page_offset
, page_length
,
803 user_data
, page_do_bit17_swizzling
,
804 partial_cacheline_write
,
805 needs_clflush_after
);
807 mutex_lock(&dev
->struct_mutex
);
810 set_page_dirty(page
);
811 mark_page_accessed(page
);
816 remain
-= page_length
;
817 user_data
+= page_length
;
818 offset
+= page_length
;
822 i915_gem_object_unpin_pages(obj
);
826 * Fixup: Flush cpu caches in case we didn't flush the dirty
827 * cachelines in-line while writing and the object moved
828 * out of the cpu write domain while we've dropped the lock.
830 if (!needs_clflush_after
&&
831 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
832 i915_gem_clflush_object(obj
);
833 i915_gem_chipset_flush(dev
);
837 if (needs_clflush_after
)
838 i915_gem_chipset_flush(dev
);
844 * Writes data to the object referenced by handle.
846 * On error, the contents of the buffer that were to be modified are undefined.
849 i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
850 struct drm_file
*file
)
852 struct drm_i915_gem_pwrite
*args
= data
;
853 struct drm_i915_gem_object
*obj
;
859 if (!access_ok(VERIFY_READ
,
860 to_user_ptr(args
->data_ptr
),
864 ret
= fault_in_multipages_readable(to_user_ptr(args
->data_ptr
),
869 ret
= i915_mutex_lock_interruptible(dev
);
873 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
874 if (&obj
->base
== NULL
) {
879 /* Bounds check destination. */
880 if (args
->offset
> obj
->base
.size
||
881 args
->size
> obj
->base
.size
- args
->offset
) {
886 /* prime objects have no backing filp to GEM pread/pwrite
889 if (!obj
->base
.filp
) {
894 trace_i915_gem_object_pwrite(obj
, args
->offset
, args
->size
);
897 /* We can only do the GTT pwrite on untiled buffers, as otherwise
898 * it would end up going through the fenced access, and we'll get
899 * different detiling behavior between reading and writing.
900 * pread/pwrite currently are reading and writing from the CPU
901 * perspective, requiring manual detiling by the client.
904 ret
= i915_gem_phys_pwrite(dev
, obj
, args
, file
);
908 if (obj
->cache_level
== I915_CACHE_NONE
&&
909 obj
->tiling_mode
== I915_TILING_NONE
&&
910 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
911 ret
= i915_gem_gtt_pwrite_fast(dev
, obj
, args
, file
);
912 /* Note that the gtt paths might fail with non-page-backed user
913 * pointers (e.g. gtt mappings when moving data between
914 * textures). Fallback to the shmem path in that case. */
917 if (ret
== -EFAULT
|| ret
== -ENOSPC
)
918 ret
= i915_gem_shmem_pwrite(dev
, obj
, args
, file
);
921 drm_gem_object_unreference(&obj
->base
);
923 mutex_unlock(&dev
->struct_mutex
);
928 i915_gem_check_wedge(struct i915_gpu_error
*error
,
931 if (i915_reset_in_progress(error
)) {
932 /* Non-interruptible callers can't handle -EAGAIN, hence return
933 * -EIO unconditionally for these. */
937 /* Recovery complete, but the reset failed ... */
938 if (i915_terminally_wedged(error
))
948 * Compare seqno against outstanding lazy request. Emit a request if they are
952 i915_gem_check_olr(struct intel_ring_buffer
*ring
, u32 seqno
)
956 BUG_ON(!mutex_is_locked(&ring
->dev
->struct_mutex
));
959 if (seqno
== ring
->outstanding_lazy_request
)
960 ret
= i915_add_request(ring
, NULL
);
966 * __wait_seqno - wait until execution of seqno has finished
967 * @ring: the ring expected to report seqno
969 * @reset_counter: reset sequence associated with the given seqno
970 * @interruptible: do an interruptible wait (normally yes)
971 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
973 * Note: It is of utmost importance that the passed in seqno and reset_counter
974 * values have been read by the caller in an smp safe manner. Where read-side
975 * locks are involved, it is sufficient to read the reset_counter before
976 * unlocking the lock that protects the seqno. For lockless tricks, the
977 * reset_counter _must_ be read before, and an appropriate smp_rmb must be
980 * Returns 0 if the seqno was found within the alloted time. Else returns the
981 * errno with remaining time filled in timeout argument.
983 static int __wait_seqno(struct intel_ring_buffer
*ring
, u32 seqno
,
984 unsigned reset_counter
,
985 bool interruptible
, struct timespec
*timeout
)
987 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
988 struct timespec before
, now
, wait_time
={1,0};
989 unsigned long timeout_jiffies
;
991 bool wait_forever
= true;
994 if (i915_seqno_passed(ring
->get_seqno(ring
, true), seqno
))
997 trace_i915_gem_request_wait_begin(ring
, seqno
);
999 if (timeout
!= NULL
) {
1000 wait_time
= *timeout
;
1001 wait_forever
= false;
1004 timeout_jiffies
= timespec_to_jiffies_timeout(&wait_time
);
1006 if (WARN_ON(!ring
->irq_get(ring
)))
1009 /* Record current time in case interrupted by signal, or wedged * */
1010 getrawmonotonic(&before
);
1013 (i915_seqno_passed(ring->get_seqno(ring, false), seqno) || \
1014 i915_reset_in_progress(&dev_priv->gpu_error) || \
1015 reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
1018 end
= wait_event_interruptible_timeout(ring
->irq_queue
,
1022 end
= wait_event_timeout(ring
->irq_queue
, EXIT_COND
,
1025 /* We need to check whether any gpu reset happened in between
1026 * the caller grabbing the seqno and now ... */
1027 if (reset_counter
!= atomic_read(&dev_priv
->gpu_error
.reset_counter
))
1030 /* ... but upgrade the -EGAIN to an -EIO if the gpu is truely
1032 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, interruptible
);
1035 } while (end
== 0 && wait_forever
);
1037 getrawmonotonic(&now
);
1039 ring
->irq_put(ring
);
1040 trace_i915_gem_request_wait_end(ring
, seqno
);
1044 struct timespec sleep_time
= timespec_sub(now
, before
);
1045 *timeout
= timespec_sub(*timeout
, sleep_time
);
1046 if (!timespec_valid(timeout
)) /* i.e. negative time remains */
1047 set_normalized_timespec(timeout
, 0, 0);
1052 case -EAGAIN
: /* Wedged */
1053 case -ERESTARTSYS
: /* Signal */
1055 case 0: /* Timeout */
1057 default: /* Completed */
1058 WARN_ON(end
< 0); /* We're not aware of other errors */
1064 * Waits for a sequence number to be signaled, and cleans up the
1065 * request and object lists appropriately for that event.
1068 i915_wait_seqno(struct intel_ring_buffer
*ring
, uint32_t seqno
)
1070 struct drm_device
*dev
= ring
->dev
;
1071 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1072 bool interruptible
= dev_priv
->mm
.interruptible
;
1075 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
1078 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, interruptible
);
1082 ret
= i915_gem_check_olr(ring
, seqno
);
1086 return __wait_seqno(ring
, seqno
,
1087 atomic_read(&dev_priv
->gpu_error
.reset_counter
),
1088 interruptible
, NULL
);
1092 i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object
*obj
,
1093 struct intel_ring_buffer
*ring
)
1095 i915_gem_retire_requests_ring(ring
);
1097 /* Manually manage the write flush as we may have not yet
1098 * retired the buffer.
1100 * Note that the last_write_seqno is always the earlier of
1101 * the two (read/write) seqno, so if we haved successfully waited,
1102 * we know we have passed the last write.
1104 obj
->last_write_seqno
= 0;
1105 obj
->base
.write_domain
&= ~I915_GEM_GPU_DOMAINS
;
1111 * Ensures that all rendering to the object has completed and the object is
1112 * safe to unbind from the GTT or access from the CPU.
1114 static __must_check
int
1115 i915_gem_object_wait_rendering(struct drm_i915_gem_object
*obj
,
1118 struct intel_ring_buffer
*ring
= obj
->ring
;
1122 seqno
= readonly
? obj
->last_write_seqno
: obj
->last_read_seqno
;
1126 ret
= i915_wait_seqno(ring
, seqno
);
1130 return i915_gem_object_wait_rendering__tail(obj
, ring
);
1133 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1134 * as the object state may change during this call.
1136 static __must_check
int
1137 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object
*obj
,
1140 struct drm_device
*dev
= obj
->base
.dev
;
1141 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1142 struct intel_ring_buffer
*ring
= obj
->ring
;
1143 unsigned reset_counter
;
1147 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
1148 BUG_ON(!dev_priv
->mm
.interruptible
);
1150 seqno
= readonly
? obj
->last_write_seqno
: obj
->last_read_seqno
;
1154 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, true);
1158 ret
= i915_gem_check_olr(ring
, seqno
);
1162 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
1163 mutex_unlock(&dev
->struct_mutex
);
1164 ret
= __wait_seqno(ring
, seqno
, reset_counter
, true, NULL
);
1165 mutex_lock(&dev
->struct_mutex
);
1169 return i915_gem_object_wait_rendering__tail(obj
, ring
);
1173 * Called when user space prepares to use an object with the CPU, either
1174 * through the mmap ioctl's mapping or a GTT mapping.
1177 i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
1178 struct drm_file
*file
)
1180 struct drm_i915_gem_set_domain
*args
= data
;
1181 struct drm_i915_gem_object
*obj
;
1182 uint32_t read_domains
= args
->read_domains
;
1183 uint32_t write_domain
= args
->write_domain
;
1186 /* Only handle setting domains to types used by the CPU. */
1187 if (write_domain
& I915_GEM_GPU_DOMAINS
)
1190 if (read_domains
& I915_GEM_GPU_DOMAINS
)
1193 /* Having something in the write domain implies it's in the read
1194 * domain, and only that read domain. Enforce that in the request.
1196 if (write_domain
!= 0 && read_domains
!= write_domain
)
1199 ret
= i915_mutex_lock_interruptible(dev
);
1203 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1204 if (&obj
->base
== NULL
) {
1209 /* Try to flush the object off the GPU without holding the lock.
1210 * We will repeat the flush holding the lock in the normal manner
1211 * to catch cases where we are gazumped.
1213 ret
= i915_gem_object_wait_rendering__nonblocking(obj
, !write_domain
);
1217 if (read_domains
& I915_GEM_DOMAIN_GTT
) {
1218 ret
= i915_gem_object_set_to_gtt_domain(obj
, write_domain
!= 0);
1220 /* Silently promote "you're not bound, there was nothing to do"
1221 * to success, since the client was just asking us to
1222 * make sure everything was done.
1227 ret
= i915_gem_object_set_to_cpu_domain(obj
, write_domain
!= 0);
1231 drm_gem_object_unreference(&obj
->base
);
1233 mutex_unlock(&dev
->struct_mutex
);
1238 * Called when user space has done writes to this buffer
1241 i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1242 struct drm_file
*file
)
1244 struct drm_i915_gem_sw_finish
*args
= data
;
1245 struct drm_i915_gem_object
*obj
;
1248 ret
= i915_mutex_lock_interruptible(dev
);
1252 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1253 if (&obj
->base
== NULL
) {
1258 /* Pinned buffers may be scanout, so flush the cache */
1260 i915_gem_object_flush_cpu_write_domain(obj
);
1262 drm_gem_object_unreference(&obj
->base
);
1264 mutex_unlock(&dev
->struct_mutex
);
1269 * Maps the contents of an object, returning the address it is mapped
1272 * While the mapping holds a reference on the contents of the object, it doesn't
1273 * imply a ref on the object itself.
1276 i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1277 struct drm_file
*file
)
1279 struct drm_i915_gem_mmap
*args
= data
;
1280 struct drm_gem_object
*obj
;
1283 obj
= drm_gem_object_lookup(dev
, file
, args
->handle
);
1287 /* prime objects have no backing filp to GEM mmap
1291 drm_gem_object_unreference_unlocked(obj
);
1295 addr
= vm_mmap(obj
->filp
, 0, args
->size
,
1296 PROT_READ
| PROT_WRITE
, MAP_SHARED
,
1298 drm_gem_object_unreference_unlocked(obj
);
1299 if (IS_ERR((void *)addr
))
1302 args
->addr_ptr
= (uint64_t) addr
;
1308 * i915_gem_fault - fault a page into the GTT
1309 * vma: VMA in question
1312 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1313 * from userspace. The fault handler takes care of binding the object to
1314 * the GTT (if needed), allocating and programming a fence register (again,
1315 * only if needed based on whether the old reg is still valid or the object
1316 * is tiled) and inserting a new PTE into the faulting process.
1318 * Note that the faulting process may involve evicting existing objects
1319 * from the GTT and/or fence registers to make room. So performance may
1320 * suffer if the GTT working set is large or there are few fence registers
1323 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
)
1325 struct drm_i915_gem_object
*obj
= to_intel_bo(vma
->vm_private_data
);
1326 struct drm_device
*dev
= obj
->base
.dev
;
1327 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1328 pgoff_t page_offset
;
1331 bool write
= !!(vmf
->flags
& FAULT_FLAG_WRITE
);
1333 /* We don't use vmf->pgoff since that has the fake offset */
1334 page_offset
= ((unsigned long)vmf
->virtual_address
- vma
->vm_start
) >>
1337 ret
= i915_mutex_lock_interruptible(dev
);
1341 trace_i915_gem_object_fault(obj
, page_offset
, true, write
);
1343 /* Access to snoopable pages through the GTT is incoherent. */
1344 if (obj
->cache_level
!= I915_CACHE_NONE
&& !HAS_LLC(dev
)) {
1349 /* Now bind it into the GTT if needed */
1350 ret
= i915_gem_object_pin(obj
, 0, true, false);
1354 ret
= i915_gem_object_set_to_gtt_domain(obj
, write
);
1358 ret
= i915_gem_object_get_fence(obj
);
1362 obj
->fault_mappable
= true;
1364 pfn
= dev_priv
->gtt
.mappable_base
+ i915_gem_obj_ggtt_offset(obj
);
1368 /* Finally, remap it using the new GTT offset */
1369 ret
= vm_insert_pfn(vma
, (unsigned long)vmf
->virtual_address
, pfn
);
1371 i915_gem_object_unpin(obj
);
1373 mutex_unlock(&dev
->struct_mutex
);
1377 /* If this -EIO is due to a gpu hang, give the reset code a
1378 * chance to clean up the mess. Otherwise return the proper
1380 if (i915_terminally_wedged(&dev_priv
->gpu_error
))
1381 return VM_FAULT_SIGBUS
;
1383 /* Give the error handler a chance to run and move the
1384 * objects off the GPU active list. Next time we service the
1385 * fault, we should be able to transition the page into the
1386 * GTT without touching the GPU (and so avoid further
1387 * EIO/EGAIN). If the GPU is wedged, then there is no issue
1388 * with coherency, just lost writes.
1396 * EBUSY is ok: this just means that another thread
1397 * already did the job.
1399 return VM_FAULT_NOPAGE
;
1401 return VM_FAULT_OOM
;
1403 return VM_FAULT_SIGBUS
;
1405 WARN_ONCE(ret
, "unhandled error in i915_gem_fault: %i\n", ret
);
1406 return VM_FAULT_SIGBUS
;
1411 * i915_gem_release_mmap - remove physical page mappings
1412 * @obj: obj in question
1414 * Preserve the reservation of the mmapping with the DRM core code, but
1415 * relinquish ownership of the pages back to the system.
1417 * It is vital that we remove the page mapping if we have mapped a tiled
1418 * object through the GTT and then lose the fence register due to
1419 * resource pressure. Similarly if the object has been moved out of the
1420 * aperture, than pages mapped into userspace must be revoked. Removing the
1421 * mapping will then trigger a page fault on the next user access, allowing
1422 * fixup by i915_gem_fault().
1425 i915_gem_release_mmap(struct drm_i915_gem_object
*obj
)
1427 if (!obj
->fault_mappable
)
1430 drm_vma_node_unmap(&obj
->base
.vma_node
, obj
->base
.dev
->dev_mapping
);
1431 obj
->fault_mappable
= false;
1435 i915_gem_get_gtt_size(struct drm_device
*dev
, uint32_t size
, int tiling_mode
)
1439 if (INTEL_INFO(dev
)->gen
>= 4 ||
1440 tiling_mode
== I915_TILING_NONE
)
1443 /* Previous chips need a power-of-two fence region when tiling */
1444 if (INTEL_INFO(dev
)->gen
== 3)
1445 gtt_size
= 1024*1024;
1447 gtt_size
= 512*1024;
1449 while (gtt_size
< size
)
1456 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1457 * @obj: object to check
1459 * Return the required GTT alignment for an object, taking into account
1460 * potential fence register mapping.
1463 i915_gem_get_gtt_alignment(struct drm_device
*dev
, uint32_t size
,
1464 int tiling_mode
, bool fenced
)
1467 * Minimum alignment is 4k (GTT page size), but might be greater
1468 * if a fence register is needed for the object.
1470 if (INTEL_INFO(dev
)->gen
>= 4 || (!fenced
&& IS_G33(dev
)) ||
1471 tiling_mode
== I915_TILING_NONE
)
1475 * Previous chips need to be aligned to the size of the smallest
1476 * fence register that can contain the object.
1478 return i915_gem_get_gtt_size(dev
, size
, tiling_mode
);
1481 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object
*obj
)
1483 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
1486 if (drm_vma_node_has_offset(&obj
->base
.vma_node
))
1489 dev_priv
->mm
.shrinker_no_lock_stealing
= true;
1491 ret
= drm_gem_create_mmap_offset(&obj
->base
);
1495 /* Badly fragmented mmap space? The only way we can recover
1496 * space is by destroying unwanted objects. We can't randomly release
1497 * mmap_offsets as userspace expects them to be persistent for the
1498 * lifetime of the objects. The closest we can is to release the
1499 * offsets on purgeable objects by truncating it and marking it purged,
1500 * which prevents userspace from ever using that object again.
1502 i915_gem_purge(dev_priv
, obj
->base
.size
>> PAGE_SHIFT
);
1503 ret
= drm_gem_create_mmap_offset(&obj
->base
);
1507 i915_gem_shrink_all(dev_priv
);
1508 ret
= drm_gem_create_mmap_offset(&obj
->base
);
1510 dev_priv
->mm
.shrinker_no_lock_stealing
= false;
1515 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object
*obj
)
1517 drm_gem_free_mmap_offset(&obj
->base
);
1521 i915_gem_mmap_gtt(struct drm_file
*file
,
1522 struct drm_device
*dev
,
1526 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1527 struct drm_i915_gem_object
*obj
;
1530 ret
= i915_mutex_lock_interruptible(dev
);
1534 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, handle
));
1535 if (&obj
->base
== NULL
) {
1540 if (obj
->base
.size
> dev_priv
->gtt
.mappable_end
) {
1545 if (obj
->madv
!= I915_MADV_WILLNEED
) {
1546 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1551 ret
= i915_gem_object_create_mmap_offset(obj
);
1555 *offset
= drm_vma_node_offset_addr(&obj
->base
.vma_node
);
1558 drm_gem_object_unreference(&obj
->base
);
1560 mutex_unlock(&dev
->struct_mutex
);
1565 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1567 * @data: GTT mapping ioctl data
1568 * @file: GEM object info
1570 * Simply returns the fake offset to userspace so it can mmap it.
1571 * The mmap call will end up in drm_gem_mmap(), which will set things
1572 * up so we can get faults in the handler above.
1574 * The fault handler will take care of binding the object into the GTT
1575 * (since it may have been evicted to make room for something), allocating
1576 * a fence register, and mapping the appropriate aperture address into
1580 i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
1581 struct drm_file
*file
)
1583 struct drm_i915_gem_mmap_gtt
*args
= data
;
1585 return i915_gem_mmap_gtt(file
, dev
, args
->handle
, &args
->offset
);
1588 /* Immediately discard the backing storage */
1590 i915_gem_object_truncate(struct drm_i915_gem_object
*obj
)
1592 struct inode
*inode
;
1594 i915_gem_object_free_mmap_offset(obj
);
1596 if (obj
->base
.filp
== NULL
)
1599 /* Our goal here is to return as much of the memory as
1600 * is possible back to the system as we are called from OOM.
1601 * To do this we must instruct the shmfs to drop all of its
1602 * backing pages, *now*.
1604 inode
= file_inode(obj
->base
.filp
);
1605 shmem_truncate_range(inode
, 0, (loff_t
)-1);
1607 obj
->madv
= __I915_MADV_PURGED
;
1611 i915_gem_object_is_purgeable(struct drm_i915_gem_object
*obj
)
1613 return obj
->madv
== I915_MADV_DONTNEED
;
1617 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object
*obj
)
1619 struct sg_page_iter sg_iter
;
1622 BUG_ON(obj
->madv
== __I915_MADV_PURGED
);
1624 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
1626 /* In the event of a disaster, abandon all caches and
1627 * hope for the best.
1629 WARN_ON(ret
!= -EIO
);
1630 i915_gem_clflush_object(obj
);
1631 obj
->base
.read_domains
= obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
1634 if (i915_gem_object_needs_bit17_swizzle(obj
))
1635 i915_gem_object_save_bit_17_swizzle(obj
);
1637 if (obj
->madv
== I915_MADV_DONTNEED
)
1640 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
, 0) {
1641 struct page
*page
= sg_page_iter_page(&sg_iter
);
1644 set_page_dirty(page
);
1646 if (obj
->madv
== I915_MADV_WILLNEED
)
1647 mark_page_accessed(page
);
1649 page_cache_release(page
);
1653 sg_free_table(obj
->pages
);
1658 i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
)
1660 const struct drm_i915_gem_object_ops
*ops
= obj
->ops
;
1662 if (obj
->pages
== NULL
)
1665 BUG_ON(i915_gem_obj_ggtt_bound(obj
));
1667 if (obj
->pages_pin_count
)
1670 /* ->put_pages might need to allocate memory for the bit17 swizzle
1671 * array, hence protect them from being reaped by removing them from gtt
1673 list_del(&obj
->global_list
);
1675 ops
->put_pages(obj
);
1678 if (i915_gem_object_is_purgeable(obj
))
1679 i915_gem_object_truncate(obj
);
1685 __i915_gem_shrink(struct drm_i915_private
*dev_priv
, long target
,
1686 bool purgeable_only
)
1688 struct drm_i915_gem_object
*obj
, *next
;
1691 list_for_each_entry_safe(obj
, next
,
1692 &dev_priv
->mm
.unbound_list
,
1694 if ((i915_gem_object_is_purgeable(obj
) || !purgeable_only
) &&
1695 i915_gem_object_put_pages(obj
) == 0) {
1696 count
+= obj
->base
.size
>> PAGE_SHIFT
;
1697 if (count
>= target
)
1702 list_for_each_entry_safe(obj
, next
,
1703 &dev_priv
->mm
.inactive_list
,
1705 if ((i915_gem_object_is_purgeable(obj
) || !purgeable_only
) &&
1706 i915_gem_object_unbind(obj
) == 0 &&
1707 i915_gem_object_put_pages(obj
) == 0) {
1708 count
+= obj
->base
.size
>> PAGE_SHIFT
;
1709 if (count
>= target
)
1718 i915_gem_purge(struct drm_i915_private
*dev_priv
, long target
)
1720 return __i915_gem_shrink(dev_priv
, target
, true);
1724 i915_gem_shrink_all(struct drm_i915_private
*dev_priv
)
1726 struct drm_i915_gem_object
*obj
, *next
;
1728 i915_gem_evict_everything(dev_priv
->dev
);
1730 list_for_each_entry_safe(obj
, next
, &dev_priv
->mm
.unbound_list
,
1732 i915_gem_object_put_pages(obj
);
1736 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object
*obj
)
1738 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
1740 struct address_space
*mapping
;
1741 struct sg_table
*st
;
1742 struct scatterlist
*sg
;
1743 struct sg_page_iter sg_iter
;
1745 unsigned long last_pfn
= 0; /* suppress gcc warning */
1748 /* Assert that the object is not currently in any GPU domain. As it
1749 * wasn't in the GTT, there shouldn't be any way it could have been in
1752 BUG_ON(obj
->base
.read_domains
& I915_GEM_GPU_DOMAINS
);
1753 BUG_ON(obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
);
1755 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
1759 page_count
= obj
->base
.size
/ PAGE_SIZE
;
1760 if (sg_alloc_table(st
, page_count
, GFP_KERNEL
)) {
1766 /* Get the list of pages out of our struct file. They'll be pinned
1767 * at this point until we release them.
1769 * Fail silently without starting the shrinker
1771 mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
1772 gfp
= mapping_gfp_mask(mapping
);
1773 gfp
|= __GFP_NORETRY
| __GFP_NOWARN
| __GFP_NO_KSWAPD
;
1774 gfp
&= ~(__GFP_IO
| __GFP_WAIT
);
1777 for (i
= 0; i
< page_count
; i
++) {
1778 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
1780 i915_gem_purge(dev_priv
, page_count
);
1781 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
1784 /* We've tried hard to allocate the memory by reaping
1785 * our own buffer, now let the real VM do its job and
1786 * go down in flames if truly OOM.
1788 gfp
&= ~(__GFP_NORETRY
| __GFP_NOWARN
| __GFP_NO_KSWAPD
);
1789 gfp
|= __GFP_IO
| __GFP_WAIT
;
1791 i915_gem_shrink_all(dev_priv
);
1792 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
1796 gfp
|= __GFP_NORETRY
| __GFP_NOWARN
| __GFP_NO_KSWAPD
;
1797 gfp
&= ~(__GFP_IO
| __GFP_WAIT
);
1799 #ifdef CONFIG_SWIOTLB
1800 if (swiotlb_nr_tbl()) {
1802 sg_set_page(sg
, page
, PAGE_SIZE
, 0);
1807 if (!i
|| page_to_pfn(page
) != last_pfn
+ 1) {
1811 sg_set_page(sg
, page
, PAGE_SIZE
, 0);
1813 sg
->length
+= PAGE_SIZE
;
1815 last_pfn
= page_to_pfn(page
);
1817 #ifdef CONFIG_SWIOTLB
1818 if (!swiotlb_nr_tbl())
1823 if (i915_gem_object_needs_bit17_swizzle(obj
))
1824 i915_gem_object_do_bit_17_swizzle(obj
);
1830 for_each_sg_page(st
->sgl
, &sg_iter
, st
->nents
, 0)
1831 page_cache_release(sg_page_iter_page(&sg_iter
));
1834 return PTR_ERR(page
);
1837 /* Ensure that the associated pages are gathered from the backing storage
1838 * and pinned into our object. i915_gem_object_get_pages() may be called
1839 * multiple times before they are released by a single call to
1840 * i915_gem_object_put_pages() - once the pages are no longer referenced
1841 * either as a result of memory pressure (reaping pages under the shrinker)
1842 * or as the object is itself released.
1845 i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
)
1847 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
1848 const struct drm_i915_gem_object_ops
*ops
= obj
->ops
;
1854 if (obj
->madv
!= I915_MADV_WILLNEED
) {
1855 DRM_ERROR("Attempting to obtain a purgeable object\n");
1859 BUG_ON(obj
->pages_pin_count
);
1861 ret
= ops
->get_pages(obj
);
1865 list_add_tail(&obj
->global_list
, &dev_priv
->mm
.unbound_list
);
1870 i915_gem_object_move_to_active(struct drm_i915_gem_object
*obj
,
1871 struct intel_ring_buffer
*ring
)
1873 struct drm_device
*dev
= obj
->base
.dev
;
1874 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1875 u32 seqno
= intel_ring_get_seqno(ring
);
1877 BUG_ON(ring
== NULL
);
1878 if (obj
->ring
!= ring
&& obj
->last_write_seqno
) {
1879 /* Keep the seqno relative to the current ring */
1880 obj
->last_write_seqno
= seqno
;
1884 /* Add a reference if we're newly entering the active list. */
1886 drm_gem_object_reference(&obj
->base
);
1890 /* Move from whatever list we were on to the tail of execution. */
1891 list_move_tail(&obj
->mm_list
, &dev_priv
->mm
.active_list
);
1892 list_move_tail(&obj
->ring_list
, &ring
->active_list
);
1894 obj
->last_read_seqno
= seqno
;
1896 if (obj
->fenced_gpu_access
) {
1897 obj
->last_fenced_seqno
= seqno
;
1899 /* Bump MRU to take account of the delayed flush */
1900 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
1901 struct drm_i915_fence_reg
*reg
;
1903 reg
= &dev_priv
->fence_regs
[obj
->fence_reg
];
1904 list_move_tail(®
->lru_list
,
1905 &dev_priv
->mm
.fence_list
);
1911 i915_gem_object_move_to_inactive(struct drm_i915_gem_object
*obj
)
1913 struct drm_device
*dev
= obj
->base
.dev
;
1914 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1916 BUG_ON(obj
->base
.write_domain
& ~I915_GEM_GPU_DOMAINS
);
1917 BUG_ON(!obj
->active
);
1919 list_move_tail(&obj
->mm_list
, &dev_priv
->mm
.inactive_list
);
1921 list_del_init(&obj
->ring_list
);
1924 obj
->last_read_seqno
= 0;
1925 obj
->last_write_seqno
= 0;
1926 obj
->base
.write_domain
= 0;
1928 obj
->last_fenced_seqno
= 0;
1929 obj
->fenced_gpu_access
= false;
1932 drm_gem_object_unreference(&obj
->base
);
1934 WARN_ON(i915_verify_lists(dev
));
1938 i915_gem_init_seqno(struct drm_device
*dev
, u32 seqno
)
1940 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1941 struct intel_ring_buffer
*ring
;
1944 /* Carefully retire all requests without writing to the rings */
1945 for_each_ring(ring
, dev_priv
, i
) {
1946 ret
= intel_ring_idle(ring
);
1950 i915_gem_retire_requests(dev
);
1952 /* Finally reset hw state */
1953 for_each_ring(ring
, dev_priv
, i
) {
1954 intel_ring_init_seqno(ring
, seqno
);
1956 for (j
= 0; j
< ARRAY_SIZE(ring
->sync_seqno
); j
++)
1957 ring
->sync_seqno
[j
] = 0;
1963 int i915_gem_set_seqno(struct drm_device
*dev
, u32 seqno
)
1965 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1971 /* HWS page needs to be set less than what we
1972 * will inject to ring
1974 ret
= i915_gem_init_seqno(dev
, seqno
- 1);
1978 /* Carefully set the last_seqno value so that wrap
1979 * detection still works
1981 dev_priv
->next_seqno
= seqno
;
1982 dev_priv
->last_seqno
= seqno
- 1;
1983 if (dev_priv
->last_seqno
== 0)
1984 dev_priv
->last_seqno
--;
1990 i915_gem_get_seqno(struct drm_device
*dev
, u32
*seqno
)
1992 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1994 /* reserve 0 for non-seqno */
1995 if (dev_priv
->next_seqno
== 0) {
1996 int ret
= i915_gem_init_seqno(dev
, 0);
2000 dev_priv
->next_seqno
= 1;
2003 *seqno
= dev_priv
->last_seqno
= dev_priv
->next_seqno
++;
2007 int __i915_add_request(struct intel_ring_buffer
*ring
,
2008 struct drm_file
*file
,
2009 struct drm_i915_gem_object
*obj
,
2012 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
2013 struct drm_i915_gem_request
*request
;
2014 u32 request_ring_position
, request_start
;
2018 request_start
= intel_ring_get_tail(ring
);
2020 * Emit any outstanding flushes - execbuf can fail to emit the flush
2021 * after having emitted the batchbuffer command. Hence we need to fix
2022 * things up similar to emitting the lazy request. The difference here
2023 * is that the flush _must_ happen before the next request, no matter
2026 ret
= intel_ring_flush_all_caches(ring
);
2030 request
= kmalloc(sizeof(*request
), GFP_KERNEL
);
2031 if (request
== NULL
)
2035 /* Record the position of the start of the request so that
2036 * should we detect the updated seqno part-way through the
2037 * GPU processing the request, we never over-estimate the
2038 * position of the head.
2040 request_ring_position
= intel_ring_get_tail(ring
);
2042 ret
= ring
->add_request(ring
);
2048 request
->seqno
= intel_ring_get_seqno(ring
);
2049 request
->ring
= ring
;
2050 request
->head
= request_start
;
2051 request
->tail
= request_ring_position
;
2052 request
->ctx
= ring
->last_context
;
2053 request
->batch_obj
= obj
;
2055 /* Whilst this request exists, batch_obj will be on the
2056 * active_list, and so will hold the active reference. Only when this
2057 * request is retired will the the batch_obj be moved onto the
2058 * inactive_list and lose its active reference. Hence we do not need
2059 * to explicitly hold another reference here.
2063 i915_gem_context_reference(request
->ctx
);
2065 request
->emitted_jiffies
= jiffies
;
2066 was_empty
= list_empty(&ring
->request_list
);
2067 list_add_tail(&request
->list
, &ring
->request_list
);
2068 request
->file_priv
= NULL
;
2071 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
2073 spin_lock(&file_priv
->mm
.lock
);
2074 request
->file_priv
= file_priv
;
2075 list_add_tail(&request
->client_list
,
2076 &file_priv
->mm
.request_list
);
2077 spin_unlock(&file_priv
->mm
.lock
);
2080 trace_i915_gem_request_add(ring
, request
->seqno
);
2081 ring
->outstanding_lazy_request
= 0;
2083 if (!dev_priv
->ums
.mm_suspended
) {
2084 if (i915_enable_hangcheck
) {
2085 mod_timer(&dev_priv
->gpu_error
.hangcheck_timer
,
2086 round_jiffies_up(jiffies
+ DRM_I915_HANGCHECK_JIFFIES
));
2089 queue_delayed_work(dev_priv
->wq
,
2090 &dev_priv
->mm
.retire_work
,
2091 round_jiffies_up_relative(HZ
));
2092 intel_mark_busy(dev_priv
->dev
);
2097 *out_seqno
= request
->seqno
;
2102 i915_gem_request_remove_from_client(struct drm_i915_gem_request
*request
)
2104 struct drm_i915_file_private
*file_priv
= request
->file_priv
;
2109 spin_lock(&file_priv
->mm
.lock
);
2110 if (request
->file_priv
) {
2111 list_del(&request
->client_list
);
2112 request
->file_priv
= NULL
;
2114 spin_unlock(&file_priv
->mm
.lock
);
2117 static bool i915_head_inside_object(u32 acthd
, struct drm_i915_gem_object
*obj
)
2119 if (acthd
>= i915_gem_obj_ggtt_offset(obj
) &&
2120 acthd
< i915_gem_obj_ggtt_offset(obj
) + obj
->base
.size
)
2126 static bool i915_head_inside_request(const u32 acthd_unmasked
,
2127 const u32 request_start
,
2128 const u32 request_end
)
2130 const u32 acthd
= acthd_unmasked
& HEAD_ADDR
;
2132 if (request_start
< request_end
) {
2133 if (acthd
>= request_start
&& acthd
< request_end
)
2135 } else if (request_start
> request_end
) {
2136 if (acthd
>= request_start
|| acthd
< request_end
)
2143 static bool i915_request_guilty(struct drm_i915_gem_request
*request
,
2144 const u32 acthd
, bool *inside
)
2146 /* There is a possibility that unmasked head address
2147 * pointing inside the ring, matches the batch_obj address range.
2148 * However this is extremely unlikely.
2151 if (request
->batch_obj
) {
2152 if (i915_head_inside_object(acthd
, request
->batch_obj
)) {
2158 if (i915_head_inside_request(acthd
, request
->head
, request
->tail
)) {
2166 static void i915_set_reset_status(struct intel_ring_buffer
*ring
,
2167 struct drm_i915_gem_request
*request
,
2170 struct i915_ctx_hang_stats
*hs
= NULL
;
2171 bool inside
, guilty
;
2173 /* Innocent until proven guilty */
2176 if (ring
->hangcheck
.action
!= wait
&&
2177 i915_request_guilty(request
, acthd
, &inside
)) {
2178 DRM_ERROR("%s hung %s bo (0x%lx ctx %d) at 0x%x\n",
2180 inside
? "inside" : "flushing",
2181 request
->batch_obj
?
2182 i915_gem_obj_ggtt_offset(request
->batch_obj
) : 0,
2183 request
->ctx
? request
->ctx
->id
: 0,
2189 /* If contexts are disabled or this is the default context, use
2190 * file_priv->reset_state
2192 if (request
->ctx
&& request
->ctx
->id
!= DEFAULT_CONTEXT_ID
)
2193 hs
= &request
->ctx
->hang_stats
;
2194 else if (request
->file_priv
)
2195 hs
= &request
->file_priv
->hang_stats
;
2201 hs
->batch_pending
++;
2205 static void i915_gem_free_request(struct drm_i915_gem_request
*request
)
2207 list_del(&request
->list
);
2208 i915_gem_request_remove_from_client(request
);
2211 i915_gem_context_unreference(request
->ctx
);
2216 static void i915_gem_reset_ring_lists(struct drm_i915_private
*dev_priv
,
2217 struct intel_ring_buffer
*ring
)
2219 u32 completed_seqno
;
2222 acthd
= intel_ring_get_active_head(ring
);
2223 completed_seqno
= ring
->get_seqno(ring
, false);
2225 while (!list_empty(&ring
->request_list
)) {
2226 struct drm_i915_gem_request
*request
;
2228 request
= list_first_entry(&ring
->request_list
,
2229 struct drm_i915_gem_request
,
2232 if (request
->seqno
> completed_seqno
)
2233 i915_set_reset_status(ring
, request
, acthd
);
2235 i915_gem_free_request(request
);
2238 while (!list_empty(&ring
->active_list
)) {
2239 struct drm_i915_gem_object
*obj
;
2241 obj
= list_first_entry(&ring
->active_list
,
2242 struct drm_i915_gem_object
,
2245 i915_gem_object_move_to_inactive(obj
);
2249 void i915_gem_restore_fences(struct drm_device
*dev
)
2251 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2254 for (i
= 0; i
< dev_priv
->num_fence_regs
; i
++) {
2255 struct drm_i915_fence_reg
*reg
= &dev_priv
->fence_regs
[i
];
2256 i915_gem_write_fence(dev
, i
, reg
->obj
);
2260 void i915_gem_reset(struct drm_device
*dev
)
2262 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2263 struct drm_i915_gem_object
*obj
;
2264 struct intel_ring_buffer
*ring
;
2267 for_each_ring(ring
, dev_priv
, i
)
2268 i915_gem_reset_ring_lists(dev_priv
, ring
);
2270 /* Move everything out of the GPU domains to ensure we do any
2271 * necessary invalidation upon reuse.
2273 list_for_each_entry(obj
,
2274 &dev_priv
->mm
.inactive_list
,
2277 obj
->base
.read_domains
&= ~I915_GEM_GPU_DOMAINS
;
2280 i915_gem_restore_fences(dev
);
2284 * This function clears the request list as sequence numbers are passed.
2287 i915_gem_retire_requests_ring(struct intel_ring_buffer
*ring
)
2291 if (list_empty(&ring
->request_list
))
2294 WARN_ON(i915_verify_lists(ring
->dev
));
2296 seqno
= ring
->get_seqno(ring
, true);
2298 while (!list_empty(&ring
->request_list
)) {
2299 struct drm_i915_gem_request
*request
;
2301 request
= list_first_entry(&ring
->request_list
,
2302 struct drm_i915_gem_request
,
2305 if (!i915_seqno_passed(seqno
, request
->seqno
))
2308 trace_i915_gem_request_retire(ring
, request
->seqno
);
2309 /* We know the GPU must have read the request to have
2310 * sent us the seqno + interrupt, so use the position
2311 * of tail of the request to update the last known position
2314 ring
->last_retired_head
= request
->tail
;
2316 i915_gem_free_request(request
);
2319 /* Move any buffers on the active list that are no longer referenced
2320 * by the ringbuffer to the flushing/inactive lists as appropriate.
2322 while (!list_empty(&ring
->active_list
)) {
2323 struct drm_i915_gem_object
*obj
;
2325 obj
= list_first_entry(&ring
->active_list
,
2326 struct drm_i915_gem_object
,
2329 if (!i915_seqno_passed(seqno
, obj
->last_read_seqno
))
2332 i915_gem_object_move_to_inactive(obj
);
2335 if (unlikely(ring
->trace_irq_seqno
&&
2336 i915_seqno_passed(seqno
, ring
->trace_irq_seqno
))) {
2337 ring
->irq_put(ring
);
2338 ring
->trace_irq_seqno
= 0;
2341 WARN_ON(i915_verify_lists(ring
->dev
));
2345 i915_gem_retire_requests(struct drm_device
*dev
)
2347 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2348 struct intel_ring_buffer
*ring
;
2351 for_each_ring(ring
, dev_priv
, i
)
2352 i915_gem_retire_requests_ring(ring
);
2356 i915_gem_retire_work_handler(struct work_struct
*work
)
2358 drm_i915_private_t
*dev_priv
;
2359 struct drm_device
*dev
;
2360 struct intel_ring_buffer
*ring
;
2364 dev_priv
= container_of(work
, drm_i915_private_t
,
2365 mm
.retire_work
.work
);
2366 dev
= dev_priv
->dev
;
2368 /* Come back later if the device is busy... */
2369 if (!mutex_trylock(&dev
->struct_mutex
)) {
2370 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
,
2371 round_jiffies_up_relative(HZ
));
2375 i915_gem_retire_requests(dev
);
2377 /* Send a periodic flush down the ring so we don't hold onto GEM
2378 * objects indefinitely.
2381 for_each_ring(ring
, dev_priv
, i
) {
2382 if (ring
->gpu_caches_dirty
)
2383 i915_add_request(ring
, NULL
);
2385 idle
&= list_empty(&ring
->request_list
);
2388 if (!dev_priv
->ums
.mm_suspended
&& !idle
)
2389 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
,
2390 round_jiffies_up_relative(HZ
));
2392 intel_mark_idle(dev
);
2394 mutex_unlock(&dev
->struct_mutex
);
2398 * Ensures that an object will eventually get non-busy by flushing any required
2399 * write domains, emitting any outstanding lazy request and retiring and
2400 * completed requests.
2403 i915_gem_object_flush_active(struct drm_i915_gem_object
*obj
)
2408 ret
= i915_gem_check_olr(obj
->ring
, obj
->last_read_seqno
);
2412 i915_gem_retire_requests_ring(obj
->ring
);
2419 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2420 * @DRM_IOCTL_ARGS: standard ioctl arguments
2422 * Returns 0 if successful, else an error is returned with the remaining time in
2423 * the timeout parameter.
2424 * -ETIME: object is still busy after timeout
2425 * -ERESTARTSYS: signal interrupted the wait
2426 * -ENONENT: object doesn't exist
2427 * Also possible, but rare:
2428 * -EAGAIN: GPU wedged
2430 * -ENODEV: Internal IRQ fail
2431 * -E?: The add request failed
2433 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2434 * non-zero timeout parameter the wait ioctl will wait for the given number of
2435 * nanoseconds on an object becoming unbusy. Since the wait itself does so
2436 * without holding struct_mutex the object may become re-busied before this
2437 * function completes. A similar but shorter * race condition exists in the busy
2441 i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
, struct drm_file
*file
)
2443 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2444 struct drm_i915_gem_wait
*args
= data
;
2445 struct drm_i915_gem_object
*obj
;
2446 struct intel_ring_buffer
*ring
= NULL
;
2447 struct timespec timeout_stack
, *timeout
= NULL
;
2448 unsigned reset_counter
;
2452 if (args
->timeout_ns
>= 0) {
2453 timeout_stack
= ns_to_timespec(args
->timeout_ns
);
2454 timeout
= &timeout_stack
;
2457 ret
= i915_mutex_lock_interruptible(dev
);
2461 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->bo_handle
));
2462 if (&obj
->base
== NULL
) {
2463 mutex_unlock(&dev
->struct_mutex
);
2467 /* Need to make sure the object gets inactive eventually. */
2468 ret
= i915_gem_object_flush_active(obj
);
2473 seqno
= obj
->last_read_seqno
;
2480 /* Do this after OLR check to make sure we make forward progress polling
2481 * on this IOCTL with a 0 timeout (like busy ioctl)
2483 if (!args
->timeout_ns
) {
2488 drm_gem_object_unreference(&obj
->base
);
2489 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
2490 mutex_unlock(&dev
->struct_mutex
);
2492 ret
= __wait_seqno(ring
, seqno
, reset_counter
, true, timeout
);
2494 args
->timeout_ns
= timespec_to_ns(timeout
);
2498 drm_gem_object_unreference(&obj
->base
);
2499 mutex_unlock(&dev
->struct_mutex
);
2504 * i915_gem_object_sync - sync an object to a ring.
2506 * @obj: object which may be in use on another ring.
2507 * @to: ring we wish to use the object on. May be NULL.
2509 * This code is meant to abstract object synchronization with the GPU.
2510 * Calling with NULL implies synchronizing the object with the CPU
2511 * rather than a particular GPU ring.
2513 * Returns 0 if successful, else propagates up the lower layer error.
2516 i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
2517 struct intel_ring_buffer
*to
)
2519 struct intel_ring_buffer
*from
= obj
->ring
;
2523 if (from
== NULL
|| to
== from
)
2526 if (to
== NULL
|| !i915_semaphore_is_enabled(obj
->base
.dev
))
2527 return i915_gem_object_wait_rendering(obj
, false);
2529 idx
= intel_ring_sync_index(from
, to
);
2531 seqno
= obj
->last_read_seqno
;
2532 if (seqno
<= from
->sync_seqno
[idx
])
2535 ret
= i915_gem_check_olr(obj
->ring
, seqno
);
2539 ret
= to
->sync_to(to
, from
, seqno
);
2541 /* We use last_read_seqno because sync_to()
2542 * might have just caused seqno wrap under
2545 from
->sync_seqno
[idx
] = obj
->last_read_seqno
;
2550 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object
*obj
)
2552 u32 old_write_domain
, old_read_domains
;
2554 /* Force a pagefault for domain tracking on next user access */
2555 i915_gem_release_mmap(obj
);
2557 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
) == 0)
2560 /* Wait for any direct GTT access to complete */
2563 old_read_domains
= obj
->base
.read_domains
;
2564 old_write_domain
= obj
->base
.write_domain
;
2566 obj
->base
.read_domains
&= ~I915_GEM_DOMAIN_GTT
;
2567 obj
->base
.write_domain
&= ~I915_GEM_DOMAIN_GTT
;
2569 trace_i915_gem_object_change_domain(obj
,
2575 * Unbinds an object from the GTT aperture.
2578 i915_gem_object_unbind(struct drm_i915_gem_object
*obj
)
2580 drm_i915_private_t
*dev_priv
= obj
->base
.dev
->dev_private
;
2583 if (!i915_gem_obj_ggtt_bound(obj
))
2589 BUG_ON(obj
->pages
== NULL
);
2591 ret
= i915_gem_object_finish_gpu(obj
);
2594 /* Continue on if we fail due to EIO, the GPU is hung so we
2595 * should be safe and we need to cleanup or else we might
2596 * cause memory corruption through use-after-free.
2599 i915_gem_object_finish_gtt(obj
);
2601 /* release the fence reg _after_ flushing */
2602 ret
= i915_gem_object_put_fence(obj
);
2606 trace_i915_gem_object_unbind(obj
);
2608 if (obj
->has_global_gtt_mapping
)
2609 i915_gem_gtt_unbind_object(obj
);
2610 if (obj
->has_aliasing_ppgtt_mapping
) {
2611 i915_ppgtt_unbind_object(dev_priv
->mm
.aliasing_ppgtt
, obj
);
2612 obj
->has_aliasing_ppgtt_mapping
= 0;
2614 i915_gem_gtt_finish_object(obj
);
2615 i915_gem_object_unpin_pages(obj
);
2617 list_del(&obj
->mm_list
);
2618 list_move_tail(&obj
->global_list
, &dev_priv
->mm
.unbound_list
);
2619 /* Avoid an unnecessary call to unbind on rebind. */
2620 obj
->map_and_fenceable
= true;
2622 drm_mm_remove_node(&obj
->gtt_space
);
2627 int i915_gpu_idle(struct drm_device
*dev
)
2629 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2630 struct intel_ring_buffer
*ring
;
2633 /* Flush everything onto the inactive list. */
2634 for_each_ring(ring
, dev_priv
, i
) {
2635 ret
= i915_switch_context(ring
, NULL
, DEFAULT_CONTEXT_ID
);
2639 ret
= intel_ring_idle(ring
);
2647 static void i965_write_fence_reg(struct drm_device
*dev
, int reg
,
2648 struct drm_i915_gem_object
*obj
)
2650 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2652 int fence_pitch_shift
;
2654 if (INTEL_INFO(dev
)->gen
>= 6) {
2655 fence_reg
= FENCE_REG_SANDYBRIDGE_0
;
2656 fence_pitch_shift
= SANDYBRIDGE_FENCE_PITCH_SHIFT
;
2658 fence_reg
= FENCE_REG_965_0
;
2659 fence_pitch_shift
= I965_FENCE_PITCH_SHIFT
;
2662 fence_reg
+= reg
* 8;
2664 /* To w/a incoherency with non-atomic 64-bit register updates,
2665 * we split the 64-bit update into two 32-bit writes. In order
2666 * for a partial fence not to be evaluated between writes, we
2667 * precede the update with write to turn off the fence register,
2668 * and only enable the fence as the last step.
2670 * For extra levels of paranoia, we make sure each step lands
2671 * before applying the next step.
2673 I915_WRITE(fence_reg
, 0);
2674 POSTING_READ(fence_reg
);
2677 u32 size
= i915_gem_obj_ggtt_size(obj
);
2680 val
= (uint64_t)((i915_gem_obj_ggtt_offset(obj
) + size
- 4096) &
2682 val
|= i915_gem_obj_ggtt_offset(obj
) & 0xfffff000;
2683 val
|= (uint64_t)((obj
->stride
/ 128) - 1) << fence_pitch_shift
;
2684 if (obj
->tiling_mode
== I915_TILING_Y
)
2685 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
2686 val
|= I965_FENCE_REG_VALID
;
2688 I915_WRITE(fence_reg
+ 4, val
>> 32);
2689 POSTING_READ(fence_reg
+ 4);
2691 I915_WRITE(fence_reg
+ 0, val
);
2692 POSTING_READ(fence_reg
);
2694 I915_WRITE(fence_reg
+ 4, 0);
2695 POSTING_READ(fence_reg
+ 4);
2699 static void i915_write_fence_reg(struct drm_device
*dev
, int reg
,
2700 struct drm_i915_gem_object
*obj
)
2702 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2706 u32 size
= i915_gem_obj_ggtt_size(obj
);
2710 WARN((i915_gem_obj_ggtt_offset(obj
) & ~I915_FENCE_START_MASK
) ||
2711 (size
& -size
) != size
||
2712 (i915_gem_obj_ggtt_offset(obj
) & (size
- 1)),
2713 "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2714 i915_gem_obj_ggtt_offset(obj
), obj
->map_and_fenceable
, size
);
2716 if (obj
->tiling_mode
== I915_TILING_Y
&& HAS_128_BYTE_Y_TILING(dev
))
2721 /* Note: pitch better be a power of two tile widths */
2722 pitch_val
= obj
->stride
/ tile_width
;
2723 pitch_val
= ffs(pitch_val
) - 1;
2725 val
= i915_gem_obj_ggtt_offset(obj
);
2726 if (obj
->tiling_mode
== I915_TILING_Y
)
2727 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2728 val
|= I915_FENCE_SIZE_BITS(size
);
2729 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2730 val
|= I830_FENCE_REG_VALID
;
2735 reg
= FENCE_REG_830_0
+ reg
* 4;
2737 reg
= FENCE_REG_945_8
+ (reg
- 8) * 4;
2739 I915_WRITE(reg
, val
);
2743 static void i830_write_fence_reg(struct drm_device
*dev
, int reg
,
2744 struct drm_i915_gem_object
*obj
)
2746 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2750 u32 size
= i915_gem_obj_ggtt_size(obj
);
2753 WARN((i915_gem_obj_ggtt_offset(obj
) & ~I830_FENCE_START_MASK
) ||
2754 (size
& -size
) != size
||
2755 (i915_gem_obj_ggtt_offset(obj
) & (size
- 1)),
2756 "object 0x%08lx not 512K or pot-size 0x%08x aligned\n",
2757 i915_gem_obj_ggtt_offset(obj
), size
);
2759 pitch_val
= obj
->stride
/ 128;
2760 pitch_val
= ffs(pitch_val
) - 1;
2762 val
= i915_gem_obj_ggtt_offset(obj
);
2763 if (obj
->tiling_mode
== I915_TILING_Y
)
2764 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2765 val
|= I830_FENCE_SIZE_BITS(size
);
2766 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2767 val
|= I830_FENCE_REG_VALID
;
2771 I915_WRITE(FENCE_REG_830_0
+ reg
* 4, val
);
2772 POSTING_READ(FENCE_REG_830_0
+ reg
* 4);
2775 inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object
*obj
)
2777 return obj
&& obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
;
2780 static void i915_gem_write_fence(struct drm_device
*dev
, int reg
,
2781 struct drm_i915_gem_object
*obj
)
2783 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2785 /* Ensure that all CPU reads are completed before installing a fence
2786 * and all writes before removing the fence.
2788 if (i915_gem_object_needs_mb(dev_priv
->fence_regs
[reg
].obj
))
2791 switch (INTEL_INFO(dev
)->gen
) {
2795 case 4: i965_write_fence_reg(dev
, reg
, obj
); break;
2796 case 3: i915_write_fence_reg(dev
, reg
, obj
); break;
2797 case 2: i830_write_fence_reg(dev
, reg
, obj
); break;
2801 /* And similarly be paranoid that no direct access to this region
2802 * is reordered to before the fence is installed.
2804 if (i915_gem_object_needs_mb(obj
))
2808 static inline int fence_number(struct drm_i915_private
*dev_priv
,
2809 struct drm_i915_fence_reg
*fence
)
2811 return fence
- dev_priv
->fence_regs
;
2814 static void i915_gem_object_update_fence(struct drm_i915_gem_object
*obj
,
2815 struct drm_i915_fence_reg
*fence
,
2818 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2819 int reg
= fence_number(dev_priv
, fence
);
2821 i915_gem_write_fence(obj
->base
.dev
, reg
, enable
? obj
: NULL
);
2824 obj
->fence_reg
= reg
;
2826 list_move_tail(&fence
->lru_list
, &dev_priv
->mm
.fence_list
);
2828 obj
->fence_reg
= I915_FENCE_REG_NONE
;
2830 list_del_init(&fence
->lru_list
);
2835 i915_gem_object_wait_fence(struct drm_i915_gem_object
*obj
)
2837 if (obj
->last_fenced_seqno
) {
2838 int ret
= i915_wait_seqno(obj
->ring
, obj
->last_fenced_seqno
);
2842 obj
->last_fenced_seqno
= 0;
2845 obj
->fenced_gpu_access
= false;
2850 i915_gem_object_put_fence(struct drm_i915_gem_object
*obj
)
2852 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2853 struct drm_i915_fence_reg
*fence
;
2856 ret
= i915_gem_object_wait_fence(obj
);
2860 if (obj
->fence_reg
== I915_FENCE_REG_NONE
)
2863 fence
= &dev_priv
->fence_regs
[obj
->fence_reg
];
2865 i915_gem_object_fence_lost(obj
);
2866 i915_gem_object_update_fence(obj
, fence
, false);
2871 static struct drm_i915_fence_reg
*
2872 i915_find_fence_reg(struct drm_device
*dev
)
2874 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2875 struct drm_i915_fence_reg
*reg
, *avail
;
2878 /* First try to find a free reg */
2880 for (i
= dev_priv
->fence_reg_start
; i
< dev_priv
->num_fence_regs
; i
++) {
2881 reg
= &dev_priv
->fence_regs
[i
];
2885 if (!reg
->pin_count
)
2892 /* None available, try to steal one or wait for a user to finish */
2893 list_for_each_entry(reg
, &dev_priv
->mm
.fence_list
, lru_list
) {
2904 * i915_gem_object_get_fence - set up fencing for an object
2905 * @obj: object to map through a fence reg
2907 * When mapping objects through the GTT, userspace wants to be able to write
2908 * to them without having to worry about swizzling if the object is tiled.
2909 * This function walks the fence regs looking for a free one for @obj,
2910 * stealing one if it can't find any.
2912 * It then sets up the reg based on the object's properties: address, pitch
2913 * and tiling format.
2915 * For an untiled surface, this removes any existing fence.
2918 i915_gem_object_get_fence(struct drm_i915_gem_object
*obj
)
2920 struct drm_device
*dev
= obj
->base
.dev
;
2921 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2922 bool enable
= obj
->tiling_mode
!= I915_TILING_NONE
;
2923 struct drm_i915_fence_reg
*reg
;
2926 /* Have we updated the tiling parameters upon the object and so
2927 * will need to serialise the write to the associated fence register?
2929 if (obj
->fence_dirty
) {
2930 ret
= i915_gem_object_wait_fence(obj
);
2935 /* Just update our place in the LRU if our fence is getting reused. */
2936 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
2937 reg
= &dev_priv
->fence_regs
[obj
->fence_reg
];
2938 if (!obj
->fence_dirty
) {
2939 list_move_tail(®
->lru_list
,
2940 &dev_priv
->mm
.fence_list
);
2943 } else if (enable
) {
2944 reg
= i915_find_fence_reg(dev
);
2949 struct drm_i915_gem_object
*old
= reg
->obj
;
2951 ret
= i915_gem_object_wait_fence(old
);
2955 i915_gem_object_fence_lost(old
);
2960 i915_gem_object_update_fence(obj
, reg
, enable
);
2961 obj
->fence_dirty
= false;
2966 static bool i915_gem_valid_gtt_space(struct drm_device
*dev
,
2967 struct drm_mm_node
*gtt_space
,
2968 unsigned long cache_level
)
2970 struct drm_mm_node
*other
;
2972 /* On non-LLC machines we have to be careful when putting differing
2973 * types of snoopable memory together to avoid the prefetcher
2974 * crossing memory domains and dying.
2979 if (!drm_mm_node_allocated(gtt_space
))
2982 if (list_empty(>t_space
->node_list
))
2985 other
= list_entry(gtt_space
->node_list
.prev
, struct drm_mm_node
, node_list
);
2986 if (other
->allocated
&& !other
->hole_follows
&& other
->color
!= cache_level
)
2989 other
= list_entry(gtt_space
->node_list
.next
, struct drm_mm_node
, node_list
);
2990 if (other
->allocated
&& !gtt_space
->hole_follows
&& other
->color
!= cache_level
)
2996 static void i915_gem_verify_gtt(struct drm_device
*dev
)
2999 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3000 struct drm_i915_gem_object
*obj
;
3003 list_for_each_entry(obj
, &dev_priv
->mm
.gtt_list
, global_list
) {
3004 if (obj
->gtt_space
== NULL
) {
3005 printk(KERN_ERR
"object found on GTT list with no space reserved\n");
3010 if (obj
->cache_level
!= obj
->gtt_space
->color
) {
3011 printk(KERN_ERR
"object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n",
3012 i915_gem_obj_ggtt_offset(obj
),
3013 i915_gem_obj_ggtt_offset(obj
) + i915_gem_obj_ggtt_size(obj
),
3015 obj
->gtt_space
->color
);
3020 if (!i915_gem_valid_gtt_space(dev
,
3022 obj
->cache_level
)) {
3023 printk(KERN_ERR
"invalid GTT space found at [%08lx, %08lx] - color=%x\n",
3024 i915_gem_obj_ggtt_offset(obj
),
3025 i915_gem_obj_ggtt_offset(obj
) + i915_gem_obj_ggtt_size(obj
),
3037 * Finds free space in the GTT aperture and binds the object there.
3040 i915_gem_object_bind_to_gtt(struct drm_i915_gem_object
*obj
,
3042 bool map_and_fenceable
,
3045 struct drm_device
*dev
= obj
->base
.dev
;
3046 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3047 u32 size
, fence_size
, fence_alignment
, unfenced_alignment
;
3048 bool mappable
, fenceable
;
3049 size_t gtt_max
= map_and_fenceable
?
3050 dev_priv
->gtt
.mappable_end
: dev_priv
->gtt
.total
;
3053 fence_size
= i915_gem_get_gtt_size(dev
,
3056 fence_alignment
= i915_gem_get_gtt_alignment(dev
,
3058 obj
->tiling_mode
, true);
3059 unfenced_alignment
=
3060 i915_gem_get_gtt_alignment(dev
,
3062 obj
->tiling_mode
, false);
3065 alignment
= map_and_fenceable
? fence_alignment
:
3067 if (map_and_fenceable
&& alignment
& (fence_alignment
- 1)) {
3068 DRM_ERROR("Invalid object alignment requested %u\n", alignment
);
3072 size
= map_and_fenceable
? fence_size
: obj
->base
.size
;
3074 /* If the object is bigger than the entire aperture, reject it early
3075 * before evicting everything in a vain attempt to find space.
3077 if (obj
->base
.size
> gtt_max
) {
3078 DRM_ERROR("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%zu\n",
3080 map_and_fenceable
? "mappable" : "total",
3085 ret
= i915_gem_object_get_pages(obj
);
3089 i915_gem_object_pin_pages(obj
);
3092 ret
= drm_mm_insert_node_in_range_generic(&dev_priv
->mm
.gtt_space
,
3095 obj
->cache_level
, 0, gtt_max
);
3097 ret
= i915_gem_evict_something(dev
, size
, alignment
,
3104 i915_gem_object_unpin_pages(obj
);
3107 if (WARN_ON(!i915_gem_valid_gtt_space(dev
, &obj
->gtt_space
,
3108 obj
->cache_level
))) {
3109 i915_gem_object_unpin_pages(obj
);
3110 drm_mm_remove_node(&obj
->gtt_space
);
3114 ret
= i915_gem_gtt_prepare_object(obj
);
3116 i915_gem_object_unpin_pages(obj
);
3117 drm_mm_remove_node(&obj
->gtt_space
);
3121 list_move_tail(&obj
->global_list
, &dev_priv
->mm
.bound_list
);
3122 list_add_tail(&obj
->mm_list
, &dev_priv
->mm
.inactive_list
);
3125 i915_gem_obj_ggtt_size(obj
) == fence_size
&&
3126 (i915_gem_obj_ggtt_offset(obj
) & (fence_alignment
- 1)) == 0;
3128 mappable
= i915_gem_obj_ggtt_offset(obj
) + obj
->base
.size
<=
3129 dev_priv
->gtt
.mappable_end
;
3131 obj
->map_and_fenceable
= mappable
&& fenceable
;
3133 trace_i915_gem_object_bind(obj
, map_and_fenceable
);
3134 i915_gem_verify_gtt(dev
);
3139 i915_gem_clflush_object(struct drm_i915_gem_object
*obj
)
3141 /* If we don't have a page list set up, then we're not pinned
3142 * to GPU, and we can ignore the cache flush because it'll happen
3143 * again at bind time.
3145 if (obj
->pages
== NULL
)
3149 * Stolen memory is always coherent with the GPU as it is explicitly
3150 * marked as wc by the system, or the system is cache-coherent.
3155 /* If the GPU is snooping the contents of the CPU cache,
3156 * we do not need to manually clear the CPU cache lines. However,
3157 * the caches are only snooped when the render cache is
3158 * flushed/invalidated. As we always have to emit invalidations
3159 * and flushes when moving into and out of the RENDER domain, correct
3160 * snooping behaviour occurs naturally as the result of our domain
3163 if (obj
->cache_level
!= I915_CACHE_NONE
)
3166 trace_i915_gem_object_clflush(obj
);
3168 drm_clflush_sg(obj
->pages
);
3171 /** Flushes the GTT write domain for the object if it's dirty. */
3173 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
)
3175 uint32_t old_write_domain
;
3177 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_GTT
)
3180 /* No actual flushing is required for the GTT write domain. Writes
3181 * to it immediately go to main memory as far as we know, so there's
3182 * no chipset flush. It also doesn't land in render cache.
3184 * However, we do have to enforce the order so that all writes through
3185 * the GTT land before any writes to the device, such as updates to
3190 old_write_domain
= obj
->base
.write_domain
;
3191 obj
->base
.write_domain
= 0;
3193 trace_i915_gem_object_change_domain(obj
,
3194 obj
->base
.read_domains
,
3198 /** Flushes the CPU write domain for the object if it's dirty. */
3200 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
)
3202 uint32_t old_write_domain
;
3204 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
)
3207 i915_gem_clflush_object(obj
);
3208 i915_gem_chipset_flush(obj
->base
.dev
);
3209 old_write_domain
= obj
->base
.write_domain
;
3210 obj
->base
.write_domain
= 0;
3212 trace_i915_gem_object_change_domain(obj
,
3213 obj
->base
.read_domains
,
3218 * Moves a single object to the GTT read, and possibly write domain.
3220 * This function returns when the move is complete, including waiting on
3224 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
, bool write
)
3226 drm_i915_private_t
*dev_priv
= obj
->base
.dev
->dev_private
;
3227 uint32_t old_write_domain
, old_read_domains
;
3230 /* Not valid to be called on unbound objects. */
3231 if (!i915_gem_obj_ggtt_bound(obj
))
3234 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_GTT
)
3237 ret
= i915_gem_object_wait_rendering(obj
, !write
);
3241 i915_gem_object_flush_cpu_write_domain(obj
);
3243 /* Serialise direct access to this object with the barriers for
3244 * coherent writes from the GPU, by effectively invalidating the
3245 * GTT domain upon first access.
3247 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
) == 0)
3250 old_write_domain
= obj
->base
.write_domain
;
3251 old_read_domains
= obj
->base
.read_domains
;
3253 /* It should now be out of any other write domains, and we can update
3254 * the domain values for our changes.
3256 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
3257 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
3259 obj
->base
.read_domains
= I915_GEM_DOMAIN_GTT
;
3260 obj
->base
.write_domain
= I915_GEM_DOMAIN_GTT
;
3264 trace_i915_gem_object_change_domain(obj
,
3268 /* And bump the LRU for this access */
3269 if (i915_gem_object_is_inactive(obj
))
3270 list_move_tail(&obj
->mm_list
, &dev_priv
->mm
.inactive_list
);
3275 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
3276 enum i915_cache_level cache_level
)
3278 struct drm_device
*dev
= obj
->base
.dev
;
3279 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3282 if (obj
->cache_level
== cache_level
)
3285 if (obj
->pin_count
) {
3286 DRM_DEBUG("can not change the cache level of pinned objects\n");
3290 if (!i915_gem_valid_gtt_space(dev
, &obj
->gtt_space
, cache_level
)) {
3291 ret
= i915_gem_object_unbind(obj
);
3296 if (i915_gem_obj_ggtt_bound(obj
)) {
3297 ret
= i915_gem_object_finish_gpu(obj
);
3301 i915_gem_object_finish_gtt(obj
);
3303 /* Before SandyBridge, you could not use tiling or fence
3304 * registers with snooped memory, so relinquish any fences
3305 * currently pointing to our region in the aperture.
3307 if (INTEL_INFO(dev
)->gen
< 6) {
3308 ret
= i915_gem_object_put_fence(obj
);
3313 if (obj
->has_global_gtt_mapping
)
3314 i915_gem_gtt_bind_object(obj
, cache_level
);
3315 if (obj
->has_aliasing_ppgtt_mapping
)
3316 i915_ppgtt_bind_object(dev_priv
->mm
.aliasing_ppgtt
,
3319 i915_gem_obj_ggtt_set_color(obj
, cache_level
);
3322 if (cache_level
== I915_CACHE_NONE
) {
3323 u32 old_read_domains
, old_write_domain
;
3325 /* If we're coming from LLC cached, then we haven't
3326 * actually been tracking whether the data is in the
3327 * CPU cache or not, since we only allow one bit set
3328 * in obj->write_domain and have been skipping the clflushes.
3329 * Just set it to the CPU cache for now.
3331 WARN_ON(obj
->base
.write_domain
& ~I915_GEM_DOMAIN_CPU
);
3332 WARN_ON(obj
->base
.read_domains
& ~I915_GEM_DOMAIN_CPU
);
3334 old_read_domains
= obj
->base
.read_domains
;
3335 old_write_domain
= obj
->base
.write_domain
;
3337 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
3338 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
3340 trace_i915_gem_object_change_domain(obj
,
3345 obj
->cache_level
= cache_level
;
3346 i915_gem_verify_gtt(dev
);
3350 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
3351 struct drm_file
*file
)
3353 struct drm_i915_gem_caching
*args
= data
;
3354 struct drm_i915_gem_object
*obj
;
3357 ret
= i915_mutex_lock_interruptible(dev
);
3361 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3362 if (&obj
->base
== NULL
) {
3367 args
->caching
= obj
->cache_level
!= I915_CACHE_NONE
;
3369 drm_gem_object_unreference(&obj
->base
);
3371 mutex_unlock(&dev
->struct_mutex
);
3375 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
3376 struct drm_file
*file
)
3378 struct drm_i915_gem_caching
*args
= data
;
3379 struct drm_i915_gem_object
*obj
;
3380 enum i915_cache_level level
;
3383 switch (args
->caching
) {
3384 case I915_CACHING_NONE
:
3385 level
= I915_CACHE_NONE
;
3387 case I915_CACHING_CACHED
:
3388 level
= I915_CACHE_LLC
;
3394 ret
= i915_mutex_lock_interruptible(dev
);
3398 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3399 if (&obj
->base
== NULL
) {
3404 ret
= i915_gem_object_set_cache_level(obj
, level
);
3406 drm_gem_object_unreference(&obj
->base
);
3408 mutex_unlock(&dev
->struct_mutex
);
3413 * Prepare buffer for display plane (scanout, cursors, etc).
3414 * Can be called from an uninterruptible phase (modesetting) and allows
3415 * any flushes to be pipelined (for pageflips).
3418 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
3420 struct intel_ring_buffer
*pipelined
)
3422 u32 old_read_domains
, old_write_domain
;
3425 if (pipelined
!= obj
->ring
) {
3426 ret
= i915_gem_object_sync(obj
, pipelined
);
3431 /* The display engine is not coherent with the LLC cache on gen6. As
3432 * a result, we make sure that the pinning that is about to occur is
3433 * done with uncached PTEs. This is lowest common denominator for all
3436 * However for gen6+, we could do better by using the GFDT bit instead
3437 * of uncaching, which would allow us to flush all the LLC-cached data
3438 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3440 ret
= i915_gem_object_set_cache_level(obj
, I915_CACHE_NONE
);
3444 /* As the user may map the buffer once pinned in the display plane
3445 * (e.g. libkms for the bootup splash), we have to ensure that we
3446 * always use map_and_fenceable for all scanout buffers.
3448 ret
= i915_gem_object_pin(obj
, alignment
, true, false);
3452 i915_gem_object_flush_cpu_write_domain(obj
);
3454 old_write_domain
= obj
->base
.write_domain
;
3455 old_read_domains
= obj
->base
.read_domains
;
3457 /* It should now be out of any other write domains, and we can update
3458 * the domain values for our changes.
3460 obj
->base
.write_domain
= 0;
3461 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
3463 trace_i915_gem_object_change_domain(obj
,
3471 i915_gem_object_finish_gpu(struct drm_i915_gem_object
*obj
)
3475 if ((obj
->base
.read_domains
& I915_GEM_GPU_DOMAINS
) == 0)
3478 ret
= i915_gem_object_wait_rendering(obj
, false);
3482 /* Ensure that we invalidate the GPU's caches and TLBs. */
3483 obj
->base
.read_domains
&= ~I915_GEM_GPU_DOMAINS
;
3488 * Moves a single object to the CPU read, and possibly write domain.
3490 * This function returns when the move is complete, including waiting on
3494 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
)
3496 uint32_t old_write_domain
, old_read_domains
;
3499 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_CPU
)
3502 ret
= i915_gem_object_wait_rendering(obj
, !write
);
3506 i915_gem_object_flush_gtt_write_domain(obj
);
3508 old_write_domain
= obj
->base
.write_domain
;
3509 old_read_domains
= obj
->base
.read_domains
;
3511 /* Flush the CPU cache if it's still invalid. */
3512 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) == 0) {
3513 i915_gem_clflush_object(obj
);
3515 obj
->base
.read_domains
|= I915_GEM_DOMAIN_CPU
;
3518 /* It should now be out of any other write domains, and we can update
3519 * the domain values for our changes.
3521 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
3523 /* If we're writing through the CPU, then the GPU read domains will
3524 * need to be invalidated at next use.
3527 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
3528 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
3531 trace_i915_gem_object_change_domain(obj
,
3538 /* Throttle our rendering by waiting until the ring has completed our requests
3539 * emitted over 20 msec ago.
3541 * Note that if we were to use the current jiffies each time around the loop,
3542 * we wouldn't escape the function with any frames outstanding if the time to
3543 * render a frame was over 20ms.
3545 * This should get us reasonable parallelism between CPU and GPU but also
3546 * relatively low latency when blocking on a particular request to finish.
3549 i915_gem_ring_throttle(struct drm_device
*dev
, struct drm_file
*file
)
3551 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3552 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
3553 unsigned long recent_enough
= jiffies
- msecs_to_jiffies(20);
3554 struct drm_i915_gem_request
*request
;
3555 struct intel_ring_buffer
*ring
= NULL
;
3556 unsigned reset_counter
;
3560 ret
= i915_gem_wait_for_error(&dev_priv
->gpu_error
);
3564 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, false);
3568 spin_lock(&file_priv
->mm
.lock
);
3569 list_for_each_entry(request
, &file_priv
->mm
.request_list
, client_list
) {
3570 if (time_after_eq(request
->emitted_jiffies
, recent_enough
))
3573 ring
= request
->ring
;
3574 seqno
= request
->seqno
;
3576 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
3577 spin_unlock(&file_priv
->mm
.lock
);
3582 ret
= __wait_seqno(ring
, seqno
, reset_counter
, true, NULL
);
3584 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, 0);
3590 i915_gem_object_pin(struct drm_i915_gem_object
*obj
,
3592 bool map_and_fenceable
,
3597 if (WARN_ON(obj
->pin_count
== DRM_I915_GEM_OBJECT_MAX_PIN_COUNT
))
3600 if (i915_gem_obj_ggtt_bound(obj
)) {
3601 if ((alignment
&& i915_gem_obj_ggtt_offset(obj
) & (alignment
- 1)) ||
3602 (map_and_fenceable
&& !obj
->map_and_fenceable
)) {
3603 WARN(obj
->pin_count
,
3604 "bo is already pinned with incorrect alignment:"
3605 " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d,"
3606 " obj->map_and_fenceable=%d\n",
3607 i915_gem_obj_ggtt_offset(obj
), alignment
,
3609 obj
->map_and_fenceable
);
3610 ret
= i915_gem_object_unbind(obj
);
3616 if (!i915_gem_obj_ggtt_bound(obj
)) {
3617 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
3619 ret
= i915_gem_object_bind_to_gtt(obj
, alignment
,
3625 if (!dev_priv
->mm
.aliasing_ppgtt
)
3626 i915_gem_gtt_bind_object(obj
, obj
->cache_level
);
3629 if (!obj
->has_global_gtt_mapping
&& map_and_fenceable
)
3630 i915_gem_gtt_bind_object(obj
, obj
->cache_level
);
3633 obj
->pin_mappable
|= map_and_fenceable
;
3639 i915_gem_object_unpin(struct drm_i915_gem_object
*obj
)
3641 BUG_ON(obj
->pin_count
== 0);
3642 BUG_ON(!i915_gem_obj_ggtt_bound(obj
));
3644 if (--obj
->pin_count
== 0)
3645 obj
->pin_mappable
= false;
3649 i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
3650 struct drm_file
*file
)
3652 struct drm_i915_gem_pin
*args
= data
;
3653 struct drm_i915_gem_object
*obj
;
3656 ret
= i915_mutex_lock_interruptible(dev
);
3660 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3661 if (&obj
->base
== NULL
) {
3666 if (obj
->madv
!= I915_MADV_WILLNEED
) {
3667 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3672 if (obj
->pin_filp
!= NULL
&& obj
->pin_filp
!= file
) {
3673 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3679 if (obj
->user_pin_count
== 0) {
3680 ret
= i915_gem_object_pin(obj
, args
->alignment
, true, false);
3685 obj
->user_pin_count
++;
3686 obj
->pin_filp
= file
;
3688 /* XXX - flush the CPU caches for pinned objects
3689 * as the X server doesn't manage domains yet
3691 i915_gem_object_flush_cpu_write_domain(obj
);
3692 args
->offset
= i915_gem_obj_ggtt_offset(obj
);
3694 drm_gem_object_unreference(&obj
->base
);
3696 mutex_unlock(&dev
->struct_mutex
);
3701 i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
3702 struct drm_file
*file
)
3704 struct drm_i915_gem_pin
*args
= data
;
3705 struct drm_i915_gem_object
*obj
;
3708 ret
= i915_mutex_lock_interruptible(dev
);
3712 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3713 if (&obj
->base
== NULL
) {
3718 if (obj
->pin_filp
!= file
) {
3719 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3724 obj
->user_pin_count
--;
3725 if (obj
->user_pin_count
== 0) {
3726 obj
->pin_filp
= NULL
;
3727 i915_gem_object_unpin(obj
);
3731 drm_gem_object_unreference(&obj
->base
);
3733 mutex_unlock(&dev
->struct_mutex
);
3738 i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
3739 struct drm_file
*file
)
3741 struct drm_i915_gem_busy
*args
= data
;
3742 struct drm_i915_gem_object
*obj
;
3745 ret
= i915_mutex_lock_interruptible(dev
);
3749 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3750 if (&obj
->base
== NULL
) {
3755 /* Count all active objects as busy, even if they are currently not used
3756 * by the gpu. Users of this interface expect objects to eventually
3757 * become non-busy without any further actions, therefore emit any
3758 * necessary flushes here.
3760 ret
= i915_gem_object_flush_active(obj
);
3762 args
->busy
= obj
->active
;
3764 BUILD_BUG_ON(I915_NUM_RINGS
> 16);
3765 args
->busy
|= intel_ring_flag(obj
->ring
) << 16;
3768 drm_gem_object_unreference(&obj
->base
);
3770 mutex_unlock(&dev
->struct_mutex
);
3775 i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
3776 struct drm_file
*file_priv
)
3778 return i915_gem_ring_throttle(dev
, file_priv
);
3782 i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
3783 struct drm_file
*file_priv
)
3785 struct drm_i915_gem_madvise
*args
= data
;
3786 struct drm_i915_gem_object
*obj
;
3789 switch (args
->madv
) {
3790 case I915_MADV_DONTNEED
:
3791 case I915_MADV_WILLNEED
:
3797 ret
= i915_mutex_lock_interruptible(dev
);
3801 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file_priv
, args
->handle
));
3802 if (&obj
->base
== NULL
) {
3807 if (obj
->pin_count
) {
3812 if (obj
->madv
!= __I915_MADV_PURGED
)
3813 obj
->madv
= args
->madv
;
3815 /* if the object is no longer attached, discard its backing storage */
3816 if (i915_gem_object_is_purgeable(obj
) && obj
->pages
== NULL
)
3817 i915_gem_object_truncate(obj
);
3819 args
->retained
= obj
->madv
!= __I915_MADV_PURGED
;
3822 drm_gem_object_unreference(&obj
->base
);
3824 mutex_unlock(&dev
->struct_mutex
);
3828 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
3829 const struct drm_i915_gem_object_ops
*ops
)
3831 INIT_LIST_HEAD(&obj
->mm_list
);
3832 INIT_LIST_HEAD(&obj
->global_list
);
3833 INIT_LIST_HEAD(&obj
->ring_list
);
3834 INIT_LIST_HEAD(&obj
->exec_list
);
3838 obj
->fence_reg
= I915_FENCE_REG_NONE
;
3839 obj
->madv
= I915_MADV_WILLNEED
;
3840 /* Avoid an unnecessary call to unbind on the first bind. */
3841 obj
->map_and_fenceable
= true;
3843 i915_gem_info_add_obj(obj
->base
.dev
->dev_private
, obj
->base
.size
);
3846 static const struct drm_i915_gem_object_ops i915_gem_object_ops
= {
3847 .get_pages
= i915_gem_object_get_pages_gtt
,
3848 .put_pages
= i915_gem_object_put_pages_gtt
,
3851 struct drm_i915_gem_object
*i915_gem_alloc_object(struct drm_device
*dev
,
3854 struct drm_i915_gem_object
*obj
;
3855 struct address_space
*mapping
;
3858 obj
= i915_gem_object_alloc(dev
);
3862 if (drm_gem_object_init(dev
, &obj
->base
, size
) != 0) {
3863 i915_gem_object_free(obj
);
3867 mask
= GFP_HIGHUSER
| __GFP_RECLAIMABLE
;
3868 if (IS_CRESTLINE(dev
) || IS_BROADWATER(dev
)) {
3869 /* 965gm cannot relocate objects above 4GiB. */
3870 mask
&= ~__GFP_HIGHMEM
;
3871 mask
|= __GFP_DMA32
;
3874 mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
3875 mapping_set_gfp_mask(mapping
, mask
);
3877 i915_gem_object_init(obj
, &i915_gem_object_ops
);
3879 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
3880 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
3883 /* On some devices, we can have the GPU use the LLC (the CPU
3884 * cache) for about a 10% performance improvement
3885 * compared to uncached. Graphics requests other than
3886 * display scanout are coherent with the CPU in
3887 * accessing this cache. This means in this mode we
3888 * don't need to clflush on the CPU side, and on the
3889 * GPU side we only need to flush internal caches to
3890 * get data visible to the CPU.
3892 * However, we maintain the display planes as UC, and so
3893 * need to rebind when first used as such.
3895 obj
->cache_level
= I915_CACHE_LLC
;
3897 obj
->cache_level
= I915_CACHE_NONE
;
3902 int i915_gem_init_object(struct drm_gem_object
*obj
)
3909 void i915_gem_free_object(struct drm_gem_object
*gem_obj
)
3911 struct drm_i915_gem_object
*obj
= to_intel_bo(gem_obj
);
3912 struct drm_device
*dev
= obj
->base
.dev
;
3913 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3915 trace_i915_gem_object_destroy(obj
);
3918 i915_gem_detach_phys_object(dev
, obj
);
3921 if (WARN_ON(i915_gem_object_unbind(obj
) == -ERESTARTSYS
)) {
3922 bool was_interruptible
;
3924 was_interruptible
= dev_priv
->mm
.interruptible
;
3925 dev_priv
->mm
.interruptible
= false;
3927 WARN_ON(i915_gem_object_unbind(obj
));
3929 dev_priv
->mm
.interruptible
= was_interruptible
;
3932 /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
3933 * before progressing. */
3935 i915_gem_object_unpin_pages(obj
);
3937 if (WARN_ON(obj
->pages_pin_count
))
3938 obj
->pages_pin_count
= 0;
3939 i915_gem_object_put_pages(obj
);
3940 i915_gem_object_free_mmap_offset(obj
);
3941 i915_gem_object_release_stolen(obj
);
3945 if (obj
->base
.import_attach
)
3946 drm_prime_gem_destroy(&obj
->base
, NULL
);
3948 drm_gem_object_release(&obj
->base
);
3949 i915_gem_info_remove_obj(dev_priv
, obj
->base
.size
);
3952 i915_gem_object_free(obj
);
3956 i915_gem_idle(struct drm_device
*dev
)
3958 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3961 if (dev_priv
->ums
.mm_suspended
) {
3962 mutex_unlock(&dev
->struct_mutex
);
3966 ret
= i915_gpu_idle(dev
);
3968 mutex_unlock(&dev
->struct_mutex
);
3971 i915_gem_retire_requests(dev
);
3973 /* Under UMS, be paranoid and evict. */
3974 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
3975 i915_gem_evict_everything(dev
);
3977 del_timer_sync(&dev_priv
->gpu_error
.hangcheck_timer
);
3979 i915_kernel_lost_context(dev
);
3980 i915_gem_cleanup_ringbuffer(dev
);
3982 /* Cancel the retire work handler, which should be idle now. */
3983 cancel_delayed_work_sync(&dev_priv
->mm
.retire_work
);
3988 void i915_gem_l3_remap(struct drm_device
*dev
)
3990 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3994 if (!HAS_L3_GPU_CACHE(dev
))
3997 if (!dev_priv
->l3_parity
.remap_info
)
4000 misccpctl
= I915_READ(GEN7_MISCCPCTL
);
4001 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
& ~GEN7_DOP_CLOCK_GATE_ENABLE
);
4002 POSTING_READ(GEN7_MISCCPCTL
);
4004 for (i
= 0; i
< GEN7_L3LOG_SIZE
; i
+= 4) {
4005 u32 remap
= I915_READ(GEN7_L3LOG_BASE
+ i
);
4006 if (remap
&& remap
!= dev_priv
->l3_parity
.remap_info
[i
/4])
4007 DRM_DEBUG("0x%x was already programmed to %x\n",
4008 GEN7_L3LOG_BASE
+ i
, remap
);
4009 if (remap
&& !dev_priv
->l3_parity
.remap_info
[i
/4])
4010 DRM_DEBUG_DRIVER("Clearing remapped register\n");
4011 I915_WRITE(GEN7_L3LOG_BASE
+ i
, dev_priv
->l3_parity
.remap_info
[i
/4]);
4014 /* Make sure all the writes land before disabling dop clock gating */
4015 POSTING_READ(GEN7_L3LOG_BASE
);
4017 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
);
4020 void i915_gem_init_swizzling(struct drm_device
*dev
)
4022 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4024 if (INTEL_INFO(dev
)->gen
< 5 ||
4025 dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_NONE
)
4028 I915_WRITE(DISP_ARB_CTL
, I915_READ(DISP_ARB_CTL
) |
4029 DISP_TILE_SURFACE_SWIZZLING
);
4034 I915_WRITE(TILECTL
, I915_READ(TILECTL
) | TILECTL_SWZCTL
);
4036 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB
));
4037 else if (IS_GEN7(dev
))
4038 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB
));
4044 intel_enable_blt(struct drm_device
*dev
)
4049 /* The blitter was dysfunctional on early prototypes */
4050 if (IS_GEN6(dev
) && dev
->pdev
->revision
< 8) {
4051 DRM_INFO("BLT not supported on this pre-production hardware;"
4052 " graphics performance will be degraded.\n");
4059 static int i915_gem_init_rings(struct drm_device
*dev
)
4061 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4064 ret
= intel_init_render_ring_buffer(dev
);
4069 ret
= intel_init_bsd_ring_buffer(dev
);
4071 goto cleanup_render_ring
;
4074 if (intel_enable_blt(dev
)) {
4075 ret
= intel_init_blt_ring_buffer(dev
);
4077 goto cleanup_bsd_ring
;
4080 if (HAS_VEBOX(dev
)) {
4081 ret
= intel_init_vebox_ring_buffer(dev
);
4083 goto cleanup_blt_ring
;
4087 ret
= i915_gem_set_seqno(dev
, ((u32
)~0 - 0x1000));
4089 goto cleanup_vebox_ring
;
4094 intel_cleanup_ring_buffer(&dev_priv
->ring
[VECS
]);
4096 intel_cleanup_ring_buffer(&dev_priv
->ring
[BCS
]);
4098 intel_cleanup_ring_buffer(&dev_priv
->ring
[VCS
]);
4099 cleanup_render_ring
:
4100 intel_cleanup_ring_buffer(&dev_priv
->ring
[RCS
]);
4106 i915_gem_init_hw(struct drm_device
*dev
)
4108 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4111 if (INTEL_INFO(dev
)->gen
< 6 && !intel_enable_gtt())
4114 if (IS_HASWELL(dev
) && (I915_READ(0x120010) == 1))
4115 I915_WRITE(0x9008, I915_READ(0x9008) | 0xf0000);
4117 if (HAS_PCH_NOP(dev
)) {
4118 u32 temp
= I915_READ(GEN7_MSG_CTL
);
4119 temp
&= ~(WAIT_FOR_PCH_FLR_ACK
| WAIT_FOR_PCH_RESET_ACK
);
4120 I915_WRITE(GEN7_MSG_CTL
, temp
);
4123 i915_gem_l3_remap(dev
);
4125 i915_gem_init_swizzling(dev
);
4127 ret
= i915_gem_init_rings(dev
);
4132 * XXX: There was some w/a described somewhere suggesting loading
4133 * contexts before PPGTT.
4135 i915_gem_context_init(dev
);
4136 if (dev_priv
->mm
.aliasing_ppgtt
) {
4137 ret
= dev_priv
->mm
.aliasing_ppgtt
->enable(dev
);
4139 i915_gem_cleanup_aliasing_ppgtt(dev
);
4140 DRM_INFO("PPGTT enable failed. This is not fatal, but unexpected\n");
4147 int i915_gem_init(struct drm_device
*dev
)
4149 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4152 mutex_lock(&dev
->struct_mutex
);
4154 if (IS_VALLEYVIEW(dev
)) {
4155 /* VLVA0 (potential hack), BIOS isn't actually waking us */
4156 I915_WRITE(VLV_GTLC_WAKE_CTRL
, 1);
4157 if (wait_for((I915_READ(VLV_GTLC_PW_STATUS
) & 1) == 1, 10))
4158 DRM_DEBUG_DRIVER("allow wake ack timed out\n");
4161 i915_gem_init_global_gtt(dev
);
4163 ret
= i915_gem_init_hw(dev
);
4164 mutex_unlock(&dev
->struct_mutex
);
4166 i915_gem_cleanup_aliasing_ppgtt(dev
);
4170 /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */
4171 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
4172 dev_priv
->dri1
.allow_batchbuffer
= 1;
4177 i915_gem_cleanup_ringbuffer(struct drm_device
*dev
)
4179 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4180 struct intel_ring_buffer
*ring
;
4183 for_each_ring(ring
, dev_priv
, i
)
4184 intel_cleanup_ring_buffer(ring
);
4188 i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
4189 struct drm_file
*file_priv
)
4191 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4194 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4197 if (i915_reset_in_progress(&dev_priv
->gpu_error
)) {
4198 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4199 atomic_set(&dev_priv
->gpu_error
.reset_counter
, 0);
4202 mutex_lock(&dev
->struct_mutex
);
4203 dev_priv
->ums
.mm_suspended
= 0;
4205 ret
= i915_gem_init_hw(dev
);
4207 mutex_unlock(&dev
->struct_mutex
);
4211 BUG_ON(!list_empty(&dev_priv
->mm
.active_list
));
4212 mutex_unlock(&dev
->struct_mutex
);
4214 ret
= drm_irq_install(dev
);
4216 goto cleanup_ringbuffer
;
4221 mutex_lock(&dev
->struct_mutex
);
4222 i915_gem_cleanup_ringbuffer(dev
);
4223 dev_priv
->ums
.mm_suspended
= 1;
4224 mutex_unlock(&dev
->struct_mutex
);
4230 i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
4231 struct drm_file
*file_priv
)
4233 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4236 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4239 drm_irq_uninstall(dev
);
4241 mutex_lock(&dev
->struct_mutex
);
4242 ret
= i915_gem_idle(dev
);
4244 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4245 * We need to replace this with a semaphore, or something.
4246 * And not confound ums.mm_suspended!
4249 dev_priv
->ums
.mm_suspended
= 1;
4250 mutex_unlock(&dev
->struct_mutex
);
4256 i915_gem_lastclose(struct drm_device
*dev
)
4260 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4263 mutex_lock(&dev
->struct_mutex
);
4264 ret
= i915_gem_idle(dev
);
4266 DRM_ERROR("failed to idle hardware: %d\n", ret
);
4267 mutex_unlock(&dev
->struct_mutex
);
4271 init_ring_lists(struct intel_ring_buffer
*ring
)
4273 INIT_LIST_HEAD(&ring
->active_list
);
4274 INIT_LIST_HEAD(&ring
->request_list
);
4278 i915_gem_load(struct drm_device
*dev
)
4280 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4284 kmem_cache_create("i915_gem_object",
4285 sizeof(struct drm_i915_gem_object
), 0,
4289 INIT_LIST_HEAD(&dev_priv
->mm
.active_list
);
4290 INIT_LIST_HEAD(&dev_priv
->mm
.inactive_list
);
4291 INIT_LIST_HEAD(&dev_priv
->mm
.unbound_list
);
4292 INIT_LIST_HEAD(&dev_priv
->mm
.bound_list
);
4293 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
4294 for (i
= 0; i
< I915_NUM_RINGS
; i
++)
4295 init_ring_lists(&dev_priv
->ring
[i
]);
4296 for (i
= 0; i
< I915_MAX_NUM_FENCES
; i
++)
4297 INIT_LIST_HEAD(&dev_priv
->fence_regs
[i
].lru_list
);
4298 INIT_DELAYED_WORK(&dev_priv
->mm
.retire_work
,
4299 i915_gem_retire_work_handler
);
4300 init_waitqueue_head(&dev_priv
->gpu_error
.reset_queue
);
4302 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4304 I915_WRITE(MI_ARB_STATE
,
4305 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE
));
4308 dev_priv
->relative_constants_mode
= I915_EXEC_CONSTANTS_REL_GENERAL
;
4310 /* Old X drivers will take 0-2 for front, back, depth buffers */
4311 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
4312 dev_priv
->fence_reg_start
= 3;
4314 if (INTEL_INFO(dev
)->gen
>= 7 && !IS_VALLEYVIEW(dev
))
4315 dev_priv
->num_fence_regs
= 32;
4316 else if (INTEL_INFO(dev
)->gen
>= 4 || IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
4317 dev_priv
->num_fence_regs
= 16;
4319 dev_priv
->num_fence_regs
= 8;
4321 /* Initialize fence registers to zero */
4322 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
4323 i915_gem_restore_fences(dev
);
4325 i915_gem_detect_bit_6_swizzle(dev
);
4326 init_waitqueue_head(&dev_priv
->pending_flip_queue
);
4328 dev_priv
->mm
.interruptible
= true;
4330 dev_priv
->mm
.inactive_shrinker
.shrink
= i915_gem_inactive_shrink
;
4331 dev_priv
->mm
.inactive_shrinker
.seeks
= DEFAULT_SEEKS
;
4332 register_shrinker(&dev_priv
->mm
.inactive_shrinker
);
4336 * Create a physically contiguous memory object for this object
4337 * e.g. for cursor + overlay regs
4339 static int i915_gem_init_phys_object(struct drm_device
*dev
,
4340 int id
, int size
, int align
)
4342 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4343 struct drm_i915_gem_phys_object
*phys_obj
;
4346 if (dev_priv
->mm
.phys_objs
[id
- 1] || !size
)
4349 phys_obj
= kzalloc(sizeof(struct drm_i915_gem_phys_object
), GFP_KERNEL
);
4355 phys_obj
->handle
= drm_pci_alloc(dev
, size
, align
);
4356 if (!phys_obj
->handle
) {
4361 set_memory_wc((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
4364 dev_priv
->mm
.phys_objs
[id
- 1] = phys_obj
;
4372 static void i915_gem_free_phys_object(struct drm_device
*dev
, int id
)
4374 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4375 struct drm_i915_gem_phys_object
*phys_obj
;
4377 if (!dev_priv
->mm
.phys_objs
[id
- 1])
4380 phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
4381 if (phys_obj
->cur_obj
) {
4382 i915_gem_detach_phys_object(dev
, phys_obj
->cur_obj
);
4386 set_memory_wb((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
4388 drm_pci_free(dev
, phys_obj
->handle
);
4390 dev_priv
->mm
.phys_objs
[id
- 1] = NULL
;
4393 void i915_gem_free_all_phys_object(struct drm_device
*dev
)
4397 for (i
= I915_GEM_PHYS_CURSOR_0
; i
<= I915_MAX_PHYS_OBJECT
; i
++)
4398 i915_gem_free_phys_object(dev
, i
);
4401 void i915_gem_detach_phys_object(struct drm_device
*dev
,
4402 struct drm_i915_gem_object
*obj
)
4404 struct address_space
*mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
4411 vaddr
= obj
->phys_obj
->handle
->vaddr
;
4413 page_count
= obj
->base
.size
/ PAGE_SIZE
;
4414 for (i
= 0; i
< page_count
; i
++) {
4415 struct page
*page
= shmem_read_mapping_page(mapping
, i
);
4416 if (!IS_ERR(page
)) {
4417 char *dst
= kmap_atomic(page
);
4418 memcpy(dst
, vaddr
+ i
*PAGE_SIZE
, PAGE_SIZE
);
4421 drm_clflush_pages(&page
, 1);
4423 set_page_dirty(page
);
4424 mark_page_accessed(page
);
4425 page_cache_release(page
);
4428 i915_gem_chipset_flush(dev
);
4430 obj
->phys_obj
->cur_obj
= NULL
;
4431 obj
->phys_obj
= NULL
;
4435 i915_gem_attach_phys_object(struct drm_device
*dev
,
4436 struct drm_i915_gem_object
*obj
,
4440 struct address_space
*mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
4441 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4446 if (id
> I915_MAX_PHYS_OBJECT
)
4449 if (obj
->phys_obj
) {
4450 if (obj
->phys_obj
->id
== id
)
4452 i915_gem_detach_phys_object(dev
, obj
);
4455 /* create a new object */
4456 if (!dev_priv
->mm
.phys_objs
[id
- 1]) {
4457 ret
= i915_gem_init_phys_object(dev
, id
,
4458 obj
->base
.size
, align
);
4460 DRM_ERROR("failed to init phys object %d size: %zu\n",
4461 id
, obj
->base
.size
);
4466 /* bind to the object */
4467 obj
->phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
4468 obj
->phys_obj
->cur_obj
= obj
;
4470 page_count
= obj
->base
.size
/ PAGE_SIZE
;
4472 for (i
= 0; i
< page_count
; i
++) {
4476 page
= shmem_read_mapping_page(mapping
, i
);
4478 return PTR_ERR(page
);
4480 src
= kmap_atomic(page
);
4481 dst
= obj
->phys_obj
->handle
->vaddr
+ (i
* PAGE_SIZE
);
4482 memcpy(dst
, src
, PAGE_SIZE
);
4485 mark_page_accessed(page
);
4486 page_cache_release(page
);
4493 i915_gem_phys_pwrite(struct drm_device
*dev
,
4494 struct drm_i915_gem_object
*obj
,
4495 struct drm_i915_gem_pwrite
*args
,
4496 struct drm_file
*file_priv
)
4498 void *vaddr
= obj
->phys_obj
->handle
->vaddr
+ args
->offset
;
4499 char __user
*user_data
= to_user_ptr(args
->data_ptr
);
4501 if (__copy_from_user_inatomic_nocache(vaddr
, user_data
, args
->size
)) {
4502 unsigned long unwritten
;
4504 /* The physical object once assigned is fixed for the lifetime
4505 * of the obj, so we can safely drop the lock and continue
4508 mutex_unlock(&dev
->struct_mutex
);
4509 unwritten
= copy_from_user(vaddr
, user_data
, args
->size
);
4510 mutex_lock(&dev
->struct_mutex
);
4515 i915_gem_chipset_flush(dev
);
4519 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
)
4521 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
4523 /* Clean up our request list when the client is going away, so that
4524 * later retire_requests won't dereference our soon-to-be-gone
4527 spin_lock(&file_priv
->mm
.lock
);
4528 while (!list_empty(&file_priv
->mm
.request_list
)) {
4529 struct drm_i915_gem_request
*request
;
4531 request
= list_first_entry(&file_priv
->mm
.request_list
,
4532 struct drm_i915_gem_request
,
4534 list_del(&request
->client_list
);
4535 request
->file_priv
= NULL
;
4537 spin_unlock(&file_priv
->mm
.lock
);
4540 static bool mutex_is_locked_by(struct mutex
*mutex
, struct task_struct
*task
)
4542 if (!mutex_is_locked(mutex
))
4545 #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES)
4546 return mutex
->owner
== task
;
4548 /* Since UP may be pre-empted, we cannot assume that we own the lock */
4554 i915_gem_inactive_shrink(struct shrinker
*shrinker
, struct shrink_control
*sc
)
4556 struct drm_i915_private
*dev_priv
=
4557 container_of(shrinker
,
4558 struct drm_i915_private
,
4559 mm
.inactive_shrinker
);
4560 struct drm_device
*dev
= dev_priv
->dev
;
4561 struct drm_i915_gem_object
*obj
;
4562 int nr_to_scan
= sc
->nr_to_scan
;
4566 if (!mutex_trylock(&dev
->struct_mutex
)) {
4567 if (!mutex_is_locked_by(&dev
->struct_mutex
, current
))
4570 if (dev_priv
->mm
.shrinker_no_lock_stealing
)
4577 nr_to_scan
-= i915_gem_purge(dev_priv
, nr_to_scan
);
4579 nr_to_scan
-= __i915_gem_shrink(dev_priv
, nr_to_scan
,
4582 i915_gem_shrink_all(dev_priv
);
4586 list_for_each_entry(obj
, &dev_priv
->mm
.unbound_list
, global_list
)
4587 if (obj
->pages_pin_count
== 0)
4588 cnt
+= obj
->base
.size
>> PAGE_SHIFT
;
4589 list_for_each_entry(obj
, &dev_priv
->mm
.inactive_list
, mm_list
)
4590 if (obj
->pin_count
== 0 && obj
->pages_pin_count
== 0)
4591 cnt
+= obj
->base
.size
>> PAGE_SHIFT
;
4594 mutex_unlock(&dev
->struct_mutex
);