2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/shmem_fs.h>
35 #include <linux/slab.h>
36 #include <linux/swap.h>
37 #include <linux/pci.h>
39 static __must_check
int i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object
*obj
);
40 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
);
41 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
);
42 static __must_check
int i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
,
44 static __must_check
int i915_gem_object_set_cpu_read_domain_range(struct drm_i915_gem_object
*obj
,
47 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_i915_gem_object
*obj
);
48 static __must_check
int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object
*obj
,
50 bool map_and_fenceable
);
51 static void i915_gem_clear_fence_reg(struct drm_device
*dev
,
52 struct drm_i915_fence_reg
*reg
);
53 static int i915_gem_phys_pwrite(struct drm_device
*dev
,
54 struct drm_i915_gem_object
*obj
,
55 struct drm_i915_gem_pwrite
*args
,
56 struct drm_file
*file
);
57 static void i915_gem_free_object_tail(struct drm_i915_gem_object
*obj
);
59 static int i915_gem_inactive_shrink(struct shrinker
*shrinker
,
60 struct shrink_control
*sc
);
61 static void i915_gem_object_truncate(struct drm_i915_gem_object
*obj
);
63 /* some bookkeeping */
64 static void i915_gem_info_add_obj(struct drm_i915_private
*dev_priv
,
67 dev_priv
->mm
.object_count
++;
68 dev_priv
->mm
.object_memory
+= size
;
71 static void i915_gem_info_remove_obj(struct drm_i915_private
*dev_priv
,
74 dev_priv
->mm
.object_count
--;
75 dev_priv
->mm
.object_memory
-= size
;
79 i915_gem_wait_for_error(struct drm_device
*dev
)
81 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
82 struct completion
*x
= &dev_priv
->error_completion
;
86 if (!atomic_read(&dev_priv
->mm
.wedged
))
89 ret
= wait_for_completion_interruptible(x
);
93 if (atomic_read(&dev_priv
->mm
.wedged
)) {
94 /* GPU is hung, bump the completion count to account for
95 * the token we just consumed so that we never hit zero and
96 * end up waiting upon a subsequent completion event that
99 spin_lock_irqsave(&x
->wait
.lock
, flags
);
101 spin_unlock_irqrestore(&x
->wait
.lock
, flags
);
106 int i915_mutex_lock_interruptible(struct drm_device
*dev
)
110 ret
= i915_gem_wait_for_error(dev
);
114 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
118 WARN_ON(i915_verify_lists(dev
));
123 i915_gem_object_is_inactive(struct drm_i915_gem_object
*obj
)
125 return obj
->gtt_space
&& !obj
->active
&& obj
->pin_count
== 0;
128 void i915_gem_do_init(struct drm_device
*dev
,
130 unsigned long mappable_end
,
133 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
135 drm_mm_init(&dev_priv
->mm
.gtt_space
, start
, end
- start
);
137 dev_priv
->mm
.gtt_start
= start
;
138 dev_priv
->mm
.gtt_mappable_end
= mappable_end
;
139 dev_priv
->mm
.gtt_end
= end
;
140 dev_priv
->mm
.gtt_total
= end
- start
;
141 dev_priv
->mm
.mappable_gtt_total
= min(end
, mappable_end
) - start
;
143 /* Take over this portion of the GTT */
144 intel_gtt_clear_range(start
/ PAGE_SIZE
, (end
-start
) / PAGE_SIZE
);
148 i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
149 struct drm_file
*file
)
151 struct drm_i915_gem_init
*args
= data
;
153 if (args
->gtt_start
>= args
->gtt_end
||
154 (args
->gtt_end
| args
->gtt_start
) & (PAGE_SIZE
- 1))
157 mutex_lock(&dev
->struct_mutex
);
158 i915_gem_do_init(dev
, args
->gtt_start
, args
->gtt_end
, args
->gtt_end
);
159 mutex_unlock(&dev
->struct_mutex
);
165 i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
166 struct drm_file
*file
)
168 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
169 struct drm_i915_gem_get_aperture
*args
= data
;
170 struct drm_i915_gem_object
*obj
;
173 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
177 mutex_lock(&dev
->struct_mutex
);
178 list_for_each_entry(obj
, &dev_priv
->mm
.pinned_list
, mm_list
)
179 pinned
+= obj
->gtt_space
->size
;
180 mutex_unlock(&dev
->struct_mutex
);
182 args
->aper_size
= dev_priv
->mm
.gtt_total
;
183 args
->aper_available_size
= args
->aper_size
- pinned
;
189 i915_gem_create(struct drm_file
*file
,
190 struct drm_device
*dev
,
194 struct drm_i915_gem_object
*obj
;
198 size
= roundup(size
, PAGE_SIZE
);
202 /* Allocate the new object */
203 obj
= i915_gem_alloc_object(dev
, size
);
207 ret
= drm_gem_handle_create(file
, &obj
->base
, &handle
);
209 drm_gem_object_release(&obj
->base
);
210 i915_gem_info_remove_obj(dev
->dev_private
, obj
->base
.size
);
215 /* drop reference from allocate - handle holds it now */
216 drm_gem_object_unreference(&obj
->base
);
217 trace_i915_gem_object_create(obj
);
224 i915_gem_dumb_create(struct drm_file
*file
,
225 struct drm_device
*dev
,
226 struct drm_mode_create_dumb
*args
)
228 /* have to work out size/pitch and return them */
229 args
->pitch
= ALIGN(args
->width
* ((args
->bpp
+ 7) / 8), 64);
230 args
->size
= args
->pitch
* args
->height
;
231 return i915_gem_create(file
, dev
,
232 args
->size
, &args
->handle
);
235 int i915_gem_dumb_destroy(struct drm_file
*file
,
236 struct drm_device
*dev
,
239 return drm_gem_handle_delete(file
, handle
);
243 * Creates a new mm object and returns a handle to it.
246 i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
247 struct drm_file
*file
)
249 struct drm_i915_gem_create
*args
= data
;
250 return i915_gem_create(file
, dev
,
251 args
->size
, &args
->handle
);
254 static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object
*obj
)
256 drm_i915_private_t
*dev_priv
= obj
->base
.dev
->dev_private
;
258 return dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_9_10_17
&&
259 obj
->tiling_mode
!= I915_TILING_NONE
;
263 * This is the fast shmem pread path, which attempts to copy_from_user directly
264 * from the backing pages of the object to the user's address space. On a
265 * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
268 i915_gem_shmem_pread_fast(struct drm_device
*dev
,
269 struct drm_i915_gem_object
*obj
,
270 struct drm_i915_gem_pread
*args
,
271 struct drm_file
*file
)
273 struct address_space
*mapping
= obj
->base
.filp
->f_path
.dentry
->d_inode
->i_mapping
;
276 char __user
*user_data
;
277 int page_offset
, page_length
;
279 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
282 offset
= args
->offset
;
289 /* Operation in this page
291 * page_offset = offset within page
292 * page_length = bytes to copy for this page
294 page_offset
= offset_in_page(offset
);
295 page_length
= remain
;
296 if ((page_offset
+ remain
) > PAGE_SIZE
)
297 page_length
= PAGE_SIZE
- page_offset
;
299 page
= shmem_read_mapping_page(mapping
, offset
>> PAGE_SHIFT
);
301 return PTR_ERR(page
);
303 vaddr
= kmap_atomic(page
);
304 ret
= __copy_to_user_inatomic(user_data
,
307 kunmap_atomic(vaddr
);
309 mark_page_accessed(page
);
310 page_cache_release(page
);
314 remain
-= page_length
;
315 user_data
+= page_length
;
316 offset
+= page_length
;
323 __copy_to_user_swizzled(char __user
*cpu_vaddr
,
324 const char *gpu_vaddr
, int gpu_offset
,
327 int ret
, cpu_offset
= 0;
330 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
331 int this_length
= min(cacheline_end
- gpu_offset
, length
);
332 int swizzled_gpu_offset
= gpu_offset
^ 64;
334 ret
= __copy_to_user(cpu_vaddr
+ cpu_offset
,
335 gpu_vaddr
+ swizzled_gpu_offset
,
340 cpu_offset
+= this_length
;
341 gpu_offset
+= this_length
;
342 length
-= this_length
;
349 __copy_from_user_swizzled(char __user
*gpu_vaddr
, int gpu_offset
,
350 const char *cpu_vaddr
,
353 int ret
, cpu_offset
= 0;
356 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
357 int this_length
= min(cacheline_end
- gpu_offset
, length
);
358 int swizzled_gpu_offset
= gpu_offset
^ 64;
360 ret
= __copy_from_user(gpu_vaddr
+ swizzled_gpu_offset
,
361 cpu_vaddr
+ cpu_offset
,
366 cpu_offset
+= this_length
;
367 gpu_offset
+= this_length
;
368 length
-= this_length
;
375 * This is the fallback shmem pread path, which allocates temporary storage
376 * in kernel space to copy_to_user into outside of the struct_mutex, so we
377 * can copy out of the object's backing pages while holding the struct mutex
378 * and not take page faults.
381 i915_gem_shmem_pread_slow(struct drm_device
*dev
,
382 struct drm_i915_gem_object
*obj
,
383 struct drm_i915_gem_pread
*args
,
384 struct drm_file
*file
)
386 struct address_space
*mapping
= obj
->base
.filp
->f_path
.dentry
->d_inode
->i_mapping
;
387 char __user
*user_data
;
390 int shmem_page_offset
, page_length
, ret
;
391 int obj_do_bit17_swizzling
, page_do_bit17_swizzling
;
393 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
396 obj_do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
398 offset
= args
->offset
;
400 mutex_unlock(&dev
->struct_mutex
);
406 /* Operation in this page
408 * shmem_page_offset = offset within page in shmem file
409 * page_length = bytes to copy for this page
411 shmem_page_offset
= offset_in_page(offset
);
412 page_length
= remain
;
413 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
414 page_length
= PAGE_SIZE
- shmem_page_offset
;
416 page
= shmem_read_mapping_page(mapping
, offset
>> PAGE_SHIFT
);
422 page_do_bit17_swizzling
= obj_do_bit17_swizzling
&&
423 (page_to_phys(page
) & (1 << 17)) != 0;
426 if (page_do_bit17_swizzling
)
427 ret
= __copy_to_user_swizzled(user_data
,
428 vaddr
, shmem_page_offset
,
431 ret
= __copy_to_user(user_data
,
432 vaddr
+ shmem_page_offset
,
436 mark_page_accessed(page
);
437 page_cache_release(page
);
444 remain
-= page_length
;
445 user_data
+= page_length
;
446 offset
+= page_length
;
450 mutex_lock(&dev
->struct_mutex
);
451 /* Fixup: Kill any reinstated backing storage pages */
452 if (obj
->madv
== __I915_MADV_PURGED
)
453 i915_gem_object_truncate(obj
);
459 * Reads data from the object referenced by handle.
461 * On error, the contents of *data are undefined.
464 i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
465 struct drm_file
*file
)
467 struct drm_i915_gem_pread
*args
= data
;
468 struct drm_i915_gem_object
*obj
;
474 if (!access_ok(VERIFY_WRITE
,
475 (char __user
*)(uintptr_t)args
->data_ptr
,
479 ret
= fault_in_pages_writeable((char __user
*)(uintptr_t)args
->data_ptr
,
484 ret
= i915_mutex_lock_interruptible(dev
);
488 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
489 if (&obj
->base
== NULL
) {
494 /* Bounds check source. */
495 if (args
->offset
> obj
->base
.size
||
496 args
->size
> obj
->base
.size
- args
->offset
) {
501 trace_i915_gem_object_pread(obj
, args
->offset
, args
->size
);
503 ret
= i915_gem_object_set_cpu_read_domain_range(obj
,
510 if (!i915_gem_object_needs_bit17_swizzle(obj
))
511 ret
= i915_gem_shmem_pread_fast(dev
, obj
, args
, file
);
513 ret
= i915_gem_shmem_pread_slow(dev
, obj
, args
, file
);
516 drm_gem_object_unreference(&obj
->base
);
518 mutex_unlock(&dev
->struct_mutex
);
522 /* This is the fast write path which cannot handle
523 * page faults in the source data
527 fast_user_write(struct io_mapping
*mapping
,
528 loff_t page_base
, int page_offset
,
529 char __user
*user_data
,
533 unsigned long unwritten
;
535 vaddr_atomic
= io_mapping_map_atomic_wc(mapping
, page_base
);
536 unwritten
= __copy_from_user_inatomic_nocache(vaddr_atomic
+ page_offset
,
538 io_mapping_unmap_atomic(vaddr_atomic
);
542 /* Here's the write path which can sleep for
547 slow_kernel_write(struct io_mapping
*mapping
,
548 loff_t gtt_base
, int gtt_offset
,
549 struct page
*user_page
, int user_offset
,
552 char __iomem
*dst_vaddr
;
555 dst_vaddr
= io_mapping_map_wc(mapping
, gtt_base
);
556 src_vaddr
= kmap(user_page
);
558 memcpy_toio(dst_vaddr
+ gtt_offset
,
559 src_vaddr
+ user_offset
,
563 io_mapping_unmap(dst_vaddr
);
567 * This is the fast pwrite path, where we copy the data directly from the
568 * user into the GTT, uncached.
571 i915_gem_gtt_pwrite_fast(struct drm_device
*dev
,
572 struct drm_i915_gem_object
*obj
,
573 struct drm_i915_gem_pwrite
*args
,
574 struct drm_file
*file
)
576 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
578 loff_t offset
, page_base
;
579 char __user
*user_data
;
580 int page_offset
, page_length
;
582 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
585 offset
= obj
->gtt_offset
+ args
->offset
;
588 /* Operation in this page
590 * page_base = page offset within aperture
591 * page_offset = offset within page
592 * page_length = bytes to copy for this page
594 page_base
= offset
& PAGE_MASK
;
595 page_offset
= offset_in_page(offset
);
596 page_length
= remain
;
597 if ((page_offset
+ remain
) > PAGE_SIZE
)
598 page_length
= PAGE_SIZE
- page_offset
;
600 /* If we get a fault while copying data, then (presumably) our
601 * source page isn't available. Return the error and we'll
602 * retry in the slow path.
604 if (fast_user_write(dev_priv
->mm
.gtt_mapping
, page_base
,
605 page_offset
, user_data
, page_length
))
608 remain
-= page_length
;
609 user_data
+= page_length
;
610 offset
+= page_length
;
617 * This is the fallback GTT pwrite path, which uses get_user_pages to pin
618 * the memory and maps it using kmap_atomic for copying.
620 * This code resulted in x11perf -rgb10text consuming about 10% more CPU
621 * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
624 i915_gem_gtt_pwrite_slow(struct drm_device
*dev
,
625 struct drm_i915_gem_object
*obj
,
626 struct drm_i915_gem_pwrite
*args
,
627 struct drm_file
*file
)
629 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
631 loff_t gtt_page_base
, offset
;
632 loff_t first_data_page
, last_data_page
, num_pages
;
633 loff_t pinned_pages
, i
;
634 struct page
**user_pages
;
635 struct mm_struct
*mm
= current
->mm
;
636 int gtt_page_offset
, data_page_offset
, data_page_index
, page_length
;
638 uint64_t data_ptr
= args
->data_ptr
;
642 /* Pin the user pages containing the data. We can't fault while
643 * holding the struct mutex, and all of the pwrite implementations
644 * want to hold it while dereferencing the user data.
646 first_data_page
= data_ptr
/ PAGE_SIZE
;
647 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
648 num_pages
= last_data_page
- first_data_page
+ 1;
650 user_pages
= drm_malloc_ab(num_pages
, sizeof(struct page
*));
651 if (user_pages
== NULL
)
654 mutex_unlock(&dev
->struct_mutex
);
655 down_read(&mm
->mmap_sem
);
656 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
657 num_pages
, 0, 0, user_pages
, NULL
);
658 up_read(&mm
->mmap_sem
);
659 mutex_lock(&dev
->struct_mutex
);
660 if (pinned_pages
< num_pages
) {
662 goto out_unpin_pages
;
665 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
667 goto out_unpin_pages
;
669 ret
= i915_gem_object_put_fence(obj
);
671 goto out_unpin_pages
;
673 offset
= obj
->gtt_offset
+ args
->offset
;
676 /* Operation in this page
678 * gtt_page_base = page offset within aperture
679 * gtt_page_offset = offset within page in aperture
680 * data_page_index = page number in get_user_pages return
681 * data_page_offset = offset with data_page_index page.
682 * page_length = bytes to copy for this page
684 gtt_page_base
= offset
& PAGE_MASK
;
685 gtt_page_offset
= offset_in_page(offset
);
686 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
687 data_page_offset
= offset_in_page(data_ptr
);
689 page_length
= remain
;
690 if ((gtt_page_offset
+ page_length
) > PAGE_SIZE
)
691 page_length
= PAGE_SIZE
- gtt_page_offset
;
692 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
693 page_length
= PAGE_SIZE
- data_page_offset
;
695 slow_kernel_write(dev_priv
->mm
.gtt_mapping
,
696 gtt_page_base
, gtt_page_offset
,
697 user_pages
[data_page_index
],
701 remain
-= page_length
;
702 offset
+= page_length
;
703 data_ptr
+= page_length
;
707 for (i
= 0; i
< pinned_pages
; i
++)
708 page_cache_release(user_pages
[i
]);
709 drm_free_large(user_pages
);
715 * This is the fast shmem pwrite path, which attempts to directly
716 * copy_from_user into the kmapped pages backing the object.
719 i915_gem_shmem_pwrite_fast(struct drm_device
*dev
,
720 struct drm_i915_gem_object
*obj
,
721 struct drm_i915_gem_pwrite
*args
,
722 struct drm_file
*file
)
724 struct address_space
*mapping
= obj
->base
.filp
->f_path
.dentry
->d_inode
->i_mapping
;
727 char __user
*user_data
;
728 int page_offset
, page_length
;
730 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
733 offset
= args
->offset
;
741 /* Operation in this page
743 * page_offset = offset within page
744 * page_length = bytes to copy for this page
746 page_offset
= offset_in_page(offset
);
747 page_length
= remain
;
748 if ((page_offset
+ remain
) > PAGE_SIZE
)
749 page_length
= PAGE_SIZE
- page_offset
;
751 page
= shmem_read_mapping_page(mapping
, offset
>> PAGE_SHIFT
);
753 return PTR_ERR(page
);
755 vaddr
= kmap_atomic(page
);
756 ret
= __copy_from_user_inatomic(vaddr
+ page_offset
,
759 kunmap_atomic(vaddr
);
761 set_page_dirty(page
);
762 mark_page_accessed(page
);
763 page_cache_release(page
);
765 /* If we get a fault while copying data, then (presumably) our
766 * source page isn't available. Return the error and we'll
767 * retry in the slow path.
772 remain
-= page_length
;
773 user_data
+= page_length
;
774 offset
+= page_length
;
781 * This is the fallback shmem pwrite path, which uses get_user_pages to pin
782 * the memory and maps it using kmap_atomic for copying.
784 * This avoids taking mmap_sem for faulting on the user's address while the
785 * struct_mutex is held.
788 i915_gem_shmem_pwrite_slow(struct drm_device
*dev
,
789 struct drm_i915_gem_object
*obj
,
790 struct drm_i915_gem_pwrite
*args
,
791 struct drm_file
*file
)
793 struct address_space
*mapping
= obj
->base
.filp
->f_path
.dentry
->d_inode
->i_mapping
;
796 char __user
*user_data
;
797 int shmem_page_offset
, page_length
, ret
;
798 int obj_do_bit17_swizzling
, page_do_bit17_swizzling
;
800 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
803 obj_do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
805 offset
= args
->offset
;
808 mutex_unlock(&dev
->struct_mutex
);
814 /* Operation in this page
816 * shmem_page_offset = offset within page in shmem file
817 * page_length = bytes to copy for this page
819 shmem_page_offset
= offset_in_page(offset
);
821 page_length
= remain
;
822 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
823 page_length
= PAGE_SIZE
- shmem_page_offset
;
825 page
= shmem_read_mapping_page(mapping
, offset
>> PAGE_SHIFT
);
831 page_do_bit17_swizzling
= obj_do_bit17_swizzling
&&
832 (page_to_phys(page
) & (1 << 17)) != 0;
835 if (page_do_bit17_swizzling
)
836 ret
= __copy_from_user_swizzled(vaddr
, shmem_page_offset
,
840 ret
= __copy_from_user(vaddr
+ shmem_page_offset
,
845 set_page_dirty(page
);
846 mark_page_accessed(page
);
847 page_cache_release(page
);
854 remain
-= page_length
;
855 user_data
+= page_length
;
856 offset
+= page_length
;
860 mutex_lock(&dev
->struct_mutex
);
861 /* Fixup: Kill any reinstated backing storage pages */
862 if (obj
->madv
== __I915_MADV_PURGED
)
863 i915_gem_object_truncate(obj
);
864 /* and flush dirty cachelines in case the object isn't in the cpu write
866 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
867 i915_gem_clflush_object(obj
);
868 intel_gtt_chipset_flush();
875 * Writes data to the object referenced by handle.
877 * On error, the contents of the buffer that were to be modified are undefined.
880 i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
881 struct drm_file
*file
)
883 struct drm_i915_gem_pwrite
*args
= data
;
884 struct drm_i915_gem_object
*obj
;
890 if (!access_ok(VERIFY_READ
,
891 (char __user
*)(uintptr_t)args
->data_ptr
,
895 ret
= fault_in_pages_readable((char __user
*)(uintptr_t)args
->data_ptr
,
900 ret
= i915_mutex_lock_interruptible(dev
);
904 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
905 if (&obj
->base
== NULL
) {
910 /* Bounds check destination. */
911 if (args
->offset
> obj
->base
.size
||
912 args
->size
> obj
->base
.size
- args
->offset
) {
917 trace_i915_gem_object_pwrite(obj
, args
->offset
, args
->size
);
919 /* We can only do the GTT pwrite on untiled buffers, as otherwise
920 * it would end up going through the fenced access, and we'll get
921 * different detiling behavior between reading and writing.
922 * pread/pwrite currently are reading and writing from the CPU
923 * perspective, requiring manual detiling by the client.
926 ret
= i915_gem_phys_pwrite(dev
, obj
, args
, file
);
930 if (obj
->gtt_space
&&
931 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
932 ret
= i915_gem_object_pin(obj
, 0, true);
936 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
940 ret
= i915_gem_object_put_fence(obj
);
944 ret
= i915_gem_gtt_pwrite_fast(dev
, obj
, args
, file
);
946 ret
= i915_gem_gtt_pwrite_slow(dev
, obj
, args
, file
);
949 i915_gem_object_unpin(obj
);
953 /* Fall through to the shmfs paths because the gtt paths might
954 * fail with non-page-backed user pointers (e.g. gtt mappings
955 * when moving data between textures). */
958 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
963 if (!i915_gem_object_needs_bit17_swizzle(obj
))
964 ret
= i915_gem_shmem_pwrite_fast(dev
, obj
, args
, file
);
966 ret
= i915_gem_shmem_pwrite_slow(dev
, obj
, args
, file
);
969 drm_gem_object_unreference(&obj
->base
);
971 mutex_unlock(&dev
->struct_mutex
);
976 * Called when user space prepares to use an object with the CPU, either
977 * through the mmap ioctl's mapping or a GTT mapping.
980 i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
981 struct drm_file
*file
)
983 struct drm_i915_gem_set_domain
*args
= data
;
984 struct drm_i915_gem_object
*obj
;
985 uint32_t read_domains
= args
->read_domains
;
986 uint32_t write_domain
= args
->write_domain
;
989 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
992 /* Only handle setting domains to types used by the CPU. */
993 if (write_domain
& I915_GEM_GPU_DOMAINS
)
996 if (read_domains
& I915_GEM_GPU_DOMAINS
)
999 /* Having something in the write domain implies it's in the read
1000 * domain, and only that read domain. Enforce that in the request.
1002 if (write_domain
!= 0 && read_domains
!= write_domain
)
1005 ret
= i915_mutex_lock_interruptible(dev
);
1009 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1010 if (&obj
->base
== NULL
) {
1015 if (read_domains
& I915_GEM_DOMAIN_GTT
) {
1016 ret
= i915_gem_object_set_to_gtt_domain(obj
, write_domain
!= 0);
1018 /* Silently promote "you're not bound, there was nothing to do"
1019 * to success, since the client was just asking us to
1020 * make sure everything was done.
1025 ret
= i915_gem_object_set_to_cpu_domain(obj
, write_domain
!= 0);
1028 drm_gem_object_unreference(&obj
->base
);
1030 mutex_unlock(&dev
->struct_mutex
);
1035 * Called when user space has done writes to this buffer
1038 i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1039 struct drm_file
*file
)
1041 struct drm_i915_gem_sw_finish
*args
= data
;
1042 struct drm_i915_gem_object
*obj
;
1045 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1048 ret
= i915_mutex_lock_interruptible(dev
);
1052 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1053 if (&obj
->base
== NULL
) {
1058 /* Pinned buffers may be scanout, so flush the cache */
1060 i915_gem_object_flush_cpu_write_domain(obj
);
1062 drm_gem_object_unreference(&obj
->base
);
1064 mutex_unlock(&dev
->struct_mutex
);
1069 * Maps the contents of an object, returning the address it is mapped
1072 * While the mapping holds a reference on the contents of the object, it doesn't
1073 * imply a ref on the object itself.
1076 i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1077 struct drm_file
*file
)
1079 struct drm_i915_gem_mmap
*args
= data
;
1080 struct drm_gem_object
*obj
;
1083 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1086 obj
= drm_gem_object_lookup(dev
, file
, args
->handle
);
1090 down_write(¤t
->mm
->mmap_sem
);
1091 addr
= do_mmap(obj
->filp
, 0, args
->size
,
1092 PROT_READ
| PROT_WRITE
, MAP_SHARED
,
1094 up_write(¤t
->mm
->mmap_sem
);
1095 drm_gem_object_unreference_unlocked(obj
);
1096 if (IS_ERR((void *)addr
))
1099 args
->addr_ptr
= (uint64_t) addr
;
1105 * i915_gem_fault - fault a page into the GTT
1106 * vma: VMA in question
1109 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1110 * from userspace. The fault handler takes care of binding the object to
1111 * the GTT (if needed), allocating and programming a fence register (again,
1112 * only if needed based on whether the old reg is still valid or the object
1113 * is tiled) and inserting a new PTE into the faulting process.
1115 * Note that the faulting process may involve evicting existing objects
1116 * from the GTT and/or fence registers to make room. So performance may
1117 * suffer if the GTT working set is large or there are few fence registers
1120 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
)
1122 struct drm_i915_gem_object
*obj
= to_intel_bo(vma
->vm_private_data
);
1123 struct drm_device
*dev
= obj
->base
.dev
;
1124 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1125 pgoff_t page_offset
;
1128 bool write
= !!(vmf
->flags
& FAULT_FLAG_WRITE
);
1130 /* We don't use vmf->pgoff since that has the fake offset */
1131 page_offset
= ((unsigned long)vmf
->virtual_address
- vma
->vm_start
) >>
1134 ret
= i915_mutex_lock_interruptible(dev
);
1138 trace_i915_gem_object_fault(obj
, page_offset
, true, write
);
1140 /* Now bind it into the GTT if needed */
1141 if (!obj
->map_and_fenceable
) {
1142 ret
= i915_gem_object_unbind(obj
);
1146 if (!obj
->gtt_space
) {
1147 ret
= i915_gem_object_bind_to_gtt(obj
, 0, true);
1151 ret
= i915_gem_object_set_to_gtt_domain(obj
, write
);
1156 if (obj
->tiling_mode
== I915_TILING_NONE
)
1157 ret
= i915_gem_object_put_fence(obj
);
1159 ret
= i915_gem_object_get_fence(obj
, NULL
);
1163 if (i915_gem_object_is_inactive(obj
))
1164 list_move_tail(&obj
->mm_list
, &dev_priv
->mm
.inactive_list
);
1166 obj
->fault_mappable
= true;
1168 pfn
= ((dev
->agp
->base
+ obj
->gtt_offset
) >> PAGE_SHIFT
) +
1171 /* Finally, remap it using the new GTT offset */
1172 ret
= vm_insert_pfn(vma
, (unsigned long)vmf
->virtual_address
, pfn
);
1174 mutex_unlock(&dev
->struct_mutex
);
1179 /* Give the error handler a chance to run and move the
1180 * objects off the GPU active list. Next time we service the
1181 * fault, we should be able to transition the page into the
1182 * GTT without touching the GPU (and so avoid further
1183 * EIO/EGAIN). If the GPU is wedged, then there is no issue
1184 * with coherency, just lost writes.
1190 return VM_FAULT_NOPAGE
;
1192 return VM_FAULT_OOM
;
1194 return VM_FAULT_SIGBUS
;
1199 * i915_gem_release_mmap - remove physical page mappings
1200 * @obj: obj in question
1202 * Preserve the reservation of the mmapping with the DRM core code, but
1203 * relinquish ownership of the pages back to the system.
1205 * It is vital that we remove the page mapping if we have mapped a tiled
1206 * object through the GTT and then lose the fence register due to
1207 * resource pressure. Similarly if the object has been moved out of the
1208 * aperture, than pages mapped into userspace must be revoked. Removing the
1209 * mapping will then trigger a page fault on the next user access, allowing
1210 * fixup by i915_gem_fault().
1213 i915_gem_release_mmap(struct drm_i915_gem_object
*obj
)
1215 if (!obj
->fault_mappable
)
1218 if (obj
->base
.dev
->dev_mapping
)
1219 unmap_mapping_range(obj
->base
.dev
->dev_mapping
,
1220 (loff_t
)obj
->base
.map_list
.hash
.key
<<PAGE_SHIFT
,
1223 obj
->fault_mappable
= false;
1227 i915_gem_get_gtt_size(struct drm_device
*dev
, uint32_t size
, int tiling_mode
)
1231 if (INTEL_INFO(dev
)->gen
>= 4 ||
1232 tiling_mode
== I915_TILING_NONE
)
1235 /* Previous chips need a power-of-two fence region when tiling */
1236 if (INTEL_INFO(dev
)->gen
== 3)
1237 gtt_size
= 1024*1024;
1239 gtt_size
= 512*1024;
1241 while (gtt_size
< size
)
1248 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1249 * @obj: object to check
1251 * Return the required GTT alignment for an object, taking into account
1252 * potential fence register mapping.
1255 i915_gem_get_gtt_alignment(struct drm_device
*dev
,
1260 * Minimum alignment is 4k (GTT page size), but might be greater
1261 * if a fence register is needed for the object.
1263 if (INTEL_INFO(dev
)->gen
>= 4 ||
1264 tiling_mode
== I915_TILING_NONE
)
1268 * Previous chips need to be aligned to the size of the smallest
1269 * fence register that can contain the object.
1271 return i915_gem_get_gtt_size(dev
, size
, tiling_mode
);
1275 * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an
1278 * @size: size of the object
1279 * @tiling_mode: tiling mode of the object
1281 * Return the required GTT alignment for an object, only taking into account
1282 * unfenced tiled surface requirements.
1285 i915_gem_get_unfenced_gtt_alignment(struct drm_device
*dev
,
1290 * Minimum alignment is 4k (GTT page size) for sane hw.
1292 if (INTEL_INFO(dev
)->gen
>= 4 || IS_G33(dev
) ||
1293 tiling_mode
== I915_TILING_NONE
)
1296 /* Previous hardware however needs to be aligned to a power-of-two
1297 * tile height. The simplest method for determining this is to reuse
1298 * the power-of-tile object size.
1300 return i915_gem_get_gtt_size(dev
, size
, tiling_mode
);
1304 i915_gem_mmap_gtt(struct drm_file
*file
,
1305 struct drm_device
*dev
,
1309 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1310 struct drm_i915_gem_object
*obj
;
1313 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1316 ret
= i915_mutex_lock_interruptible(dev
);
1320 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, handle
));
1321 if (&obj
->base
== NULL
) {
1326 if (obj
->base
.size
> dev_priv
->mm
.gtt_mappable_end
) {
1331 if (obj
->madv
!= I915_MADV_WILLNEED
) {
1332 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1337 if (!obj
->base
.map_list
.map
) {
1338 ret
= drm_gem_create_mmap_offset(&obj
->base
);
1343 *offset
= (u64
)obj
->base
.map_list
.hash
.key
<< PAGE_SHIFT
;
1346 drm_gem_object_unreference(&obj
->base
);
1348 mutex_unlock(&dev
->struct_mutex
);
1353 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1355 * @data: GTT mapping ioctl data
1356 * @file: GEM object info
1358 * Simply returns the fake offset to userspace so it can mmap it.
1359 * The mmap call will end up in drm_gem_mmap(), which will set things
1360 * up so we can get faults in the handler above.
1362 * The fault handler will take care of binding the object into the GTT
1363 * (since it may have been evicted to make room for something), allocating
1364 * a fence register, and mapping the appropriate aperture address into
1368 i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
1369 struct drm_file
*file
)
1371 struct drm_i915_gem_mmap_gtt
*args
= data
;
1373 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1376 return i915_gem_mmap_gtt(file
, dev
, args
->handle
, &args
->offset
);
1381 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object
*obj
,
1385 struct address_space
*mapping
;
1386 struct inode
*inode
;
1389 /* Get the list of pages out of our struct file. They'll be pinned
1390 * at this point until we release them.
1392 page_count
= obj
->base
.size
/ PAGE_SIZE
;
1393 BUG_ON(obj
->pages
!= NULL
);
1394 obj
->pages
= drm_malloc_ab(page_count
, sizeof(struct page
*));
1395 if (obj
->pages
== NULL
)
1398 inode
= obj
->base
.filp
->f_path
.dentry
->d_inode
;
1399 mapping
= inode
->i_mapping
;
1400 gfpmask
|= mapping_gfp_mask(mapping
);
1402 for (i
= 0; i
< page_count
; i
++) {
1403 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfpmask
);
1407 obj
->pages
[i
] = page
;
1410 if (i915_gem_object_needs_bit17_swizzle(obj
))
1411 i915_gem_object_do_bit_17_swizzle(obj
);
1417 page_cache_release(obj
->pages
[i
]);
1419 drm_free_large(obj
->pages
);
1421 return PTR_ERR(page
);
1425 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object
*obj
)
1427 int page_count
= obj
->base
.size
/ PAGE_SIZE
;
1430 BUG_ON(obj
->madv
== __I915_MADV_PURGED
);
1432 if (i915_gem_object_needs_bit17_swizzle(obj
))
1433 i915_gem_object_save_bit_17_swizzle(obj
);
1435 if (obj
->madv
== I915_MADV_DONTNEED
)
1438 for (i
= 0; i
< page_count
; i
++) {
1440 set_page_dirty(obj
->pages
[i
]);
1442 if (obj
->madv
== I915_MADV_WILLNEED
)
1443 mark_page_accessed(obj
->pages
[i
]);
1445 page_cache_release(obj
->pages
[i
]);
1449 drm_free_large(obj
->pages
);
1454 i915_gem_object_move_to_active(struct drm_i915_gem_object
*obj
,
1455 struct intel_ring_buffer
*ring
,
1458 struct drm_device
*dev
= obj
->base
.dev
;
1459 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1461 BUG_ON(ring
== NULL
);
1464 /* Add a reference if we're newly entering the active list. */
1466 drm_gem_object_reference(&obj
->base
);
1470 /* Move from whatever list we were on to the tail of execution. */
1471 list_move_tail(&obj
->mm_list
, &dev_priv
->mm
.active_list
);
1472 list_move_tail(&obj
->ring_list
, &ring
->active_list
);
1474 obj
->last_rendering_seqno
= seqno
;
1475 if (obj
->fenced_gpu_access
) {
1476 struct drm_i915_fence_reg
*reg
;
1478 BUG_ON(obj
->fence_reg
== I915_FENCE_REG_NONE
);
1480 obj
->last_fenced_seqno
= seqno
;
1481 obj
->last_fenced_ring
= ring
;
1483 reg
= &dev_priv
->fence_regs
[obj
->fence_reg
];
1484 list_move_tail(®
->lru_list
, &dev_priv
->mm
.fence_list
);
1489 i915_gem_object_move_off_active(struct drm_i915_gem_object
*obj
)
1491 list_del_init(&obj
->ring_list
);
1492 obj
->last_rendering_seqno
= 0;
1496 i915_gem_object_move_to_flushing(struct drm_i915_gem_object
*obj
)
1498 struct drm_device
*dev
= obj
->base
.dev
;
1499 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1501 BUG_ON(!obj
->active
);
1502 list_move_tail(&obj
->mm_list
, &dev_priv
->mm
.flushing_list
);
1504 i915_gem_object_move_off_active(obj
);
1508 i915_gem_object_move_to_inactive(struct drm_i915_gem_object
*obj
)
1510 struct drm_device
*dev
= obj
->base
.dev
;
1511 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1513 if (obj
->pin_count
!= 0)
1514 list_move_tail(&obj
->mm_list
, &dev_priv
->mm
.pinned_list
);
1516 list_move_tail(&obj
->mm_list
, &dev_priv
->mm
.inactive_list
);
1518 BUG_ON(!list_empty(&obj
->gpu_write_list
));
1519 BUG_ON(!obj
->active
);
1522 i915_gem_object_move_off_active(obj
);
1523 obj
->fenced_gpu_access
= false;
1526 obj
->pending_gpu_write
= false;
1527 drm_gem_object_unreference(&obj
->base
);
1529 WARN_ON(i915_verify_lists(dev
));
1532 /* Immediately discard the backing storage */
1534 i915_gem_object_truncate(struct drm_i915_gem_object
*obj
)
1536 struct inode
*inode
;
1538 /* Our goal here is to return as much of the memory as
1539 * is possible back to the system as we are called from OOM.
1540 * To do this we must instruct the shmfs to drop all of its
1541 * backing pages, *now*.
1543 inode
= obj
->base
.filp
->f_path
.dentry
->d_inode
;
1544 shmem_truncate_range(inode
, 0, (loff_t
)-1);
1546 obj
->madv
= __I915_MADV_PURGED
;
1550 i915_gem_object_is_purgeable(struct drm_i915_gem_object
*obj
)
1552 return obj
->madv
== I915_MADV_DONTNEED
;
1556 i915_gem_process_flushing_list(struct intel_ring_buffer
*ring
,
1557 uint32_t flush_domains
)
1559 struct drm_i915_gem_object
*obj
, *next
;
1561 list_for_each_entry_safe(obj
, next
,
1562 &ring
->gpu_write_list
,
1564 if (obj
->base
.write_domain
& flush_domains
) {
1565 uint32_t old_write_domain
= obj
->base
.write_domain
;
1567 obj
->base
.write_domain
= 0;
1568 list_del_init(&obj
->gpu_write_list
);
1569 i915_gem_object_move_to_active(obj
, ring
,
1570 i915_gem_next_request_seqno(ring
));
1572 trace_i915_gem_object_change_domain(obj
,
1573 obj
->base
.read_domains
,
1580 i915_add_request(struct intel_ring_buffer
*ring
,
1581 struct drm_file
*file
,
1582 struct drm_i915_gem_request
*request
)
1584 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
1589 BUG_ON(request
== NULL
);
1591 ret
= ring
->add_request(ring
, &seqno
);
1595 trace_i915_gem_request_add(ring
, seqno
);
1597 request
->seqno
= seqno
;
1598 request
->ring
= ring
;
1599 request
->emitted_jiffies
= jiffies
;
1600 was_empty
= list_empty(&ring
->request_list
);
1601 list_add_tail(&request
->list
, &ring
->request_list
);
1604 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
1606 spin_lock(&file_priv
->mm
.lock
);
1607 request
->file_priv
= file_priv
;
1608 list_add_tail(&request
->client_list
,
1609 &file_priv
->mm
.request_list
);
1610 spin_unlock(&file_priv
->mm
.lock
);
1613 ring
->outstanding_lazy_request
= false;
1615 if (!dev_priv
->mm
.suspended
) {
1616 if (i915_enable_hangcheck
) {
1617 mod_timer(&dev_priv
->hangcheck_timer
,
1619 msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD
));
1622 queue_delayed_work(dev_priv
->wq
,
1623 &dev_priv
->mm
.retire_work
, HZ
);
1629 i915_gem_request_remove_from_client(struct drm_i915_gem_request
*request
)
1631 struct drm_i915_file_private
*file_priv
= request
->file_priv
;
1636 spin_lock(&file_priv
->mm
.lock
);
1637 if (request
->file_priv
) {
1638 list_del(&request
->client_list
);
1639 request
->file_priv
= NULL
;
1641 spin_unlock(&file_priv
->mm
.lock
);
1644 static void i915_gem_reset_ring_lists(struct drm_i915_private
*dev_priv
,
1645 struct intel_ring_buffer
*ring
)
1647 while (!list_empty(&ring
->request_list
)) {
1648 struct drm_i915_gem_request
*request
;
1650 request
= list_first_entry(&ring
->request_list
,
1651 struct drm_i915_gem_request
,
1654 list_del(&request
->list
);
1655 i915_gem_request_remove_from_client(request
);
1659 while (!list_empty(&ring
->active_list
)) {
1660 struct drm_i915_gem_object
*obj
;
1662 obj
= list_first_entry(&ring
->active_list
,
1663 struct drm_i915_gem_object
,
1666 obj
->base
.write_domain
= 0;
1667 list_del_init(&obj
->gpu_write_list
);
1668 i915_gem_object_move_to_inactive(obj
);
1672 static void i915_gem_reset_fences(struct drm_device
*dev
)
1674 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1677 for (i
= 0; i
< dev_priv
->num_fence_regs
; i
++) {
1678 struct drm_i915_fence_reg
*reg
= &dev_priv
->fence_regs
[i
];
1679 struct drm_i915_gem_object
*obj
= reg
->obj
;
1684 if (obj
->tiling_mode
)
1685 i915_gem_release_mmap(obj
);
1687 reg
->obj
->fence_reg
= I915_FENCE_REG_NONE
;
1688 reg
->obj
->fenced_gpu_access
= false;
1689 reg
->obj
->last_fenced_seqno
= 0;
1690 reg
->obj
->last_fenced_ring
= NULL
;
1691 i915_gem_clear_fence_reg(dev
, reg
);
1695 void i915_gem_reset(struct drm_device
*dev
)
1697 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1698 struct drm_i915_gem_object
*obj
;
1701 for (i
= 0; i
< I915_NUM_RINGS
; i
++)
1702 i915_gem_reset_ring_lists(dev_priv
, &dev_priv
->ring
[i
]);
1704 /* Remove anything from the flushing lists. The GPU cache is likely
1705 * to be lost on reset along with the data, so simply move the
1706 * lost bo to the inactive list.
1708 while (!list_empty(&dev_priv
->mm
.flushing_list
)) {
1709 obj
= list_first_entry(&dev_priv
->mm
.flushing_list
,
1710 struct drm_i915_gem_object
,
1713 obj
->base
.write_domain
= 0;
1714 list_del_init(&obj
->gpu_write_list
);
1715 i915_gem_object_move_to_inactive(obj
);
1718 /* Move everything out of the GPU domains to ensure we do any
1719 * necessary invalidation upon reuse.
1721 list_for_each_entry(obj
,
1722 &dev_priv
->mm
.inactive_list
,
1725 obj
->base
.read_domains
&= ~I915_GEM_GPU_DOMAINS
;
1728 /* The fence registers are invalidated so clear them out */
1729 i915_gem_reset_fences(dev
);
1733 * This function clears the request list as sequence numbers are passed.
1736 i915_gem_retire_requests_ring(struct intel_ring_buffer
*ring
)
1741 if (list_empty(&ring
->request_list
))
1744 WARN_ON(i915_verify_lists(ring
->dev
));
1746 seqno
= ring
->get_seqno(ring
);
1748 for (i
= 0; i
< ARRAY_SIZE(ring
->sync_seqno
); i
++)
1749 if (seqno
>= ring
->sync_seqno
[i
])
1750 ring
->sync_seqno
[i
] = 0;
1752 while (!list_empty(&ring
->request_list
)) {
1753 struct drm_i915_gem_request
*request
;
1755 request
= list_first_entry(&ring
->request_list
,
1756 struct drm_i915_gem_request
,
1759 if (!i915_seqno_passed(seqno
, request
->seqno
))
1762 trace_i915_gem_request_retire(ring
, request
->seqno
);
1764 list_del(&request
->list
);
1765 i915_gem_request_remove_from_client(request
);
1769 /* Move any buffers on the active list that are no longer referenced
1770 * by the ringbuffer to the flushing/inactive lists as appropriate.
1772 while (!list_empty(&ring
->active_list
)) {
1773 struct drm_i915_gem_object
*obj
;
1775 obj
= list_first_entry(&ring
->active_list
,
1776 struct drm_i915_gem_object
,
1779 if (!i915_seqno_passed(seqno
, obj
->last_rendering_seqno
))
1782 if (obj
->base
.write_domain
!= 0)
1783 i915_gem_object_move_to_flushing(obj
);
1785 i915_gem_object_move_to_inactive(obj
);
1788 if (unlikely(ring
->trace_irq_seqno
&&
1789 i915_seqno_passed(seqno
, ring
->trace_irq_seqno
))) {
1790 ring
->irq_put(ring
);
1791 ring
->trace_irq_seqno
= 0;
1794 WARN_ON(i915_verify_lists(ring
->dev
));
1798 i915_gem_retire_requests(struct drm_device
*dev
)
1800 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1803 if (!list_empty(&dev_priv
->mm
.deferred_free_list
)) {
1804 struct drm_i915_gem_object
*obj
, *next
;
1806 /* We must be careful that during unbind() we do not
1807 * accidentally infinitely recurse into retire requests.
1809 * retire -> free -> unbind -> wait -> retire_ring
1811 list_for_each_entry_safe(obj
, next
,
1812 &dev_priv
->mm
.deferred_free_list
,
1814 i915_gem_free_object_tail(obj
);
1817 for (i
= 0; i
< I915_NUM_RINGS
; i
++)
1818 i915_gem_retire_requests_ring(&dev_priv
->ring
[i
]);
1822 i915_gem_retire_work_handler(struct work_struct
*work
)
1824 drm_i915_private_t
*dev_priv
;
1825 struct drm_device
*dev
;
1829 dev_priv
= container_of(work
, drm_i915_private_t
,
1830 mm
.retire_work
.work
);
1831 dev
= dev_priv
->dev
;
1833 /* Come back later if the device is busy... */
1834 if (!mutex_trylock(&dev
->struct_mutex
)) {
1835 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, HZ
);
1839 i915_gem_retire_requests(dev
);
1841 /* Send a periodic flush down the ring so we don't hold onto GEM
1842 * objects indefinitely.
1845 for (i
= 0; i
< I915_NUM_RINGS
; i
++) {
1846 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[i
];
1848 if (!list_empty(&ring
->gpu_write_list
)) {
1849 struct drm_i915_gem_request
*request
;
1852 ret
= i915_gem_flush_ring(ring
,
1853 0, I915_GEM_GPU_DOMAINS
);
1854 request
= kzalloc(sizeof(*request
), GFP_KERNEL
);
1855 if (ret
|| request
== NULL
||
1856 i915_add_request(ring
, NULL
, request
))
1860 idle
&= list_empty(&ring
->request_list
);
1863 if (!dev_priv
->mm
.suspended
&& !idle
)
1864 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, HZ
);
1866 mutex_unlock(&dev
->struct_mutex
);
1870 * Waits for a sequence number to be signaled, and cleans up the
1871 * request and object lists appropriately for that event.
1874 i915_wait_request(struct intel_ring_buffer
*ring
,
1878 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
1884 if (atomic_read(&dev_priv
->mm
.wedged
)) {
1885 struct completion
*x
= &dev_priv
->error_completion
;
1886 bool recovery_complete
;
1887 unsigned long flags
;
1889 /* Give the error handler a chance to run. */
1890 spin_lock_irqsave(&x
->wait
.lock
, flags
);
1891 recovery_complete
= x
->done
> 0;
1892 spin_unlock_irqrestore(&x
->wait
.lock
, flags
);
1894 return recovery_complete
? -EIO
: -EAGAIN
;
1897 if (seqno
== ring
->outstanding_lazy_request
) {
1898 struct drm_i915_gem_request
*request
;
1900 request
= kzalloc(sizeof(*request
), GFP_KERNEL
);
1901 if (request
== NULL
)
1904 ret
= i915_add_request(ring
, NULL
, request
);
1910 seqno
= request
->seqno
;
1913 if (!i915_seqno_passed(ring
->get_seqno(ring
), seqno
)) {
1914 if (HAS_PCH_SPLIT(ring
->dev
))
1915 ier
= I915_READ(DEIER
) | I915_READ(GTIER
);
1917 ier
= I915_READ(IER
);
1919 DRM_ERROR("something (likely vbetool) disabled "
1920 "interrupts, re-enabling\n");
1921 ring
->dev
->driver
->irq_preinstall(ring
->dev
);
1922 ring
->dev
->driver
->irq_postinstall(ring
->dev
);
1925 trace_i915_gem_request_wait_begin(ring
, seqno
);
1927 ring
->waiting_seqno
= seqno
;
1928 if (ring
->irq_get(ring
)) {
1929 if (dev_priv
->mm
.interruptible
)
1930 ret
= wait_event_interruptible(ring
->irq_queue
,
1931 i915_seqno_passed(ring
->get_seqno(ring
), seqno
)
1932 || atomic_read(&dev_priv
->mm
.wedged
));
1934 wait_event(ring
->irq_queue
,
1935 i915_seqno_passed(ring
->get_seqno(ring
), seqno
)
1936 || atomic_read(&dev_priv
->mm
.wedged
));
1938 ring
->irq_put(ring
);
1939 } else if (wait_for_atomic(i915_seqno_passed(ring
->get_seqno(ring
),
1941 atomic_read(&dev_priv
->mm
.wedged
), 3000))
1943 ring
->waiting_seqno
= 0;
1945 trace_i915_gem_request_wait_end(ring
, seqno
);
1947 if (atomic_read(&dev_priv
->mm
.wedged
))
1950 if (ret
&& ret
!= -ERESTARTSYS
)
1951 DRM_ERROR("%s returns %d (awaiting %d at %d, next %d)\n",
1952 __func__
, ret
, seqno
, ring
->get_seqno(ring
),
1953 dev_priv
->next_seqno
);
1955 /* Directly dispatch request retiring. While we have the work queue
1956 * to handle this, the waiter on a request often wants an associated
1957 * buffer to have made it to the inactive list, and we would need
1958 * a separate wait queue to handle that.
1960 if (ret
== 0 && do_retire
)
1961 i915_gem_retire_requests_ring(ring
);
1967 * Ensures that all rendering to the object has completed and the object is
1968 * safe to unbind from the GTT or access from the CPU.
1971 i915_gem_object_wait_rendering(struct drm_i915_gem_object
*obj
)
1975 /* This function only exists to support waiting for existing rendering,
1976 * not for emitting required flushes.
1978 BUG_ON((obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
) != 0);
1980 /* If there is rendering queued on the buffer being evicted, wait for
1984 ret
= i915_wait_request(obj
->ring
, obj
->last_rendering_seqno
,
1993 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object
*obj
)
1995 u32 old_write_domain
, old_read_domains
;
1997 /* Act a barrier for all accesses through the GTT */
2000 /* Force a pagefault for domain tracking on next user access */
2001 i915_gem_release_mmap(obj
);
2003 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
) == 0)
2006 old_read_domains
= obj
->base
.read_domains
;
2007 old_write_domain
= obj
->base
.write_domain
;
2009 obj
->base
.read_domains
&= ~I915_GEM_DOMAIN_GTT
;
2010 obj
->base
.write_domain
&= ~I915_GEM_DOMAIN_GTT
;
2012 trace_i915_gem_object_change_domain(obj
,
2018 * Unbinds an object from the GTT aperture.
2021 i915_gem_object_unbind(struct drm_i915_gem_object
*obj
)
2025 if (obj
->gtt_space
== NULL
)
2028 if (obj
->pin_count
!= 0) {
2029 DRM_ERROR("Attempting to unbind pinned buffer\n");
2033 ret
= i915_gem_object_finish_gpu(obj
);
2034 if (ret
== -ERESTARTSYS
)
2036 /* Continue on if we fail due to EIO, the GPU is hung so we
2037 * should be safe and we need to cleanup or else we might
2038 * cause memory corruption through use-after-free.
2041 i915_gem_object_finish_gtt(obj
);
2043 /* Move the object to the CPU domain to ensure that
2044 * any possible CPU writes while it's not in the GTT
2045 * are flushed when we go to remap it.
2048 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
2049 if (ret
== -ERESTARTSYS
)
2052 /* In the event of a disaster, abandon all caches and
2053 * hope for the best.
2055 i915_gem_clflush_object(obj
);
2056 obj
->base
.read_domains
= obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
2059 /* release the fence reg _after_ flushing */
2060 ret
= i915_gem_object_put_fence(obj
);
2061 if (ret
== -ERESTARTSYS
)
2064 trace_i915_gem_object_unbind(obj
);
2066 i915_gem_gtt_unbind_object(obj
);
2067 i915_gem_object_put_pages_gtt(obj
);
2069 list_del_init(&obj
->gtt_list
);
2070 list_del_init(&obj
->mm_list
);
2071 /* Avoid an unnecessary call to unbind on rebind. */
2072 obj
->map_and_fenceable
= true;
2074 drm_mm_put_block(obj
->gtt_space
);
2075 obj
->gtt_space
= NULL
;
2076 obj
->gtt_offset
= 0;
2078 if (i915_gem_object_is_purgeable(obj
))
2079 i915_gem_object_truncate(obj
);
2085 i915_gem_flush_ring(struct intel_ring_buffer
*ring
,
2086 uint32_t invalidate_domains
,
2087 uint32_t flush_domains
)
2091 if (((invalidate_domains
| flush_domains
) & I915_GEM_GPU_DOMAINS
) == 0)
2094 trace_i915_gem_ring_flush(ring
, invalidate_domains
, flush_domains
);
2096 ret
= ring
->flush(ring
, invalidate_domains
, flush_domains
);
2100 if (flush_domains
& I915_GEM_GPU_DOMAINS
)
2101 i915_gem_process_flushing_list(ring
, flush_domains
);
2106 static int i915_ring_idle(struct intel_ring_buffer
*ring
, bool do_retire
)
2110 if (list_empty(&ring
->gpu_write_list
) && list_empty(&ring
->active_list
))
2113 if (!list_empty(&ring
->gpu_write_list
)) {
2114 ret
= i915_gem_flush_ring(ring
,
2115 I915_GEM_GPU_DOMAINS
, I915_GEM_GPU_DOMAINS
);
2120 return i915_wait_request(ring
, i915_gem_next_request_seqno(ring
),
2124 int i915_gpu_idle(struct drm_device
*dev
, bool do_retire
)
2126 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2129 /* Flush everything onto the inactive list. */
2130 for (i
= 0; i
< I915_NUM_RINGS
; i
++) {
2131 ret
= i915_ring_idle(&dev_priv
->ring
[i
], do_retire
);
2139 static int sandybridge_write_fence_reg(struct drm_i915_gem_object
*obj
,
2140 struct intel_ring_buffer
*pipelined
)
2142 struct drm_device
*dev
= obj
->base
.dev
;
2143 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2144 u32 size
= obj
->gtt_space
->size
;
2145 int regnum
= obj
->fence_reg
;
2148 val
= (uint64_t)((obj
->gtt_offset
+ size
- 4096) &
2150 val
|= obj
->gtt_offset
& 0xfffff000;
2151 val
|= (uint64_t)((obj
->stride
/ 128) - 1) <<
2152 SANDYBRIDGE_FENCE_PITCH_SHIFT
;
2154 if (obj
->tiling_mode
== I915_TILING_Y
)
2155 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
2156 val
|= I965_FENCE_REG_VALID
;
2159 int ret
= intel_ring_begin(pipelined
, 6);
2163 intel_ring_emit(pipelined
, MI_NOOP
);
2164 intel_ring_emit(pipelined
, MI_LOAD_REGISTER_IMM(2));
2165 intel_ring_emit(pipelined
, FENCE_REG_SANDYBRIDGE_0
+ regnum
*8);
2166 intel_ring_emit(pipelined
, (u32
)val
);
2167 intel_ring_emit(pipelined
, FENCE_REG_SANDYBRIDGE_0
+ regnum
*8 + 4);
2168 intel_ring_emit(pipelined
, (u32
)(val
>> 32));
2169 intel_ring_advance(pipelined
);
2171 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0
+ regnum
* 8, val
);
2176 static int i965_write_fence_reg(struct drm_i915_gem_object
*obj
,
2177 struct intel_ring_buffer
*pipelined
)
2179 struct drm_device
*dev
= obj
->base
.dev
;
2180 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2181 u32 size
= obj
->gtt_space
->size
;
2182 int regnum
= obj
->fence_reg
;
2185 val
= (uint64_t)((obj
->gtt_offset
+ size
- 4096) &
2187 val
|= obj
->gtt_offset
& 0xfffff000;
2188 val
|= ((obj
->stride
/ 128) - 1) << I965_FENCE_PITCH_SHIFT
;
2189 if (obj
->tiling_mode
== I915_TILING_Y
)
2190 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
2191 val
|= I965_FENCE_REG_VALID
;
2194 int ret
= intel_ring_begin(pipelined
, 6);
2198 intel_ring_emit(pipelined
, MI_NOOP
);
2199 intel_ring_emit(pipelined
, MI_LOAD_REGISTER_IMM(2));
2200 intel_ring_emit(pipelined
, FENCE_REG_965_0
+ regnum
*8);
2201 intel_ring_emit(pipelined
, (u32
)val
);
2202 intel_ring_emit(pipelined
, FENCE_REG_965_0
+ regnum
*8 + 4);
2203 intel_ring_emit(pipelined
, (u32
)(val
>> 32));
2204 intel_ring_advance(pipelined
);
2206 I915_WRITE64(FENCE_REG_965_0
+ regnum
* 8, val
);
2211 static int i915_write_fence_reg(struct drm_i915_gem_object
*obj
,
2212 struct intel_ring_buffer
*pipelined
)
2214 struct drm_device
*dev
= obj
->base
.dev
;
2215 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2216 u32 size
= obj
->gtt_space
->size
;
2217 u32 fence_reg
, val
, pitch_val
;
2220 if (WARN((obj
->gtt_offset
& ~I915_FENCE_START_MASK
) ||
2221 (size
& -size
) != size
||
2222 (obj
->gtt_offset
& (size
- 1)),
2223 "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2224 obj
->gtt_offset
, obj
->map_and_fenceable
, size
))
2227 if (obj
->tiling_mode
== I915_TILING_Y
&& HAS_128_BYTE_Y_TILING(dev
))
2232 /* Note: pitch better be a power of two tile widths */
2233 pitch_val
= obj
->stride
/ tile_width
;
2234 pitch_val
= ffs(pitch_val
) - 1;
2236 val
= obj
->gtt_offset
;
2237 if (obj
->tiling_mode
== I915_TILING_Y
)
2238 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2239 val
|= I915_FENCE_SIZE_BITS(size
);
2240 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2241 val
|= I830_FENCE_REG_VALID
;
2243 fence_reg
= obj
->fence_reg
;
2245 fence_reg
= FENCE_REG_830_0
+ fence_reg
* 4;
2247 fence_reg
= FENCE_REG_945_8
+ (fence_reg
- 8) * 4;
2250 int ret
= intel_ring_begin(pipelined
, 4);
2254 intel_ring_emit(pipelined
, MI_NOOP
);
2255 intel_ring_emit(pipelined
, MI_LOAD_REGISTER_IMM(1));
2256 intel_ring_emit(pipelined
, fence_reg
);
2257 intel_ring_emit(pipelined
, val
);
2258 intel_ring_advance(pipelined
);
2260 I915_WRITE(fence_reg
, val
);
2265 static int i830_write_fence_reg(struct drm_i915_gem_object
*obj
,
2266 struct intel_ring_buffer
*pipelined
)
2268 struct drm_device
*dev
= obj
->base
.dev
;
2269 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2270 u32 size
= obj
->gtt_space
->size
;
2271 int regnum
= obj
->fence_reg
;
2275 if (WARN((obj
->gtt_offset
& ~I830_FENCE_START_MASK
) ||
2276 (size
& -size
) != size
||
2277 (obj
->gtt_offset
& (size
- 1)),
2278 "object 0x%08x not 512K or pot-size 0x%08x aligned\n",
2279 obj
->gtt_offset
, size
))
2282 pitch_val
= obj
->stride
/ 128;
2283 pitch_val
= ffs(pitch_val
) - 1;
2285 val
= obj
->gtt_offset
;
2286 if (obj
->tiling_mode
== I915_TILING_Y
)
2287 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2288 val
|= I830_FENCE_SIZE_BITS(size
);
2289 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2290 val
|= I830_FENCE_REG_VALID
;
2293 int ret
= intel_ring_begin(pipelined
, 4);
2297 intel_ring_emit(pipelined
, MI_NOOP
);
2298 intel_ring_emit(pipelined
, MI_LOAD_REGISTER_IMM(1));
2299 intel_ring_emit(pipelined
, FENCE_REG_830_0
+ regnum
*4);
2300 intel_ring_emit(pipelined
, val
);
2301 intel_ring_advance(pipelined
);
2303 I915_WRITE(FENCE_REG_830_0
+ regnum
* 4, val
);
2308 static bool ring_passed_seqno(struct intel_ring_buffer
*ring
, u32 seqno
)
2310 return i915_seqno_passed(ring
->get_seqno(ring
), seqno
);
2314 i915_gem_object_flush_fence(struct drm_i915_gem_object
*obj
,
2315 struct intel_ring_buffer
*pipelined
)
2319 if (obj
->fenced_gpu_access
) {
2320 if (obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
) {
2321 ret
= i915_gem_flush_ring(obj
->last_fenced_ring
,
2322 0, obj
->base
.write_domain
);
2327 obj
->fenced_gpu_access
= false;
2330 if (obj
->last_fenced_seqno
&& pipelined
!= obj
->last_fenced_ring
) {
2331 if (!ring_passed_seqno(obj
->last_fenced_ring
,
2332 obj
->last_fenced_seqno
)) {
2333 ret
= i915_wait_request(obj
->last_fenced_ring
,
2334 obj
->last_fenced_seqno
,
2340 obj
->last_fenced_seqno
= 0;
2341 obj
->last_fenced_ring
= NULL
;
2344 /* Ensure that all CPU reads are completed before installing a fence
2345 * and all writes before removing the fence.
2347 if (obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
)
2354 i915_gem_object_put_fence(struct drm_i915_gem_object
*obj
)
2358 if (obj
->tiling_mode
)
2359 i915_gem_release_mmap(obj
);
2361 ret
= i915_gem_object_flush_fence(obj
, NULL
);
2365 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
2366 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2368 WARN_ON(dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
);
2369 i915_gem_clear_fence_reg(obj
->base
.dev
,
2370 &dev_priv
->fence_regs
[obj
->fence_reg
]);
2372 obj
->fence_reg
= I915_FENCE_REG_NONE
;
2378 static struct drm_i915_fence_reg
*
2379 i915_find_fence_reg(struct drm_device
*dev
,
2380 struct intel_ring_buffer
*pipelined
)
2382 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2383 struct drm_i915_fence_reg
*reg
, *first
, *avail
;
2386 /* First try to find a free reg */
2388 for (i
= dev_priv
->fence_reg_start
; i
< dev_priv
->num_fence_regs
; i
++) {
2389 reg
= &dev_priv
->fence_regs
[i
];
2393 if (!reg
->pin_count
)
2400 /* None available, try to steal one or wait for a user to finish */
2401 avail
= first
= NULL
;
2402 list_for_each_entry(reg
, &dev_priv
->mm
.fence_list
, lru_list
) {
2410 !reg
->obj
->last_fenced_ring
||
2411 reg
->obj
->last_fenced_ring
== pipelined
) {
2424 * i915_gem_object_get_fence - set up a fence reg for an object
2425 * @obj: object to map through a fence reg
2426 * @pipelined: ring on which to queue the change, or NULL for CPU access
2427 * @interruptible: must we wait uninterruptibly for the register to retire?
2429 * When mapping objects through the GTT, userspace wants to be able to write
2430 * to them without having to worry about swizzling if the object is tiled.
2432 * This function walks the fence regs looking for a free one for @obj,
2433 * stealing one if it can't find any.
2435 * It then sets up the reg based on the object's properties: address, pitch
2436 * and tiling format.
2439 i915_gem_object_get_fence(struct drm_i915_gem_object
*obj
,
2440 struct intel_ring_buffer
*pipelined
)
2442 struct drm_device
*dev
= obj
->base
.dev
;
2443 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2444 struct drm_i915_fence_reg
*reg
;
2447 /* XXX disable pipelining. There are bugs. Shocking. */
2450 /* Just update our place in the LRU if our fence is getting reused. */
2451 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
2452 reg
= &dev_priv
->fence_regs
[obj
->fence_reg
];
2453 list_move_tail(®
->lru_list
, &dev_priv
->mm
.fence_list
);
2455 if (obj
->tiling_changed
) {
2456 ret
= i915_gem_object_flush_fence(obj
, pipelined
);
2460 if (!obj
->fenced_gpu_access
&& !obj
->last_fenced_seqno
)
2465 i915_gem_next_request_seqno(pipelined
);
2466 obj
->last_fenced_seqno
= reg
->setup_seqno
;
2467 obj
->last_fenced_ring
= pipelined
;
2474 if (reg
->setup_seqno
) {
2475 if (!ring_passed_seqno(obj
->last_fenced_ring
,
2476 reg
->setup_seqno
)) {
2477 ret
= i915_wait_request(obj
->last_fenced_ring
,
2484 reg
->setup_seqno
= 0;
2486 } else if (obj
->last_fenced_ring
&&
2487 obj
->last_fenced_ring
!= pipelined
) {
2488 ret
= i915_gem_object_flush_fence(obj
, pipelined
);
2496 reg
= i915_find_fence_reg(dev
, pipelined
);
2500 ret
= i915_gem_object_flush_fence(obj
, pipelined
);
2505 struct drm_i915_gem_object
*old
= reg
->obj
;
2507 drm_gem_object_reference(&old
->base
);
2509 if (old
->tiling_mode
)
2510 i915_gem_release_mmap(old
);
2512 ret
= i915_gem_object_flush_fence(old
, pipelined
);
2514 drm_gem_object_unreference(&old
->base
);
2518 if (old
->last_fenced_seqno
== 0 && obj
->last_fenced_seqno
== 0)
2521 old
->fence_reg
= I915_FENCE_REG_NONE
;
2522 old
->last_fenced_ring
= pipelined
;
2523 old
->last_fenced_seqno
=
2524 pipelined
? i915_gem_next_request_seqno(pipelined
) : 0;
2526 drm_gem_object_unreference(&old
->base
);
2527 } else if (obj
->last_fenced_seqno
== 0)
2531 list_move_tail(®
->lru_list
, &dev_priv
->mm
.fence_list
);
2532 obj
->fence_reg
= reg
- dev_priv
->fence_regs
;
2533 obj
->last_fenced_ring
= pipelined
;
2536 pipelined
? i915_gem_next_request_seqno(pipelined
) : 0;
2537 obj
->last_fenced_seqno
= reg
->setup_seqno
;
2540 obj
->tiling_changed
= false;
2541 switch (INTEL_INFO(dev
)->gen
) {
2544 ret
= sandybridge_write_fence_reg(obj
, pipelined
);
2548 ret
= i965_write_fence_reg(obj
, pipelined
);
2551 ret
= i915_write_fence_reg(obj
, pipelined
);
2554 ret
= i830_write_fence_reg(obj
, pipelined
);
2562 * i915_gem_clear_fence_reg - clear out fence register info
2563 * @obj: object to clear
2565 * Zeroes out the fence register itself and clears out the associated
2566 * data structures in dev_priv and obj.
2569 i915_gem_clear_fence_reg(struct drm_device
*dev
,
2570 struct drm_i915_fence_reg
*reg
)
2572 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2573 uint32_t fence_reg
= reg
- dev_priv
->fence_regs
;
2575 switch (INTEL_INFO(dev
)->gen
) {
2578 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0
+ fence_reg
*8, 0);
2582 I915_WRITE64(FENCE_REG_965_0
+ fence_reg
*8, 0);
2586 fence_reg
= FENCE_REG_945_8
+ (fence_reg
- 8) * 4;
2589 fence_reg
= FENCE_REG_830_0
+ fence_reg
* 4;
2591 I915_WRITE(fence_reg
, 0);
2595 list_del_init(®
->lru_list
);
2597 reg
->setup_seqno
= 0;
2602 * Finds free space in the GTT aperture and binds the object there.
2605 i915_gem_object_bind_to_gtt(struct drm_i915_gem_object
*obj
,
2607 bool map_and_fenceable
)
2609 struct drm_device
*dev
= obj
->base
.dev
;
2610 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2611 struct drm_mm_node
*free_space
;
2612 gfp_t gfpmask
= __GFP_NORETRY
| __GFP_NOWARN
;
2613 u32 size
, fence_size
, fence_alignment
, unfenced_alignment
;
2614 bool mappable
, fenceable
;
2617 if (obj
->madv
!= I915_MADV_WILLNEED
) {
2618 DRM_ERROR("Attempting to bind a purgeable object\n");
2622 fence_size
= i915_gem_get_gtt_size(dev
,
2625 fence_alignment
= i915_gem_get_gtt_alignment(dev
,
2628 unfenced_alignment
=
2629 i915_gem_get_unfenced_gtt_alignment(dev
,
2634 alignment
= map_and_fenceable
? fence_alignment
:
2636 if (map_and_fenceable
&& alignment
& (fence_alignment
- 1)) {
2637 DRM_ERROR("Invalid object alignment requested %u\n", alignment
);
2641 size
= map_and_fenceable
? fence_size
: obj
->base
.size
;
2643 /* If the object is bigger than the entire aperture, reject it early
2644 * before evicting everything in a vain attempt to find space.
2646 if (obj
->base
.size
>
2647 (map_and_fenceable
? dev_priv
->mm
.gtt_mappable_end
: dev_priv
->mm
.gtt_total
)) {
2648 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2653 if (map_and_fenceable
)
2655 drm_mm_search_free_in_range(&dev_priv
->mm
.gtt_space
,
2657 dev_priv
->mm
.gtt_mappable_end
,
2660 free_space
= drm_mm_search_free(&dev_priv
->mm
.gtt_space
,
2661 size
, alignment
, 0);
2663 if (free_space
!= NULL
) {
2664 if (map_and_fenceable
)
2666 drm_mm_get_block_range_generic(free_space
,
2668 dev_priv
->mm
.gtt_mappable_end
,
2672 drm_mm_get_block(free_space
, size
, alignment
);
2674 if (obj
->gtt_space
== NULL
) {
2675 /* If the gtt is empty and we're still having trouble
2676 * fitting our object in, we're out of memory.
2678 ret
= i915_gem_evict_something(dev
, size
, alignment
,
2686 ret
= i915_gem_object_get_pages_gtt(obj
, gfpmask
);
2688 drm_mm_put_block(obj
->gtt_space
);
2689 obj
->gtt_space
= NULL
;
2691 if (ret
== -ENOMEM
) {
2692 /* first try to reclaim some memory by clearing the GTT */
2693 ret
= i915_gem_evict_everything(dev
, false);
2695 /* now try to shrink everyone else */
2710 ret
= i915_gem_gtt_bind_object(obj
);
2712 i915_gem_object_put_pages_gtt(obj
);
2713 drm_mm_put_block(obj
->gtt_space
);
2714 obj
->gtt_space
= NULL
;
2716 if (i915_gem_evict_everything(dev
, false))
2722 list_add_tail(&obj
->gtt_list
, &dev_priv
->mm
.gtt_list
);
2723 list_add_tail(&obj
->mm_list
, &dev_priv
->mm
.inactive_list
);
2725 /* Assert that the object is not currently in any GPU domain. As it
2726 * wasn't in the GTT, there shouldn't be any way it could have been in
2729 BUG_ON(obj
->base
.read_domains
& I915_GEM_GPU_DOMAINS
);
2730 BUG_ON(obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
);
2732 obj
->gtt_offset
= obj
->gtt_space
->start
;
2735 obj
->gtt_space
->size
== fence_size
&&
2736 (obj
->gtt_space
->start
& (fence_alignment
- 1)) == 0;
2739 obj
->gtt_offset
+ obj
->base
.size
<= dev_priv
->mm
.gtt_mappable_end
;
2741 obj
->map_and_fenceable
= mappable
&& fenceable
;
2743 trace_i915_gem_object_bind(obj
, map_and_fenceable
);
2748 i915_gem_clflush_object(struct drm_i915_gem_object
*obj
)
2750 /* If we don't have a page list set up, then we're not pinned
2751 * to GPU, and we can ignore the cache flush because it'll happen
2752 * again at bind time.
2754 if (obj
->pages
== NULL
)
2757 /* If the GPU is snooping the contents of the CPU cache,
2758 * we do not need to manually clear the CPU cache lines. However,
2759 * the caches are only snooped when the render cache is
2760 * flushed/invalidated. As we always have to emit invalidations
2761 * and flushes when moving into and out of the RENDER domain, correct
2762 * snooping behaviour occurs naturally as the result of our domain
2765 if (obj
->cache_level
!= I915_CACHE_NONE
)
2768 trace_i915_gem_object_clflush(obj
);
2770 drm_clflush_pages(obj
->pages
, obj
->base
.size
/ PAGE_SIZE
);
2773 /** Flushes any GPU write domain for the object if it's dirty. */
2775 i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object
*obj
)
2777 if ((obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
) == 0)
2780 /* Queue the GPU write cache flushing we need. */
2781 return i915_gem_flush_ring(obj
->ring
, 0, obj
->base
.write_domain
);
2784 /** Flushes the GTT write domain for the object if it's dirty. */
2786 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
)
2788 uint32_t old_write_domain
;
2790 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_GTT
)
2793 /* No actual flushing is required for the GTT write domain. Writes
2794 * to it immediately go to main memory as far as we know, so there's
2795 * no chipset flush. It also doesn't land in render cache.
2797 * However, we do have to enforce the order so that all writes through
2798 * the GTT land before any writes to the device, such as updates to
2803 old_write_domain
= obj
->base
.write_domain
;
2804 obj
->base
.write_domain
= 0;
2806 trace_i915_gem_object_change_domain(obj
,
2807 obj
->base
.read_domains
,
2811 /** Flushes the CPU write domain for the object if it's dirty. */
2813 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
)
2815 uint32_t old_write_domain
;
2817 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
)
2820 i915_gem_clflush_object(obj
);
2821 intel_gtt_chipset_flush();
2822 old_write_domain
= obj
->base
.write_domain
;
2823 obj
->base
.write_domain
= 0;
2825 trace_i915_gem_object_change_domain(obj
,
2826 obj
->base
.read_domains
,
2831 * Moves a single object to the GTT read, and possibly write domain.
2833 * This function returns when the move is complete, including waiting on
2837 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
, bool write
)
2839 uint32_t old_write_domain
, old_read_domains
;
2842 /* Not valid to be called on unbound objects. */
2843 if (obj
->gtt_space
== NULL
)
2846 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_GTT
)
2849 ret
= i915_gem_object_flush_gpu_write_domain(obj
);
2853 if (obj
->pending_gpu_write
|| write
) {
2854 ret
= i915_gem_object_wait_rendering(obj
);
2859 i915_gem_object_flush_cpu_write_domain(obj
);
2861 old_write_domain
= obj
->base
.write_domain
;
2862 old_read_domains
= obj
->base
.read_domains
;
2864 /* It should now be out of any other write domains, and we can update
2865 * the domain values for our changes.
2867 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
2868 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
2870 obj
->base
.read_domains
= I915_GEM_DOMAIN_GTT
;
2871 obj
->base
.write_domain
= I915_GEM_DOMAIN_GTT
;
2875 trace_i915_gem_object_change_domain(obj
,
2882 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
2883 enum i915_cache_level cache_level
)
2887 if (obj
->cache_level
== cache_level
)
2890 if (obj
->pin_count
) {
2891 DRM_DEBUG("can not change the cache level of pinned objects\n");
2895 if (obj
->gtt_space
) {
2896 ret
= i915_gem_object_finish_gpu(obj
);
2900 i915_gem_object_finish_gtt(obj
);
2902 /* Before SandyBridge, you could not use tiling or fence
2903 * registers with snooped memory, so relinquish any fences
2904 * currently pointing to our region in the aperture.
2906 if (INTEL_INFO(obj
->base
.dev
)->gen
< 6) {
2907 ret
= i915_gem_object_put_fence(obj
);
2912 i915_gem_gtt_rebind_object(obj
, cache_level
);
2915 if (cache_level
== I915_CACHE_NONE
) {
2916 u32 old_read_domains
, old_write_domain
;
2918 /* If we're coming from LLC cached, then we haven't
2919 * actually been tracking whether the data is in the
2920 * CPU cache or not, since we only allow one bit set
2921 * in obj->write_domain and have been skipping the clflushes.
2922 * Just set it to the CPU cache for now.
2924 WARN_ON(obj
->base
.write_domain
& ~I915_GEM_DOMAIN_CPU
);
2925 WARN_ON(obj
->base
.read_domains
& ~I915_GEM_DOMAIN_CPU
);
2927 old_read_domains
= obj
->base
.read_domains
;
2928 old_write_domain
= obj
->base
.write_domain
;
2930 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
2931 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
2933 trace_i915_gem_object_change_domain(obj
,
2938 obj
->cache_level
= cache_level
;
2943 * Prepare buffer for display plane (scanout, cursors, etc).
2944 * Can be called from an uninterruptible phase (modesetting) and allows
2945 * any flushes to be pipelined (for pageflips).
2947 * For the display plane, we want to be in the GTT but out of any write
2948 * domains. So in many ways this looks like set_to_gtt_domain() apart from the
2949 * ability to pipeline the waits, pinning and any additional subtleties
2950 * that may differentiate the display plane from ordinary buffers.
2953 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
2955 struct intel_ring_buffer
*pipelined
)
2957 u32 old_read_domains
, old_write_domain
;
2960 ret
= i915_gem_object_flush_gpu_write_domain(obj
);
2964 if (pipelined
!= obj
->ring
) {
2965 ret
= i915_gem_object_wait_rendering(obj
);
2966 if (ret
== -ERESTARTSYS
)
2970 /* The display engine is not coherent with the LLC cache on gen6. As
2971 * a result, we make sure that the pinning that is about to occur is
2972 * done with uncached PTEs. This is lowest common denominator for all
2975 * However for gen6+, we could do better by using the GFDT bit instead
2976 * of uncaching, which would allow us to flush all the LLC-cached data
2977 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
2979 ret
= i915_gem_object_set_cache_level(obj
, I915_CACHE_NONE
);
2983 /* As the user may map the buffer once pinned in the display plane
2984 * (e.g. libkms for the bootup splash), we have to ensure that we
2985 * always use map_and_fenceable for all scanout buffers.
2987 ret
= i915_gem_object_pin(obj
, alignment
, true);
2991 i915_gem_object_flush_cpu_write_domain(obj
);
2993 old_write_domain
= obj
->base
.write_domain
;
2994 old_read_domains
= obj
->base
.read_domains
;
2996 /* It should now be out of any other write domains, and we can update
2997 * the domain values for our changes.
2999 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
3000 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
3002 trace_i915_gem_object_change_domain(obj
,
3010 i915_gem_object_finish_gpu(struct drm_i915_gem_object
*obj
)
3014 if ((obj
->base
.read_domains
& I915_GEM_GPU_DOMAINS
) == 0)
3017 if (obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
) {
3018 ret
= i915_gem_flush_ring(obj
->ring
, 0, obj
->base
.write_domain
);
3023 /* Ensure that we invalidate the GPU's caches and TLBs. */
3024 obj
->base
.read_domains
&= ~I915_GEM_GPU_DOMAINS
;
3026 return i915_gem_object_wait_rendering(obj
);
3030 * Moves a single object to the CPU read, and possibly write domain.
3032 * This function returns when the move is complete, including waiting on
3036 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
)
3038 uint32_t old_write_domain
, old_read_domains
;
3041 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_CPU
)
3044 ret
= i915_gem_object_flush_gpu_write_domain(obj
);
3048 ret
= i915_gem_object_wait_rendering(obj
);
3052 i915_gem_object_flush_gtt_write_domain(obj
);
3054 /* If we have a partially-valid cache of the object in the CPU,
3055 * finish invalidating it and free the per-page flags.
3057 i915_gem_object_set_to_full_cpu_read_domain(obj
);
3059 old_write_domain
= obj
->base
.write_domain
;
3060 old_read_domains
= obj
->base
.read_domains
;
3062 /* Flush the CPU cache if it's still invalid. */
3063 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) == 0) {
3064 i915_gem_clflush_object(obj
);
3066 obj
->base
.read_domains
|= I915_GEM_DOMAIN_CPU
;
3069 /* It should now be out of any other write domains, and we can update
3070 * the domain values for our changes.
3072 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
3074 /* If we're writing through the CPU, then the GPU read domains will
3075 * need to be invalidated at next use.
3078 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
3079 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
3082 trace_i915_gem_object_change_domain(obj
,
3090 * Moves the object from a partially CPU read to a full one.
3092 * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3093 * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
3096 i915_gem_object_set_to_full_cpu_read_domain(struct drm_i915_gem_object
*obj
)
3098 if (!obj
->page_cpu_valid
)
3101 /* If we're partially in the CPU read domain, finish moving it in.
3103 if (obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) {
3106 for (i
= 0; i
<= (obj
->base
.size
- 1) / PAGE_SIZE
; i
++) {
3107 if (obj
->page_cpu_valid
[i
])
3109 drm_clflush_pages(obj
->pages
+ i
, 1);
3113 /* Free the page_cpu_valid mappings which are now stale, whether
3114 * or not we've got I915_GEM_DOMAIN_CPU.
3116 kfree(obj
->page_cpu_valid
);
3117 obj
->page_cpu_valid
= NULL
;
3121 * Set the CPU read domain on a range of the object.
3123 * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3124 * not entirely valid. The page_cpu_valid member of the object flags which
3125 * pages have been flushed, and will be respected by
3126 * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3127 * of the whole object.
3129 * This function returns when the move is complete, including waiting on
3133 i915_gem_object_set_cpu_read_domain_range(struct drm_i915_gem_object
*obj
,
3134 uint64_t offset
, uint64_t size
)
3136 uint32_t old_read_domains
;
3139 if (offset
== 0 && size
== obj
->base
.size
)
3140 return i915_gem_object_set_to_cpu_domain(obj
, 0);
3142 ret
= i915_gem_object_flush_gpu_write_domain(obj
);
3146 ret
= i915_gem_object_wait_rendering(obj
);
3150 i915_gem_object_flush_gtt_write_domain(obj
);
3152 /* If we're already fully in the CPU read domain, we're done. */
3153 if (obj
->page_cpu_valid
== NULL
&&
3154 (obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) != 0)
3157 /* Otherwise, create/clear the per-page CPU read domain flag if we're
3158 * newly adding I915_GEM_DOMAIN_CPU
3160 if (obj
->page_cpu_valid
== NULL
) {
3161 obj
->page_cpu_valid
= kzalloc(obj
->base
.size
/ PAGE_SIZE
,
3163 if (obj
->page_cpu_valid
== NULL
)
3165 } else if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) == 0)
3166 memset(obj
->page_cpu_valid
, 0, obj
->base
.size
/ PAGE_SIZE
);
3168 /* Flush the cache on any pages that are still invalid from the CPU's
3171 for (i
= offset
/ PAGE_SIZE
; i
<= (offset
+ size
- 1) / PAGE_SIZE
;
3173 if (obj
->page_cpu_valid
[i
])
3176 drm_clflush_pages(obj
->pages
+ i
, 1);
3178 obj
->page_cpu_valid
[i
] = 1;
3181 /* It should now be out of any other write domains, and we can update
3182 * the domain values for our changes.
3184 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
3186 old_read_domains
= obj
->base
.read_domains
;
3187 obj
->base
.read_domains
|= I915_GEM_DOMAIN_CPU
;
3189 trace_i915_gem_object_change_domain(obj
,
3191 obj
->base
.write_domain
);
3196 /* Throttle our rendering by waiting until the ring has completed our requests
3197 * emitted over 20 msec ago.
3199 * Note that if we were to use the current jiffies each time around the loop,
3200 * we wouldn't escape the function with any frames outstanding if the time to
3201 * render a frame was over 20ms.
3203 * This should get us reasonable parallelism between CPU and GPU but also
3204 * relatively low latency when blocking on a particular request to finish.
3207 i915_gem_ring_throttle(struct drm_device
*dev
, struct drm_file
*file
)
3209 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3210 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
3211 unsigned long recent_enough
= jiffies
- msecs_to_jiffies(20);
3212 struct drm_i915_gem_request
*request
;
3213 struct intel_ring_buffer
*ring
= NULL
;
3217 if (atomic_read(&dev_priv
->mm
.wedged
))
3220 spin_lock(&file_priv
->mm
.lock
);
3221 list_for_each_entry(request
, &file_priv
->mm
.request_list
, client_list
) {
3222 if (time_after_eq(request
->emitted_jiffies
, recent_enough
))
3225 ring
= request
->ring
;
3226 seqno
= request
->seqno
;
3228 spin_unlock(&file_priv
->mm
.lock
);
3234 if (!i915_seqno_passed(ring
->get_seqno(ring
), seqno
)) {
3235 /* And wait for the seqno passing without holding any locks and
3236 * causing extra latency for others. This is safe as the irq
3237 * generation is designed to be run atomically and so is
3240 if (ring
->irq_get(ring
)) {
3241 ret
= wait_event_interruptible(ring
->irq_queue
,
3242 i915_seqno_passed(ring
->get_seqno(ring
), seqno
)
3243 || atomic_read(&dev_priv
->mm
.wedged
));
3244 ring
->irq_put(ring
);
3246 if (ret
== 0 && atomic_read(&dev_priv
->mm
.wedged
))
3248 } else if (wait_for_atomic(i915_seqno_passed(ring
->get_seqno(ring
),
3250 atomic_read(&dev_priv
->mm
.wedged
), 3000)) {
3256 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, 0);
3262 i915_gem_object_pin(struct drm_i915_gem_object
*obj
,
3264 bool map_and_fenceable
)
3266 struct drm_device
*dev
= obj
->base
.dev
;
3267 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3270 BUG_ON(obj
->pin_count
== DRM_I915_GEM_OBJECT_MAX_PIN_COUNT
);
3271 WARN_ON(i915_verify_lists(dev
));
3273 if (obj
->gtt_space
!= NULL
) {
3274 if ((alignment
&& obj
->gtt_offset
& (alignment
- 1)) ||
3275 (map_and_fenceable
&& !obj
->map_and_fenceable
)) {
3276 WARN(obj
->pin_count
,
3277 "bo is already pinned with incorrect alignment:"
3278 " offset=%x, req.alignment=%x, req.map_and_fenceable=%d,"
3279 " obj->map_and_fenceable=%d\n",
3280 obj
->gtt_offset
, alignment
,
3282 obj
->map_and_fenceable
);
3283 ret
= i915_gem_object_unbind(obj
);
3289 if (obj
->gtt_space
== NULL
) {
3290 ret
= i915_gem_object_bind_to_gtt(obj
, alignment
,
3296 if (obj
->pin_count
++ == 0) {
3298 list_move_tail(&obj
->mm_list
,
3299 &dev_priv
->mm
.pinned_list
);
3301 obj
->pin_mappable
|= map_and_fenceable
;
3303 WARN_ON(i915_verify_lists(dev
));
3308 i915_gem_object_unpin(struct drm_i915_gem_object
*obj
)
3310 struct drm_device
*dev
= obj
->base
.dev
;
3311 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3313 WARN_ON(i915_verify_lists(dev
));
3314 BUG_ON(obj
->pin_count
== 0);
3315 BUG_ON(obj
->gtt_space
== NULL
);
3317 if (--obj
->pin_count
== 0) {
3319 list_move_tail(&obj
->mm_list
,
3320 &dev_priv
->mm
.inactive_list
);
3321 obj
->pin_mappable
= false;
3323 WARN_ON(i915_verify_lists(dev
));
3327 i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
3328 struct drm_file
*file
)
3330 struct drm_i915_gem_pin
*args
= data
;
3331 struct drm_i915_gem_object
*obj
;
3334 ret
= i915_mutex_lock_interruptible(dev
);
3338 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3339 if (&obj
->base
== NULL
) {
3344 if (obj
->madv
!= I915_MADV_WILLNEED
) {
3345 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3350 if (obj
->pin_filp
!= NULL
&& obj
->pin_filp
!= file
) {
3351 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3357 obj
->user_pin_count
++;
3358 obj
->pin_filp
= file
;
3359 if (obj
->user_pin_count
== 1) {
3360 ret
= i915_gem_object_pin(obj
, args
->alignment
, true);
3365 /* XXX - flush the CPU caches for pinned objects
3366 * as the X server doesn't manage domains yet
3368 i915_gem_object_flush_cpu_write_domain(obj
);
3369 args
->offset
= obj
->gtt_offset
;
3371 drm_gem_object_unreference(&obj
->base
);
3373 mutex_unlock(&dev
->struct_mutex
);
3378 i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
3379 struct drm_file
*file
)
3381 struct drm_i915_gem_pin
*args
= data
;
3382 struct drm_i915_gem_object
*obj
;
3385 ret
= i915_mutex_lock_interruptible(dev
);
3389 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3390 if (&obj
->base
== NULL
) {
3395 if (obj
->pin_filp
!= file
) {
3396 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3401 obj
->user_pin_count
--;
3402 if (obj
->user_pin_count
== 0) {
3403 obj
->pin_filp
= NULL
;
3404 i915_gem_object_unpin(obj
);
3408 drm_gem_object_unreference(&obj
->base
);
3410 mutex_unlock(&dev
->struct_mutex
);
3415 i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
3416 struct drm_file
*file
)
3418 struct drm_i915_gem_busy
*args
= data
;
3419 struct drm_i915_gem_object
*obj
;
3422 ret
= i915_mutex_lock_interruptible(dev
);
3426 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3427 if (&obj
->base
== NULL
) {
3432 /* Count all active objects as busy, even if they are currently not used
3433 * by the gpu. Users of this interface expect objects to eventually
3434 * become non-busy without any further actions, therefore emit any
3435 * necessary flushes here.
3437 args
->busy
= obj
->active
;
3439 /* Unconditionally flush objects, even when the gpu still uses this
3440 * object. Userspace calling this function indicates that it wants to
3441 * use this buffer rather sooner than later, so issuing the required
3442 * flush earlier is beneficial.
3444 if (obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
) {
3445 ret
= i915_gem_flush_ring(obj
->ring
,
3446 0, obj
->base
.write_domain
);
3447 } else if (obj
->ring
->outstanding_lazy_request
==
3448 obj
->last_rendering_seqno
) {
3449 struct drm_i915_gem_request
*request
;
3451 /* This ring is not being cleared by active usage,
3452 * so emit a request to do so.
3454 request
= kzalloc(sizeof(*request
), GFP_KERNEL
);
3456 ret
= i915_add_request(obj
->ring
, NULL
, request
);
3463 /* Update the active list for the hardware's current position.
3464 * Otherwise this only updates on a delayed timer or when irqs
3465 * are actually unmasked, and our working set ends up being
3466 * larger than required.
3468 i915_gem_retire_requests_ring(obj
->ring
);
3470 args
->busy
= obj
->active
;
3473 drm_gem_object_unreference(&obj
->base
);
3475 mutex_unlock(&dev
->struct_mutex
);
3480 i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
3481 struct drm_file
*file_priv
)
3483 return i915_gem_ring_throttle(dev
, file_priv
);
3487 i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
3488 struct drm_file
*file_priv
)
3490 struct drm_i915_gem_madvise
*args
= data
;
3491 struct drm_i915_gem_object
*obj
;
3494 switch (args
->madv
) {
3495 case I915_MADV_DONTNEED
:
3496 case I915_MADV_WILLNEED
:
3502 ret
= i915_mutex_lock_interruptible(dev
);
3506 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file_priv
, args
->handle
));
3507 if (&obj
->base
== NULL
) {
3512 if (obj
->pin_count
) {
3517 if (obj
->madv
!= __I915_MADV_PURGED
)
3518 obj
->madv
= args
->madv
;
3520 /* if the object is no longer bound, discard its backing storage */
3521 if (i915_gem_object_is_purgeable(obj
) &&
3522 obj
->gtt_space
== NULL
)
3523 i915_gem_object_truncate(obj
);
3525 args
->retained
= obj
->madv
!= __I915_MADV_PURGED
;
3528 drm_gem_object_unreference(&obj
->base
);
3530 mutex_unlock(&dev
->struct_mutex
);
3534 struct drm_i915_gem_object
*i915_gem_alloc_object(struct drm_device
*dev
,
3537 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3538 struct drm_i915_gem_object
*obj
;
3539 struct address_space
*mapping
;
3541 obj
= kzalloc(sizeof(*obj
), GFP_KERNEL
);
3545 if (drm_gem_object_init(dev
, &obj
->base
, size
) != 0) {
3550 mapping
= obj
->base
.filp
->f_path
.dentry
->d_inode
->i_mapping
;
3551 mapping_set_gfp_mask(mapping
, GFP_HIGHUSER
| __GFP_RECLAIMABLE
);
3553 i915_gem_info_add_obj(dev_priv
, size
);
3555 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
3556 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
3559 /* On some devices, we can have the GPU use the LLC (the CPU
3560 * cache) for about a 10% performance improvement
3561 * compared to uncached. Graphics requests other than
3562 * display scanout are coherent with the CPU in
3563 * accessing this cache. This means in this mode we
3564 * don't need to clflush on the CPU side, and on the
3565 * GPU side we only need to flush internal caches to
3566 * get data visible to the CPU.
3568 * However, we maintain the display planes as UC, and so
3569 * need to rebind when first used as such.
3571 obj
->cache_level
= I915_CACHE_LLC
;
3573 obj
->cache_level
= I915_CACHE_NONE
;
3575 obj
->base
.driver_private
= NULL
;
3576 obj
->fence_reg
= I915_FENCE_REG_NONE
;
3577 INIT_LIST_HEAD(&obj
->mm_list
);
3578 INIT_LIST_HEAD(&obj
->gtt_list
);
3579 INIT_LIST_HEAD(&obj
->ring_list
);
3580 INIT_LIST_HEAD(&obj
->exec_list
);
3581 INIT_LIST_HEAD(&obj
->gpu_write_list
);
3582 obj
->madv
= I915_MADV_WILLNEED
;
3583 /* Avoid an unnecessary call to unbind on the first bind. */
3584 obj
->map_and_fenceable
= true;
3589 int i915_gem_init_object(struct drm_gem_object
*obj
)
3596 static void i915_gem_free_object_tail(struct drm_i915_gem_object
*obj
)
3598 struct drm_device
*dev
= obj
->base
.dev
;
3599 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3602 ret
= i915_gem_object_unbind(obj
);
3603 if (ret
== -ERESTARTSYS
) {
3604 list_move(&obj
->mm_list
,
3605 &dev_priv
->mm
.deferred_free_list
);
3609 trace_i915_gem_object_destroy(obj
);
3611 if (obj
->base
.map_list
.map
)
3612 drm_gem_free_mmap_offset(&obj
->base
);
3614 drm_gem_object_release(&obj
->base
);
3615 i915_gem_info_remove_obj(dev_priv
, obj
->base
.size
);
3617 kfree(obj
->page_cpu_valid
);
3622 void i915_gem_free_object(struct drm_gem_object
*gem_obj
)
3624 struct drm_i915_gem_object
*obj
= to_intel_bo(gem_obj
);
3625 struct drm_device
*dev
= obj
->base
.dev
;
3627 while (obj
->pin_count
> 0)
3628 i915_gem_object_unpin(obj
);
3631 i915_gem_detach_phys_object(dev
, obj
);
3633 i915_gem_free_object_tail(obj
);
3637 i915_gem_idle(struct drm_device
*dev
)
3639 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3642 mutex_lock(&dev
->struct_mutex
);
3644 if (dev_priv
->mm
.suspended
) {
3645 mutex_unlock(&dev
->struct_mutex
);
3649 ret
= i915_gpu_idle(dev
, true);
3651 mutex_unlock(&dev
->struct_mutex
);
3655 /* Under UMS, be paranoid and evict. */
3656 if (!drm_core_check_feature(dev
, DRIVER_MODESET
)) {
3657 ret
= i915_gem_evict_inactive(dev
, false);
3659 mutex_unlock(&dev
->struct_mutex
);
3664 i915_gem_reset_fences(dev
);
3666 /* Hack! Don't let anybody do execbuf while we don't control the chip.
3667 * We need to replace this with a semaphore, or something.
3668 * And not confound mm.suspended!
3670 dev_priv
->mm
.suspended
= 1;
3671 del_timer_sync(&dev_priv
->hangcheck_timer
);
3673 i915_kernel_lost_context(dev
);
3674 i915_gem_cleanup_ringbuffer(dev
);
3676 mutex_unlock(&dev
->struct_mutex
);
3678 /* Cancel the retire work handler, which should be idle now. */
3679 cancel_delayed_work_sync(&dev_priv
->mm
.retire_work
);
3684 void i915_gem_init_swizzling(struct drm_device
*dev
)
3686 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3688 if (INTEL_INFO(dev
)->gen
< 6 ||
3689 dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_NONE
)
3692 I915_WRITE(DISP_ARB_CTL
, I915_READ(DISP_ARB_CTL
) |
3693 DISP_TILE_SURFACE_SWIZZLING
);
3695 I915_WRITE(TILECTL
, I915_READ(TILECTL
) | TILECTL_SWZCTL
);
3697 I915_WRITE(ARB_MODE
, ARB_MODE_ENABLE(ARB_MODE_SWIZZLE_SNB
));
3699 I915_WRITE(ARB_MODE
, ARB_MODE_ENABLE(ARB_MODE_SWIZZLE_IVB
));
3702 i915_gem_init_hw(struct drm_device
*dev
)
3704 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3707 i915_gem_init_swizzling(dev
);
3709 ret
= intel_init_render_ring_buffer(dev
);
3714 ret
= intel_init_bsd_ring_buffer(dev
);
3716 goto cleanup_render_ring
;
3720 ret
= intel_init_blt_ring_buffer(dev
);
3722 goto cleanup_bsd_ring
;
3725 dev_priv
->next_seqno
= 1;
3730 intel_cleanup_ring_buffer(&dev_priv
->ring
[VCS
]);
3731 cleanup_render_ring
:
3732 intel_cleanup_ring_buffer(&dev_priv
->ring
[RCS
]);
3737 i915_gem_cleanup_ringbuffer(struct drm_device
*dev
)
3739 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3742 for (i
= 0; i
< I915_NUM_RINGS
; i
++)
3743 intel_cleanup_ring_buffer(&dev_priv
->ring
[i
]);
3747 i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
3748 struct drm_file
*file_priv
)
3750 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3753 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
3756 if (atomic_read(&dev_priv
->mm
.wedged
)) {
3757 DRM_ERROR("Reenabling wedged hardware, good luck\n");
3758 atomic_set(&dev_priv
->mm
.wedged
, 0);
3761 mutex_lock(&dev
->struct_mutex
);
3762 dev_priv
->mm
.suspended
= 0;
3764 ret
= i915_gem_init_hw(dev
);
3766 mutex_unlock(&dev
->struct_mutex
);
3770 BUG_ON(!list_empty(&dev_priv
->mm
.active_list
));
3771 BUG_ON(!list_empty(&dev_priv
->mm
.flushing_list
));
3772 BUG_ON(!list_empty(&dev_priv
->mm
.inactive_list
));
3773 for (i
= 0; i
< I915_NUM_RINGS
; i
++) {
3774 BUG_ON(!list_empty(&dev_priv
->ring
[i
].active_list
));
3775 BUG_ON(!list_empty(&dev_priv
->ring
[i
].request_list
));
3777 mutex_unlock(&dev
->struct_mutex
);
3779 ret
= drm_irq_install(dev
);
3781 goto cleanup_ringbuffer
;
3786 mutex_lock(&dev
->struct_mutex
);
3787 i915_gem_cleanup_ringbuffer(dev
);
3788 dev_priv
->mm
.suspended
= 1;
3789 mutex_unlock(&dev
->struct_mutex
);
3795 i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
3796 struct drm_file
*file_priv
)
3798 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
3801 drm_irq_uninstall(dev
);
3802 return i915_gem_idle(dev
);
3806 i915_gem_lastclose(struct drm_device
*dev
)
3810 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
3813 ret
= i915_gem_idle(dev
);
3815 DRM_ERROR("failed to idle hardware: %d\n", ret
);
3819 init_ring_lists(struct intel_ring_buffer
*ring
)
3821 INIT_LIST_HEAD(&ring
->active_list
);
3822 INIT_LIST_HEAD(&ring
->request_list
);
3823 INIT_LIST_HEAD(&ring
->gpu_write_list
);
3827 i915_gem_load(struct drm_device
*dev
)
3830 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3832 INIT_LIST_HEAD(&dev_priv
->mm
.active_list
);
3833 INIT_LIST_HEAD(&dev_priv
->mm
.flushing_list
);
3834 INIT_LIST_HEAD(&dev_priv
->mm
.inactive_list
);
3835 INIT_LIST_HEAD(&dev_priv
->mm
.pinned_list
);
3836 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
3837 INIT_LIST_HEAD(&dev_priv
->mm
.deferred_free_list
);
3838 INIT_LIST_HEAD(&dev_priv
->mm
.gtt_list
);
3839 for (i
= 0; i
< I915_NUM_RINGS
; i
++)
3840 init_ring_lists(&dev_priv
->ring
[i
]);
3841 for (i
= 0; i
< I915_MAX_NUM_FENCES
; i
++)
3842 INIT_LIST_HEAD(&dev_priv
->fence_regs
[i
].lru_list
);
3843 INIT_DELAYED_WORK(&dev_priv
->mm
.retire_work
,
3844 i915_gem_retire_work_handler
);
3845 init_completion(&dev_priv
->error_completion
);
3847 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
3849 u32 tmp
= I915_READ(MI_ARB_STATE
);
3850 if (!(tmp
& MI_ARB_C3_LP_WRITE_ENABLE
)) {
3851 /* arb state is a masked write, so set bit + bit in mask */
3852 tmp
= MI_ARB_C3_LP_WRITE_ENABLE
| (MI_ARB_C3_LP_WRITE_ENABLE
<< MI_ARB_MASK_SHIFT
);
3853 I915_WRITE(MI_ARB_STATE
, tmp
);
3857 dev_priv
->relative_constants_mode
= I915_EXEC_CONSTANTS_REL_GENERAL
;
3859 /* Old X drivers will take 0-2 for front, back, depth buffers */
3860 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
3861 dev_priv
->fence_reg_start
= 3;
3863 if (INTEL_INFO(dev
)->gen
>= 4 || IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
3864 dev_priv
->num_fence_regs
= 16;
3866 dev_priv
->num_fence_regs
= 8;
3868 /* Initialize fence registers to zero */
3869 for (i
= 0; i
< dev_priv
->num_fence_regs
; i
++) {
3870 i915_gem_clear_fence_reg(dev
, &dev_priv
->fence_regs
[i
]);
3873 i915_gem_detect_bit_6_swizzle(dev
);
3874 init_waitqueue_head(&dev_priv
->pending_flip_queue
);
3876 dev_priv
->mm
.interruptible
= true;
3878 dev_priv
->mm
.inactive_shrinker
.shrink
= i915_gem_inactive_shrink
;
3879 dev_priv
->mm
.inactive_shrinker
.seeks
= DEFAULT_SEEKS
;
3880 register_shrinker(&dev_priv
->mm
.inactive_shrinker
);
3884 * Create a physically contiguous memory object for this object
3885 * e.g. for cursor + overlay regs
3887 static int i915_gem_init_phys_object(struct drm_device
*dev
,
3888 int id
, int size
, int align
)
3890 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3891 struct drm_i915_gem_phys_object
*phys_obj
;
3894 if (dev_priv
->mm
.phys_objs
[id
- 1] || !size
)
3897 phys_obj
= kzalloc(sizeof(struct drm_i915_gem_phys_object
), GFP_KERNEL
);
3903 phys_obj
->handle
= drm_pci_alloc(dev
, size
, align
);
3904 if (!phys_obj
->handle
) {
3909 set_memory_wc((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
3912 dev_priv
->mm
.phys_objs
[id
- 1] = phys_obj
;
3920 static void i915_gem_free_phys_object(struct drm_device
*dev
, int id
)
3922 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3923 struct drm_i915_gem_phys_object
*phys_obj
;
3925 if (!dev_priv
->mm
.phys_objs
[id
- 1])
3928 phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
3929 if (phys_obj
->cur_obj
) {
3930 i915_gem_detach_phys_object(dev
, phys_obj
->cur_obj
);
3934 set_memory_wb((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
3936 drm_pci_free(dev
, phys_obj
->handle
);
3938 dev_priv
->mm
.phys_objs
[id
- 1] = NULL
;
3941 void i915_gem_free_all_phys_object(struct drm_device
*dev
)
3945 for (i
= I915_GEM_PHYS_CURSOR_0
; i
<= I915_MAX_PHYS_OBJECT
; i
++)
3946 i915_gem_free_phys_object(dev
, i
);
3949 void i915_gem_detach_phys_object(struct drm_device
*dev
,
3950 struct drm_i915_gem_object
*obj
)
3952 struct address_space
*mapping
= obj
->base
.filp
->f_path
.dentry
->d_inode
->i_mapping
;
3959 vaddr
= obj
->phys_obj
->handle
->vaddr
;
3961 page_count
= obj
->base
.size
/ PAGE_SIZE
;
3962 for (i
= 0; i
< page_count
; i
++) {
3963 struct page
*page
= shmem_read_mapping_page(mapping
, i
);
3964 if (!IS_ERR(page
)) {
3965 char *dst
= kmap_atomic(page
);
3966 memcpy(dst
, vaddr
+ i
*PAGE_SIZE
, PAGE_SIZE
);
3969 drm_clflush_pages(&page
, 1);
3971 set_page_dirty(page
);
3972 mark_page_accessed(page
);
3973 page_cache_release(page
);
3976 intel_gtt_chipset_flush();
3978 obj
->phys_obj
->cur_obj
= NULL
;
3979 obj
->phys_obj
= NULL
;
3983 i915_gem_attach_phys_object(struct drm_device
*dev
,
3984 struct drm_i915_gem_object
*obj
,
3988 struct address_space
*mapping
= obj
->base
.filp
->f_path
.dentry
->d_inode
->i_mapping
;
3989 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3994 if (id
> I915_MAX_PHYS_OBJECT
)
3997 if (obj
->phys_obj
) {
3998 if (obj
->phys_obj
->id
== id
)
4000 i915_gem_detach_phys_object(dev
, obj
);
4003 /* create a new object */
4004 if (!dev_priv
->mm
.phys_objs
[id
- 1]) {
4005 ret
= i915_gem_init_phys_object(dev
, id
,
4006 obj
->base
.size
, align
);
4008 DRM_ERROR("failed to init phys object %d size: %zu\n",
4009 id
, obj
->base
.size
);
4014 /* bind to the object */
4015 obj
->phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
4016 obj
->phys_obj
->cur_obj
= obj
;
4018 page_count
= obj
->base
.size
/ PAGE_SIZE
;
4020 for (i
= 0; i
< page_count
; i
++) {
4024 page
= shmem_read_mapping_page(mapping
, i
);
4026 return PTR_ERR(page
);
4028 src
= kmap_atomic(page
);
4029 dst
= obj
->phys_obj
->handle
->vaddr
+ (i
* PAGE_SIZE
);
4030 memcpy(dst
, src
, PAGE_SIZE
);
4033 mark_page_accessed(page
);
4034 page_cache_release(page
);
4041 i915_gem_phys_pwrite(struct drm_device
*dev
,
4042 struct drm_i915_gem_object
*obj
,
4043 struct drm_i915_gem_pwrite
*args
,
4044 struct drm_file
*file_priv
)
4046 void *vaddr
= obj
->phys_obj
->handle
->vaddr
+ args
->offset
;
4047 char __user
*user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
4049 if (__copy_from_user_inatomic_nocache(vaddr
, user_data
, args
->size
)) {
4050 unsigned long unwritten
;
4052 /* The physical object once assigned is fixed for the lifetime
4053 * of the obj, so we can safely drop the lock and continue
4056 mutex_unlock(&dev
->struct_mutex
);
4057 unwritten
= copy_from_user(vaddr
, user_data
, args
->size
);
4058 mutex_lock(&dev
->struct_mutex
);
4063 intel_gtt_chipset_flush();
4067 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
)
4069 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
4071 /* Clean up our request list when the client is going away, so that
4072 * later retire_requests won't dereference our soon-to-be-gone
4075 spin_lock(&file_priv
->mm
.lock
);
4076 while (!list_empty(&file_priv
->mm
.request_list
)) {
4077 struct drm_i915_gem_request
*request
;
4079 request
= list_first_entry(&file_priv
->mm
.request_list
,
4080 struct drm_i915_gem_request
,
4082 list_del(&request
->client_list
);
4083 request
->file_priv
= NULL
;
4085 spin_unlock(&file_priv
->mm
.lock
);
4089 i915_gpu_is_active(struct drm_device
*dev
)
4091 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4094 lists_empty
= list_empty(&dev_priv
->mm
.flushing_list
) &&
4095 list_empty(&dev_priv
->mm
.active_list
);
4097 return !lists_empty
;
4101 i915_gem_inactive_shrink(struct shrinker
*shrinker
, struct shrink_control
*sc
)
4103 struct drm_i915_private
*dev_priv
=
4104 container_of(shrinker
,
4105 struct drm_i915_private
,
4106 mm
.inactive_shrinker
);
4107 struct drm_device
*dev
= dev_priv
->dev
;
4108 struct drm_i915_gem_object
*obj
, *next
;
4109 int nr_to_scan
= sc
->nr_to_scan
;
4112 if (!mutex_trylock(&dev
->struct_mutex
))
4115 /* "fast-path" to count number of available objects */
4116 if (nr_to_scan
== 0) {
4118 list_for_each_entry(obj
,
4119 &dev_priv
->mm
.inactive_list
,
4122 mutex_unlock(&dev
->struct_mutex
);
4123 return cnt
/ 100 * sysctl_vfs_cache_pressure
;
4127 /* first scan for clean buffers */
4128 i915_gem_retire_requests(dev
);
4130 list_for_each_entry_safe(obj
, next
,
4131 &dev_priv
->mm
.inactive_list
,
4133 if (i915_gem_object_is_purgeable(obj
)) {
4134 if (i915_gem_object_unbind(obj
) == 0 &&
4140 /* second pass, evict/count anything still on the inactive list */
4142 list_for_each_entry_safe(obj
, next
,
4143 &dev_priv
->mm
.inactive_list
,
4146 i915_gem_object_unbind(obj
) == 0)
4152 if (nr_to_scan
&& i915_gpu_is_active(dev
)) {
4154 * We are desperate for pages, so as a last resort, wait
4155 * for the GPU to finish and discard whatever we can.
4156 * This has a dramatic impact to reduce the number of
4157 * OOM-killer events whilst running the GPU aggressively.
4159 if (i915_gpu_idle(dev
, true) == 0)
4162 mutex_unlock(&dev
->struct_mutex
);
4163 return cnt
/ 100 * sysctl_vfs_cache_pressure
;