2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/i915_drm.h>
31 #include "i915_trace.h"
32 #include "intel_drv.h"
33 #include <linux/shmem_fs.h>
34 #include <linux/slab.h>
35 #include <linux/swap.h>
36 #include <linux/pci.h>
37 #include <linux/dma-buf.h>
39 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
);
40 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
);
41 static __must_check
int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object
*obj
,
43 bool map_and_fenceable
,
45 static int i915_gem_phys_pwrite(struct drm_device
*dev
,
46 struct drm_i915_gem_object
*obj
,
47 struct drm_i915_gem_pwrite
*args
,
48 struct drm_file
*file
);
50 static void i915_gem_write_fence(struct drm_device
*dev
, int reg
,
51 struct drm_i915_gem_object
*obj
);
52 static void i915_gem_object_update_fence(struct drm_i915_gem_object
*obj
,
53 struct drm_i915_fence_reg
*fence
,
56 static int i915_gem_inactive_shrink(struct shrinker
*shrinker
,
57 struct shrink_control
*sc
);
58 static long i915_gem_purge(struct drm_i915_private
*dev_priv
, long target
);
59 static void i915_gem_shrink_all(struct drm_i915_private
*dev_priv
);
60 static void i915_gem_object_truncate(struct drm_i915_gem_object
*obj
);
62 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object
*obj
)
65 i915_gem_release_mmap(obj
);
67 /* As we do not have an associated fence register, we will force
68 * a tiling change if we ever need to acquire one.
70 obj
->fence_dirty
= false;
71 obj
->fence_reg
= I915_FENCE_REG_NONE
;
74 /* some bookkeeping */
75 static void i915_gem_info_add_obj(struct drm_i915_private
*dev_priv
,
78 dev_priv
->mm
.object_count
++;
79 dev_priv
->mm
.object_memory
+= size
;
82 static void i915_gem_info_remove_obj(struct drm_i915_private
*dev_priv
,
85 dev_priv
->mm
.object_count
--;
86 dev_priv
->mm
.object_memory
-= size
;
90 i915_gem_wait_for_error(struct drm_device
*dev
)
92 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
93 struct completion
*x
= &dev_priv
->gpu_error
.completion
;
97 if (!atomic_read(&dev_priv
->mm
.wedged
))
101 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
102 * userspace. If it takes that long something really bad is going on and
103 * we should simply try to bail out and fail as gracefully as possible.
105 ret
= wait_for_completion_interruptible_timeout(x
, 10*HZ
);
107 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
109 } else if (ret
< 0) {
113 if (atomic_read(&dev_priv
->mm
.wedged
)) {
114 /* GPU is hung, bump the completion count to account for
115 * the token we just consumed so that we never hit zero and
116 * end up waiting upon a subsequent completion event that
119 spin_lock_irqsave(&x
->wait
.lock
, flags
);
121 spin_unlock_irqrestore(&x
->wait
.lock
, flags
);
126 int i915_mutex_lock_interruptible(struct drm_device
*dev
)
130 ret
= i915_gem_wait_for_error(dev
);
134 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
138 WARN_ON(i915_verify_lists(dev
));
143 i915_gem_object_is_inactive(struct drm_i915_gem_object
*obj
)
145 return obj
->gtt_space
&& !obj
->active
;
149 i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
150 struct drm_file
*file
)
152 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
153 struct drm_i915_gem_init
*args
= data
;
155 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
158 if (args
->gtt_start
>= args
->gtt_end
||
159 (args
->gtt_end
| args
->gtt_start
) & (PAGE_SIZE
- 1))
162 /* GEM with user mode setting was never supported on ilk and later. */
163 if (INTEL_INFO(dev
)->gen
>= 5)
166 mutex_lock(&dev
->struct_mutex
);
167 i915_gem_setup_global_gtt(dev
, args
->gtt_start
, args
->gtt_end
,
169 dev_priv
->gtt
.mappable_end
= args
->gtt_end
;
170 mutex_unlock(&dev
->struct_mutex
);
176 i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
177 struct drm_file
*file
)
179 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
180 struct drm_i915_gem_get_aperture
*args
= data
;
181 struct drm_i915_gem_object
*obj
;
185 mutex_lock(&dev
->struct_mutex
);
186 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, gtt_list
)
188 pinned
+= obj
->gtt_space
->size
;
189 mutex_unlock(&dev
->struct_mutex
);
191 args
->aper_size
= dev_priv
->gtt
.total
;
192 args
->aper_available_size
= args
->aper_size
- pinned
;
197 void *i915_gem_object_alloc(struct drm_device
*dev
)
199 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
200 return kmem_cache_alloc(dev_priv
->slab
, GFP_KERNEL
| __GFP_ZERO
);
203 void i915_gem_object_free(struct drm_i915_gem_object
*obj
)
205 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
206 kmem_cache_free(dev_priv
->slab
, obj
);
210 i915_gem_create(struct drm_file
*file
,
211 struct drm_device
*dev
,
215 struct drm_i915_gem_object
*obj
;
219 size
= roundup(size
, PAGE_SIZE
);
223 /* Allocate the new object */
224 obj
= i915_gem_alloc_object(dev
, size
);
228 ret
= drm_gem_handle_create(file
, &obj
->base
, &handle
);
230 drm_gem_object_release(&obj
->base
);
231 i915_gem_info_remove_obj(dev
->dev_private
, obj
->base
.size
);
232 i915_gem_object_free(obj
);
236 /* drop reference from allocate - handle holds it now */
237 drm_gem_object_unreference(&obj
->base
);
238 trace_i915_gem_object_create(obj
);
245 i915_gem_dumb_create(struct drm_file
*file
,
246 struct drm_device
*dev
,
247 struct drm_mode_create_dumb
*args
)
249 /* have to work out size/pitch and return them */
250 args
->pitch
= ALIGN(args
->width
* ((args
->bpp
+ 7) / 8), 64);
251 args
->size
= args
->pitch
* args
->height
;
252 return i915_gem_create(file
, dev
,
253 args
->size
, &args
->handle
);
256 int i915_gem_dumb_destroy(struct drm_file
*file
,
257 struct drm_device
*dev
,
260 return drm_gem_handle_delete(file
, handle
);
264 * Creates a new mm object and returns a handle to it.
267 i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
268 struct drm_file
*file
)
270 struct drm_i915_gem_create
*args
= data
;
272 return i915_gem_create(file
, dev
,
273 args
->size
, &args
->handle
);
277 __copy_to_user_swizzled(char __user
*cpu_vaddr
,
278 const char *gpu_vaddr
, int gpu_offset
,
281 int ret
, cpu_offset
= 0;
284 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
285 int this_length
= min(cacheline_end
- gpu_offset
, length
);
286 int swizzled_gpu_offset
= gpu_offset
^ 64;
288 ret
= __copy_to_user(cpu_vaddr
+ cpu_offset
,
289 gpu_vaddr
+ swizzled_gpu_offset
,
294 cpu_offset
+= this_length
;
295 gpu_offset
+= this_length
;
296 length
-= this_length
;
303 __copy_from_user_swizzled(char *gpu_vaddr
, int gpu_offset
,
304 const char __user
*cpu_vaddr
,
307 int ret
, cpu_offset
= 0;
310 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
311 int this_length
= min(cacheline_end
- gpu_offset
, length
);
312 int swizzled_gpu_offset
= gpu_offset
^ 64;
314 ret
= __copy_from_user(gpu_vaddr
+ swizzled_gpu_offset
,
315 cpu_vaddr
+ cpu_offset
,
320 cpu_offset
+= this_length
;
321 gpu_offset
+= this_length
;
322 length
-= this_length
;
328 /* Per-page copy function for the shmem pread fastpath.
329 * Flushes invalid cachelines before reading the target if
330 * needs_clflush is set. */
332 shmem_pread_fast(struct page
*page
, int shmem_page_offset
, int page_length
,
333 char __user
*user_data
,
334 bool page_do_bit17_swizzling
, bool needs_clflush
)
339 if (unlikely(page_do_bit17_swizzling
))
342 vaddr
= kmap_atomic(page
);
344 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
346 ret
= __copy_to_user_inatomic(user_data
,
347 vaddr
+ shmem_page_offset
,
349 kunmap_atomic(vaddr
);
351 return ret
? -EFAULT
: 0;
355 shmem_clflush_swizzled_range(char *addr
, unsigned long length
,
358 if (unlikely(swizzled
)) {
359 unsigned long start
= (unsigned long) addr
;
360 unsigned long end
= (unsigned long) addr
+ length
;
362 /* For swizzling simply ensure that we always flush both
363 * channels. Lame, but simple and it works. Swizzled
364 * pwrite/pread is far from a hotpath - current userspace
365 * doesn't use it at all. */
366 start
= round_down(start
, 128);
367 end
= round_up(end
, 128);
369 drm_clflush_virt_range((void *)start
, end
- start
);
371 drm_clflush_virt_range(addr
, length
);
376 /* Only difference to the fast-path function is that this can handle bit17
377 * and uses non-atomic copy and kmap functions. */
379 shmem_pread_slow(struct page
*page
, int shmem_page_offset
, int page_length
,
380 char __user
*user_data
,
381 bool page_do_bit17_swizzling
, bool needs_clflush
)
388 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
390 page_do_bit17_swizzling
);
392 if (page_do_bit17_swizzling
)
393 ret
= __copy_to_user_swizzled(user_data
,
394 vaddr
, shmem_page_offset
,
397 ret
= __copy_to_user(user_data
,
398 vaddr
+ shmem_page_offset
,
402 return ret
? - EFAULT
: 0;
406 i915_gem_shmem_pread(struct drm_device
*dev
,
407 struct drm_i915_gem_object
*obj
,
408 struct drm_i915_gem_pread
*args
,
409 struct drm_file
*file
)
411 char __user
*user_data
;
414 int shmem_page_offset
, page_length
, ret
= 0;
415 int obj_do_bit17_swizzling
, page_do_bit17_swizzling
;
417 int needs_clflush
= 0;
418 struct scatterlist
*sg
;
421 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
424 obj_do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
426 if (!(obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
)) {
427 /* If we're not in the cpu read domain, set ourself into the gtt
428 * read domain and manually flush cachelines (if required). This
429 * optimizes for the case when the gpu will dirty the data
430 * anyway again before the next pread happens. */
431 if (obj
->cache_level
== I915_CACHE_NONE
)
433 if (obj
->gtt_space
) {
434 ret
= i915_gem_object_set_to_gtt_domain(obj
, false);
440 ret
= i915_gem_object_get_pages(obj
);
444 i915_gem_object_pin_pages(obj
);
446 offset
= args
->offset
;
448 for_each_sg(obj
->pages
->sgl
, sg
, obj
->pages
->nents
, i
) {
451 if (i
< offset
>> PAGE_SHIFT
)
457 /* Operation in this page
459 * shmem_page_offset = offset within page in shmem file
460 * page_length = bytes to copy for this page
462 shmem_page_offset
= offset_in_page(offset
);
463 page_length
= remain
;
464 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
465 page_length
= PAGE_SIZE
- shmem_page_offset
;
468 page_do_bit17_swizzling
= obj_do_bit17_swizzling
&&
469 (page_to_phys(page
) & (1 << 17)) != 0;
471 ret
= shmem_pread_fast(page
, shmem_page_offset
, page_length
,
472 user_data
, page_do_bit17_swizzling
,
477 mutex_unlock(&dev
->struct_mutex
);
480 ret
= fault_in_multipages_writeable(user_data
, remain
);
481 /* Userspace is tricking us, but we've already clobbered
482 * its pages with the prefault and promised to write the
483 * data up to the first fault. Hence ignore any errors
484 * and just continue. */
489 ret
= shmem_pread_slow(page
, shmem_page_offset
, page_length
,
490 user_data
, page_do_bit17_swizzling
,
493 mutex_lock(&dev
->struct_mutex
);
496 mark_page_accessed(page
);
501 remain
-= page_length
;
502 user_data
+= page_length
;
503 offset
+= page_length
;
507 i915_gem_object_unpin_pages(obj
);
513 * Reads data from the object referenced by handle.
515 * On error, the contents of *data are undefined.
518 i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
519 struct drm_file
*file
)
521 struct drm_i915_gem_pread
*args
= data
;
522 struct drm_i915_gem_object
*obj
;
528 if (!access_ok(VERIFY_WRITE
,
529 (char __user
*)(uintptr_t)args
->data_ptr
,
533 ret
= i915_mutex_lock_interruptible(dev
);
537 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
538 if (&obj
->base
== NULL
) {
543 /* Bounds check source. */
544 if (args
->offset
> obj
->base
.size
||
545 args
->size
> obj
->base
.size
- args
->offset
) {
550 /* prime objects have no backing filp to GEM pread/pwrite
553 if (!obj
->base
.filp
) {
558 trace_i915_gem_object_pread(obj
, args
->offset
, args
->size
);
560 ret
= i915_gem_shmem_pread(dev
, obj
, args
, file
);
563 drm_gem_object_unreference(&obj
->base
);
565 mutex_unlock(&dev
->struct_mutex
);
569 /* This is the fast write path which cannot handle
570 * page faults in the source data
574 fast_user_write(struct io_mapping
*mapping
,
575 loff_t page_base
, int page_offset
,
576 char __user
*user_data
,
579 void __iomem
*vaddr_atomic
;
581 unsigned long unwritten
;
583 vaddr_atomic
= io_mapping_map_atomic_wc(mapping
, page_base
);
584 /* We can use the cpu mem copy function because this is X86. */
585 vaddr
= (void __force
*)vaddr_atomic
+ page_offset
;
586 unwritten
= __copy_from_user_inatomic_nocache(vaddr
,
588 io_mapping_unmap_atomic(vaddr_atomic
);
593 * This is the fast pwrite path, where we copy the data directly from the
594 * user into the GTT, uncached.
597 i915_gem_gtt_pwrite_fast(struct drm_device
*dev
,
598 struct drm_i915_gem_object
*obj
,
599 struct drm_i915_gem_pwrite
*args
,
600 struct drm_file
*file
)
602 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
604 loff_t offset
, page_base
;
605 char __user
*user_data
;
606 int page_offset
, page_length
, ret
;
608 ret
= i915_gem_object_pin(obj
, 0, true, true);
612 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
616 ret
= i915_gem_object_put_fence(obj
);
620 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
623 offset
= obj
->gtt_offset
+ args
->offset
;
626 /* Operation in this page
628 * page_base = page offset within aperture
629 * page_offset = offset within page
630 * page_length = bytes to copy for this page
632 page_base
= offset
& PAGE_MASK
;
633 page_offset
= offset_in_page(offset
);
634 page_length
= remain
;
635 if ((page_offset
+ remain
) > PAGE_SIZE
)
636 page_length
= PAGE_SIZE
- page_offset
;
638 /* If we get a fault while copying data, then (presumably) our
639 * source page isn't available. Return the error and we'll
640 * retry in the slow path.
642 if (fast_user_write(dev_priv
->gtt
.mappable
, page_base
,
643 page_offset
, user_data
, page_length
)) {
648 remain
-= page_length
;
649 user_data
+= page_length
;
650 offset
+= page_length
;
654 i915_gem_object_unpin(obj
);
659 /* Per-page copy function for the shmem pwrite fastpath.
660 * Flushes invalid cachelines before writing to the target if
661 * needs_clflush_before is set and flushes out any written cachelines after
662 * writing if needs_clflush is set. */
664 shmem_pwrite_fast(struct page
*page
, int shmem_page_offset
, int page_length
,
665 char __user
*user_data
,
666 bool page_do_bit17_swizzling
,
667 bool needs_clflush_before
,
668 bool needs_clflush_after
)
673 if (unlikely(page_do_bit17_swizzling
))
676 vaddr
= kmap_atomic(page
);
677 if (needs_clflush_before
)
678 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
680 ret
= __copy_from_user_inatomic_nocache(vaddr
+ shmem_page_offset
,
683 if (needs_clflush_after
)
684 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
686 kunmap_atomic(vaddr
);
688 return ret
? -EFAULT
: 0;
691 /* Only difference to the fast-path function is that this can handle bit17
692 * and uses non-atomic copy and kmap functions. */
694 shmem_pwrite_slow(struct page
*page
, int shmem_page_offset
, int page_length
,
695 char __user
*user_data
,
696 bool page_do_bit17_swizzling
,
697 bool needs_clflush_before
,
698 bool needs_clflush_after
)
704 if (unlikely(needs_clflush_before
|| page_do_bit17_swizzling
))
705 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
707 page_do_bit17_swizzling
);
708 if (page_do_bit17_swizzling
)
709 ret
= __copy_from_user_swizzled(vaddr
, shmem_page_offset
,
713 ret
= __copy_from_user(vaddr
+ shmem_page_offset
,
716 if (needs_clflush_after
)
717 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
719 page_do_bit17_swizzling
);
722 return ret
? -EFAULT
: 0;
726 i915_gem_shmem_pwrite(struct drm_device
*dev
,
727 struct drm_i915_gem_object
*obj
,
728 struct drm_i915_gem_pwrite
*args
,
729 struct drm_file
*file
)
733 char __user
*user_data
;
734 int shmem_page_offset
, page_length
, ret
= 0;
735 int obj_do_bit17_swizzling
, page_do_bit17_swizzling
;
736 int hit_slowpath
= 0;
737 int needs_clflush_after
= 0;
738 int needs_clflush_before
= 0;
740 struct scatterlist
*sg
;
742 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
745 obj_do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
747 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
748 /* If we're not in the cpu write domain, set ourself into the gtt
749 * write domain and manually flush cachelines (if required). This
750 * optimizes for the case when the gpu will use the data
751 * right away and we therefore have to clflush anyway. */
752 if (obj
->cache_level
== I915_CACHE_NONE
)
753 needs_clflush_after
= 1;
754 if (obj
->gtt_space
) {
755 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
760 /* Same trick applies for invalidate partially written cachelines before
762 if (!(obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
)
763 && obj
->cache_level
== I915_CACHE_NONE
)
764 needs_clflush_before
= 1;
766 ret
= i915_gem_object_get_pages(obj
);
770 i915_gem_object_pin_pages(obj
);
772 offset
= args
->offset
;
775 for_each_sg(obj
->pages
->sgl
, sg
, obj
->pages
->nents
, i
) {
777 int partial_cacheline_write
;
779 if (i
< offset
>> PAGE_SHIFT
)
785 /* Operation in this page
787 * shmem_page_offset = offset within page in shmem file
788 * page_length = bytes to copy for this page
790 shmem_page_offset
= offset_in_page(offset
);
792 page_length
= remain
;
793 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
794 page_length
= PAGE_SIZE
- shmem_page_offset
;
796 /* If we don't overwrite a cacheline completely we need to be
797 * careful to have up-to-date data by first clflushing. Don't
798 * overcomplicate things and flush the entire patch. */
799 partial_cacheline_write
= needs_clflush_before
&&
800 ((shmem_page_offset
| page_length
)
801 & (boot_cpu_data
.x86_clflush_size
- 1));
804 page_do_bit17_swizzling
= obj_do_bit17_swizzling
&&
805 (page_to_phys(page
) & (1 << 17)) != 0;
807 ret
= shmem_pwrite_fast(page
, shmem_page_offset
, page_length
,
808 user_data
, page_do_bit17_swizzling
,
809 partial_cacheline_write
,
810 needs_clflush_after
);
815 mutex_unlock(&dev
->struct_mutex
);
816 ret
= shmem_pwrite_slow(page
, shmem_page_offset
, page_length
,
817 user_data
, page_do_bit17_swizzling
,
818 partial_cacheline_write
,
819 needs_clflush_after
);
821 mutex_lock(&dev
->struct_mutex
);
824 set_page_dirty(page
);
825 mark_page_accessed(page
);
830 remain
-= page_length
;
831 user_data
+= page_length
;
832 offset
+= page_length
;
836 i915_gem_object_unpin_pages(obj
);
840 * Fixup: Flush cpu caches in case we didn't flush the dirty
841 * cachelines in-line while writing and the object moved
842 * out of the cpu write domain while we've dropped the lock.
844 if (!needs_clflush_after
&&
845 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
846 i915_gem_clflush_object(obj
);
847 i915_gem_chipset_flush(dev
);
851 if (needs_clflush_after
)
852 i915_gem_chipset_flush(dev
);
858 * Writes data to the object referenced by handle.
860 * On error, the contents of the buffer that were to be modified are undefined.
863 i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
864 struct drm_file
*file
)
866 struct drm_i915_gem_pwrite
*args
= data
;
867 struct drm_i915_gem_object
*obj
;
873 if (!access_ok(VERIFY_READ
,
874 (char __user
*)(uintptr_t)args
->data_ptr
,
878 ret
= fault_in_multipages_readable((char __user
*)(uintptr_t)args
->data_ptr
,
883 ret
= i915_mutex_lock_interruptible(dev
);
887 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
888 if (&obj
->base
== NULL
) {
893 /* Bounds check destination. */
894 if (args
->offset
> obj
->base
.size
||
895 args
->size
> obj
->base
.size
- args
->offset
) {
900 /* prime objects have no backing filp to GEM pread/pwrite
903 if (!obj
->base
.filp
) {
908 trace_i915_gem_object_pwrite(obj
, args
->offset
, args
->size
);
911 /* We can only do the GTT pwrite on untiled buffers, as otherwise
912 * it would end up going through the fenced access, and we'll get
913 * different detiling behavior between reading and writing.
914 * pread/pwrite currently are reading and writing from the CPU
915 * perspective, requiring manual detiling by the client.
918 ret
= i915_gem_phys_pwrite(dev
, obj
, args
, file
);
922 if (obj
->cache_level
== I915_CACHE_NONE
&&
923 obj
->tiling_mode
== I915_TILING_NONE
&&
924 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
925 ret
= i915_gem_gtt_pwrite_fast(dev
, obj
, args
, file
);
926 /* Note that the gtt paths might fail with non-page-backed user
927 * pointers (e.g. gtt mappings when moving data between
928 * textures). Fallback to the shmem path in that case. */
931 if (ret
== -EFAULT
|| ret
== -ENOSPC
)
932 ret
= i915_gem_shmem_pwrite(dev
, obj
, args
, file
);
935 drm_gem_object_unreference(&obj
->base
);
937 mutex_unlock(&dev
->struct_mutex
);
942 i915_gem_check_wedge(struct drm_i915_private
*dev_priv
,
945 if (atomic_read(&dev_priv
->mm
.wedged
)) {
946 struct completion
*x
= &dev_priv
->gpu_error
.completion
;
947 bool recovery_complete
;
950 /* Give the error handler a chance to run. */
951 spin_lock_irqsave(&x
->wait
.lock
, flags
);
952 recovery_complete
= x
->done
> 0;
953 spin_unlock_irqrestore(&x
->wait
.lock
, flags
);
955 /* Non-interruptible callers can't handle -EAGAIN, hence return
956 * -EIO unconditionally for these. */
960 /* Recovery complete, but still wedged means reset failure. */
961 if (recovery_complete
)
971 * Compare seqno against outstanding lazy request. Emit a request if they are
975 i915_gem_check_olr(struct intel_ring_buffer
*ring
, u32 seqno
)
979 BUG_ON(!mutex_is_locked(&ring
->dev
->struct_mutex
));
982 if (seqno
== ring
->outstanding_lazy_request
)
983 ret
= i915_add_request(ring
, NULL
, NULL
);
989 * __wait_seqno - wait until execution of seqno has finished
990 * @ring: the ring expected to report seqno
992 * @interruptible: do an interruptible wait (normally yes)
993 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
995 * Returns 0 if the seqno was found within the alloted time. Else returns the
996 * errno with remaining time filled in timeout argument.
998 static int __wait_seqno(struct intel_ring_buffer
*ring
, u32 seqno
,
999 bool interruptible
, struct timespec
*timeout
)
1001 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
1002 struct timespec before
, now
, wait_time
={1,0};
1003 unsigned long timeout_jiffies
;
1005 bool wait_forever
= true;
1008 if (i915_seqno_passed(ring
->get_seqno(ring
, true), seqno
))
1011 trace_i915_gem_request_wait_begin(ring
, seqno
);
1013 if (timeout
!= NULL
) {
1014 wait_time
= *timeout
;
1015 wait_forever
= false;
1018 timeout_jiffies
= timespec_to_jiffies(&wait_time
);
1020 if (WARN_ON(!ring
->irq_get(ring
)))
1023 /* Record current time in case interrupted by signal, or wedged * */
1024 getrawmonotonic(&before
);
1027 (i915_seqno_passed(ring->get_seqno(ring, false), seqno) || \
1028 atomic_read(&dev_priv->mm.wedged))
1031 end
= wait_event_interruptible_timeout(ring
->irq_queue
,
1035 end
= wait_event_timeout(ring
->irq_queue
, EXIT_COND
,
1038 ret
= i915_gem_check_wedge(dev_priv
, interruptible
);
1041 } while (end
== 0 && wait_forever
);
1043 getrawmonotonic(&now
);
1045 ring
->irq_put(ring
);
1046 trace_i915_gem_request_wait_end(ring
, seqno
);
1050 struct timespec sleep_time
= timespec_sub(now
, before
);
1051 *timeout
= timespec_sub(*timeout
, sleep_time
);
1056 case -EAGAIN
: /* Wedged */
1057 case -ERESTARTSYS
: /* Signal */
1059 case 0: /* Timeout */
1061 set_normalized_timespec(timeout
, 0, 0);
1063 default: /* Completed */
1064 WARN_ON(end
< 0); /* We're not aware of other errors */
1070 * Waits for a sequence number to be signaled, and cleans up the
1071 * request and object lists appropriately for that event.
1074 i915_wait_seqno(struct intel_ring_buffer
*ring
, uint32_t seqno
)
1076 struct drm_device
*dev
= ring
->dev
;
1077 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1078 bool interruptible
= dev_priv
->mm
.interruptible
;
1081 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
1084 ret
= i915_gem_check_wedge(dev_priv
, interruptible
);
1088 ret
= i915_gem_check_olr(ring
, seqno
);
1092 return __wait_seqno(ring
, seqno
, interruptible
, NULL
);
1096 * Ensures that all rendering to the object has completed and the object is
1097 * safe to unbind from the GTT or access from the CPU.
1099 static __must_check
int
1100 i915_gem_object_wait_rendering(struct drm_i915_gem_object
*obj
,
1103 struct intel_ring_buffer
*ring
= obj
->ring
;
1107 seqno
= readonly
? obj
->last_write_seqno
: obj
->last_read_seqno
;
1111 ret
= i915_wait_seqno(ring
, seqno
);
1115 i915_gem_retire_requests_ring(ring
);
1117 /* Manually manage the write flush as we may have not yet
1118 * retired the buffer.
1120 if (obj
->last_write_seqno
&&
1121 i915_seqno_passed(seqno
, obj
->last_write_seqno
)) {
1122 obj
->last_write_seqno
= 0;
1123 obj
->base
.write_domain
&= ~I915_GEM_GPU_DOMAINS
;
1129 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1130 * as the object state may change during this call.
1132 static __must_check
int
1133 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object
*obj
,
1136 struct drm_device
*dev
= obj
->base
.dev
;
1137 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1138 struct intel_ring_buffer
*ring
= obj
->ring
;
1142 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
1143 BUG_ON(!dev_priv
->mm
.interruptible
);
1145 seqno
= readonly
? obj
->last_write_seqno
: obj
->last_read_seqno
;
1149 ret
= i915_gem_check_wedge(dev_priv
, true);
1153 ret
= i915_gem_check_olr(ring
, seqno
);
1157 mutex_unlock(&dev
->struct_mutex
);
1158 ret
= __wait_seqno(ring
, seqno
, true, NULL
);
1159 mutex_lock(&dev
->struct_mutex
);
1161 i915_gem_retire_requests_ring(ring
);
1163 /* Manually manage the write flush as we may have not yet
1164 * retired the buffer.
1166 if (obj
->last_write_seqno
&&
1167 i915_seqno_passed(seqno
, obj
->last_write_seqno
)) {
1168 obj
->last_write_seqno
= 0;
1169 obj
->base
.write_domain
&= ~I915_GEM_GPU_DOMAINS
;
1176 * Called when user space prepares to use an object with the CPU, either
1177 * through the mmap ioctl's mapping or a GTT mapping.
1180 i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
1181 struct drm_file
*file
)
1183 struct drm_i915_gem_set_domain
*args
= data
;
1184 struct drm_i915_gem_object
*obj
;
1185 uint32_t read_domains
= args
->read_domains
;
1186 uint32_t write_domain
= args
->write_domain
;
1189 /* Only handle setting domains to types used by the CPU. */
1190 if (write_domain
& I915_GEM_GPU_DOMAINS
)
1193 if (read_domains
& I915_GEM_GPU_DOMAINS
)
1196 /* Having something in the write domain implies it's in the read
1197 * domain, and only that read domain. Enforce that in the request.
1199 if (write_domain
!= 0 && read_domains
!= write_domain
)
1202 ret
= i915_mutex_lock_interruptible(dev
);
1206 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1207 if (&obj
->base
== NULL
) {
1212 /* Try to flush the object off the GPU without holding the lock.
1213 * We will repeat the flush holding the lock in the normal manner
1214 * to catch cases where we are gazumped.
1216 ret
= i915_gem_object_wait_rendering__nonblocking(obj
, !write_domain
);
1220 if (read_domains
& I915_GEM_DOMAIN_GTT
) {
1221 ret
= i915_gem_object_set_to_gtt_domain(obj
, write_domain
!= 0);
1223 /* Silently promote "you're not bound, there was nothing to do"
1224 * to success, since the client was just asking us to
1225 * make sure everything was done.
1230 ret
= i915_gem_object_set_to_cpu_domain(obj
, write_domain
!= 0);
1234 drm_gem_object_unreference(&obj
->base
);
1236 mutex_unlock(&dev
->struct_mutex
);
1241 * Called when user space has done writes to this buffer
1244 i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1245 struct drm_file
*file
)
1247 struct drm_i915_gem_sw_finish
*args
= data
;
1248 struct drm_i915_gem_object
*obj
;
1251 ret
= i915_mutex_lock_interruptible(dev
);
1255 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1256 if (&obj
->base
== NULL
) {
1261 /* Pinned buffers may be scanout, so flush the cache */
1263 i915_gem_object_flush_cpu_write_domain(obj
);
1265 drm_gem_object_unreference(&obj
->base
);
1267 mutex_unlock(&dev
->struct_mutex
);
1272 * Maps the contents of an object, returning the address it is mapped
1275 * While the mapping holds a reference on the contents of the object, it doesn't
1276 * imply a ref on the object itself.
1279 i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1280 struct drm_file
*file
)
1282 struct drm_i915_gem_mmap
*args
= data
;
1283 struct drm_gem_object
*obj
;
1286 obj
= drm_gem_object_lookup(dev
, file
, args
->handle
);
1290 /* prime objects have no backing filp to GEM mmap
1294 drm_gem_object_unreference_unlocked(obj
);
1298 addr
= vm_mmap(obj
->filp
, 0, args
->size
,
1299 PROT_READ
| PROT_WRITE
, MAP_SHARED
,
1301 drm_gem_object_unreference_unlocked(obj
);
1302 if (IS_ERR((void *)addr
))
1305 args
->addr_ptr
= (uint64_t) addr
;
1311 * i915_gem_fault - fault a page into the GTT
1312 * vma: VMA in question
1315 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1316 * from userspace. The fault handler takes care of binding the object to
1317 * the GTT (if needed), allocating and programming a fence register (again,
1318 * only if needed based on whether the old reg is still valid or the object
1319 * is tiled) and inserting a new PTE into the faulting process.
1321 * Note that the faulting process may involve evicting existing objects
1322 * from the GTT and/or fence registers to make room. So performance may
1323 * suffer if the GTT working set is large or there are few fence registers
1326 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
)
1328 struct drm_i915_gem_object
*obj
= to_intel_bo(vma
->vm_private_data
);
1329 struct drm_device
*dev
= obj
->base
.dev
;
1330 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1331 pgoff_t page_offset
;
1334 bool write
= !!(vmf
->flags
& FAULT_FLAG_WRITE
);
1336 /* We don't use vmf->pgoff since that has the fake offset */
1337 page_offset
= ((unsigned long)vmf
->virtual_address
- vma
->vm_start
) >>
1340 ret
= i915_mutex_lock_interruptible(dev
);
1344 trace_i915_gem_object_fault(obj
, page_offset
, true, write
);
1346 /* Access to snoopable pages through the GTT is incoherent. */
1347 if (obj
->cache_level
!= I915_CACHE_NONE
&& !HAS_LLC(dev
)) {
1352 /* Now bind it into the GTT if needed */
1353 ret
= i915_gem_object_pin(obj
, 0, true, false);
1357 ret
= i915_gem_object_set_to_gtt_domain(obj
, write
);
1361 ret
= i915_gem_object_get_fence(obj
);
1365 obj
->fault_mappable
= true;
1367 pfn
= ((dev_priv
->gtt
.mappable_base
+ obj
->gtt_offset
) >> PAGE_SHIFT
) +
1370 /* Finally, remap it using the new GTT offset */
1371 ret
= vm_insert_pfn(vma
, (unsigned long)vmf
->virtual_address
, pfn
);
1373 i915_gem_object_unpin(obj
);
1375 mutex_unlock(&dev
->struct_mutex
);
1379 /* If this -EIO is due to a gpu hang, give the reset code a
1380 * chance to clean up the mess. Otherwise return the proper
1382 if (!atomic_read(&dev_priv
->mm
.wedged
))
1383 return VM_FAULT_SIGBUS
;
1385 /* Give the error handler a chance to run and move the
1386 * objects off the GPU active list. Next time we service the
1387 * fault, we should be able to transition the page into the
1388 * GTT without touching the GPU (and so avoid further
1389 * EIO/EGAIN). If the GPU is wedged, then there is no issue
1390 * with coherency, just lost writes.
1398 * EBUSY is ok: this just means that another thread
1399 * already did the job.
1401 return VM_FAULT_NOPAGE
;
1403 return VM_FAULT_OOM
;
1405 return VM_FAULT_SIGBUS
;
1407 WARN_ONCE(ret
, "unhandled error in i915_gem_fault: %i\n", ret
);
1408 return VM_FAULT_SIGBUS
;
1413 * i915_gem_release_mmap - remove physical page mappings
1414 * @obj: obj in question
1416 * Preserve the reservation of the mmapping with the DRM core code, but
1417 * relinquish ownership of the pages back to the system.
1419 * It is vital that we remove the page mapping if we have mapped a tiled
1420 * object through the GTT and then lose the fence register due to
1421 * resource pressure. Similarly if the object has been moved out of the
1422 * aperture, than pages mapped into userspace must be revoked. Removing the
1423 * mapping will then trigger a page fault on the next user access, allowing
1424 * fixup by i915_gem_fault().
1427 i915_gem_release_mmap(struct drm_i915_gem_object
*obj
)
1429 if (!obj
->fault_mappable
)
1432 if (obj
->base
.dev
->dev_mapping
)
1433 unmap_mapping_range(obj
->base
.dev
->dev_mapping
,
1434 (loff_t
)obj
->base
.map_list
.hash
.key
<<PAGE_SHIFT
,
1437 obj
->fault_mappable
= false;
1441 i915_gem_get_gtt_size(struct drm_device
*dev
, uint32_t size
, int tiling_mode
)
1445 if (INTEL_INFO(dev
)->gen
>= 4 ||
1446 tiling_mode
== I915_TILING_NONE
)
1449 /* Previous chips need a power-of-two fence region when tiling */
1450 if (INTEL_INFO(dev
)->gen
== 3)
1451 gtt_size
= 1024*1024;
1453 gtt_size
= 512*1024;
1455 while (gtt_size
< size
)
1462 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1463 * @obj: object to check
1465 * Return the required GTT alignment for an object, taking into account
1466 * potential fence register mapping.
1469 i915_gem_get_gtt_alignment(struct drm_device
*dev
, uint32_t size
,
1470 int tiling_mode
, bool fenced
)
1473 * Minimum alignment is 4k (GTT page size), but might be greater
1474 * if a fence register is needed for the object.
1476 if (INTEL_INFO(dev
)->gen
>= 4 || (!fenced
&& IS_G33(dev
)) ||
1477 tiling_mode
== I915_TILING_NONE
)
1481 * Previous chips need to be aligned to the size of the smallest
1482 * fence register that can contain the object.
1484 return i915_gem_get_gtt_size(dev
, size
, tiling_mode
);
1487 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object
*obj
)
1489 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
1492 if (obj
->base
.map_list
.map
)
1495 dev_priv
->mm
.shrinker_no_lock_stealing
= true;
1497 ret
= drm_gem_create_mmap_offset(&obj
->base
);
1501 /* Badly fragmented mmap space? The only way we can recover
1502 * space is by destroying unwanted objects. We can't randomly release
1503 * mmap_offsets as userspace expects them to be persistent for the
1504 * lifetime of the objects. The closest we can is to release the
1505 * offsets on purgeable objects by truncating it and marking it purged,
1506 * which prevents userspace from ever using that object again.
1508 i915_gem_purge(dev_priv
, obj
->base
.size
>> PAGE_SHIFT
);
1509 ret
= drm_gem_create_mmap_offset(&obj
->base
);
1513 i915_gem_shrink_all(dev_priv
);
1514 ret
= drm_gem_create_mmap_offset(&obj
->base
);
1516 dev_priv
->mm
.shrinker_no_lock_stealing
= false;
1521 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object
*obj
)
1523 if (!obj
->base
.map_list
.map
)
1526 drm_gem_free_mmap_offset(&obj
->base
);
1530 i915_gem_mmap_gtt(struct drm_file
*file
,
1531 struct drm_device
*dev
,
1535 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1536 struct drm_i915_gem_object
*obj
;
1539 ret
= i915_mutex_lock_interruptible(dev
);
1543 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, handle
));
1544 if (&obj
->base
== NULL
) {
1549 if (obj
->base
.size
> dev_priv
->gtt
.mappable_end
) {
1554 if (obj
->madv
!= I915_MADV_WILLNEED
) {
1555 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1560 ret
= i915_gem_object_create_mmap_offset(obj
);
1564 *offset
= (u64
)obj
->base
.map_list
.hash
.key
<< PAGE_SHIFT
;
1567 drm_gem_object_unreference(&obj
->base
);
1569 mutex_unlock(&dev
->struct_mutex
);
1574 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1576 * @data: GTT mapping ioctl data
1577 * @file: GEM object info
1579 * Simply returns the fake offset to userspace so it can mmap it.
1580 * The mmap call will end up in drm_gem_mmap(), which will set things
1581 * up so we can get faults in the handler above.
1583 * The fault handler will take care of binding the object into the GTT
1584 * (since it may have been evicted to make room for something), allocating
1585 * a fence register, and mapping the appropriate aperture address into
1589 i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
1590 struct drm_file
*file
)
1592 struct drm_i915_gem_mmap_gtt
*args
= data
;
1594 return i915_gem_mmap_gtt(file
, dev
, args
->handle
, &args
->offset
);
1597 /* Immediately discard the backing storage */
1599 i915_gem_object_truncate(struct drm_i915_gem_object
*obj
)
1601 struct inode
*inode
;
1603 i915_gem_object_free_mmap_offset(obj
);
1605 if (obj
->base
.filp
== NULL
)
1608 /* Our goal here is to return as much of the memory as
1609 * is possible back to the system as we are called from OOM.
1610 * To do this we must instruct the shmfs to drop all of its
1611 * backing pages, *now*.
1613 inode
= obj
->base
.filp
->f_path
.dentry
->d_inode
;
1614 shmem_truncate_range(inode
, 0, (loff_t
)-1);
1616 obj
->madv
= __I915_MADV_PURGED
;
1620 i915_gem_object_is_purgeable(struct drm_i915_gem_object
*obj
)
1622 return obj
->madv
== I915_MADV_DONTNEED
;
1626 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object
*obj
)
1628 int page_count
= obj
->base
.size
/ PAGE_SIZE
;
1629 struct scatterlist
*sg
;
1632 BUG_ON(obj
->madv
== __I915_MADV_PURGED
);
1634 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
1636 /* In the event of a disaster, abandon all caches and
1637 * hope for the best.
1639 WARN_ON(ret
!= -EIO
);
1640 i915_gem_clflush_object(obj
);
1641 obj
->base
.read_domains
= obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
1644 if (i915_gem_object_needs_bit17_swizzle(obj
))
1645 i915_gem_object_save_bit_17_swizzle(obj
);
1647 if (obj
->madv
== I915_MADV_DONTNEED
)
1650 for_each_sg(obj
->pages
->sgl
, sg
, page_count
, i
) {
1651 struct page
*page
= sg_page(sg
);
1654 set_page_dirty(page
);
1656 if (obj
->madv
== I915_MADV_WILLNEED
)
1657 mark_page_accessed(page
);
1659 page_cache_release(page
);
1663 sg_free_table(obj
->pages
);
1668 i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
)
1670 const struct drm_i915_gem_object_ops
*ops
= obj
->ops
;
1672 if (obj
->pages
== NULL
)
1675 BUG_ON(obj
->gtt_space
);
1677 if (obj
->pages_pin_count
)
1680 /* ->put_pages might need to allocate memory for the bit17 swizzle
1681 * array, hence protect them from being reaped by removing them from gtt
1683 list_del(&obj
->gtt_list
);
1685 ops
->put_pages(obj
);
1688 if (i915_gem_object_is_purgeable(obj
))
1689 i915_gem_object_truncate(obj
);
1695 i915_gem_purge(struct drm_i915_private
*dev_priv
, long target
)
1697 struct drm_i915_gem_object
*obj
, *next
;
1700 list_for_each_entry_safe(obj
, next
,
1701 &dev_priv
->mm
.unbound_list
,
1703 if (i915_gem_object_is_purgeable(obj
) &&
1704 i915_gem_object_put_pages(obj
) == 0) {
1705 count
+= obj
->base
.size
>> PAGE_SHIFT
;
1706 if (count
>= target
)
1711 list_for_each_entry_safe(obj
, next
,
1712 &dev_priv
->mm
.inactive_list
,
1714 if (i915_gem_object_is_purgeable(obj
) &&
1715 i915_gem_object_unbind(obj
) == 0 &&
1716 i915_gem_object_put_pages(obj
) == 0) {
1717 count
+= obj
->base
.size
>> PAGE_SHIFT
;
1718 if (count
>= target
)
1727 i915_gem_shrink_all(struct drm_i915_private
*dev_priv
)
1729 struct drm_i915_gem_object
*obj
, *next
;
1731 i915_gem_evict_everything(dev_priv
->dev
);
1733 list_for_each_entry_safe(obj
, next
, &dev_priv
->mm
.unbound_list
, gtt_list
)
1734 i915_gem_object_put_pages(obj
);
1738 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object
*obj
)
1740 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
1742 struct address_space
*mapping
;
1743 struct sg_table
*st
;
1744 struct scatterlist
*sg
;
1748 /* Assert that the object is not currently in any GPU domain. As it
1749 * wasn't in the GTT, there shouldn't be any way it could have been in
1752 BUG_ON(obj
->base
.read_domains
& I915_GEM_GPU_DOMAINS
);
1753 BUG_ON(obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
);
1755 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
1759 page_count
= obj
->base
.size
/ PAGE_SIZE
;
1760 if (sg_alloc_table(st
, page_count
, GFP_KERNEL
)) {
1766 /* Get the list of pages out of our struct file. They'll be pinned
1767 * at this point until we release them.
1769 * Fail silently without starting the shrinker
1771 mapping
= obj
->base
.filp
->f_path
.dentry
->d_inode
->i_mapping
;
1772 gfp
= mapping_gfp_mask(mapping
);
1773 gfp
|= __GFP_NORETRY
| __GFP_NOWARN
| __GFP_NO_KSWAPD
;
1774 gfp
&= ~(__GFP_IO
| __GFP_WAIT
);
1775 for_each_sg(st
->sgl
, sg
, page_count
, i
) {
1776 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
1778 i915_gem_purge(dev_priv
, page_count
);
1779 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
1782 /* We've tried hard to allocate the memory by reaping
1783 * our own buffer, now let the real VM do its job and
1784 * go down in flames if truly OOM.
1786 gfp
&= ~(__GFP_NORETRY
| __GFP_NOWARN
| __GFP_NO_KSWAPD
);
1787 gfp
|= __GFP_IO
| __GFP_WAIT
;
1789 i915_gem_shrink_all(dev_priv
);
1790 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
1794 gfp
|= __GFP_NORETRY
| __GFP_NOWARN
| __GFP_NO_KSWAPD
;
1795 gfp
&= ~(__GFP_IO
| __GFP_WAIT
);
1798 sg_set_page(sg
, page
, PAGE_SIZE
, 0);
1803 if (i915_gem_object_needs_bit17_swizzle(obj
))
1804 i915_gem_object_do_bit_17_swizzle(obj
);
1809 for_each_sg(st
->sgl
, sg
, i
, page_count
)
1810 page_cache_release(sg_page(sg
));
1813 return PTR_ERR(page
);
1816 /* Ensure that the associated pages are gathered from the backing storage
1817 * and pinned into our object. i915_gem_object_get_pages() may be called
1818 * multiple times before they are released by a single call to
1819 * i915_gem_object_put_pages() - once the pages are no longer referenced
1820 * either as a result of memory pressure (reaping pages under the shrinker)
1821 * or as the object is itself released.
1824 i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
)
1826 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
1827 const struct drm_i915_gem_object_ops
*ops
= obj
->ops
;
1833 if (obj
->madv
!= I915_MADV_WILLNEED
) {
1834 DRM_ERROR("Attempting to obtain a purgeable object\n");
1838 BUG_ON(obj
->pages_pin_count
);
1840 ret
= ops
->get_pages(obj
);
1844 list_add_tail(&obj
->gtt_list
, &dev_priv
->mm
.unbound_list
);
1849 i915_gem_object_move_to_active(struct drm_i915_gem_object
*obj
,
1850 struct intel_ring_buffer
*ring
)
1852 struct drm_device
*dev
= obj
->base
.dev
;
1853 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1854 u32 seqno
= intel_ring_get_seqno(ring
);
1856 BUG_ON(ring
== NULL
);
1859 /* Add a reference if we're newly entering the active list. */
1861 drm_gem_object_reference(&obj
->base
);
1865 /* Move from whatever list we were on to the tail of execution. */
1866 list_move_tail(&obj
->mm_list
, &dev_priv
->mm
.active_list
);
1867 list_move_tail(&obj
->ring_list
, &ring
->active_list
);
1869 obj
->last_read_seqno
= seqno
;
1871 if (obj
->fenced_gpu_access
) {
1872 obj
->last_fenced_seqno
= seqno
;
1874 /* Bump MRU to take account of the delayed flush */
1875 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
1876 struct drm_i915_fence_reg
*reg
;
1878 reg
= &dev_priv
->fence_regs
[obj
->fence_reg
];
1879 list_move_tail(®
->lru_list
,
1880 &dev_priv
->mm
.fence_list
);
1886 i915_gem_object_move_to_inactive(struct drm_i915_gem_object
*obj
)
1888 struct drm_device
*dev
= obj
->base
.dev
;
1889 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1891 BUG_ON(obj
->base
.write_domain
& ~I915_GEM_GPU_DOMAINS
);
1892 BUG_ON(!obj
->active
);
1894 if (obj
->pin_count
) /* are we a framebuffer? */
1895 intel_mark_fb_idle(obj
);
1897 list_move_tail(&obj
->mm_list
, &dev_priv
->mm
.inactive_list
);
1899 list_del_init(&obj
->ring_list
);
1902 obj
->last_read_seqno
= 0;
1903 obj
->last_write_seqno
= 0;
1904 obj
->base
.write_domain
= 0;
1906 obj
->last_fenced_seqno
= 0;
1907 obj
->fenced_gpu_access
= false;
1910 drm_gem_object_unreference(&obj
->base
);
1912 WARN_ON(i915_verify_lists(dev
));
1916 i915_gem_init_seqno(struct drm_device
*dev
, u32 seqno
)
1918 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1919 struct intel_ring_buffer
*ring
;
1922 /* Carefully retire all requests without writing to the rings */
1923 for_each_ring(ring
, dev_priv
, i
) {
1924 ret
= intel_ring_idle(ring
);
1928 i915_gem_retire_requests(dev
);
1930 /* Finally reset hw state */
1931 for_each_ring(ring
, dev_priv
, i
) {
1932 intel_ring_init_seqno(ring
, seqno
);
1934 for (j
= 0; j
< ARRAY_SIZE(ring
->sync_seqno
); j
++)
1935 ring
->sync_seqno
[j
] = 0;
1941 int i915_gem_set_seqno(struct drm_device
*dev
, u32 seqno
)
1943 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1949 /* HWS page needs to be set less than what we
1950 * will inject to ring
1952 ret
= i915_gem_init_seqno(dev
, seqno
- 1);
1956 /* Carefully set the last_seqno value so that wrap
1957 * detection still works
1959 dev_priv
->next_seqno
= seqno
;
1960 dev_priv
->last_seqno
= seqno
- 1;
1961 if (dev_priv
->last_seqno
== 0)
1962 dev_priv
->last_seqno
--;
1968 i915_gem_get_seqno(struct drm_device
*dev
, u32
*seqno
)
1970 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1972 /* reserve 0 for non-seqno */
1973 if (dev_priv
->next_seqno
== 0) {
1974 int ret
= i915_gem_init_seqno(dev
, 0);
1978 dev_priv
->next_seqno
= 1;
1981 *seqno
= dev_priv
->last_seqno
= dev_priv
->next_seqno
++;
1986 i915_add_request(struct intel_ring_buffer
*ring
,
1987 struct drm_file
*file
,
1990 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
1991 struct drm_i915_gem_request
*request
;
1992 u32 request_ring_position
;
1997 * Emit any outstanding flushes - execbuf can fail to emit the flush
1998 * after having emitted the batchbuffer command. Hence we need to fix
1999 * things up similar to emitting the lazy request. The difference here
2000 * is that the flush _must_ happen before the next request, no matter
2003 ret
= intel_ring_flush_all_caches(ring
);
2007 request
= kmalloc(sizeof(*request
), GFP_KERNEL
);
2008 if (request
== NULL
)
2012 /* Record the position of the start of the request so that
2013 * should we detect the updated seqno part-way through the
2014 * GPU processing the request, we never over-estimate the
2015 * position of the head.
2017 request_ring_position
= intel_ring_get_tail(ring
);
2019 ret
= ring
->add_request(ring
);
2025 request
->seqno
= intel_ring_get_seqno(ring
);
2026 request
->ring
= ring
;
2027 request
->tail
= request_ring_position
;
2028 request
->emitted_jiffies
= jiffies
;
2029 was_empty
= list_empty(&ring
->request_list
);
2030 list_add_tail(&request
->list
, &ring
->request_list
);
2031 request
->file_priv
= NULL
;
2034 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
2036 spin_lock(&file_priv
->mm
.lock
);
2037 request
->file_priv
= file_priv
;
2038 list_add_tail(&request
->client_list
,
2039 &file_priv
->mm
.request_list
);
2040 spin_unlock(&file_priv
->mm
.lock
);
2043 trace_i915_gem_request_add(ring
, request
->seqno
);
2044 ring
->outstanding_lazy_request
= 0;
2046 if (!dev_priv
->mm
.suspended
) {
2047 if (i915_enable_hangcheck
) {
2048 mod_timer(&dev_priv
->gpu_error
.hangcheck_timer
,
2049 round_jiffies_up(jiffies
+ DRM_I915_HANGCHECK_JIFFIES
));
2052 queue_delayed_work(dev_priv
->wq
,
2053 &dev_priv
->mm
.retire_work
,
2054 round_jiffies_up_relative(HZ
));
2055 intel_mark_busy(dev_priv
->dev
);
2060 *out_seqno
= request
->seqno
;
2065 i915_gem_request_remove_from_client(struct drm_i915_gem_request
*request
)
2067 struct drm_i915_file_private
*file_priv
= request
->file_priv
;
2072 spin_lock(&file_priv
->mm
.lock
);
2073 if (request
->file_priv
) {
2074 list_del(&request
->client_list
);
2075 request
->file_priv
= NULL
;
2077 spin_unlock(&file_priv
->mm
.lock
);
2080 static void i915_gem_reset_ring_lists(struct drm_i915_private
*dev_priv
,
2081 struct intel_ring_buffer
*ring
)
2083 while (!list_empty(&ring
->request_list
)) {
2084 struct drm_i915_gem_request
*request
;
2086 request
= list_first_entry(&ring
->request_list
,
2087 struct drm_i915_gem_request
,
2090 list_del(&request
->list
);
2091 i915_gem_request_remove_from_client(request
);
2095 while (!list_empty(&ring
->active_list
)) {
2096 struct drm_i915_gem_object
*obj
;
2098 obj
= list_first_entry(&ring
->active_list
,
2099 struct drm_i915_gem_object
,
2102 i915_gem_object_move_to_inactive(obj
);
2106 static void i915_gem_reset_fences(struct drm_device
*dev
)
2108 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2111 for (i
= 0; i
< dev_priv
->num_fence_regs
; i
++) {
2112 struct drm_i915_fence_reg
*reg
= &dev_priv
->fence_regs
[i
];
2114 i915_gem_write_fence(dev
, i
, NULL
);
2117 i915_gem_object_fence_lost(reg
->obj
);
2121 INIT_LIST_HEAD(®
->lru_list
);
2124 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
2127 void i915_gem_reset(struct drm_device
*dev
)
2129 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2130 struct drm_i915_gem_object
*obj
;
2131 struct intel_ring_buffer
*ring
;
2134 for_each_ring(ring
, dev_priv
, i
)
2135 i915_gem_reset_ring_lists(dev_priv
, ring
);
2137 /* Move everything out of the GPU domains to ensure we do any
2138 * necessary invalidation upon reuse.
2140 list_for_each_entry(obj
,
2141 &dev_priv
->mm
.inactive_list
,
2144 obj
->base
.read_domains
&= ~I915_GEM_GPU_DOMAINS
;
2147 /* The fence registers are invalidated so clear them out */
2148 i915_gem_reset_fences(dev
);
2152 * This function clears the request list as sequence numbers are passed.
2155 i915_gem_retire_requests_ring(struct intel_ring_buffer
*ring
)
2159 if (list_empty(&ring
->request_list
))
2162 WARN_ON(i915_verify_lists(ring
->dev
));
2164 seqno
= ring
->get_seqno(ring
, true);
2166 while (!list_empty(&ring
->request_list
)) {
2167 struct drm_i915_gem_request
*request
;
2169 request
= list_first_entry(&ring
->request_list
,
2170 struct drm_i915_gem_request
,
2173 if (!i915_seqno_passed(seqno
, request
->seqno
))
2176 trace_i915_gem_request_retire(ring
, request
->seqno
);
2177 /* We know the GPU must have read the request to have
2178 * sent us the seqno + interrupt, so use the position
2179 * of tail of the request to update the last known position
2182 ring
->last_retired_head
= request
->tail
;
2184 list_del(&request
->list
);
2185 i915_gem_request_remove_from_client(request
);
2189 /* Move any buffers on the active list that are no longer referenced
2190 * by the ringbuffer to the flushing/inactive lists as appropriate.
2192 while (!list_empty(&ring
->active_list
)) {
2193 struct drm_i915_gem_object
*obj
;
2195 obj
= list_first_entry(&ring
->active_list
,
2196 struct drm_i915_gem_object
,
2199 if (!i915_seqno_passed(seqno
, obj
->last_read_seqno
))
2202 i915_gem_object_move_to_inactive(obj
);
2205 if (unlikely(ring
->trace_irq_seqno
&&
2206 i915_seqno_passed(seqno
, ring
->trace_irq_seqno
))) {
2207 ring
->irq_put(ring
);
2208 ring
->trace_irq_seqno
= 0;
2211 WARN_ON(i915_verify_lists(ring
->dev
));
2215 i915_gem_retire_requests(struct drm_device
*dev
)
2217 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2218 struct intel_ring_buffer
*ring
;
2221 for_each_ring(ring
, dev_priv
, i
)
2222 i915_gem_retire_requests_ring(ring
);
2226 i915_gem_retire_work_handler(struct work_struct
*work
)
2228 drm_i915_private_t
*dev_priv
;
2229 struct drm_device
*dev
;
2230 struct intel_ring_buffer
*ring
;
2234 dev_priv
= container_of(work
, drm_i915_private_t
,
2235 mm
.retire_work
.work
);
2236 dev
= dev_priv
->dev
;
2238 /* Come back later if the device is busy... */
2239 if (!mutex_trylock(&dev
->struct_mutex
)) {
2240 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
,
2241 round_jiffies_up_relative(HZ
));
2245 i915_gem_retire_requests(dev
);
2247 /* Send a periodic flush down the ring so we don't hold onto GEM
2248 * objects indefinitely.
2251 for_each_ring(ring
, dev_priv
, i
) {
2252 if (ring
->gpu_caches_dirty
)
2253 i915_add_request(ring
, NULL
, NULL
);
2255 idle
&= list_empty(&ring
->request_list
);
2258 if (!dev_priv
->mm
.suspended
&& !idle
)
2259 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
,
2260 round_jiffies_up_relative(HZ
));
2262 intel_mark_idle(dev
);
2264 mutex_unlock(&dev
->struct_mutex
);
2268 * Ensures that an object will eventually get non-busy by flushing any required
2269 * write domains, emitting any outstanding lazy request and retiring and
2270 * completed requests.
2273 i915_gem_object_flush_active(struct drm_i915_gem_object
*obj
)
2278 ret
= i915_gem_check_olr(obj
->ring
, obj
->last_read_seqno
);
2282 i915_gem_retire_requests_ring(obj
->ring
);
2289 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2290 * @DRM_IOCTL_ARGS: standard ioctl arguments
2292 * Returns 0 if successful, else an error is returned with the remaining time in
2293 * the timeout parameter.
2294 * -ETIME: object is still busy after timeout
2295 * -ERESTARTSYS: signal interrupted the wait
2296 * -ENONENT: object doesn't exist
2297 * Also possible, but rare:
2298 * -EAGAIN: GPU wedged
2300 * -ENODEV: Internal IRQ fail
2301 * -E?: The add request failed
2303 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2304 * non-zero timeout parameter the wait ioctl will wait for the given number of
2305 * nanoseconds on an object becoming unbusy. Since the wait itself does so
2306 * without holding struct_mutex the object may become re-busied before this
2307 * function completes. A similar but shorter * race condition exists in the busy
2311 i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
, struct drm_file
*file
)
2313 struct drm_i915_gem_wait
*args
= data
;
2314 struct drm_i915_gem_object
*obj
;
2315 struct intel_ring_buffer
*ring
= NULL
;
2316 struct timespec timeout_stack
, *timeout
= NULL
;
2320 if (args
->timeout_ns
>= 0) {
2321 timeout_stack
= ns_to_timespec(args
->timeout_ns
);
2322 timeout
= &timeout_stack
;
2325 ret
= i915_mutex_lock_interruptible(dev
);
2329 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->bo_handle
));
2330 if (&obj
->base
== NULL
) {
2331 mutex_unlock(&dev
->struct_mutex
);
2335 /* Need to make sure the object gets inactive eventually. */
2336 ret
= i915_gem_object_flush_active(obj
);
2341 seqno
= obj
->last_read_seqno
;
2348 /* Do this after OLR check to make sure we make forward progress polling
2349 * on this IOCTL with a 0 timeout (like busy ioctl)
2351 if (!args
->timeout_ns
) {
2356 drm_gem_object_unreference(&obj
->base
);
2357 mutex_unlock(&dev
->struct_mutex
);
2359 ret
= __wait_seqno(ring
, seqno
, true, timeout
);
2361 WARN_ON(!timespec_valid(timeout
));
2362 args
->timeout_ns
= timespec_to_ns(timeout
);
2367 drm_gem_object_unreference(&obj
->base
);
2368 mutex_unlock(&dev
->struct_mutex
);
2373 * i915_gem_object_sync - sync an object to a ring.
2375 * @obj: object which may be in use on another ring.
2376 * @to: ring we wish to use the object on. May be NULL.
2378 * This code is meant to abstract object synchronization with the GPU.
2379 * Calling with NULL implies synchronizing the object with the CPU
2380 * rather than a particular GPU ring.
2382 * Returns 0 if successful, else propagates up the lower layer error.
2385 i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
2386 struct intel_ring_buffer
*to
)
2388 struct intel_ring_buffer
*from
= obj
->ring
;
2392 if (from
== NULL
|| to
== from
)
2395 if (to
== NULL
|| !i915_semaphore_is_enabled(obj
->base
.dev
))
2396 return i915_gem_object_wait_rendering(obj
, false);
2398 idx
= intel_ring_sync_index(from
, to
);
2400 seqno
= obj
->last_read_seqno
;
2401 if (seqno
<= from
->sync_seqno
[idx
])
2404 ret
= i915_gem_check_olr(obj
->ring
, seqno
);
2408 ret
= to
->sync_to(to
, from
, seqno
);
2410 /* We use last_read_seqno because sync_to()
2411 * might have just caused seqno wrap under
2414 from
->sync_seqno
[idx
] = obj
->last_read_seqno
;
2419 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object
*obj
)
2421 u32 old_write_domain
, old_read_domains
;
2423 /* Act a barrier for all accesses through the GTT */
2426 /* Force a pagefault for domain tracking on next user access */
2427 i915_gem_release_mmap(obj
);
2429 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
) == 0)
2432 old_read_domains
= obj
->base
.read_domains
;
2433 old_write_domain
= obj
->base
.write_domain
;
2435 obj
->base
.read_domains
&= ~I915_GEM_DOMAIN_GTT
;
2436 obj
->base
.write_domain
&= ~I915_GEM_DOMAIN_GTT
;
2438 trace_i915_gem_object_change_domain(obj
,
2444 * Unbinds an object from the GTT aperture.
2447 i915_gem_object_unbind(struct drm_i915_gem_object
*obj
)
2449 drm_i915_private_t
*dev_priv
= obj
->base
.dev
->dev_private
;
2452 if (obj
->gtt_space
== NULL
)
2458 BUG_ON(obj
->pages
== NULL
);
2460 ret
= i915_gem_object_finish_gpu(obj
);
2463 /* Continue on if we fail due to EIO, the GPU is hung so we
2464 * should be safe and we need to cleanup or else we might
2465 * cause memory corruption through use-after-free.
2468 i915_gem_object_finish_gtt(obj
);
2470 /* release the fence reg _after_ flushing */
2471 ret
= i915_gem_object_put_fence(obj
);
2475 trace_i915_gem_object_unbind(obj
);
2477 if (obj
->has_global_gtt_mapping
)
2478 i915_gem_gtt_unbind_object(obj
);
2479 if (obj
->has_aliasing_ppgtt_mapping
) {
2480 i915_ppgtt_unbind_object(dev_priv
->mm
.aliasing_ppgtt
, obj
);
2481 obj
->has_aliasing_ppgtt_mapping
= 0;
2483 i915_gem_gtt_finish_object(obj
);
2485 list_del(&obj
->mm_list
);
2486 list_move_tail(&obj
->gtt_list
, &dev_priv
->mm
.unbound_list
);
2487 /* Avoid an unnecessary call to unbind on rebind. */
2488 obj
->map_and_fenceable
= true;
2490 drm_mm_put_block(obj
->gtt_space
);
2491 obj
->gtt_space
= NULL
;
2492 obj
->gtt_offset
= 0;
2497 int i915_gpu_idle(struct drm_device
*dev
)
2499 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2500 struct intel_ring_buffer
*ring
;
2503 /* Flush everything onto the inactive list. */
2504 for_each_ring(ring
, dev_priv
, i
) {
2505 ret
= i915_switch_context(ring
, NULL
, DEFAULT_CONTEXT_ID
);
2509 ret
= intel_ring_idle(ring
);
2517 static void i965_write_fence_reg(struct drm_device
*dev
, int reg
,
2518 struct drm_i915_gem_object
*obj
)
2520 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2522 int fence_pitch_shift
;
2525 if (INTEL_INFO(dev
)->gen
>= 6) {
2526 fence_reg
= FENCE_REG_SANDYBRIDGE_0
;
2527 fence_pitch_shift
= SANDYBRIDGE_FENCE_PITCH_SHIFT
;
2529 fence_reg
= FENCE_REG_965_0
;
2530 fence_pitch_shift
= I965_FENCE_PITCH_SHIFT
;
2534 u32 size
= obj
->gtt_space
->size
;
2536 val
= (uint64_t)((obj
->gtt_offset
+ size
- 4096) &
2538 val
|= obj
->gtt_offset
& 0xfffff000;
2539 val
|= (uint64_t)((obj
->stride
/ 128) - 1) << fence_pitch_shift
;
2540 if (obj
->tiling_mode
== I915_TILING_Y
)
2541 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
2542 val
|= I965_FENCE_REG_VALID
;
2546 fence_reg
+= reg
* 8;
2547 I915_WRITE64(fence_reg
, val
);
2548 POSTING_READ(fence_reg
);
2551 static void i915_write_fence_reg(struct drm_device
*dev
, int reg
,
2552 struct drm_i915_gem_object
*obj
)
2554 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2558 u32 size
= obj
->gtt_space
->size
;
2562 WARN((obj
->gtt_offset
& ~I915_FENCE_START_MASK
) ||
2563 (size
& -size
) != size
||
2564 (obj
->gtt_offset
& (size
- 1)),
2565 "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2566 obj
->gtt_offset
, obj
->map_and_fenceable
, size
);
2568 if (obj
->tiling_mode
== I915_TILING_Y
&& HAS_128_BYTE_Y_TILING(dev
))
2573 /* Note: pitch better be a power of two tile widths */
2574 pitch_val
= obj
->stride
/ tile_width
;
2575 pitch_val
= ffs(pitch_val
) - 1;
2577 val
= obj
->gtt_offset
;
2578 if (obj
->tiling_mode
== I915_TILING_Y
)
2579 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2580 val
|= I915_FENCE_SIZE_BITS(size
);
2581 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2582 val
|= I830_FENCE_REG_VALID
;
2587 reg
= FENCE_REG_830_0
+ reg
* 4;
2589 reg
= FENCE_REG_945_8
+ (reg
- 8) * 4;
2591 I915_WRITE(reg
, val
);
2595 static void i830_write_fence_reg(struct drm_device
*dev
, int reg
,
2596 struct drm_i915_gem_object
*obj
)
2598 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2602 u32 size
= obj
->gtt_space
->size
;
2605 WARN((obj
->gtt_offset
& ~I830_FENCE_START_MASK
) ||
2606 (size
& -size
) != size
||
2607 (obj
->gtt_offset
& (size
- 1)),
2608 "object 0x%08x not 512K or pot-size 0x%08x aligned\n",
2609 obj
->gtt_offset
, size
);
2611 pitch_val
= obj
->stride
/ 128;
2612 pitch_val
= ffs(pitch_val
) - 1;
2614 val
= obj
->gtt_offset
;
2615 if (obj
->tiling_mode
== I915_TILING_Y
)
2616 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2617 val
|= I830_FENCE_SIZE_BITS(size
);
2618 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2619 val
|= I830_FENCE_REG_VALID
;
2623 I915_WRITE(FENCE_REG_830_0
+ reg
* 4, val
);
2624 POSTING_READ(FENCE_REG_830_0
+ reg
* 4);
2627 static void i915_gem_write_fence(struct drm_device
*dev
, int reg
,
2628 struct drm_i915_gem_object
*obj
)
2630 switch (INTEL_INFO(dev
)->gen
) {
2634 case 4: i965_write_fence_reg(dev
, reg
, obj
); break;
2635 case 3: i915_write_fence_reg(dev
, reg
, obj
); break;
2636 case 2: i830_write_fence_reg(dev
, reg
, obj
); break;
2641 static inline int fence_number(struct drm_i915_private
*dev_priv
,
2642 struct drm_i915_fence_reg
*fence
)
2644 return fence
- dev_priv
->fence_regs
;
2647 static void i915_gem_object_update_fence(struct drm_i915_gem_object
*obj
,
2648 struct drm_i915_fence_reg
*fence
,
2651 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2652 int reg
= fence_number(dev_priv
, fence
);
2654 i915_gem_write_fence(obj
->base
.dev
, reg
, enable
? obj
: NULL
);
2657 obj
->fence_reg
= reg
;
2659 list_move_tail(&fence
->lru_list
, &dev_priv
->mm
.fence_list
);
2661 obj
->fence_reg
= I915_FENCE_REG_NONE
;
2663 list_del_init(&fence
->lru_list
);
2668 i915_gem_object_flush_fence(struct drm_i915_gem_object
*obj
)
2670 if (obj
->last_fenced_seqno
) {
2671 int ret
= i915_wait_seqno(obj
->ring
, obj
->last_fenced_seqno
);
2675 obj
->last_fenced_seqno
= 0;
2678 /* Ensure that all CPU reads are completed before installing a fence
2679 * and all writes before removing the fence.
2681 if (obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
)
2684 obj
->fenced_gpu_access
= false;
2689 i915_gem_object_put_fence(struct drm_i915_gem_object
*obj
)
2691 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2694 ret
= i915_gem_object_flush_fence(obj
);
2698 if (obj
->fence_reg
== I915_FENCE_REG_NONE
)
2701 i915_gem_object_update_fence(obj
,
2702 &dev_priv
->fence_regs
[obj
->fence_reg
],
2704 i915_gem_object_fence_lost(obj
);
2709 static struct drm_i915_fence_reg
*
2710 i915_find_fence_reg(struct drm_device
*dev
)
2712 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2713 struct drm_i915_fence_reg
*reg
, *avail
;
2716 /* First try to find a free reg */
2718 for (i
= dev_priv
->fence_reg_start
; i
< dev_priv
->num_fence_regs
; i
++) {
2719 reg
= &dev_priv
->fence_regs
[i
];
2723 if (!reg
->pin_count
)
2730 /* None available, try to steal one or wait for a user to finish */
2731 list_for_each_entry(reg
, &dev_priv
->mm
.fence_list
, lru_list
) {
2742 * i915_gem_object_get_fence - set up fencing for an object
2743 * @obj: object to map through a fence reg
2745 * When mapping objects through the GTT, userspace wants to be able to write
2746 * to them without having to worry about swizzling if the object is tiled.
2747 * This function walks the fence regs looking for a free one for @obj,
2748 * stealing one if it can't find any.
2750 * It then sets up the reg based on the object's properties: address, pitch
2751 * and tiling format.
2753 * For an untiled surface, this removes any existing fence.
2756 i915_gem_object_get_fence(struct drm_i915_gem_object
*obj
)
2758 struct drm_device
*dev
= obj
->base
.dev
;
2759 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2760 bool enable
= obj
->tiling_mode
!= I915_TILING_NONE
;
2761 struct drm_i915_fence_reg
*reg
;
2764 /* Have we updated the tiling parameters upon the object and so
2765 * will need to serialise the write to the associated fence register?
2767 if (obj
->fence_dirty
) {
2768 ret
= i915_gem_object_flush_fence(obj
);
2773 /* Just update our place in the LRU if our fence is getting reused. */
2774 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
2775 reg
= &dev_priv
->fence_regs
[obj
->fence_reg
];
2776 if (!obj
->fence_dirty
) {
2777 list_move_tail(®
->lru_list
,
2778 &dev_priv
->mm
.fence_list
);
2781 } else if (enable
) {
2782 reg
= i915_find_fence_reg(dev
);
2787 struct drm_i915_gem_object
*old
= reg
->obj
;
2789 ret
= i915_gem_object_flush_fence(old
);
2793 i915_gem_object_fence_lost(old
);
2798 i915_gem_object_update_fence(obj
, reg
, enable
);
2799 obj
->fence_dirty
= false;
2804 static bool i915_gem_valid_gtt_space(struct drm_device
*dev
,
2805 struct drm_mm_node
*gtt_space
,
2806 unsigned long cache_level
)
2808 struct drm_mm_node
*other
;
2810 /* On non-LLC machines we have to be careful when putting differing
2811 * types of snoopable memory together to avoid the prefetcher
2812 * crossing memory domains and dying.
2817 if (gtt_space
== NULL
)
2820 if (list_empty(>t_space
->node_list
))
2823 other
= list_entry(gtt_space
->node_list
.prev
, struct drm_mm_node
, node_list
);
2824 if (other
->allocated
&& !other
->hole_follows
&& other
->color
!= cache_level
)
2827 other
= list_entry(gtt_space
->node_list
.next
, struct drm_mm_node
, node_list
);
2828 if (other
->allocated
&& !gtt_space
->hole_follows
&& other
->color
!= cache_level
)
2834 static void i915_gem_verify_gtt(struct drm_device
*dev
)
2837 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2838 struct drm_i915_gem_object
*obj
;
2841 list_for_each_entry(obj
, &dev_priv
->mm
.gtt_list
, gtt_list
) {
2842 if (obj
->gtt_space
== NULL
) {
2843 printk(KERN_ERR
"object found on GTT list with no space reserved\n");
2848 if (obj
->cache_level
!= obj
->gtt_space
->color
) {
2849 printk(KERN_ERR
"object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n",
2850 obj
->gtt_space
->start
,
2851 obj
->gtt_space
->start
+ obj
->gtt_space
->size
,
2853 obj
->gtt_space
->color
);
2858 if (!i915_gem_valid_gtt_space(dev
,
2860 obj
->cache_level
)) {
2861 printk(KERN_ERR
"invalid GTT space found at [%08lx, %08lx] - color=%x\n",
2862 obj
->gtt_space
->start
,
2863 obj
->gtt_space
->start
+ obj
->gtt_space
->size
,
2875 * Finds free space in the GTT aperture and binds the object there.
2878 i915_gem_object_bind_to_gtt(struct drm_i915_gem_object
*obj
,
2880 bool map_and_fenceable
,
2883 struct drm_device
*dev
= obj
->base
.dev
;
2884 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2885 struct drm_mm_node
*node
;
2886 u32 size
, fence_size
, fence_alignment
, unfenced_alignment
;
2887 bool mappable
, fenceable
;
2890 fence_size
= i915_gem_get_gtt_size(dev
,
2893 fence_alignment
= i915_gem_get_gtt_alignment(dev
,
2895 obj
->tiling_mode
, true);
2896 unfenced_alignment
=
2897 i915_gem_get_gtt_alignment(dev
,
2899 obj
->tiling_mode
, false);
2902 alignment
= map_and_fenceable
? fence_alignment
:
2904 if (map_and_fenceable
&& alignment
& (fence_alignment
- 1)) {
2905 DRM_ERROR("Invalid object alignment requested %u\n", alignment
);
2909 size
= map_and_fenceable
? fence_size
: obj
->base
.size
;
2911 /* If the object is bigger than the entire aperture, reject it early
2912 * before evicting everything in a vain attempt to find space.
2914 if (obj
->base
.size
>
2915 (map_and_fenceable
? dev_priv
->gtt
.mappable_end
: dev_priv
->gtt
.total
)) {
2916 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2920 ret
= i915_gem_object_get_pages(obj
);
2924 i915_gem_object_pin_pages(obj
);
2926 node
= kzalloc(sizeof(*node
), GFP_KERNEL
);
2928 i915_gem_object_unpin_pages(obj
);
2933 if (map_and_fenceable
)
2934 ret
= drm_mm_insert_node_in_range_generic(&dev_priv
->mm
.gtt_space
, node
,
2935 size
, alignment
, obj
->cache_level
,
2936 0, dev_priv
->gtt
.mappable_end
);
2938 ret
= drm_mm_insert_node_generic(&dev_priv
->mm
.gtt_space
, node
,
2939 size
, alignment
, obj
->cache_level
);
2941 ret
= i915_gem_evict_something(dev
, size
, alignment
,
2948 i915_gem_object_unpin_pages(obj
);
2952 if (WARN_ON(!i915_gem_valid_gtt_space(dev
, node
, obj
->cache_level
))) {
2953 i915_gem_object_unpin_pages(obj
);
2954 drm_mm_put_block(node
);
2958 ret
= i915_gem_gtt_prepare_object(obj
);
2960 i915_gem_object_unpin_pages(obj
);
2961 drm_mm_put_block(node
);
2965 list_move_tail(&obj
->gtt_list
, &dev_priv
->mm
.bound_list
);
2966 list_add_tail(&obj
->mm_list
, &dev_priv
->mm
.inactive_list
);
2968 obj
->gtt_space
= node
;
2969 obj
->gtt_offset
= node
->start
;
2972 node
->size
== fence_size
&&
2973 (node
->start
& (fence_alignment
- 1)) == 0;
2976 obj
->gtt_offset
+ obj
->base
.size
<= dev_priv
->gtt
.mappable_end
;
2978 obj
->map_and_fenceable
= mappable
&& fenceable
;
2980 i915_gem_object_unpin_pages(obj
);
2981 trace_i915_gem_object_bind(obj
, map_and_fenceable
);
2982 i915_gem_verify_gtt(dev
);
2987 i915_gem_clflush_object(struct drm_i915_gem_object
*obj
)
2989 /* If we don't have a page list set up, then we're not pinned
2990 * to GPU, and we can ignore the cache flush because it'll happen
2991 * again at bind time.
2993 if (obj
->pages
== NULL
)
2996 /* If the GPU is snooping the contents of the CPU cache,
2997 * we do not need to manually clear the CPU cache lines. However,
2998 * the caches are only snooped when the render cache is
2999 * flushed/invalidated. As we always have to emit invalidations
3000 * and flushes when moving into and out of the RENDER domain, correct
3001 * snooping behaviour occurs naturally as the result of our domain
3004 if (obj
->cache_level
!= I915_CACHE_NONE
)
3007 trace_i915_gem_object_clflush(obj
);
3009 drm_clflush_sg(obj
->pages
);
3012 /** Flushes the GTT write domain for the object if it's dirty. */
3014 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
)
3016 uint32_t old_write_domain
;
3018 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_GTT
)
3021 /* No actual flushing is required for the GTT write domain. Writes
3022 * to it immediately go to main memory as far as we know, so there's
3023 * no chipset flush. It also doesn't land in render cache.
3025 * However, we do have to enforce the order so that all writes through
3026 * the GTT land before any writes to the device, such as updates to
3031 old_write_domain
= obj
->base
.write_domain
;
3032 obj
->base
.write_domain
= 0;
3034 trace_i915_gem_object_change_domain(obj
,
3035 obj
->base
.read_domains
,
3039 /** Flushes the CPU write domain for the object if it's dirty. */
3041 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
)
3043 uint32_t old_write_domain
;
3045 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
)
3048 i915_gem_clflush_object(obj
);
3049 i915_gem_chipset_flush(obj
->base
.dev
);
3050 old_write_domain
= obj
->base
.write_domain
;
3051 obj
->base
.write_domain
= 0;
3053 trace_i915_gem_object_change_domain(obj
,
3054 obj
->base
.read_domains
,
3059 * Moves a single object to the GTT read, and possibly write domain.
3061 * This function returns when the move is complete, including waiting on
3065 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
, bool write
)
3067 drm_i915_private_t
*dev_priv
= obj
->base
.dev
->dev_private
;
3068 uint32_t old_write_domain
, old_read_domains
;
3071 /* Not valid to be called on unbound objects. */
3072 if (obj
->gtt_space
== NULL
)
3075 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_GTT
)
3078 ret
= i915_gem_object_wait_rendering(obj
, !write
);
3082 i915_gem_object_flush_cpu_write_domain(obj
);
3084 old_write_domain
= obj
->base
.write_domain
;
3085 old_read_domains
= obj
->base
.read_domains
;
3087 /* It should now be out of any other write domains, and we can update
3088 * the domain values for our changes.
3090 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
3091 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
3093 obj
->base
.read_domains
= I915_GEM_DOMAIN_GTT
;
3094 obj
->base
.write_domain
= I915_GEM_DOMAIN_GTT
;
3098 trace_i915_gem_object_change_domain(obj
,
3102 /* And bump the LRU for this access */
3103 if (i915_gem_object_is_inactive(obj
))
3104 list_move_tail(&obj
->mm_list
, &dev_priv
->mm
.inactive_list
);
3109 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
3110 enum i915_cache_level cache_level
)
3112 struct drm_device
*dev
= obj
->base
.dev
;
3113 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3116 if (obj
->cache_level
== cache_level
)
3119 if (obj
->pin_count
) {
3120 DRM_DEBUG("can not change the cache level of pinned objects\n");
3124 if (!i915_gem_valid_gtt_space(dev
, obj
->gtt_space
, cache_level
)) {
3125 ret
= i915_gem_object_unbind(obj
);
3130 if (obj
->gtt_space
) {
3131 ret
= i915_gem_object_finish_gpu(obj
);
3135 i915_gem_object_finish_gtt(obj
);
3137 /* Before SandyBridge, you could not use tiling or fence
3138 * registers with snooped memory, so relinquish any fences
3139 * currently pointing to our region in the aperture.
3141 if (INTEL_INFO(dev
)->gen
< 6) {
3142 ret
= i915_gem_object_put_fence(obj
);
3147 if (obj
->has_global_gtt_mapping
)
3148 i915_gem_gtt_bind_object(obj
, cache_level
);
3149 if (obj
->has_aliasing_ppgtt_mapping
)
3150 i915_ppgtt_bind_object(dev_priv
->mm
.aliasing_ppgtt
,
3153 obj
->gtt_space
->color
= cache_level
;
3156 if (cache_level
== I915_CACHE_NONE
) {
3157 u32 old_read_domains
, old_write_domain
;
3159 /* If we're coming from LLC cached, then we haven't
3160 * actually been tracking whether the data is in the
3161 * CPU cache or not, since we only allow one bit set
3162 * in obj->write_domain and have been skipping the clflushes.
3163 * Just set it to the CPU cache for now.
3165 WARN_ON(obj
->base
.write_domain
& ~I915_GEM_DOMAIN_CPU
);
3166 WARN_ON(obj
->base
.read_domains
& ~I915_GEM_DOMAIN_CPU
);
3168 old_read_domains
= obj
->base
.read_domains
;
3169 old_write_domain
= obj
->base
.write_domain
;
3171 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
3172 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
3174 trace_i915_gem_object_change_domain(obj
,
3179 obj
->cache_level
= cache_level
;
3180 i915_gem_verify_gtt(dev
);
3184 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
3185 struct drm_file
*file
)
3187 struct drm_i915_gem_caching
*args
= data
;
3188 struct drm_i915_gem_object
*obj
;
3191 ret
= i915_mutex_lock_interruptible(dev
);
3195 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3196 if (&obj
->base
== NULL
) {
3201 args
->caching
= obj
->cache_level
!= I915_CACHE_NONE
;
3203 drm_gem_object_unreference(&obj
->base
);
3205 mutex_unlock(&dev
->struct_mutex
);
3209 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
3210 struct drm_file
*file
)
3212 struct drm_i915_gem_caching
*args
= data
;
3213 struct drm_i915_gem_object
*obj
;
3214 enum i915_cache_level level
;
3217 switch (args
->caching
) {
3218 case I915_CACHING_NONE
:
3219 level
= I915_CACHE_NONE
;
3221 case I915_CACHING_CACHED
:
3222 level
= I915_CACHE_LLC
;
3228 ret
= i915_mutex_lock_interruptible(dev
);
3232 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3233 if (&obj
->base
== NULL
) {
3238 ret
= i915_gem_object_set_cache_level(obj
, level
);
3240 drm_gem_object_unreference(&obj
->base
);
3242 mutex_unlock(&dev
->struct_mutex
);
3247 * Prepare buffer for display plane (scanout, cursors, etc).
3248 * Can be called from an uninterruptible phase (modesetting) and allows
3249 * any flushes to be pipelined (for pageflips).
3252 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
3254 struct intel_ring_buffer
*pipelined
)
3256 u32 old_read_domains
, old_write_domain
;
3259 if (pipelined
!= obj
->ring
) {
3260 ret
= i915_gem_object_sync(obj
, pipelined
);
3265 /* The display engine is not coherent with the LLC cache on gen6. As
3266 * a result, we make sure that the pinning that is about to occur is
3267 * done with uncached PTEs. This is lowest common denominator for all
3270 * However for gen6+, we could do better by using the GFDT bit instead
3271 * of uncaching, which would allow us to flush all the LLC-cached data
3272 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3274 ret
= i915_gem_object_set_cache_level(obj
, I915_CACHE_NONE
);
3278 /* As the user may map the buffer once pinned in the display plane
3279 * (e.g. libkms for the bootup splash), we have to ensure that we
3280 * always use map_and_fenceable for all scanout buffers.
3282 ret
= i915_gem_object_pin(obj
, alignment
, true, false);
3286 i915_gem_object_flush_cpu_write_domain(obj
);
3288 old_write_domain
= obj
->base
.write_domain
;
3289 old_read_domains
= obj
->base
.read_domains
;
3291 /* It should now be out of any other write domains, and we can update
3292 * the domain values for our changes.
3294 obj
->base
.write_domain
= 0;
3295 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
3297 trace_i915_gem_object_change_domain(obj
,
3305 i915_gem_object_finish_gpu(struct drm_i915_gem_object
*obj
)
3309 if ((obj
->base
.read_domains
& I915_GEM_GPU_DOMAINS
) == 0)
3312 ret
= i915_gem_object_wait_rendering(obj
, false);
3316 /* Ensure that we invalidate the GPU's caches and TLBs. */
3317 obj
->base
.read_domains
&= ~I915_GEM_GPU_DOMAINS
;
3322 * Moves a single object to the CPU read, and possibly write domain.
3324 * This function returns when the move is complete, including waiting on
3328 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
)
3330 uint32_t old_write_domain
, old_read_domains
;
3333 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_CPU
)
3336 ret
= i915_gem_object_wait_rendering(obj
, !write
);
3340 i915_gem_object_flush_gtt_write_domain(obj
);
3342 old_write_domain
= obj
->base
.write_domain
;
3343 old_read_domains
= obj
->base
.read_domains
;
3345 /* Flush the CPU cache if it's still invalid. */
3346 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) == 0) {
3347 i915_gem_clflush_object(obj
);
3349 obj
->base
.read_domains
|= I915_GEM_DOMAIN_CPU
;
3352 /* It should now be out of any other write domains, and we can update
3353 * the domain values for our changes.
3355 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
3357 /* If we're writing through the CPU, then the GPU read domains will
3358 * need to be invalidated at next use.
3361 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
3362 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
3365 trace_i915_gem_object_change_domain(obj
,
3372 /* Throttle our rendering by waiting until the ring has completed our requests
3373 * emitted over 20 msec ago.
3375 * Note that if we were to use the current jiffies each time around the loop,
3376 * we wouldn't escape the function with any frames outstanding if the time to
3377 * render a frame was over 20ms.
3379 * This should get us reasonable parallelism between CPU and GPU but also
3380 * relatively low latency when blocking on a particular request to finish.
3383 i915_gem_ring_throttle(struct drm_device
*dev
, struct drm_file
*file
)
3385 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3386 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
3387 unsigned long recent_enough
= jiffies
- msecs_to_jiffies(20);
3388 struct drm_i915_gem_request
*request
;
3389 struct intel_ring_buffer
*ring
= NULL
;
3393 if (atomic_read(&dev_priv
->mm
.wedged
))
3396 spin_lock(&file_priv
->mm
.lock
);
3397 list_for_each_entry(request
, &file_priv
->mm
.request_list
, client_list
) {
3398 if (time_after_eq(request
->emitted_jiffies
, recent_enough
))
3401 ring
= request
->ring
;
3402 seqno
= request
->seqno
;
3404 spin_unlock(&file_priv
->mm
.lock
);
3409 ret
= __wait_seqno(ring
, seqno
, true, NULL
);
3411 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, 0);
3417 i915_gem_object_pin(struct drm_i915_gem_object
*obj
,
3419 bool map_and_fenceable
,
3424 if (WARN_ON(obj
->pin_count
== DRM_I915_GEM_OBJECT_MAX_PIN_COUNT
))
3427 if (obj
->gtt_space
!= NULL
) {
3428 if ((alignment
&& obj
->gtt_offset
& (alignment
- 1)) ||
3429 (map_and_fenceable
&& !obj
->map_and_fenceable
)) {
3430 WARN(obj
->pin_count
,
3431 "bo is already pinned with incorrect alignment:"
3432 " offset=%x, req.alignment=%x, req.map_and_fenceable=%d,"
3433 " obj->map_and_fenceable=%d\n",
3434 obj
->gtt_offset
, alignment
,
3436 obj
->map_and_fenceable
);
3437 ret
= i915_gem_object_unbind(obj
);
3443 if (obj
->gtt_space
== NULL
) {
3444 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
3446 ret
= i915_gem_object_bind_to_gtt(obj
, alignment
,
3452 if (!dev_priv
->mm
.aliasing_ppgtt
)
3453 i915_gem_gtt_bind_object(obj
, obj
->cache_level
);
3456 if (!obj
->has_global_gtt_mapping
&& map_and_fenceable
)
3457 i915_gem_gtt_bind_object(obj
, obj
->cache_level
);
3460 obj
->pin_mappable
|= map_and_fenceable
;
3466 i915_gem_object_unpin(struct drm_i915_gem_object
*obj
)
3468 BUG_ON(obj
->pin_count
== 0);
3469 BUG_ON(obj
->gtt_space
== NULL
);
3471 if (--obj
->pin_count
== 0)
3472 obj
->pin_mappable
= false;
3476 i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
3477 struct drm_file
*file
)
3479 struct drm_i915_gem_pin
*args
= data
;
3480 struct drm_i915_gem_object
*obj
;
3483 ret
= i915_mutex_lock_interruptible(dev
);
3487 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3488 if (&obj
->base
== NULL
) {
3493 if (obj
->madv
!= I915_MADV_WILLNEED
) {
3494 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3499 if (obj
->pin_filp
!= NULL
&& obj
->pin_filp
!= file
) {
3500 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3506 obj
->user_pin_count
++;
3507 obj
->pin_filp
= file
;
3508 if (obj
->user_pin_count
== 1) {
3509 ret
= i915_gem_object_pin(obj
, args
->alignment
, true, false);
3514 /* XXX - flush the CPU caches for pinned objects
3515 * as the X server doesn't manage domains yet
3517 i915_gem_object_flush_cpu_write_domain(obj
);
3518 args
->offset
= obj
->gtt_offset
;
3520 drm_gem_object_unreference(&obj
->base
);
3522 mutex_unlock(&dev
->struct_mutex
);
3527 i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
3528 struct drm_file
*file
)
3530 struct drm_i915_gem_pin
*args
= data
;
3531 struct drm_i915_gem_object
*obj
;
3534 ret
= i915_mutex_lock_interruptible(dev
);
3538 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3539 if (&obj
->base
== NULL
) {
3544 if (obj
->pin_filp
!= file
) {
3545 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3550 obj
->user_pin_count
--;
3551 if (obj
->user_pin_count
== 0) {
3552 obj
->pin_filp
= NULL
;
3553 i915_gem_object_unpin(obj
);
3557 drm_gem_object_unreference(&obj
->base
);
3559 mutex_unlock(&dev
->struct_mutex
);
3564 i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
3565 struct drm_file
*file
)
3567 struct drm_i915_gem_busy
*args
= data
;
3568 struct drm_i915_gem_object
*obj
;
3571 ret
= i915_mutex_lock_interruptible(dev
);
3575 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3576 if (&obj
->base
== NULL
) {
3581 /* Count all active objects as busy, even if they are currently not used
3582 * by the gpu. Users of this interface expect objects to eventually
3583 * become non-busy without any further actions, therefore emit any
3584 * necessary flushes here.
3586 ret
= i915_gem_object_flush_active(obj
);
3588 args
->busy
= obj
->active
;
3590 BUILD_BUG_ON(I915_NUM_RINGS
> 16);
3591 args
->busy
|= intel_ring_flag(obj
->ring
) << 16;
3594 drm_gem_object_unreference(&obj
->base
);
3596 mutex_unlock(&dev
->struct_mutex
);
3601 i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
3602 struct drm_file
*file_priv
)
3604 return i915_gem_ring_throttle(dev
, file_priv
);
3608 i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
3609 struct drm_file
*file_priv
)
3611 struct drm_i915_gem_madvise
*args
= data
;
3612 struct drm_i915_gem_object
*obj
;
3615 switch (args
->madv
) {
3616 case I915_MADV_DONTNEED
:
3617 case I915_MADV_WILLNEED
:
3623 ret
= i915_mutex_lock_interruptible(dev
);
3627 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file_priv
, args
->handle
));
3628 if (&obj
->base
== NULL
) {
3633 if (obj
->pin_count
) {
3638 if (obj
->madv
!= __I915_MADV_PURGED
)
3639 obj
->madv
= args
->madv
;
3641 /* if the object is no longer attached, discard its backing storage */
3642 if (i915_gem_object_is_purgeable(obj
) && obj
->pages
== NULL
)
3643 i915_gem_object_truncate(obj
);
3645 args
->retained
= obj
->madv
!= __I915_MADV_PURGED
;
3648 drm_gem_object_unreference(&obj
->base
);
3650 mutex_unlock(&dev
->struct_mutex
);
3654 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
3655 const struct drm_i915_gem_object_ops
*ops
)
3657 INIT_LIST_HEAD(&obj
->mm_list
);
3658 INIT_LIST_HEAD(&obj
->gtt_list
);
3659 INIT_LIST_HEAD(&obj
->ring_list
);
3660 INIT_LIST_HEAD(&obj
->exec_list
);
3664 obj
->fence_reg
= I915_FENCE_REG_NONE
;
3665 obj
->madv
= I915_MADV_WILLNEED
;
3666 /* Avoid an unnecessary call to unbind on the first bind. */
3667 obj
->map_and_fenceable
= true;
3669 i915_gem_info_add_obj(obj
->base
.dev
->dev_private
, obj
->base
.size
);
3672 static const struct drm_i915_gem_object_ops i915_gem_object_ops
= {
3673 .get_pages
= i915_gem_object_get_pages_gtt
,
3674 .put_pages
= i915_gem_object_put_pages_gtt
,
3677 struct drm_i915_gem_object
*i915_gem_alloc_object(struct drm_device
*dev
,
3680 struct drm_i915_gem_object
*obj
;
3681 struct address_space
*mapping
;
3684 obj
= i915_gem_object_alloc(dev
);
3688 if (drm_gem_object_init(dev
, &obj
->base
, size
) != 0) {
3689 i915_gem_object_free(obj
);
3693 mask
= GFP_HIGHUSER
| __GFP_RECLAIMABLE
;
3694 if (IS_CRESTLINE(dev
) || IS_BROADWATER(dev
)) {
3695 /* 965gm cannot relocate objects above 4GiB. */
3696 mask
&= ~__GFP_HIGHMEM
;
3697 mask
|= __GFP_DMA32
;
3700 mapping
= obj
->base
.filp
->f_path
.dentry
->d_inode
->i_mapping
;
3701 mapping_set_gfp_mask(mapping
, mask
);
3703 i915_gem_object_init(obj
, &i915_gem_object_ops
);
3705 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
3706 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
3709 /* On some devices, we can have the GPU use the LLC (the CPU
3710 * cache) for about a 10% performance improvement
3711 * compared to uncached. Graphics requests other than
3712 * display scanout are coherent with the CPU in
3713 * accessing this cache. This means in this mode we
3714 * don't need to clflush on the CPU side, and on the
3715 * GPU side we only need to flush internal caches to
3716 * get data visible to the CPU.
3718 * However, we maintain the display planes as UC, and so
3719 * need to rebind when first used as such.
3721 obj
->cache_level
= I915_CACHE_LLC
;
3723 obj
->cache_level
= I915_CACHE_NONE
;
3728 int i915_gem_init_object(struct drm_gem_object
*obj
)
3735 void i915_gem_free_object(struct drm_gem_object
*gem_obj
)
3737 struct drm_i915_gem_object
*obj
= to_intel_bo(gem_obj
);
3738 struct drm_device
*dev
= obj
->base
.dev
;
3739 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3741 trace_i915_gem_object_destroy(obj
);
3744 i915_gem_detach_phys_object(dev
, obj
);
3747 if (WARN_ON(i915_gem_object_unbind(obj
) == -ERESTARTSYS
)) {
3748 bool was_interruptible
;
3750 was_interruptible
= dev_priv
->mm
.interruptible
;
3751 dev_priv
->mm
.interruptible
= false;
3753 WARN_ON(i915_gem_object_unbind(obj
));
3755 dev_priv
->mm
.interruptible
= was_interruptible
;
3758 obj
->pages_pin_count
= 0;
3759 i915_gem_object_put_pages(obj
);
3760 i915_gem_object_free_mmap_offset(obj
);
3761 i915_gem_object_release_stolen(obj
);
3765 if (obj
->base
.import_attach
)
3766 drm_prime_gem_destroy(&obj
->base
, NULL
);
3768 drm_gem_object_release(&obj
->base
);
3769 i915_gem_info_remove_obj(dev_priv
, obj
->base
.size
);
3772 i915_gem_object_free(obj
);
3776 i915_gem_idle(struct drm_device
*dev
)
3778 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3781 mutex_lock(&dev
->struct_mutex
);
3783 if (dev_priv
->mm
.suspended
) {
3784 mutex_unlock(&dev
->struct_mutex
);
3788 ret
= i915_gpu_idle(dev
);
3790 mutex_unlock(&dev
->struct_mutex
);
3793 i915_gem_retire_requests(dev
);
3795 /* Under UMS, be paranoid and evict. */
3796 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
3797 i915_gem_evict_everything(dev
);
3799 i915_gem_reset_fences(dev
);
3801 /* Hack! Don't let anybody do execbuf while we don't control the chip.
3802 * We need to replace this with a semaphore, or something.
3803 * And not confound mm.suspended!
3805 dev_priv
->mm
.suspended
= 1;
3806 del_timer_sync(&dev_priv
->gpu_error
.hangcheck_timer
);
3808 i915_kernel_lost_context(dev
);
3809 i915_gem_cleanup_ringbuffer(dev
);
3811 mutex_unlock(&dev
->struct_mutex
);
3813 /* Cancel the retire work handler, which should be idle now. */
3814 cancel_delayed_work_sync(&dev_priv
->mm
.retire_work
);
3819 void i915_gem_l3_remap(struct drm_device
*dev
)
3821 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3825 if (!IS_IVYBRIDGE(dev
))
3828 if (!dev_priv
->l3_parity
.remap_info
)
3831 misccpctl
= I915_READ(GEN7_MISCCPCTL
);
3832 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
& ~GEN7_DOP_CLOCK_GATE_ENABLE
);
3833 POSTING_READ(GEN7_MISCCPCTL
);
3835 for (i
= 0; i
< GEN7_L3LOG_SIZE
; i
+= 4) {
3836 u32 remap
= I915_READ(GEN7_L3LOG_BASE
+ i
);
3837 if (remap
&& remap
!= dev_priv
->l3_parity
.remap_info
[i
/4])
3838 DRM_DEBUG("0x%x was already programmed to %x\n",
3839 GEN7_L3LOG_BASE
+ i
, remap
);
3840 if (remap
&& !dev_priv
->l3_parity
.remap_info
[i
/4])
3841 DRM_DEBUG_DRIVER("Clearing remapped register\n");
3842 I915_WRITE(GEN7_L3LOG_BASE
+ i
, dev_priv
->l3_parity
.remap_info
[i
/4]);
3845 /* Make sure all the writes land before disabling dop clock gating */
3846 POSTING_READ(GEN7_L3LOG_BASE
);
3848 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
);
3851 void i915_gem_init_swizzling(struct drm_device
*dev
)
3853 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3855 if (INTEL_INFO(dev
)->gen
< 5 ||
3856 dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_NONE
)
3859 I915_WRITE(DISP_ARB_CTL
, I915_READ(DISP_ARB_CTL
) |
3860 DISP_TILE_SURFACE_SWIZZLING
);
3865 I915_WRITE(TILECTL
, I915_READ(TILECTL
) | TILECTL_SWZCTL
);
3867 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB
));
3868 else if (IS_GEN7(dev
))
3869 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB
));
3875 intel_enable_blt(struct drm_device
*dev
)
3880 /* The blitter was dysfunctional on early prototypes */
3881 if (IS_GEN6(dev
) && dev
->pdev
->revision
< 8) {
3882 DRM_INFO("BLT not supported on this pre-production hardware;"
3883 " graphics performance will be degraded.\n");
3891 i915_gem_init_hw(struct drm_device
*dev
)
3893 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3896 if (INTEL_INFO(dev
)->gen
< 6 && !intel_enable_gtt())
3899 if (IS_HASWELL(dev
) && (I915_READ(0x120010) == 1))
3900 I915_WRITE(0x9008, I915_READ(0x9008) | 0xf0000);
3902 i915_gem_l3_remap(dev
);
3904 i915_gem_init_swizzling(dev
);
3906 dev_priv
->next_seqno
= dev_priv
->last_seqno
= (u32
)~0 - 0x1000;
3908 ret
= intel_init_render_ring_buffer(dev
);
3913 ret
= intel_init_bsd_ring_buffer(dev
);
3915 goto cleanup_render_ring
;
3918 if (intel_enable_blt(dev
)) {
3919 ret
= intel_init_blt_ring_buffer(dev
);
3921 goto cleanup_bsd_ring
;
3925 * XXX: There was some w/a described somewhere suggesting loading
3926 * contexts before PPGTT.
3928 i915_gem_context_init(dev
);
3929 i915_gem_init_ppgtt(dev
);
3934 intel_cleanup_ring_buffer(&dev_priv
->ring
[VCS
]);
3935 cleanup_render_ring
:
3936 intel_cleanup_ring_buffer(&dev_priv
->ring
[RCS
]);
3940 int i915_gem_init(struct drm_device
*dev
)
3942 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3945 mutex_lock(&dev
->struct_mutex
);
3946 i915_gem_init_global_gtt(dev
);
3947 ret
= i915_gem_init_hw(dev
);
3948 mutex_unlock(&dev
->struct_mutex
);
3950 i915_gem_cleanup_aliasing_ppgtt(dev
);
3954 /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */
3955 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
3956 dev_priv
->dri1
.allow_batchbuffer
= 1;
3961 i915_gem_cleanup_ringbuffer(struct drm_device
*dev
)
3963 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3964 struct intel_ring_buffer
*ring
;
3967 for_each_ring(ring
, dev_priv
, i
)
3968 intel_cleanup_ring_buffer(ring
);
3972 i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
3973 struct drm_file
*file_priv
)
3975 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3978 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
3981 if (atomic_read(&dev_priv
->mm
.wedged
)) {
3982 DRM_ERROR("Reenabling wedged hardware, good luck\n");
3983 atomic_set(&dev_priv
->mm
.wedged
, 0);
3986 mutex_lock(&dev
->struct_mutex
);
3987 dev_priv
->mm
.suspended
= 0;
3989 ret
= i915_gem_init_hw(dev
);
3991 mutex_unlock(&dev
->struct_mutex
);
3995 BUG_ON(!list_empty(&dev_priv
->mm
.active_list
));
3996 mutex_unlock(&dev
->struct_mutex
);
3998 ret
= drm_irq_install(dev
);
4000 goto cleanup_ringbuffer
;
4005 mutex_lock(&dev
->struct_mutex
);
4006 i915_gem_cleanup_ringbuffer(dev
);
4007 dev_priv
->mm
.suspended
= 1;
4008 mutex_unlock(&dev
->struct_mutex
);
4014 i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
4015 struct drm_file
*file_priv
)
4017 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4020 drm_irq_uninstall(dev
);
4021 return i915_gem_idle(dev
);
4025 i915_gem_lastclose(struct drm_device
*dev
)
4029 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4032 ret
= i915_gem_idle(dev
);
4034 DRM_ERROR("failed to idle hardware: %d\n", ret
);
4038 init_ring_lists(struct intel_ring_buffer
*ring
)
4040 INIT_LIST_HEAD(&ring
->active_list
);
4041 INIT_LIST_HEAD(&ring
->request_list
);
4045 i915_gem_load(struct drm_device
*dev
)
4047 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4051 kmem_cache_create("i915_gem_object",
4052 sizeof(struct drm_i915_gem_object
), 0,
4056 INIT_LIST_HEAD(&dev_priv
->mm
.active_list
);
4057 INIT_LIST_HEAD(&dev_priv
->mm
.inactive_list
);
4058 INIT_LIST_HEAD(&dev_priv
->mm
.unbound_list
);
4059 INIT_LIST_HEAD(&dev_priv
->mm
.bound_list
);
4060 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
4061 for (i
= 0; i
< I915_NUM_RINGS
; i
++)
4062 init_ring_lists(&dev_priv
->ring
[i
]);
4063 for (i
= 0; i
< I915_MAX_NUM_FENCES
; i
++)
4064 INIT_LIST_HEAD(&dev_priv
->fence_regs
[i
].lru_list
);
4065 INIT_DELAYED_WORK(&dev_priv
->mm
.retire_work
,
4066 i915_gem_retire_work_handler
);
4067 init_completion(&dev_priv
->gpu_error
.completion
);
4069 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4071 I915_WRITE(MI_ARB_STATE
,
4072 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE
));
4075 dev_priv
->relative_constants_mode
= I915_EXEC_CONSTANTS_REL_GENERAL
;
4077 /* Old X drivers will take 0-2 for front, back, depth buffers */
4078 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
4079 dev_priv
->fence_reg_start
= 3;
4081 if (INTEL_INFO(dev
)->gen
>= 4 || IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
4082 dev_priv
->num_fence_regs
= 16;
4084 dev_priv
->num_fence_regs
= 8;
4086 /* Initialize fence registers to zero */
4087 i915_gem_reset_fences(dev
);
4089 i915_gem_detect_bit_6_swizzle(dev
);
4090 init_waitqueue_head(&dev_priv
->pending_flip_queue
);
4092 dev_priv
->mm
.interruptible
= true;
4094 dev_priv
->mm
.inactive_shrinker
.shrink
= i915_gem_inactive_shrink
;
4095 dev_priv
->mm
.inactive_shrinker
.seeks
= DEFAULT_SEEKS
;
4096 register_shrinker(&dev_priv
->mm
.inactive_shrinker
);
4100 * Create a physically contiguous memory object for this object
4101 * e.g. for cursor + overlay regs
4103 static int i915_gem_init_phys_object(struct drm_device
*dev
,
4104 int id
, int size
, int align
)
4106 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4107 struct drm_i915_gem_phys_object
*phys_obj
;
4110 if (dev_priv
->mm
.phys_objs
[id
- 1] || !size
)
4113 phys_obj
= kzalloc(sizeof(struct drm_i915_gem_phys_object
), GFP_KERNEL
);
4119 phys_obj
->handle
= drm_pci_alloc(dev
, size
, align
);
4120 if (!phys_obj
->handle
) {
4125 set_memory_wc((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
4128 dev_priv
->mm
.phys_objs
[id
- 1] = phys_obj
;
4136 static void i915_gem_free_phys_object(struct drm_device
*dev
, int id
)
4138 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4139 struct drm_i915_gem_phys_object
*phys_obj
;
4141 if (!dev_priv
->mm
.phys_objs
[id
- 1])
4144 phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
4145 if (phys_obj
->cur_obj
) {
4146 i915_gem_detach_phys_object(dev
, phys_obj
->cur_obj
);
4150 set_memory_wb((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
4152 drm_pci_free(dev
, phys_obj
->handle
);
4154 dev_priv
->mm
.phys_objs
[id
- 1] = NULL
;
4157 void i915_gem_free_all_phys_object(struct drm_device
*dev
)
4161 for (i
= I915_GEM_PHYS_CURSOR_0
; i
<= I915_MAX_PHYS_OBJECT
; i
++)
4162 i915_gem_free_phys_object(dev
, i
);
4165 void i915_gem_detach_phys_object(struct drm_device
*dev
,
4166 struct drm_i915_gem_object
*obj
)
4168 struct address_space
*mapping
= obj
->base
.filp
->f_path
.dentry
->d_inode
->i_mapping
;
4175 vaddr
= obj
->phys_obj
->handle
->vaddr
;
4177 page_count
= obj
->base
.size
/ PAGE_SIZE
;
4178 for (i
= 0; i
< page_count
; i
++) {
4179 struct page
*page
= shmem_read_mapping_page(mapping
, i
);
4180 if (!IS_ERR(page
)) {
4181 char *dst
= kmap_atomic(page
);
4182 memcpy(dst
, vaddr
+ i
*PAGE_SIZE
, PAGE_SIZE
);
4185 drm_clflush_pages(&page
, 1);
4187 set_page_dirty(page
);
4188 mark_page_accessed(page
);
4189 page_cache_release(page
);
4192 i915_gem_chipset_flush(dev
);
4194 obj
->phys_obj
->cur_obj
= NULL
;
4195 obj
->phys_obj
= NULL
;
4199 i915_gem_attach_phys_object(struct drm_device
*dev
,
4200 struct drm_i915_gem_object
*obj
,
4204 struct address_space
*mapping
= obj
->base
.filp
->f_path
.dentry
->d_inode
->i_mapping
;
4205 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4210 if (id
> I915_MAX_PHYS_OBJECT
)
4213 if (obj
->phys_obj
) {
4214 if (obj
->phys_obj
->id
== id
)
4216 i915_gem_detach_phys_object(dev
, obj
);
4219 /* create a new object */
4220 if (!dev_priv
->mm
.phys_objs
[id
- 1]) {
4221 ret
= i915_gem_init_phys_object(dev
, id
,
4222 obj
->base
.size
, align
);
4224 DRM_ERROR("failed to init phys object %d size: %zu\n",
4225 id
, obj
->base
.size
);
4230 /* bind to the object */
4231 obj
->phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
4232 obj
->phys_obj
->cur_obj
= obj
;
4234 page_count
= obj
->base
.size
/ PAGE_SIZE
;
4236 for (i
= 0; i
< page_count
; i
++) {
4240 page
= shmem_read_mapping_page(mapping
, i
);
4242 return PTR_ERR(page
);
4244 src
= kmap_atomic(page
);
4245 dst
= obj
->phys_obj
->handle
->vaddr
+ (i
* PAGE_SIZE
);
4246 memcpy(dst
, src
, PAGE_SIZE
);
4249 mark_page_accessed(page
);
4250 page_cache_release(page
);
4257 i915_gem_phys_pwrite(struct drm_device
*dev
,
4258 struct drm_i915_gem_object
*obj
,
4259 struct drm_i915_gem_pwrite
*args
,
4260 struct drm_file
*file_priv
)
4262 void *vaddr
= obj
->phys_obj
->handle
->vaddr
+ args
->offset
;
4263 char __user
*user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
4265 if (__copy_from_user_inatomic_nocache(vaddr
, user_data
, args
->size
)) {
4266 unsigned long unwritten
;
4268 /* The physical object once assigned is fixed for the lifetime
4269 * of the obj, so we can safely drop the lock and continue
4272 mutex_unlock(&dev
->struct_mutex
);
4273 unwritten
= copy_from_user(vaddr
, user_data
, args
->size
);
4274 mutex_lock(&dev
->struct_mutex
);
4279 i915_gem_chipset_flush(dev
);
4283 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
)
4285 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
4287 /* Clean up our request list when the client is going away, so that
4288 * later retire_requests won't dereference our soon-to-be-gone
4291 spin_lock(&file_priv
->mm
.lock
);
4292 while (!list_empty(&file_priv
->mm
.request_list
)) {
4293 struct drm_i915_gem_request
*request
;
4295 request
= list_first_entry(&file_priv
->mm
.request_list
,
4296 struct drm_i915_gem_request
,
4298 list_del(&request
->client_list
);
4299 request
->file_priv
= NULL
;
4301 spin_unlock(&file_priv
->mm
.lock
);
4304 static bool mutex_is_locked_by(struct mutex
*mutex
, struct task_struct
*task
)
4306 if (!mutex_is_locked(mutex
))
4309 #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES)
4310 return mutex
->owner
== task
;
4312 /* Since UP may be pre-empted, we cannot assume that we own the lock */
4318 i915_gem_inactive_shrink(struct shrinker
*shrinker
, struct shrink_control
*sc
)
4320 struct drm_i915_private
*dev_priv
=
4321 container_of(shrinker
,
4322 struct drm_i915_private
,
4323 mm
.inactive_shrinker
);
4324 struct drm_device
*dev
= dev_priv
->dev
;
4325 struct drm_i915_gem_object
*obj
;
4326 int nr_to_scan
= sc
->nr_to_scan
;
4330 if (!mutex_trylock(&dev
->struct_mutex
)) {
4331 if (!mutex_is_locked_by(&dev
->struct_mutex
, current
))
4334 if (dev_priv
->mm
.shrinker_no_lock_stealing
)
4341 nr_to_scan
-= i915_gem_purge(dev_priv
, nr_to_scan
);
4343 i915_gem_shrink_all(dev_priv
);
4347 list_for_each_entry(obj
, &dev_priv
->mm
.unbound_list
, gtt_list
)
4348 if (obj
->pages_pin_count
== 0)
4349 cnt
+= obj
->base
.size
>> PAGE_SHIFT
;
4350 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, gtt_list
)
4351 if (obj
->pin_count
== 0 && obj
->pages_pin_count
== 0)
4352 cnt
+= obj
->base
.size
>> PAGE_SHIFT
;
4355 mutex_unlock(&dev
->struct_mutex
);