2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/i915_drm.h>
31 #include "i915_trace.h"
32 #include "intel_drv.h"
33 #include <linux/shmem_fs.h>
34 #include <linux/slab.h>
35 #include <linux/swap.h>
36 #include <linux/pci.h>
37 #include <linux/dma-buf.h>
39 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
);
40 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
);
41 static __must_check
int
42 i915_gem_object_bind_to_vm(struct drm_i915_gem_object
*obj
,
43 struct i915_address_space
*vm
,
45 bool map_and_fenceable
,
47 static int i915_gem_phys_pwrite(struct drm_device
*dev
,
48 struct drm_i915_gem_object
*obj
,
49 struct drm_i915_gem_pwrite
*args
,
50 struct drm_file
*file
);
52 static void i915_gem_write_fence(struct drm_device
*dev
, int reg
,
53 struct drm_i915_gem_object
*obj
);
54 static void i915_gem_object_update_fence(struct drm_i915_gem_object
*obj
,
55 struct drm_i915_fence_reg
*fence
,
58 static int i915_gem_inactive_shrink(struct shrinker
*shrinker
,
59 struct shrink_control
*sc
);
60 static long i915_gem_purge(struct drm_i915_private
*dev_priv
, long target
);
61 static void i915_gem_shrink_all(struct drm_i915_private
*dev_priv
);
62 static void i915_gem_object_truncate(struct drm_i915_gem_object
*obj
);
64 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object
*obj
)
67 i915_gem_release_mmap(obj
);
69 /* As we do not have an associated fence register, we will force
70 * a tiling change if we ever need to acquire one.
72 obj
->fence_dirty
= false;
73 obj
->fence_reg
= I915_FENCE_REG_NONE
;
76 /* some bookkeeping */
77 static void i915_gem_info_add_obj(struct drm_i915_private
*dev_priv
,
80 spin_lock(&dev_priv
->mm
.object_stat_lock
);
81 dev_priv
->mm
.object_count
++;
82 dev_priv
->mm
.object_memory
+= size
;
83 spin_unlock(&dev_priv
->mm
.object_stat_lock
);
86 static void i915_gem_info_remove_obj(struct drm_i915_private
*dev_priv
,
89 spin_lock(&dev_priv
->mm
.object_stat_lock
);
90 dev_priv
->mm
.object_count
--;
91 dev_priv
->mm
.object_memory
-= size
;
92 spin_unlock(&dev_priv
->mm
.object_stat_lock
);
96 i915_gem_wait_for_error(struct i915_gpu_error
*error
)
100 #define EXIT_COND (!i915_reset_in_progress(error) || \
101 i915_terminally_wedged(error))
106 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
107 * userspace. If it takes that long something really bad is going on and
108 * we should simply try to bail out and fail as gracefully as possible.
110 ret
= wait_event_interruptible_timeout(error
->reset_queue
,
114 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
116 } else if (ret
< 0) {
124 int i915_mutex_lock_interruptible(struct drm_device
*dev
)
126 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
129 ret
= i915_gem_wait_for_error(&dev_priv
->gpu_error
);
133 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
137 WARN_ON(i915_verify_lists(dev
));
142 i915_gem_object_is_inactive(struct drm_i915_gem_object
*obj
)
144 return i915_gem_obj_bound_any(obj
) && !obj
->active
;
148 i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
149 struct drm_file
*file
)
151 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
152 struct drm_i915_gem_init
*args
= data
;
154 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
157 if (args
->gtt_start
>= args
->gtt_end
||
158 (args
->gtt_end
| args
->gtt_start
) & (PAGE_SIZE
- 1))
161 /* GEM with user mode setting was never supported on ilk and later. */
162 if (INTEL_INFO(dev
)->gen
>= 5)
165 mutex_lock(&dev
->struct_mutex
);
166 i915_gem_setup_global_gtt(dev
, args
->gtt_start
, args
->gtt_end
,
168 dev_priv
->gtt
.mappable_end
= args
->gtt_end
;
169 mutex_unlock(&dev
->struct_mutex
);
175 i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
176 struct drm_file
*file
)
178 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
179 struct drm_i915_gem_get_aperture
*args
= data
;
180 struct drm_i915_gem_object
*obj
;
184 mutex_lock(&dev
->struct_mutex
);
185 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
)
187 pinned
+= i915_gem_obj_ggtt_size(obj
);
188 mutex_unlock(&dev
->struct_mutex
);
190 args
->aper_size
= dev_priv
->gtt
.base
.total
;
191 args
->aper_available_size
= args
->aper_size
- pinned
;
196 void *i915_gem_object_alloc(struct drm_device
*dev
)
198 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
199 return kmem_cache_alloc(dev_priv
->slab
, GFP_KERNEL
| __GFP_ZERO
);
202 void i915_gem_object_free(struct drm_i915_gem_object
*obj
)
204 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
205 kmem_cache_free(dev_priv
->slab
, obj
);
209 i915_gem_create(struct drm_file
*file
,
210 struct drm_device
*dev
,
214 struct drm_i915_gem_object
*obj
;
218 size
= roundup(size
, PAGE_SIZE
);
222 /* Allocate the new object */
223 obj
= i915_gem_alloc_object(dev
, size
);
227 ret
= drm_gem_handle_create(file
, &obj
->base
, &handle
);
228 /* drop reference from allocate - handle holds it now */
229 drm_gem_object_unreference_unlocked(&obj
->base
);
238 i915_gem_dumb_create(struct drm_file
*file
,
239 struct drm_device
*dev
,
240 struct drm_mode_create_dumb
*args
)
242 /* have to work out size/pitch and return them */
243 args
->pitch
= ALIGN(args
->width
* ((args
->bpp
+ 7) / 8), 64);
244 args
->size
= args
->pitch
* args
->height
;
245 return i915_gem_create(file
, dev
,
246 args
->size
, &args
->handle
);
249 int i915_gem_dumb_destroy(struct drm_file
*file
,
250 struct drm_device
*dev
,
253 return drm_gem_handle_delete(file
, handle
);
257 * Creates a new mm object and returns a handle to it.
260 i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
261 struct drm_file
*file
)
263 struct drm_i915_gem_create
*args
= data
;
265 return i915_gem_create(file
, dev
,
266 args
->size
, &args
->handle
);
270 __copy_to_user_swizzled(char __user
*cpu_vaddr
,
271 const char *gpu_vaddr
, int gpu_offset
,
274 int ret
, cpu_offset
= 0;
277 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
278 int this_length
= min(cacheline_end
- gpu_offset
, length
);
279 int swizzled_gpu_offset
= gpu_offset
^ 64;
281 ret
= __copy_to_user(cpu_vaddr
+ cpu_offset
,
282 gpu_vaddr
+ swizzled_gpu_offset
,
287 cpu_offset
+= this_length
;
288 gpu_offset
+= this_length
;
289 length
-= this_length
;
296 __copy_from_user_swizzled(char *gpu_vaddr
, int gpu_offset
,
297 const char __user
*cpu_vaddr
,
300 int ret
, cpu_offset
= 0;
303 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
304 int this_length
= min(cacheline_end
- gpu_offset
, length
);
305 int swizzled_gpu_offset
= gpu_offset
^ 64;
307 ret
= __copy_from_user(gpu_vaddr
+ swizzled_gpu_offset
,
308 cpu_vaddr
+ cpu_offset
,
313 cpu_offset
+= this_length
;
314 gpu_offset
+= this_length
;
315 length
-= this_length
;
321 /* Per-page copy function for the shmem pread fastpath.
322 * Flushes invalid cachelines before reading the target if
323 * needs_clflush is set. */
325 shmem_pread_fast(struct page
*page
, int shmem_page_offset
, int page_length
,
326 char __user
*user_data
,
327 bool page_do_bit17_swizzling
, bool needs_clflush
)
332 if (unlikely(page_do_bit17_swizzling
))
335 vaddr
= kmap_atomic(page
);
337 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
339 ret
= __copy_to_user_inatomic(user_data
,
340 vaddr
+ shmem_page_offset
,
342 kunmap_atomic(vaddr
);
344 return ret
? -EFAULT
: 0;
348 shmem_clflush_swizzled_range(char *addr
, unsigned long length
,
351 if (unlikely(swizzled
)) {
352 unsigned long start
= (unsigned long) addr
;
353 unsigned long end
= (unsigned long) addr
+ length
;
355 /* For swizzling simply ensure that we always flush both
356 * channels. Lame, but simple and it works. Swizzled
357 * pwrite/pread is far from a hotpath - current userspace
358 * doesn't use it at all. */
359 start
= round_down(start
, 128);
360 end
= round_up(end
, 128);
362 drm_clflush_virt_range((void *)start
, end
- start
);
364 drm_clflush_virt_range(addr
, length
);
369 /* Only difference to the fast-path function is that this can handle bit17
370 * and uses non-atomic copy and kmap functions. */
372 shmem_pread_slow(struct page
*page
, int shmem_page_offset
, int page_length
,
373 char __user
*user_data
,
374 bool page_do_bit17_swizzling
, bool needs_clflush
)
381 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
383 page_do_bit17_swizzling
);
385 if (page_do_bit17_swizzling
)
386 ret
= __copy_to_user_swizzled(user_data
,
387 vaddr
, shmem_page_offset
,
390 ret
= __copy_to_user(user_data
,
391 vaddr
+ shmem_page_offset
,
395 return ret
? - EFAULT
: 0;
399 i915_gem_shmem_pread(struct drm_device
*dev
,
400 struct drm_i915_gem_object
*obj
,
401 struct drm_i915_gem_pread
*args
,
402 struct drm_file
*file
)
404 char __user
*user_data
;
407 int shmem_page_offset
, page_length
, ret
= 0;
408 int obj_do_bit17_swizzling
, page_do_bit17_swizzling
;
410 int needs_clflush
= 0;
411 struct sg_page_iter sg_iter
;
413 user_data
= to_user_ptr(args
->data_ptr
);
416 obj_do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
418 if (!(obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
)) {
419 /* If we're not in the cpu read domain, set ourself into the gtt
420 * read domain and manually flush cachelines (if required). This
421 * optimizes for the case when the gpu will dirty the data
422 * anyway again before the next pread happens. */
423 if (obj
->cache_level
== I915_CACHE_NONE
)
425 if (i915_gem_obj_bound_any(obj
)) {
426 ret
= i915_gem_object_set_to_gtt_domain(obj
, false);
432 ret
= i915_gem_object_get_pages(obj
);
436 i915_gem_object_pin_pages(obj
);
438 offset
= args
->offset
;
440 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
,
441 offset
>> PAGE_SHIFT
) {
442 struct page
*page
= sg_page_iter_page(&sg_iter
);
447 /* Operation in this page
449 * shmem_page_offset = offset within page in shmem file
450 * page_length = bytes to copy for this page
452 shmem_page_offset
= offset_in_page(offset
);
453 page_length
= remain
;
454 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
455 page_length
= PAGE_SIZE
- shmem_page_offset
;
457 page_do_bit17_swizzling
= obj_do_bit17_swizzling
&&
458 (page_to_phys(page
) & (1 << 17)) != 0;
460 ret
= shmem_pread_fast(page
, shmem_page_offset
, page_length
,
461 user_data
, page_do_bit17_swizzling
,
466 mutex_unlock(&dev
->struct_mutex
);
468 if (likely(!i915_prefault_disable
) && !prefaulted
) {
469 ret
= fault_in_multipages_writeable(user_data
, remain
);
470 /* Userspace is tricking us, but we've already clobbered
471 * its pages with the prefault and promised to write the
472 * data up to the first fault. Hence ignore any errors
473 * and just continue. */
478 ret
= shmem_pread_slow(page
, shmem_page_offset
, page_length
,
479 user_data
, page_do_bit17_swizzling
,
482 mutex_lock(&dev
->struct_mutex
);
485 mark_page_accessed(page
);
490 remain
-= page_length
;
491 user_data
+= page_length
;
492 offset
+= page_length
;
496 i915_gem_object_unpin_pages(obj
);
502 * Reads data from the object referenced by handle.
504 * On error, the contents of *data are undefined.
507 i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
508 struct drm_file
*file
)
510 struct drm_i915_gem_pread
*args
= data
;
511 struct drm_i915_gem_object
*obj
;
517 if (!access_ok(VERIFY_WRITE
,
518 to_user_ptr(args
->data_ptr
),
522 ret
= i915_mutex_lock_interruptible(dev
);
526 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
527 if (&obj
->base
== NULL
) {
532 /* Bounds check source. */
533 if (args
->offset
> obj
->base
.size
||
534 args
->size
> obj
->base
.size
- args
->offset
) {
539 /* prime objects have no backing filp to GEM pread/pwrite
542 if (!obj
->base
.filp
) {
547 trace_i915_gem_object_pread(obj
, args
->offset
, args
->size
);
549 ret
= i915_gem_shmem_pread(dev
, obj
, args
, file
);
552 drm_gem_object_unreference(&obj
->base
);
554 mutex_unlock(&dev
->struct_mutex
);
558 /* This is the fast write path which cannot handle
559 * page faults in the source data
563 fast_user_write(struct io_mapping
*mapping
,
564 loff_t page_base
, int page_offset
,
565 char __user
*user_data
,
568 void __iomem
*vaddr_atomic
;
570 unsigned long unwritten
;
572 vaddr_atomic
= io_mapping_map_atomic_wc(mapping
, page_base
);
573 /* We can use the cpu mem copy function because this is X86. */
574 vaddr
= (void __force
*)vaddr_atomic
+ page_offset
;
575 unwritten
= __copy_from_user_inatomic_nocache(vaddr
,
577 io_mapping_unmap_atomic(vaddr_atomic
);
582 * This is the fast pwrite path, where we copy the data directly from the
583 * user into the GTT, uncached.
586 i915_gem_gtt_pwrite_fast(struct drm_device
*dev
,
587 struct drm_i915_gem_object
*obj
,
588 struct drm_i915_gem_pwrite
*args
,
589 struct drm_file
*file
)
591 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
593 loff_t offset
, page_base
;
594 char __user
*user_data
;
595 int page_offset
, page_length
, ret
;
597 ret
= i915_gem_obj_ggtt_pin(obj
, 0, true, true);
601 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
605 ret
= i915_gem_object_put_fence(obj
);
609 user_data
= to_user_ptr(args
->data_ptr
);
612 offset
= i915_gem_obj_ggtt_offset(obj
) + args
->offset
;
615 /* Operation in this page
617 * page_base = page offset within aperture
618 * page_offset = offset within page
619 * page_length = bytes to copy for this page
621 page_base
= offset
& PAGE_MASK
;
622 page_offset
= offset_in_page(offset
);
623 page_length
= remain
;
624 if ((page_offset
+ remain
) > PAGE_SIZE
)
625 page_length
= PAGE_SIZE
- page_offset
;
627 /* If we get a fault while copying data, then (presumably) our
628 * source page isn't available. Return the error and we'll
629 * retry in the slow path.
631 if (fast_user_write(dev_priv
->gtt
.mappable
, page_base
,
632 page_offset
, user_data
, page_length
)) {
637 remain
-= page_length
;
638 user_data
+= page_length
;
639 offset
+= page_length
;
643 i915_gem_object_unpin(obj
);
648 /* Per-page copy function for the shmem pwrite fastpath.
649 * Flushes invalid cachelines before writing to the target if
650 * needs_clflush_before is set and flushes out any written cachelines after
651 * writing if needs_clflush is set. */
653 shmem_pwrite_fast(struct page
*page
, int shmem_page_offset
, int page_length
,
654 char __user
*user_data
,
655 bool page_do_bit17_swizzling
,
656 bool needs_clflush_before
,
657 bool needs_clflush_after
)
662 if (unlikely(page_do_bit17_swizzling
))
665 vaddr
= kmap_atomic(page
);
666 if (needs_clflush_before
)
667 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
669 ret
= __copy_from_user_inatomic_nocache(vaddr
+ shmem_page_offset
,
672 if (needs_clflush_after
)
673 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
675 kunmap_atomic(vaddr
);
677 return ret
? -EFAULT
: 0;
680 /* Only difference to the fast-path function is that this can handle bit17
681 * and uses non-atomic copy and kmap functions. */
683 shmem_pwrite_slow(struct page
*page
, int shmem_page_offset
, int page_length
,
684 char __user
*user_data
,
685 bool page_do_bit17_swizzling
,
686 bool needs_clflush_before
,
687 bool needs_clflush_after
)
693 if (unlikely(needs_clflush_before
|| page_do_bit17_swizzling
))
694 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
696 page_do_bit17_swizzling
);
697 if (page_do_bit17_swizzling
)
698 ret
= __copy_from_user_swizzled(vaddr
, shmem_page_offset
,
702 ret
= __copy_from_user(vaddr
+ shmem_page_offset
,
705 if (needs_clflush_after
)
706 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
708 page_do_bit17_swizzling
);
711 return ret
? -EFAULT
: 0;
715 i915_gem_shmem_pwrite(struct drm_device
*dev
,
716 struct drm_i915_gem_object
*obj
,
717 struct drm_i915_gem_pwrite
*args
,
718 struct drm_file
*file
)
722 char __user
*user_data
;
723 int shmem_page_offset
, page_length
, ret
= 0;
724 int obj_do_bit17_swizzling
, page_do_bit17_swizzling
;
725 int hit_slowpath
= 0;
726 int needs_clflush_after
= 0;
727 int needs_clflush_before
= 0;
728 struct sg_page_iter sg_iter
;
730 user_data
= to_user_ptr(args
->data_ptr
);
733 obj_do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
735 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
736 /* If we're not in the cpu write domain, set ourself into the gtt
737 * write domain and manually flush cachelines (if required). This
738 * optimizes for the case when the gpu will use the data
739 * right away and we therefore have to clflush anyway. */
740 if (obj
->cache_level
== I915_CACHE_NONE
)
741 needs_clflush_after
= 1;
742 if (i915_gem_obj_bound_any(obj
)) {
743 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
748 /* Same trick applies for invalidate partially written cachelines before
750 if (!(obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
)
751 && obj
->cache_level
== I915_CACHE_NONE
)
752 needs_clflush_before
= 1;
754 ret
= i915_gem_object_get_pages(obj
);
758 i915_gem_object_pin_pages(obj
);
760 offset
= args
->offset
;
763 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
,
764 offset
>> PAGE_SHIFT
) {
765 struct page
*page
= sg_page_iter_page(&sg_iter
);
766 int partial_cacheline_write
;
771 /* Operation in this page
773 * shmem_page_offset = offset within page in shmem file
774 * page_length = bytes to copy for this page
776 shmem_page_offset
= offset_in_page(offset
);
778 page_length
= remain
;
779 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
780 page_length
= PAGE_SIZE
- shmem_page_offset
;
782 /* If we don't overwrite a cacheline completely we need to be
783 * careful to have up-to-date data by first clflushing. Don't
784 * overcomplicate things and flush the entire patch. */
785 partial_cacheline_write
= needs_clflush_before
&&
786 ((shmem_page_offset
| page_length
)
787 & (boot_cpu_data
.x86_clflush_size
- 1));
789 page_do_bit17_swizzling
= obj_do_bit17_swizzling
&&
790 (page_to_phys(page
) & (1 << 17)) != 0;
792 ret
= shmem_pwrite_fast(page
, shmem_page_offset
, page_length
,
793 user_data
, page_do_bit17_swizzling
,
794 partial_cacheline_write
,
795 needs_clflush_after
);
800 mutex_unlock(&dev
->struct_mutex
);
801 ret
= shmem_pwrite_slow(page
, shmem_page_offset
, page_length
,
802 user_data
, page_do_bit17_swizzling
,
803 partial_cacheline_write
,
804 needs_clflush_after
);
806 mutex_lock(&dev
->struct_mutex
);
809 set_page_dirty(page
);
810 mark_page_accessed(page
);
815 remain
-= page_length
;
816 user_data
+= page_length
;
817 offset
+= page_length
;
821 i915_gem_object_unpin_pages(obj
);
825 * Fixup: Flush cpu caches in case we didn't flush the dirty
826 * cachelines in-line while writing and the object moved
827 * out of the cpu write domain while we've dropped the lock.
829 if (!needs_clflush_after
&&
830 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
831 i915_gem_clflush_object(obj
);
832 i915_gem_chipset_flush(dev
);
836 if (needs_clflush_after
)
837 i915_gem_chipset_flush(dev
);
843 * Writes data to the object referenced by handle.
845 * On error, the contents of the buffer that were to be modified are undefined.
848 i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
849 struct drm_file
*file
)
851 struct drm_i915_gem_pwrite
*args
= data
;
852 struct drm_i915_gem_object
*obj
;
858 if (!access_ok(VERIFY_READ
,
859 to_user_ptr(args
->data_ptr
),
863 if (likely(!i915_prefault_disable
)) {
864 ret
= fault_in_multipages_readable(to_user_ptr(args
->data_ptr
),
870 ret
= i915_mutex_lock_interruptible(dev
);
874 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
875 if (&obj
->base
== NULL
) {
880 /* Bounds check destination. */
881 if (args
->offset
> obj
->base
.size
||
882 args
->size
> obj
->base
.size
- args
->offset
) {
887 /* prime objects have no backing filp to GEM pread/pwrite
890 if (!obj
->base
.filp
) {
895 trace_i915_gem_object_pwrite(obj
, args
->offset
, args
->size
);
898 /* We can only do the GTT pwrite on untiled buffers, as otherwise
899 * it would end up going through the fenced access, and we'll get
900 * different detiling behavior between reading and writing.
901 * pread/pwrite currently are reading and writing from the CPU
902 * perspective, requiring manual detiling by the client.
905 ret
= i915_gem_phys_pwrite(dev
, obj
, args
, file
);
909 if (obj
->cache_level
== I915_CACHE_NONE
&&
910 obj
->tiling_mode
== I915_TILING_NONE
&&
911 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
912 ret
= i915_gem_gtt_pwrite_fast(dev
, obj
, args
, file
);
913 /* Note that the gtt paths might fail with non-page-backed user
914 * pointers (e.g. gtt mappings when moving data between
915 * textures). Fallback to the shmem path in that case. */
918 if (ret
== -EFAULT
|| ret
== -ENOSPC
)
919 ret
= i915_gem_shmem_pwrite(dev
, obj
, args
, file
);
922 drm_gem_object_unreference(&obj
->base
);
924 mutex_unlock(&dev
->struct_mutex
);
929 i915_gem_check_wedge(struct i915_gpu_error
*error
,
932 if (i915_reset_in_progress(error
)) {
933 /* Non-interruptible callers can't handle -EAGAIN, hence return
934 * -EIO unconditionally for these. */
938 /* Recovery complete, but the reset failed ... */
939 if (i915_terminally_wedged(error
))
949 * Compare seqno against outstanding lazy request. Emit a request if they are
953 i915_gem_check_olr(struct intel_ring_buffer
*ring
, u32 seqno
)
957 BUG_ON(!mutex_is_locked(&ring
->dev
->struct_mutex
));
960 if (seqno
== ring
->outstanding_lazy_request
)
961 ret
= i915_add_request(ring
, NULL
);
967 * __wait_seqno - wait until execution of seqno has finished
968 * @ring: the ring expected to report seqno
970 * @reset_counter: reset sequence associated with the given seqno
971 * @interruptible: do an interruptible wait (normally yes)
972 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
974 * Note: It is of utmost importance that the passed in seqno and reset_counter
975 * values have been read by the caller in an smp safe manner. Where read-side
976 * locks are involved, it is sufficient to read the reset_counter before
977 * unlocking the lock that protects the seqno. For lockless tricks, the
978 * reset_counter _must_ be read before, and an appropriate smp_rmb must be
981 * Returns 0 if the seqno was found within the alloted time. Else returns the
982 * errno with remaining time filled in timeout argument.
984 static int __wait_seqno(struct intel_ring_buffer
*ring
, u32 seqno
,
985 unsigned reset_counter
,
986 bool interruptible
, struct timespec
*timeout
)
988 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
989 struct timespec before
, now
, wait_time
={1,0};
990 unsigned long timeout_jiffies
;
992 bool wait_forever
= true;
995 if (i915_seqno_passed(ring
->get_seqno(ring
, true), seqno
))
998 trace_i915_gem_request_wait_begin(ring
, seqno
);
1000 if (timeout
!= NULL
) {
1001 wait_time
= *timeout
;
1002 wait_forever
= false;
1005 timeout_jiffies
= timespec_to_jiffies_timeout(&wait_time
);
1007 if (WARN_ON(!ring
->irq_get(ring
)))
1010 /* Record current time in case interrupted by signal, or wedged * */
1011 getrawmonotonic(&before
);
1014 (i915_seqno_passed(ring->get_seqno(ring, false), seqno) || \
1015 i915_reset_in_progress(&dev_priv->gpu_error) || \
1016 reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
1019 end
= wait_event_interruptible_timeout(ring
->irq_queue
,
1023 end
= wait_event_timeout(ring
->irq_queue
, EXIT_COND
,
1026 /* We need to check whether any gpu reset happened in between
1027 * the caller grabbing the seqno and now ... */
1028 if (reset_counter
!= atomic_read(&dev_priv
->gpu_error
.reset_counter
))
1031 /* ... but upgrade the -EGAIN to an -EIO if the gpu is truely
1033 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, interruptible
);
1036 } while (end
== 0 && wait_forever
);
1038 getrawmonotonic(&now
);
1040 ring
->irq_put(ring
);
1041 trace_i915_gem_request_wait_end(ring
, seqno
);
1045 struct timespec sleep_time
= timespec_sub(now
, before
);
1046 *timeout
= timespec_sub(*timeout
, sleep_time
);
1047 if (!timespec_valid(timeout
)) /* i.e. negative time remains */
1048 set_normalized_timespec(timeout
, 0, 0);
1053 case -EAGAIN
: /* Wedged */
1054 case -ERESTARTSYS
: /* Signal */
1056 case 0: /* Timeout */
1058 default: /* Completed */
1059 WARN_ON(end
< 0); /* We're not aware of other errors */
1065 * Waits for a sequence number to be signaled, and cleans up the
1066 * request and object lists appropriately for that event.
1069 i915_wait_seqno(struct intel_ring_buffer
*ring
, uint32_t seqno
)
1071 struct drm_device
*dev
= ring
->dev
;
1072 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1073 bool interruptible
= dev_priv
->mm
.interruptible
;
1076 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
1079 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, interruptible
);
1083 ret
= i915_gem_check_olr(ring
, seqno
);
1087 return __wait_seqno(ring
, seqno
,
1088 atomic_read(&dev_priv
->gpu_error
.reset_counter
),
1089 interruptible
, NULL
);
1093 i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object
*obj
,
1094 struct intel_ring_buffer
*ring
)
1096 i915_gem_retire_requests_ring(ring
);
1098 /* Manually manage the write flush as we may have not yet
1099 * retired the buffer.
1101 * Note that the last_write_seqno is always the earlier of
1102 * the two (read/write) seqno, so if we haved successfully waited,
1103 * we know we have passed the last write.
1105 obj
->last_write_seqno
= 0;
1106 obj
->base
.write_domain
&= ~I915_GEM_GPU_DOMAINS
;
1112 * Ensures that all rendering to the object has completed and the object is
1113 * safe to unbind from the GTT or access from the CPU.
1115 static __must_check
int
1116 i915_gem_object_wait_rendering(struct drm_i915_gem_object
*obj
,
1119 struct intel_ring_buffer
*ring
= obj
->ring
;
1123 seqno
= readonly
? obj
->last_write_seqno
: obj
->last_read_seqno
;
1127 ret
= i915_wait_seqno(ring
, seqno
);
1131 return i915_gem_object_wait_rendering__tail(obj
, ring
);
1134 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1135 * as the object state may change during this call.
1137 static __must_check
int
1138 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object
*obj
,
1141 struct drm_device
*dev
= obj
->base
.dev
;
1142 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1143 struct intel_ring_buffer
*ring
= obj
->ring
;
1144 unsigned reset_counter
;
1148 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
1149 BUG_ON(!dev_priv
->mm
.interruptible
);
1151 seqno
= readonly
? obj
->last_write_seqno
: obj
->last_read_seqno
;
1155 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, true);
1159 ret
= i915_gem_check_olr(ring
, seqno
);
1163 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
1164 mutex_unlock(&dev
->struct_mutex
);
1165 ret
= __wait_seqno(ring
, seqno
, reset_counter
, true, NULL
);
1166 mutex_lock(&dev
->struct_mutex
);
1170 return i915_gem_object_wait_rendering__tail(obj
, ring
);
1174 * Called when user space prepares to use an object with the CPU, either
1175 * through the mmap ioctl's mapping or a GTT mapping.
1178 i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
1179 struct drm_file
*file
)
1181 struct drm_i915_gem_set_domain
*args
= data
;
1182 struct drm_i915_gem_object
*obj
;
1183 uint32_t read_domains
= args
->read_domains
;
1184 uint32_t write_domain
= args
->write_domain
;
1187 /* Only handle setting domains to types used by the CPU. */
1188 if (write_domain
& I915_GEM_GPU_DOMAINS
)
1191 if (read_domains
& I915_GEM_GPU_DOMAINS
)
1194 /* Having something in the write domain implies it's in the read
1195 * domain, and only that read domain. Enforce that in the request.
1197 if (write_domain
!= 0 && read_domains
!= write_domain
)
1200 ret
= i915_mutex_lock_interruptible(dev
);
1204 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1205 if (&obj
->base
== NULL
) {
1210 /* Try to flush the object off the GPU without holding the lock.
1211 * We will repeat the flush holding the lock in the normal manner
1212 * to catch cases where we are gazumped.
1214 ret
= i915_gem_object_wait_rendering__nonblocking(obj
, !write_domain
);
1218 if (read_domains
& I915_GEM_DOMAIN_GTT
) {
1219 ret
= i915_gem_object_set_to_gtt_domain(obj
, write_domain
!= 0);
1221 /* Silently promote "you're not bound, there was nothing to do"
1222 * to success, since the client was just asking us to
1223 * make sure everything was done.
1228 ret
= i915_gem_object_set_to_cpu_domain(obj
, write_domain
!= 0);
1232 drm_gem_object_unreference(&obj
->base
);
1234 mutex_unlock(&dev
->struct_mutex
);
1239 * Called when user space has done writes to this buffer
1242 i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1243 struct drm_file
*file
)
1245 struct drm_i915_gem_sw_finish
*args
= data
;
1246 struct drm_i915_gem_object
*obj
;
1249 ret
= i915_mutex_lock_interruptible(dev
);
1253 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1254 if (&obj
->base
== NULL
) {
1259 /* Pinned buffers may be scanout, so flush the cache */
1261 i915_gem_object_flush_cpu_write_domain(obj
);
1263 drm_gem_object_unreference(&obj
->base
);
1265 mutex_unlock(&dev
->struct_mutex
);
1270 * Maps the contents of an object, returning the address it is mapped
1273 * While the mapping holds a reference on the contents of the object, it doesn't
1274 * imply a ref on the object itself.
1277 i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1278 struct drm_file
*file
)
1280 struct drm_i915_gem_mmap
*args
= data
;
1281 struct drm_gem_object
*obj
;
1284 obj
= drm_gem_object_lookup(dev
, file
, args
->handle
);
1288 /* prime objects have no backing filp to GEM mmap
1292 drm_gem_object_unreference_unlocked(obj
);
1296 addr
= vm_mmap(obj
->filp
, 0, args
->size
,
1297 PROT_READ
| PROT_WRITE
, MAP_SHARED
,
1299 drm_gem_object_unreference_unlocked(obj
);
1300 if (IS_ERR((void *)addr
))
1303 args
->addr_ptr
= (uint64_t) addr
;
1309 * i915_gem_fault - fault a page into the GTT
1310 * vma: VMA in question
1313 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1314 * from userspace. The fault handler takes care of binding the object to
1315 * the GTT (if needed), allocating and programming a fence register (again,
1316 * only if needed based on whether the old reg is still valid or the object
1317 * is tiled) and inserting a new PTE into the faulting process.
1319 * Note that the faulting process may involve evicting existing objects
1320 * from the GTT and/or fence registers to make room. So performance may
1321 * suffer if the GTT working set is large or there are few fence registers
1324 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
)
1326 struct drm_i915_gem_object
*obj
= to_intel_bo(vma
->vm_private_data
);
1327 struct drm_device
*dev
= obj
->base
.dev
;
1328 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1329 pgoff_t page_offset
;
1332 bool write
= !!(vmf
->flags
& FAULT_FLAG_WRITE
);
1334 /* We don't use vmf->pgoff since that has the fake offset */
1335 page_offset
= ((unsigned long)vmf
->virtual_address
- vma
->vm_start
) >>
1338 ret
= i915_mutex_lock_interruptible(dev
);
1342 trace_i915_gem_object_fault(obj
, page_offset
, true, write
);
1344 /* Access to snoopable pages through the GTT is incoherent. */
1345 if (obj
->cache_level
!= I915_CACHE_NONE
&& !HAS_LLC(dev
)) {
1350 /* Now bind it into the GTT if needed */
1351 ret
= i915_gem_obj_ggtt_pin(obj
, 0, true, false);
1355 ret
= i915_gem_object_set_to_gtt_domain(obj
, write
);
1359 ret
= i915_gem_object_get_fence(obj
);
1363 obj
->fault_mappable
= true;
1365 pfn
= dev_priv
->gtt
.mappable_base
+ i915_gem_obj_ggtt_offset(obj
);
1369 /* Finally, remap it using the new GTT offset */
1370 ret
= vm_insert_pfn(vma
, (unsigned long)vmf
->virtual_address
, pfn
);
1372 i915_gem_object_unpin(obj
);
1374 mutex_unlock(&dev
->struct_mutex
);
1378 /* If this -EIO is due to a gpu hang, give the reset code a
1379 * chance to clean up the mess. Otherwise return the proper
1381 if (i915_terminally_wedged(&dev_priv
->gpu_error
))
1382 return VM_FAULT_SIGBUS
;
1384 /* Give the error handler a chance to run and move the
1385 * objects off the GPU active list. Next time we service the
1386 * fault, we should be able to transition the page into the
1387 * GTT without touching the GPU (and so avoid further
1388 * EIO/EGAIN). If the GPU is wedged, then there is no issue
1389 * with coherency, just lost writes.
1397 * EBUSY is ok: this just means that another thread
1398 * already did the job.
1400 return VM_FAULT_NOPAGE
;
1402 return VM_FAULT_OOM
;
1404 return VM_FAULT_SIGBUS
;
1406 WARN_ONCE(ret
, "unhandled error in i915_gem_fault: %i\n", ret
);
1407 return VM_FAULT_SIGBUS
;
1412 * i915_gem_release_mmap - remove physical page mappings
1413 * @obj: obj in question
1415 * Preserve the reservation of the mmapping with the DRM core code, but
1416 * relinquish ownership of the pages back to the system.
1418 * It is vital that we remove the page mapping if we have mapped a tiled
1419 * object through the GTT and then lose the fence register due to
1420 * resource pressure. Similarly if the object has been moved out of the
1421 * aperture, than pages mapped into userspace must be revoked. Removing the
1422 * mapping will then trigger a page fault on the next user access, allowing
1423 * fixup by i915_gem_fault().
1426 i915_gem_release_mmap(struct drm_i915_gem_object
*obj
)
1428 if (!obj
->fault_mappable
)
1431 if (obj
->base
.dev
->dev_mapping
)
1432 unmap_mapping_range(obj
->base
.dev
->dev_mapping
,
1433 (loff_t
)obj
->base
.map_list
.hash
.key
<<PAGE_SHIFT
,
1436 obj
->fault_mappable
= false;
1440 i915_gem_get_gtt_size(struct drm_device
*dev
, uint32_t size
, int tiling_mode
)
1444 if (INTEL_INFO(dev
)->gen
>= 4 ||
1445 tiling_mode
== I915_TILING_NONE
)
1448 /* Previous chips need a power-of-two fence region when tiling */
1449 if (INTEL_INFO(dev
)->gen
== 3)
1450 gtt_size
= 1024*1024;
1452 gtt_size
= 512*1024;
1454 while (gtt_size
< size
)
1461 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1462 * @obj: object to check
1464 * Return the required GTT alignment for an object, taking into account
1465 * potential fence register mapping.
1468 i915_gem_get_gtt_alignment(struct drm_device
*dev
, uint32_t size
,
1469 int tiling_mode
, bool fenced
)
1472 * Minimum alignment is 4k (GTT page size), but might be greater
1473 * if a fence register is needed for the object.
1475 if (INTEL_INFO(dev
)->gen
>= 4 || (!fenced
&& IS_G33(dev
)) ||
1476 tiling_mode
== I915_TILING_NONE
)
1480 * Previous chips need to be aligned to the size of the smallest
1481 * fence register that can contain the object.
1483 return i915_gem_get_gtt_size(dev
, size
, tiling_mode
);
1486 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object
*obj
)
1488 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
1491 if (obj
->base
.map_list
.map
)
1494 dev_priv
->mm
.shrinker_no_lock_stealing
= true;
1496 ret
= drm_gem_create_mmap_offset(&obj
->base
);
1500 /* Badly fragmented mmap space? The only way we can recover
1501 * space is by destroying unwanted objects. We can't randomly release
1502 * mmap_offsets as userspace expects them to be persistent for the
1503 * lifetime of the objects. The closest we can is to release the
1504 * offsets on purgeable objects by truncating it and marking it purged,
1505 * which prevents userspace from ever using that object again.
1507 i915_gem_purge(dev_priv
, obj
->base
.size
>> PAGE_SHIFT
);
1508 ret
= drm_gem_create_mmap_offset(&obj
->base
);
1512 i915_gem_shrink_all(dev_priv
);
1513 ret
= drm_gem_create_mmap_offset(&obj
->base
);
1515 dev_priv
->mm
.shrinker_no_lock_stealing
= false;
1520 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object
*obj
)
1522 if (!obj
->base
.map_list
.map
)
1525 drm_gem_free_mmap_offset(&obj
->base
);
1529 i915_gem_mmap_gtt(struct drm_file
*file
,
1530 struct drm_device
*dev
,
1534 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1535 struct drm_i915_gem_object
*obj
;
1538 ret
= i915_mutex_lock_interruptible(dev
);
1542 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, handle
));
1543 if (&obj
->base
== NULL
) {
1548 if (obj
->base
.size
> dev_priv
->gtt
.mappable_end
) {
1553 if (obj
->madv
!= I915_MADV_WILLNEED
) {
1554 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1559 ret
= i915_gem_object_create_mmap_offset(obj
);
1563 *offset
= (u64
)obj
->base
.map_list
.hash
.key
<< PAGE_SHIFT
;
1566 drm_gem_object_unreference(&obj
->base
);
1568 mutex_unlock(&dev
->struct_mutex
);
1573 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1575 * @data: GTT mapping ioctl data
1576 * @file: GEM object info
1578 * Simply returns the fake offset to userspace so it can mmap it.
1579 * The mmap call will end up in drm_gem_mmap(), which will set things
1580 * up so we can get faults in the handler above.
1582 * The fault handler will take care of binding the object into the GTT
1583 * (since it may have been evicted to make room for something), allocating
1584 * a fence register, and mapping the appropriate aperture address into
1588 i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
1589 struct drm_file
*file
)
1591 struct drm_i915_gem_mmap_gtt
*args
= data
;
1593 return i915_gem_mmap_gtt(file
, dev
, args
->handle
, &args
->offset
);
1596 /* Immediately discard the backing storage */
1598 i915_gem_object_truncate(struct drm_i915_gem_object
*obj
)
1600 struct inode
*inode
;
1602 i915_gem_object_free_mmap_offset(obj
);
1604 if (obj
->base
.filp
== NULL
)
1607 /* Our goal here is to return as much of the memory as
1608 * is possible back to the system as we are called from OOM.
1609 * To do this we must instruct the shmfs to drop all of its
1610 * backing pages, *now*.
1612 inode
= file_inode(obj
->base
.filp
);
1613 shmem_truncate_range(inode
, 0, (loff_t
)-1);
1615 obj
->madv
= __I915_MADV_PURGED
;
1619 i915_gem_object_is_purgeable(struct drm_i915_gem_object
*obj
)
1621 return obj
->madv
== I915_MADV_DONTNEED
;
1625 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object
*obj
)
1627 struct sg_page_iter sg_iter
;
1630 BUG_ON(obj
->madv
== __I915_MADV_PURGED
);
1632 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
1634 /* In the event of a disaster, abandon all caches and
1635 * hope for the best.
1637 WARN_ON(ret
!= -EIO
);
1638 i915_gem_clflush_object(obj
);
1639 obj
->base
.read_domains
= obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
1642 if (i915_gem_object_needs_bit17_swizzle(obj
))
1643 i915_gem_object_save_bit_17_swizzle(obj
);
1645 if (obj
->madv
== I915_MADV_DONTNEED
)
1648 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
, 0) {
1649 struct page
*page
= sg_page_iter_page(&sg_iter
);
1652 set_page_dirty(page
);
1654 if (obj
->madv
== I915_MADV_WILLNEED
)
1655 mark_page_accessed(page
);
1657 page_cache_release(page
);
1661 sg_free_table(obj
->pages
);
1666 i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
)
1668 const struct drm_i915_gem_object_ops
*ops
= obj
->ops
;
1670 if (obj
->pages
== NULL
)
1673 if (obj
->pages_pin_count
)
1676 BUG_ON(i915_gem_obj_bound_any(obj
));
1678 /* ->put_pages might need to allocate memory for the bit17 swizzle
1679 * array, hence protect them from being reaped by removing them from gtt
1681 list_del(&obj
->global_list
);
1683 ops
->put_pages(obj
);
1686 if (i915_gem_object_is_purgeable(obj
))
1687 i915_gem_object_truncate(obj
);
1693 __i915_gem_shrink(struct drm_i915_private
*dev_priv
, long target
,
1694 bool purgeable_only
)
1696 struct drm_i915_gem_object
*obj
, *next
;
1699 list_for_each_entry_safe(obj
, next
,
1700 &dev_priv
->mm
.unbound_list
,
1702 if ((i915_gem_object_is_purgeable(obj
) || !purgeable_only
) &&
1703 i915_gem_object_put_pages(obj
) == 0) {
1704 count
+= obj
->base
.size
>> PAGE_SHIFT
;
1705 if (count
>= target
)
1710 list_for_each_entry_safe(obj
, next
, &dev_priv
->mm
.bound_list
,
1712 struct i915_vma
*vma
, *v
;
1714 if (!i915_gem_object_is_purgeable(obj
) && purgeable_only
)
1717 list_for_each_entry_safe(vma
, v
, &obj
->vma_list
, vma_link
)
1718 if (i915_vma_unbind(vma
))
1721 if (!i915_gem_object_put_pages(obj
)) {
1722 count
+= obj
->base
.size
>> PAGE_SHIFT
;
1723 if (count
>= target
)
1732 i915_gem_purge(struct drm_i915_private
*dev_priv
, long target
)
1734 return __i915_gem_shrink(dev_priv
, target
, true);
1738 i915_gem_shrink_all(struct drm_i915_private
*dev_priv
)
1740 struct drm_i915_gem_object
*obj
, *next
;
1742 i915_gem_evict_everything(dev_priv
->dev
);
1744 list_for_each_entry_safe(obj
, next
, &dev_priv
->mm
.unbound_list
,
1746 i915_gem_object_put_pages(obj
);
1750 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object
*obj
)
1752 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
1754 struct address_space
*mapping
;
1755 struct sg_table
*st
;
1756 struct scatterlist
*sg
;
1757 struct sg_page_iter sg_iter
;
1759 unsigned long last_pfn
= 0; /* suppress gcc warning */
1762 /* Assert that the object is not currently in any GPU domain. As it
1763 * wasn't in the GTT, there shouldn't be any way it could have been in
1766 BUG_ON(obj
->base
.read_domains
& I915_GEM_GPU_DOMAINS
);
1767 BUG_ON(obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
);
1769 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
1773 page_count
= obj
->base
.size
/ PAGE_SIZE
;
1774 if (sg_alloc_table(st
, page_count
, GFP_KERNEL
)) {
1780 /* Get the list of pages out of our struct file. They'll be pinned
1781 * at this point until we release them.
1783 * Fail silently without starting the shrinker
1785 mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
1786 gfp
= mapping_gfp_mask(mapping
);
1787 gfp
|= __GFP_NORETRY
| __GFP_NOWARN
| __GFP_NO_KSWAPD
;
1788 gfp
&= ~(__GFP_IO
| __GFP_WAIT
);
1791 for (i
= 0; i
< page_count
; i
++) {
1792 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
1794 i915_gem_purge(dev_priv
, page_count
);
1795 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
1798 /* We've tried hard to allocate the memory by reaping
1799 * our own buffer, now let the real VM do its job and
1800 * go down in flames if truly OOM.
1802 gfp
&= ~(__GFP_NORETRY
| __GFP_NOWARN
| __GFP_NO_KSWAPD
);
1803 gfp
|= __GFP_IO
| __GFP_WAIT
;
1805 i915_gem_shrink_all(dev_priv
);
1806 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
1810 gfp
|= __GFP_NORETRY
| __GFP_NOWARN
| __GFP_NO_KSWAPD
;
1811 gfp
&= ~(__GFP_IO
| __GFP_WAIT
);
1813 #ifdef CONFIG_SWIOTLB
1814 if (swiotlb_nr_tbl()) {
1816 sg_set_page(sg
, page
, PAGE_SIZE
, 0);
1821 if (!i
|| page_to_pfn(page
) != last_pfn
+ 1) {
1825 sg_set_page(sg
, page
, PAGE_SIZE
, 0);
1827 sg
->length
+= PAGE_SIZE
;
1829 last_pfn
= page_to_pfn(page
);
1831 #ifdef CONFIG_SWIOTLB
1832 if (!swiotlb_nr_tbl())
1837 if (i915_gem_object_needs_bit17_swizzle(obj
))
1838 i915_gem_object_do_bit_17_swizzle(obj
);
1844 for_each_sg_page(st
->sgl
, &sg_iter
, st
->nents
, 0)
1845 page_cache_release(sg_page_iter_page(&sg_iter
));
1848 return PTR_ERR(page
);
1851 /* Ensure that the associated pages are gathered from the backing storage
1852 * and pinned into our object. i915_gem_object_get_pages() may be called
1853 * multiple times before they are released by a single call to
1854 * i915_gem_object_put_pages() - once the pages are no longer referenced
1855 * either as a result of memory pressure (reaping pages under the shrinker)
1856 * or as the object is itself released.
1859 i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
)
1861 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
1862 const struct drm_i915_gem_object_ops
*ops
= obj
->ops
;
1868 if (obj
->madv
!= I915_MADV_WILLNEED
) {
1869 DRM_ERROR("Attempting to obtain a purgeable object\n");
1873 BUG_ON(obj
->pages_pin_count
);
1875 ret
= ops
->get_pages(obj
);
1879 list_add_tail(&obj
->global_list
, &dev_priv
->mm
.unbound_list
);
1884 i915_gem_object_move_to_active(struct drm_i915_gem_object
*obj
,
1885 struct intel_ring_buffer
*ring
)
1887 struct drm_device
*dev
= obj
->base
.dev
;
1888 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1889 struct i915_address_space
*vm
= &dev_priv
->gtt
.base
;
1890 u32 seqno
= intel_ring_get_seqno(ring
);
1892 BUG_ON(ring
== NULL
);
1893 if (obj
->ring
!= ring
&& obj
->last_write_seqno
) {
1894 /* Keep the seqno relative to the current ring */
1895 obj
->last_write_seqno
= seqno
;
1899 /* Add a reference if we're newly entering the active list. */
1901 drm_gem_object_reference(&obj
->base
);
1905 /* Move from whatever list we were on to the tail of execution. */
1906 list_move_tail(&obj
->mm_list
, &vm
->active_list
);
1907 list_move_tail(&obj
->ring_list
, &ring
->active_list
);
1909 obj
->last_read_seqno
= seqno
;
1911 if (obj
->fenced_gpu_access
) {
1912 obj
->last_fenced_seqno
= seqno
;
1914 /* Bump MRU to take account of the delayed flush */
1915 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
1916 struct drm_i915_fence_reg
*reg
;
1918 reg
= &dev_priv
->fence_regs
[obj
->fence_reg
];
1919 list_move_tail(®
->lru_list
,
1920 &dev_priv
->mm
.fence_list
);
1926 i915_gem_object_move_to_inactive(struct drm_i915_gem_object
*obj
)
1928 struct drm_device
*dev
= obj
->base
.dev
;
1929 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1930 struct i915_address_space
*vm
= &dev_priv
->gtt
.base
;
1932 BUG_ON(obj
->base
.write_domain
& ~I915_GEM_GPU_DOMAINS
);
1933 BUG_ON(!obj
->active
);
1935 list_move_tail(&obj
->mm_list
, &vm
->inactive_list
);
1937 list_del_init(&obj
->ring_list
);
1940 obj
->last_read_seqno
= 0;
1941 obj
->last_write_seqno
= 0;
1942 obj
->base
.write_domain
= 0;
1944 obj
->last_fenced_seqno
= 0;
1945 obj
->fenced_gpu_access
= false;
1948 drm_gem_object_unreference(&obj
->base
);
1950 WARN_ON(i915_verify_lists(dev
));
1954 i915_gem_init_seqno(struct drm_device
*dev
, u32 seqno
)
1956 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1957 struct intel_ring_buffer
*ring
;
1960 /* Carefully retire all requests without writing to the rings */
1961 for_each_ring(ring
, dev_priv
, i
) {
1962 ret
= intel_ring_idle(ring
);
1966 i915_gem_retire_requests(dev
);
1968 /* Finally reset hw state */
1969 for_each_ring(ring
, dev_priv
, i
) {
1970 intel_ring_init_seqno(ring
, seqno
);
1972 for (j
= 0; j
< ARRAY_SIZE(ring
->sync_seqno
); j
++)
1973 ring
->sync_seqno
[j
] = 0;
1979 int i915_gem_set_seqno(struct drm_device
*dev
, u32 seqno
)
1981 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1987 /* HWS page needs to be set less than what we
1988 * will inject to ring
1990 ret
= i915_gem_init_seqno(dev
, seqno
- 1);
1994 /* Carefully set the last_seqno value so that wrap
1995 * detection still works
1997 dev_priv
->next_seqno
= seqno
;
1998 dev_priv
->last_seqno
= seqno
- 1;
1999 if (dev_priv
->last_seqno
== 0)
2000 dev_priv
->last_seqno
--;
2006 i915_gem_get_seqno(struct drm_device
*dev
, u32
*seqno
)
2008 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2010 /* reserve 0 for non-seqno */
2011 if (dev_priv
->next_seqno
== 0) {
2012 int ret
= i915_gem_init_seqno(dev
, 0);
2016 dev_priv
->next_seqno
= 1;
2019 *seqno
= dev_priv
->last_seqno
= dev_priv
->next_seqno
++;
2023 int __i915_add_request(struct intel_ring_buffer
*ring
,
2024 struct drm_file
*file
,
2025 struct drm_i915_gem_object
*obj
,
2028 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
2029 struct drm_i915_gem_request
*request
;
2030 u32 request_ring_position
, request_start
;
2034 request_start
= intel_ring_get_tail(ring
);
2036 * Emit any outstanding flushes - execbuf can fail to emit the flush
2037 * after having emitted the batchbuffer command. Hence we need to fix
2038 * things up similar to emitting the lazy request. The difference here
2039 * is that the flush _must_ happen before the next request, no matter
2042 ret
= intel_ring_flush_all_caches(ring
);
2046 request
= kmalloc(sizeof(*request
), GFP_KERNEL
);
2047 if (request
== NULL
)
2051 /* Record the position of the start of the request so that
2052 * should we detect the updated seqno part-way through the
2053 * GPU processing the request, we never over-estimate the
2054 * position of the head.
2056 request_ring_position
= intel_ring_get_tail(ring
);
2058 ret
= ring
->add_request(ring
);
2064 request
->seqno
= intel_ring_get_seqno(ring
);
2065 request
->ring
= ring
;
2066 request
->head
= request_start
;
2067 request
->tail
= request_ring_position
;
2068 request
->ctx
= ring
->last_context
;
2069 request
->batch_obj
= obj
;
2071 /* Whilst this request exists, batch_obj will be on the
2072 * active_list, and so will hold the active reference. Only when this
2073 * request is retired will the the batch_obj be moved onto the
2074 * inactive_list and lose its active reference. Hence we do not need
2075 * to explicitly hold another reference here.
2079 i915_gem_context_reference(request
->ctx
);
2081 request
->emitted_jiffies
= jiffies
;
2082 was_empty
= list_empty(&ring
->request_list
);
2083 list_add_tail(&request
->list
, &ring
->request_list
);
2084 request
->file_priv
= NULL
;
2087 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
2089 spin_lock(&file_priv
->mm
.lock
);
2090 request
->file_priv
= file_priv
;
2091 list_add_tail(&request
->client_list
,
2092 &file_priv
->mm
.request_list
);
2093 spin_unlock(&file_priv
->mm
.lock
);
2096 trace_i915_gem_request_add(ring
, request
->seqno
);
2097 ring
->outstanding_lazy_request
= 0;
2099 if (!dev_priv
->ums
.mm_suspended
) {
2100 i915_queue_hangcheck(ring
->dev
);
2103 queue_delayed_work(dev_priv
->wq
,
2104 &dev_priv
->mm
.retire_work
,
2105 round_jiffies_up_relative(HZ
));
2106 intel_mark_busy(dev_priv
->dev
);
2111 *out_seqno
= request
->seqno
;
2116 i915_gem_request_remove_from_client(struct drm_i915_gem_request
*request
)
2118 struct drm_i915_file_private
*file_priv
= request
->file_priv
;
2123 spin_lock(&file_priv
->mm
.lock
);
2124 if (request
->file_priv
) {
2125 list_del(&request
->client_list
);
2126 request
->file_priv
= NULL
;
2128 spin_unlock(&file_priv
->mm
.lock
);
2131 static bool i915_head_inside_object(u32 acthd
, struct drm_i915_gem_object
*obj
,
2132 struct i915_address_space
*vm
)
2134 if (acthd
>= i915_gem_obj_offset(obj
, vm
) &&
2135 acthd
< i915_gem_obj_offset(obj
, vm
) + obj
->base
.size
)
2141 static bool i915_head_inside_request(const u32 acthd_unmasked
,
2142 const u32 request_start
,
2143 const u32 request_end
)
2145 const u32 acthd
= acthd_unmasked
& HEAD_ADDR
;
2147 if (request_start
< request_end
) {
2148 if (acthd
>= request_start
&& acthd
< request_end
)
2150 } else if (request_start
> request_end
) {
2151 if (acthd
>= request_start
|| acthd
< request_end
)
2158 static struct i915_address_space
*
2159 request_to_vm(struct drm_i915_gem_request
*request
)
2161 struct drm_i915_private
*dev_priv
= request
->ring
->dev
->dev_private
;
2162 struct i915_address_space
*vm
;
2164 vm
= &dev_priv
->gtt
.base
;
2169 static bool i915_request_guilty(struct drm_i915_gem_request
*request
,
2170 const u32 acthd
, bool *inside
)
2172 /* There is a possibility that unmasked head address
2173 * pointing inside the ring, matches the batch_obj address range.
2174 * However this is extremely unlikely.
2176 if (request
->batch_obj
) {
2177 if (i915_head_inside_object(acthd
, request
->batch_obj
,
2178 request_to_vm(request
))) {
2184 if (i915_head_inside_request(acthd
, request
->head
, request
->tail
)) {
2192 static void i915_set_reset_status(struct intel_ring_buffer
*ring
,
2193 struct drm_i915_gem_request
*request
,
2196 struct i915_ctx_hang_stats
*hs
= NULL
;
2197 bool inside
, guilty
;
2198 unsigned long offset
= 0;
2200 /* Innocent until proven guilty */
2203 if (request
->batch_obj
)
2204 offset
= i915_gem_obj_offset(request
->batch_obj
,
2205 request_to_vm(request
));
2207 if (ring
->hangcheck
.action
!= wait
&&
2208 i915_request_guilty(request
, acthd
, &inside
)) {
2209 DRM_ERROR("%s hung %s bo (0x%lx ctx %d) at 0x%x\n",
2211 inside
? "inside" : "flushing",
2213 request
->ctx
? request
->ctx
->id
: 0,
2219 /* If contexts are disabled or this is the default context, use
2220 * file_priv->reset_state
2222 if (request
->ctx
&& request
->ctx
->id
!= DEFAULT_CONTEXT_ID
)
2223 hs
= &request
->ctx
->hang_stats
;
2224 else if (request
->file_priv
)
2225 hs
= &request
->file_priv
->hang_stats
;
2231 hs
->batch_pending
++;
2235 static void i915_gem_free_request(struct drm_i915_gem_request
*request
)
2237 list_del(&request
->list
);
2238 i915_gem_request_remove_from_client(request
);
2241 i915_gem_context_unreference(request
->ctx
);
2246 static void i915_gem_reset_ring_lists(struct drm_i915_private
*dev_priv
,
2247 struct intel_ring_buffer
*ring
)
2249 u32 completed_seqno
;
2252 acthd
= intel_ring_get_active_head(ring
);
2253 completed_seqno
= ring
->get_seqno(ring
, false);
2255 while (!list_empty(&ring
->request_list
)) {
2256 struct drm_i915_gem_request
*request
;
2258 request
= list_first_entry(&ring
->request_list
,
2259 struct drm_i915_gem_request
,
2262 if (request
->seqno
> completed_seqno
)
2263 i915_set_reset_status(ring
, request
, acthd
);
2265 i915_gem_free_request(request
);
2268 while (!list_empty(&ring
->active_list
)) {
2269 struct drm_i915_gem_object
*obj
;
2271 obj
= list_first_entry(&ring
->active_list
,
2272 struct drm_i915_gem_object
,
2275 i915_gem_object_move_to_inactive(obj
);
2279 void i915_gem_restore_fences(struct drm_device
*dev
)
2281 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2284 for (i
= 0; i
< dev_priv
->num_fence_regs
; i
++) {
2285 struct drm_i915_fence_reg
*reg
= &dev_priv
->fence_regs
[i
];
2288 * Commit delayed tiling changes if we have an object still
2289 * attached to the fence, otherwise just clear the fence.
2292 i915_gem_object_update_fence(reg
->obj
, reg
,
2293 reg
->obj
->tiling_mode
);
2295 i915_gem_write_fence(dev
, i
, NULL
);
2300 void i915_gem_reset(struct drm_device
*dev
)
2302 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2303 struct intel_ring_buffer
*ring
;
2306 for_each_ring(ring
, dev_priv
, i
)
2307 i915_gem_reset_ring_lists(dev_priv
, ring
);
2309 i915_gem_restore_fences(dev
);
2313 * This function clears the request list as sequence numbers are passed.
2316 i915_gem_retire_requests_ring(struct intel_ring_buffer
*ring
)
2320 if (list_empty(&ring
->request_list
))
2323 WARN_ON(i915_verify_lists(ring
->dev
));
2325 seqno
= ring
->get_seqno(ring
, true);
2327 while (!list_empty(&ring
->request_list
)) {
2328 struct drm_i915_gem_request
*request
;
2330 request
= list_first_entry(&ring
->request_list
,
2331 struct drm_i915_gem_request
,
2334 if (!i915_seqno_passed(seqno
, request
->seqno
))
2337 trace_i915_gem_request_retire(ring
, request
->seqno
);
2338 /* We know the GPU must have read the request to have
2339 * sent us the seqno + interrupt, so use the position
2340 * of tail of the request to update the last known position
2343 ring
->last_retired_head
= request
->tail
;
2345 i915_gem_free_request(request
);
2348 /* Move any buffers on the active list that are no longer referenced
2349 * by the ringbuffer to the flushing/inactive lists as appropriate.
2351 while (!list_empty(&ring
->active_list
)) {
2352 struct drm_i915_gem_object
*obj
;
2354 obj
= list_first_entry(&ring
->active_list
,
2355 struct drm_i915_gem_object
,
2358 if (!i915_seqno_passed(seqno
, obj
->last_read_seqno
))
2361 i915_gem_object_move_to_inactive(obj
);
2364 if (unlikely(ring
->trace_irq_seqno
&&
2365 i915_seqno_passed(seqno
, ring
->trace_irq_seqno
))) {
2366 ring
->irq_put(ring
);
2367 ring
->trace_irq_seqno
= 0;
2370 WARN_ON(i915_verify_lists(ring
->dev
));
2374 i915_gem_retire_requests(struct drm_device
*dev
)
2376 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2377 struct intel_ring_buffer
*ring
;
2380 for_each_ring(ring
, dev_priv
, i
)
2381 i915_gem_retire_requests_ring(ring
);
2385 i915_gem_retire_work_handler(struct work_struct
*work
)
2387 drm_i915_private_t
*dev_priv
;
2388 struct drm_device
*dev
;
2389 struct intel_ring_buffer
*ring
;
2393 dev_priv
= container_of(work
, drm_i915_private_t
,
2394 mm
.retire_work
.work
);
2395 dev
= dev_priv
->dev
;
2397 /* Come back later if the device is busy... */
2398 if (!mutex_trylock(&dev
->struct_mutex
)) {
2399 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
,
2400 round_jiffies_up_relative(HZ
));
2404 i915_gem_retire_requests(dev
);
2406 /* Send a periodic flush down the ring so we don't hold onto GEM
2407 * objects indefinitely.
2410 for_each_ring(ring
, dev_priv
, i
) {
2411 if (ring
->gpu_caches_dirty
)
2412 i915_add_request(ring
, NULL
);
2414 idle
&= list_empty(&ring
->request_list
);
2417 if (!dev_priv
->ums
.mm_suspended
&& !idle
)
2418 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
,
2419 round_jiffies_up_relative(HZ
));
2421 intel_mark_idle(dev
);
2423 mutex_unlock(&dev
->struct_mutex
);
2427 * Ensures that an object will eventually get non-busy by flushing any required
2428 * write domains, emitting any outstanding lazy request and retiring and
2429 * completed requests.
2432 i915_gem_object_flush_active(struct drm_i915_gem_object
*obj
)
2437 ret
= i915_gem_check_olr(obj
->ring
, obj
->last_read_seqno
);
2441 i915_gem_retire_requests_ring(obj
->ring
);
2448 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2449 * @DRM_IOCTL_ARGS: standard ioctl arguments
2451 * Returns 0 if successful, else an error is returned with the remaining time in
2452 * the timeout parameter.
2453 * -ETIME: object is still busy after timeout
2454 * -ERESTARTSYS: signal interrupted the wait
2455 * -ENONENT: object doesn't exist
2456 * Also possible, but rare:
2457 * -EAGAIN: GPU wedged
2459 * -ENODEV: Internal IRQ fail
2460 * -E?: The add request failed
2462 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2463 * non-zero timeout parameter the wait ioctl will wait for the given number of
2464 * nanoseconds on an object becoming unbusy. Since the wait itself does so
2465 * without holding struct_mutex the object may become re-busied before this
2466 * function completes. A similar but shorter * race condition exists in the busy
2470 i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
, struct drm_file
*file
)
2472 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2473 struct drm_i915_gem_wait
*args
= data
;
2474 struct drm_i915_gem_object
*obj
;
2475 struct intel_ring_buffer
*ring
= NULL
;
2476 struct timespec timeout_stack
, *timeout
= NULL
;
2477 unsigned reset_counter
;
2481 if (args
->timeout_ns
>= 0) {
2482 timeout_stack
= ns_to_timespec(args
->timeout_ns
);
2483 timeout
= &timeout_stack
;
2486 ret
= i915_mutex_lock_interruptible(dev
);
2490 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->bo_handle
));
2491 if (&obj
->base
== NULL
) {
2492 mutex_unlock(&dev
->struct_mutex
);
2496 /* Need to make sure the object gets inactive eventually. */
2497 ret
= i915_gem_object_flush_active(obj
);
2502 seqno
= obj
->last_read_seqno
;
2509 /* Do this after OLR check to make sure we make forward progress polling
2510 * on this IOCTL with a 0 timeout (like busy ioctl)
2512 if (!args
->timeout_ns
) {
2517 drm_gem_object_unreference(&obj
->base
);
2518 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
2519 mutex_unlock(&dev
->struct_mutex
);
2521 ret
= __wait_seqno(ring
, seqno
, reset_counter
, true, timeout
);
2523 args
->timeout_ns
= timespec_to_ns(timeout
);
2527 drm_gem_object_unreference(&obj
->base
);
2528 mutex_unlock(&dev
->struct_mutex
);
2533 * i915_gem_object_sync - sync an object to a ring.
2535 * @obj: object which may be in use on another ring.
2536 * @to: ring we wish to use the object on. May be NULL.
2538 * This code is meant to abstract object synchronization with the GPU.
2539 * Calling with NULL implies synchronizing the object with the CPU
2540 * rather than a particular GPU ring.
2542 * Returns 0 if successful, else propagates up the lower layer error.
2545 i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
2546 struct intel_ring_buffer
*to
)
2548 struct intel_ring_buffer
*from
= obj
->ring
;
2552 if (from
== NULL
|| to
== from
)
2555 if (to
== NULL
|| !i915_semaphore_is_enabled(obj
->base
.dev
))
2556 return i915_gem_object_wait_rendering(obj
, false);
2558 idx
= intel_ring_sync_index(from
, to
);
2560 seqno
= obj
->last_read_seqno
;
2561 if (seqno
<= from
->sync_seqno
[idx
])
2564 ret
= i915_gem_check_olr(obj
->ring
, seqno
);
2568 ret
= to
->sync_to(to
, from
, seqno
);
2570 /* We use last_read_seqno because sync_to()
2571 * might have just caused seqno wrap under
2574 from
->sync_seqno
[idx
] = obj
->last_read_seqno
;
2579 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object
*obj
)
2581 u32 old_write_domain
, old_read_domains
;
2583 /* Force a pagefault for domain tracking on next user access */
2584 i915_gem_release_mmap(obj
);
2586 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
) == 0)
2589 /* Wait for any direct GTT access to complete */
2592 old_read_domains
= obj
->base
.read_domains
;
2593 old_write_domain
= obj
->base
.write_domain
;
2595 obj
->base
.read_domains
&= ~I915_GEM_DOMAIN_GTT
;
2596 obj
->base
.write_domain
&= ~I915_GEM_DOMAIN_GTT
;
2598 trace_i915_gem_object_change_domain(obj
,
2603 int i915_vma_unbind(struct i915_vma
*vma
)
2605 struct drm_i915_gem_object
*obj
= vma
->obj
;
2606 drm_i915_private_t
*dev_priv
= obj
->base
.dev
->dev_private
;
2609 if (list_empty(&vma
->vma_link
))
2615 BUG_ON(obj
->pages
== NULL
);
2617 ret
= i915_gem_object_finish_gpu(obj
);
2620 /* Continue on if we fail due to EIO, the GPU is hung so we
2621 * should be safe and we need to cleanup or else we might
2622 * cause memory corruption through use-after-free.
2625 i915_gem_object_finish_gtt(obj
);
2627 /* release the fence reg _after_ flushing */
2628 ret
= i915_gem_object_put_fence(obj
);
2632 trace_i915_vma_unbind(vma
);
2634 if (obj
->has_global_gtt_mapping
)
2635 i915_gem_gtt_unbind_object(obj
);
2636 if (obj
->has_aliasing_ppgtt_mapping
) {
2637 i915_ppgtt_unbind_object(dev_priv
->mm
.aliasing_ppgtt
, obj
);
2638 obj
->has_aliasing_ppgtt_mapping
= 0;
2640 i915_gem_gtt_finish_object(obj
);
2641 i915_gem_object_unpin_pages(obj
);
2643 list_del(&obj
->mm_list
);
2644 /* Avoid an unnecessary call to unbind on rebind. */
2645 obj
->map_and_fenceable
= true;
2647 list_del(&vma
->vma_link
);
2648 drm_mm_remove_node(&vma
->node
);
2649 i915_gem_vma_destroy(vma
);
2651 /* Since the unbound list is global, only move to that list if
2652 * no more VMAs exist.
2653 * NB: Until we have real VMAs there will only ever be one */
2654 WARN_ON(!list_empty(&obj
->vma_list
));
2655 if (list_empty(&obj
->vma_list
))
2656 list_move_tail(&obj
->global_list
, &dev_priv
->mm
.unbound_list
);
2662 * Unbinds an object from the global GTT aperture.
2665 i915_gem_object_ggtt_unbind(struct drm_i915_gem_object
*obj
)
2667 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2668 struct i915_address_space
*ggtt
= &dev_priv
->gtt
.base
;
2670 if (!i915_gem_obj_ggtt_bound(obj
));
2676 BUG_ON(obj
->pages
== NULL
);
2678 return i915_vma_unbind(i915_gem_obj_to_vma(obj
, ggtt
));
2681 int i915_gpu_idle(struct drm_device
*dev
)
2683 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2684 struct intel_ring_buffer
*ring
;
2687 /* Flush everything onto the inactive list. */
2688 for_each_ring(ring
, dev_priv
, i
) {
2689 ret
= i915_switch_context(ring
, NULL
, DEFAULT_CONTEXT_ID
);
2693 ret
= intel_ring_idle(ring
);
2701 static void i965_write_fence_reg(struct drm_device
*dev
, int reg
,
2702 struct drm_i915_gem_object
*obj
)
2704 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2706 int fence_pitch_shift
;
2708 if (INTEL_INFO(dev
)->gen
>= 6) {
2709 fence_reg
= FENCE_REG_SANDYBRIDGE_0
;
2710 fence_pitch_shift
= SANDYBRIDGE_FENCE_PITCH_SHIFT
;
2712 fence_reg
= FENCE_REG_965_0
;
2713 fence_pitch_shift
= I965_FENCE_PITCH_SHIFT
;
2716 fence_reg
+= reg
* 8;
2718 /* To w/a incoherency with non-atomic 64-bit register updates,
2719 * we split the 64-bit update into two 32-bit writes. In order
2720 * for a partial fence not to be evaluated between writes, we
2721 * precede the update with write to turn off the fence register,
2722 * and only enable the fence as the last step.
2724 * For extra levels of paranoia, we make sure each step lands
2725 * before applying the next step.
2727 I915_WRITE(fence_reg
, 0);
2728 POSTING_READ(fence_reg
);
2731 u32 size
= i915_gem_obj_ggtt_size(obj
);
2734 val
= (uint64_t)((i915_gem_obj_ggtt_offset(obj
) + size
- 4096) &
2736 val
|= i915_gem_obj_ggtt_offset(obj
) & 0xfffff000;
2737 val
|= (uint64_t)((obj
->stride
/ 128) - 1) << fence_pitch_shift
;
2738 if (obj
->tiling_mode
== I915_TILING_Y
)
2739 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
2740 val
|= I965_FENCE_REG_VALID
;
2742 I915_WRITE(fence_reg
+ 4, val
>> 32);
2743 POSTING_READ(fence_reg
+ 4);
2745 I915_WRITE(fence_reg
+ 0, val
);
2746 POSTING_READ(fence_reg
);
2748 I915_WRITE(fence_reg
+ 4, 0);
2749 POSTING_READ(fence_reg
+ 4);
2753 static void i915_write_fence_reg(struct drm_device
*dev
, int reg
,
2754 struct drm_i915_gem_object
*obj
)
2756 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2760 u32 size
= i915_gem_obj_ggtt_size(obj
);
2764 WARN((i915_gem_obj_ggtt_offset(obj
) & ~I915_FENCE_START_MASK
) ||
2765 (size
& -size
) != size
||
2766 (i915_gem_obj_ggtt_offset(obj
) & (size
- 1)),
2767 "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2768 i915_gem_obj_ggtt_offset(obj
), obj
->map_and_fenceable
, size
);
2770 if (obj
->tiling_mode
== I915_TILING_Y
&& HAS_128_BYTE_Y_TILING(dev
))
2775 /* Note: pitch better be a power of two tile widths */
2776 pitch_val
= obj
->stride
/ tile_width
;
2777 pitch_val
= ffs(pitch_val
) - 1;
2779 val
= i915_gem_obj_ggtt_offset(obj
);
2780 if (obj
->tiling_mode
== I915_TILING_Y
)
2781 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2782 val
|= I915_FENCE_SIZE_BITS(size
);
2783 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2784 val
|= I830_FENCE_REG_VALID
;
2789 reg
= FENCE_REG_830_0
+ reg
* 4;
2791 reg
= FENCE_REG_945_8
+ (reg
- 8) * 4;
2793 I915_WRITE(reg
, val
);
2797 static void i830_write_fence_reg(struct drm_device
*dev
, int reg
,
2798 struct drm_i915_gem_object
*obj
)
2800 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2804 u32 size
= i915_gem_obj_ggtt_size(obj
);
2807 WARN((i915_gem_obj_ggtt_offset(obj
) & ~I830_FENCE_START_MASK
) ||
2808 (size
& -size
) != size
||
2809 (i915_gem_obj_ggtt_offset(obj
) & (size
- 1)),
2810 "object 0x%08lx not 512K or pot-size 0x%08x aligned\n",
2811 i915_gem_obj_ggtt_offset(obj
), size
);
2813 pitch_val
= obj
->stride
/ 128;
2814 pitch_val
= ffs(pitch_val
) - 1;
2816 val
= i915_gem_obj_ggtt_offset(obj
);
2817 if (obj
->tiling_mode
== I915_TILING_Y
)
2818 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2819 val
|= I830_FENCE_SIZE_BITS(size
);
2820 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2821 val
|= I830_FENCE_REG_VALID
;
2825 I915_WRITE(FENCE_REG_830_0
+ reg
* 4, val
);
2826 POSTING_READ(FENCE_REG_830_0
+ reg
* 4);
2829 inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object
*obj
)
2831 return obj
&& obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
;
2834 static void i915_gem_write_fence(struct drm_device
*dev
, int reg
,
2835 struct drm_i915_gem_object
*obj
)
2837 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2839 /* Ensure that all CPU reads are completed before installing a fence
2840 * and all writes before removing the fence.
2842 if (i915_gem_object_needs_mb(dev_priv
->fence_regs
[reg
].obj
))
2845 WARN(obj
&& (!obj
->stride
|| !obj
->tiling_mode
),
2846 "bogus fence setup with stride: 0x%x, tiling mode: %i\n",
2847 obj
->stride
, obj
->tiling_mode
);
2849 switch (INTEL_INFO(dev
)->gen
) {
2853 case 4: i965_write_fence_reg(dev
, reg
, obj
); break;
2854 case 3: i915_write_fence_reg(dev
, reg
, obj
); break;
2855 case 2: i830_write_fence_reg(dev
, reg
, obj
); break;
2859 /* And similarly be paranoid that no direct access to this region
2860 * is reordered to before the fence is installed.
2862 if (i915_gem_object_needs_mb(obj
))
2866 static inline int fence_number(struct drm_i915_private
*dev_priv
,
2867 struct drm_i915_fence_reg
*fence
)
2869 return fence
- dev_priv
->fence_regs
;
2872 static void i915_gem_object_update_fence(struct drm_i915_gem_object
*obj
,
2873 struct drm_i915_fence_reg
*fence
,
2876 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2877 int reg
= fence_number(dev_priv
, fence
);
2879 i915_gem_write_fence(obj
->base
.dev
, reg
, enable
? obj
: NULL
);
2882 obj
->fence_reg
= reg
;
2884 list_move_tail(&fence
->lru_list
, &dev_priv
->mm
.fence_list
);
2886 obj
->fence_reg
= I915_FENCE_REG_NONE
;
2888 list_del_init(&fence
->lru_list
);
2890 obj
->fence_dirty
= false;
2894 i915_gem_object_wait_fence(struct drm_i915_gem_object
*obj
)
2896 if (obj
->last_fenced_seqno
) {
2897 int ret
= i915_wait_seqno(obj
->ring
, obj
->last_fenced_seqno
);
2901 obj
->last_fenced_seqno
= 0;
2904 obj
->fenced_gpu_access
= false;
2909 i915_gem_object_put_fence(struct drm_i915_gem_object
*obj
)
2911 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2912 struct drm_i915_fence_reg
*fence
;
2915 ret
= i915_gem_object_wait_fence(obj
);
2919 if (obj
->fence_reg
== I915_FENCE_REG_NONE
)
2922 fence
= &dev_priv
->fence_regs
[obj
->fence_reg
];
2924 i915_gem_object_fence_lost(obj
);
2925 i915_gem_object_update_fence(obj
, fence
, false);
2930 static struct drm_i915_fence_reg
*
2931 i915_find_fence_reg(struct drm_device
*dev
)
2933 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2934 struct drm_i915_fence_reg
*reg
, *avail
;
2937 /* First try to find a free reg */
2939 for (i
= dev_priv
->fence_reg_start
; i
< dev_priv
->num_fence_regs
; i
++) {
2940 reg
= &dev_priv
->fence_regs
[i
];
2944 if (!reg
->pin_count
)
2951 /* None available, try to steal one or wait for a user to finish */
2952 list_for_each_entry(reg
, &dev_priv
->mm
.fence_list
, lru_list
) {
2963 * i915_gem_object_get_fence - set up fencing for an object
2964 * @obj: object to map through a fence reg
2966 * When mapping objects through the GTT, userspace wants to be able to write
2967 * to them without having to worry about swizzling if the object is tiled.
2968 * This function walks the fence regs looking for a free one for @obj,
2969 * stealing one if it can't find any.
2971 * It then sets up the reg based on the object's properties: address, pitch
2972 * and tiling format.
2974 * For an untiled surface, this removes any existing fence.
2977 i915_gem_object_get_fence(struct drm_i915_gem_object
*obj
)
2979 struct drm_device
*dev
= obj
->base
.dev
;
2980 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2981 bool enable
= obj
->tiling_mode
!= I915_TILING_NONE
;
2982 struct drm_i915_fence_reg
*reg
;
2985 /* Have we updated the tiling parameters upon the object and so
2986 * will need to serialise the write to the associated fence register?
2988 if (obj
->fence_dirty
) {
2989 ret
= i915_gem_object_wait_fence(obj
);
2994 /* Just update our place in the LRU if our fence is getting reused. */
2995 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
2996 reg
= &dev_priv
->fence_regs
[obj
->fence_reg
];
2997 if (!obj
->fence_dirty
) {
2998 list_move_tail(®
->lru_list
,
2999 &dev_priv
->mm
.fence_list
);
3002 } else if (enable
) {
3003 reg
= i915_find_fence_reg(dev
);
3008 struct drm_i915_gem_object
*old
= reg
->obj
;
3010 ret
= i915_gem_object_wait_fence(old
);
3014 i915_gem_object_fence_lost(old
);
3019 i915_gem_object_update_fence(obj
, reg
, enable
);
3024 static bool i915_gem_valid_gtt_space(struct drm_device
*dev
,
3025 struct drm_mm_node
*gtt_space
,
3026 unsigned long cache_level
)
3028 struct drm_mm_node
*other
;
3030 /* On non-LLC machines we have to be careful when putting differing
3031 * types of snoopable memory together to avoid the prefetcher
3032 * crossing memory domains and dying.
3037 if (!drm_mm_node_allocated(gtt_space
))
3040 if (list_empty(>t_space
->node_list
))
3043 other
= list_entry(gtt_space
->node_list
.prev
, struct drm_mm_node
, node_list
);
3044 if (other
->allocated
&& !other
->hole_follows
&& other
->color
!= cache_level
)
3047 other
= list_entry(gtt_space
->node_list
.next
, struct drm_mm_node
, node_list
);
3048 if (other
->allocated
&& !gtt_space
->hole_follows
&& other
->color
!= cache_level
)
3054 static void i915_gem_verify_gtt(struct drm_device
*dev
)
3057 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3058 struct drm_i915_gem_object
*obj
;
3061 list_for_each_entry(obj
, &dev_priv
->mm
.gtt_list
, global_list
) {
3062 if (obj
->gtt_space
== NULL
) {
3063 printk(KERN_ERR
"object found on GTT list with no space reserved\n");
3068 if (obj
->cache_level
!= obj
->gtt_space
->color
) {
3069 printk(KERN_ERR
"object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n",
3070 i915_gem_obj_ggtt_offset(obj
),
3071 i915_gem_obj_ggtt_offset(obj
) + i915_gem_obj_ggtt_size(obj
),
3073 obj
->gtt_space
->color
);
3078 if (!i915_gem_valid_gtt_space(dev
,
3080 obj
->cache_level
)) {
3081 printk(KERN_ERR
"invalid GTT space found at [%08lx, %08lx] - color=%x\n",
3082 i915_gem_obj_ggtt_offset(obj
),
3083 i915_gem_obj_ggtt_offset(obj
) + i915_gem_obj_ggtt_size(obj
),
3095 * Finds free space in the GTT aperture and binds the object there.
3098 i915_gem_object_bind_to_vm(struct drm_i915_gem_object
*obj
,
3099 struct i915_address_space
*vm
,
3101 bool map_and_fenceable
,
3104 struct drm_device
*dev
= obj
->base
.dev
;
3105 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3106 u32 size
, fence_size
, fence_alignment
, unfenced_alignment
;
3107 bool mappable
, fenceable
;
3109 map_and_fenceable
? dev_priv
->gtt
.mappable_end
: vm
->total
;
3110 struct i915_vma
*vma
;
3113 if (WARN_ON(!list_empty(&obj
->vma_list
)))
3116 fence_size
= i915_gem_get_gtt_size(dev
,
3119 fence_alignment
= i915_gem_get_gtt_alignment(dev
,
3121 obj
->tiling_mode
, true);
3122 unfenced_alignment
=
3123 i915_gem_get_gtt_alignment(dev
,
3125 obj
->tiling_mode
, false);
3128 alignment
= map_and_fenceable
? fence_alignment
:
3130 if (map_and_fenceable
&& alignment
& (fence_alignment
- 1)) {
3131 DRM_ERROR("Invalid object alignment requested %u\n", alignment
);
3135 size
= map_and_fenceable
? fence_size
: obj
->base
.size
;
3137 /* If the object is bigger than the entire aperture, reject it early
3138 * before evicting everything in a vain attempt to find space.
3140 if (obj
->base
.size
> gtt_max
) {
3141 DRM_ERROR("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%zu\n",
3143 map_and_fenceable
? "mappable" : "total",
3148 ret
= i915_gem_object_get_pages(obj
);
3152 i915_gem_object_pin_pages(obj
);
3154 /* FIXME: For now we only ever use 1 VMA per object */
3155 BUG_ON(!i915_is_ggtt(vm
));
3156 WARN_ON(!list_empty(&obj
->vma_list
));
3158 vma
= i915_gem_vma_create(obj
, vm
);
3165 ret
= drm_mm_insert_node_in_range_generic(&vm
->mm
, &vma
->node
,
3167 obj
->cache_level
, 0, gtt_max
);
3169 ret
= i915_gem_evict_something(dev
, vm
, size
, alignment
,
3178 if (WARN_ON(!i915_gem_valid_gtt_space(dev
, &vma
->node
,
3179 obj
->cache_level
))) {
3181 goto err_remove_node
;
3184 ret
= i915_gem_gtt_prepare_object(obj
);
3186 goto err_remove_node
;
3188 list_move_tail(&obj
->global_list
, &dev_priv
->mm
.bound_list
);
3189 list_add_tail(&obj
->mm_list
, &vm
->inactive_list
);
3191 /* Keep GGTT vmas first to make debug easier */
3192 if (i915_is_ggtt(vm
))
3193 list_add(&vma
->vma_link
, &obj
->vma_list
);
3195 list_add_tail(&vma
->vma_link
, &obj
->vma_list
);
3199 i915_gem_obj_ggtt_size(obj
) == fence_size
&&
3200 (i915_gem_obj_ggtt_offset(obj
) & (fence_alignment
- 1)) == 0;
3204 vma
->node
.start
+ obj
->base
.size
<= dev_priv
->gtt
.mappable_end
;
3206 obj
->map_and_fenceable
= mappable
&& fenceable
;
3208 trace_i915_vma_bind(vma
, map_and_fenceable
);
3209 i915_gem_verify_gtt(dev
);
3213 drm_mm_remove_node(&vma
->node
);
3215 i915_gem_vma_destroy(vma
);
3217 i915_gem_object_unpin_pages(obj
);
3222 i915_gem_clflush_object(struct drm_i915_gem_object
*obj
)
3224 /* If we don't have a page list set up, then we're not pinned
3225 * to GPU, and we can ignore the cache flush because it'll happen
3226 * again at bind time.
3228 if (obj
->pages
== NULL
)
3232 * Stolen memory is always coherent with the GPU as it is explicitly
3233 * marked as wc by the system, or the system is cache-coherent.
3238 /* If the GPU is snooping the contents of the CPU cache,
3239 * we do not need to manually clear the CPU cache lines. However,
3240 * the caches are only snooped when the render cache is
3241 * flushed/invalidated. As we always have to emit invalidations
3242 * and flushes when moving into and out of the RENDER domain, correct
3243 * snooping behaviour occurs naturally as the result of our domain
3246 if (obj
->cache_level
!= I915_CACHE_NONE
)
3249 trace_i915_gem_object_clflush(obj
);
3251 drm_clflush_sg(obj
->pages
);
3254 /** Flushes the GTT write domain for the object if it's dirty. */
3256 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
)
3258 uint32_t old_write_domain
;
3260 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_GTT
)
3263 /* No actual flushing is required for the GTT write domain. Writes
3264 * to it immediately go to main memory as far as we know, so there's
3265 * no chipset flush. It also doesn't land in render cache.
3267 * However, we do have to enforce the order so that all writes through
3268 * the GTT land before any writes to the device, such as updates to
3273 old_write_domain
= obj
->base
.write_domain
;
3274 obj
->base
.write_domain
= 0;
3276 trace_i915_gem_object_change_domain(obj
,
3277 obj
->base
.read_domains
,
3281 /** Flushes the CPU write domain for the object if it's dirty. */
3283 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
)
3285 uint32_t old_write_domain
;
3287 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
)
3290 i915_gem_clflush_object(obj
);
3291 i915_gem_chipset_flush(obj
->base
.dev
);
3292 old_write_domain
= obj
->base
.write_domain
;
3293 obj
->base
.write_domain
= 0;
3295 trace_i915_gem_object_change_domain(obj
,
3296 obj
->base
.read_domains
,
3301 * Moves a single object to the GTT read, and possibly write domain.
3303 * This function returns when the move is complete, including waiting on
3307 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
, bool write
)
3309 drm_i915_private_t
*dev_priv
= obj
->base
.dev
->dev_private
;
3310 uint32_t old_write_domain
, old_read_domains
;
3313 /* Not valid to be called on unbound objects. */
3314 if (!i915_gem_obj_bound_any(obj
))
3317 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_GTT
)
3320 ret
= i915_gem_object_wait_rendering(obj
, !write
);
3324 i915_gem_object_flush_cpu_write_domain(obj
);
3326 /* Serialise direct access to this object with the barriers for
3327 * coherent writes from the GPU, by effectively invalidating the
3328 * GTT domain upon first access.
3330 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
) == 0)
3333 old_write_domain
= obj
->base
.write_domain
;
3334 old_read_domains
= obj
->base
.read_domains
;
3336 /* It should now be out of any other write domains, and we can update
3337 * the domain values for our changes.
3339 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
3340 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
3342 obj
->base
.read_domains
= I915_GEM_DOMAIN_GTT
;
3343 obj
->base
.write_domain
= I915_GEM_DOMAIN_GTT
;
3347 trace_i915_gem_object_change_domain(obj
,
3351 /* And bump the LRU for this access */
3352 if (i915_gem_object_is_inactive(obj
))
3353 list_move_tail(&obj
->mm_list
,
3354 &dev_priv
->gtt
.base
.inactive_list
);
3359 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
3360 enum i915_cache_level cache_level
)
3362 struct drm_device
*dev
= obj
->base
.dev
;
3363 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3364 struct i915_vma
*vma
;
3367 if (obj
->cache_level
== cache_level
)
3370 if (obj
->pin_count
) {
3371 DRM_DEBUG("can not change the cache level of pinned objects\n");
3375 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
) {
3376 if (!i915_gem_valid_gtt_space(dev
, &vma
->node
, cache_level
)) {
3377 ret
= i915_vma_unbind(vma
);
3385 if (i915_gem_obj_bound_any(obj
)) {
3386 ret
= i915_gem_object_finish_gpu(obj
);
3390 i915_gem_object_finish_gtt(obj
);
3392 /* Before SandyBridge, you could not use tiling or fence
3393 * registers with snooped memory, so relinquish any fences
3394 * currently pointing to our region in the aperture.
3396 if (INTEL_INFO(dev
)->gen
< 6) {
3397 ret
= i915_gem_object_put_fence(obj
);
3402 if (obj
->has_global_gtt_mapping
)
3403 i915_gem_gtt_bind_object(obj
, cache_level
);
3404 if (obj
->has_aliasing_ppgtt_mapping
)
3405 i915_ppgtt_bind_object(dev_priv
->mm
.aliasing_ppgtt
,
3409 if (cache_level
== I915_CACHE_NONE
) {
3410 u32 old_read_domains
, old_write_domain
;
3412 /* If we're coming from LLC cached, then we haven't
3413 * actually been tracking whether the data is in the
3414 * CPU cache or not, since we only allow one bit set
3415 * in obj->write_domain and have been skipping the clflushes.
3416 * Just set it to the CPU cache for now.
3418 WARN_ON(obj
->base
.write_domain
& ~I915_GEM_DOMAIN_CPU
);
3419 WARN_ON(obj
->base
.read_domains
& ~I915_GEM_DOMAIN_CPU
);
3421 old_read_domains
= obj
->base
.read_domains
;
3422 old_write_domain
= obj
->base
.write_domain
;
3424 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
3425 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
3427 trace_i915_gem_object_change_domain(obj
,
3432 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
3433 vma
->node
.color
= cache_level
;
3434 obj
->cache_level
= cache_level
;
3435 i915_gem_verify_gtt(dev
);
3439 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
3440 struct drm_file
*file
)
3442 struct drm_i915_gem_caching
*args
= data
;
3443 struct drm_i915_gem_object
*obj
;
3446 ret
= i915_mutex_lock_interruptible(dev
);
3450 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3451 if (&obj
->base
== NULL
) {
3456 args
->caching
= obj
->cache_level
!= I915_CACHE_NONE
;
3458 drm_gem_object_unreference(&obj
->base
);
3460 mutex_unlock(&dev
->struct_mutex
);
3464 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
3465 struct drm_file
*file
)
3467 struct drm_i915_gem_caching
*args
= data
;
3468 struct drm_i915_gem_object
*obj
;
3469 enum i915_cache_level level
;
3472 switch (args
->caching
) {
3473 case I915_CACHING_NONE
:
3474 level
= I915_CACHE_NONE
;
3476 case I915_CACHING_CACHED
:
3477 level
= I915_CACHE_LLC
;
3483 ret
= i915_mutex_lock_interruptible(dev
);
3487 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3488 if (&obj
->base
== NULL
) {
3493 ret
= i915_gem_object_set_cache_level(obj
, level
);
3495 drm_gem_object_unreference(&obj
->base
);
3497 mutex_unlock(&dev
->struct_mutex
);
3502 * Prepare buffer for display plane (scanout, cursors, etc).
3503 * Can be called from an uninterruptible phase (modesetting) and allows
3504 * any flushes to be pipelined (for pageflips).
3507 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
3509 struct intel_ring_buffer
*pipelined
)
3511 u32 old_read_domains
, old_write_domain
;
3514 if (pipelined
!= obj
->ring
) {
3515 ret
= i915_gem_object_sync(obj
, pipelined
);
3520 /* The display engine is not coherent with the LLC cache on gen6. As
3521 * a result, we make sure that the pinning that is about to occur is
3522 * done with uncached PTEs. This is lowest common denominator for all
3525 * However for gen6+, we could do better by using the GFDT bit instead
3526 * of uncaching, which would allow us to flush all the LLC-cached data
3527 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3529 ret
= i915_gem_object_set_cache_level(obj
, I915_CACHE_NONE
);
3533 /* As the user may map the buffer once pinned in the display plane
3534 * (e.g. libkms for the bootup splash), we have to ensure that we
3535 * always use map_and_fenceable for all scanout buffers.
3537 ret
= i915_gem_obj_ggtt_pin(obj
, alignment
, true, false);
3541 i915_gem_object_flush_cpu_write_domain(obj
);
3543 old_write_domain
= obj
->base
.write_domain
;
3544 old_read_domains
= obj
->base
.read_domains
;
3546 /* It should now be out of any other write domains, and we can update
3547 * the domain values for our changes.
3549 obj
->base
.write_domain
= 0;
3550 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
3552 trace_i915_gem_object_change_domain(obj
,
3560 i915_gem_object_finish_gpu(struct drm_i915_gem_object
*obj
)
3564 if ((obj
->base
.read_domains
& I915_GEM_GPU_DOMAINS
) == 0)
3567 ret
= i915_gem_object_wait_rendering(obj
, false);
3571 /* Ensure that we invalidate the GPU's caches and TLBs. */
3572 obj
->base
.read_domains
&= ~I915_GEM_GPU_DOMAINS
;
3577 * Moves a single object to the CPU read, and possibly write domain.
3579 * This function returns when the move is complete, including waiting on
3583 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
)
3585 uint32_t old_write_domain
, old_read_domains
;
3588 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_CPU
)
3591 ret
= i915_gem_object_wait_rendering(obj
, !write
);
3595 i915_gem_object_flush_gtt_write_domain(obj
);
3597 old_write_domain
= obj
->base
.write_domain
;
3598 old_read_domains
= obj
->base
.read_domains
;
3600 /* Flush the CPU cache if it's still invalid. */
3601 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) == 0) {
3602 i915_gem_clflush_object(obj
);
3604 obj
->base
.read_domains
|= I915_GEM_DOMAIN_CPU
;
3607 /* It should now be out of any other write domains, and we can update
3608 * the domain values for our changes.
3610 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
3612 /* If we're writing through the CPU, then the GPU read domains will
3613 * need to be invalidated at next use.
3616 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
3617 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
3620 trace_i915_gem_object_change_domain(obj
,
3627 /* Throttle our rendering by waiting until the ring has completed our requests
3628 * emitted over 20 msec ago.
3630 * Note that if we were to use the current jiffies each time around the loop,
3631 * we wouldn't escape the function with any frames outstanding if the time to
3632 * render a frame was over 20ms.
3634 * This should get us reasonable parallelism between CPU and GPU but also
3635 * relatively low latency when blocking on a particular request to finish.
3638 i915_gem_ring_throttle(struct drm_device
*dev
, struct drm_file
*file
)
3640 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3641 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
3642 unsigned long recent_enough
= jiffies
- msecs_to_jiffies(20);
3643 struct drm_i915_gem_request
*request
;
3644 struct intel_ring_buffer
*ring
= NULL
;
3645 unsigned reset_counter
;
3649 ret
= i915_gem_wait_for_error(&dev_priv
->gpu_error
);
3653 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, false);
3657 spin_lock(&file_priv
->mm
.lock
);
3658 list_for_each_entry(request
, &file_priv
->mm
.request_list
, client_list
) {
3659 if (time_after_eq(request
->emitted_jiffies
, recent_enough
))
3662 ring
= request
->ring
;
3663 seqno
= request
->seqno
;
3665 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
3666 spin_unlock(&file_priv
->mm
.lock
);
3671 ret
= __wait_seqno(ring
, seqno
, reset_counter
, true, NULL
);
3673 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, 0);
3679 i915_gem_object_pin(struct drm_i915_gem_object
*obj
,
3680 struct i915_address_space
*vm
,
3682 bool map_and_fenceable
,
3685 struct i915_vma
*vma
;
3688 if (WARN_ON(obj
->pin_count
== DRM_I915_GEM_OBJECT_MAX_PIN_COUNT
))
3691 WARN_ON(map_and_fenceable
&& !i915_is_ggtt(vm
));
3693 vma
= i915_gem_obj_to_vma(obj
, vm
);
3697 vma
->node
.start
& (alignment
- 1)) ||
3698 (map_and_fenceable
&& !obj
->map_and_fenceable
)) {
3699 WARN(obj
->pin_count
,
3700 "bo is already pinned with incorrect alignment:"
3701 " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d,"
3702 " obj->map_and_fenceable=%d\n",
3703 i915_gem_obj_offset(obj
, vm
), alignment
,
3705 obj
->map_and_fenceable
);
3706 ret
= i915_vma_unbind(vma
);
3712 if (!i915_gem_obj_bound(obj
, vm
)) {
3713 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
3715 ret
= i915_gem_object_bind_to_vm(obj
, vm
, alignment
,
3721 if (!dev_priv
->mm
.aliasing_ppgtt
)
3722 i915_gem_gtt_bind_object(obj
, obj
->cache_level
);
3725 if (!obj
->has_global_gtt_mapping
&& map_and_fenceable
)
3726 i915_gem_gtt_bind_object(obj
, obj
->cache_level
);
3729 obj
->pin_mappable
|= map_and_fenceable
;
3735 i915_gem_object_unpin(struct drm_i915_gem_object
*obj
)
3737 BUG_ON(obj
->pin_count
== 0);
3738 BUG_ON(!i915_gem_obj_bound_any(obj
));
3740 if (--obj
->pin_count
== 0)
3741 obj
->pin_mappable
= false;
3745 i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
3746 struct drm_file
*file
)
3748 struct drm_i915_gem_pin
*args
= data
;
3749 struct drm_i915_gem_object
*obj
;
3752 ret
= i915_mutex_lock_interruptible(dev
);
3756 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3757 if (&obj
->base
== NULL
) {
3762 if (obj
->madv
!= I915_MADV_WILLNEED
) {
3763 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3768 if (obj
->pin_filp
!= NULL
&& obj
->pin_filp
!= file
) {
3769 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3775 if (obj
->user_pin_count
== 0) {
3776 ret
= i915_gem_obj_ggtt_pin(obj
, args
->alignment
, true, false);
3781 obj
->user_pin_count
++;
3782 obj
->pin_filp
= file
;
3784 /* XXX - flush the CPU caches for pinned objects
3785 * as the X server doesn't manage domains yet
3787 i915_gem_object_flush_cpu_write_domain(obj
);
3788 args
->offset
= i915_gem_obj_ggtt_offset(obj
);
3790 drm_gem_object_unreference(&obj
->base
);
3792 mutex_unlock(&dev
->struct_mutex
);
3797 i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
3798 struct drm_file
*file
)
3800 struct drm_i915_gem_pin
*args
= data
;
3801 struct drm_i915_gem_object
*obj
;
3804 ret
= i915_mutex_lock_interruptible(dev
);
3808 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3809 if (&obj
->base
== NULL
) {
3814 if (obj
->pin_filp
!= file
) {
3815 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3820 obj
->user_pin_count
--;
3821 if (obj
->user_pin_count
== 0) {
3822 obj
->pin_filp
= NULL
;
3823 i915_gem_object_unpin(obj
);
3827 drm_gem_object_unreference(&obj
->base
);
3829 mutex_unlock(&dev
->struct_mutex
);
3834 i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
3835 struct drm_file
*file
)
3837 struct drm_i915_gem_busy
*args
= data
;
3838 struct drm_i915_gem_object
*obj
;
3841 ret
= i915_mutex_lock_interruptible(dev
);
3845 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3846 if (&obj
->base
== NULL
) {
3851 /* Count all active objects as busy, even if they are currently not used
3852 * by the gpu. Users of this interface expect objects to eventually
3853 * become non-busy without any further actions, therefore emit any
3854 * necessary flushes here.
3856 ret
= i915_gem_object_flush_active(obj
);
3858 args
->busy
= obj
->active
;
3860 BUILD_BUG_ON(I915_NUM_RINGS
> 16);
3861 args
->busy
|= intel_ring_flag(obj
->ring
) << 16;
3864 drm_gem_object_unreference(&obj
->base
);
3866 mutex_unlock(&dev
->struct_mutex
);
3871 i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
3872 struct drm_file
*file_priv
)
3874 return i915_gem_ring_throttle(dev
, file_priv
);
3878 i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
3879 struct drm_file
*file_priv
)
3881 struct drm_i915_gem_madvise
*args
= data
;
3882 struct drm_i915_gem_object
*obj
;
3885 switch (args
->madv
) {
3886 case I915_MADV_DONTNEED
:
3887 case I915_MADV_WILLNEED
:
3893 ret
= i915_mutex_lock_interruptible(dev
);
3897 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file_priv
, args
->handle
));
3898 if (&obj
->base
== NULL
) {
3903 if (obj
->pin_count
) {
3908 if (obj
->madv
!= __I915_MADV_PURGED
)
3909 obj
->madv
= args
->madv
;
3911 /* if the object is no longer attached, discard its backing storage */
3912 if (i915_gem_object_is_purgeable(obj
) && obj
->pages
== NULL
)
3913 i915_gem_object_truncate(obj
);
3915 args
->retained
= obj
->madv
!= __I915_MADV_PURGED
;
3918 drm_gem_object_unreference(&obj
->base
);
3920 mutex_unlock(&dev
->struct_mutex
);
3924 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
3925 const struct drm_i915_gem_object_ops
*ops
)
3927 INIT_LIST_HEAD(&obj
->mm_list
);
3928 INIT_LIST_HEAD(&obj
->global_list
);
3929 INIT_LIST_HEAD(&obj
->ring_list
);
3930 INIT_LIST_HEAD(&obj
->exec_list
);
3931 INIT_LIST_HEAD(&obj
->vma_list
);
3935 obj
->fence_reg
= I915_FENCE_REG_NONE
;
3936 obj
->madv
= I915_MADV_WILLNEED
;
3937 /* Avoid an unnecessary call to unbind on the first bind. */
3938 obj
->map_and_fenceable
= true;
3940 i915_gem_info_add_obj(obj
->base
.dev
->dev_private
, obj
->base
.size
);
3943 static const struct drm_i915_gem_object_ops i915_gem_object_ops
= {
3944 .get_pages
= i915_gem_object_get_pages_gtt
,
3945 .put_pages
= i915_gem_object_put_pages_gtt
,
3948 struct drm_i915_gem_object
*i915_gem_alloc_object(struct drm_device
*dev
,
3951 struct drm_i915_gem_object
*obj
;
3952 struct address_space
*mapping
;
3955 obj
= i915_gem_object_alloc(dev
);
3959 if (drm_gem_object_init(dev
, &obj
->base
, size
) != 0) {
3960 i915_gem_object_free(obj
);
3964 mask
= GFP_HIGHUSER
| __GFP_RECLAIMABLE
;
3965 if (IS_CRESTLINE(dev
) || IS_BROADWATER(dev
)) {
3966 /* 965gm cannot relocate objects above 4GiB. */
3967 mask
&= ~__GFP_HIGHMEM
;
3968 mask
|= __GFP_DMA32
;
3971 mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
3972 mapping_set_gfp_mask(mapping
, mask
);
3974 i915_gem_object_init(obj
, &i915_gem_object_ops
);
3976 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
3977 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
3980 /* On some devices, we can have the GPU use the LLC (the CPU
3981 * cache) for about a 10% performance improvement
3982 * compared to uncached. Graphics requests other than
3983 * display scanout are coherent with the CPU in
3984 * accessing this cache. This means in this mode we
3985 * don't need to clflush on the CPU side, and on the
3986 * GPU side we only need to flush internal caches to
3987 * get data visible to the CPU.
3989 * However, we maintain the display planes as UC, and so
3990 * need to rebind when first used as such.
3992 obj
->cache_level
= I915_CACHE_LLC
;
3994 obj
->cache_level
= I915_CACHE_NONE
;
3996 trace_i915_gem_object_create(obj
);
4001 int i915_gem_init_object(struct drm_gem_object
*obj
)
4008 void i915_gem_free_object(struct drm_gem_object
*gem_obj
)
4010 struct drm_i915_gem_object
*obj
= to_intel_bo(gem_obj
);
4011 struct drm_device
*dev
= obj
->base
.dev
;
4012 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4013 struct i915_vma
*vma
, *next
;
4015 trace_i915_gem_object_destroy(obj
);
4018 i915_gem_detach_phys_object(dev
, obj
);
4021 /* NB: 0 or 1 elements */
4022 WARN_ON(!list_empty(&obj
->vma_list
) &&
4023 !list_is_singular(&obj
->vma_list
));
4024 list_for_each_entry_safe(vma
, next
, &obj
->vma_list
, vma_link
) {
4025 int ret
= i915_vma_unbind(vma
);
4026 if (WARN_ON(ret
== -ERESTARTSYS
)) {
4027 bool was_interruptible
;
4029 was_interruptible
= dev_priv
->mm
.interruptible
;
4030 dev_priv
->mm
.interruptible
= false;
4032 WARN_ON(i915_vma_unbind(vma
));
4034 dev_priv
->mm
.interruptible
= was_interruptible
;
4038 /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
4039 * before progressing. */
4041 i915_gem_object_unpin_pages(obj
);
4043 if (WARN_ON(obj
->pages_pin_count
))
4044 obj
->pages_pin_count
= 0;
4045 i915_gem_object_put_pages(obj
);
4046 i915_gem_object_free_mmap_offset(obj
);
4047 i915_gem_object_release_stolen(obj
);
4051 if (obj
->base
.import_attach
)
4052 drm_prime_gem_destroy(&obj
->base
, NULL
);
4054 drm_gem_object_release(&obj
->base
);
4055 i915_gem_info_remove_obj(dev_priv
, obj
->base
.size
);
4058 i915_gem_object_free(obj
);
4061 struct i915_vma
*i915_gem_vma_create(struct drm_i915_gem_object
*obj
,
4062 struct i915_address_space
*vm
)
4064 struct i915_vma
*vma
= kzalloc(sizeof(*vma
), GFP_KERNEL
);
4066 return ERR_PTR(-ENOMEM
);
4068 INIT_LIST_HEAD(&vma
->vma_link
);
4075 void i915_gem_vma_destroy(struct i915_vma
*vma
)
4077 WARN_ON(vma
->node
.allocated
);
4082 i915_gem_idle(struct drm_device
*dev
)
4084 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4087 if (dev_priv
->ums
.mm_suspended
) {
4088 mutex_unlock(&dev
->struct_mutex
);
4092 ret
= i915_gpu_idle(dev
);
4094 mutex_unlock(&dev
->struct_mutex
);
4097 i915_gem_retire_requests(dev
);
4099 /* Under UMS, be paranoid and evict. */
4100 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
4101 i915_gem_evict_everything(dev
);
4103 del_timer_sync(&dev_priv
->gpu_error
.hangcheck_timer
);
4105 i915_kernel_lost_context(dev
);
4106 i915_gem_cleanup_ringbuffer(dev
);
4108 /* Cancel the retire work handler, which should be idle now. */
4109 cancel_delayed_work_sync(&dev_priv
->mm
.retire_work
);
4114 void i915_gem_l3_remap(struct drm_device
*dev
)
4116 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4120 if (!HAS_L3_GPU_CACHE(dev
))
4123 if (!dev_priv
->l3_parity
.remap_info
)
4126 misccpctl
= I915_READ(GEN7_MISCCPCTL
);
4127 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
& ~GEN7_DOP_CLOCK_GATE_ENABLE
);
4128 POSTING_READ(GEN7_MISCCPCTL
);
4130 for (i
= 0; i
< GEN7_L3LOG_SIZE
; i
+= 4) {
4131 u32 remap
= I915_READ(GEN7_L3LOG_BASE
+ i
);
4132 if (remap
&& remap
!= dev_priv
->l3_parity
.remap_info
[i
/4])
4133 DRM_DEBUG("0x%x was already programmed to %x\n",
4134 GEN7_L3LOG_BASE
+ i
, remap
);
4135 if (remap
&& !dev_priv
->l3_parity
.remap_info
[i
/4])
4136 DRM_DEBUG_DRIVER("Clearing remapped register\n");
4137 I915_WRITE(GEN7_L3LOG_BASE
+ i
, dev_priv
->l3_parity
.remap_info
[i
/4]);
4140 /* Make sure all the writes land before disabling dop clock gating */
4141 POSTING_READ(GEN7_L3LOG_BASE
);
4143 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
);
4146 void i915_gem_init_swizzling(struct drm_device
*dev
)
4148 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4150 if (INTEL_INFO(dev
)->gen
< 5 ||
4151 dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_NONE
)
4154 I915_WRITE(DISP_ARB_CTL
, I915_READ(DISP_ARB_CTL
) |
4155 DISP_TILE_SURFACE_SWIZZLING
);
4160 I915_WRITE(TILECTL
, I915_READ(TILECTL
) | TILECTL_SWZCTL
);
4162 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB
));
4163 else if (IS_GEN7(dev
))
4164 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB
));
4170 intel_enable_blt(struct drm_device
*dev
)
4175 /* The blitter was dysfunctional on early prototypes */
4176 if (IS_GEN6(dev
) && dev
->pdev
->revision
< 8) {
4177 DRM_INFO("BLT not supported on this pre-production hardware;"
4178 " graphics performance will be degraded.\n");
4185 static int i915_gem_init_rings(struct drm_device
*dev
)
4187 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4190 ret
= intel_init_render_ring_buffer(dev
);
4195 ret
= intel_init_bsd_ring_buffer(dev
);
4197 goto cleanup_render_ring
;
4200 if (intel_enable_blt(dev
)) {
4201 ret
= intel_init_blt_ring_buffer(dev
);
4203 goto cleanup_bsd_ring
;
4206 if (HAS_VEBOX(dev
)) {
4207 ret
= intel_init_vebox_ring_buffer(dev
);
4209 goto cleanup_blt_ring
;
4213 ret
= i915_gem_set_seqno(dev
, ((u32
)~0 - 0x1000));
4215 goto cleanup_vebox_ring
;
4220 intel_cleanup_ring_buffer(&dev_priv
->ring
[VECS
]);
4222 intel_cleanup_ring_buffer(&dev_priv
->ring
[BCS
]);
4224 intel_cleanup_ring_buffer(&dev_priv
->ring
[VCS
]);
4225 cleanup_render_ring
:
4226 intel_cleanup_ring_buffer(&dev_priv
->ring
[RCS
]);
4232 i915_gem_init_hw(struct drm_device
*dev
)
4234 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4237 if (INTEL_INFO(dev
)->gen
< 6 && !intel_enable_gtt())
4240 if (dev_priv
->ellc_size
)
4241 I915_WRITE(HSW_IDICR
, I915_READ(HSW_IDICR
) | IDIHASHMSK(0xf));
4243 if (HAS_PCH_NOP(dev
)) {
4244 u32 temp
= I915_READ(GEN7_MSG_CTL
);
4245 temp
&= ~(WAIT_FOR_PCH_FLR_ACK
| WAIT_FOR_PCH_RESET_ACK
);
4246 I915_WRITE(GEN7_MSG_CTL
, temp
);
4249 i915_gem_l3_remap(dev
);
4251 i915_gem_init_swizzling(dev
);
4253 ret
= i915_gem_init_rings(dev
);
4258 * XXX: There was some w/a described somewhere suggesting loading
4259 * contexts before PPGTT.
4261 i915_gem_context_init(dev
);
4262 if (dev_priv
->mm
.aliasing_ppgtt
) {
4263 ret
= dev_priv
->mm
.aliasing_ppgtt
->enable(dev
);
4265 i915_gem_cleanup_aliasing_ppgtt(dev
);
4266 DRM_INFO("PPGTT enable failed. This is not fatal, but unexpected\n");
4273 int i915_gem_init(struct drm_device
*dev
)
4275 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4278 mutex_lock(&dev
->struct_mutex
);
4280 if (IS_VALLEYVIEW(dev
)) {
4281 /* VLVA0 (potential hack), BIOS isn't actually waking us */
4282 I915_WRITE(VLV_GTLC_WAKE_CTRL
, 1);
4283 if (wait_for((I915_READ(VLV_GTLC_PW_STATUS
) & 1) == 1, 10))
4284 DRM_DEBUG_DRIVER("allow wake ack timed out\n");
4287 i915_gem_init_global_gtt(dev
);
4289 ret
= i915_gem_init_hw(dev
);
4290 mutex_unlock(&dev
->struct_mutex
);
4292 i915_gem_cleanup_aliasing_ppgtt(dev
);
4296 /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */
4297 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
4298 dev_priv
->dri1
.allow_batchbuffer
= 1;
4303 i915_gem_cleanup_ringbuffer(struct drm_device
*dev
)
4305 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4306 struct intel_ring_buffer
*ring
;
4309 for_each_ring(ring
, dev_priv
, i
)
4310 intel_cleanup_ring_buffer(ring
);
4314 i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
4315 struct drm_file
*file_priv
)
4317 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4320 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4323 if (i915_reset_in_progress(&dev_priv
->gpu_error
)) {
4324 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4325 atomic_set(&dev_priv
->gpu_error
.reset_counter
, 0);
4328 mutex_lock(&dev
->struct_mutex
);
4329 dev_priv
->ums
.mm_suspended
= 0;
4331 ret
= i915_gem_init_hw(dev
);
4333 mutex_unlock(&dev
->struct_mutex
);
4337 BUG_ON(!list_empty(&dev_priv
->gtt
.base
.active_list
));
4338 mutex_unlock(&dev
->struct_mutex
);
4340 ret
= drm_irq_install(dev
);
4342 goto cleanup_ringbuffer
;
4347 mutex_lock(&dev
->struct_mutex
);
4348 i915_gem_cleanup_ringbuffer(dev
);
4349 dev_priv
->ums
.mm_suspended
= 1;
4350 mutex_unlock(&dev
->struct_mutex
);
4356 i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
4357 struct drm_file
*file_priv
)
4359 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4362 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4365 drm_irq_uninstall(dev
);
4367 mutex_lock(&dev
->struct_mutex
);
4368 ret
= i915_gem_idle(dev
);
4370 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4371 * We need to replace this with a semaphore, or something.
4372 * And not confound ums.mm_suspended!
4375 dev_priv
->ums
.mm_suspended
= 1;
4376 mutex_unlock(&dev
->struct_mutex
);
4382 i915_gem_lastclose(struct drm_device
*dev
)
4386 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4389 mutex_lock(&dev
->struct_mutex
);
4390 ret
= i915_gem_idle(dev
);
4392 DRM_ERROR("failed to idle hardware: %d\n", ret
);
4393 mutex_unlock(&dev
->struct_mutex
);
4397 init_ring_lists(struct intel_ring_buffer
*ring
)
4399 INIT_LIST_HEAD(&ring
->active_list
);
4400 INIT_LIST_HEAD(&ring
->request_list
);
4403 static void i915_init_vm(struct drm_i915_private
*dev_priv
,
4404 struct i915_address_space
*vm
)
4406 vm
->dev
= dev_priv
->dev
;
4407 INIT_LIST_HEAD(&vm
->active_list
);
4408 INIT_LIST_HEAD(&vm
->inactive_list
);
4409 INIT_LIST_HEAD(&vm
->global_link
);
4410 list_add(&vm
->global_link
, &dev_priv
->vm_list
);
4414 i915_gem_load(struct drm_device
*dev
)
4416 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4420 kmem_cache_create("i915_gem_object",
4421 sizeof(struct drm_i915_gem_object
), 0,
4425 INIT_LIST_HEAD(&dev_priv
->vm_list
);
4426 i915_init_vm(dev_priv
, &dev_priv
->gtt
.base
);
4428 INIT_LIST_HEAD(&dev_priv
->mm
.unbound_list
);
4429 INIT_LIST_HEAD(&dev_priv
->mm
.bound_list
);
4430 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
4431 for (i
= 0; i
< I915_NUM_RINGS
; i
++)
4432 init_ring_lists(&dev_priv
->ring
[i
]);
4433 for (i
= 0; i
< I915_MAX_NUM_FENCES
; i
++)
4434 INIT_LIST_HEAD(&dev_priv
->fence_regs
[i
].lru_list
);
4435 INIT_DELAYED_WORK(&dev_priv
->mm
.retire_work
,
4436 i915_gem_retire_work_handler
);
4437 init_waitqueue_head(&dev_priv
->gpu_error
.reset_queue
);
4439 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4441 I915_WRITE(MI_ARB_STATE
,
4442 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE
));
4445 dev_priv
->relative_constants_mode
= I915_EXEC_CONSTANTS_REL_GENERAL
;
4447 /* Old X drivers will take 0-2 for front, back, depth buffers */
4448 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
4449 dev_priv
->fence_reg_start
= 3;
4451 if (INTEL_INFO(dev
)->gen
>= 7 && !IS_VALLEYVIEW(dev
))
4452 dev_priv
->num_fence_regs
= 32;
4453 else if (INTEL_INFO(dev
)->gen
>= 4 || IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
4454 dev_priv
->num_fence_regs
= 16;
4456 dev_priv
->num_fence_regs
= 8;
4458 /* Initialize fence registers to zero */
4459 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
4460 i915_gem_restore_fences(dev
);
4462 i915_gem_detect_bit_6_swizzle(dev
);
4463 init_waitqueue_head(&dev_priv
->pending_flip_queue
);
4465 dev_priv
->mm
.interruptible
= true;
4467 dev_priv
->mm
.inactive_shrinker
.shrink
= i915_gem_inactive_shrink
;
4468 dev_priv
->mm
.inactive_shrinker
.seeks
= DEFAULT_SEEKS
;
4469 register_shrinker(&dev_priv
->mm
.inactive_shrinker
);
4473 * Create a physically contiguous memory object for this object
4474 * e.g. for cursor + overlay regs
4476 static int i915_gem_init_phys_object(struct drm_device
*dev
,
4477 int id
, int size
, int align
)
4479 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4480 struct drm_i915_gem_phys_object
*phys_obj
;
4483 if (dev_priv
->mm
.phys_objs
[id
- 1] || !size
)
4486 phys_obj
= kzalloc(sizeof(struct drm_i915_gem_phys_object
), GFP_KERNEL
);
4492 phys_obj
->handle
= drm_pci_alloc(dev
, size
, align
);
4493 if (!phys_obj
->handle
) {
4498 set_memory_wc((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
4501 dev_priv
->mm
.phys_objs
[id
- 1] = phys_obj
;
4509 static void i915_gem_free_phys_object(struct drm_device
*dev
, int id
)
4511 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4512 struct drm_i915_gem_phys_object
*phys_obj
;
4514 if (!dev_priv
->mm
.phys_objs
[id
- 1])
4517 phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
4518 if (phys_obj
->cur_obj
) {
4519 i915_gem_detach_phys_object(dev
, phys_obj
->cur_obj
);
4523 set_memory_wb((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
4525 drm_pci_free(dev
, phys_obj
->handle
);
4527 dev_priv
->mm
.phys_objs
[id
- 1] = NULL
;
4530 void i915_gem_free_all_phys_object(struct drm_device
*dev
)
4534 for (i
= I915_GEM_PHYS_CURSOR_0
; i
<= I915_MAX_PHYS_OBJECT
; i
++)
4535 i915_gem_free_phys_object(dev
, i
);
4538 void i915_gem_detach_phys_object(struct drm_device
*dev
,
4539 struct drm_i915_gem_object
*obj
)
4541 struct address_space
*mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
4548 vaddr
= obj
->phys_obj
->handle
->vaddr
;
4550 page_count
= obj
->base
.size
/ PAGE_SIZE
;
4551 for (i
= 0; i
< page_count
; i
++) {
4552 struct page
*page
= shmem_read_mapping_page(mapping
, i
);
4553 if (!IS_ERR(page
)) {
4554 char *dst
= kmap_atomic(page
);
4555 memcpy(dst
, vaddr
+ i
*PAGE_SIZE
, PAGE_SIZE
);
4558 drm_clflush_pages(&page
, 1);
4560 set_page_dirty(page
);
4561 mark_page_accessed(page
);
4562 page_cache_release(page
);
4565 i915_gem_chipset_flush(dev
);
4567 obj
->phys_obj
->cur_obj
= NULL
;
4568 obj
->phys_obj
= NULL
;
4572 i915_gem_attach_phys_object(struct drm_device
*dev
,
4573 struct drm_i915_gem_object
*obj
,
4577 struct address_space
*mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
4578 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4583 if (id
> I915_MAX_PHYS_OBJECT
)
4586 if (obj
->phys_obj
) {
4587 if (obj
->phys_obj
->id
== id
)
4589 i915_gem_detach_phys_object(dev
, obj
);
4592 /* create a new object */
4593 if (!dev_priv
->mm
.phys_objs
[id
- 1]) {
4594 ret
= i915_gem_init_phys_object(dev
, id
,
4595 obj
->base
.size
, align
);
4597 DRM_ERROR("failed to init phys object %d size: %zu\n",
4598 id
, obj
->base
.size
);
4603 /* bind to the object */
4604 obj
->phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
4605 obj
->phys_obj
->cur_obj
= obj
;
4607 page_count
= obj
->base
.size
/ PAGE_SIZE
;
4609 for (i
= 0; i
< page_count
; i
++) {
4613 page
= shmem_read_mapping_page(mapping
, i
);
4615 return PTR_ERR(page
);
4617 src
= kmap_atomic(page
);
4618 dst
= obj
->phys_obj
->handle
->vaddr
+ (i
* PAGE_SIZE
);
4619 memcpy(dst
, src
, PAGE_SIZE
);
4622 mark_page_accessed(page
);
4623 page_cache_release(page
);
4630 i915_gem_phys_pwrite(struct drm_device
*dev
,
4631 struct drm_i915_gem_object
*obj
,
4632 struct drm_i915_gem_pwrite
*args
,
4633 struct drm_file
*file_priv
)
4635 void *vaddr
= obj
->phys_obj
->handle
->vaddr
+ args
->offset
;
4636 char __user
*user_data
= to_user_ptr(args
->data_ptr
);
4638 if (__copy_from_user_inatomic_nocache(vaddr
, user_data
, args
->size
)) {
4639 unsigned long unwritten
;
4641 /* The physical object once assigned is fixed for the lifetime
4642 * of the obj, so we can safely drop the lock and continue
4645 mutex_unlock(&dev
->struct_mutex
);
4646 unwritten
= copy_from_user(vaddr
, user_data
, args
->size
);
4647 mutex_lock(&dev
->struct_mutex
);
4652 i915_gem_chipset_flush(dev
);
4656 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
)
4658 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
4660 /* Clean up our request list when the client is going away, so that
4661 * later retire_requests won't dereference our soon-to-be-gone
4664 spin_lock(&file_priv
->mm
.lock
);
4665 while (!list_empty(&file_priv
->mm
.request_list
)) {
4666 struct drm_i915_gem_request
*request
;
4668 request
= list_first_entry(&file_priv
->mm
.request_list
,
4669 struct drm_i915_gem_request
,
4671 list_del(&request
->client_list
);
4672 request
->file_priv
= NULL
;
4674 spin_unlock(&file_priv
->mm
.lock
);
4677 static bool mutex_is_locked_by(struct mutex
*mutex
, struct task_struct
*task
)
4679 if (!mutex_is_locked(mutex
))
4682 #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES)
4683 return mutex
->owner
== task
;
4685 /* Since UP may be pre-empted, we cannot assume that we own the lock */
4691 i915_gem_inactive_shrink(struct shrinker
*shrinker
, struct shrink_control
*sc
)
4693 struct drm_i915_private
*dev_priv
=
4694 container_of(shrinker
,
4695 struct drm_i915_private
,
4696 mm
.inactive_shrinker
);
4697 struct drm_device
*dev
= dev_priv
->dev
;
4698 struct drm_i915_gem_object
*obj
;
4699 int nr_to_scan
= sc
->nr_to_scan
;
4703 if (!mutex_trylock(&dev
->struct_mutex
)) {
4704 if (!mutex_is_locked_by(&dev
->struct_mutex
, current
))
4707 if (dev_priv
->mm
.shrinker_no_lock_stealing
)
4714 nr_to_scan
-= i915_gem_purge(dev_priv
, nr_to_scan
);
4716 nr_to_scan
-= __i915_gem_shrink(dev_priv
, nr_to_scan
,
4719 i915_gem_shrink_all(dev_priv
);
4723 list_for_each_entry(obj
, &dev_priv
->mm
.unbound_list
, global_list
)
4724 if (obj
->pages_pin_count
== 0)
4725 cnt
+= obj
->base
.size
>> PAGE_SHIFT
;
4727 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
4731 if (obj
->pin_count
== 0 && obj
->pages_pin_count
== 0)
4732 cnt
+= obj
->base
.size
>> PAGE_SHIFT
;
4736 mutex_unlock(&dev
->struct_mutex
);
4740 /* All the new VM stuff */
4741 unsigned long i915_gem_obj_offset(struct drm_i915_gem_object
*o
,
4742 struct i915_address_space
*vm
)
4744 struct drm_i915_private
*dev_priv
= o
->base
.dev
->dev_private
;
4745 struct i915_vma
*vma
;
4747 if (vm
== &dev_priv
->mm
.aliasing_ppgtt
->base
)
4748 vm
= &dev_priv
->gtt
.base
;
4750 BUG_ON(list_empty(&o
->vma_list
));
4751 list_for_each_entry(vma
, &o
->vma_list
, vma_link
) {
4753 return vma
->node
.start
;
4759 bool i915_gem_obj_bound(struct drm_i915_gem_object
*o
,
4760 struct i915_address_space
*vm
)
4762 struct i915_vma
*vma
;
4764 list_for_each_entry(vma
, &o
->vma_list
, vma_link
)
4771 bool i915_gem_obj_bound_any(struct drm_i915_gem_object
*o
)
4773 struct drm_i915_private
*dev_priv
= o
->base
.dev
->dev_private
;
4774 struct i915_address_space
*vm
;
4776 list_for_each_entry(vm
, &dev_priv
->vm_list
, global_link
)
4777 if (i915_gem_obj_bound(o
, vm
))
4783 unsigned long i915_gem_obj_size(struct drm_i915_gem_object
*o
,
4784 struct i915_address_space
*vm
)
4786 struct drm_i915_private
*dev_priv
= o
->base
.dev
->dev_private
;
4787 struct i915_vma
*vma
;
4789 if (vm
== &dev_priv
->mm
.aliasing_ppgtt
->base
)
4790 vm
= &dev_priv
->gtt
.base
;
4792 BUG_ON(list_empty(&o
->vma_list
));
4794 list_for_each_entry(vma
, &o
->vma_list
, vma_link
)
4796 return vma
->node
.size
;
4801 struct i915_vma
*i915_gem_obj_to_vma(struct drm_i915_gem_object
*obj
,
4802 struct i915_address_space
*vm
)
4804 struct i915_vma
*vma
;
4805 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)