2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/drm_vma_manager.h>
30 #include <drm/i915_drm.h>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/shmem_fs.h>
35 #include <linux/slab.h>
36 #include <linux/swap.h>
37 #include <linux/pci.h>
38 #include <linux/dma-buf.h>
40 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
);
41 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
,
43 static __must_check
int
44 i915_gem_object_wait_rendering(struct drm_i915_gem_object
*obj
,
47 static void i915_gem_write_fence(struct drm_device
*dev
, int reg
,
48 struct drm_i915_gem_object
*obj
);
49 static void i915_gem_object_update_fence(struct drm_i915_gem_object
*obj
,
50 struct drm_i915_fence_reg
*fence
,
53 static unsigned long i915_gem_inactive_count(struct shrinker
*shrinker
,
54 struct shrink_control
*sc
);
55 static unsigned long i915_gem_inactive_scan(struct shrinker
*shrinker
,
56 struct shrink_control
*sc
);
57 static unsigned long i915_gem_purge(struct drm_i915_private
*dev_priv
, long target
);
58 static unsigned long i915_gem_shrink_all(struct drm_i915_private
*dev_priv
);
59 static void i915_gem_object_truncate(struct drm_i915_gem_object
*obj
);
60 static void i915_gem_retire_requests_ring(struct intel_ring_buffer
*ring
);
62 static bool cpu_cache_is_coherent(struct drm_device
*dev
,
63 enum i915_cache_level level
)
65 return HAS_LLC(dev
) || level
!= I915_CACHE_NONE
;
68 static bool cpu_write_needs_clflush(struct drm_i915_gem_object
*obj
)
70 if (!cpu_cache_is_coherent(obj
->base
.dev
, obj
->cache_level
))
73 return obj
->pin_display
;
76 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object
*obj
)
79 i915_gem_release_mmap(obj
);
81 /* As we do not have an associated fence register, we will force
82 * a tiling change if we ever need to acquire one.
84 obj
->fence_dirty
= false;
85 obj
->fence_reg
= I915_FENCE_REG_NONE
;
88 /* some bookkeeping */
89 static void i915_gem_info_add_obj(struct drm_i915_private
*dev_priv
,
92 spin_lock(&dev_priv
->mm
.object_stat_lock
);
93 dev_priv
->mm
.object_count
++;
94 dev_priv
->mm
.object_memory
+= size
;
95 spin_unlock(&dev_priv
->mm
.object_stat_lock
);
98 static void i915_gem_info_remove_obj(struct drm_i915_private
*dev_priv
,
101 spin_lock(&dev_priv
->mm
.object_stat_lock
);
102 dev_priv
->mm
.object_count
--;
103 dev_priv
->mm
.object_memory
-= size
;
104 spin_unlock(&dev_priv
->mm
.object_stat_lock
);
108 i915_gem_wait_for_error(struct i915_gpu_error
*error
)
112 #define EXIT_COND (!i915_reset_in_progress(error) || \
113 i915_terminally_wedged(error))
118 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
119 * userspace. If it takes that long something really bad is going on and
120 * we should simply try to bail out and fail as gracefully as possible.
122 ret
= wait_event_interruptible_timeout(error
->reset_queue
,
126 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
128 } else if (ret
< 0) {
136 int i915_mutex_lock_interruptible(struct drm_device
*dev
)
138 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
141 ret
= i915_gem_wait_for_error(&dev_priv
->gpu_error
);
145 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
149 WARN_ON(i915_verify_lists(dev
));
154 i915_gem_object_is_inactive(struct drm_i915_gem_object
*obj
)
156 return i915_gem_obj_bound_any(obj
) && !obj
->active
;
160 i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
161 struct drm_file
*file
)
163 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
164 struct drm_i915_gem_init
*args
= data
;
166 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
169 if (args
->gtt_start
>= args
->gtt_end
||
170 (args
->gtt_end
| args
->gtt_start
) & (PAGE_SIZE
- 1))
173 /* GEM with user mode setting was never supported on ilk and later. */
174 if (INTEL_INFO(dev
)->gen
>= 5)
177 mutex_lock(&dev
->struct_mutex
);
178 i915_gem_setup_global_gtt(dev
, args
->gtt_start
, args
->gtt_end
,
180 dev_priv
->gtt
.mappable_end
= args
->gtt_end
;
181 mutex_unlock(&dev
->struct_mutex
);
187 i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
188 struct drm_file
*file
)
190 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
191 struct drm_i915_gem_get_aperture
*args
= data
;
192 struct drm_i915_gem_object
*obj
;
196 mutex_lock(&dev
->struct_mutex
);
197 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
)
198 if (i915_gem_obj_is_pinned(obj
))
199 pinned
+= i915_gem_obj_ggtt_size(obj
);
200 mutex_unlock(&dev
->struct_mutex
);
202 args
->aper_size
= dev_priv
->gtt
.base
.total
;
203 args
->aper_available_size
= args
->aper_size
- pinned
;
208 static void i915_gem_object_detach_phys(struct drm_i915_gem_object
*obj
)
210 drm_dma_handle_t
*phys
= obj
->phys_handle
;
215 if (obj
->madv
== I915_MADV_WILLNEED
) {
216 struct address_space
*mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
217 char *vaddr
= phys
->vaddr
;
220 for (i
= 0; i
< obj
->base
.size
/ PAGE_SIZE
; i
++) {
221 struct page
*page
= shmem_read_mapping_page(mapping
, i
);
223 char *dst
= kmap_atomic(page
);
224 memcpy(dst
, vaddr
, PAGE_SIZE
);
225 drm_clflush_virt_range(dst
, PAGE_SIZE
);
228 set_page_dirty(page
);
229 mark_page_accessed(page
);
230 page_cache_release(page
);
234 i915_gem_chipset_flush(obj
->base
.dev
);
238 set_memory_wb((unsigned long)phys
->vaddr
, phys
->size
/ PAGE_SIZE
);
240 drm_pci_free(obj
->base
.dev
, phys
);
241 obj
->phys_handle
= NULL
;
245 i915_gem_object_attach_phys(struct drm_i915_gem_object
*obj
,
248 drm_dma_handle_t
*phys
;
249 struct address_space
*mapping
;
253 if (obj
->phys_handle
) {
254 if ((unsigned long)obj
->phys_handle
->vaddr
& (align
-1))
260 if (obj
->madv
!= I915_MADV_WILLNEED
)
263 if (obj
->base
.filp
== NULL
)
266 /* create a new object */
267 phys
= drm_pci_alloc(obj
->base
.dev
, obj
->base
.size
, align
);
273 set_memory_wc((unsigned long)vaddr
, phys
->size
/ PAGE_SIZE
);
275 mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
276 for (i
= 0; i
< obj
->base
.size
/ PAGE_SIZE
; i
++) {
280 page
= shmem_read_mapping_page(mapping
, i
);
283 set_memory_wb((unsigned long)phys
->vaddr
, phys
->size
/ PAGE_SIZE
);
285 drm_pci_free(obj
->base
.dev
, phys
);
286 return PTR_ERR(page
);
289 src
= kmap_atomic(page
);
290 memcpy(vaddr
, src
, PAGE_SIZE
);
293 mark_page_accessed(page
);
294 page_cache_release(page
);
299 obj
->phys_handle
= phys
;
304 i915_gem_phys_pwrite(struct drm_i915_gem_object
*obj
,
305 struct drm_i915_gem_pwrite
*args
,
306 struct drm_file
*file_priv
)
308 struct drm_device
*dev
= obj
->base
.dev
;
309 void *vaddr
= obj
->phys_handle
->vaddr
+ args
->offset
;
310 char __user
*user_data
= to_user_ptr(args
->data_ptr
);
312 if (__copy_from_user_inatomic_nocache(vaddr
, user_data
, args
->size
)) {
313 unsigned long unwritten
;
315 /* The physical object once assigned is fixed for the lifetime
316 * of the obj, so we can safely drop the lock and continue
319 mutex_unlock(&dev
->struct_mutex
);
320 unwritten
= copy_from_user(vaddr
, user_data
, args
->size
);
321 mutex_lock(&dev
->struct_mutex
);
326 i915_gem_chipset_flush(dev
);
330 void *i915_gem_object_alloc(struct drm_device
*dev
)
332 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
333 return kmem_cache_zalloc(dev_priv
->slab
, GFP_KERNEL
);
336 void i915_gem_object_free(struct drm_i915_gem_object
*obj
)
338 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
339 kmem_cache_free(dev_priv
->slab
, obj
);
343 i915_gem_create(struct drm_file
*file
,
344 struct drm_device
*dev
,
348 struct drm_i915_gem_object
*obj
;
352 size
= roundup(size
, PAGE_SIZE
);
356 /* Allocate the new object */
357 obj
= i915_gem_alloc_object(dev
, size
);
361 ret
= drm_gem_handle_create(file
, &obj
->base
, &handle
);
362 /* drop reference from allocate - handle holds it now */
363 drm_gem_object_unreference_unlocked(&obj
->base
);
372 i915_gem_dumb_create(struct drm_file
*file
,
373 struct drm_device
*dev
,
374 struct drm_mode_create_dumb
*args
)
376 /* have to work out size/pitch and return them */
377 args
->pitch
= ALIGN(args
->width
* DIV_ROUND_UP(args
->bpp
, 8), 64);
378 args
->size
= args
->pitch
* args
->height
;
379 return i915_gem_create(file
, dev
,
380 args
->size
, &args
->handle
);
384 * Creates a new mm object and returns a handle to it.
387 i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
388 struct drm_file
*file
)
390 struct drm_i915_gem_create
*args
= data
;
392 return i915_gem_create(file
, dev
,
393 args
->size
, &args
->handle
);
397 __copy_to_user_swizzled(char __user
*cpu_vaddr
,
398 const char *gpu_vaddr
, int gpu_offset
,
401 int ret
, cpu_offset
= 0;
404 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
405 int this_length
= min(cacheline_end
- gpu_offset
, length
);
406 int swizzled_gpu_offset
= gpu_offset
^ 64;
408 ret
= __copy_to_user(cpu_vaddr
+ cpu_offset
,
409 gpu_vaddr
+ swizzled_gpu_offset
,
414 cpu_offset
+= this_length
;
415 gpu_offset
+= this_length
;
416 length
-= this_length
;
423 __copy_from_user_swizzled(char *gpu_vaddr
, int gpu_offset
,
424 const char __user
*cpu_vaddr
,
427 int ret
, cpu_offset
= 0;
430 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
431 int this_length
= min(cacheline_end
- gpu_offset
, length
);
432 int swizzled_gpu_offset
= gpu_offset
^ 64;
434 ret
= __copy_from_user(gpu_vaddr
+ swizzled_gpu_offset
,
435 cpu_vaddr
+ cpu_offset
,
440 cpu_offset
+= this_length
;
441 gpu_offset
+= this_length
;
442 length
-= this_length
;
449 * Pins the specified object's pages and synchronizes the object with
450 * GPU accesses. Sets needs_clflush to non-zero if the caller should
451 * flush the object from the CPU cache.
453 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object
*obj
,
463 if (!(obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
)) {
464 /* If we're not in the cpu read domain, set ourself into the gtt
465 * read domain and manually flush cachelines (if required). This
466 * optimizes for the case when the gpu will dirty the data
467 * anyway again before the next pread happens. */
468 *needs_clflush
= !cpu_cache_is_coherent(obj
->base
.dev
,
470 ret
= i915_gem_object_wait_rendering(obj
, true);
475 ret
= i915_gem_object_get_pages(obj
);
479 i915_gem_object_pin_pages(obj
);
484 /* Per-page copy function for the shmem pread fastpath.
485 * Flushes invalid cachelines before reading the target if
486 * needs_clflush is set. */
488 shmem_pread_fast(struct page
*page
, int shmem_page_offset
, int page_length
,
489 char __user
*user_data
,
490 bool page_do_bit17_swizzling
, bool needs_clflush
)
495 if (unlikely(page_do_bit17_swizzling
))
498 vaddr
= kmap_atomic(page
);
500 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
502 ret
= __copy_to_user_inatomic(user_data
,
503 vaddr
+ shmem_page_offset
,
505 kunmap_atomic(vaddr
);
507 return ret
? -EFAULT
: 0;
511 shmem_clflush_swizzled_range(char *addr
, unsigned long length
,
514 if (unlikely(swizzled
)) {
515 unsigned long start
= (unsigned long) addr
;
516 unsigned long end
= (unsigned long) addr
+ length
;
518 /* For swizzling simply ensure that we always flush both
519 * channels. Lame, but simple and it works. Swizzled
520 * pwrite/pread is far from a hotpath - current userspace
521 * doesn't use it at all. */
522 start
= round_down(start
, 128);
523 end
= round_up(end
, 128);
525 drm_clflush_virt_range((void *)start
, end
- start
);
527 drm_clflush_virt_range(addr
, length
);
532 /* Only difference to the fast-path function is that this can handle bit17
533 * and uses non-atomic copy and kmap functions. */
535 shmem_pread_slow(struct page
*page
, int shmem_page_offset
, int page_length
,
536 char __user
*user_data
,
537 bool page_do_bit17_swizzling
, bool needs_clflush
)
544 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
546 page_do_bit17_swizzling
);
548 if (page_do_bit17_swizzling
)
549 ret
= __copy_to_user_swizzled(user_data
,
550 vaddr
, shmem_page_offset
,
553 ret
= __copy_to_user(user_data
,
554 vaddr
+ shmem_page_offset
,
558 return ret
? - EFAULT
: 0;
562 i915_gem_shmem_pread(struct drm_device
*dev
,
563 struct drm_i915_gem_object
*obj
,
564 struct drm_i915_gem_pread
*args
,
565 struct drm_file
*file
)
567 char __user
*user_data
;
570 int shmem_page_offset
, page_length
, ret
= 0;
571 int obj_do_bit17_swizzling
, page_do_bit17_swizzling
;
573 int needs_clflush
= 0;
574 struct sg_page_iter sg_iter
;
576 user_data
= to_user_ptr(args
->data_ptr
);
579 obj_do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
581 ret
= i915_gem_obj_prepare_shmem_read(obj
, &needs_clflush
);
585 offset
= args
->offset
;
587 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
,
588 offset
>> PAGE_SHIFT
) {
589 struct page
*page
= sg_page_iter_page(&sg_iter
);
594 /* Operation in this page
596 * shmem_page_offset = offset within page in shmem file
597 * page_length = bytes to copy for this page
599 shmem_page_offset
= offset_in_page(offset
);
600 page_length
= remain
;
601 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
602 page_length
= PAGE_SIZE
- shmem_page_offset
;
604 page_do_bit17_swizzling
= obj_do_bit17_swizzling
&&
605 (page_to_phys(page
) & (1 << 17)) != 0;
607 ret
= shmem_pread_fast(page
, shmem_page_offset
, page_length
,
608 user_data
, page_do_bit17_swizzling
,
613 mutex_unlock(&dev
->struct_mutex
);
615 if (likely(!i915
.prefault_disable
) && !prefaulted
) {
616 ret
= fault_in_multipages_writeable(user_data
, remain
);
617 /* Userspace is tricking us, but we've already clobbered
618 * its pages with the prefault and promised to write the
619 * data up to the first fault. Hence ignore any errors
620 * and just continue. */
625 ret
= shmem_pread_slow(page
, shmem_page_offset
, page_length
,
626 user_data
, page_do_bit17_swizzling
,
629 mutex_lock(&dev
->struct_mutex
);
635 remain
-= page_length
;
636 user_data
+= page_length
;
637 offset
+= page_length
;
641 i915_gem_object_unpin_pages(obj
);
647 * Reads data from the object referenced by handle.
649 * On error, the contents of *data are undefined.
652 i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
653 struct drm_file
*file
)
655 struct drm_i915_gem_pread
*args
= data
;
656 struct drm_i915_gem_object
*obj
;
662 if (!access_ok(VERIFY_WRITE
,
663 to_user_ptr(args
->data_ptr
),
667 ret
= i915_mutex_lock_interruptible(dev
);
671 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
672 if (&obj
->base
== NULL
) {
677 /* Bounds check source. */
678 if (args
->offset
> obj
->base
.size
||
679 args
->size
> obj
->base
.size
- args
->offset
) {
684 /* prime objects have no backing filp to GEM pread/pwrite
687 if (!obj
->base
.filp
) {
692 trace_i915_gem_object_pread(obj
, args
->offset
, args
->size
);
694 ret
= i915_gem_shmem_pread(dev
, obj
, args
, file
);
697 drm_gem_object_unreference(&obj
->base
);
699 mutex_unlock(&dev
->struct_mutex
);
703 /* This is the fast write path which cannot handle
704 * page faults in the source data
708 fast_user_write(struct io_mapping
*mapping
,
709 loff_t page_base
, int page_offset
,
710 char __user
*user_data
,
713 void __iomem
*vaddr_atomic
;
715 unsigned long unwritten
;
717 vaddr_atomic
= io_mapping_map_atomic_wc(mapping
, page_base
);
718 /* We can use the cpu mem copy function because this is X86. */
719 vaddr
= (void __force
*)vaddr_atomic
+ page_offset
;
720 unwritten
= __copy_from_user_inatomic_nocache(vaddr
,
722 io_mapping_unmap_atomic(vaddr_atomic
);
727 * This is the fast pwrite path, where we copy the data directly from the
728 * user into the GTT, uncached.
731 i915_gem_gtt_pwrite_fast(struct drm_device
*dev
,
732 struct drm_i915_gem_object
*obj
,
733 struct drm_i915_gem_pwrite
*args
,
734 struct drm_file
*file
)
736 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
738 loff_t offset
, page_base
;
739 char __user
*user_data
;
740 int page_offset
, page_length
, ret
;
742 ret
= i915_gem_obj_ggtt_pin(obj
, 0, PIN_MAPPABLE
| PIN_NONBLOCK
);
746 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
750 ret
= i915_gem_object_put_fence(obj
);
754 user_data
= to_user_ptr(args
->data_ptr
);
757 offset
= i915_gem_obj_ggtt_offset(obj
) + args
->offset
;
760 /* Operation in this page
762 * page_base = page offset within aperture
763 * page_offset = offset within page
764 * page_length = bytes to copy for this page
766 page_base
= offset
& PAGE_MASK
;
767 page_offset
= offset_in_page(offset
);
768 page_length
= remain
;
769 if ((page_offset
+ remain
) > PAGE_SIZE
)
770 page_length
= PAGE_SIZE
- page_offset
;
772 /* If we get a fault while copying data, then (presumably) our
773 * source page isn't available. Return the error and we'll
774 * retry in the slow path.
776 if (fast_user_write(dev_priv
->gtt
.mappable
, page_base
,
777 page_offset
, user_data
, page_length
)) {
782 remain
-= page_length
;
783 user_data
+= page_length
;
784 offset
+= page_length
;
788 i915_gem_object_ggtt_unpin(obj
);
793 /* Per-page copy function for the shmem pwrite fastpath.
794 * Flushes invalid cachelines before writing to the target if
795 * needs_clflush_before is set and flushes out any written cachelines after
796 * writing if needs_clflush is set. */
798 shmem_pwrite_fast(struct page
*page
, int shmem_page_offset
, int page_length
,
799 char __user
*user_data
,
800 bool page_do_bit17_swizzling
,
801 bool needs_clflush_before
,
802 bool needs_clflush_after
)
807 if (unlikely(page_do_bit17_swizzling
))
810 vaddr
= kmap_atomic(page
);
811 if (needs_clflush_before
)
812 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
814 ret
= __copy_from_user_inatomic(vaddr
+ shmem_page_offset
,
815 user_data
, page_length
);
816 if (needs_clflush_after
)
817 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
819 kunmap_atomic(vaddr
);
821 return ret
? -EFAULT
: 0;
824 /* Only difference to the fast-path function is that this can handle bit17
825 * and uses non-atomic copy and kmap functions. */
827 shmem_pwrite_slow(struct page
*page
, int shmem_page_offset
, int page_length
,
828 char __user
*user_data
,
829 bool page_do_bit17_swizzling
,
830 bool needs_clflush_before
,
831 bool needs_clflush_after
)
837 if (unlikely(needs_clflush_before
|| page_do_bit17_swizzling
))
838 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
840 page_do_bit17_swizzling
);
841 if (page_do_bit17_swizzling
)
842 ret
= __copy_from_user_swizzled(vaddr
, shmem_page_offset
,
846 ret
= __copy_from_user(vaddr
+ shmem_page_offset
,
849 if (needs_clflush_after
)
850 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
852 page_do_bit17_swizzling
);
855 return ret
? -EFAULT
: 0;
859 i915_gem_shmem_pwrite(struct drm_device
*dev
,
860 struct drm_i915_gem_object
*obj
,
861 struct drm_i915_gem_pwrite
*args
,
862 struct drm_file
*file
)
866 char __user
*user_data
;
867 int shmem_page_offset
, page_length
, ret
= 0;
868 int obj_do_bit17_swizzling
, page_do_bit17_swizzling
;
869 int hit_slowpath
= 0;
870 int needs_clflush_after
= 0;
871 int needs_clflush_before
= 0;
872 struct sg_page_iter sg_iter
;
874 user_data
= to_user_ptr(args
->data_ptr
);
877 obj_do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
879 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
880 /* If we're not in the cpu write domain, set ourself into the gtt
881 * write domain and manually flush cachelines (if required). This
882 * optimizes for the case when the gpu will use the data
883 * right away and we therefore have to clflush anyway. */
884 needs_clflush_after
= cpu_write_needs_clflush(obj
);
885 ret
= i915_gem_object_wait_rendering(obj
, false);
889 /* Same trick applies to invalidate partially written cachelines read
891 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) == 0)
892 needs_clflush_before
=
893 !cpu_cache_is_coherent(dev
, obj
->cache_level
);
895 ret
= i915_gem_object_get_pages(obj
);
899 i915_gem_object_pin_pages(obj
);
901 offset
= args
->offset
;
904 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
,
905 offset
>> PAGE_SHIFT
) {
906 struct page
*page
= sg_page_iter_page(&sg_iter
);
907 int partial_cacheline_write
;
912 /* Operation in this page
914 * shmem_page_offset = offset within page in shmem file
915 * page_length = bytes to copy for this page
917 shmem_page_offset
= offset_in_page(offset
);
919 page_length
= remain
;
920 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
921 page_length
= PAGE_SIZE
- shmem_page_offset
;
923 /* If we don't overwrite a cacheline completely we need to be
924 * careful to have up-to-date data by first clflushing. Don't
925 * overcomplicate things and flush the entire patch. */
926 partial_cacheline_write
= needs_clflush_before
&&
927 ((shmem_page_offset
| page_length
)
928 & (boot_cpu_data
.x86_clflush_size
- 1));
930 page_do_bit17_swizzling
= obj_do_bit17_swizzling
&&
931 (page_to_phys(page
) & (1 << 17)) != 0;
933 ret
= shmem_pwrite_fast(page
, shmem_page_offset
, page_length
,
934 user_data
, page_do_bit17_swizzling
,
935 partial_cacheline_write
,
936 needs_clflush_after
);
941 mutex_unlock(&dev
->struct_mutex
);
942 ret
= shmem_pwrite_slow(page
, shmem_page_offset
, page_length
,
943 user_data
, page_do_bit17_swizzling
,
944 partial_cacheline_write
,
945 needs_clflush_after
);
947 mutex_lock(&dev
->struct_mutex
);
953 remain
-= page_length
;
954 user_data
+= page_length
;
955 offset
+= page_length
;
959 i915_gem_object_unpin_pages(obj
);
963 * Fixup: Flush cpu caches in case we didn't flush the dirty
964 * cachelines in-line while writing and the object moved
965 * out of the cpu write domain while we've dropped the lock.
967 if (!needs_clflush_after
&&
968 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
969 if (i915_gem_clflush_object(obj
, obj
->pin_display
))
970 i915_gem_chipset_flush(dev
);
974 if (needs_clflush_after
)
975 i915_gem_chipset_flush(dev
);
981 * Writes data to the object referenced by handle.
983 * On error, the contents of the buffer that were to be modified are undefined.
986 i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
987 struct drm_file
*file
)
989 struct drm_i915_gem_pwrite
*args
= data
;
990 struct drm_i915_gem_object
*obj
;
996 if (!access_ok(VERIFY_READ
,
997 to_user_ptr(args
->data_ptr
),
1001 if (likely(!i915
.prefault_disable
)) {
1002 ret
= fault_in_multipages_readable(to_user_ptr(args
->data_ptr
),
1008 ret
= i915_mutex_lock_interruptible(dev
);
1012 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1013 if (&obj
->base
== NULL
) {
1018 /* Bounds check destination. */
1019 if (args
->offset
> obj
->base
.size
||
1020 args
->size
> obj
->base
.size
- args
->offset
) {
1025 /* prime objects have no backing filp to GEM pread/pwrite
1028 if (!obj
->base
.filp
) {
1033 trace_i915_gem_object_pwrite(obj
, args
->offset
, args
->size
);
1036 /* We can only do the GTT pwrite on untiled buffers, as otherwise
1037 * it would end up going through the fenced access, and we'll get
1038 * different detiling behavior between reading and writing.
1039 * pread/pwrite currently are reading and writing from the CPU
1040 * perspective, requiring manual detiling by the client.
1042 if (obj
->phys_handle
) {
1043 ret
= i915_gem_phys_pwrite(obj
, args
, file
);
1047 if (obj
->tiling_mode
== I915_TILING_NONE
&&
1048 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
&&
1049 cpu_write_needs_clflush(obj
)) {
1050 ret
= i915_gem_gtt_pwrite_fast(dev
, obj
, args
, file
);
1051 /* Note that the gtt paths might fail with non-page-backed user
1052 * pointers (e.g. gtt mappings when moving data between
1053 * textures). Fallback to the shmem path in that case. */
1056 if (ret
== -EFAULT
|| ret
== -ENOSPC
)
1057 ret
= i915_gem_shmem_pwrite(dev
, obj
, args
, file
);
1060 drm_gem_object_unreference(&obj
->base
);
1062 mutex_unlock(&dev
->struct_mutex
);
1067 i915_gem_check_wedge(struct i915_gpu_error
*error
,
1070 if (i915_reset_in_progress(error
)) {
1071 /* Non-interruptible callers can't handle -EAGAIN, hence return
1072 * -EIO unconditionally for these. */
1076 /* Recovery complete, but the reset failed ... */
1077 if (i915_terminally_wedged(error
))
1087 * Compare seqno against outstanding lazy request. Emit a request if they are
1091 i915_gem_check_olr(struct intel_ring_buffer
*ring
, u32 seqno
)
1095 BUG_ON(!mutex_is_locked(&ring
->dev
->struct_mutex
));
1098 if (seqno
== ring
->outstanding_lazy_seqno
)
1099 ret
= i915_add_request(ring
, NULL
);
1104 static void fake_irq(unsigned long data
)
1106 wake_up_process((struct task_struct
*)data
);
1109 static bool missed_irq(struct drm_i915_private
*dev_priv
,
1110 struct intel_ring_buffer
*ring
)
1112 return test_bit(ring
->id
, &dev_priv
->gpu_error
.missed_irq_rings
);
1115 static bool can_wait_boost(struct drm_i915_file_private
*file_priv
)
1117 if (file_priv
== NULL
)
1120 return !atomic_xchg(&file_priv
->rps_wait_boost
, true);
1124 * __wait_seqno - wait until execution of seqno has finished
1125 * @ring: the ring expected to report seqno
1127 * @reset_counter: reset sequence associated with the given seqno
1128 * @interruptible: do an interruptible wait (normally yes)
1129 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
1131 * Note: It is of utmost importance that the passed in seqno and reset_counter
1132 * values have been read by the caller in an smp safe manner. Where read-side
1133 * locks are involved, it is sufficient to read the reset_counter before
1134 * unlocking the lock that protects the seqno. For lockless tricks, the
1135 * reset_counter _must_ be read before, and an appropriate smp_rmb must be
1138 * Returns 0 if the seqno was found within the alloted time. Else returns the
1139 * errno with remaining time filled in timeout argument.
1141 static int __wait_seqno(struct intel_ring_buffer
*ring
, u32 seqno
,
1142 unsigned reset_counter
,
1144 struct timespec
*timeout
,
1145 struct drm_i915_file_private
*file_priv
)
1147 struct drm_device
*dev
= ring
->dev
;
1148 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1149 const bool irq_test_in_progress
=
1150 ACCESS_ONCE(dev_priv
->gpu_error
.test_irq_rings
) & intel_ring_flag(ring
);
1151 struct timespec before
, now
;
1153 unsigned long timeout_expire
;
1156 WARN(dev_priv
->pm
.irqs_disabled
, "IRQs disabled\n");
1158 if (i915_seqno_passed(ring
->get_seqno(ring
, true), seqno
))
1161 timeout_expire
= timeout
? jiffies
+ timespec_to_jiffies_timeout(timeout
) : 0;
1163 if (INTEL_INFO(dev
)->gen
>= 6 && can_wait_boost(file_priv
)) {
1164 gen6_rps_boost(dev_priv
);
1166 mod_delayed_work(dev_priv
->wq
,
1167 &file_priv
->mm
.idle_work
,
1168 msecs_to_jiffies(100));
1171 if (!irq_test_in_progress
&& WARN_ON(!ring
->irq_get(ring
)))
1174 /* Record current time in case interrupted by signal, or wedged */
1175 trace_i915_gem_request_wait_begin(ring
, seqno
);
1176 getrawmonotonic(&before
);
1178 struct timer_list timer
;
1180 prepare_to_wait(&ring
->irq_queue
, &wait
,
1181 interruptible
? TASK_INTERRUPTIBLE
: TASK_UNINTERRUPTIBLE
);
1183 /* We need to check whether any gpu reset happened in between
1184 * the caller grabbing the seqno and now ... */
1185 if (reset_counter
!= atomic_read(&dev_priv
->gpu_error
.reset_counter
)) {
1186 /* ... but upgrade the -EAGAIN to an -EIO if the gpu
1187 * is truely gone. */
1188 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, interruptible
);
1194 if (i915_seqno_passed(ring
->get_seqno(ring
, false), seqno
)) {
1199 if (interruptible
&& signal_pending(current
)) {
1204 if (timeout
&& time_after_eq(jiffies
, timeout_expire
)) {
1209 timer
.function
= NULL
;
1210 if (timeout
|| missed_irq(dev_priv
, ring
)) {
1211 unsigned long expire
;
1213 setup_timer_on_stack(&timer
, fake_irq
, (unsigned long)current
);
1214 expire
= missed_irq(dev_priv
, ring
) ? jiffies
+ 1 : timeout_expire
;
1215 mod_timer(&timer
, expire
);
1220 if (timer
.function
) {
1221 del_singleshot_timer_sync(&timer
);
1222 destroy_timer_on_stack(&timer
);
1225 getrawmonotonic(&now
);
1226 trace_i915_gem_request_wait_end(ring
, seqno
);
1228 if (!irq_test_in_progress
)
1229 ring
->irq_put(ring
);
1231 finish_wait(&ring
->irq_queue
, &wait
);
1234 struct timespec sleep_time
= timespec_sub(now
, before
);
1235 *timeout
= timespec_sub(*timeout
, sleep_time
);
1236 if (!timespec_valid(timeout
)) /* i.e. negative time remains */
1237 set_normalized_timespec(timeout
, 0, 0);
1244 * Waits for a sequence number to be signaled, and cleans up the
1245 * request and object lists appropriately for that event.
1248 i915_wait_seqno(struct intel_ring_buffer
*ring
, uint32_t seqno
)
1250 struct drm_device
*dev
= ring
->dev
;
1251 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1252 bool interruptible
= dev_priv
->mm
.interruptible
;
1255 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
1258 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, interruptible
);
1262 ret
= i915_gem_check_olr(ring
, seqno
);
1266 return __wait_seqno(ring
, seqno
,
1267 atomic_read(&dev_priv
->gpu_error
.reset_counter
),
1268 interruptible
, NULL
, NULL
);
1272 i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object
*obj
,
1273 struct intel_ring_buffer
*ring
)
1275 i915_gem_retire_requests_ring(ring
);
1277 /* Manually manage the write flush as we may have not yet
1278 * retired the buffer.
1280 * Note that the last_write_seqno is always the earlier of
1281 * the two (read/write) seqno, so if we haved successfully waited,
1282 * we know we have passed the last write.
1284 obj
->last_write_seqno
= 0;
1285 obj
->base
.write_domain
&= ~I915_GEM_GPU_DOMAINS
;
1291 * Ensures that all rendering to the object has completed and the object is
1292 * safe to unbind from the GTT or access from the CPU.
1294 static __must_check
int
1295 i915_gem_object_wait_rendering(struct drm_i915_gem_object
*obj
,
1298 struct intel_ring_buffer
*ring
= obj
->ring
;
1302 seqno
= readonly
? obj
->last_write_seqno
: obj
->last_read_seqno
;
1306 ret
= i915_wait_seqno(ring
, seqno
);
1310 return i915_gem_object_wait_rendering__tail(obj
, ring
);
1313 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1314 * as the object state may change during this call.
1316 static __must_check
int
1317 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object
*obj
,
1318 struct drm_i915_file_private
*file_priv
,
1321 struct drm_device
*dev
= obj
->base
.dev
;
1322 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1323 struct intel_ring_buffer
*ring
= obj
->ring
;
1324 unsigned reset_counter
;
1328 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
1329 BUG_ON(!dev_priv
->mm
.interruptible
);
1331 seqno
= readonly
? obj
->last_write_seqno
: obj
->last_read_seqno
;
1335 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, true);
1339 ret
= i915_gem_check_olr(ring
, seqno
);
1343 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
1344 mutex_unlock(&dev
->struct_mutex
);
1345 ret
= __wait_seqno(ring
, seqno
, reset_counter
, true, NULL
, file_priv
);
1346 mutex_lock(&dev
->struct_mutex
);
1350 return i915_gem_object_wait_rendering__tail(obj
, ring
);
1354 * Called when user space prepares to use an object with the CPU, either
1355 * through the mmap ioctl's mapping or a GTT mapping.
1358 i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
1359 struct drm_file
*file
)
1361 struct drm_i915_gem_set_domain
*args
= data
;
1362 struct drm_i915_gem_object
*obj
;
1363 uint32_t read_domains
= args
->read_domains
;
1364 uint32_t write_domain
= args
->write_domain
;
1367 /* Only handle setting domains to types used by the CPU. */
1368 if (write_domain
& I915_GEM_GPU_DOMAINS
)
1371 if (read_domains
& I915_GEM_GPU_DOMAINS
)
1374 /* Having something in the write domain implies it's in the read
1375 * domain, and only that read domain. Enforce that in the request.
1377 if (write_domain
!= 0 && read_domains
!= write_domain
)
1380 ret
= i915_mutex_lock_interruptible(dev
);
1384 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1385 if (&obj
->base
== NULL
) {
1390 /* Try to flush the object off the GPU without holding the lock.
1391 * We will repeat the flush holding the lock in the normal manner
1392 * to catch cases where we are gazumped.
1394 ret
= i915_gem_object_wait_rendering__nonblocking(obj
,
1400 if (read_domains
& I915_GEM_DOMAIN_GTT
) {
1401 ret
= i915_gem_object_set_to_gtt_domain(obj
, write_domain
!= 0);
1403 /* Silently promote "you're not bound, there was nothing to do"
1404 * to success, since the client was just asking us to
1405 * make sure everything was done.
1410 ret
= i915_gem_object_set_to_cpu_domain(obj
, write_domain
!= 0);
1414 drm_gem_object_unreference(&obj
->base
);
1416 mutex_unlock(&dev
->struct_mutex
);
1421 * Called when user space has done writes to this buffer
1424 i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1425 struct drm_file
*file
)
1427 struct drm_i915_gem_sw_finish
*args
= data
;
1428 struct drm_i915_gem_object
*obj
;
1431 ret
= i915_mutex_lock_interruptible(dev
);
1435 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1436 if (&obj
->base
== NULL
) {
1441 /* Pinned buffers may be scanout, so flush the cache */
1442 if (obj
->pin_display
)
1443 i915_gem_object_flush_cpu_write_domain(obj
, true);
1445 drm_gem_object_unreference(&obj
->base
);
1447 mutex_unlock(&dev
->struct_mutex
);
1452 * Maps the contents of an object, returning the address it is mapped
1455 * While the mapping holds a reference on the contents of the object, it doesn't
1456 * imply a ref on the object itself.
1459 i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1460 struct drm_file
*file
)
1462 struct drm_i915_gem_mmap
*args
= data
;
1463 struct drm_gem_object
*obj
;
1466 obj
= drm_gem_object_lookup(dev
, file
, args
->handle
);
1470 /* prime objects have no backing filp to GEM mmap
1474 drm_gem_object_unreference_unlocked(obj
);
1478 addr
= vm_mmap(obj
->filp
, 0, args
->size
,
1479 PROT_READ
| PROT_WRITE
, MAP_SHARED
,
1481 drm_gem_object_unreference_unlocked(obj
);
1482 if (IS_ERR((void *)addr
))
1485 args
->addr_ptr
= (uint64_t) addr
;
1491 * i915_gem_fault - fault a page into the GTT
1492 * vma: VMA in question
1495 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1496 * from userspace. The fault handler takes care of binding the object to
1497 * the GTT (if needed), allocating and programming a fence register (again,
1498 * only if needed based on whether the old reg is still valid or the object
1499 * is tiled) and inserting a new PTE into the faulting process.
1501 * Note that the faulting process may involve evicting existing objects
1502 * from the GTT and/or fence registers to make room. So performance may
1503 * suffer if the GTT working set is large or there are few fence registers
1506 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
)
1508 struct drm_i915_gem_object
*obj
= to_intel_bo(vma
->vm_private_data
);
1509 struct drm_device
*dev
= obj
->base
.dev
;
1510 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1511 pgoff_t page_offset
;
1514 bool write
= !!(vmf
->flags
& FAULT_FLAG_WRITE
);
1516 intel_runtime_pm_get(dev_priv
);
1518 /* We don't use vmf->pgoff since that has the fake offset */
1519 page_offset
= ((unsigned long)vmf
->virtual_address
- vma
->vm_start
) >>
1522 ret
= i915_mutex_lock_interruptible(dev
);
1526 trace_i915_gem_object_fault(obj
, page_offset
, true, write
);
1528 /* Try to flush the object off the GPU first without holding the lock.
1529 * Upon reacquiring the lock, we will perform our sanity checks and then
1530 * repeat the flush holding the lock in the normal manner to catch cases
1531 * where we are gazumped.
1533 ret
= i915_gem_object_wait_rendering__nonblocking(obj
, NULL
, !write
);
1537 /* Access to snoopable pages through the GTT is incoherent. */
1538 if (obj
->cache_level
!= I915_CACHE_NONE
&& !HAS_LLC(dev
)) {
1543 /* Now bind it into the GTT if needed */
1544 ret
= i915_gem_obj_ggtt_pin(obj
, 0, PIN_MAPPABLE
);
1548 ret
= i915_gem_object_set_to_gtt_domain(obj
, write
);
1552 ret
= i915_gem_object_get_fence(obj
);
1556 obj
->fault_mappable
= true;
1558 pfn
= dev_priv
->gtt
.mappable_base
+ i915_gem_obj_ggtt_offset(obj
);
1562 /* Finally, remap it using the new GTT offset */
1563 ret
= vm_insert_pfn(vma
, (unsigned long)vmf
->virtual_address
, pfn
);
1565 i915_gem_object_ggtt_unpin(obj
);
1567 mutex_unlock(&dev
->struct_mutex
);
1571 /* If this -EIO is due to a gpu hang, give the reset code a
1572 * chance to clean up the mess. Otherwise return the proper
1574 if (i915_terminally_wedged(&dev_priv
->gpu_error
)) {
1575 ret
= VM_FAULT_SIGBUS
;
1580 * EAGAIN means the gpu is hung and we'll wait for the error
1581 * handler to reset everything when re-faulting in
1582 * i915_mutex_lock_interruptible.
1589 * EBUSY is ok: this just means that another thread
1590 * already did the job.
1592 ret
= VM_FAULT_NOPAGE
;
1599 ret
= VM_FAULT_SIGBUS
;
1602 WARN_ONCE(ret
, "unhandled error in i915_gem_fault: %i\n", ret
);
1603 ret
= VM_FAULT_SIGBUS
;
1607 intel_runtime_pm_put(dev_priv
);
1611 void i915_gem_release_all_mmaps(struct drm_i915_private
*dev_priv
)
1613 struct i915_vma
*vma
;
1616 * Only the global gtt is relevant for gtt memory mappings, so restrict
1617 * list traversal to objects bound into the global address space. Note
1618 * that the active list should be empty, but better safe than sorry.
1620 WARN_ON(!list_empty(&dev_priv
->gtt
.base
.active_list
));
1621 list_for_each_entry(vma
, &dev_priv
->gtt
.base
.active_list
, mm_list
)
1622 i915_gem_release_mmap(vma
->obj
);
1623 list_for_each_entry(vma
, &dev_priv
->gtt
.base
.inactive_list
, mm_list
)
1624 i915_gem_release_mmap(vma
->obj
);
1628 * i915_gem_release_mmap - remove physical page mappings
1629 * @obj: obj in question
1631 * Preserve the reservation of the mmapping with the DRM core code, but
1632 * relinquish ownership of the pages back to the system.
1634 * It is vital that we remove the page mapping if we have mapped a tiled
1635 * object through the GTT and then lose the fence register due to
1636 * resource pressure. Similarly if the object has been moved out of the
1637 * aperture, than pages mapped into userspace must be revoked. Removing the
1638 * mapping will then trigger a page fault on the next user access, allowing
1639 * fixup by i915_gem_fault().
1642 i915_gem_release_mmap(struct drm_i915_gem_object
*obj
)
1644 if (!obj
->fault_mappable
)
1647 drm_vma_node_unmap(&obj
->base
.vma_node
,
1648 obj
->base
.dev
->anon_inode
->i_mapping
);
1649 obj
->fault_mappable
= false;
1653 i915_gem_get_gtt_size(struct drm_device
*dev
, uint32_t size
, int tiling_mode
)
1657 if (INTEL_INFO(dev
)->gen
>= 4 ||
1658 tiling_mode
== I915_TILING_NONE
)
1661 /* Previous chips need a power-of-two fence region when tiling */
1662 if (INTEL_INFO(dev
)->gen
== 3)
1663 gtt_size
= 1024*1024;
1665 gtt_size
= 512*1024;
1667 while (gtt_size
< size
)
1674 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1675 * @obj: object to check
1677 * Return the required GTT alignment for an object, taking into account
1678 * potential fence register mapping.
1681 i915_gem_get_gtt_alignment(struct drm_device
*dev
, uint32_t size
,
1682 int tiling_mode
, bool fenced
)
1685 * Minimum alignment is 4k (GTT page size), but might be greater
1686 * if a fence register is needed for the object.
1688 if (INTEL_INFO(dev
)->gen
>= 4 || (!fenced
&& IS_G33(dev
)) ||
1689 tiling_mode
== I915_TILING_NONE
)
1693 * Previous chips need to be aligned to the size of the smallest
1694 * fence register that can contain the object.
1696 return i915_gem_get_gtt_size(dev
, size
, tiling_mode
);
1699 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object
*obj
)
1701 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
1704 if (drm_vma_node_has_offset(&obj
->base
.vma_node
))
1707 dev_priv
->mm
.shrinker_no_lock_stealing
= true;
1709 ret
= drm_gem_create_mmap_offset(&obj
->base
);
1713 /* Badly fragmented mmap space? The only way we can recover
1714 * space is by destroying unwanted objects. We can't randomly release
1715 * mmap_offsets as userspace expects them to be persistent for the
1716 * lifetime of the objects. The closest we can is to release the
1717 * offsets on purgeable objects by truncating it and marking it purged,
1718 * which prevents userspace from ever using that object again.
1720 i915_gem_purge(dev_priv
, obj
->base
.size
>> PAGE_SHIFT
);
1721 ret
= drm_gem_create_mmap_offset(&obj
->base
);
1725 i915_gem_shrink_all(dev_priv
);
1726 ret
= drm_gem_create_mmap_offset(&obj
->base
);
1728 dev_priv
->mm
.shrinker_no_lock_stealing
= false;
1733 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object
*obj
)
1735 drm_gem_free_mmap_offset(&obj
->base
);
1739 i915_gem_mmap_gtt(struct drm_file
*file
,
1740 struct drm_device
*dev
,
1744 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1745 struct drm_i915_gem_object
*obj
;
1748 ret
= i915_mutex_lock_interruptible(dev
);
1752 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, handle
));
1753 if (&obj
->base
== NULL
) {
1758 if (obj
->base
.size
> dev_priv
->gtt
.mappable_end
) {
1763 if (obj
->madv
!= I915_MADV_WILLNEED
) {
1764 DRM_DEBUG("Attempting to mmap a purgeable buffer\n");
1769 ret
= i915_gem_object_create_mmap_offset(obj
);
1773 *offset
= drm_vma_node_offset_addr(&obj
->base
.vma_node
);
1776 drm_gem_object_unreference(&obj
->base
);
1778 mutex_unlock(&dev
->struct_mutex
);
1783 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1785 * @data: GTT mapping ioctl data
1786 * @file: GEM object info
1788 * Simply returns the fake offset to userspace so it can mmap it.
1789 * The mmap call will end up in drm_gem_mmap(), which will set things
1790 * up so we can get faults in the handler above.
1792 * The fault handler will take care of binding the object into the GTT
1793 * (since it may have been evicted to make room for something), allocating
1794 * a fence register, and mapping the appropriate aperture address into
1798 i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
1799 struct drm_file
*file
)
1801 struct drm_i915_gem_mmap_gtt
*args
= data
;
1803 return i915_gem_mmap_gtt(file
, dev
, args
->handle
, &args
->offset
);
1806 /* Immediately discard the backing storage */
1808 i915_gem_object_truncate(struct drm_i915_gem_object
*obj
)
1810 struct inode
*inode
;
1812 i915_gem_object_free_mmap_offset(obj
);
1814 if (obj
->base
.filp
== NULL
)
1817 /* Our goal here is to return as much of the memory as
1818 * is possible back to the system as we are called from OOM.
1819 * To do this we must instruct the shmfs to drop all of its
1820 * backing pages, *now*.
1822 inode
= file_inode(obj
->base
.filp
);
1823 shmem_truncate_range(inode
, 0, (loff_t
)-1);
1825 obj
->madv
= __I915_MADV_PURGED
;
1829 i915_gem_object_is_purgeable(struct drm_i915_gem_object
*obj
)
1831 return obj
->madv
== I915_MADV_DONTNEED
;
1835 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object
*obj
)
1837 struct sg_page_iter sg_iter
;
1840 BUG_ON(obj
->madv
== __I915_MADV_PURGED
);
1842 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
1844 /* In the event of a disaster, abandon all caches and
1845 * hope for the best.
1847 WARN_ON(ret
!= -EIO
);
1848 i915_gem_clflush_object(obj
, true);
1849 obj
->base
.read_domains
= obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
1852 if (i915_gem_object_needs_bit17_swizzle(obj
))
1853 i915_gem_object_save_bit_17_swizzle(obj
);
1855 if (obj
->madv
== I915_MADV_DONTNEED
)
1858 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
, 0) {
1859 struct page
*page
= sg_page_iter_page(&sg_iter
);
1862 set_page_dirty(page
);
1864 if (obj
->madv
== I915_MADV_WILLNEED
)
1865 mark_page_accessed(page
);
1867 page_cache_release(page
);
1871 sg_free_table(obj
->pages
);
1876 i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
)
1878 const struct drm_i915_gem_object_ops
*ops
= obj
->ops
;
1880 if (obj
->pages
== NULL
)
1883 if (obj
->pages_pin_count
)
1886 BUG_ON(i915_gem_obj_bound_any(obj
));
1888 /* ->put_pages might need to allocate memory for the bit17 swizzle
1889 * array, hence protect them from being reaped by removing them from gtt
1891 list_del(&obj
->global_list
);
1893 ops
->put_pages(obj
);
1896 if (i915_gem_object_is_purgeable(obj
))
1897 i915_gem_object_truncate(obj
);
1902 static unsigned long
1903 __i915_gem_shrink(struct drm_i915_private
*dev_priv
, long target
,
1904 bool purgeable_only
)
1906 struct list_head still_bound_list
;
1907 struct drm_i915_gem_object
*obj
, *next
;
1908 unsigned long count
= 0;
1910 list_for_each_entry_safe(obj
, next
,
1911 &dev_priv
->mm
.unbound_list
,
1913 if ((i915_gem_object_is_purgeable(obj
) || !purgeable_only
) &&
1914 i915_gem_object_put_pages(obj
) == 0) {
1915 count
+= obj
->base
.size
>> PAGE_SHIFT
;
1916 if (count
>= target
)
1922 * As we may completely rewrite the bound list whilst unbinding
1923 * (due to retiring requests) we have to strictly process only
1924 * one element of the list at the time, and recheck the list
1925 * on every iteration.
1927 INIT_LIST_HEAD(&still_bound_list
);
1928 while (count
< target
&& !list_empty(&dev_priv
->mm
.bound_list
)) {
1929 struct i915_vma
*vma
, *v
;
1931 obj
= list_first_entry(&dev_priv
->mm
.bound_list
,
1932 typeof(*obj
), global_list
);
1933 list_move_tail(&obj
->global_list
, &still_bound_list
);
1935 if (!i915_gem_object_is_purgeable(obj
) && purgeable_only
)
1939 * Hold a reference whilst we unbind this object, as we may
1940 * end up waiting for and retiring requests. This might
1941 * release the final reference (held by the active list)
1942 * and result in the object being freed from under us.
1943 * in this object being freed.
1945 * Note 1: Shrinking the bound list is special since only active
1946 * (and hence bound objects) can contain such limbo objects, so
1947 * we don't need special tricks for shrinking the unbound list.
1948 * The only other place where we have to be careful with active
1949 * objects suddenly disappearing due to retiring requests is the
1952 * Note 2: Even though the bound list doesn't hold a reference
1953 * to the object we can safely grab one here: The final object
1954 * unreferencing and the bound_list are both protected by the
1955 * dev->struct_mutex and so we won't ever be able to observe an
1956 * object on the bound_list with a reference count equals 0.
1958 drm_gem_object_reference(&obj
->base
);
1960 list_for_each_entry_safe(vma
, v
, &obj
->vma_list
, vma_link
)
1961 if (i915_vma_unbind(vma
))
1964 if (i915_gem_object_put_pages(obj
) == 0)
1965 count
+= obj
->base
.size
>> PAGE_SHIFT
;
1967 drm_gem_object_unreference(&obj
->base
);
1969 list_splice(&still_bound_list
, &dev_priv
->mm
.bound_list
);
1974 static unsigned long
1975 i915_gem_purge(struct drm_i915_private
*dev_priv
, long target
)
1977 return __i915_gem_shrink(dev_priv
, target
, true);
1980 static unsigned long
1981 i915_gem_shrink_all(struct drm_i915_private
*dev_priv
)
1983 struct drm_i915_gem_object
*obj
, *next
;
1986 i915_gem_evict_everything(dev_priv
->dev
);
1988 list_for_each_entry_safe(obj
, next
, &dev_priv
->mm
.unbound_list
,
1990 if (i915_gem_object_put_pages(obj
) == 0)
1991 freed
+= obj
->base
.size
>> PAGE_SHIFT
;
1997 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object
*obj
)
1999 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2001 struct address_space
*mapping
;
2002 struct sg_table
*st
;
2003 struct scatterlist
*sg
;
2004 struct sg_page_iter sg_iter
;
2006 unsigned long last_pfn
= 0; /* suppress gcc warning */
2009 /* Assert that the object is not currently in any GPU domain. As it
2010 * wasn't in the GTT, there shouldn't be any way it could have been in
2013 BUG_ON(obj
->base
.read_domains
& I915_GEM_GPU_DOMAINS
);
2014 BUG_ON(obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
);
2016 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
2020 page_count
= obj
->base
.size
/ PAGE_SIZE
;
2021 if (sg_alloc_table(st
, page_count
, GFP_KERNEL
)) {
2026 /* Get the list of pages out of our struct file. They'll be pinned
2027 * at this point until we release them.
2029 * Fail silently without starting the shrinker
2031 mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
2032 gfp
= mapping_gfp_mask(mapping
);
2033 gfp
|= __GFP_NORETRY
| __GFP_NOWARN
| __GFP_NO_KSWAPD
;
2034 gfp
&= ~(__GFP_IO
| __GFP_WAIT
);
2037 for (i
= 0; i
< page_count
; i
++) {
2038 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
2040 i915_gem_purge(dev_priv
, page_count
);
2041 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
2044 /* We've tried hard to allocate the memory by reaping
2045 * our own buffer, now let the real VM do its job and
2046 * go down in flames if truly OOM.
2048 gfp
&= ~(__GFP_NORETRY
| __GFP_NOWARN
| __GFP_NO_KSWAPD
);
2049 gfp
|= __GFP_IO
| __GFP_WAIT
;
2051 i915_gem_shrink_all(dev_priv
);
2052 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
2056 gfp
|= __GFP_NORETRY
| __GFP_NOWARN
| __GFP_NO_KSWAPD
;
2057 gfp
&= ~(__GFP_IO
| __GFP_WAIT
);
2059 #ifdef CONFIG_SWIOTLB
2060 if (swiotlb_nr_tbl()) {
2062 sg_set_page(sg
, page
, PAGE_SIZE
, 0);
2067 if (!i
|| page_to_pfn(page
) != last_pfn
+ 1) {
2071 sg_set_page(sg
, page
, PAGE_SIZE
, 0);
2073 sg
->length
+= PAGE_SIZE
;
2075 last_pfn
= page_to_pfn(page
);
2077 /* Check that the i965g/gm workaround works. */
2078 WARN_ON((gfp
& __GFP_DMA32
) && (last_pfn
>= 0x00100000UL
));
2080 #ifdef CONFIG_SWIOTLB
2081 if (!swiotlb_nr_tbl())
2086 if (i915_gem_object_needs_bit17_swizzle(obj
))
2087 i915_gem_object_do_bit_17_swizzle(obj
);
2093 for_each_sg_page(st
->sgl
, &sg_iter
, st
->nents
, 0)
2094 page_cache_release(sg_page_iter_page(&sg_iter
));
2097 return PTR_ERR(page
);
2100 /* Ensure that the associated pages are gathered from the backing storage
2101 * and pinned into our object. i915_gem_object_get_pages() may be called
2102 * multiple times before they are released by a single call to
2103 * i915_gem_object_put_pages() - once the pages are no longer referenced
2104 * either as a result of memory pressure (reaping pages under the shrinker)
2105 * or as the object is itself released.
2108 i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
)
2110 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2111 const struct drm_i915_gem_object_ops
*ops
= obj
->ops
;
2117 if (obj
->madv
!= I915_MADV_WILLNEED
) {
2118 DRM_DEBUG("Attempting to obtain a purgeable object\n");
2122 BUG_ON(obj
->pages_pin_count
);
2124 ret
= ops
->get_pages(obj
);
2128 list_add_tail(&obj
->global_list
, &dev_priv
->mm
.unbound_list
);
2133 i915_gem_object_move_to_active(struct drm_i915_gem_object
*obj
,
2134 struct intel_ring_buffer
*ring
)
2136 struct drm_device
*dev
= obj
->base
.dev
;
2137 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2138 u32 seqno
= intel_ring_get_seqno(ring
);
2140 BUG_ON(ring
== NULL
);
2141 if (obj
->ring
!= ring
&& obj
->last_write_seqno
) {
2142 /* Keep the seqno relative to the current ring */
2143 obj
->last_write_seqno
= seqno
;
2147 /* Add a reference if we're newly entering the active list. */
2149 drm_gem_object_reference(&obj
->base
);
2153 list_move_tail(&obj
->ring_list
, &ring
->active_list
);
2155 obj
->last_read_seqno
= seqno
;
2157 if (obj
->fenced_gpu_access
) {
2158 obj
->last_fenced_seqno
= seqno
;
2160 /* Bump MRU to take account of the delayed flush */
2161 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
2162 struct drm_i915_fence_reg
*reg
;
2164 reg
= &dev_priv
->fence_regs
[obj
->fence_reg
];
2165 list_move_tail(®
->lru_list
,
2166 &dev_priv
->mm
.fence_list
);
2171 void i915_vma_move_to_active(struct i915_vma
*vma
,
2172 struct intel_ring_buffer
*ring
)
2174 list_move_tail(&vma
->mm_list
, &vma
->vm
->active_list
);
2175 return i915_gem_object_move_to_active(vma
->obj
, ring
);
2179 i915_gem_object_move_to_inactive(struct drm_i915_gem_object
*obj
)
2181 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2182 struct i915_address_space
*vm
;
2183 struct i915_vma
*vma
;
2185 BUG_ON(obj
->base
.write_domain
& ~I915_GEM_GPU_DOMAINS
);
2186 BUG_ON(!obj
->active
);
2188 list_for_each_entry(vm
, &dev_priv
->vm_list
, global_link
) {
2189 vma
= i915_gem_obj_to_vma(obj
, vm
);
2190 if (vma
&& !list_empty(&vma
->mm_list
))
2191 list_move_tail(&vma
->mm_list
, &vm
->inactive_list
);
2194 list_del_init(&obj
->ring_list
);
2197 obj
->last_read_seqno
= 0;
2198 obj
->last_write_seqno
= 0;
2199 obj
->base
.write_domain
= 0;
2201 obj
->last_fenced_seqno
= 0;
2202 obj
->fenced_gpu_access
= false;
2205 drm_gem_object_unreference(&obj
->base
);
2207 WARN_ON(i915_verify_lists(dev
));
2211 i915_gem_init_seqno(struct drm_device
*dev
, u32 seqno
)
2213 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2214 struct intel_ring_buffer
*ring
;
2217 /* Carefully retire all requests without writing to the rings */
2218 for_each_ring(ring
, dev_priv
, i
) {
2219 ret
= intel_ring_idle(ring
);
2223 i915_gem_retire_requests(dev
);
2225 /* Finally reset hw state */
2226 for_each_ring(ring
, dev_priv
, i
) {
2227 intel_ring_init_seqno(ring
, seqno
);
2229 for (j
= 0; j
< ARRAY_SIZE(ring
->sync_seqno
); j
++)
2230 ring
->sync_seqno
[j
] = 0;
2236 int i915_gem_set_seqno(struct drm_device
*dev
, u32 seqno
)
2238 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2244 /* HWS page needs to be set less than what we
2245 * will inject to ring
2247 ret
= i915_gem_init_seqno(dev
, seqno
- 1);
2251 /* Carefully set the last_seqno value so that wrap
2252 * detection still works
2254 dev_priv
->next_seqno
= seqno
;
2255 dev_priv
->last_seqno
= seqno
- 1;
2256 if (dev_priv
->last_seqno
== 0)
2257 dev_priv
->last_seqno
--;
2263 i915_gem_get_seqno(struct drm_device
*dev
, u32
*seqno
)
2265 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2267 /* reserve 0 for non-seqno */
2268 if (dev_priv
->next_seqno
== 0) {
2269 int ret
= i915_gem_init_seqno(dev
, 0);
2273 dev_priv
->next_seqno
= 1;
2276 *seqno
= dev_priv
->last_seqno
= dev_priv
->next_seqno
++;
2280 int __i915_add_request(struct intel_ring_buffer
*ring
,
2281 struct drm_file
*file
,
2282 struct drm_i915_gem_object
*obj
,
2285 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
2286 struct drm_i915_gem_request
*request
;
2287 u32 request_ring_position
, request_start
;
2290 request_start
= intel_ring_get_tail(ring
);
2292 * Emit any outstanding flushes - execbuf can fail to emit the flush
2293 * after having emitted the batchbuffer command. Hence we need to fix
2294 * things up similar to emitting the lazy request. The difference here
2295 * is that the flush _must_ happen before the next request, no matter
2298 ret
= intel_ring_flush_all_caches(ring
);
2302 request
= ring
->preallocated_lazy_request
;
2303 if (WARN_ON(request
== NULL
))
2306 /* Record the position of the start of the request so that
2307 * should we detect the updated seqno part-way through the
2308 * GPU processing the request, we never over-estimate the
2309 * position of the head.
2311 request_ring_position
= intel_ring_get_tail(ring
);
2313 ret
= ring
->add_request(ring
);
2317 request
->seqno
= intel_ring_get_seqno(ring
);
2318 request
->ring
= ring
;
2319 request
->head
= request_start
;
2320 request
->tail
= request_ring_position
;
2322 /* Whilst this request exists, batch_obj will be on the
2323 * active_list, and so will hold the active reference. Only when this
2324 * request is retired will the the batch_obj be moved onto the
2325 * inactive_list and lose its active reference. Hence we do not need
2326 * to explicitly hold another reference here.
2328 request
->batch_obj
= obj
;
2330 /* Hold a reference to the current context so that we can inspect
2331 * it later in case a hangcheck error event fires.
2333 request
->ctx
= ring
->last_context
;
2335 i915_gem_context_reference(request
->ctx
);
2337 request
->emitted_jiffies
= jiffies
;
2338 list_add_tail(&request
->list
, &ring
->request_list
);
2339 request
->file_priv
= NULL
;
2342 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
2344 spin_lock(&file_priv
->mm
.lock
);
2345 request
->file_priv
= file_priv
;
2346 list_add_tail(&request
->client_list
,
2347 &file_priv
->mm
.request_list
);
2348 spin_unlock(&file_priv
->mm
.lock
);
2351 trace_i915_gem_request_add(ring
, request
->seqno
);
2352 ring
->outstanding_lazy_seqno
= 0;
2353 ring
->preallocated_lazy_request
= NULL
;
2355 if (!dev_priv
->ums
.mm_suspended
) {
2356 i915_queue_hangcheck(ring
->dev
);
2358 cancel_delayed_work_sync(&dev_priv
->mm
.idle_work
);
2359 queue_delayed_work(dev_priv
->wq
,
2360 &dev_priv
->mm
.retire_work
,
2361 round_jiffies_up_relative(HZ
));
2362 intel_mark_busy(dev_priv
->dev
);
2366 *out_seqno
= request
->seqno
;
2371 i915_gem_request_remove_from_client(struct drm_i915_gem_request
*request
)
2373 struct drm_i915_file_private
*file_priv
= request
->file_priv
;
2378 spin_lock(&file_priv
->mm
.lock
);
2379 list_del(&request
->client_list
);
2380 request
->file_priv
= NULL
;
2381 spin_unlock(&file_priv
->mm
.lock
);
2384 static bool i915_context_is_banned(struct drm_i915_private
*dev_priv
,
2385 const struct i915_hw_context
*ctx
)
2387 unsigned long elapsed
;
2389 elapsed
= get_seconds() - ctx
->hang_stats
.guilty_ts
;
2391 if (ctx
->hang_stats
.banned
)
2394 if (elapsed
<= DRM_I915_CTX_BAN_PERIOD
) {
2395 if (!i915_gem_context_is_default(ctx
)) {
2396 DRM_DEBUG("context hanging too fast, banning!\n");
2398 } else if (dev_priv
->gpu_error
.stop_rings
== 0) {
2399 DRM_ERROR("gpu hanging too fast, banning!\n");
2407 static void i915_set_reset_status(struct drm_i915_private
*dev_priv
,
2408 struct i915_hw_context
*ctx
,
2411 struct i915_ctx_hang_stats
*hs
;
2416 hs
= &ctx
->hang_stats
;
2419 hs
->banned
= i915_context_is_banned(dev_priv
, ctx
);
2421 hs
->guilty_ts
= get_seconds();
2423 hs
->batch_pending
++;
2427 static void i915_gem_free_request(struct drm_i915_gem_request
*request
)
2429 list_del(&request
->list
);
2430 i915_gem_request_remove_from_client(request
);
2433 i915_gem_context_unreference(request
->ctx
);
2438 struct drm_i915_gem_request
*
2439 i915_gem_find_active_request(struct intel_ring_buffer
*ring
)
2441 struct drm_i915_gem_request
*request
;
2442 u32 completed_seqno
;
2444 completed_seqno
= ring
->get_seqno(ring
, false);
2446 list_for_each_entry(request
, &ring
->request_list
, list
) {
2447 if (i915_seqno_passed(completed_seqno
, request
->seqno
))
2456 static void i915_gem_reset_ring_status(struct drm_i915_private
*dev_priv
,
2457 struct intel_ring_buffer
*ring
)
2459 struct drm_i915_gem_request
*request
;
2462 request
= i915_gem_find_active_request(ring
);
2464 if (request
== NULL
)
2467 ring_hung
= ring
->hangcheck
.score
>= HANGCHECK_SCORE_RING_HUNG
;
2469 i915_set_reset_status(dev_priv
, request
->ctx
, ring_hung
);
2471 list_for_each_entry_continue(request
, &ring
->request_list
, list
)
2472 i915_set_reset_status(dev_priv
, request
->ctx
, false);
2475 static void i915_gem_reset_ring_cleanup(struct drm_i915_private
*dev_priv
,
2476 struct intel_ring_buffer
*ring
)
2478 while (!list_empty(&ring
->active_list
)) {
2479 struct drm_i915_gem_object
*obj
;
2481 obj
= list_first_entry(&ring
->active_list
,
2482 struct drm_i915_gem_object
,
2485 i915_gem_object_move_to_inactive(obj
);
2489 * We must free the requests after all the corresponding objects have
2490 * been moved off active lists. Which is the same order as the normal
2491 * retire_requests function does. This is important if object hold
2492 * implicit references on things like e.g. ppgtt address spaces through
2495 while (!list_empty(&ring
->request_list
)) {
2496 struct drm_i915_gem_request
*request
;
2498 request
= list_first_entry(&ring
->request_list
,
2499 struct drm_i915_gem_request
,
2502 i915_gem_free_request(request
);
2506 void i915_gem_restore_fences(struct drm_device
*dev
)
2508 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2511 for (i
= 0; i
< dev_priv
->num_fence_regs
; i
++) {
2512 struct drm_i915_fence_reg
*reg
= &dev_priv
->fence_regs
[i
];
2515 * Commit delayed tiling changes if we have an object still
2516 * attached to the fence, otherwise just clear the fence.
2519 i915_gem_object_update_fence(reg
->obj
, reg
,
2520 reg
->obj
->tiling_mode
);
2522 i915_gem_write_fence(dev
, i
, NULL
);
2527 void i915_gem_reset(struct drm_device
*dev
)
2529 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2530 struct intel_ring_buffer
*ring
;
2534 * Before we free the objects from the requests, we need to inspect
2535 * them for finding the guilty party. As the requests only borrow
2536 * their reference to the objects, the inspection must be done first.
2538 for_each_ring(ring
, dev_priv
, i
)
2539 i915_gem_reset_ring_status(dev_priv
, ring
);
2541 for_each_ring(ring
, dev_priv
, i
)
2542 i915_gem_reset_ring_cleanup(dev_priv
, ring
);
2544 i915_gem_cleanup_ringbuffer(dev
);
2546 i915_gem_context_reset(dev
);
2548 i915_gem_restore_fences(dev
);
2552 * This function clears the request list as sequence numbers are passed.
2555 i915_gem_retire_requests_ring(struct intel_ring_buffer
*ring
)
2559 if (list_empty(&ring
->request_list
))
2562 WARN_ON(i915_verify_lists(ring
->dev
));
2564 seqno
= ring
->get_seqno(ring
, true);
2566 /* Move any buffers on the active list that are no longer referenced
2567 * by the ringbuffer to the flushing/inactive lists as appropriate,
2568 * before we free the context associated with the requests.
2570 while (!list_empty(&ring
->active_list
)) {
2571 struct drm_i915_gem_object
*obj
;
2573 obj
= list_first_entry(&ring
->active_list
,
2574 struct drm_i915_gem_object
,
2577 if (!i915_seqno_passed(seqno
, obj
->last_read_seqno
))
2580 i915_gem_object_move_to_inactive(obj
);
2584 while (!list_empty(&ring
->request_list
)) {
2585 struct drm_i915_gem_request
*request
;
2587 request
= list_first_entry(&ring
->request_list
,
2588 struct drm_i915_gem_request
,
2591 if (!i915_seqno_passed(seqno
, request
->seqno
))
2594 trace_i915_gem_request_retire(ring
, request
->seqno
);
2595 /* We know the GPU must have read the request to have
2596 * sent us the seqno + interrupt, so use the position
2597 * of tail of the request to update the last known position
2600 ring
->last_retired_head
= request
->tail
;
2602 i915_gem_free_request(request
);
2605 if (unlikely(ring
->trace_irq_seqno
&&
2606 i915_seqno_passed(seqno
, ring
->trace_irq_seqno
))) {
2607 ring
->irq_put(ring
);
2608 ring
->trace_irq_seqno
= 0;
2611 WARN_ON(i915_verify_lists(ring
->dev
));
2615 i915_gem_retire_requests(struct drm_device
*dev
)
2617 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2618 struct intel_ring_buffer
*ring
;
2622 for_each_ring(ring
, dev_priv
, i
) {
2623 i915_gem_retire_requests_ring(ring
);
2624 idle
&= list_empty(&ring
->request_list
);
2628 mod_delayed_work(dev_priv
->wq
,
2629 &dev_priv
->mm
.idle_work
,
2630 msecs_to_jiffies(100));
2636 i915_gem_retire_work_handler(struct work_struct
*work
)
2638 struct drm_i915_private
*dev_priv
=
2639 container_of(work
, typeof(*dev_priv
), mm
.retire_work
.work
);
2640 struct drm_device
*dev
= dev_priv
->dev
;
2643 /* Come back later if the device is busy... */
2645 if (mutex_trylock(&dev
->struct_mutex
)) {
2646 idle
= i915_gem_retire_requests(dev
);
2647 mutex_unlock(&dev
->struct_mutex
);
2650 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
,
2651 round_jiffies_up_relative(HZ
));
2655 i915_gem_idle_work_handler(struct work_struct
*work
)
2657 struct drm_i915_private
*dev_priv
=
2658 container_of(work
, typeof(*dev_priv
), mm
.idle_work
.work
);
2660 intel_mark_idle(dev_priv
->dev
);
2664 * Ensures that an object will eventually get non-busy by flushing any required
2665 * write domains, emitting any outstanding lazy request and retiring and
2666 * completed requests.
2669 i915_gem_object_flush_active(struct drm_i915_gem_object
*obj
)
2674 ret
= i915_gem_check_olr(obj
->ring
, obj
->last_read_seqno
);
2678 i915_gem_retire_requests_ring(obj
->ring
);
2685 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2686 * @DRM_IOCTL_ARGS: standard ioctl arguments
2688 * Returns 0 if successful, else an error is returned with the remaining time in
2689 * the timeout parameter.
2690 * -ETIME: object is still busy after timeout
2691 * -ERESTARTSYS: signal interrupted the wait
2692 * -ENONENT: object doesn't exist
2693 * Also possible, but rare:
2694 * -EAGAIN: GPU wedged
2696 * -ENODEV: Internal IRQ fail
2697 * -E?: The add request failed
2699 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2700 * non-zero timeout parameter the wait ioctl will wait for the given number of
2701 * nanoseconds on an object becoming unbusy. Since the wait itself does so
2702 * without holding struct_mutex the object may become re-busied before this
2703 * function completes. A similar but shorter * race condition exists in the busy
2707 i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
, struct drm_file
*file
)
2709 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2710 struct drm_i915_gem_wait
*args
= data
;
2711 struct drm_i915_gem_object
*obj
;
2712 struct intel_ring_buffer
*ring
= NULL
;
2713 struct timespec timeout_stack
, *timeout
= NULL
;
2714 unsigned reset_counter
;
2718 if (args
->timeout_ns
>= 0) {
2719 timeout_stack
= ns_to_timespec(args
->timeout_ns
);
2720 timeout
= &timeout_stack
;
2723 ret
= i915_mutex_lock_interruptible(dev
);
2727 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->bo_handle
));
2728 if (&obj
->base
== NULL
) {
2729 mutex_unlock(&dev
->struct_mutex
);
2733 /* Need to make sure the object gets inactive eventually. */
2734 ret
= i915_gem_object_flush_active(obj
);
2739 seqno
= obj
->last_read_seqno
;
2746 /* Do this after OLR check to make sure we make forward progress polling
2747 * on this IOCTL with a 0 timeout (like busy ioctl)
2749 if (!args
->timeout_ns
) {
2754 drm_gem_object_unreference(&obj
->base
);
2755 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
2756 mutex_unlock(&dev
->struct_mutex
);
2758 ret
= __wait_seqno(ring
, seqno
, reset_counter
, true, timeout
, file
->driver_priv
);
2760 args
->timeout_ns
= timespec_to_ns(timeout
);
2764 drm_gem_object_unreference(&obj
->base
);
2765 mutex_unlock(&dev
->struct_mutex
);
2770 * i915_gem_object_sync - sync an object to a ring.
2772 * @obj: object which may be in use on another ring.
2773 * @to: ring we wish to use the object on. May be NULL.
2775 * This code is meant to abstract object synchronization with the GPU.
2776 * Calling with NULL implies synchronizing the object with the CPU
2777 * rather than a particular GPU ring.
2779 * Returns 0 if successful, else propagates up the lower layer error.
2782 i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
2783 struct intel_ring_buffer
*to
)
2785 struct intel_ring_buffer
*from
= obj
->ring
;
2789 if (from
== NULL
|| to
== from
)
2792 if (to
== NULL
|| !i915_semaphore_is_enabled(obj
->base
.dev
))
2793 return i915_gem_object_wait_rendering(obj
, false);
2795 idx
= intel_ring_sync_index(from
, to
);
2797 seqno
= obj
->last_read_seqno
;
2798 if (seqno
<= from
->sync_seqno
[idx
])
2801 ret
= i915_gem_check_olr(obj
->ring
, seqno
);
2805 trace_i915_gem_ring_sync_to(from
, to
, seqno
);
2806 ret
= to
->sync_to(to
, from
, seqno
);
2808 /* We use last_read_seqno because sync_to()
2809 * might have just caused seqno wrap under
2812 from
->sync_seqno
[idx
] = obj
->last_read_seqno
;
2817 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object
*obj
)
2819 u32 old_write_domain
, old_read_domains
;
2821 /* Force a pagefault for domain tracking on next user access */
2822 i915_gem_release_mmap(obj
);
2824 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
) == 0)
2827 /* Wait for any direct GTT access to complete */
2830 old_read_domains
= obj
->base
.read_domains
;
2831 old_write_domain
= obj
->base
.write_domain
;
2833 obj
->base
.read_domains
&= ~I915_GEM_DOMAIN_GTT
;
2834 obj
->base
.write_domain
&= ~I915_GEM_DOMAIN_GTT
;
2836 trace_i915_gem_object_change_domain(obj
,
2841 int i915_vma_unbind(struct i915_vma
*vma
)
2843 struct drm_i915_gem_object
*obj
= vma
->obj
;
2844 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2847 if (list_empty(&vma
->vma_link
))
2850 if (!drm_mm_node_allocated(&vma
->node
)) {
2851 i915_gem_vma_destroy(vma
);
2858 BUG_ON(obj
->pages
== NULL
);
2860 ret
= i915_gem_object_finish_gpu(obj
);
2863 /* Continue on if we fail due to EIO, the GPU is hung so we
2864 * should be safe and we need to cleanup or else we might
2865 * cause memory corruption through use-after-free.
2868 i915_gem_object_finish_gtt(obj
);
2870 /* release the fence reg _after_ flushing */
2871 ret
= i915_gem_object_put_fence(obj
);
2875 trace_i915_vma_unbind(vma
);
2877 vma
->unbind_vma(vma
);
2879 i915_gem_gtt_finish_object(obj
);
2881 list_del_init(&vma
->mm_list
);
2882 /* Avoid an unnecessary call to unbind on rebind. */
2883 if (i915_is_ggtt(vma
->vm
))
2884 obj
->map_and_fenceable
= true;
2886 drm_mm_remove_node(&vma
->node
);
2887 i915_gem_vma_destroy(vma
);
2889 /* Since the unbound list is global, only move to that list if
2890 * no more VMAs exist. */
2891 if (list_empty(&obj
->vma_list
))
2892 list_move_tail(&obj
->global_list
, &dev_priv
->mm
.unbound_list
);
2894 /* And finally now the object is completely decoupled from this vma,
2895 * we can drop its hold on the backing storage and allow it to be
2896 * reaped by the shrinker.
2898 i915_gem_object_unpin_pages(obj
);
2903 int i915_gpu_idle(struct drm_device
*dev
)
2905 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2906 struct intel_ring_buffer
*ring
;
2909 /* Flush everything onto the inactive list. */
2910 for_each_ring(ring
, dev_priv
, i
) {
2911 ret
= i915_switch_context(ring
, ring
->default_context
);
2915 ret
= intel_ring_idle(ring
);
2923 static void i965_write_fence_reg(struct drm_device
*dev
, int reg
,
2924 struct drm_i915_gem_object
*obj
)
2926 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2928 int fence_pitch_shift
;
2930 if (INTEL_INFO(dev
)->gen
>= 6) {
2931 fence_reg
= FENCE_REG_SANDYBRIDGE_0
;
2932 fence_pitch_shift
= SANDYBRIDGE_FENCE_PITCH_SHIFT
;
2934 fence_reg
= FENCE_REG_965_0
;
2935 fence_pitch_shift
= I965_FENCE_PITCH_SHIFT
;
2938 fence_reg
+= reg
* 8;
2940 /* To w/a incoherency with non-atomic 64-bit register updates,
2941 * we split the 64-bit update into two 32-bit writes. In order
2942 * for a partial fence not to be evaluated between writes, we
2943 * precede the update with write to turn off the fence register,
2944 * and only enable the fence as the last step.
2946 * For extra levels of paranoia, we make sure each step lands
2947 * before applying the next step.
2949 I915_WRITE(fence_reg
, 0);
2950 POSTING_READ(fence_reg
);
2953 u32 size
= i915_gem_obj_ggtt_size(obj
);
2956 val
= (uint64_t)((i915_gem_obj_ggtt_offset(obj
) + size
- 4096) &
2958 val
|= i915_gem_obj_ggtt_offset(obj
) & 0xfffff000;
2959 val
|= (uint64_t)((obj
->stride
/ 128) - 1) << fence_pitch_shift
;
2960 if (obj
->tiling_mode
== I915_TILING_Y
)
2961 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
2962 val
|= I965_FENCE_REG_VALID
;
2964 I915_WRITE(fence_reg
+ 4, val
>> 32);
2965 POSTING_READ(fence_reg
+ 4);
2967 I915_WRITE(fence_reg
+ 0, val
);
2968 POSTING_READ(fence_reg
);
2970 I915_WRITE(fence_reg
+ 4, 0);
2971 POSTING_READ(fence_reg
+ 4);
2975 static void i915_write_fence_reg(struct drm_device
*dev
, int reg
,
2976 struct drm_i915_gem_object
*obj
)
2978 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2982 u32 size
= i915_gem_obj_ggtt_size(obj
);
2986 WARN((i915_gem_obj_ggtt_offset(obj
) & ~I915_FENCE_START_MASK
) ||
2987 (size
& -size
) != size
||
2988 (i915_gem_obj_ggtt_offset(obj
) & (size
- 1)),
2989 "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2990 i915_gem_obj_ggtt_offset(obj
), obj
->map_and_fenceable
, size
);
2992 if (obj
->tiling_mode
== I915_TILING_Y
&& HAS_128_BYTE_Y_TILING(dev
))
2997 /* Note: pitch better be a power of two tile widths */
2998 pitch_val
= obj
->stride
/ tile_width
;
2999 pitch_val
= ffs(pitch_val
) - 1;
3001 val
= i915_gem_obj_ggtt_offset(obj
);
3002 if (obj
->tiling_mode
== I915_TILING_Y
)
3003 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
3004 val
|= I915_FENCE_SIZE_BITS(size
);
3005 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
3006 val
|= I830_FENCE_REG_VALID
;
3011 reg
= FENCE_REG_830_0
+ reg
* 4;
3013 reg
= FENCE_REG_945_8
+ (reg
- 8) * 4;
3015 I915_WRITE(reg
, val
);
3019 static void i830_write_fence_reg(struct drm_device
*dev
, int reg
,
3020 struct drm_i915_gem_object
*obj
)
3022 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3026 u32 size
= i915_gem_obj_ggtt_size(obj
);
3029 WARN((i915_gem_obj_ggtt_offset(obj
) & ~I830_FENCE_START_MASK
) ||
3030 (size
& -size
) != size
||
3031 (i915_gem_obj_ggtt_offset(obj
) & (size
- 1)),
3032 "object 0x%08lx not 512K or pot-size 0x%08x aligned\n",
3033 i915_gem_obj_ggtt_offset(obj
), size
);
3035 pitch_val
= obj
->stride
/ 128;
3036 pitch_val
= ffs(pitch_val
) - 1;
3038 val
= i915_gem_obj_ggtt_offset(obj
);
3039 if (obj
->tiling_mode
== I915_TILING_Y
)
3040 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
3041 val
|= I830_FENCE_SIZE_BITS(size
);
3042 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
3043 val
|= I830_FENCE_REG_VALID
;
3047 I915_WRITE(FENCE_REG_830_0
+ reg
* 4, val
);
3048 POSTING_READ(FENCE_REG_830_0
+ reg
* 4);
3051 inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object
*obj
)
3053 return obj
&& obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
;
3056 static void i915_gem_write_fence(struct drm_device
*dev
, int reg
,
3057 struct drm_i915_gem_object
*obj
)
3059 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3061 /* Ensure that all CPU reads are completed before installing a fence
3062 * and all writes before removing the fence.
3064 if (i915_gem_object_needs_mb(dev_priv
->fence_regs
[reg
].obj
))
3067 WARN(obj
&& (!obj
->stride
|| !obj
->tiling_mode
),
3068 "bogus fence setup with stride: 0x%x, tiling mode: %i\n",
3069 obj
->stride
, obj
->tiling_mode
);
3071 switch (INTEL_INFO(dev
)->gen
) {
3076 case 4: i965_write_fence_reg(dev
, reg
, obj
); break;
3077 case 3: i915_write_fence_reg(dev
, reg
, obj
); break;
3078 case 2: i830_write_fence_reg(dev
, reg
, obj
); break;
3082 /* And similarly be paranoid that no direct access to this region
3083 * is reordered to before the fence is installed.
3085 if (i915_gem_object_needs_mb(obj
))
3089 static inline int fence_number(struct drm_i915_private
*dev_priv
,
3090 struct drm_i915_fence_reg
*fence
)
3092 return fence
- dev_priv
->fence_regs
;
3095 static void i915_gem_object_update_fence(struct drm_i915_gem_object
*obj
,
3096 struct drm_i915_fence_reg
*fence
,
3099 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
3100 int reg
= fence_number(dev_priv
, fence
);
3102 i915_gem_write_fence(obj
->base
.dev
, reg
, enable
? obj
: NULL
);
3105 obj
->fence_reg
= reg
;
3107 list_move_tail(&fence
->lru_list
, &dev_priv
->mm
.fence_list
);
3109 obj
->fence_reg
= I915_FENCE_REG_NONE
;
3111 list_del_init(&fence
->lru_list
);
3113 obj
->fence_dirty
= false;
3117 i915_gem_object_wait_fence(struct drm_i915_gem_object
*obj
)
3119 if (obj
->last_fenced_seqno
) {
3120 int ret
= i915_wait_seqno(obj
->ring
, obj
->last_fenced_seqno
);
3124 obj
->last_fenced_seqno
= 0;
3127 obj
->fenced_gpu_access
= false;
3132 i915_gem_object_put_fence(struct drm_i915_gem_object
*obj
)
3134 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
3135 struct drm_i915_fence_reg
*fence
;
3138 ret
= i915_gem_object_wait_fence(obj
);
3142 if (obj
->fence_reg
== I915_FENCE_REG_NONE
)
3145 fence
= &dev_priv
->fence_regs
[obj
->fence_reg
];
3147 i915_gem_object_fence_lost(obj
);
3148 i915_gem_object_update_fence(obj
, fence
, false);
3153 static struct drm_i915_fence_reg
*
3154 i915_find_fence_reg(struct drm_device
*dev
)
3156 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3157 struct drm_i915_fence_reg
*reg
, *avail
;
3160 /* First try to find a free reg */
3162 for (i
= dev_priv
->fence_reg_start
; i
< dev_priv
->num_fence_regs
; i
++) {
3163 reg
= &dev_priv
->fence_regs
[i
];
3167 if (!reg
->pin_count
)
3174 /* None available, try to steal one or wait for a user to finish */
3175 list_for_each_entry(reg
, &dev_priv
->mm
.fence_list
, lru_list
) {
3183 /* Wait for completion of pending flips which consume fences */
3184 if (intel_has_pending_fb_unpin(dev
))
3185 return ERR_PTR(-EAGAIN
);
3187 return ERR_PTR(-EDEADLK
);
3191 * i915_gem_object_get_fence - set up fencing for an object
3192 * @obj: object to map through a fence reg
3194 * When mapping objects through the GTT, userspace wants to be able to write
3195 * to them without having to worry about swizzling if the object is tiled.
3196 * This function walks the fence regs looking for a free one for @obj,
3197 * stealing one if it can't find any.
3199 * It then sets up the reg based on the object's properties: address, pitch
3200 * and tiling format.
3202 * For an untiled surface, this removes any existing fence.
3205 i915_gem_object_get_fence(struct drm_i915_gem_object
*obj
)
3207 struct drm_device
*dev
= obj
->base
.dev
;
3208 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3209 bool enable
= obj
->tiling_mode
!= I915_TILING_NONE
;
3210 struct drm_i915_fence_reg
*reg
;
3213 /* Have we updated the tiling parameters upon the object and so
3214 * will need to serialise the write to the associated fence register?
3216 if (obj
->fence_dirty
) {
3217 ret
= i915_gem_object_wait_fence(obj
);
3222 /* Just update our place in the LRU if our fence is getting reused. */
3223 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
3224 reg
= &dev_priv
->fence_regs
[obj
->fence_reg
];
3225 if (!obj
->fence_dirty
) {
3226 list_move_tail(®
->lru_list
,
3227 &dev_priv
->mm
.fence_list
);
3230 } else if (enable
) {
3231 reg
= i915_find_fence_reg(dev
);
3233 return PTR_ERR(reg
);
3236 struct drm_i915_gem_object
*old
= reg
->obj
;
3238 ret
= i915_gem_object_wait_fence(old
);
3242 i915_gem_object_fence_lost(old
);
3247 i915_gem_object_update_fence(obj
, reg
, enable
);
3252 static bool i915_gem_valid_gtt_space(struct drm_device
*dev
,
3253 struct drm_mm_node
*gtt_space
,
3254 unsigned long cache_level
)
3256 struct drm_mm_node
*other
;
3258 /* On non-LLC machines we have to be careful when putting differing
3259 * types of snoopable memory together to avoid the prefetcher
3260 * crossing memory domains and dying.
3265 if (!drm_mm_node_allocated(gtt_space
))
3268 if (list_empty(>t_space
->node_list
))
3271 other
= list_entry(gtt_space
->node_list
.prev
, struct drm_mm_node
, node_list
);
3272 if (other
->allocated
&& !other
->hole_follows
&& other
->color
!= cache_level
)
3275 other
= list_entry(gtt_space
->node_list
.next
, struct drm_mm_node
, node_list
);
3276 if (other
->allocated
&& !gtt_space
->hole_follows
&& other
->color
!= cache_level
)
3282 static void i915_gem_verify_gtt(struct drm_device
*dev
)
3285 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3286 struct drm_i915_gem_object
*obj
;
3289 list_for_each_entry(obj
, &dev_priv
->mm
.gtt_list
, global_list
) {
3290 if (obj
->gtt_space
== NULL
) {
3291 printk(KERN_ERR
"object found on GTT list with no space reserved\n");
3296 if (obj
->cache_level
!= obj
->gtt_space
->color
) {
3297 printk(KERN_ERR
"object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n",
3298 i915_gem_obj_ggtt_offset(obj
),
3299 i915_gem_obj_ggtt_offset(obj
) + i915_gem_obj_ggtt_size(obj
),
3301 obj
->gtt_space
->color
);
3306 if (!i915_gem_valid_gtt_space(dev
,
3308 obj
->cache_level
)) {
3309 printk(KERN_ERR
"invalid GTT space found at [%08lx, %08lx] - color=%x\n",
3310 i915_gem_obj_ggtt_offset(obj
),
3311 i915_gem_obj_ggtt_offset(obj
) + i915_gem_obj_ggtt_size(obj
),
3323 * Finds free space in the GTT aperture and binds the object there.
3325 static struct i915_vma
*
3326 i915_gem_object_bind_to_vm(struct drm_i915_gem_object
*obj
,
3327 struct i915_address_space
*vm
,
3331 struct drm_device
*dev
= obj
->base
.dev
;
3332 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3333 u32 size
, fence_size
, fence_alignment
, unfenced_alignment
;
3335 flags
& PIN_MAPPABLE
? dev_priv
->gtt
.mappable_end
: vm
->total
;
3336 struct i915_vma
*vma
;
3339 fence_size
= i915_gem_get_gtt_size(dev
,
3342 fence_alignment
= i915_gem_get_gtt_alignment(dev
,
3344 obj
->tiling_mode
, true);
3345 unfenced_alignment
=
3346 i915_gem_get_gtt_alignment(dev
,
3348 obj
->tiling_mode
, false);
3351 alignment
= flags
& PIN_MAPPABLE
? fence_alignment
:
3353 if (flags
& PIN_MAPPABLE
&& alignment
& (fence_alignment
- 1)) {
3354 DRM_DEBUG("Invalid object alignment requested %u\n", alignment
);
3355 return ERR_PTR(-EINVAL
);
3358 size
= flags
& PIN_MAPPABLE
? fence_size
: obj
->base
.size
;
3360 /* If the object is bigger than the entire aperture, reject it early
3361 * before evicting everything in a vain attempt to find space.
3363 if (obj
->base
.size
> gtt_max
) {
3364 DRM_DEBUG("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%zu\n",
3366 flags
& PIN_MAPPABLE
? "mappable" : "total",
3368 return ERR_PTR(-E2BIG
);
3371 ret
= i915_gem_object_get_pages(obj
);
3373 return ERR_PTR(ret
);
3375 i915_gem_object_pin_pages(obj
);
3377 vma
= i915_gem_obj_lookup_or_create_vma(obj
, vm
);
3382 ret
= drm_mm_insert_node_in_range_generic(&vm
->mm
, &vma
->node
,
3384 obj
->cache_level
, 0, gtt_max
,
3385 DRM_MM_SEARCH_DEFAULT
,
3386 DRM_MM_CREATE_DEFAULT
);
3388 ret
= i915_gem_evict_something(dev
, vm
, size
, alignment
,
3389 obj
->cache_level
, flags
);
3395 if (WARN_ON(!i915_gem_valid_gtt_space(dev
, &vma
->node
,
3396 obj
->cache_level
))) {
3398 goto err_remove_node
;
3401 ret
= i915_gem_gtt_prepare_object(obj
);
3403 goto err_remove_node
;
3405 list_move_tail(&obj
->global_list
, &dev_priv
->mm
.bound_list
);
3406 list_add_tail(&vma
->mm_list
, &vm
->inactive_list
);
3408 if (i915_is_ggtt(vm
)) {
3409 bool mappable
, fenceable
;
3411 fenceable
= (vma
->node
.size
== fence_size
&&
3412 (vma
->node
.start
& (fence_alignment
- 1)) == 0);
3414 mappable
= (vma
->node
.start
+ obj
->base
.size
<=
3415 dev_priv
->gtt
.mappable_end
);
3417 obj
->map_and_fenceable
= mappable
&& fenceable
;
3420 WARN_ON(flags
& PIN_MAPPABLE
&& !obj
->map_and_fenceable
);
3422 trace_i915_vma_bind(vma
, flags
);
3423 vma
->bind_vma(vma
, obj
->cache_level
,
3424 flags
& (PIN_MAPPABLE
| PIN_GLOBAL
) ? GLOBAL_BIND
: 0);
3426 i915_gem_verify_gtt(dev
);
3430 drm_mm_remove_node(&vma
->node
);
3432 i915_gem_vma_destroy(vma
);
3435 i915_gem_object_unpin_pages(obj
);
3440 i915_gem_clflush_object(struct drm_i915_gem_object
*obj
,
3443 /* If we don't have a page list set up, then we're not pinned
3444 * to GPU, and we can ignore the cache flush because it'll happen
3445 * again at bind time.
3447 if (obj
->pages
== NULL
)
3451 * Stolen memory is always coherent with the GPU as it is explicitly
3452 * marked as wc by the system, or the system is cache-coherent.
3457 /* If the GPU is snooping the contents of the CPU cache,
3458 * we do not need to manually clear the CPU cache lines. However,
3459 * the caches are only snooped when the render cache is
3460 * flushed/invalidated. As we always have to emit invalidations
3461 * and flushes when moving into and out of the RENDER domain, correct
3462 * snooping behaviour occurs naturally as the result of our domain
3465 if (!force
&& cpu_cache_is_coherent(obj
->base
.dev
, obj
->cache_level
))
3468 trace_i915_gem_object_clflush(obj
);
3469 drm_clflush_sg(obj
->pages
);
3474 /** Flushes the GTT write domain for the object if it's dirty. */
3476 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
)
3478 uint32_t old_write_domain
;
3480 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_GTT
)
3483 /* No actual flushing is required for the GTT write domain. Writes
3484 * to it immediately go to main memory as far as we know, so there's
3485 * no chipset flush. It also doesn't land in render cache.
3487 * However, we do have to enforce the order so that all writes through
3488 * the GTT land before any writes to the device, such as updates to
3493 old_write_domain
= obj
->base
.write_domain
;
3494 obj
->base
.write_domain
= 0;
3496 trace_i915_gem_object_change_domain(obj
,
3497 obj
->base
.read_domains
,
3501 /** Flushes the CPU write domain for the object if it's dirty. */
3503 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
,
3506 uint32_t old_write_domain
;
3508 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
)
3511 if (i915_gem_clflush_object(obj
, force
))
3512 i915_gem_chipset_flush(obj
->base
.dev
);
3514 old_write_domain
= obj
->base
.write_domain
;
3515 obj
->base
.write_domain
= 0;
3517 trace_i915_gem_object_change_domain(obj
,
3518 obj
->base
.read_domains
,
3523 * Moves a single object to the GTT read, and possibly write domain.
3525 * This function returns when the move is complete, including waiting on
3529 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
, bool write
)
3531 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
3532 uint32_t old_write_domain
, old_read_domains
;
3535 /* Not valid to be called on unbound objects. */
3536 if (!i915_gem_obj_bound_any(obj
))
3539 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_GTT
)
3542 ret
= i915_gem_object_wait_rendering(obj
, !write
);
3546 i915_gem_object_flush_cpu_write_domain(obj
, false);
3548 /* Serialise direct access to this object with the barriers for
3549 * coherent writes from the GPU, by effectively invalidating the
3550 * GTT domain upon first access.
3552 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
) == 0)
3555 old_write_domain
= obj
->base
.write_domain
;
3556 old_read_domains
= obj
->base
.read_domains
;
3558 /* It should now be out of any other write domains, and we can update
3559 * the domain values for our changes.
3561 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
3562 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
3564 obj
->base
.read_domains
= I915_GEM_DOMAIN_GTT
;
3565 obj
->base
.write_domain
= I915_GEM_DOMAIN_GTT
;
3569 trace_i915_gem_object_change_domain(obj
,
3573 /* And bump the LRU for this access */
3574 if (i915_gem_object_is_inactive(obj
)) {
3575 struct i915_vma
*vma
= i915_gem_obj_to_ggtt(obj
);
3577 list_move_tail(&vma
->mm_list
,
3578 &dev_priv
->gtt
.base
.inactive_list
);
3585 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
3586 enum i915_cache_level cache_level
)
3588 struct drm_device
*dev
= obj
->base
.dev
;
3589 struct i915_vma
*vma
, *next
;
3592 if (obj
->cache_level
== cache_level
)
3595 if (i915_gem_obj_is_pinned(obj
)) {
3596 DRM_DEBUG("can not change the cache level of pinned objects\n");
3600 list_for_each_entry_safe(vma
, next
, &obj
->vma_list
, vma_link
) {
3601 if (!i915_gem_valid_gtt_space(dev
, &vma
->node
, cache_level
)) {
3602 ret
= i915_vma_unbind(vma
);
3608 if (i915_gem_obj_bound_any(obj
)) {
3609 ret
= i915_gem_object_finish_gpu(obj
);
3613 i915_gem_object_finish_gtt(obj
);
3615 /* Before SandyBridge, you could not use tiling or fence
3616 * registers with snooped memory, so relinquish any fences
3617 * currently pointing to our region in the aperture.
3619 if (INTEL_INFO(dev
)->gen
< 6) {
3620 ret
= i915_gem_object_put_fence(obj
);
3625 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
3626 if (drm_mm_node_allocated(&vma
->node
))
3627 vma
->bind_vma(vma
, cache_level
,
3628 obj
->has_global_gtt_mapping
? GLOBAL_BIND
: 0);
3631 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
3632 vma
->node
.color
= cache_level
;
3633 obj
->cache_level
= cache_level
;
3635 if (cpu_write_needs_clflush(obj
)) {
3636 u32 old_read_domains
, old_write_domain
;
3638 /* If we're coming from LLC cached, then we haven't
3639 * actually been tracking whether the data is in the
3640 * CPU cache or not, since we only allow one bit set
3641 * in obj->write_domain and have been skipping the clflushes.
3642 * Just set it to the CPU cache for now.
3644 WARN_ON(obj
->base
.write_domain
& ~I915_GEM_DOMAIN_CPU
);
3646 old_read_domains
= obj
->base
.read_domains
;
3647 old_write_domain
= obj
->base
.write_domain
;
3649 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
3650 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
3652 trace_i915_gem_object_change_domain(obj
,
3657 i915_gem_verify_gtt(dev
);
3661 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
3662 struct drm_file
*file
)
3664 struct drm_i915_gem_caching
*args
= data
;
3665 struct drm_i915_gem_object
*obj
;
3668 ret
= i915_mutex_lock_interruptible(dev
);
3672 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3673 if (&obj
->base
== NULL
) {
3678 switch (obj
->cache_level
) {
3679 case I915_CACHE_LLC
:
3680 case I915_CACHE_L3_LLC
:
3681 args
->caching
= I915_CACHING_CACHED
;
3685 args
->caching
= I915_CACHING_DISPLAY
;
3689 args
->caching
= I915_CACHING_NONE
;
3693 drm_gem_object_unreference(&obj
->base
);
3695 mutex_unlock(&dev
->struct_mutex
);
3699 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
3700 struct drm_file
*file
)
3702 struct drm_i915_gem_caching
*args
= data
;
3703 struct drm_i915_gem_object
*obj
;
3704 enum i915_cache_level level
;
3707 switch (args
->caching
) {
3708 case I915_CACHING_NONE
:
3709 level
= I915_CACHE_NONE
;
3711 case I915_CACHING_CACHED
:
3712 level
= I915_CACHE_LLC
;
3714 case I915_CACHING_DISPLAY
:
3715 level
= HAS_WT(dev
) ? I915_CACHE_WT
: I915_CACHE_NONE
;
3721 ret
= i915_mutex_lock_interruptible(dev
);
3725 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3726 if (&obj
->base
== NULL
) {
3731 ret
= i915_gem_object_set_cache_level(obj
, level
);
3733 drm_gem_object_unreference(&obj
->base
);
3735 mutex_unlock(&dev
->struct_mutex
);
3739 static bool is_pin_display(struct drm_i915_gem_object
*obj
)
3741 /* There are 3 sources that pin objects:
3742 * 1. The display engine (scanouts, sprites, cursors);
3743 * 2. Reservations for execbuffer;
3746 * We can ignore reservations as we hold the struct_mutex and
3747 * are only called outside of the reservation path. The user
3748 * can only increment pin_count once, and so if after
3749 * subtracting the potential reference by the user, any pin_count
3750 * remains, it must be due to another use by the display engine.
3752 return i915_gem_obj_to_ggtt(obj
)->pin_count
- !!obj
->user_pin_count
;
3756 * Prepare buffer for display plane (scanout, cursors, etc).
3757 * Can be called from an uninterruptible phase (modesetting) and allows
3758 * any flushes to be pipelined (for pageflips).
3761 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
3763 struct intel_ring_buffer
*pipelined
)
3765 u32 old_read_domains
, old_write_domain
;
3768 if (pipelined
!= obj
->ring
) {
3769 ret
= i915_gem_object_sync(obj
, pipelined
);
3774 /* Mark the pin_display early so that we account for the
3775 * display coherency whilst setting up the cache domains.
3777 obj
->pin_display
= true;
3779 /* The display engine is not coherent with the LLC cache on gen6. As
3780 * a result, we make sure that the pinning that is about to occur is
3781 * done with uncached PTEs. This is lowest common denominator for all
3784 * However for gen6+, we could do better by using the GFDT bit instead
3785 * of uncaching, which would allow us to flush all the LLC-cached data
3786 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3788 ret
= i915_gem_object_set_cache_level(obj
,
3789 HAS_WT(obj
->base
.dev
) ? I915_CACHE_WT
: I915_CACHE_NONE
);
3791 goto err_unpin_display
;
3793 /* As the user may map the buffer once pinned in the display plane
3794 * (e.g. libkms for the bootup splash), we have to ensure that we
3795 * always use map_and_fenceable for all scanout buffers.
3797 ret
= i915_gem_obj_ggtt_pin(obj
, alignment
, PIN_MAPPABLE
);
3799 goto err_unpin_display
;
3801 i915_gem_object_flush_cpu_write_domain(obj
, true);
3803 old_write_domain
= obj
->base
.write_domain
;
3804 old_read_domains
= obj
->base
.read_domains
;
3806 /* It should now be out of any other write domains, and we can update
3807 * the domain values for our changes.
3809 obj
->base
.write_domain
= 0;
3810 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
3812 trace_i915_gem_object_change_domain(obj
,
3819 obj
->pin_display
= is_pin_display(obj
);
3824 i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object
*obj
)
3826 i915_gem_object_ggtt_unpin(obj
);
3827 obj
->pin_display
= is_pin_display(obj
);
3831 i915_gem_object_finish_gpu(struct drm_i915_gem_object
*obj
)
3835 if ((obj
->base
.read_domains
& I915_GEM_GPU_DOMAINS
) == 0)
3838 ret
= i915_gem_object_wait_rendering(obj
, false);
3842 /* Ensure that we invalidate the GPU's caches and TLBs. */
3843 obj
->base
.read_domains
&= ~I915_GEM_GPU_DOMAINS
;
3848 * Moves a single object to the CPU read, and possibly write domain.
3850 * This function returns when the move is complete, including waiting on
3854 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
)
3856 uint32_t old_write_domain
, old_read_domains
;
3859 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_CPU
)
3862 ret
= i915_gem_object_wait_rendering(obj
, !write
);
3866 i915_gem_object_flush_gtt_write_domain(obj
);
3868 old_write_domain
= obj
->base
.write_domain
;
3869 old_read_domains
= obj
->base
.read_domains
;
3871 /* Flush the CPU cache if it's still invalid. */
3872 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) == 0) {
3873 i915_gem_clflush_object(obj
, false);
3875 obj
->base
.read_domains
|= I915_GEM_DOMAIN_CPU
;
3878 /* It should now be out of any other write domains, and we can update
3879 * the domain values for our changes.
3881 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
3883 /* If we're writing through the CPU, then the GPU read domains will
3884 * need to be invalidated at next use.
3887 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
3888 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
3891 trace_i915_gem_object_change_domain(obj
,
3898 /* Throttle our rendering by waiting until the ring has completed our requests
3899 * emitted over 20 msec ago.
3901 * Note that if we were to use the current jiffies each time around the loop,
3902 * we wouldn't escape the function with any frames outstanding if the time to
3903 * render a frame was over 20ms.
3905 * This should get us reasonable parallelism between CPU and GPU but also
3906 * relatively low latency when blocking on a particular request to finish.
3909 i915_gem_ring_throttle(struct drm_device
*dev
, struct drm_file
*file
)
3911 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3912 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
3913 unsigned long recent_enough
= jiffies
- msecs_to_jiffies(20);
3914 struct drm_i915_gem_request
*request
;
3915 struct intel_ring_buffer
*ring
= NULL
;
3916 unsigned reset_counter
;
3920 ret
= i915_gem_wait_for_error(&dev_priv
->gpu_error
);
3924 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, false);
3928 spin_lock(&file_priv
->mm
.lock
);
3929 list_for_each_entry(request
, &file_priv
->mm
.request_list
, client_list
) {
3930 if (time_after_eq(request
->emitted_jiffies
, recent_enough
))
3933 ring
= request
->ring
;
3934 seqno
= request
->seqno
;
3936 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
3937 spin_unlock(&file_priv
->mm
.lock
);
3942 ret
= __wait_seqno(ring
, seqno
, reset_counter
, true, NULL
, NULL
);
3944 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, 0);
3950 i915_gem_object_pin(struct drm_i915_gem_object
*obj
,
3951 struct i915_address_space
*vm
,
3955 struct i915_vma
*vma
;
3958 if (WARN_ON(flags
& (PIN_GLOBAL
| PIN_MAPPABLE
) && !i915_is_ggtt(vm
)))
3961 vma
= i915_gem_obj_to_vma(obj
, vm
);
3963 if (WARN_ON(vma
->pin_count
== DRM_I915_GEM_OBJECT_MAX_PIN_COUNT
))
3967 vma
->node
.start
& (alignment
- 1)) ||
3968 (flags
& PIN_MAPPABLE
&& !obj
->map_and_fenceable
)) {
3969 WARN(vma
->pin_count
,
3970 "bo is already pinned with incorrect alignment:"
3971 " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d,"
3972 " obj->map_and_fenceable=%d\n",
3973 i915_gem_obj_offset(obj
, vm
), alignment
,
3974 flags
& PIN_MAPPABLE
,
3975 obj
->map_and_fenceable
);
3976 ret
= i915_vma_unbind(vma
);
3984 if (vma
== NULL
|| !drm_mm_node_allocated(&vma
->node
)) {
3985 vma
= i915_gem_object_bind_to_vm(obj
, vm
, alignment
, flags
);
3987 return PTR_ERR(vma
);
3990 if (flags
& PIN_GLOBAL
&& !obj
->has_global_gtt_mapping
)
3991 vma
->bind_vma(vma
, obj
->cache_level
, GLOBAL_BIND
);
3994 if (flags
& PIN_MAPPABLE
)
3995 obj
->pin_mappable
|= true;
4001 i915_gem_object_ggtt_unpin(struct drm_i915_gem_object
*obj
)
4003 struct i915_vma
*vma
= i915_gem_obj_to_ggtt(obj
);
4006 BUG_ON(vma
->pin_count
== 0);
4007 BUG_ON(!i915_gem_obj_ggtt_bound(obj
));
4009 if (--vma
->pin_count
== 0)
4010 obj
->pin_mappable
= false;
4014 i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
4015 struct drm_file
*file
)
4017 struct drm_i915_gem_pin
*args
= data
;
4018 struct drm_i915_gem_object
*obj
;
4021 if (INTEL_INFO(dev
)->gen
>= 6)
4024 ret
= i915_mutex_lock_interruptible(dev
);
4028 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
4029 if (&obj
->base
== NULL
) {
4034 if (obj
->madv
!= I915_MADV_WILLNEED
) {
4035 DRM_DEBUG("Attempting to pin a purgeable buffer\n");
4040 if (obj
->pin_filp
!= NULL
&& obj
->pin_filp
!= file
) {
4041 DRM_DEBUG("Already pinned in i915_gem_pin_ioctl(): %d\n",
4047 if (obj
->user_pin_count
== ULONG_MAX
) {
4052 if (obj
->user_pin_count
== 0) {
4053 ret
= i915_gem_obj_ggtt_pin(obj
, args
->alignment
, PIN_MAPPABLE
);
4058 obj
->user_pin_count
++;
4059 obj
->pin_filp
= file
;
4061 args
->offset
= i915_gem_obj_ggtt_offset(obj
);
4063 drm_gem_object_unreference(&obj
->base
);
4065 mutex_unlock(&dev
->struct_mutex
);
4070 i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
4071 struct drm_file
*file
)
4073 struct drm_i915_gem_pin
*args
= data
;
4074 struct drm_i915_gem_object
*obj
;
4077 ret
= i915_mutex_lock_interruptible(dev
);
4081 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
4082 if (&obj
->base
== NULL
) {
4087 if (obj
->pin_filp
!= file
) {
4088 DRM_DEBUG("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4093 obj
->user_pin_count
--;
4094 if (obj
->user_pin_count
== 0) {
4095 obj
->pin_filp
= NULL
;
4096 i915_gem_object_ggtt_unpin(obj
);
4100 drm_gem_object_unreference(&obj
->base
);
4102 mutex_unlock(&dev
->struct_mutex
);
4107 i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
4108 struct drm_file
*file
)
4110 struct drm_i915_gem_busy
*args
= data
;
4111 struct drm_i915_gem_object
*obj
;
4114 ret
= i915_mutex_lock_interruptible(dev
);
4118 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
4119 if (&obj
->base
== NULL
) {
4124 /* Count all active objects as busy, even if they are currently not used
4125 * by the gpu. Users of this interface expect objects to eventually
4126 * become non-busy without any further actions, therefore emit any
4127 * necessary flushes here.
4129 ret
= i915_gem_object_flush_active(obj
);
4131 args
->busy
= obj
->active
;
4133 BUILD_BUG_ON(I915_NUM_RINGS
> 16);
4134 args
->busy
|= intel_ring_flag(obj
->ring
) << 16;
4137 drm_gem_object_unreference(&obj
->base
);
4139 mutex_unlock(&dev
->struct_mutex
);
4144 i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
4145 struct drm_file
*file_priv
)
4147 return i915_gem_ring_throttle(dev
, file_priv
);
4151 i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
4152 struct drm_file
*file_priv
)
4154 struct drm_i915_gem_madvise
*args
= data
;
4155 struct drm_i915_gem_object
*obj
;
4158 switch (args
->madv
) {
4159 case I915_MADV_DONTNEED
:
4160 case I915_MADV_WILLNEED
:
4166 ret
= i915_mutex_lock_interruptible(dev
);
4170 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file_priv
, args
->handle
));
4171 if (&obj
->base
== NULL
) {
4176 if (i915_gem_obj_is_pinned(obj
)) {
4181 if (obj
->madv
!= __I915_MADV_PURGED
)
4182 obj
->madv
= args
->madv
;
4184 /* if the object is no longer attached, discard its backing storage */
4185 if (i915_gem_object_is_purgeable(obj
) && obj
->pages
== NULL
)
4186 i915_gem_object_truncate(obj
);
4188 args
->retained
= obj
->madv
!= __I915_MADV_PURGED
;
4191 drm_gem_object_unreference(&obj
->base
);
4193 mutex_unlock(&dev
->struct_mutex
);
4197 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
4198 const struct drm_i915_gem_object_ops
*ops
)
4200 INIT_LIST_HEAD(&obj
->global_list
);
4201 INIT_LIST_HEAD(&obj
->ring_list
);
4202 INIT_LIST_HEAD(&obj
->obj_exec_link
);
4203 INIT_LIST_HEAD(&obj
->vma_list
);
4207 obj
->fence_reg
= I915_FENCE_REG_NONE
;
4208 obj
->madv
= I915_MADV_WILLNEED
;
4209 /* Avoid an unnecessary call to unbind on the first bind. */
4210 obj
->map_and_fenceable
= true;
4212 i915_gem_info_add_obj(obj
->base
.dev
->dev_private
, obj
->base
.size
);
4215 static const struct drm_i915_gem_object_ops i915_gem_object_ops
= {
4216 .get_pages
= i915_gem_object_get_pages_gtt
,
4217 .put_pages
= i915_gem_object_put_pages_gtt
,
4220 struct drm_i915_gem_object
*i915_gem_alloc_object(struct drm_device
*dev
,
4223 struct drm_i915_gem_object
*obj
;
4224 struct address_space
*mapping
;
4227 obj
= i915_gem_object_alloc(dev
);
4231 if (drm_gem_object_init(dev
, &obj
->base
, size
) != 0) {
4232 i915_gem_object_free(obj
);
4236 mask
= GFP_HIGHUSER
| __GFP_RECLAIMABLE
;
4237 if (IS_CRESTLINE(dev
) || IS_BROADWATER(dev
)) {
4238 /* 965gm cannot relocate objects above 4GiB. */
4239 mask
&= ~__GFP_HIGHMEM
;
4240 mask
|= __GFP_DMA32
;
4243 mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
4244 mapping_set_gfp_mask(mapping
, mask
);
4246 i915_gem_object_init(obj
, &i915_gem_object_ops
);
4248 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
4249 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
4252 /* On some devices, we can have the GPU use the LLC (the CPU
4253 * cache) for about a 10% performance improvement
4254 * compared to uncached. Graphics requests other than
4255 * display scanout are coherent with the CPU in
4256 * accessing this cache. This means in this mode we
4257 * don't need to clflush on the CPU side, and on the
4258 * GPU side we only need to flush internal caches to
4259 * get data visible to the CPU.
4261 * However, we maintain the display planes as UC, and so
4262 * need to rebind when first used as such.
4264 obj
->cache_level
= I915_CACHE_LLC
;
4266 obj
->cache_level
= I915_CACHE_NONE
;
4268 trace_i915_gem_object_create(obj
);
4273 void i915_gem_free_object(struct drm_gem_object
*gem_obj
)
4275 struct drm_i915_gem_object
*obj
= to_intel_bo(gem_obj
);
4276 struct drm_device
*dev
= obj
->base
.dev
;
4277 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4278 struct i915_vma
*vma
, *next
;
4280 intel_runtime_pm_get(dev_priv
);
4282 trace_i915_gem_object_destroy(obj
);
4284 list_for_each_entry_safe(vma
, next
, &obj
->vma_list
, vma_link
) {
4288 ret
= i915_vma_unbind(vma
);
4289 if (WARN_ON(ret
== -ERESTARTSYS
)) {
4290 bool was_interruptible
;
4292 was_interruptible
= dev_priv
->mm
.interruptible
;
4293 dev_priv
->mm
.interruptible
= false;
4295 WARN_ON(i915_vma_unbind(vma
));
4297 dev_priv
->mm
.interruptible
= was_interruptible
;
4301 i915_gem_object_detach_phys(obj
);
4303 /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
4304 * before progressing. */
4306 i915_gem_object_unpin_pages(obj
);
4308 if (WARN_ON(obj
->pages_pin_count
))
4309 obj
->pages_pin_count
= 0;
4310 i915_gem_object_put_pages(obj
);
4311 i915_gem_object_free_mmap_offset(obj
);
4312 i915_gem_object_release_stolen(obj
);
4316 if (obj
->base
.import_attach
)
4317 drm_prime_gem_destroy(&obj
->base
, NULL
);
4319 drm_gem_object_release(&obj
->base
);
4320 i915_gem_info_remove_obj(dev_priv
, obj
->base
.size
);
4323 i915_gem_object_free(obj
);
4325 intel_runtime_pm_put(dev_priv
);
4328 struct i915_vma
*i915_gem_obj_to_vma(struct drm_i915_gem_object
*obj
,
4329 struct i915_address_space
*vm
)
4331 struct i915_vma
*vma
;
4332 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
4339 void i915_gem_vma_destroy(struct i915_vma
*vma
)
4341 WARN_ON(vma
->node
.allocated
);
4343 /* Keep the vma as a placeholder in the execbuffer reservation lists */
4344 if (!list_empty(&vma
->exec_list
))
4347 list_del(&vma
->vma_link
);
4353 i915_gem_suspend(struct drm_device
*dev
)
4355 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4358 mutex_lock(&dev
->struct_mutex
);
4359 if (dev_priv
->ums
.mm_suspended
)
4362 ret
= i915_gpu_idle(dev
);
4366 i915_gem_retire_requests(dev
);
4368 /* Under UMS, be paranoid and evict. */
4369 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
4370 i915_gem_evict_everything(dev
);
4372 i915_kernel_lost_context(dev
);
4373 i915_gem_cleanup_ringbuffer(dev
);
4375 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4376 * We need to replace this with a semaphore, or something.
4377 * And not confound ums.mm_suspended!
4379 dev_priv
->ums
.mm_suspended
= !drm_core_check_feature(dev
,
4381 mutex_unlock(&dev
->struct_mutex
);
4383 del_timer_sync(&dev_priv
->gpu_error
.hangcheck_timer
);
4384 cancel_delayed_work_sync(&dev_priv
->mm
.retire_work
);
4385 cancel_delayed_work_sync(&dev_priv
->mm
.idle_work
);
4390 mutex_unlock(&dev
->struct_mutex
);
4394 int i915_gem_l3_remap(struct intel_ring_buffer
*ring
, int slice
)
4396 struct drm_device
*dev
= ring
->dev
;
4397 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4398 u32 reg_base
= GEN7_L3LOG_BASE
+ (slice
* 0x200);
4399 u32
*remap_info
= dev_priv
->l3_parity
.remap_info
[slice
];
4402 if (!HAS_L3_DPF(dev
) || !remap_info
)
4405 ret
= intel_ring_begin(ring
, GEN7_L3LOG_SIZE
/ 4 * 3);
4410 * Note: We do not worry about the concurrent register cacheline hang
4411 * here because no other code should access these registers other than
4412 * at initialization time.
4414 for (i
= 0; i
< GEN7_L3LOG_SIZE
; i
+= 4) {
4415 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
4416 intel_ring_emit(ring
, reg_base
+ i
);
4417 intel_ring_emit(ring
, remap_info
[i
/4]);
4420 intel_ring_advance(ring
);
4425 void i915_gem_init_swizzling(struct drm_device
*dev
)
4427 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4429 if (INTEL_INFO(dev
)->gen
< 5 ||
4430 dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_NONE
)
4433 I915_WRITE(DISP_ARB_CTL
, I915_READ(DISP_ARB_CTL
) |
4434 DISP_TILE_SURFACE_SWIZZLING
);
4439 I915_WRITE(TILECTL
, I915_READ(TILECTL
) | TILECTL_SWZCTL
);
4441 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB
));
4442 else if (IS_GEN7(dev
))
4443 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB
));
4444 else if (IS_GEN8(dev
))
4445 I915_WRITE(GAMTARBMODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW
));
4451 intel_enable_blt(struct drm_device
*dev
)
4456 /* The blitter was dysfunctional on early prototypes */
4457 if (IS_GEN6(dev
) && dev
->pdev
->revision
< 8) {
4458 DRM_INFO("BLT not supported on this pre-production hardware;"
4459 " graphics performance will be degraded.\n");
4466 static int i915_gem_init_rings(struct drm_device
*dev
)
4468 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4471 ret
= intel_init_render_ring_buffer(dev
);
4476 ret
= intel_init_bsd_ring_buffer(dev
);
4478 goto cleanup_render_ring
;
4481 if (intel_enable_blt(dev
)) {
4482 ret
= intel_init_blt_ring_buffer(dev
);
4484 goto cleanup_bsd_ring
;
4487 if (HAS_VEBOX(dev
)) {
4488 ret
= intel_init_vebox_ring_buffer(dev
);
4490 goto cleanup_blt_ring
;
4494 ret
= i915_gem_set_seqno(dev
, ((u32
)~0 - 0x1000));
4496 goto cleanup_vebox_ring
;
4501 intel_cleanup_ring_buffer(&dev_priv
->ring
[VECS
]);
4503 intel_cleanup_ring_buffer(&dev_priv
->ring
[BCS
]);
4505 intel_cleanup_ring_buffer(&dev_priv
->ring
[VCS
]);
4506 cleanup_render_ring
:
4507 intel_cleanup_ring_buffer(&dev_priv
->ring
[RCS
]);
4513 i915_gem_init_hw(struct drm_device
*dev
)
4515 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4518 if (INTEL_INFO(dev
)->gen
< 6 && !intel_enable_gtt())
4521 if (dev_priv
->ellc_size
)
4522 I915_WRITE(HSW_IDICR
, I915_READ(HSW_IDICR
) | IDIHASHMSK(0xf));
4524 if (IS_HASWELL(dev
))
4525 I915_WRITE(MI_PREDICATE_RESULT_2
, IS_HSW_GT3(dev
) ?
4526 LOWER_SLICE_ENABLED
: LOWER_SLICE_DISABLED
);
4528 if (HAS_PCH_NOP(dev
)) {
4529 if (IS_IVYBRIDGE(dev
)) {
4530 u32 temp
= I915_READ(GEN7_MSG_CTL
);
4531 temp
&= ~(WAIT_FOR_PCH_FLR_ACK
| WAIT_FOR_PCH_RESET_ACK
);
4532 I915_WRITE(GEN7_MSG_CTL
, temp
);
4533 } else if (INTEL_INFO(dev
)->gen
>= 7) {
4534 u32 temp
= I915_READ(HSW_NDE_RSTWRN_OPT
);
4535 temp
&= ~RESET_PCH_HANDSHAKE_ENABLE
;
4536 I915_WRITE(HSW_NDE_RSTWRN_OPT
, temp
);
4540 i915_gem_init_swizzling(dev
);
4542 ret
= i915_gem_init_rings(dev
);
4546 for (i
= 0; i
< NUM_L3_SLICES(dev
); i
++)
4547 i915_gem_l3_remap(&dev_priv
->ring
[RCS
], i
);
4550 * XXX: Contexts should only be initialized once. Doing a switch to the
4551 * default context switch however is something we'd like to do after
4552 * reset or thaw (the latter may not actually be necessary for HW, but
4553 * goes with our code better). Context switching requires rings (for
4554 * the do_switch), but before enabling PPGTT. So don't move this.
4556 ret
= i915_gem_context_enable(dev_priv
);
4558 DRM_ERROR("Context enable failed %d\n", ret
);
4565 i915_gem_cleanup_ringbuffer(dev
);
4569 int i915_gem_init(struct drm_device
*dev
)
4571 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4574 mutex_lock(&dev
->struct_mutex
);
4576 if (IS_VALLEYVIEW(dev
)) {
4577 /* VLVA0 (potential hack), BIOS isn't actually waking us */
4578 I915_WRITE(VLV_GTLC_WAKE_CTRL
, 1);
4579 if (wait_for((I915_READ(VLV_GTLC_PW_STATUS
) & 1) == 1, 10))
4580 DRM_DEBUG_DRIVER("allow wake ack timed out\n");
4583 i915_gem_init_global_gtt(dev
);
4585 ret
= i915_gem_context_init(dev
);
4587 mutex_unlock(&dev
->struct_mutex
);
4591 ret
= i915_gem_init_hw(dev
);
4592 mutex_unlock(&dev
->struct_mutex
);
4594 WARN_ON(dev_priv
->mm
.aliasing_ppgtt
);
4595 i915_gem_context_fini(dev
);
4596 drm_mm_takedown(&dev_priv
->gtt
.base
.mm
);
4600 /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */
4601 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
4602 dev_priv
->dri1
.allow_batchbuffer
= 1;
4607 i915_gem_cleanup_ringbuffer(struct drm_device
*dev
)
4609 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4610 struct intel_ring_buffer
*ring
;
4613 for_each_ring(ring
, dev_priv
, i
)
4614 intel_cleanup_ring_buffer(ring
);
4618 i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
4619 struct drm_file
*file_priv
)
4621 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4624 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4627 if (i915_reset_in_progress(&dev_priv
->gpu_error
)) {
4628 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4629 atomic_set(&dev_priv
->gpu_error
.reset_counter
, 0);
4632 mutex_lock(&dev
->struct_mutex
);
4633 dev_priv
->ums
.mm_suspended
= 0;
4635 ret
= i915_gem_init_hw(dev
);
4637 mutex_unlock(&dev
->struct_mutex
);
4641 BUG_ON(!list_empty(&dev_priv
->gtt
.base
.active_list
));
4642 mutex_unlock(&dev
->struct_mutex
);
4644 ret
= drm_irq_install(dev
);
4646 goto cleanup_ringbuffer
;
4651 mutex_lock(&dev
->struct_mutex
);
4652 i915_gem_cleanup_ringbuffer(dev
);
4653 dev_priv
->ums
.mm_suspended
= 1;
4654 mutex_unlock(&dev
->struct_mutex
);
4660 i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
4661 struct drm_file
*file_priv
)
4663 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4666 drm_irq_uninstall(dev
);
4668 return i915_gem_suspend(dev
);
4672 i915_gem_lastclose(struct drm_device
*dev
)
4676 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4679 ret
= i915_gem_suspend(dev
);
4681 DRM_ERROR("failed to idle hardware: %d\n", ret
);
4685 init_ring_lists(struct intel_ring_buffer
*ring
)
4687 INIT_LIST_HEAD(&ring
->active_list
);
4688 INIT_LIST_HEAD(&ring
->request_list
);
4691 void i915_init_vm(struct drm_i915_private
*dev_priv
,
4692 struct i915_address_space
*vm
)
4694 if (!i915_is_ggtt(vm
))
4695 drm_mm_init(&vm
->mm
, vm
->start
, vm
->total
);
4696 vm
->dev
= dev_priv
->dev
;
4697 INIT_LIST_HEAD(&vm
->active_list
);
4698 INIT_LIST_HEAD(&vm
->inactive_list
);
4699 INIT_LIST_HEAD(&vm
->global_link
);
4700 list_add_tail(&vm
->global_link
, &dev_priv
->vm_list
);
4704 i915_gem_load(struct drm_device
*dev
)
4706 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4710 kmem_cache_create("i915_gem_object",
4711 sizeof(struct drm_i915_gem_object
), 0,
4715 INIT_LIST_HEAD(&dev_priv
->vm_list
);
4716 i915_init_vm(dev_priv
, &dev_priv
->gtt
.base
);
4718 INIT_LIST_HEAD(&dev_priv
->context_list
);
4719 INIT_LIST_HEAD(&dev_priv
->mm
.unbound_list
);
4720 INIT_LIST_HEAD(&dev_priv
->mm
.bound_list
);
4721 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
4722 for (i
= 0; i
< I915_NUM_RINGS
; i
++)
4723 init_ring_lists(&dev_priv
->ring
[i
]);
4724 for (i
= 0; i
< I915_MAX_NUM_FENCES
; i
++)
4725 INIT_LIST_HEAD(&dev_priv
->fence_regs
[i
].lru_list
);
4726 INIT_DELAYED_WORK(&dev_priv
->mm
.retire_work
,
4727 i915_gem_retire_work_handler
);
4728 INIT_DELAYED_WORK(&dev_priv
->mm
.idle_work
,
4729 i915_gem_idle_work_handler
);
4730 init_waitqueue_head(&dev_priv
->gpu_error
.reset_queue
);
4732 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4734 I915_WRITE(MI_ARB_STATE
,
4735 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE
));
4738 dev_priv
->relative_constants_mode
= I915_EXEC_CONSTANTS_REL_GENERAL
;
4740 /* Old X drivers will take 0-2 for front, back, depth buffers */
4741 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
4742 dev_priv
->fence_reg_start
= 3;
4744 if (INTEL_INFO(dev
)->gen
>= 7 && !IS_VALLEYVIEW(dev
))
4745 dev_priv
->num_fence_regs
= 32;
4746 else if (INTEL_INFO(dev
)->gen
>= 4 || IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
4747 dev_priv
->num_fence_regs
= 16;
4749 dev_priv
->num_fence_regs
= 8;
4751 /* Initialize fence registers to zero */
4752 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
4753 i915_gem_restore_fences(dev
);
4755 i915_gem_detect_bit_6_swizzle(dev
);
4756 init_waitqueue_head(&dev_priv
->pending_flip_queue
);
4758 dev_priv
->mm
.interruptible
= true;
4760 dev_priv
->mm
.inactive_shrinker
.scan_objects
= i915_gem_inactive_scan
;
4761 dev_priv
->mm
.inactive_shrinker
.count_objects
= i915_gem_inactive_count
;
4762 dev_priv
->mm
.inactive_shrinker
.seeks
= DEFAULT_SEEKS
;
4763 register_shrinker(&dev_priv
->mm
.inactive_shrinker
);
4766 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
)
4768 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
4770 cancel_delayed_work_sync(&file_priv
->mm
.idle_work
);
4772 /* Clean up our request list when the client is going away, so that
4773 * later retire_requests won't dereference our soon-to-be-gone
4776 spin_lock(&file_priv
->mm
.lock
);
4777 while (!list_empty(&file_priv
->mm
.request_list
)) {
4778 struct drm_i915_gem_request
*request
;
4780 request
= list_first_entry(&file_priv
->mm
.request_list
,
4781 struct drm_i915_gem_request
,
4783 list_del(&request
->client_list
);
4784 request
->file_priv
= NULL
;
4786 spin_unlock(&file_priv
->mm
.lock
);
4790 i915_gem_file_idle_work_handler(struct work_struct
*work
)
4792 struct drm_i915_file_private
*file_priv
=
4793 container_of(work
, typeof(*file_priv
), mm
.idle_work
.work
);
4795 atomic_set(&file_priv
->rps_wait_boost
, false);
4798 int i915_gem_open(struct drm_device
*dev
, struct drm_file
*file
)
4800 struct drm_i915_file_private
*file_priv
;
4803 DRM_DEBUG_DRIVER("\n");
4805 file_priv
= kzalloc(sizeof(*file_priv
), GFP_KERNEL
);
4809 file
->driver_priv
= file_priv
;
4810 file_priv
->dev_priv
= dev
->dev_private
;
4811 file_priv
->file
= file
;
4813 spin_lock_init(&file_priv
->mm
.lock
);
4814 INIT_LIST_HEAD(&file_priv
->mm
.request_list
);
4815 INIT_DELAYED_WORK(&file_priv
->mm
.idle_work
,
4816 i915_gem_file_idle_work_handler
);
4818 ret
= i915_gem_context_open(dev
, file
);
4825 static bool mutex_is_locked_by(struct mutex
*mutex
, struct task_struct
*task
)
4827 if (!mutex_is_locked(mutex
))
4830 #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES)
4831 return mutex
->owner
== task
;
4833 /* Since UP may be pre-empted, we cannot assume that we own the lock */
4838 static unsigned long
4839 i915_gem_inactive_count(struct shrinker
*shrinker
, struct shrink_control
*sc
)
4841 struct drm_i915_private
*dev_priv
=
4842 container_of(shrinker
,
4843 struct drm_i915_private
,
4844 mm
.inactive_shrinker
);
4845 struct drm_device
*dev
= dev_priv
->dev
;
4846 struct drm_i915_gem_object
*obj
;
4848 unsigned long count
;
4850 if (!mutex_trylock(&dev
->struct_mutex
)) {
4851 if (!mutex_is_locked_by(&dev
->struct_mutex
, current
))
4854 if (dev_priv
->mm
.shrinker_no_lock_stealing
)
4861 list_for_each_entry(obj
, &dev_priv
->mm
.unbound_list
, global_list
)
4862 if (obj
->pages_pin_count
== 0)
4863 count
+= obj
->base
.size
>> PAGE_SHIFT
;
4865 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
4869 if (!i915_gem_obj_is_pinned(obj
) && obj
->pages_pin_count
== 0)
4870 count
+= obj
->base
.size
>> PAGE_SHIFT
;
4874 mutex_unlock(&dev
->struct_mutex
);
4879 /* All the new VM stuff */
4880 unsigned long i915_gem_obj_offset(struct drm_i915_gem_object
*o
,
4881 struct i915_address_space
*vm
)
4883 struct drm_i915_private
*dev_priv
= o
->base
.dev
->dev_private
;
4884 struct i915_vma
*vma
;
4886 if (!dev_priv
->mm
.aliasing_ppgtt
||
4887 vm
== &dev_priv
->mm
.aliasing_ppgtt
->base
)
4888 vm
= &dev_priv
->gtt
.base
;
4890 BUG_ON(list_empty(&o
->vma_list
));
4891 list_for_each_entry(vma
, &o
->vma_list
, vma_link
) {
4893 return vma
->node
.start
;
4899 bool i915_gem_obj_bound(struct drm_i915_gem_object
*o
,
4900 struct i915_address_space
*vm
)
4902 struct i915_vma
*vma
;
4904 list_for_each_entry(vma
, &o
->vma_list
, vma_link
)
4905 if (vma
->vm
== vm
&& drm_mm_node_allocated(&vma
->node
))
4911 bool i915_gem_obj_bound_any(struct drm_i915_gem_object
*o
)
4913 struct i915_vma
*vma
;
4915 list_for_each_entry(vma
, &o
->vma_list
, vma_link
)
4916 if (drm_mm_node_allocated(&vma
->node
))
4922 unsigned long i915_gem_obj_size(struct drm_i915_gem_object
*o
,
4923 struct i915_address_space
*vm
)
4925 struct drm_i915_private
*dev_priv
= o
->base
.dev
->dev_private
;
4926 struct i915_vma
*vma
;
4928 if (!dev_priv
->mm
.aliasing_ppgtt
||
4929 vm
== &dev_priv
->mm
.aliasing_ppgtt
->base
)
4930 vm
= &dev_priv
->gtt
.base
;
4932 BUG_ON(list_empty(&o
->vma_list
));
4934 list_for_each_entry(vma
, &o
->vma_list
, vma_link
)
4936 return vma
->node
.size
;
4941 static unsigned long
4942 i915_gem_inactive_scan(struct shrinker
*shrinker
, struct shrink_control
*sc
)
4944 struct drm_i915_private
*dev_priv
=
4945 container_of(shrinker
,
4946 struct drm_i915_private
,
4947 mm
.inactive_shrinker
);
4948 struct drm_device
*dev
= dev_priv
->dev
;
4949 unsigned long freed
;
4952 if (!mutex_trylock(&dev
->struct_mutex
)) {
4953 if (!mutex_is_locked_by(&dev
->struct_mutex
, current
))
4956 if (dev_priv
->mm
.shrinker_no_lock_stealing
)
4962 freed
= i915_gem_purge(dev_priv
, sc
->nr_to_scan
);
4963 if (freed
< sc
->nr_to_scan
)
4964 freed
+= __i915_gem_shrink(dev_priv
,
4965 sc
->nr_to_scan
- freed
,
4967 if (freed
< sc
->nr_to_scan
)
4968 freed
+= i915_gem_shrink_all(dev_priv
);
4971 mutex_unlock(&dev
->struct_mutex
);
4976 struct i915_vma
*i915_gem_obj_to_ggtt(struct drm_i915_gem_object
*obj
)
4978 struct i915_vma
*vma
;
4980 if (WARN_ON(list_empty(&obj
->vma_list
)))
4983 vma
= list_first_entry(&obj
->vma_list
, typeof(*vma
), vma_link
);
4984 if (vma
->vm
!= obj_to_ggtt(obj
))