2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/slab.h>
35 #include <linux/swap.h>
36 #include <linux/pci.h>
37 #include <linux/intel-gtt.h>
39 static uint32_t i915_gem_get_gtt_alignment(struct drm_gem_object
*obj
);
41 static int i915_gem_object_flush_gpu_write_domain(struct drm_gem_object
*obj
,
43 static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object
*obj
);
44 static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object
*obj
);
45 static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object
*obj
,
47 static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object
*obj
,
50 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object
*obj
);
51 static int i915_gem_object_wait_rendering(struct drm_gem_object
*obj
,
53 static int i915_gem_object_bind_to_gtt(struct drm_gem_object
*obj
,
55 static void i915_gem_clear_fence_reg(struct drm_gem_object
*obj
);
56 static int i915_gem_phys_pwrite(struct drm_device
*dev
, struct drm_gem_object
*obj
,
57 struct drm_i915_gem_pwrite
*args
,
58 struct drm_file
*file_priv
);
59 static void i915_gem_free_object_tail(struct drm_gem_object
*obj
);
61 static LIST_HEAD(shrink_list
);
62 static DEFINE_SPINLOCK(shrink_list_lock
);
65 i915_gem_object_is_inactive(struct drm_i915_gem_object
*obj_priv
)
67 return obj_priv
->gtt_space
&&
69 obj_priv
->pin_count
== 0;
72 int i915_gem_do_init(struct drm_device
*dev
, unsigned long start
,
75 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
78 (start
& (PAGE_SIZE
- 1)) != 0 ||
79 (end
& (PAGE_SIZE
- 1)) != 0) {
83 drm_mm_init(&dev_priv
->mm
.gtt_space
, start
,
86 dev
->gtt_total
= (uint32_t) (end
- start
);
92 i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
93 struct drm_file
*file_priv
)
95 struct drm_i915_gem_init
*args
= data
;
98 mutex_lock(&dev
->struct_mutex
);
99 ret
= i915_gem_do_init(dev
, args
->gtt_start
, args
->gtt_end
);
100 mutex_unlock(&dev
->struct_mutex
);
106 i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
107 struct drm_file
*file_priv
)
109 struct drm_i915_gem_get_aperture
*args
= data
;
111 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
114 args
->aper_size
= dev
->gtt_total
;
115 args
->aper_available_size
= (args
->aper_size
-
116 atomic_read(&dev
->pin_memory
));
123 * Creates a new mm object and returns a handle to it.
126 i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
127 struct drm_file
*file_priv
)
129 struct drm_i915_gem_create
*args
= data
;
130 struct drm_gem_object
*obj
;
134 args
->size
= roundup(args
->size
, PAGE_SIZE
);
136 /* Allocate the new object */
137 obj
= i915_gem_alloc_object(dev
, args
->size
);
141 ret
= drm_gem_handle_create(file_priv
, obj
, &handle
);
143 drm_gem_object_unreference_unlocked(obj
);
147 /* Sink the floating reference from kref_init(handlecount) */
148 drm_gem_object_handle_unreference_unlocked(obj
);
150 args
->handle
= handle
;
155 fast_shmem_read(struct page
**pages
,
156 loff_t page_base
, int page_offset
,
163 vaddr
= kmap_atomic(pages
[page_base
>> PAGE_SHIFT
], KM_USER0
);
166 unwritten
= __copy_to_user_inatomic(data
, vaddr
+ page_offset
, length
);
167 kunmap_atomic(vaddr
, KM_USER0
);
175 static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object
*obj
)
177 drm_i915_private_t
*dev_priv
= obj
->dev
->dev_private
;
178 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
180 return dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_9_10_17
&&
181 obj_priv
->tiling_mode
!= I915_TILING_NONE
;
185 slow_shmem_copy(struct page
*dst_page
,
187 struct page
*src_page
,
191 char *dst_vaddr
, *src_vaddr
;
193 dst_vaddr
= kmap(dst_page
);
194 src_vaddr
= kmap(src_page
);
196 memcpy(dst_vaddr
+ dst_offset
, src_vaddr
+ src_offset
, length
);
203 slow_shmem_bit17_copy(struct page
*gpu_page
,
205 struct page
*cpu_page
,
210 char *gpu_vaddr
, *cpu_vaddr
;
212 /* Use the unswizzled path if this page isn't affected. */
213 if ((page_to_phys(gpu_page
) & (1 << 17)) == 0) {
215 return slow_shmem_copy(cpu_page
, cpu_offset
,
216 gpu_page
, gpu_offset
, length
);
218 return slow_shmem_copy(gpu_page
, gpu_offset
,
219 cpu_page
, cpu_offset
, length
);
222 gpu_vaddr
= kmap(gpu_page
);
223 cpu_vaddr
= kmap(cpu_page
);
225 /* Copy the data, XORing A6 with A17 (1). The user already knows he's
226 * XORing with the other bits (A9 for Y, A9 and A10 for X)
229 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
230 int this_length
= min(cacheline_end
- gpu_offset
, length
);
231 int swizzled_gpu_offset
= gpu_offset
^ 64;
234 memcpy(cpu_vaddr
+ cpu_offset
,
235 gpu_vaddr
+ swizzled_gpu_offset
,
238 memcpy(gpu_vaddr
+ swizzled_gpu_offset
,
239 cpu_vaddr
+ cpu_offset
,
242 cpu_offset
+= this_length
;
243 gpu_offset
+= this_length
;
244 length
-= this_length
;
252 * This is the fast shmem pread path, which attempts to copy_from_user directly
253 * from the backing pages of the object to the user's address space. On a
254 * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
257 i915_gem_shmem_pread_fast(struct drm_device
*dev
, struct drm_gem_object
*obj
,
258 struct drm_i915_gem_pread
*args
,
259 struct drm_file
*file_priv
)
261 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
263 loff_t offset
, page_base
;
264 char __user
*user_data
;
265 int page_offset
, page_length
;
268 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
271 mutex_lock(&dev
->struct_mutex
);
273 ret
= i915_gem_object_get_pages(obj
, 0);
277 ret
= i915_gem_object_set_cpu_read_domain_range(obj
, args
->offset
,
282 obj_priv
= to_intel_bo(obj
);
283 offset
= args
->offset
;
286 /* Operation in this page
288 * page_base = page offset within aperture
289 * page_offset = offset within page
290 * page_length = bytes to copy for this page
292 page_base
= (offset
& ~(PAGE_SIZE
-1));
293 page_offset
= offset
& (PAGE_SIZE
-1);
294 page_length
= remain
;
295 if ((page_offset
+ remain
) > PAGE_SIZE
)
296 page_length
= PAGE_SIZE
- page_offset
;
298 ret
= fast_shmem_read(obj_priv
->pages
,
299 page_base
, page_offset
,
300 user_data
, page_length
);
304 remain
-= page_length
;
305 user_data
+= page_length
;
306 offset
+= page_length
;
310 i915_gem_object_put_pages(obj
);
312 mutex_unlock(&dev
->struct_mutex
);
318 i915_gem_object_get_pages_or_evict(struct drm_gem_object
*obj
)
322 ret
= i915_gem_object_get_pages(obj
, __GFP_NORETRY
| __GFP_NOWARN
);
324 /* If we've insufficient memory to map in the pages, attempt
325 * to make some space by throwing out some old buffers.
327 if (ret
== -ENOMEM
) {
328 struct drm_device
*dev
= obj
->dev
;
330 ret
= i915_gem_evict_something(dev
, obj
->size
,
331 i915_gem_get_gtt_alignment(obj
));
335 ret
= i915_gem_object_get_pages(obj
, 0);
342 * This is the fallback shmem pread path, which allocates temporary storage
343 * in kernel space to copy_to_user into outside of the struct_mutex, so we
344 * can copy out of the object's backing pages while holding the struct mutex
345 * and not take page faults.
348 i915_gem_shmem_pread_slow(struct drm_device
*dev
, struct drm_gem_object
*obj
,
349 struct drm_i915_gem_pread
*args
,
350 struct drm_file
*file_priv
)
352 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
353 struct mm_struct
*mm
= current
->mm
;
354 struct page
**user_pages
;
356 loff_t offset
, pinned_pages
, i
;
357 loff_t first_data_page
, last_data_page
, num_pages
;
358 int shmem_page_index
, shmem_page_offset
;
359 int data_page_index
, data_page_offset
;
362 uint64_t data_ptr
= args
->data_ptr
;
363 int do_bit17_swizzling
;
367 /* Pin the user pages containing the data. We can't fault while
368 * holding the struct mutex, yet we want to hold it while
369 * dereferencing the user data.
371 first_data_page
= data_ptr
/ PAGE_SIZE
;
372 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
373 num_pages
= last_data_page
- first_data_page
+ 1;
375 user_pages
= drm_calloc_large(num_pages
, sizeof(struct page
*));
376 if (user_pages
== NULL
)
379 down_read(&mm
->mmap_sem
);
380 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
381 num_pages
, 1, 0, user_pages
, NULL
);
382 up_read(&mm
->mmap_sem
);
383 if (pinned_pages
< num_pages
) {
385 goto fail_put_user_pages
;
388 do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
390 mutex_lock(&dev
->struct_mutex
);
392 ret
= i915_gem_object_get_pages_or_evict(obj
);
396 ret
= i915_gem_object_set_cpu_read_domain_range(obj
, args
->offset
,
401 obj_priv
= to_intel_bo(obj
);
402 offset
= args
->offset
;
405 /* Operation in this page
407 * shmem_page_index = page number within shmem file
408 * shmem_page_offset = offset within page in shmem file
409 * data_page_index = page number in get_user_pages return
410 * data_page_offset = offset with data_page_index page.
411 * page_length = bytes to copy for this page
413 shmem_page_index
= offset
/ PAGE_SIZE
;
414 shmem_page_offset
= offset
& ~PAGE_MASK
;
415 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
416 data_page_offset
= data_ptr
& ~PAGE_MASK
;
418 page_length
= remain
;
419 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
420 page_length
= PAGE_SIZE
- shmem_page_offset
;
421 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
422 page_length
= PAGE_SIZE
- data_page_offset
;
424 if (do_bit17_swizzling
) {
425 slow_shmem_bit17_copy(obj_priv
->pages
[shmem_page_index
],
427 user_pages
[data_page_index
],
432 slow_shmem_copy(user_pages
[data_page_index
],
434 obj_priv
->pages
[shmem_page_index
],
439 remain
-= page_length
;
440 data_ptr
+= page_length
;
441 offset
+= page_length
;
445 i915_gem_object_put_pages(obj
);
447 mutex_unlock(&dev
->struct_mutex
);
449 for (i
= 0; i
< pinned_pages
; i
++) {
450 SetPageDirty(user_pages
[i
]);
451 page_cache_release(user_pages
[i
]);
453 drm_free_large(user_pages
);
459 * Reads data from the object referenced by handle.
461 * On error, the contents of *data are undefined.
464 i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
465 struct drm_file
*file_priv
)
467 struct drm_i915_gem_pread
*args
= data
;
468 struct drm_gem_object
*obj
;
469 struct drm_i915_gem_object
*obj_priv
;
472 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
475 obj_priv
= to_intel_bo(obj
);
477 /* Bounds check source.
479 * XXX: This could use review for overflow issues...
481 if (args
->offset
> obj
->size
|| args
->size
> obj
->size
||
482 args
->offset
+ args
->size
> obj
->size
) {
483 drm_gem_object_unreference_unlocked(obj
);
487 if (i915_gem_object_needs_bit17_swizzle(obj
)) {
488 ret
= i915_gem_shmem_pread_slow(dev
, obj
, args
, file_priv
);
490 ret
= i915_gem_shmem_pread_fast(dev
, obj
, args
, file_priv
);
492 ret
= i915_gem_shmem_pread_slow(dev
, obj
, args
,
496 drm_gem_object_unreference_unlocked(obj
);
501 /* This is the fast write path which cannot handle
502 * page faults in the source data
506 fast_user_write(struct io_mapping
*mapping
,
507 loff_t page_base
, int page_offset
,
508 char __user
*user_data
,
512 unsigned long unwritten
;
514 vaddr_atomic
= io_mapping_map_atomic_wc(mapping
, page_base
, KM_USER0
);
515 unwritten
= __copy_from_user_inatomic_nocache(vaddr_atomic
+ page_offset
,
517 io_mapping_unmap_atomic(vaddr_atomic
, KM_USER0
);
523 /* Here's the write path which can sleep for
528 slow_kernel_write(struct io_mapping
*mapping
,
529 loff_t gtt_base
, int gtt_offset
,
530 struct page
*user_page
, int user_offset
,
533 char __iomem
*dst_vaddr
;
536 dst_vaddr
= io_mapping_map_wc(mapping
, gtt_base
);
537 src_vaddr
= kmap(user_page
);
539 memcpy_toio(dst_vaddr
+ gtt_offset
,
540 src_vaddr
+ user_offset
,
544 io_mapping_unmap(dst_vaddr
);
548 fast_shmem_write(struct page
**pages
,
549 loff_t page_base
, int page_offset
,
554 unsigned long unwritten
;
556 vaddr
= kmap_atomic(pages
[page_base
>> PAGE_SHIFT
], KM_USER0
);
559 unwritten
= __copy_from_user_inatomic(vaddr
+ page_offset
, data
, length
);
560 kunmap_atomic(vaddr
, KM_USER0
);
568 * This is the fast pwrite path, where we copy the data directly from the
569 * user into the GTT, uncached.
572 i915_gem_gtt_pwrite_fast(struct drm_device
*dev
, struct drm_gem_object
*obj
,
573 struct drm_i915_gem_pwrite
*args
,
574 struct drm_file
*file_priv
)
576 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
577 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
579 loff_t offset
, page_base
;
580 char __user
*user_data
;
581 int page_offset
, page_length
;
584 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
586 if (!access_ok(VERIFY_READ
, user_data
, remain
))
590 mutex_lock(&dev
->struct_mutex
);
591 ret
= i915_gem_object_pin(obj
, 0);
593 mutex_unlock(&dev
->struct_mutex
);
596 ret
= i915_gem_object_set_to_gtt_domain(obj
, 1);
600 obj_priv
= to_intel_bo(obj
);
601 offset
= obj_priv
->gtt_offset
+ args
->offset
;
604 /* Operation in this page
606 * page_base = page offset within aperture
607 * page_offset = offset within page
608 * page_length = bytes to copy for this page
610 page_base
= (offset
& ~(PAGE_SIZE
-1));
611 page_offset
= offset
& (PAGE_SIZE
-1);
612 page_length
= remain
;
613 if ((page_offset
+ remain
) > PAGE_SIZE
)
614 page_length
= PAGE_SIZE
- page_offset
;
616 ret
= fast_user_write (dev_priv
->mm
.gtt_mapping
, page_base
,
617 page_offset
, user_data
, page_length
);
619 /* If we get a fault while copying data, then (presumably) our
620 * source page isn't available. Return the error and we'll
621 * retry in the slow path.
626 remain
-= page_length
;
627 user_data
+= page_length
;
628 offset
+= page_length
;
632 i915_gem_object_unpin(obj
);
633 mutex_unlock(&dev
->struct_mutex
);
639 * This is the fallback GTT pwrite path, which uses get_user_pages to pin
640 * the memory and maps it using kmap_atomic for copying.
642 * This code resulted in x11perf -rgb10text consuming about 10% more CPU
643 * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
646 i915_gem_gtt_pwrite_slow(struct drm_device
*dev
, struct drm_gem_object
*obj
,
647 struct drm_i915_gem_pwrite
*args
,
648 struct drm_file
*file_priv
)
650 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
651 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
653 loff_t gtt_page_base
, offset
;
654 loff_t first_data_page
, last_data_page
, num_pages
;
655 loff_t pinned_pages
, i
;
656 struct page
**user_pages
;
657 struct mm_struct
*mm
= current
->mm
;
658 int gtt_page_offset
, data_page_offset
, data_page_index
, page_length
;
660 uint64_t data_ptr
= args
->data_ptr
;
664 /* Pin the user pages containing the data. We can't fault while
665 * holding the struct mutex, and all of the pwrite implementations
666 * want to hold it while dereferencing the user data.
668 first_data_page
= data_ptr
/ PAGE_SIZE
;
669 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
670 num_pages
= last_data_page
- first_data_page
+ 1;
672 user_pages
= drm_calloc_large(num_pages
, sizeof(struct page
*));
673 if (user_pages
== NULL
)
676 down_read(&mm
->mmap_sem
);
677 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
678 num_pages
, 0, 0, user_pages
, NULL
);
679 up_read(&mm
->mmap_sem
);
680 if (pinned_pages
< num_pages
) {
682 goto out_unpin_pages
;
685 mutex_lock(&dev
->struct_mutex
);
686 ret
= i915_gem_object_pin(obj
, 0);
690 ret
= i915_gem_object_set_to_gtt_domain(obj
, 1);
692 goto out_unpin_object
;
694 obj_priv
= to_intel_bo(obj
);
695 offset
= obj_priv
->gtt_offset
+ args
->offset
;
698 /* Operation in this page
700 * gtt_page_base = page offset within aperture
701 * gtt_page_offset = offset within page in aperture
702 * data_page_index = page number in get_user_pages return
703 * data_page_offset = offset with data_page_index page.
704 * page_length = bytes to copy for this page
706 gtt_page_base
= offset
& PAGE_MASK
;
707 gtt_page_offset
= offset
& ~PAGE_MASK
;
708 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
709 data_page_offset
= data_ptr
& ~PAGE_MASK
;
711 page_length
= remain
;
712 if ((gtt_page_offset
+ page_length
) > PAGE_SIZE
)
713 page_length
= PAGE_SIZE
- gtt_page_offset
;
714 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
715 page_length
= PAGE_SIZE
- data_page_offset
;
717 slow_kernel_write(dev_priv
->mm
.gtt_mapping
,
718 gtt_page_base
, gtt_page_offset
,
719 user_pages
[data_page_index
],
723 remain
-= page_length
;
724 offset
+= page_length
;
725 data_ptr
+= page_length
;
729 i915_gem_object_unpin(obj
);
731 mutex_unlock(&dev
->struct_mutex
);
733 for (i
= 0; i
< pinned_pages
; i
++)
734 page_cache_release(user_pages
[i
]);
735 drm_free_large(user_pages
);
741 * This is the fast shmem pwrite path, which attempts to directly
742 * copy_from_user into the kmapped pages backing the object.
745 i915_gem_shmem_pwrite_fast(struct drm_device
*dev
, struct drm_gem_object
*obj
,
746 struct drm_i915_gem_pwrite
*args
,
747 struct drm_file
*file_priv
)
749 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
751 loff_t offset
, page_base
;
752 char __user
*user_data
;
753 int page_offset
, page_length
;
756 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
759 mutex_lock(&dev
->struct_mutex
);
761 ret
= i915_gem_object_get_pages(obj
, 0);
765 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
769 obj_priv
= to_intel_bo(obj
);
770 offset
= args
->offset
;
774 /* Operation in this page
776 * page_base = page offset within aperture
777 * page_offset = offset within page
778 * page_length = bytes to copy for this page
780 page_base
= (offset
& ~(PAGE_SIZE
-1));
781 page_offset
= offset
& (PAGE_SIZE
-1);
782 page_length
= remain
;
783 if ((page_offset
+ remain
) > PAGE_SIZE
)
784 page_length
= PAGE_SIZE
- page_offset
;
786 ret
= fast_shmem_write(obj_priv
->pages
,
787 page_base
, page_offset
,
788 user_data
, page_length
);
792 remain
-= page_length
;
793 user_data
+= page_length
;
794 offset
+= page_length
;
798 i915_gem_object_put_pages(obj
);
800 mutex_unlock(&dev
->struct_mutex
);
806 * This is the fallback shmem pwrite path, which uses get_user_pages to pin
807 * the memory and maps it using kmap_atomic for copying.
809 * This avoids taking mmap_sem for faulting on the user's address while the
810 * struct_mutex is held.
813 i915_gem_shmem_pwrite_slow(struct drm_device
*dev
, struct drm_gem_object
*obj
,
814 struct drm_i915_gem_pwrite
*args
,
815 struct drm_file
*file_priv
)
817 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
818 struct mm_struct
*mm
= current
->mm
;
819 struct page
**user_pages
;
821 loff_t offset
, pinned_pages
, i
;
822 loff_t first_data_page
, last_data_page
, num_pages
;
823 int shmem_page_index
, shmem_page_offset
;
824 int data_page_index
, data_page_offset
;
827 uint64_t data_ptr
= args
->data_ptr
;
828 int do_bit17_swizzling
;
832 /* Pin the user pages containing the data. We can't fault while
833 * holding the struct mutex, and all of the pwrite implementations
834 * want to hold it while dereferencing the user data.
836 first_data_page
= data_ptr
/ PAGE_SIZE
;
837 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
838 num_pages
= last_data_page
- first_data_page
+ 1;
840 user_pages
= drm_calloc_large(num_pages
, sizeof(struct page
*));
841 if (user_pages
== NULL
)
844 down_read(&mm
->mmap_sem
);
845 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
846 num_pages
, 0, 0, user_pages
, NULL
);
847 up_read(&mm
->mmap_sem
);
848 if (pinned_pages
< num_pages
) {
850 goto fail_put_user_pages
;
853 do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
855 mutex_lock(&dev
->struct_mutex
);
857 ret
= i915_gem_object_get_pages_or_evict(obj
);
861 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
865 obj_priv
= to_intel_bo(obj
);
866 offset
= args
->offset
;
870 /* Operation in this page
872 * shmem_page_index = page number within shmem file
873 * shmem_page_offset = offset within page in shmem file
874 * data_page_index = page number in get_user_pages return
875 * data_page_offset = offset with data_page_index page.
876 * page_length = bytes to copy for this page
878 shmem_page_index
= offset
/ PAGE_SIZE
;
879 shmem_page_offset
= offset
& ~PAGE_MASK
;
880 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
881 data_page_offset
= data_ptr
& ~PAGE_MASK
;
883 page_length
= remain
;
884 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
885 page_length
= PAGE_SIZE
- shmem_page_offset
;
886 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
887 page_length
= PAGE_SIZE
- data_page_offset
;
889 if (do_bit17_swizzling
) {
890 slow_shmem_bit17_copy(obj_priv
->pages
[shmem_page_index
],
892 user_pages
[data_page_index
],
897 slow_shmem_copy(obj_priv
->pages
[shmem_page_index
],
899 user_pages
[data_page_index
],
904 remain
-= page_length
;
905 data_ptr
+= page_length
;
906 offset
+= page_length
;
910 i915_gem_object_put_pages(obj
);
912 mutex_unlock(&dev
->struct_mutex
);
914 for (i
= 0; i
< pinned_pages
; i
++)
915 page_cache_release(user_pages
[i
]);
916 drm_free_large(user_pages
);
922 * Writes data to the object referenced by handle.
924 * On error, the contents of the buffer that were to be modified are undefined.
927 i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
928 struct drm_file
*file_priv
)
930 struct drm_i915_gem_pwrite
*args
= data
;
931 struct drm_gem_object
*obj
;
932 struct drm_i915_gem_object
*obj_priv
;
935 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
938 obj_priv
= to_intel_bo(obj
);
940 /* Bounds check destination.
942 * XXX: This could use review for overflow issues...
944 if (args
->offset
> obj
->size
|| args
->size
> obj
->size
||
945 args
->offset
+ args
->size
> obj
->size
) {
946 drm_gem_object_unreference_unlocked(obj
);
950 /* We can only do the GTT pwrite on untiled buffers, as otherwise
951 * it would end up going through the fenced access, and we'll get
952 * different detiling behavior between reading and writing.
953 * pread/pwrite currently are reading and writing from the CPU
954 * perspective, requiring manual detiling by the client.
956 if (obj_priv
->phys_obj
)
957 ret
= i915_gem_phys_pwrite(dev
, obj
, args
, file_priv
);
958 else if (obj_priv
->tiling_mode
== I915_TILING_NONE
&&
959 dev
->gtt_total
!= 0 &&
960 obj
->write_domain
!= I915_GEM_DOMAIN_CPU
) {
961 ret
= i915_gem_gtt_pwrite_fast(dev
, obj
, args
, file_priv
);
962 if (ret
== -EFAULT
) {
963 ret
= i915_gem_gtt_pwrite_slow(dev
, obj
, args
,
966 } else if (i915_gem_object_needs_bit17_swizzle(obj
)) {
967 ret
= i915_gem_shmem_pwrite_slow(dev
, obj
, args
, file_priv
);
969 ret
= i915_gem_shmem_pwrite_fast(dev
, obj
, args
, file_priv
);
970 if (ret
== -EFAULT
) {
971 ret
= i915_gem_shmem_pwrite_slow(dev
, obj
, args
,
978 DRM_INFO("pwrite failed %d\n", ret
);
981 drm_gem_object_unreference_unlocked(obj
);
987 * Called when user space prepares to use an object with the CPU, either
988 * through the mmap ioctl's mapping or a GTT mapping.
991 i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
992 struct drm_file
*file_priv
)
994 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
995 struct drm_i915_gem_set_domain
*args
= data
;
996 struct drm_gem_object
*obj
;
997 struct drm_i915_gem_object
*obj_priv
;
998 uint32_t read_domains
= args
->read_domains
;
999 uint32_t write_domain
= args
->write_domain
;
1002 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1005 /* Only handle setting domains to types used by the CPU. */
1006 if (write_domain
& I915_GEM_GPU_DOMAINS
)
1009 if (read_domains
& I915_GEM_GPU_DOMAINS
)
1012 /* Having something in the write domain implies it's in the read
1013 * domain, and only that read domain. Enforce that in the request.
1015 if (write_domain
!= 0 && read_domains
!= write_domain
)
1018 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1021 obj_priv
= to_intel_bo(obj
);
1023 mutex_lock(&dev
->struct_mutex
);
1025 intel_mark_busy(dev
, obj
);
1028 DRM_INFO("set_domain_ioctl %p(%zd), %08x %08x\n",
1029 obj
, obj
->size
, read_domains
, write_domain
);
1031 if (read_domains
& I915_GEM_DOMAIN_GTT
) {
1032 ret
= i915_gem_object_set_to_gtt_domain(obj
, write_domain
!= 0);
1034 /* Update the LRU on the fence for the CPU access that's
1037 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
) {
1038 struct drm_i915_fence_reg
*reg
=
1039 &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
1040 list_move_tail(®
->lru_list
,
1041 &dev_priv
->mm
.fence_list
);
1044 /* Silently promote "you're not bound, there was nothing to do"
1045 * to success, since the client was just asking us to
1046 * make sure everything was done.
1051 ret
= i915_gem_object_set_to_cpu_domain(obj
, write_domain
!= 0);
1055 /* Maintain LRU order of "inactive" objects */
1056 if (ret
== 0 && i915_gem_object_is_inactive(obj_priv
))
1057 list_move_tail(&obj_priv
->list
, &dev_priv
->mm
.inactive_list
);
1059 drm_gem_object_unreference(obj
);
1060 mutex_unlock(&dev
->struct_mutex
);
1065 * Called when user space has done writes to this buffer
1068 i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1069 struct drm_file
*file_priv
)
1071 struct drm_i915_gem_sw_finish
*args
= data
;
1072 struct drm_gem_object
*obj
;
1073 struct drm_i915_gem_object
*obj_priv
;
1076 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1079 mutex_lock(&dev
->struct_mutex
);
1080 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1082 mutex_unlock(&dev
->struct_mutex
);
1087 DRM_INFO("%s: sw_finish %d (%p %zd)\n",
1088 __func__
, args
->handle
, obj
, obj
->size
);
1090 obj_priv
= to_intel_bo(obj
);
1092 /* Pinned buffers may be scanout, so flush the cache */
1093 if (obj_priv
->pin_count
)
1094 i915_gem_object_flush_cpu_write_domain(obj
);
1096 drm_gem_object_unreference(obj
);
1097 mutex_unlock(&dev
->struct_mutex
);
1102 * Maps the contents of an object, returning the address it is mapped
1105 * While the mapping holds a reference on the contents of the object, it doesn't
1106 * imply a ref on the object itself.
1109 i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1110 struct drm_file
*file_priv
)
1112 struct drm_i915_gem_mmap
*args
= data
;
1113 struct drm_gem_object
*obj
;
1117 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1120 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1124 offset
= args
->offset
;
1126 down_write(¤t
->mm
->mmap_sem
);
1127 addr
= do_mmap(obj
->filp
, 0, args
->size
,
1128 PROT_READ
| PROT_WRITE
, MAP_SHARED
,
1130 up_write(¤t
->mm
->mmap_sem
);
1131 drm_gem_object_unreference_unlocked(obj
);
1132 if (IS_ERR((void *)addr
))
1135 args
->addr_ptr
= (uint64_t) addr
;
1141 * i915_gem_fault - fault a page into the GTT
1142 * vma: VMA in question
1145 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1146 * from userspace. The fault handler takes care of binding the object to
1147 * the GTT (if needed), allocating and programming a fence register (again,
1148 * only if needed based on whether the old reg is still valid or the object
1149 * is tiled) and inserting a new PTE into the faulting process.
1151 * Note that the faulting process may involve evicting existing objects
1152 * from the GTT and/or fence registers to make room. So performance may
1153 * suffer if the GTT working set is large or there are few fence registers
1156 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
)
1158 struct drm_gem_object
*obj
= vma
->vm_private_data
;
1159 struct drm_device
*dev
= obj
->dev
;
1160 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1161 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1162 pgoff_t page_offset
;
1165 bool write
= !!(vmf
->flags
& FAULT_FLAG_WRITE
);
1167 /* We don't use vmf->pgoff since that has the fake offset */
1168 page_offset
= ((unsigned long)vmf
->virtual_address
- vma
->vm_start
) >>
1171 /* Now bind it into the GTT if needed */
1172 mutex_lock(&dev
->struct_mutex
);
1173 if (!obj_priv
->gtt_space
) {
1174 ret
= i915_gem_object_bind_to_gtt(obj
, 0);
1178 ret
= i915_gem_object_set_to_gtt_domain(obj
, write
);
1183 /* Need a new fence register? */
1184 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
) {
1185 ret
= i915_gem_object_get_fence_reg(obj
, true);
1190 if (i915_gem_object_is_inactive(obj_priv
))
1191 list_move_tail(&obj_priv
->list
, &dev_priv
->mm
.inactive_list
);
1193 pfn
= ((dev
->agp
->base
+ obj_priv
->gtt_offset
) >> PAGE_SHIFT
) +
1196 /* Finally, remap it using the new GTT offset */
1197 ret
= vm_insert_pfn(vma
, (unsigned long)vmf
->virtual_address
, pfn
);
1199 mutex_unlock(&dev
->struct_mutex
);
1204 return VM_FAULT_NOPAGE
;
1207 return VM_FAULT_OOM
;
1209 return VM_FAULT_SIGBUS
;
1214 * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1215 * @obj: obj in question
1217 * GEM memory mapping works by handing back to userspace a fake mmap offset
1218 * it can use in a subsequent mmap(2) call. The DRM core code then looks
1219 * up the object based on the offset and sets up the various memory mapping
1222 * This routine allocates and attaches a fake offset for @obj.
1225 i915_gem_create_mmap_offset(struct drm_gem_object
*obj
)
1227 struct drm_device
*dev
= obj
->dev
;
1228 struct drm_gem_mm
*mm
= dev
->mm_private
;
1229 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1230 struct drm_map_list
*list
;
1231 struct drm_local_map
*map
;
1234 /* Set the object up for mmap'ing */
1235 list
= &obj
->map_list
;
1236 list
->map
= kzalloc(sizeof(struct drm_map_list
), GFP_KERNEL
);
1241 map
->type
= _DRM_GEM
;
1242 map
->size
= obj
->size
;
1245 /* Get a DRM GEM mmap offset allocated... */
1246 list
->file_offset_node
= drm_mm_search_free(&mm
->offset_manager
,
1247 obj
->size
/ PAGE_SIZE
, 0, 0);
1248 if (!list
->file_offset_node
) {
1249 DRM_ERROR("failed to allocate offset for bo %d\n", obj
->name
);
1254 list
->file_offset_node
= drm_mm_get_block(list
->file_offset_node
,
1255 obj
->size
/ PAGE_SIZE
, 0);
1256 if (!list
->file_offset_node
) {
1261 list
->hash
.key
= list
->file_offset_node
->start
;
1262 if (drm_ht_insert_item(&mm
->offset_hash
, &list
->hash
)) {
1263 DRM_ERROR("failed to add to map hash\n");
1268 /* By now we should be all set, any drm_mmap request on the offset
1269 * below will get to our mmap & fault handler */
1270 obj_priv
->mmap_offset
= ((uint64_t) list
->hash
.key
) << PAGE_SHIFT
;
1275 drm_mm_put_block(list
->file_offset_node
);
1283 * i915_gem_release_mmap - remove physical page mappings
1284 * @obj: obj in question
1286 * Preserve the reservation of the mmapping with the DRM core code, but
1287 * relinquish ownership of the pages back to the system.
1289 * It is vital that we remove the page mapping if we have mapped a tiled
1290 * object through the GTT and then lose the fence register due to
1291 * resource pressure. Similarly if the object has been moved out of the
1292 * aperture, than pages mapped into userspace must be revoked. Removing the
1293 * mapping will then trigger a page fault on the next user access, allowing
1294 * fixup by i915_gem_fault().
1297 i915_gem_release_mmap(struct drm_gem_object
*obj
)
1299 struct drm_device
*dev
= obj
->dev
;
1300 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1302 if (dev
->dev_mapping
)
1303 unmap_mapping_range(dev
->dev_mapping
,
1304 obj_priv
->mmap_offset
, obj
->size
, 1);
1308 i915_gem_free_mmap_offset(struct drm_gem_object
*obj
)
1310 struct drm_device
*dev
= obj
->dev
;
1311 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1312 struct drm_gem_mm
*mm
= dev
->mm_private
;
1313 struct drm_map_list
*list
;
1315 list
= &obj
->map_list
;
1316 drm_ht_remove_item(&mm
->offset_hash
, &list
->hash
);
1318 if (list
->file_offset_node
) {
1319 drm_mm_put_block(list
->file_offset_node
);
1320 list
->file_offset_node
= NULL
;
1328 obj_priv
->mmap_offset
= 0;
1332 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1333 * @obj: object to check
1335 * Return the required GTT alignment for an object, taking into account
1336 * potential fence register mapping if needed.
1339 i915_gem_get_gtt_alignment(struct drm_gem_object
*obj
)
1341 struct drm_device
*dev
= obj
->dev
;
1342 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1346 * Minimum alignment is 4k (GTT page size), but might be greater
1347 * if a fence register is needed for the object.
1349 if (INTEL_INFO(dev
)->gen
>= 4 || obj_priv
->tiling_mode
== I915_TILING_NONE
)
1353 * Previous chips need to be aligned to the size of the smallest
1354 * fence register that can contain the object.
1356 if (INTEL_INFO(dev
)->gen
== 3)
1361 for (i
= start
; i
< obj
->size
; i
<<= 1)
1368 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1370 * @data: GTT mapping ioctl data
1371 * @file_priv: GEM object info
1373 * Simply returns the fake offset to userspace so it can mmap it.
1374 * The mmap call will end up in drm_gem_mmap(), which will set things
1375 * up so we can get faults in the handler above.
1377 * The fault handler will take care of binding the object into the GTT
1378 * (since it may have been evicted to make room for something), allocating
1379 * a fence register, and mapping the appropriate aperture address into
1383 i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
1384 struct drm_file
*file_priv
)
1386 struct drm_i915_gem_mmap_gtt
*args
= data
;
1387 struct drm_gem_object
*obj
;
1388 struct drm_i915_gem_object
*obj_priv
;
1391 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1394 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1398 mutex_lock(&dev
->struct_mutex
);
1400 obj_priv
= to_intel_bo(obj
);
1402 if (obj_priv
->madv
!= I915_MADV_WILLNEED
) {
1403 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1404 drm_gem_object_unreference(obj
);
1405 mutex_unlock(&dev
->struct_mutex
);
1410 if (!obj_priv
->mmap_offset
) {
1411 ret
= i915_gem_create_mmap_offset(obj
);
1413 drm_gem_object_unreference(obj
);
1414 mutex_unlock(&dev
->struct_mutex
);
1419 args
->offset
= obj_priv
->mmap_offset
;
1422 * Pull it into the GTT so that we have a page list (makes the
1423 * initial fault faster and any subsequent flushing possible).
1425 if (!obj_priv
->agp_mem
) {
1426 ret
= i915_gem_object_bind_to_gtt(obj
, 0);
1428 drm_gem_object_unreference(obj
);
1429 mutex_unlock(&dev
->struct_mutex
);
1434 drm_gem_object_unreference(obj
);
1435 mutex_unlock(&dev
->struct_mutex
);
1441 i915_gem_object_put_pages(struct drm_gem_object
*obj
)
1443 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1444 int page_count
= obj
->size
/ PAGE_SIZE
;
1447 BUG_ON(obj_priv
->pages_refcount
== 0);
1448 BUG_ON(obj_priv
->madv
== __I915_MADV_PURGED
);
1450 if (--obj_priv
->pages_refcount
!= 0)
1453 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
)
1454 i915_gem_object_save_bit_17_swizzle(obj
);
1456 if (obj_priv
->madv
== I915_MADV_DONTNEED
)
1457 obj_priv
->dirty
= 0;
1459 for (i
= 0; i
< page_count
; i
++) {
1460 if (obj_priv
->dirty
)
1461 set_page_dirty(obj_priv
->pages
[i
]);
1463 if (obj_priv
->madv
== I915_MADV_WILLNEED
)
1464 mark_page_accessed(obj_priv
->pages
[i
]);
1466 page_cache_release(obj_priv
->pages
[i
]);
1468 obj_priv
->dirty
= 0;
1470 drm_free_large(obj_priv
->pages
);
1471 obj_priv
->pages
= NULL
;
1475 i915_gem_next_request_seqno(struct drm_device
*dev
,
1476 struct intel_ring_buffer
*ring
)
1478 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1480 ring
->outstanding_lazy_request
= true;
1482 return dev_priv
->next_seqno
;
1486 i915_gem_object_move_to_active(struct drm_gem_object
*obj
,
1487 struct intel_ring_buffer
*ring
)
1489 struct drm_device
*dev
= obj
->dev
;
1490 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1491 uint32_t seqno
= i915_gem_next_request_seqno(dev
, ring
);
1493 BUG_ON(ring
== NULL
);
1494 obj_priv
->ring
= ring
;
1496 /* Add a reference if we're newly entering the active list. */
1497 if (!obj_priv
->active
) {
1498 drm_gem_object_reference(obj
);
1499 obj_priv
->active
= 1;
1502 /* Move from whatever list we were on to the tail of execution. */
1503 list_move_tail(&obj_priv
->list
, &ring
->active_list
);
1504 obj_priv
->last_rendering_seqno
= seqno
;
1508 i915_gem_object_move_to_flushing(struct drm_gem_object
*obj
)
1510 struct drm_device
*dev
= obj
->dev
;
1511 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1512 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1514 BUG_ON(!obj_priv
->active
);
1515 list_move_tail(&obj_priv
->list
, &dev_priv
->mm
.flushing_list
);
1516 obj_priv
->last_rendering_seqno
= 0;
1519 /* Immediately discard the backing storage */
1521 i915_gem_object_truncate(struct drm_gem_object
*obj
)
1523 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1524 struct inode
*inode
;
1526 /* Our goal here is to return as much of the memory as
1527 * is possible back to the system as we are called from OOM.
1528 * To do this we must instruct the shmfs to drop all of its
1529 * backing pages, *now*. Here we mirror the actions taken
1530 * when by shmem_delete_inode() to release the backing store.
1532 inode
= obj
->filp
->f_path
.dentry
->d_inode
;
1533 truncate_inode_pages(inode
->i_mapping
, 0);
1534 if (inode
->i_op
->truncate_range
)
1535 inode
->i_op
->truncate_range(inode
, 0, (loff_t
)-1);
1537 obj_priv
->madv
= __I915_MADV_PURGED
;
1541 i915_gem_object_is_purgeable(struct drm_i915_gem_object
*obj_priv
)
1543 return obj_priv
->madv
== I915_MADV_DONTNEED
;
1547 i915_gem_object_move_to_inactive(struct drm_gem_object
*obj
)
1549 struct drm_device
*dev
= obj
->dev
;
1550 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1551 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1553 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
1554 if (obj_priv
->pin_count
!= 0)
1555 list_del_init(&obj_priv
->list
);
1557 list_move_tail(&obj_priv
->list
, &dev_priv
->mm
.inactive_list
);
1559 BUG_ON(!list_empty(&obj_priv
->gpu_write_list
));
1561 obj_priv
->last_rendering_seqno
= 0;
1562 obj_priv
->ring
= NULL
;
1563 if (obj_priv
->active
) {
1564 obj_priv
->active
= 0;
1565 drm_gem_object_unreference(obj
);
1567 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
1571 i915_gem_process_flushing_list(struct drm_device
*dev
,
1572 uint32_t flush_domains
,
1573 struct intel_ring_buffer
*ring
)
1575 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1576 struct drm_i915_gem_object
*obj_priv
, *next
;
1578 list_for_each_entry_safe(obj_priv
, next
,
1579 &dev_priv
->mm
.gpu_write_list
,
1581 struct drm_gem_object
*obj
= &obj_priv
->base
;
1583 if (obj
->write_domain
& flush_domains
&&
1584 obj_priv
->ring
== ring
) {
1585 uint32_t old_write_domain
= obj
->write_domain
;
1587 obj
->write_domain
= 0;
1588 list_del_init(&obj_priv
->gpu_write_list
);
1589 i915_gem_object_move_to_active(obj
, ring
);
1591 /* update the fence lru list */
1592 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
) {
1593 struct drm_i915_fence_reg
*reg
=
1594 &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
1595 list_move_tail(®
->lru_list
,
1596 &dev_priv
->mm
.fence_list
);
1599 trace_i915_gem_object_change_domain(obj
,
1607 i915_add_request(struct drm_device
*dev
,
1608 struct drm_file
*file_priv
,
1609 struct drm_i915_gem_request
*request
,
1610 struct intel_ring_buffer
*ring
)
1612 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1613 struct drm_i915_file_private
*i915_file_priv
= NULL
;
1617 if (file_priv
!= NULL
)
1618 i915_file_priv
= file_priv
->driver_priv
;
1620 if (request
== NULL
) {
1621 request
= kzalloc(sizeof(*request
), GFP_KERNEL
);
1622 if (request
== NULL
)
1626 seqno
= ring
->add_request(dev
, ring
, file_priv
, 0);
1628 request
->seqno
= seqno
;
1629 request
->ring
= ring
;
1630 request
->emitted_jiffies
= jiffies
;
1631 was_empty
= list_empty(&ring
->request_list
);
1632 list_add_tail(&request
->list
, &ring
->request_list
);
1634 if (i915_file_priv
) {
1635 list_add_tail(&request
->client_list
,
1636 &i915_file_priv
->mm
.request_list
);
1638 INIT_LIST_HEAD(&request
->client_list
);
1641 if (!dev_priv
->mm
.suspended
) {
1642 mod_timer(&dev_priv
->hangcheck_timer
,
1643 jiffies
+ msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD
));
1645 queue_delayed_work(dev_priv
->wq
,
1646 &dev_priv
->mm
.retire_work
, HZ
);
1652 * Command execution barrier
1654 * Ensures that all commands in the ring are finished
1655 * before signalling the CPU
1658 i915_retire_commands(struct drm_device
*dev
, struct intel_ring_buffer
*ring
)
1660 uint32_t flush_domains
= 0;
1662 /* The sampler always gets flushed on i965 (sigh) */
1663 if (INTEL_INFO(dev
)->gen
>= 4)
1664 flush_domains
|= I915_GEM_DOMAIN_SAMPLER
;
1666 ring
->flush(dev
, ring
,
1667 I915_GEM_DOMAIN_COMMAND
, flush_domains
);
1671 * Returns true if seq1 is later than seq2.
1674 i915_seqno_passed(uint32_t seq1
, uint32_t seq2
)
1676 return (int32_t)(seq1
- seq2
) >= 0;
1680 i915_get_gem_seqno(struct drm_device
*dev
,
1681 struct intel_ring_buffer
*ring
)
1683 return ring
->get_gem_seqno(dev
, ring
);
1687 * This function clears the request list as sequence numbers are passed.
1690 i915_gem_retire_requests_ring(struct drm_device
*dev
,
1691 struct intel_ring_buffer
*ring
)
1693 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1697 if (!ring
->status_page
.page_addr
||
1698 list_empty(&ring
->request_list
))
1701 seqno
= i915_get_gem_seqno(dev
, ring
);
1702 wedged
= atomic_read(&dev_priv
->mm
.wedged
);
1704 while (!list_empty(&ring
->request_list
)) {
1705 struct drm_i915_gem_request
*request
;
1707 request
= list_first_entry(&ring
->request_list
,
1708 struct drm_i915_gem_request
,
1711 if (!wedged
&& !i915_seqno_passed(seqno
, request
->seqno
))
1714 trace_i915_gem_request_retire(dev
, request
->seqno
);
1716 list_del(&request
->list
);
1717 list_del(&request
->client_list
);
1721 /* Move any buffers on the active list that are no longer referenced
1722 * by the ringbuffer to the flushing/inactive lists as appropriate.
1724 while (!list_empty(&ring
->active_list
)) {
1725 struct drm_gem_object
*obj
;
1726 struct drm_i915_gem_object
*obj_priv
;
1728 obj_priv
= list_first_entry(&ring
->active_list
,
1729 struct drm_i915_gem_object
,
1733 !i915_seqno_passed(seqno
, obj_priv
->last_rendering_seqno
))
1736 obj
= &obj_priv
->base
;
1739 DRM_INFO("%s: retire %d moves to inactive list %p\n",
1740 __func__
, request
->seqno
, obj
);
1743 if (obj
->write_domain
!= 0)
1744 i915_gem_object_move_to_flushing(obj
);
1746 i915_gem_object_move_to_inactive(obj
);
1749 if (unlikely (dev_priv
->trace_irq_seqno
&&
1750 i915_seqno_passed(dev_priv
->trace_irq_seqno
, seqno
))) {
1751 ring
->user_irq_put(dev
, ring
);
1752 dev_priv
->trace_irq_seqno
= 0;
1757 i915_gem_retire_requests(struct drm_device
*dev
)
1759 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1761 if (!list_empty(&dev_priv
->mm
.deferred_free_list
)) {
1762 struct drm_i915_gem_object
*obj_priv
, *tmp
;
1764 /* We must be careful that during unbind() we do not
1765 * accidentally infinitely recurse into retire requests.
1767 * retire -> free -> unbind -> wait -> retire_ring
1769 list_for_each_entry_safe(obj_priv
, tmp
,
1770 &dev_priv
->mm
.deferred_free_list
,
1772 i915_gem_free_object_tail(&obj_priv
->base
);
1775 i915_gem_retire_requests_ring(dev
, &dev_priv
->render_ring
);
1777 i915_gem_retire_requests_ring(dev
, &dev_priv
->bsd_ring
);
1781 i915_gem_retire_work_handler(struct work_struct
*work
)
1783 drm_i915_private_t
*dev_priv
;
1784 struct drm_device
*dev
;
1786 dev_priv
= container_of(work
, drm_i915_private_t
,
1787 mm
.retire_work
.work
);
1788 dev
= dev_priv
->dev
;
1790 mutex_lock(&dev
->struct_mutex
);
1791 i915_gem_retire_requests(dev
);
1793 if (!dev_priv
->mm
.suspended
&&
1794 (!list_empty(&dev_priv
->render_ring
.request_list
) ||
1796 !list_empty(&dev_priv
->bsd_ring
.request_list
))))
1797 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, HZ
);
1798 mutex_unlock(&dev
->struct_mutex
);
1802 i915_do_wait_request(struct drm_device
*dev
, uint32_t seqno
,
1803 bool interruptible
, struct intel_ring_buffer
*ring
)
1805 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1811 if (seqno
== dev_priv
->next_seqno
) {
1812 seqno
= i915_add_request(dev
, NULL
, NULL
, ring
);
1817 if (atomic_read(&dev_priv
->mm
.wedged
))
1820 if (!i915_seqno_passed(ring
->get_gem_seqno(dev
, ring
), seqno
)) {
1821 if (HAS_PCH_SPLIT(dev
))
1822 ier
= I915_READ(DEIER
) | I915_READ(GTIER
);
1824 ier
= I915_READ(IER
);
1826 DRM_ERROR("something (likely vbetool) disabled "
1827 "interrupts, re-enabling\n");
1828 i915_driver_irq_preinstall(dev
);
1829 i915_driver_irq_postinstall(dev
);
1832 trace_i915_gem_request_wait_begin(dev
, seqno
);
1834 ring
->waiting_gem_seqno
= seqno
;
1835 ring
->user_irq_get(dev
, ring
);
1837 ret
= wait_event_interruptible(ring
->irq_queue
,
1839 ring
->get_gem_seqno(dev
, ring
), seqno
)
1840 || atomic_read(&dev_priv
->mm
.wedged
));
1842 wait_event(ring
->irq_queue
,
1844 ring
->get_gem_seqno(dev
, ring
), seqno
)
1845 || atomic_read(&dev_priv
->mm
.wedged
));
1847 ring
->user_irq_put(dev
, ring
);
1848 ring
->waiting_gem_seqno
= 0;
1850 trace_i915_gem_request_wait_end(dev
, seqno
);
1852 if (atomic_read(&dev_priv
->mm
.wedged
))
1855 if (ret
&& ret
!= -ERESTARTSYS
)
1856 DRM_ERROR("%s returns %d (awaiting %d at %d, next %d)\n",
1857 __func__
, ret
, seqno
, ring
->get_gem_seqno(dev
, ring
),
1858 dev_priv
->next_seqno
);
1860 /* Directly dispatch request retiring. While we have the work queue
1861 * to handle this, the waiter on a request often wants an associated
1862 * buffer to have made it to the inactive list, and we would need
1863 * a separate wait queue to handle that.
1866 i915_gem_retire_requests_ring(dev
, ring
);
1872 * Waits for a sequence number to be signaled, and cleans up the
1873 * request and object lists appropriately for that event.
1876 i915_wait_request(struct drm_device
*dev
, uint32_t seqno
,
1877 struct intel_ring_buffer
*ring
)
1879 return i915_do_wait_request(dev
, seqno
, 1, ring
);
1883 i915_gem_flush_ring(struct drm_device
*dev
,
1884 struct intel_ring_buffer
*ring
,
1885 uint32_t invalidate_domains
,
1886 uint32_t flush_domains
)
1888 ring
->flush(dev
, ring
, invalidate_domains
, flush_domains
);
1889 i915_gem_process_flushing_list(dev
, flush_domains
, ring
);
1893 i915_gem_flush(struct drm_device
*dev
,
1894 uint32_t invalidate_domains
,
1895 uint32_t flush_domains
,
1896 uint32_t flush_rings
)
1898 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1900 if (flush_domains
& I915_GEM_DOMAIN_CPU
)
1901 drm_agp_chipset_flush(dev
);
1903 if ((flush_domains
| invalidate_domains
) & I915_GEM_GPU_DOMAINS
) {
1904 if (flush_rings
& RING_RENDER
)
1905 i915_gem_flush_ring(dev
,
1906 &dev_priv
->render_ring
,
1907 invalidate_domains
, flush_domains
);
1908 if (flush_rings
& RING_BSD
)
1909 i915_gem_flush_ring(dev
,
1910 &dev_priv
->bsd_ring
,
1911 invalidate_domains
, flush_domains
);
1916 * Ensures that all rendering to the object has completed and the object is
1917 * safe to unbind from the GTT or access from the CPU.
1920 i915_gem_object_wait_rendering(struct drm_gem_object
*obj
,
1923 struct drm_device
*dev
= obj
->dev
;
1924 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1927 /* This function only exists to support waiting for existing rendering,
1928 * not for emitting required flushes.
1930 BUG_ON((obj
->write_domain
& I915_GEM_GPU_DOMAINS
) != 0);
1932 /* If there is rendering queued on the buffer being evicted, wait for
1935 if (obj_priv
->active
) {
1937 DRM_INFO("%s: object %p wait for seqno %08x\n",
1938 __func__
, obj
, obj_priv
->last_rendering_seqno
);
1940 ret
= i915_do_wait_request(dev
,
1941 obj_priv
->last_rendering_seqno
,
1952 * Unbinds an object from the GTT aperture.
1955 i915_gem_object_unbind(struct drm_gem_object
*obj
)
1957 struct drm_device
*dev
= obj
->dev
;
1958 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1962 DRM_INFO("%s:%d %p\n", __func__
, __LINE__
, obj
);
1963 DRM_INFO("gtt_space %p\n", obj_priv
->gtt_space
);
1965 if (obj_priv
->gtt_space
== NULL
)
1968 if (obj_priv
->pin_count
!= 0) {
1969 DRM_ERROR("Attempting to unbind pinned buffer\n");
1973 /* blow away mappings if mapped through GTT */
1974 i915_gem_release_mmap(obj
);
1976 /* Move the object to the CPU domain to ensure that
1977 * any possible CPU writes while it's not in the GTT
1978 * are flushed when we go to remap it. This will
1979 * also ensure that all pending GPU writes are finished
1982 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
1983 if (ret
== -ERESTARTSYS
)
1985 /* Continue on if we fail due to EIO, the GPU is hung so we
1986 * should be safe and we need to cleanup or else we might
1987 * cause memory corruption through use-after-free.
1990 /* release the fence reg _after_ flushing */
1991 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
)
1992 i915_gem_clear_fence_reg(obj
);
1994 if (obj_priv
->agp_mem
!= NULL
) {
1995 drm_unbind_agp(obj_priv
->agp_mem
);
1996 drm_free_agp(obj_priv
->agp_mem
, obj
->size
/ PAGE_SIZE
);
1997 obj_priv
->agp_mem
= NULL
;
2000 i915_gem_object_put_pages(obj
);
2001 BUG_ON(obj_priv
->pages_refcount
);
2003 if (obj_priv
->gtt_space
) {
2004 atomic_dec(&dev
->gtt_count
);
2005 atomic_sub(obj
->size
, &dev
->gtt_memory
);
2007 drm_mm_put_block(obj_priv
->gtt_space
);
2008 obj_priv
->gtt_space
= NULL
;
2011 /* Remove ourselves from the LRU list if present. */
2012 if (!list_empty(&obj_priv
->list
))
2013 list_del_init(&obj_priv
->list
);
2015 if (i915_gem_object_is_purgeable(obj_priv
))
2016 i915_gem_object_truncate(obj
);
2018 trace_i915_gem_object_unbind(obj
);
2024 i915_gpu_idle(struct drm_device
*dev
)
2026 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2030 lists_empty
= (list_empty(&dev_priv
->mm
.flushing_list
) &&
2031 list_empty(&dev_priv
->render_ring
.active_list
) &&
2033 list_empty(&dev_priv
->bsd_ring
.active_list
)));
2037 /* Flush everything onto the inactive list. */
2038 i915_gem_flush_ring(dev
,
2039 &dev_priv
->render_ring
,
2040 I915_GEM_GPU_DOMAINS
, I915_GEM_GPU_DOMAINS
);
2042 ret
= i915_wait_request(dev
,
2043 i915_gem_next_request_seqno(dev
, &dev_priv
->render_ring
),
2044 &dev_priv
->render_ring
);
2049 i915_gem_flush_ring(dev
,
2050 &dev_priv
->bsd_ring
,
2051 I915_GEM_GPU_DOMAINS
, I915_GEM_GPU_DOMAINS
);
2053 ret
= i915_wait_request(dev
,
2054 i915_gem_next_request_seqno(dev
, &dev_priv
->bsd_ring
),
2055 &dev_priv
->bsd_ring
);
2064 i915_gem_object_get_pages(struct drm_gem_object
*obj
,
2067 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2069 struct address_space
*mapping
;
2070 struct inode
*inode
;
2073 BUG_ON(obj_priv
->pages_refcount
2074 == DRM_I915_GEM_OBJECT_MAX_PAGES_REFCOUNT
);
2076 if (obj_priv
->pages_refcount
++ != 0)
2079 /* Get the list of pages out of our struct file. They'll be pinned
2080 * at this point until we release them.
2082 page_count
= obj
->size
/ PAGE_SIZE
;
2083 BUG_ON(obj_priv
->pages
!= NULL
);
2084 obj_priv
->pages
= drm_calloc_large(page_count
, sizeof(struct page
*));
2085 if (obj_priv
->pages
== NULL
) {
2086 obj_priv
->pages_refcount
--;
2090 inode
= obj
->filp
->f_path
.dentry
->d_inode
;
2091 mapping
= inode
->i_mapping
;
2092 for (i
= 0; i
< page_count
; i
++) {
2093 page
= read_cache_page_gfp(mapping
, i
,
2101 obj_priv
->pages
[i
] = page
;
2104 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
)
2105 i915_gem_object_do_bit_17_swizzle(obj
);
2111 page_cache_release(obj_priv
->pages
[i
]);
2113 drm_free_large(obj_priv
->pages
);
2114 obj_priv
->pages
= NULL
;
2115 obj_priv
->pages_refcount
--;
2116 return PTR_ERR(page
);
2119 static void sandybridge_write_fence_reg(struct drm_i915_fence_reg
*reg
)
2121 struct drm_gem_object
*obj
= reg
->obj
;
2122 struct drm_device
*dev
= obj
->dev
;
2123 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2124 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2125 int regnum
= obj_priv
->fence_reg
;
2128 val
= (uint64_t)((obj_priv
->gtt_offset
+ obj
->size
- 4096) &
2130 val
|= obj_priv
->gtt_offset
& 0xfffff000;
2131 val
|= (uint64_t)((obj_priv
->stride
/ 128) - 1) <<
2132 SANDYBRIDGE_FENCE_PITCH_SHIFT
;
2134 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2135 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
2136 val
|= I965_FENCE_REG_VALID
;
2138 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0
+ (regnum
* 8), val
);
2141 static void i965_write_fence_reg(struct drm_i915_fence_reg
*reg
)
2143 struct drm_gem_object
*obj
= reg
->obj
;
2144 struct drm_device
*dev
= obj
->dev
;
2145 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2146 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2147 int regnum
= obj_priv
->fence_reg
;
2150 val
= (uint64_t)((obj_priv
->gtt_offset
+ obj
->size
- 4096) &
2152 val
|= obj_priv
->gtt_offset
& 0xfffff000;
2153 val
|= ((obj_priv
->stride
/ 128) - 1) << I965_FENCE_PITCH_SHIFT
;
2154 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2155 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
2156 val
|= I965_FENCE_REG_VALID
;
2158 I915_WRITE64(FENCE_REG_965_0
+ (regnum
* 8), val
);
2161 static void i915_write_fence_reg(struct drm_i915_fence_reg
*reg
)
2163 struct drm_gem_object
*obj
= reg
->obj
;
2164 struct drm_device
*dev
= obj
->dev
;
2165 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2166 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2167 int regnum
= obj_priv
->fence_reg
;
2169 uint32_t fence_reg
, val
;
2172 if ((obj_priv
->gtt_offset
& ~I915_FENCE_START_MASK
) ||
2173 (obj_priv
->gtt_offset
& (obj
->size
- 1))) {
2174 WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
2175 __func__
, obj_priv
->gtt_offset
, obj
->size
);
2179 if (obj_priv
->tiling_mode
== I915_TILING_Y
&&
2180 HAS_128_BYTE_Y_TILING(dev
))
2185 /* Note: pitch better be a power of two tile widths */
2186 pitch_val
= obj_priv
->stride
/ tile_width
;
2187 pitch_val
= ffs(pitch_val
) - 1;
2189 if (obj_priv
->tiling_mode
== I915_TILING_Y
&&
2190 HAS_128_BYTE_Y_TILING(dev
))
2191 WARN_ON(pitch_val
> I830_FENCE_MAX_PITCH_VAL
);
2193 WARN_ON(pitch_val
> I915_FENCE_MAX_PITCH_VAL
);
2195 val
= obj_priv
->gtt_offset
;
2196 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2197 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2198 val
|= I915_FENCE_SIZE_BITS(obj
->size
);
2199 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2200 val
|= I830_FENCE_REG_VALID
;
2203 fence_reg
= FENCE_REG_830_0
+ (regnum
* 4);
2205 fence_reg
= FENCE_REG_945_8
+ ((regnum
- 8) * 4);
2206 I915_WRITE(fence_reg
, val
);
2209 static void i830_write_fence_reg(struct drm_i915_fence_reg
*reg
)
2211 struct drm_gem_object
*obj
= reg
->obj
;
2212 struct drm_device
*dev
= obj
->dev
;
2213 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2214 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2215 int regnum
= obj_priv
->fence_reg
;
2218 uint32_t fence_size_bits
;
2220 if ((obj_priv
->gtt_offset
& ~I830_FENCE_START_MASK
) ||
2221 (obj_priv
->gtt_offset
& (obj
->size
- 1))) {
2222 WARN(1, "%s: object 0x%08x not 512K or size aligned\n",
2223 __func__
, obj_priv
->gtt_offset
);
2227 pitch_val
= obj_priv
->stride
/ 128;
2228 pitch_val
= ffs(pitch_val
) - 1;
2229 WARN_ON(pitch_val
> I830_FENCE_MAX_PITCH_VAL
);
2231 val
= obj_priv
->gtt_offset
;
2232 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2233 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2234 fence_size_bits
= I830_FENCE_SIZE_BITS(obj
->size
);
2235 WARN_ON(fence_size_bits
& ~0x00000f00);
2236 val
|= fence_size_bits
;
2237 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2238 val
|= I830_FENCE_REG_VALID
;
2240 I915_WRITE(FENCE_REG_830_0
+ (regnum
* 4), val
);
2243 static int i915_find_fence_reg(struct drm_device
*dev
,
2246 struct drm_i915_fence_reg
*reg
= NULL
;
2247 struct drm_i915_gem_object
*obj_priv
= NULL
;
2248 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2249 struct drm_gem_object
*obj
= NULL
;
2252 /* First try to find a free reg */
2254 for (i
= dev_priv
->fence_reg_start
; i
< dev_priv
->num_fence_regs
; i
++) {
2255 reg
= &dev_priv
->fence_regs
[i
];
2259 obj_priv
= to_intel_bo(reg
->obj
);
2260 if (!obj_priv
->pin_count
)
2267 /* None available, try to steal one or wait for a user to finish */
2268 i
= I915_FENCE_REG_NONE
;
2269 list_for_each_entry(reg
, &dev_priv
->mm
.fence_list
,
2272 obj_priv
= to_intel_bo(obj
);
2274 if (obj_priv
->pin_count
)
2278 i
= obj_priv
->fence_reg
;
2282 BUG_ON(i
== I915_FENCE_REG_NONE
);
2284 /* We only have a reference on obj from the active list. put_fence_reg
2285 * might drop that one, causing a use-after-free in it. So hold a
2286 * private reference to obj like the other callers of put_fence_reg
2287 * (set_tiling ioctl) do. */
2288 drm_gem_object_reference(obj
);
2289 ret
= i915_gem_object_put_fence_reg(obj
, interruptible
);
2290 drm_gem_object_unreference(obj
);
2298 * i915_gem_object_get_fence_reg - set up a fence reg for an object
2299 * @obj: object to map through a fence reg
2301 * When mapping objects through the GTT, userspace wants to be able to write
2302 * to them without having to worry about swizzling if the object is tiled.
2304 * This function walks the fence regs looking for a free one for @obj,
2305 * stealing one if it can't find any.
2307 * It then sets up the reg based on the object's properties: address, pitch
2308 * and tiling format.
2311 i915_gem_object_get_fence_reg(struct drm_gem_object
*obj
,
2314 struct drm_device
*dev
= obj
->dev
;
2315 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2316 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2317 struct drm_i915_fence_reg
*reg
= NULL
;
2320 /* Just update our place in the LRU if our fence is getting used. */
2321 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
) {
2322 reg
= &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
2323 list_move_tail(®
->lru_list
, &dev_priv
->mm
.fence_list
);
2327 switch (obj_priv
->tiling_mode
) {
2328 case I915_TILING_NONE
:
2329 WARN(1, "allocating a fence for non-tiled object?\n");
2332 if (!obj_priv
->stride
)
2334 WARN((obj_priv
->stride
& (512 - 1)),
2335 "object 0x%08x is X tiled but has non-512B pitch\n",
2336 obj_priv
->gtt_offset
);
2339 if (!obj_priv
->stride
)
2341 WARN((obj_priv
->stride
& (128 - 1)),
2342 "object 0x%08x is Y tiled but has non-128B pitch\n",
2343 obj_priv
->gtt_offset
);
2347 ret
= i915_find_fence_reg(dev
, interruptible
);
2351 obj_priv
->fence_reg
= ret
;
2352 reg
= &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
2353 list_add_tail(®
->lru_list
, &dev_priv
->mm
.fence_list
);
2357 switch (INTEL_INFO(dev
)->gen
) {
2359 sandybridge_write_fence_reg(reg
);
2363 i965_write_fence_reg(reg
);
2366 i915_write_fence_reg(reg
);
2369 i830_write_fence_reg(reg
);
2373 trace_i915_gem_object_get_fence(obj
, obj_priv
->fence_reg
,
2374 obj_priv
->tiling_mode
);
2380 * i915_gem_clear_fence_reg - clear out fence register info
2381 * @obj: object to clear
2383 * Zeroes out the fence register itself and clears out the associated
2384 * data structures in dev_priv and obj_priv.
2387 i915_gem_clear_fence_reg(struct drm_gem_object
*obj
)
2389 struct drm_device
*dev
= obj
->dev
;
2390 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2391 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2392 struct drm_i915_fence_reg
*reg
=
2393 &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
2396 switch (INTEL_INFO(dev
)->gen
) {
2398 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0
+
2399 (obj_priv
->fence_reg
* 8), 0);
2403 I915_WRITE64(FENCE_REG_965_0
+ (obj_priv
->fence_reg
* 8), 0);
2406 if (obj_priv
->fence_reg
> 8)
2407 fence_reg
= FENCE_REG_945_8
+ (obj_priv
->fence_reg
- 8) * 4;
2410 fence_reg
= FENCE_REG_830_0
+ obj_priv
->fence_reg
* 4;
2412 I915_WRITE(fence_reg
, 0);
2417 obj_priv
->fence_reg
= I915_FENCE_REG_NONE
;
2418 list_del_init(®
->lru_list
);
2422 * i915_gem_object_put_fence_reg - waits on outstanding fenced access
2423 * to the buffer to finish, and then resets the fence register.
2424 * @obj: tiled object holding a fence register.
2425 * @bool: whether the wait upon the fence is interruptible
2427 * Zeroes out the fence register itself and clears out the associated
2428 * data structures in dev_priv and obj_priv.
2431 i915_gem_object_put_fence_reg(struct drm_gem_object
*obj
,
2434 struct drm_device
*dev
= obj
->dev
;
2435 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2437 if (obj_priv
->fence_reg
== I915_FENCE_REG_NONE
)
2440 /* If we've changed tiling, GTT-mappings of the object
2441 * need to re-fault to ensure that the correct fence register
2442 * setup is in place.
2444 i915_gem_release_mmap(obj
);
2446 /* On the i915, GPU access to tiled buffers is via a fence,
2447 * therefore we must wait for any outstanding access to complete
2448 * before clearing the fence.
2450 if (INTEL_INFO(dev
)->gen
< 4) {
2453 ret
= i915_gem_object_flush_gpu_write_domain(obj
, true);
2457 ret
= i915_gem_object_wait_rendering(obj
, interruptible
);
2462 i915_gem_object_flush_gtt_write_domain(obj
);
2463 i915_gem_clear_fence_reg(obj
);
2469 * Finds free space in the GTT aperture and binds the object there.
2472 i915_gem_object_bind_to_gtt(struct drm_gem_object
*obj
, unsigned alignment
)
2474 struct drm_device
*dev
= obj
->dev
;
2475 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2476 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2477 struct drm_mm_node
*free_space
;
2478 gfp_t gfpmask
= __GFP_NORETRY
| __GFP_NOWARN
;
2481 if (obj_priv
->madv
!= I915_MADV_WILLNEED
) {
2482 DRM_ERROR("Attempting to bind a purgeable object\n");
2487 alignment
= i915_gem_get_gtt_alignment(obj
);
2488 if (alignment
& (i915_gem_get_gtt_alignment(obj
) - 1)) {
2489 DRM_ERROR("Invalid object alignment requested %u\n", alignment
);
2493 /* If the object is bigger than the entire aperture, reject it early
2494 * before evicting everything in a vain attempt to find space.
2496 if (obj
->size
> dev
->gtt_total
) {
2497 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2502 free_space
= drm_mm_search_free(&dev_priv
->mm
.gtt_space
,
2503 obj
->size
, alignment
, 0);
2504 if (free_space
!= NULL
) {
2505 obj_priv
->gtt_space
= drm_mm_get_block(free_space
, obj
->size
,
2507 if (obj_priv
->gtt_space
!= NULL
)
2508 obj_priv
->gtt_offset
= obj_priv
->gtt_space
->start
;
2510 if (obj_priv
->gtt_space
== NULL
) {
2511 /* If the gtt is empty and we're still having trouble
2512 * fitting our object in, we're out of memory.
2515 DRM_INFO("%s: GTT full, evicting something\n", __func__
);
2517 ret
= i915_gem_evict_something(dev
, obj
->size
, alignment
);
2525 DRM_INFO("Binding object of size %zd at 0x%08x\n",
2526 obj
->size
, obj_priv
->gtt_offset
);
2528 ret
= i915_gem_object_get_pages(obj
, gfpmask
);
2530 drm_mm_put_block(obj_priv
->gtt_space
);
2531 obj_priv
->gtt_space
= NULL
;
2533 if (ret
== -ENOMEM
) {
2534 /* first try to clear up some space from the GTT */
2535 ret
= i915_gem_evict_something(dev
, obj
->size
,
2538 /* now try to shrink everyone else */
2553 /* Create an AGP memory structure pointing at our pages, and bind it
2556 obj_priv
->agp_mem
= drm_agp_bind_pages(dev
,
2558 obj
->size
>> PAGE_SHIFT
,
2559 obj_priv
->gtt_offset
,
2560 obj_priv
->agp_type
);
2561 if (obj_priv
->agp_mem
== NULL
) {
2562 i915_gem_object_put_pages(obj
);
2563 drm_mm_put_block(obj_priv
->gtt_space
);
2564 obj_priv
->gtt_space
= NULL
;
2566 ret
= i915_gem_evict_something(dev
, obj
->size
, alignment
);
2572 atomic_inc(&dev
->gtt_count
);
2573 atomic_add(obj
->size
, &dev
->gtt_memory
);
2575 /* keep track of bounds object by adding it to the inactive list */
2576 list_add_tail(&obj_priv
->list
, &dev_priv
->mm
.inactive_list
);
2578 /* Assert that the object is not currently in any GPU domain. As it
2579 * wasn't in the GTT, there shouldn't be any way it could have been in
2582 BUG_ON(obj
->read_domains
& I915_GEM_GPU_DOMAINS
);
2583 BUG_ON(obj
->write_domain
& I915_GEM_GPU_DOMAINS
);
2585 trace_i915_gem_object_bind(obj
, obj_priv
->gtt_offset
);
2591 i915_gem_clflush_object(struct drm_gem_object
*obj
)
2593 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2595 /* If we don't have a page list set up, then we're not pinned
2596 * to GPU, and we can ignore the cache flush because it'll happen
2597 * again at bind time.
2599 if (obj_priv
->pages
== NULL
)
2602 trace_i915_gem_object_clflush(obj
);
2604 drm_clflush_pages(obj_priv
->pages
, obj
->size
/ PAGE_SIZE
);
2607 /** Flushes any GPU write domain for the object if it's dirty. */
2609 i915_gem_object_flush_gpu_write_domain(struct drm_gem_object
*obj
,
2612 struct drm_device
*dev
= obj
->dev
;
2613 uint32_t old_write_domain
;
2615 if ((obj
->write_domain
& I915_GEM_GPU_DOMAINS
) == 0)
2618 /* Queue the GPU write cache flushing we need. */
2619 old_write_domain
= obj
->write_domain
;
2620 i915_gem_flush_ring(dev
,
2621 to_intel_bo(obj
)->ring
,
2622 0, obj
->write_domain
);
2623 BUG_ON(obj
->write_domain
);
2625 trace_i915_gem_object_change_domain(obj
,
2632 return i915_gem_object_wait_rendering(obj
, true);
2635 /** Flushes the GTT write domain for the object if it's dirty. */
2637 i915_gem_object_flush_gtt_write_domain(struct drm_gem_object
*obj
)
2639 uint32_t old_write_domain
;
2641 if (obj
->write_domain
!= I915_GEM_DOMAIN_GTT
)
2644 /* No actual flushing is required for the GTT write domain. Writes
2645 * to it immediately go to main memory as far as we know, so there's
2646 * no chipset flush. It also doesn't land in render cache.
2648 old_write_domain
= obj
->write_domain
;
2649 obj
->write_domain
= 0;
2651 trace_i915_gem_object_change_domain(obj
,
2656 /** Flushes the CPU write domain for the object if it's dirty. */
2658 i915_gem_object_flush_cpu_write_domain(struct drm_gem_object
*obj
)
2660 struct drm_device
*dev
= obj
->dev
;
2661 uint32_t old_write_domain
;
2663 if (obj
->write_domain
!= I915_GEM_DOMAIN_CPU
)
2666 i915_gem_clflush_object(obj
);
2667 drm_agp_chipset_flush(dev
);
2668 old_write_domain
= obj
->write_domain
;
2669 obj
->write_domain
= 0;
2671 trace_i915_gem_object_change_domain(obj
,
2677 * Moves a single object to the GTT read, and possibly write domain.
2679 * This function returns when the move is complete, including waiting on
2683 i915_gem_object_set_to_gtt_domain(struct drm_gem_object
*obj
, int write
)
2685 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2686 uint32_t old_write_domain
, old_read_domains
;
2689 /* Not valid to be called on unbound objects. */
2690 if (obj_priv
->gtt_space
== NULL
)
2693 ret
= i915_gem_object_flush_gpu_write_domain(obj
, false);
2697 i915_gem_object_flush_cpu_write_domain(obj
);
2700 ret
= i915_gem_object_wait_rendering(obj
, true);
2705 old_write_domain
= obj
->write_domain
;
2706 old_read_domains
= obj
->read_domains
;
2708 /* It should now be out of any other write domains, and we can update
2709 * the domain values for our changes.
2711 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
2712 obj
->read_domains
|= I915_GEM_DOMAIN_GTT
;
2714 obj
->read_domains
= I915_GEM_DOMAIN_GTT
;
2715 obj
->write_domain
= I915_GEM_DOMAIN_GTT
;
2716 obj_priv
->dirty
= 1;
2719 trace_i915_gem_object_change_domain(obj
,
2727 * Prepare buffer for display plane. Use uninterruptible for possible flush
2728 * wait, as in modesetting process we're not supposed to be interrupted.
2731 i915_gem_object_set_to_display_plane(struct drm_gem_object
*obj
,
2734 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2735 uint32_t old_read_domains
;
2738 /* Not valid to be called on unbound objects. */
2739 if (obj_priv
->gtt_space
== NULL
)
2742 ret
= i915_gem_object_flush_gpu_write_domain(obj
, pipelined
);
2746 i915_gem_object_flush_cpu_write_domain(obj
);
2748 old_read_domains
= obj
->read_domains
;
2749 obj
->read_domains
= I915_GEM_DOMAIN_GTT
;
2751 trace_i915_gem_object_change_domain(obj
,
2759 * Moves a single object to the CPU read, and possibly write domain.
2761 * This function returns when the move is complete, including waiting on
2765 i915_gem_object_set_to_cpu_domain(struct drm_gem_object
*obj
, int write
)
2767 uint32_t old_write_domain
, old_read_domains
;
2770 ret
= i915_gem_object_flush_gpu_write_domain(obj
, false);
2774 i915_gem_object_flush_gtt_write_domain(obj
);
2776 /* If we have a partially-valid cache of the object in the CPU,
2777 * finish invalidating it and free the per-page flags.
2779 i915_gem_object_set_to_full_cpu_read_domain(obj
);
2782 ret
= i915_gem_object_wait_rendering(obj
, true);
2787 old_write_domain
= obj
->write_domain
;
2788 old_read_domains
= obj
->read_domains
;
2790 /* Flush the CPU cache if it's still invalid. */
2791 if ((obj
->read_domains
& I915_GEM_DOMAIN_CPU
) == 0) {
2792 i915_gem_clflush_object(obj
);
2794 obj
->read_domains
|= I915_GEM_DOMAIN_CPU
;
2797 /* It should now be out of any other write domains, and we can update
2798 * the domain values for our changes.
2800 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
2802 /* If we're writing through the CPU, then the GPU read domains will
2803 * need to be invalidated at next use.
2806 obj
->read_domains
&= I915_GEM_DOMAIN_CPU
;
2807 obj
->write_domain
= I915_GEM_DOMAIN_CPU
;
2810 trace_i915_gem_object_change_domain(obj
,
2818 * Set the next domain for the specified object. This
2819 * may not actually perform the necessary flushing/invaliding though,
2820 * as that may want to be batched with other set_domain operations
2822 * This is (we hope) the only really tricky part of gem. The goal
2823 * is fairly simple -- track which caches hold bits of the object
2824 * and make sure they remain coherent. A few concrete examples may
2825 * help to explain how it works. For shorthand, we use the notation
2826 * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
2827 * a pair of read and write domain masks.
2829 * Case 1: the batch buffer
2835 * 5. Unmapped from GTT
2838 * Let's take these a step at a time
2841 * Pages allocated from the kernel may still have
2842 * cache contents, so we set them to (CPU, CPU) always.
2843 * 2. Written by CPU (using pwrite)
2844 * The pwrite function calls set_domain (CPU, CPU) and
2845 * this function does nothing (as nothing changes)
2847 * This function asserts that the object is not
2848 * currently in any GPU-based read or write domains
2850 * i915_gem_execbuffer calls set_domain (COMMAND, 0).
2851 * As write_domain is zero, this function adds in the
2852 * current read domains (CPU+COMMAND, 0).
2853 * flush_domains is set to CPU.
2854 * invalidate_domains is set to COMMAND
2855 * clflush is run to get data out of the CPU caches
2856 * then i915_dev_set_domain calls i915_gem_flush to
2857 * emit an MI_FLUSH and drm_agp_chipset_flush
2858 * 5. Unmapped from GTT
2859 * i915_gem_object_unbind calls set_domain (CPU, CPU)
2860 * flush_domains and invalidate_domains end up both zero
2861 * so no flushing/invalidating happens
2865 * Case 2: The shared render buffer
2869 * 3. Read/written by GPU
2870 * 4. set_domain to (CPU,CPU)
2871 * 5. Read/written by CPU
2872 * 6. Read/written by GPU
2875 * Same as last example, (CPU, CPU)
2877 * Nothing changes (assertions find that it is not in the GPU)
2878 * 3. Read/written by GPU
2879 * execbuffer calls set_domain (RENDER, RENDER)
2880 * flush_domains gets CPU
2881 * invalidate_domains gets GPU
2883 * MI_FLUSH and drm_agp_chipset_flush
2884 * 4. set_domain (CPU, CPU)
2885 * flush_domains gets GPU
2886 * invalidate_domains gets CPU
2887 * wait_rendering (obj) to make sure all drawing is complete.
2888 * This will include an MI_FLUSH to get the data from GPU
2890 * clflush (obj) to invalidate the CPU cache
2891 * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
2892 * 5. Read/written by CPU
2893 * cache lines are loaded and dirtied
2894 * 6. Read written by GPU
2895 * Same as last GPU access
2897 * Case 3: The constant buffer
2902 * 4. Updated (written) by CPU again
2911 * flush_domains = CPU
2912 * invalidate_domains = RENDER
2915 * drm_agp_chipset_flush
2916 * 4. Updated (written) by CPU again
2918 * flush_domains = 0 (no previous write domain)
2919 * invalidate_domains = 0 (no new read domains)
2922 * flush_domains = CPU
2923 * invalidate_domains = RENDER
2926 * drm_agp_chipset_flush
2929 i915_gem_object_set_to_gpu_domain(struct drm_gem_object
*obj
)
2931 struct drm_device
*dev
= obj
->dev
;
2932 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2933 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2934 uint32_t invalidate_domains
= 0;
2935 uint32_t flush_domains
= 0;
2936 uint32_t old_read_domains
;
2938 BUG_ON(obj
->pending_read_domains
& I915_GEM_DOMAIN_CPU
);
2939 BUG_ON(obj
->pending_write_domain
== I915_GEM_DOMAIN_CPU
);
2941 intel_mark_busy(dev
, obj
);
2944 DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
2946 obj
->read_domains
, obj
->pending_read_domains
,
2947 obj
->write_domain
, obj
->pending_write_domain
);
2950 * If the object isn't moving to a new write domain,
2951 * let the object stay in multiple read domains
2953 if (obj
->pending_write_domain
== 0)
2954 obj
->pending_read_domains
|= obj
->read_domains
;
2956 obj_priv
->dirty
= 1;
2959 * Flush the current write domain if
2960 * the new read domains don't match. Invalidate
2961 * any read domains which differ from the old
2964 if (obj
->write_domain
&&
2965 obj
->write_domain
!= obj
->pending_read_domains
) {
2966 flush_domains
|= obj
->write_domain
;
2967 invalidate_domains
|=
2968 obj
->pending_read_domains
& ~obj
->write_domain
;
2971 * Invalidate any read caches which may have
2972 * stale data. That is, any new read domains.
2974 invalidate_domains
|= obj
->pending_read_domains
& ~obj
->read_domains
;
2975 if ((flush_domains
| invalidate_domains
) & I915_GEM_DOMAIN_CPU
) {
2977 DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
2978 __func__
, flush_domains
, invalidate_domains
);
2980 i915_gem_clflush_object(obj
);
2983 old_read_domains
= obj
->read_domains
;
2985 /* The actual obj->write_domain will be updated with
2986 * pending_write_domain after we emit the accumulated flush for all
2987 * of our domain changes in execbuffers (which clears objects'
2988 * write_domains). So if we have a current write domain that we
2989 * aren't changing, set pending_write_domain to that.
2991 if (flush_domains
== 0 && obj
->pending_write_domain
== 0)
2992 obj
->pending_write_domain
= obj
->write_domain
;
2993 obj
->read_domains
= obj
->pending_read_domains
;
2995 dev
->invalidate_domains
|= invalidate_domains
;
2996 dev
->flush_domains
|= flush_domains
;
2998 dev_priv
->mm
.flush_rings
|= obj_priv
->ring
->id
;
3000 DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n",
3002 obj
->read_domains
, obj
->write_domain
,
3003 dev
->invalidate_domains
, dev
->flush_domains
);
3006 trace_i915_gem_object_change_domain(obj
,
3012 * Moves the object from a partially CPU read to a full one.
3014 * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3015 * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
3018 i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object
*obj
)
3020 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
3022 if (!obj_priv
->page_cpu_valid
)
3025 /* If we're partially in the CPU read domain, finish moving it in.
3027 if (obj
->read_domains
& I915_GEM_DOMAIN_CPU
) {
3030 for (i
= 0; i
<= (obj
->size
- 1) / PAGE_SIZE
; i
++) {
3031 if (obj_priv
->page_cpu_valid
[i
])
3033 drm_clflush_pages(obj_priv
->pages
+ i
, 1);
3037 /* Free the page_cpu_valid mappings which are now stale, whether
3038 * or not we've got I915_GEM_DOMAIN_CPU.
3040 kfree(obj_priv
->page_cpu_valid
);
3041 obj_priv
->page_cpu_valid
= NULL
;
3045 * Set the CPU read domain on a range of the object.
3047 * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3048 * not entirely valid. The page_cpu_valid member of the object flags which
3049 * pages have been flushed, and will be respected by
3050 * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3051 * of the whole object.
3053 * This function returns when the move is complete, including waiting on
3057 i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object
*obj
,
3058 uint64_t offset
, uint64_t size
)
3060 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
3061 uint32_t old_read_domains
;
3064 if (offset
== 0 && size
== obj
->size
)
3065 return i915_gem_object_set_to_cpu_domain(obj
, 0);
3067 ret
= i915_gem_object_flush_gpu_write_domain(obj
, false);
3070 i915_gem_object_flush_gtt_write_domain(obj
);
3072 /* If we're already fully in the CPU read domain, we're done. */
3073 if (obj_priv
->page_cpu_valid
== NULL
&&
3074 (obj
->read_domains
& I915_GEM_DOMAIN_CPU
) != 0)
3077 /* Otherwise, create/clear the per-page CPU read domain flag if we're
3078 * newly adding I915_GEM_DOMAIN_CPU
3080 if (obj_priv
->page_cpu_valid
== NULL
) {
3081 obj_priv
->page_cpu_valid
= kzalloc(obj
->size
/ PAGE_SIZE
,
3083 if (obj_priv
->page_cpu_valid
== NULL
)
3085 } else if ((obj
->read_domains
& I915_GEM_DOMAIN_CPU
) == 0)
3086 memset(obj_priv
->page_cpu_valid
, 0, obj
->size
/ PAGE_SIZE
);
3088 /* Flush the cache on any pages that are still invalid from the CPU's
3091 for (i
= offset
/ PAGE_SIZE
; i
<= (offset
+ size
- 1) / PAGE_SIZE
;
3093 if (obj_priv
->page_cpu_valid
[i
])
3096 drm_clflush_pages(obj_priv
->pages
+ i
, 1);
3098 obj_priv
->page_cpu_valid
[i
] = 1;
3101 /* It should now be out of any other write domains, and we can update
3102 * the domain values for our changes.
3104 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
3106 old_read_domains
= obj
->read_domains
;
3107 obj
->read_domains
|= I915_GEM_DOMAIN_CPU
;
3109 trace_i915_gem_object_change_domain(obj
,
3117 * Pin an object to the GTT and evaluate the relocations landing in it.
3120 i915_gem_object_pin_and_relocate(struct drm_gem_object
*obj
,
3121 struct drm_file
*file_priv
,
3122 struct drm_i915_gem_exec_object2
*entry
,
3123 struct drm_i915_gem_relocation_entry
*relocs
)
3125 struct drm_device
*dev
= obj
->dev
;
3126 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3127 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
3129 void __iomem
*reloc_page
;
3132 need_fence
= entry
->flags
& EXEC_OBJECT_NEEDS_FENCE
&&
3133 obj_priv
->tiling_mode
!= I915_TILING_NONE
;
3135 /* Check fence reg constraints and rebind if necessary */
3137 !i915_gem_object_fence_offset_ok(obj
,
3138 obj_priv
->tiling_mode
)) {
3139 ret
= i915_gem_object_unbind(obj
);
3144 /* Choose the GTT offset for our buffer and put it there. */
3145 ret
= i915_gem_object_pin(obj
, (uint32_t) entry
->alignment
);
3150 * Pre-965 chips need a fence register set up in order to
3151 * properly handle blits to/from tiled surfaces.
3154 ret
= i915_gem_object_get_fence_reg(obj
, false);
3156 i915_gem_object_unpin(obj
);
3161 entry
->offset
= obj_priv
->gtt_offset
;
3163 /* Apply the relocations, using the GTT aperture to avoid cache
3164 * flushing requirements.
3166 for (i
= 0; i
< entry
->relocation_count
; i
++) {
3167 struct drm_i915_gem_relocation_entry
*reloc
= &relocs
[i
];
3168 struct drm_gem_object
*target_obj
;
3169 struct drm_i915_gem_object
*target_obj_priv
;
3170 uint32_t reloc_val
, reloc_offset
;
3171 uint32_t __iomem
*reloc_entry
;
3173 target_obj
= drm_gem_object_lookup(obj
->dev
, file_priv
,
3174 reloc
->target_handle
);
3175 if (target_obj
== NULL
) {
3176 i915_gem_object_unpin(obj
);
3179 target_obj_priv
= to_intel_bo(target_obj
);
3182 DRM_INFO("%s: obj %p offset %08x target %d "
3183 "read %08x write %08x gtt %08x "
3184 "presumed %08x delta %08x\n",
3187 (int) reloc
->offset
,
3188 (int) reloc
->target_handle
,
3189 (int) reloc
->read_domains
,
3190 (int) reloc
->write_domain
,
3191 (int) target_obj_priv
->gtt_offset
,
3192 (int) reloc
->presumed_offset
,
3196 /* The target buffer should have appeared before us in the
3197 * exec_object list, so it should have a GTT space bound by now.
3199 if (target_obj_priv
->gtt_space
== NULL
) {
3200 DRM_ERROR("No GTT space found for object %d\n",
3201 reloc
->target_handle
);
3202 drm_gem_object_unreference(target_obj
);
3203 i915_gem_object_unpin(obj
);
3207 /* Validate that the target is in a valid r/w GPU domain */
3208 if (reloc
->write_domain
& (reloc
->write_domain
- 1)) {
3209 DRM_ERROR("reloc with multiple write domains: "
3210 "obj %p target %d offset %d "
3211 "read %08x write %08x",
3212 obj
, reloc
->target_handle
,
3213 (int) reloc
->offset
,
3214 reloc
->read_domains
,
3215 reloc
->write_domain
);
3218 if (reloc
->write_domain
& I915_GEM_DOMAIN_CPU
||
3219 reloc
->read_domains
& I915_GEM_DOMAIN_CPU
) {
3220 DRM_ERROR("reloc with read/write CPU domains: "
3221 "obj %p target %d offset %d "
3222 "read %08x write %08x",
3223 obj
, reloc
->target_handle
,
3224 (int) reloc
->offset
,
3225 reloc
->read_domains
,
3226 reloc
->write_domain
);
3227 drm_gem_object_unreference(target_obj
);
3228 i915_gem_object_unpin(obj
);
3231 if (reloc
->write_domain
&& target_obj
->pending_write_domain
&&
3232 reloc
->write_domain
!= target_obj
->pending_write_domain
) {
3233 DRM_ERROR("Write domain conflict: "
3234 "obj %p target %d offset %d "
3235 "new %08x old %08x\n",
3236 obj
, reloc
->target_handle
,
3237 (int) reloc
->offset
,
3238 reloc
->write_domain
,
3239 target_obj
->pending_write_domain
);
3240 drm_gem_object_unreference(target_obj
);
3241 i915_gem_object_unpin(obj
);
3245 target_obj
->pending_read_domains
|= reloc
->read_domains
;
3246 target_obj
->pending_write_domain
|= reloc
->write_domain
;
3248 /* If the relocation already has the right value in it, no
3249 * more work needs to be done.
3251 if (target_obj_priv
->gtt_offset
== reloc
->presumed_offset
) {
3252 drm_gem_object_unreference(target_obj
);
3256 /* Check that the relocation address is valid... */
3257 if (reloc
->offset
> obj
->size
- 4) {
3258 DRM_ERROR("Relocation beyond object bounds: "
3259 "obj %p target %d offset %d size %d.\n",
3260 obj
, reloc
->target_handle
,
3261 (int) reloc
->offset
, (int) obj
->size
);
3262 drm_gem_object_unreference(target_obj
);
3263 i915_gem_object_unpin(obj
);
3266 if (reloc
->offset
& 3) {
3267 DRM_ERROR("Relocation not 4-byte aligned: "
3268 "obj %p target %d offset %d.\n",
3269 obj
, reloc
->target_handle
,
3270 (int) reloc
->offset
);
3271 drm_gem_object_unreference(target_obj
);
3272 i915_gem_object_unpin(obj
);
3276 /* and points to somewhere within the target object. */
3277 if (reloc
->delta
>= target_obj
->size
) {
3278 DRM_ERROR("Relocation beyond target object bounds: "
3279 "obj %p target %d delta %d size %d.\n",
3280 obj
, reloc
->target_handle
,
3281 (int) reloc
->delta
, (int) target_obj
->size
);
3282 drm_gem_object_unreference(target_obj
);
3283 i915_gem_object_unpin(obj
);
3287 ret
= i915_gem_object_set_to_gtt_domain(obj
, 1);
3289 drm_gem_object_unreference(target_obj
);
3290 i915_gem_object_unpin(obj
);
3294 /* Map the page containing the relocation we're going to
3297 reloc_offset
= obj_priv
->gtt_offset
+ reloc
->offset
;
3298 reloc_page
= io_mapping_map_atomic_wc(dev_priv
->mm
.gtt_mapping
,
3302 reloc_entry
= (uint32_t __iomem
*)(reloc_page
+
3303 (reloc_offset
& (PAGE_SIZE
- 1)));
3304 reloc_val
= target_obj_priv
->gtt_offset
+ reloc
->delta
;
3307 DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n",
3308 obj
, (unsigned int) reloc
->offset
,
3309 readl(reloc_entry
), reloc_val
);
3311 writel(reloc_val
, reloc_entry
);
3312 io_mapping_unmap_atomic(reloc_page
, KM_USER0
);
3314 /* The updated presumed offset for this entry will be
3315 * copied back out to the user.
3317 reloc
->presumed_offset
= target_obj_priv
->gtt_offset
;
3319 drm_gem_object_unreference(target_obj
);
3324 i915_gem_dump_object(obj
, 128, __func__
, ~0);
3329 /* Throttle our rendering by waiting until the ring has completed our requests
3330 * emitted over 20 msec ago.
3332 * Note that if we were to use the current jiffies each time around the loop,
3333 * we wouldn't escape the function with any frames outstanding if the time to
3334 * render a frame was over 20ms.
3336 * This should get us reasonable parallelism between CPU and GPU but also
3337 * relatively low latency when blocking on a particular request to finish.
3340 i915_gem_ring_throttle(struct drm_device
*dev
, struct drm_file
*file_priv
)
3342 struct drm_i915_file_private
*i915_file_priv
= file_priv
->driver_priv
;
3344 unsigned long recent_enough
= jiffies
- msecs_to_jiffies(20);
3346 mutex_lock(&dev
->struct_mutex
);
3347 while (!list_empty(&i915_file_priv
->mm
.request_list
)) {
3348 struct drm_i915_gem_request
*request
;
3350 request
= list_first_entry(&i915_file_priv
->mm
.request_list
,
3351 struct drm_i915_gem_request
,
3354 if (time_after_eq(request
->emitted_jiffies
, recent_enough
))
3357 ret
= i915_wait_request(dev
, request
->seqno
, request
->ring
);
3361 mutex_unlock(&dev
->struct_mutex
);
3367 i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object2
*exec_list
,
3368 uint32_t buffer_count
,
3369 struct drm_i915_gem_relocation_entry
**relocs
)
3371 uint32_t reloc_count
= 0, reloc_index
= 0, i
;
3375 for (i
= 0; i
< buffer_count
; i
++) {
3376 if (reloc_count
+ exec_list
[i
].relocation_count
< reloc_count
)
3378 reloc_count
+= exec_list
[i
].relocation_count
;
3381 *relocs
= drm_calloc_large(reloc_count
, sizeof(**relocs
));
3382 if (*relocs
== NULL
) {
3383 DRM_ERROR("failed to alloc relocs, count %d\n", reloc_count
);
3387 for (i
= 0; i
< buffer_count
; i
++) {
3388 struct drm_i915_gem_relocation_entry __user
*user_relocs
;
3390 user_relocs
= (void __user
*)(uintptr_t)exec_list
[i
].relocs_ptr
;
3392 ret
= copy_from_user(&(*relocs
)[reloc_index
],
3394 exec_list
[i
].relocation_count
*
3397 drm_free_large(*relocs
);
3402 reloc_index
+= exec_list
[i
].relocation_count
;
3409 i915_gem_put_relocs_to_user(struct drm_i915_gem_exec_object2
*exec_list
,
3410 uint32_t buffer_count
,
3411 struct drm_i915_gem_relocation_entry
*relocs
)
3413 uint32_t reloc_count
= 0, i
;
3419 for (i
= 0; i
< buffer_count
; i
++) {
3420 struct drm_i915_gem_relocation_entry __user
*user_relocs
;
3423 user_relocs
= (void __user
*)(uintptr_t)exec_list
[i
].relocs_ptr
;
3425 unwritten
= copy_to_user(user_relocs
,
3426 &relocs
[reloc_count
],
3427 exec_list
[i
].relocation_count
*
3435 reloc_count
+= exec_list
[i
].relocation_count
;
3439 drm_free_large(relocs
);
3445 i915_gem_check_execbuffer (struct drm_i915_gem_execbuffer2
*exec
,
3446 uint64_t exec_offset
)
3448 uint32_t exec_start
, exec_len
;
3450 exec_start
= (uint32_t) exec_offset
+ exec
->batch_start_offset
;
3451 exec_len
= (uint32_t) exec
->batch_len
;
3453 if ((exec_start
| exec_len
) & 0x7)
3463 i915_gem_wait_for_pending_flip(struct drm_device
*dev
,
3464 struct drm_gem_object
**object_list
,
3467 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3468 struct drm_i915_gem_object
*obj_priv
;
3473 prepare_to_wait(&dev_priv
->pending_flip_queue
,
3474 &wait
, TASK_INTERRUPTIBLE
);
3475 for (i
= 0; i
< count
; i
++) {
3476 obj_priv
= to_intel_bo(object_list
[i
]);
3477 if (atomic_read(&obj_priv
->pending_flip
) > 0)
3483 if (!signal_pending(current
)) {
3484 mutex_unlock(&dev
->struct_mutex
);
3486 mutex_lock(&dev
->struct_mutex
);
3492 finish_wait(&dev_priv
->pending_flip_queue
, &wait
);
3498 i915_gem_do_execbuffer(struct drm_device
*dev
, void *data
,
3499 struct drm_file
*file_priv
,
3500 struct drm_i915_gem_execbuffer2
*args
,
3501 struct drm_i915_gem_exec_object2
*exec_list
)
3503 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3504 struct drm_gem_object
**object_list
= NULL
;
3505 struct drm_gem_object
*batch_obj
;
3506 struct drm_i915_gem_object
*obj_priv
;
3507 struct drm_clip_rect
*cliprects
= NULL
;
3508 struct drm_i915_gem_relocation_entry
*relocs
= NULL
;
3509 struct drm_i915_gem_request
*request
= NULL
;
3510 int ret
= 0, ret2
, i
, pinned
= 0;
3511 uint64_t exec_offset
;
3512 uint32_t seqno
, reloc_index
;
3513 int pin_tries
, flips
;
3515 struct intel_ring_buffer
*ring
= NULL
;
3518 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3519 (int) args
->buffers_ptr
, args
->buffer_count
, args
->batch_len
);
3521 if (args
->flags
& I915_EXEC_BSD
) {
3522 if (!HAS_BSD(dev
)) {
3523 DRM_ERROR("execbuf with wrong flag\n");
3526 ring
= &dev_priv
->bsd_ring
;
3528 ring
= &dev_priv
->render_ring
;
3531 if (args
->buffer_count
< 1) {
3532 DRM_ERROR("execbuf with %d buffers\n", args
->buffer_count
);
3535 object_list
= drm_malloc_ab(sizeof(*object_list
), args
->buffer_count
);
3536 if (object_list
== NULL
) {
3537 DRM_ERROR("Failed to allocate object list for %d buffers\n",
3538 args
->buffer_count
);
3543 if (args
->num_cliprects
!= 0) {
3544 cliprects
= kcalloc(args
->num_cliprects
, sizeof(*cliprects
),
3546 if (cliprects
== NULL
) {
3551 ret
= copy_from_user(cliprects
,
3552 (struct drm_clip_rect __user
*)
3553 (uintptr_t) args
->cliprects_ptr
,
3554 sizeof(*cliprects
) * args
->num_cliprects
);
3556 DRM_ERROR("copy %d cliprects failed: %d\n",
3557 args
->num_cliprects
, ret
);
3563 request
= kzalloc(sizeof(*request
), GFP_KERNEL
);
3564 if (request
== NULL
) {
3569 ret
= i915_gem_get_relocs_from_user(exec_list
, args
->buffer_count
,
3574 mutex_lock(&dev
->struct_mutex
);
3576 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3578 if (atomic_read(&dev_priv
->mm
.wedged
)) {
3579 mutex_unlock(&dev
->struct_mutex
);
3584 if (dev_priv
->mm
.suspended
) {
3585 mutex_unlock(&dev
->struct_mutex
);
3590 /* Look up object handles */
3592 for (i
= 0; i
< args
->buffer_count
; i
++) {
3593 object_list
[i
] = drm_gem_object_lookup(dev
, file_priv
,
3594 exec_list
[i
].handle
);
3595 if (object_list
[i
] == NULL
) {
3596 DRM_ERROR("Invalid object handle %d at index %d\n",
3597 exec_list
[i
].handle
, i
);
3598 /* prevent error path from reading uninitialized data */
3599 args
->buffer_count
= i
+ 1;
3604 obj_priv
= to_intel_bo(object_list
[i
]);
3605 if (obj_priv
->in_execbuffer
) {
3606 DRM_ERROR("Object %p appears more than once in object list\n",
3608 /* prevent error path from reading uninitialized data */
3609 args
->buffer_count
= i
+ 1;
3613 obj_priv
->in_execbuffer
= true;
3614 flips
+= atomic_read(&obj_priv
->pending_flip
);
3618 ret
= i915_gem_wait_for_pending_flip(dev
, object_list
,
3619 args
->buffer_count
);
3624 /* Pin and relocate */
3625 for (pin_tries
= 0; ; pin_tries
++) {
3629 for (i
= 0; i
< args
->buffer_count
; i
++) {
3630 object_list
[i
]->pending_read_domains
= 0;
3631 object_list
[i
]->pending_write_domain
= 0;
3632 ret
= i915_gem_object_pin_and_relocate(object_list
[i
],
3635 &relocs
[reloc_index
]);
3639 reloc_index
+= exec_list
[i
].relocation_count
;
3645 /* error other than GTT full, or we've already tried again */
3646 if (ret
!= -ENOSPC
|| pin_tries
>= 1) {
3647 if (ret
!= -ERESTARTSYS
) {
3648 unsigned long long total_size
= 0;
3650 for (i
= 0; i
< args
->buffer_count
; i
++) {
3651 obj_priv
= to_intel_bo(object_list
[i
]);
3653 total_size
+= object_list
[i
]->size
;
3655 exec_list
[i
].flags
& EXEC_OBJECT_NEEDS_FENCE
&&
3656 obj_priv
->tiling_mode
!= I915_TILING_NONE
;
3658 DRM_ERROR("Failed to pin buffer %d of %d, total %llu bytes, %d fences: %d\n",
3659 pinned
+1, args
->buffer_count
,
3660 total_size
, num_fences
,
3662 DRM_ERROR("%d objects [%d pinned], "
3663 "%d object bytes [%d pinned], "
3664 "%d/%d gtt bytes\n",
3665 atomic_read(&dev
->object_count
),
3666 atomic_read(&dev
->pin_count
),
3667 atomic_read(&dev
->object_memory
),
3668 atomic_read(&dev
->pin_memory
),
3669 atomic_read(&dev
->gtt_memory
),
3675 /* unpin all of our buffers */
3676 for (i
= 0; i
< pinned
; i
++)
3677 i915_gem_object_unpin(object_list
[i
]);
3680 /* evict everyone we can from the aperture */
3681 ret
= i915_gem_evict_everything(dev
);
3682 if (ret
&& ret
!= -ENOSPC
)
3686 /* Set the pending read domains for the batch buffer to COMMAND */
3687 batch_obj
= object_list
[args
->buffer_count
-1];
3688 if (batch_obj
->pending_write_domain
) {
3689 DRM_ERROR("Attempting to use self-modifying batch buffer\n");
3693 batch_obj
->pending_read_domains
|= I915_GEM_DOMAIN_COMMAND
;
3695 /* Sanity check the batch buffer, prior to moving objects */
3696 exec_offset
= exec_list
[args
->buffer_count
- 1].offset
;
3697 ret
= i915_gem_check_execbuffer (args
, exec_offset
);
3699 DRM_ERROR("execbuf with invalid offset/length\n");
3703 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3705 /* Zero the global flush/invalidate flags. These
3706 * will be modified as new domains are computed
3709 dev
->invalidate_domains
= 0;
3710 dev
->flush_domains
= 0;
3711 dev_priv
->mm
.flush_rings
= 0;
3713 for (i
= 0; i
< args
->buffer_count
; i
++) {
3714 struct drm_gem_object
*obj
= object_list
[i
];
3716 /* Compute new gpu domains and update invalidate/flush */
3717 i915_gem_object_set_to_gpu_domain(obj
);
3720 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3722 if (dev
->invalidate_domains
| dev
->flush_domains
) {
3724 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
3726 dev
->invalidate_domains
,
3727 dev
->flush_domains
);
3730 dev
->invalidate_domains
,
3732 dev_priv
->mm
.flush_rings
);
3735 if (dev_priv
->render_ring
.outstanding_lazy_request
) {
3736 (void)i915_add_request(dev
, file_priv
, NULL
, &dev_priv
->render_ring
);
3737 dev_priv
->render_ring
.outstanding_lazy_request
= false;
3739 if (dev_priv
->bsd_ring
.outstanding_lazy_request
) {
3740 (void)i915_add_request(dev
, file_priv
, NULL
, &dev_priv
->bsd_ring
);
3741 dev_priv
->bsd_ring
.outstanding_lazy_request
= false;
3744 for (i
= 0; i
< args
->buffer_count
; i
++) {
3745 struct drm_gem_object
*obj
= object_list
[i
];
3746 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
3747 uint32_t old_write_domain
= obj
->write_domain
;
3749 obj
->write_domain
= obj
->pending_write_domain
;
3750 if (obj
->write_domain
)
3751 list_move_tail(&obj_priv
->gpu_write_list
,
3752 &dev_priv
->mm
.gpu_write_list
);
3754 list_del_init(&obj_priv
->gpu_write_list
);
3756 trace_i915_gem_object_change_domain(obj
,
3761 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3764 for (i
= 0; i
< args
->buffer_count
; i
++) {
3765 i915_gem_object_check_coherency(object_list
[i
],
3766 exec_list
[i
].handle
);
3771 i915_gem_dump_object(batch_obj
,
3777 /* Exec the batchbuffer */
3778 ret
= ring
->dispatch_gem_execbuffer(dev
, ring
, args
,
3779 cliprects
, exec_offset
);
3781 DRM_ERROR("dispatch failed %d\n", ret
);
3786 * Ensure that the commands in the batch buffer are
3787 * finished before the interrupt fires
3789 i915_retire_commands(dev
, ring
);
3791 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3793 for (i
= 0; i
< args
->buffer_count
; i
++) {
3794 struct drm_gem_object
*obj
= object_list
[i
];
3795 obj_priv
= to_intel_bo(obj
);
3797 i915_gem_object_move_to_active(obj
, ring
);
3799 DRM_INFO("%s: move to exec list %p\n", __func__
, obj
);
3804 * Get a seqno representing the execution of the current buffer,
3805 * which we can wait on. We would like to mitigate these interrupts,
3806 * likely by only creating seqnos occasionally (so that we have
3807 * *some* interrupts representing completion of buffers that we can
3808 * wait on when trying to clear up gtt space).
3810 seqno
= i915_add_request(dev
, file_priv
, request
, ring
);
3814 i915_dump_lru(dev
, __func__
);
3817 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3820 for (i
= 0; i
< pinned
; i
++)
3821 i915_gem_object_unpin(object_list
[i
]);
3823 for (i
= 0; i
< args
->buffer_count
; i
++) {
3824 if (object_list
[i
]) {
3825 obj_priv
= to_intel_bo(object_list
[i
]);
3826 obj_priv
->in_execbuffer
= false;
3828 drm_gem_object_unreference(object_list
[i
]);
3831 mutex_unlock(&dev
->struct_mutex
);
3834 /* Copy the updated relocations out regardless of current error
3835 * state. Failure to update the relocs would mean that the next
3836 * time userland calls execbuf, it would do so with presumed offset
3837 * state that didn't match the actual object state.
3839 ret2
= i915_gem_put_relocs_to_user(exec_list
, args
->buffer_count
,
3842 DRM_ERROR("Failed to copy relocations back out: %d\n", ret2
);
3848 drm_free_large(object_list
);
3856 * Legacy execbuffer just creates an exec2 list from the original exec object
3857 * list array and passes it to the real function.
3860 i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
3861 struct drm_file
*file_priv
)
3863 struct drm_i915_gem_execbuffer
*args
= data
;
3864 struct drm_i915_gem_execbuffer2 exec2
;
3865 struct drm_i915_gem_exec_object
*exec_list
= NULL
;
3866 struct drm_i915_gem_exec_object2
*exec2_list
= NULL
;
3870 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3871 (int) args
->buffers_ptr
, args
->buffer_count
, args
->batch_len
);
3874 if (args
->buffer_count
< 1) {
3875 DRM_ERROR("execbuf with %d buffers\n", args
->buffer_count
);
3879 /* Copy in the exec list from userland */
3880 exec_list
= drm_malloc_ab(sizeof(*exec_list
), args
->buffer_count
);
3881 exec2_list
= drm_malloc_ab(sizeof(*exec2_list
), args
->buffer_count
);
3882 if (exec_list
== NULL
|| exec2_list
== NULL
) {
3883 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
3884 args
->buffer_count
);
3885 drm_free_large(exec_list
);
3886 drm_free_large(exec2_list
);
3889 ret
= copy_from_user(exec_list
,
3890 (struct drm_i915_relocation_entry __user
*)
3891 (uintptr_t) args
->buffers_ptr
,
3892 sizeof(*exec_list
) * args
->buffer_count
);
3894 DRM_ERROR("copy %d exec entries failed %d\n",
3895 args
->buffer_count
, ret
);
3896 drm_free_large(exec_list
);
3897 drm_free_large(exec2_list
);
3901 for (i
= 0; i
< args
->buffer_count
; i
++) {
3902 exec2_list
[i
].handle
= exec_list
[i
].handle
;
3903 exec2_list
[i
].relocation_count
= exec_list
[i
].relocation_count
;
3904 exec2_list
[i
].relocs_ptr
= exec_list
[i
].relocs_ptr
;
3905 exec2_list
[i
].alignment
= exec_list
[i
].alignment
;
3906 exec2_list
[i
].offset
= exec_list
[i
].offset
;
3907 if (INTEL_INFO(dev
)->gen
< 4)
3908 exec2_list
[i
].flags
= EXEC_OBJECT_NEEDS_FENCE
;
3910 exec2_list
[i
].flags
= 0;
3913 exec2
.buffers_ptr
= args
->buffers_ptr
;
3914 exec2
.buffer_count
= args
->buffer_count
;
3915 exec2
.batch_start_offset
= args
->batch_start_offset
;
3916 exec2
.batch_len
= args
->batch_len
;
3917 exec2
.DR1
= args
->DR1
;
3918 exec2
.DR4
= args
->DR4
;
3919 exec2
.num_cliprects
= args
->num_cliprects
;
3920 exec2
.cliprects_ptr
= args
->cliprects_ptr
;
3921 exec2
.flags
= I915_EXEC_RENDER
;
3923 ret
= i915_gem_do_execbuffer(dev
, data
, file_priv
, &exec2
, exec2_list
);
3925 /* Copy the new buffer offsets back to the user's exec list. */
3926 for (i
= 0; i
< args
->buffer_count
; i
++)
3927 exec_list
[i
].offset
= exec2_list
[i
].offset
;
3928 /* ... and back out to userspace */
3929 ret
= copy_to_user((struct drm_i915_relocation_entry __user
*)
3930 (uintptr_t) args
->buffers_ptr
,
3932 sizeof(*exec_list
) * args
->buffer_count
);
3935 DRM_ERROR("failed to copy %d exec entries "
3936 "back to user (%d)\n",
3937 args
->buffer_count
, ret
);
3941 drm_free_large(exec_list
);
3942 drm_free_large(exec2_list
);
3947 i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
3948 struct drm_file
*file_priv
)
3950 struct drm_i915_gem_execbuffer2
*args
= data
;
3951 struct drm_i915_gem_exec_object2
*exec2_list
= NULL
;
3955 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3956 (int) args
->buffers_ptr
, args
->buffer_count
, args
->batch_len
);
3959 if (args
->buffer_count
< 1) {
3960 DRM_ERROR("execbuf2 with %d buffers\n", args
->buffer_count
);
3964 exec2_list
= drm_malloc_ab(sizeof(*exec2_list
), args
->buffer_count
);
3965 if (exec2_list
== NULL
) {
3966 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
3967 args
->buffer_count
);
3970 ret
= copy_from_user(exec2_list
,
3971 (struct drm_i915_relocation_entry __user
*)
3972 (uintptr_t) args
->buffers_ptr
,
3973 sizeof(*exec2_list
) * args
->buffer_count
);
3975 DRM_ERROR("copy %d exec entries failed %d\n",
3976 args
->buffer_count
, ret
);
3977 drm_free_large(exec2_list
);
3981 ret
= i915_gem_do_execbuffer(dev
, data
, file_priv
, args
, exec2_list
);
3983 /* Copy the new buffer offsets back to the user's exec list. */
3984 ret
= copy_to_user((struct drm_i915_relocation_entry __user
*)
3985 (uintptr_t) args
->buffers_ptr
,
3987 sizeof(*exec2_list
) * args
->buffer_count
);
3990 DRM_ERROR("failed to copy %d exec entries "
3991 "back to user (%d)\n",
3992 args
->buffer_count
, ret
);
3996 drm_free_large(exec2_list
);
4001 i915_gem_object_pin(struct drm_gem_object
*obj
, uint32_t alignment
)
4003 struct drm_device
*dev
= obj
->dev
;
4004 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
4007 BUG_ON(obj_priv
->pin_count
== DRM_I915_GEM_OBJECT_MAX_PIN_COUNT
);
4009 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
4011 if (obj_priv
->gtt_space
!= NULL
) {
4013 alignment
= i915_gem_get_gtt_alignment(obj
);
4014 if (obj_priv
->gtt_offset
& (alignment
- 1)) {
4015 WARN(obj_priv
->pin_count
,
4016 "bo is already pinned with incorrect alignment:"
4017 " offset=%x, req.alignment=%x\n",
4018 obj_priv
->gtt_offset
, alignment
);
4019 ret
= i915_gem_object_unbind(obj
);
4025 if (obj_priv
->gtt_space
== NULL
) {
4026 ret
= i915_gem_object_bind_to_gtt(obj
, alignment
);
4031 obj_priv
->pin_count
++;
4033 /* If the object is not active and not pending a flush,
4034 * remove it from the inactive list
4036 if (obj_priv
->pin_count
== 1) {
4037 atomic_inc(&dev
->pin_count
);
4038 atomic_add(obj
->size
, &dev
->pin_memory
);
4039 if (!obj_priv
->active
&&
4040 (obj
->write_domain
& I915_GEM_GPU_DOMAINS
) == 0)
4041 list_del_init(&obj_priv
->list
);
4043 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
4049 i915_gem_object_unpin(struct drm_gem_object
*obj
)
4051 struct drm_device
*dev
= obj
->dev
;
4052 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4053 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
4055 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
4056 obj_priv
->pin_count
--;
4057 BUG_ON(obj_priv
->pin_count
< 0);
4058 BUG_ON(obj_priv
->gtt_space
== NULL
);
4060 /* If the object is no longer pinned, and is
4061 * neither active nor being flushed, then stick it on
4064 if (obj_priv
->pin_count
== 0) {
4065 if (!obj_priv
->active
&&
4066 (obj
->write_domain
& I915_GEM_GPU_DOMAINS
) == 0)
4067 list_move_tail(&obj_priv
->list
,
4068 &dev_priv
->mm
.inactive_list
);
4069 atomic_dec(&dev
->pin_count
);
4070 atomic_sub(obj
->size
, &dev
->pin_memory
);
4072 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
4076 i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
4077 struct drm_file
*file_priv
)
4079 struct drm_i915_gem_pin
*args
= data
;
4080 struct drm_gem_object
*obj
;
4081 struct drm_i915_gem_object
*obj_priv
;
4084 mutex_lock(&dev
->struct_mutex
);
4086 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4088 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
4090 mutex_unlock(&dev
->struct_mutex
);
4093 obj_priv
= to_intel_bo(obj
);
4095 if (obj_priv
->madv
!= I915_MADV_WILLNEED
) {
4096 DRM_ERROR("Attempting to pin a purgeable buffer\n");
4097 drm_gem_object_unreference(obj
);
4098 mutex_unlock(&dev
->struct_mutex
);
4102 if (obj_priv
->pin_filp
!= NULL
&& obj_priv
->pin_filp
!= file_priv
) {
4103 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
4105 drm_gem_object_unreference(obj
);
4106 mutex_unlock(&dev
->struct_mutex
);
4110 obj_priv
->user_pin_count
++;
4111 obj_priv
->pin_filp
= file_priv
;
4112 if (obj_priv
->user_pin_count
== 1) {
4113 ret
= i915_gem_object_pin(obj
, args
->alignment
);
4115 drm_gem_object_unreference(obj
);
4116 mutex_unlock(&dev
->struct_mutex
);
4121 /* XXX - flush the CPU caches for pinned objects
4122 * as the X server doesn't manage domains yet
4124 i915_gem_object_flush_cpu_write_domain(obj
);
4125 args
->offset
= obj_priv
->gtt_offset
;
4126 drm_gem_object_unreference(obj
);
4127 mutex_unlock(&dev
->struct_mutex
);
4133 i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
4134 struct drm_file
*file_priv
)
4136 struct drm_i915_gem_pin
*args
= data
;
4137 struct drm_gem_object
*obj
;
4138 struct drm_i915_gem_object
*obj_priv
;
4140 mutex_lock(&dev
->struct_mutex
);
4142 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4144 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
4146 mutex_unlock(&dev
->struct_mutex
);
4150 obj_priv
= to_intel_bo(obj
);
4151 if (obj_priv
->pin_filp
!= file_priv
) {
4152 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4154 drm_gem_object_unreference(obj
);
4155 mutex_unlock(&dev
->struct_mutex
);
4158 obj_priv
->user_pin_count
--;
4159 if (obj_priv
->user_pin_count
== 0) {
4160 obj_priv
->pin_filp
= NULL
;
4161 i915_gem_object_unpin(obj
);
4164 drm_gem_object_unreference(obj
);
4165 mutex_unlock(&dev
->struct_mutex
);
4170 i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
4171 struct drm_file
*file_priv
)
4173 struct drm_i915_gem_busy
*args
= data
;
4174 struct drm_gem_object
*obj
;
4175 struct drm_i915_gem_object
*obj_priv
;
4177 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4179 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
4184 mutex_lock(&dev
->struct_mutex
);
4186 /* Count all active objects as busy, even if they are currently not used
4187 * by the gpu. Users of this interface expect objects to eventually
4188 * become non-busy without any further actions, therefore emit any
4189 * necessary flushes here.
4191 obj_priv
= to_intel_bo(obj
);
4192 args
->busy
= obj_priv
->active
;
4194 /* Unconditionally flush objects, even when the gpu still uses this
4195 * object. Userspace calling this function indicates that it wants to
4196 * use this buffer rather sooner than later, so issuing the required
4197 * flush earlier is beneficial.
4199 if (obj
->write_domain
& I915_GEM_GPU_DOMAINS
) {
4200 i915_gem_flush_ring(dev
,
4202 0, obj
->write_domain
);
4203 (void)i915_add_request(dev
, file_priv
, NULL
, obj_priv
->ring
);
4206 /* Update the active list for the hardware's current position.
4207 * Otherwise this only updates on a delayed timer or when irqs
4208 * are actually unmasked, and our working set ends up being
4209 * larger than required.
4211 i915_gem_retire_requests_ring(dev
, obj_priv
->ring
);
4213 args
->busy
= obj_priv
->active
;
4216 drm_gem_object_unreference(obj
);
4217 mutex_unlock(&dev
->struct_mutex
);
4222 i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
4223 struct drm_file
*file_priv
)
4225 return i915_gem_ring_throttle(dev
, file_priv
);
4229 i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
4230 struct drm_file
*file_priv
)
4232 struct drm_i915_gem_madvise
*args
= data
;
4233 struct drm_gem_object
*obj
;
4234 struct drm_i915_gem_object
*obj_priv
;
4236 switch (args
->madv
) {
4237 case I915_MADV_DONTNEED
:
4238 case I915_MADV_WILLNEED
:
4244 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4246 DRM_ERROR("Bad handle in i915_gem_madvise_ioctl(): %d\n",
4251 mutex_lock(&dev
->struct_mutex
);
4252 obj_priv
= to_intel_bo(obj
);
4254 if (obj_priv
->pin_count
) {
4255 drm_gem_object_unreference(obj
);
4256 mutex_unlock(&dev
->struct_mutex
);
4258 DRM_ERROR("Attempted i915_gem_madvise_ioctl() on a pinned object\n");
4262 if (obj_priv
->madv
!= __I915_MADV_PURGED
)
4263 obj_priv
->madv
= args
->madv
;
4265 /* if the object is no longer bound, discard its backing storage */
4266 if (i915_gem_object_is_purgeable(obj_priv
) &&
4267 obj_priv
->gtt_space
== NULL
)
4268 i915_gem_object_truncate(obj
);
4270 args
->retained
= obj_priv
->madv
!= __I915_MADV_PURGED
;
4272 drm_gem_object_unreference(obj
);
4273 mutex_unlock(&dev
->struct_mutex
);
4278 struct drm_gem_object
* i915_gem_alloc_object(struct drm_device
*dev
,
4281 struct drm_i915_gem_object
*obj
;
4283 obj
= kzalloc(sizeof(*obj
), GFP_KERNEL
);
4287 if (drm_gem_object_init(dev
, &obj
->base
, size
) != 0) {
4292 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
4293 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
4295 obj
->agp_type
= AGP_USER_MEMORY
;
4296 obj
->base
.driver_private
= NULL
;
4297 obj
->fence_reg
= I915_FENCE_REG_NONE
;
4298 INIT_LIST_HEAD(&obj
->list
);
4299 INIT_LIST_HEAD(&obj
->gpu_write_list
);
4300 obj
->madv
= I915_MADV_WILLNEED
;
4302 trace_i915_gem_object_create(&obj
->base
);
4307 int i915_gem_init_object(struct drm_gem_object
*obj
)
4314 static void i915_gem_free_object_tail(struct drm_gem_object
*obj
)
4316 struct drm_device
*dev
= obj
->dev
;
4317 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4318 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
4321 ret
= i915_gem_object_unbind(obj
);
4322 if (ret
== -ERESTARTSYS
) {
4323 list_move(&obj_priv
->list
,
4324 &dev_priv
->mm
.deferred_free_list
);
4328 if (obj_priv
->mmap_offset
)
4329 i915_gem_free_mmap_offset(obj
);
4331 drm_gem_object_release(obj
);
4333 kfree(obj_priv
->page_cpu_valid
);
4334 kfree(obj_priv
->bit_17
);
4338 void i915_gem_free_object(struct drm_gem_object
*obj
)
4340 struct drm_device
*dev
= obj
->dev
;
4341 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
4343 trace_i915_gem_object_destroy(obj
);
4345 while (obj_priv
->pin_count
> 0)
4346 i915_gem_object_unpin(obj
);
4348 if (obj_priv
->phys_obj
)
4349 i915_gem_detach_phys_object(dev
, obj
);
4351 i915_gem_free_object_tail(obj
);
4355 i915_gem_idle(struct drm_device
*dev
)
4357 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4360 mutex_lock(&dev
->struct_mutex
);
4362 if (dev_priv
->mm
.suspended
||
4363 (dev_priv
->render_ring
.gem_object
== NULL
) ||
4365 dev_priv
->bsd_ring
.gem_object
== NULL
)) {
4366 mutex_unlock(&dev
->struct_mutex
);
4370 ret
= i915_gpu_idle(dev
);
4372 mutex_unlock(&dev
->struct_mutex
);
4376 /* Under UMS, be paranoid and evict. */
4377 if (!drm_core_check_feature(dev
, DRIVER_MODESET
)) {
4378 ret
= i915_gem_evict_inactive(dev
);
4380 mutex_unlock(&dev
->struct_mutex
);
4385 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4386 * We need to replace this with a semaphore, or something.
4387 * And not confound mm.suspended!
4389 dev_priv
->mm
.suspended
= 1;
4390 del_timer_sync(&dev_priv
->hangcheck_timer
);
4392 i915_kernel_lost_context(dev
);
4393 i915_gem_cleanup_ringbuffer(dev
);
4395 mutex_unlock(&dev
->struct_mutex
);
4397 /* Cancel the retire work handler, which should be idle now. */
4398 cancel_delayed_work_sync(&dev_priv
->mm
.retire_work
);
4404 * 965+ support PIPE_CONTROL commands, which provide finer grained control
4405 * over cache flushing.
4408 i915_gem_init_pipe_control(struct drm_device
*dev
)
4410 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4411 struct drm_gem_object
*obj
;
4412 struct drm_i915_gem_object
*obj_priv
;
4415 obj
= i915_gem_alloc_object(dev
, 4096);
4417 DRM_ERROR("Failed to allocate seqno page\n");
4421 obj_priv
= to_intel_bo(obj
);
4422 obj_priv
->agp_type
= AGP_USER_CACHED_MEMORY
;
4424 ret
= i915_gem_object_pin(obj
, 4096);
4428 dev_priv
->seqno_gfx_addr
= obj_priv
->gtt_offset
;
4429 dev_priv
->seqno_page
= kmap(obj_priv
->pages
[0]);
4430 if (dev_priv
->seqno_page
== NULL
)
4433 dev_priv
->seqno_obj
= obj
;
4434 memset(dev_priv
->seqno_page
, 0, PAGE_SIZE
);
4439 i915_gem_object_unpin(obj
);
4441 drm_gem_object_unreference(obj
);
4448 i915_gem_cleanup_pipe_control(struct drm_device
*dev
)
4450 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4451 struct drm_gem_object
*obj
;
4452 struct drm_i915_gem_object
*obj_priv
;
4454 obj
= dev_priv
->seqno_obj
;
4455 obj_priv
= to_intel_bo(obj
);
4456 kunmap(obj_priv
->pages
[0]);
4457 i915_gem_object_unpin(obj
);
4458 drm_gem_object_unreference(obj
);
4459 dev_priv
->seqno_obj
= NULL
;
4461 dev_priv
->seqno_page
= NULL
;
4465 i915_gem_init_ringbuffer(struct drm_device
*dev
)
4467 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4470 dev_priv
->render_ring
= render_ring
;
4472 if (!I915_NEED_GFX_HWS(dev
)) {
4473 dev_priv
->render_ring
.status_page
.page_addr
4474 = dev_priv
->status_page_dmah
->vaddr
;
4475 memset(dev_priv
->render_ring
.status_page
.page_addr
,
4479 if (HAS_PIPE_CONTROL(dev
)) {
4480 ret
= i915_gem_init_pipe_control(dev
);
4485 ret
= intel_init_ring_buffer(dev
, &dev_priv
->render_ring
);
4487 goto cleanup_pipe_control
;
4490 dev_priv
->bsd_ring
= bsd_ring
;
4491 ret
= intel_init_ring_buffer(dev
, &dev_priv
->bsd_ring
);
4493 goto cleanup_render_ring
;
4496 dev_priv
->next_seqno
= 1;
4500 cleanup_render_ring
:
4501 intel_cleanup_ring_buffer(dev
, &dev_priv
->render_ring
);
4502 cleanup_pipe_control
:
4503 if (HAS_PIPE_CONTROL(dev
))
4504 i915_gem_cleanup_pipe_control(dev
);
4509 i915_gem_cleanup_ringbuffer(struct drm_device
*dev
)
4511 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4513 intel_cleanup_ring_buffer(dev
, &dev_priv
->render_ring
);
4515 intel_cleanup_ring_buffer(dev
, &dev_priv
->bsd_ring
);
4516 if (HAS_PIPE_CONTROL(dev
))
4517 i915_gem_cleanup_pipe_control(dev
);
4521 i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
4522 struct drm_file
*file_priv
)
4524 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4527 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4530 if (atomic_read(&dev_priv
->mm
.wedged
)) {
4531 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4532 atomic_set(&dev_priv
->mm
.wedged
, 0);
4535 mutex_lock(&dev
->struct_mutex
);
4536 dev_priv
->mm
.suspended
= 0;
4538 ret
= i915_gem_init_ringbuffer(dev
);
4540 mutex_unlock(&dev
->struct_mutex
);
4544 BUG_ON(!list_empty(&dev_priv
->render_ring
.active_list
));
4545 BUG_ON(HAS_BSD(dev
) && !list_empty(&dev_priv
->bsd_ring
.active_list
));
4546 BUG_ON(!list_empty(&dev_priv
->mm
.flushing_list
));
4547 BUG_ON(!list_empty(&dev_priv
->mm
.inactive_list
));
4548 BUG_ON(!list_empty(&dev_priv
->render_ring
.request_list
));
4549 BUG_ON(HAS_BSD(dev
) && !list_empty(&dev_priv
->bsd_ring
.request_list
));
4550 mutex_unlock(&dev
->struct_mutex
);
4552 ret
= drm_irq_install(dev
);
4554 goto cleanup_ringbuffer
;
4559 mutex_lock(&dev
->struct_mutex
);
4560 i915_gem_cleanup_ringbuffer(dev
);
4561 dev_priv
->mm
.suspended
= 1;
4562 mutex_unlock(&dev
->struct_mutex
);
4568 i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
4569 struct drm_file
*file_priv
)
4571 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4574 drm_irq_uninstall(dev
);
4575 return i915_gem_idle(dev
);
4579 i915_gem_lastclose(struct drm_device
*dev
)
4583 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4586 ret
= i915_gem_idle(dev
);
4588 DRM_ERROR("failed to idle hardware: %d\n", ret
);
4592 i915_gem_load(struct drm_device
*dev
)
4595 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4597 INIT_LIST_HEAD(&dev_priv
->mm
.flushing_list
);
4598 INIT_LIST_HEAD(&dev_priv
->mm
.gpu_write_list
);
4599 INIT_LIST_HEAD(&dev_priv
->mm
.inactive_list
);
4600 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
4601 INIT_LIST_HEAD(&dev_priv
->mm
.deferred_free_list
);
4602 INIT_LIST_HEAD(&dev_priv
->render_ring
.active_list
);
4603 INIT_LIST_HEAD(&dev_priv
->render_ring
.request_list
);
4605 INIT_LIST_HEAD(&dev_priv
->bsd_ring
.active_list
);
4606 INIT_LIST_HEAD(&dev_priv
->bsd_ring
.request_list
);
4608 for (i
= 0; i
< 16; i
++)
4609 INIT_LIST_HEAD(&dev_priv
->fence_regs
[i
].lru_list
);
4610 INIT_DELAYED_WORK(&dev_priv
->mm
.retire_work
,
4611 i915_gem_retire_work_handler
);
4612 spin_lock(&shrink_list_lock
);
4613 list_add(&dev_priv
->mm
.shrink_list
, &shrink_list
);
4614 spin_unlock(&shrink_list_lock
);
4616 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4618 u32 tmp
= I915_READ(MI_ARB_STATE
);
4619 if (!(tmp
& MI_ARB_C3_LP_WRITE_ENABLE
)) {
4620 /* arb state is a masked write, so set bit + bit in mask */
4621 tmp
= MI_ARB_C3_LP_WRITE_ENABLE
| (MI_ARB_C3_LP_WRITE_ENABLE
<< MI_ARB_MASK_SHIFT
);
4622 I915_WRITE(MI_ARB_STATE
, tmp
);
4626 /* Old X drivers will take 0-2 for front, back, depth buffers */
4627 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
4628 dev_priv
->fence_reg_start
= 3;
4630 if (INTEL_INFO(dev
)->gen
>= 4 || IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
4631 dev_priv
->num_fence_regs
= 16;
4633 dev_priv
->num_fence_regs
= 8;
4635 /* Initialize fence registers to zero */
4636 switch (INTEL_INFO(dev
)->gen
) {
4638 for (i
= 0; i
< 16; i
++)
4639 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0
+ (i
* 8), 0);
4643 for (i
= 0; i
< 16; i
++)
4644 I915_WRITE64(FENCE_REG_965_0
+ (i
* 8), 0);
4647 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
4648 for (i
= 0; i
< 8; i
++)
4649 I915_WRITE(FENCE_REG_945_8
+ (i
* 4), 0);
4651 for (i
= 0; i
< 8; i
++)
4652 I915_WRITE(FENCE_REG_830_0
+ (i
* 4), 0);
4655 i915_gem_detect_bit_6_swizzle(dev
);
4656 init_waitqueue_head(&dev_priv
->pending_flip_queue
);
4660 * Create a physically contiguous memory object for this object
4661 * e.g. for cursor + overlay regs
4663 static int i915_gem_init_phys_object(struct drm_device
*dev
,
4664 int id
, int size
, int align
)
4666 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4667 struct drm_i915_gem_phys_object
*phys_obj
;
4670 if (dev_priv
->mm
.phys_objs
[id
- 1] || !size
)
4673 phys_obj
= kzalloc(sizeof(struct drm_i915_gem_phys_object
), GFP_KERNEL
);
4679 phys_obj
->handle
= drm_pci_alloc(dev
, size
, align
);
4680 if (!phys_obj
->handle
) {
4685 set_memory_wc((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
4688 dev_priv
->mm
.phys_objs
[id
- 1] = phys_obj
;
4696 static void i915_gem_free_phys_object(struct drm_device
*dev
, int id
)
4698 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4699 struct drm_i915_gem_phys_object
*phys_obj
;
4701 if (!dev_priv
->mm
.phys_objs
[id
- 1])
4704 phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
4705 if (phys_obj
->cur_obj
) {
4706 i915_gem_detach_phys_object(dev
, phys_obj
->cur_obj
);
4710 set_memory_wb((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
4712 drm_pci_free(dev
, phys_obj
->handle
);
4714 dev_priv
->mm
.phys_objs
[id
- 1] = NULL
;
4717 void i915_gem_free_all_phys_object(struct drm_device
*dev
)
4721 for (i
= I915_GEM_PHYS_CURSOR_0
; i
<= I915_MAX_PHYS_OBJECT
; i
++)
4722 i915_gem_free_phys_object(dev
, i
);
4725 void i915_gem_detach_phys_object(struct drm_device
*dev
,
4726 struct drm_gem_object
*obj
)
4728 struct drm_i915_gem_object
*obj_priv
;
4733 obj_priv
= to_intel_bo(obj
);
4734 if (!obj_priv
->phys_obj
)
4737 ret
= i915_gem_object_get_pages(obj
, 0);
4741 page_count
= obj
->size
/ PAGE_SIZE
;
4743 for (i
= 0; i
< page_count
; i
++) {
4744 char *dst
= kmap_atomic(obj_priv
->pages
[i
], KM_USER0
);
4745 char *src
= obj_priv
->phys_obj
->handle
->vaddr
+ (i
* PAGE_SIZE
);
4747 memcpy(dst
, src
, PAGE_SIZE
);
4748 kunmap_atomic(dst
, KM_USER0
);
4750 drm_clflush_pages(obj_priv
->pages
, page_count
);
4751 drm_agp_chipset_flush(dev
);
4753 i915_gem_object_put_pages(obj
);
4755 obj_priv
->phys_obj
->cur_obj
= NULL
;
4756 obj_priv
->phys_obj
= NULL
;
4760 i915_gem_attach_phys_object(struct drm_device
*dev
,
4761 struct drm_gem_object
*obj
,
4765 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4766 struct drm_i915_gem_object
*obj_priv
;
4771 if (id
> I915_MAX_PHYS_OBJECT
)
4774 obj_priv
= to_intel_bo(obj
);
4776 if (obj_priv
->phys_obj
) {
4777 if (obj_priv
->phys_obj
->id
== id
)
4779 i915_gem_detach_phys_object(dev
, obj
);
4782 /* create a new object */
4783 if (!dev_priv
->mm
.phys_objs
[id
- 1]) {
4784 ret
= i915_gem_init_phys_object(dev
, id
,
4787 DRM_ERROR("failed to init phys object %d size: %zu\n", id
, obj
->size
);
4792 /* bind to the object */
4793 obj_priv
->phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
4794 obj_priv
->phys_obj
->cur_obj
= obj
;
4796 ret
= i915_gem_object_get_pages(obj
, 0);
4798 DRM_ERROR("failed to get page list\n");
4802 page_count
= obj
->size
/ PAGE_SIZE
;
4804 for (i
= 0; i
< page_count
; i
++) {
4805 char *src
= kmap_atomic(obj_priv
->pages
[i
], KM_USER0
);
4806 char *dst
= obj_priv
->phys_obj
->handle
->vaddr
+ (i
* PAGE_SIZE
);
4808 memcpy(dst
, src
, PAGE_SIZE
);
4809 kunmap_atomic(src
, KM_USER0
);
4812 i915_gem_object_put_pages(obj
);
4820 i915_gem_phys_pwrite(struct drm_device
*dev
, struct drm_gem_object
*obj
,
4821 struct drm_i915_gem_pwrite
*args
,
4822 struct drm_file
*file_priv
)
4824 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
4827 char __user
*user_data
;
4829 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
4830 obj_addr
= obj_priv
->phys_obj
->handle
->vaddr
+ args
->offset
;
4832 DRM_DEBUG_DRIVER("obj_addr %p, %lld\n", obj_addr
, args
->size
);
4833 ret
= copy_from_user(obj_addr
, user_data
, args
->size
);
4837 drm_agp_chipset_flush(dev
);
4841 void i915_gem_release(struct drm_device
* dev
, struct drm_file
*file_priv
)
4843 struct drm_i915_file_private
*i915_file_priv
= file_priv
->driver_priv
;
4845 /* Clean up our request list when the client is going away, so that
4846 * later retire_requests won't dereference our soon-to-be-gone
4849 mutex_lock(&dev
->struct_mutex
);
4850 while (!list_empty(&i915_file_priv
->mm
.request_list
))
4851 list_del_init(i915_file_priv
->mm
.request_list
.next
);
4852 mutex_unlock(&dev
->struct_mutex
);
4856 i915_gpu_is_active(struct drm_device
*dev
)
4858 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4861 lists_empty
= list_empty(&dev_priv
->mm
.flushing_list
) &&
4862 list_empty(&dev_priv
->render_ring
.active_list
);
4864 lists_empty
&= list_empty(&dev_priv
->bsd_ring
.active_list
);
4866 return !lists_empty
;
4870 i915_gem_shrink(struct shrinker
*shrink
, int nr_to_scan
, gfp_t gfp_mask
)
4872 drm_i915_private_t
*dev_priv
, *next_dev
;
4873 struct drm_i915_gem_object
*obj_priv
, *next_obj
;
4875 int would_deadlock
= 1;
4877 /* "fast-path" to count number of available objects */
4878 if (nr_to_scan
== 0) {
4879 spin_lock(&shrink_list_lock
);
4880 list_for_each_entry(dev_priv
, &shrink_list
, mm
.shrink_list
) {
4881 struct drm_device
*dev
= dev_priv
->dev
;
4883 if (mutex_trylock(&dev
->struct_mutex
)) {
4884 list_for_each_entry(obj_priv
,
4885 &dev_priv
->mm
.inactive_list
,
4888 mutex_unlock(&dev
->struct_mutex
);
4891 spin_unlock(&shrink_list_lock
);
4893 return (cnt
/ 100) * sysctl_vfs_cache_pressure
;
4896 spin_lock(&shrink_list_lock
);
4899 /* first scan for clean buffers */
4900 list_for_each_entry_safe(dev_priv
, next_dev
,
4901 &shrink_list
, mm
.shrink_list
) {
4902 struct drm_device
*dev
= dev_priv
->dev
;
4904 if (! mutex_trylock(&dev
->struct_mutex
))
4907 spin_unlock(&shrink_list_lock
);
4908 i915_gem_retire_requests(dev
);
4910 list_for_each_entry_safe(obj_priv
, next_obj
,
4911 &dev_priv
->mm
.inactive_list
,
4913 if (i915_gem_object_is_purgeable(obj_priv
)) {
4914 i915_gem_object_unbind(&obj_priv
->base
);
4915 if (--nr_to_scan
<= 0)
4920 spin_lock(&shrink_list_lock
);
4921 mutex_unlock(&dev
->struct_mutex
);
4925 if (nr_to_scan
<= 0)
4929 /* second pass, evict/count anything still on the inactive list */
4930 list_for_each_entry_safe(dev_priv
, next_dev
,
4931 &shrink_list
, mm
.shrink_list
) {
4932 struct drm_device
*dev
= dev_priv
->dev
;
4934 if (! mutex_trylock(&dev
->struct_mutex
))
4937 spin_unlock(&shrink_list_lock
);
4939 list_for_each_entry_safe(obj_priv
, next_obj
,
4940 &dev_priv
->mm
.inactive_list
,
4942 if (nr_to_scan
> 0) {
4943 i915_gem_object_unbind(&obj_priv
->base
);
4949 spin_lock(&shrink_list_lock
);
4950 mutex_unlock(&dev
->struct_mutex
);
4959 * We are desperate for pages, so as a last resort, wait
4960 * for the GPU to finish and discard whatever we can.
4961 * This has a dramatic impact to reduce the number of
4962 * OOM-killer events whilst running the GPU aggressively.
4964 list_for_each_entry(dev_priv
, &shrink_list
, mm
.shrink_list
) {
4965 struct drm_device
*dev
= dev_priv
->dev
;
4967 if (!mutex_trylock(&dev
->struct_mutex
))
4970 spin_unlock(&shrink_list_lock
);
4972 if (i915_gpu_is_active(dev
)) {
4977 spin_lock(&shrink_list_lock
);
4978 mutex_unlock(&dev
->struct_mutex
);
4985 spin_unlock(&shrink_list_lock
);
4990 return (cnt
/ 100) * sysctl_vfs_cache_pressure
;
4995 static struct shrinker shrinker
= {
4996 .shrink
= i915_gem_shrink
,
4997 .seeks
= DEFAULT_SEEKS
,
5001 i915_gem_shrinker_init(void)
5003 register_shrinker(&shrinker
);
5007 i915_gem_shrinker_exit(void)
5009 unregister_shrinker(&shrinker
);