2 * Copyright © 2008-2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/drm_vma_manager.h>
30 #include <drm/i915_drm.h>
32 #include "i915_vgpu.h"
33 #include "i915_trace.h"
34 #include "intel_drv.h"
35 #include "intel_mocs.h"
36 #include <linux/shmem_fs.h>
37 #include <linux/slab.h>
38 #include <linux/swap.h>
39 #include <linux/pci.h>
40 #include <linux/dma-buf.h>
42 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
);
43 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
);
45 i915_gem_object_retire__write(struct drm_i915_gem_object
*obj
);
47 i915_gem_object_retire__read(struct drm_i915_gem_object
*obj
, int ring
);
49 static bool cpu_cache_is_coherent(struct drm_device
*dev
,
50 enum i915_cache_level level
)
52 return HAS_LLC(dev
) || level
!= I915_CACHE_NONE
;
55 static bool cpu_write_needs_clflush(struct drm_i915_gem_object
*obj
)
57 if (!cpu_cache_is_coherent(obj
->base
.dev
, obj
->cache_level
))
60 return obj
->pin_display
;
63 /* some bookkeeping */
64 static void i915_gem_info_add_obj(struct drm_i915_private
*dev_priv
,
67 spin_lock(&dev_priv
->mm
.object_stat_lock
);
68 dev_priv
->mm
.object_count
++;
69 dev_priv
->mm
.object_memory
+= size
;
70 spin_unlock(&dev_priv
->mm
.object_stat_lock
);
73 static void i915_gem_info_remove_obj(struct drm_i915_private
*dev_priv
,
76 spin_lock(&dev_priv
->mm
.object_stat_lock
);
77 dev_priv
->mm
.object_count
--;
78 dev_priv
->mm
.object_memory
-= size
;
79 spin_unlock(&dev_priv
->mm
.object_stat_lock
);
83 i915_gem_wait_for_error(struct i915_gpu_error
*error
)
87 if (!i915_reset_in_progress(error
))
91 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
92 * userspace. If it takes that long something really bad is going on and
93 * we should simply try to bail out and fail as gracefully as possible.
95 ret
= wait_event_interruptible_timeout(error
->reset_queue
,
96 !i915_reset_in_progress(error
),
99 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
101 } else if (ret
< 0) {
108 int i915_mutex_lock_interruptible(struct drm_device
*dev
)
110 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
113 ret
= i915_gem_wait_for_error(&dev_priv
->gpu_error
);
117 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
121 WARN_ON(i915_verify_lists(dev
));
126 i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
127 struct drm_file
*file
)
129 struct drm_i915_private
*dev_priv
= to_i915(dev
);
130 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
131 struct drm_i915_gem_get_aperture
*args
= data
;
132 struct i915_vma
*vma
;
136 mutex_lock(&dev
->struct_mutex
);
137 list_for_each_entry(vma
, &ggtt
->base
.active_list
, vm_link
)
139 pinned
+= vma
->node
.size
;
140 list_for_each_entry(vma
, &ggtt
->base
.inactive_list
, vm_link
)
142 pinned
+= vma
->node
.size
;
143 mutex_unlock(&dev
->struct_mutex
);
145 args
->aper_size
= ggtt
->base
.total
;
146 args
->aper_available_size
= args
->aper_size
- pinned
;
152 i915_gem_object_get_pages_phys(struct drm_i915_gem_object
*obj
)
154 struct address_space
*mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
155 char *vaddr
= obj
->phys_handle
->vaddr
;
157 struct scatterlist
*sg
;
160 if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj
)))
163 for (i
= 0; i
< obj
->base
.size
/ PAGE_SIZE
; i
++) {
167 page
= shmem_read_mapping_page(mapping
, i
);
169 return PTR_ERR(page
);
171 src
= kmap_atomic(page
);
172 memcpy(vaddr
, src
, PAGE_SIZE
);
173 drm_clflush_virt_range(vaddr
, PAGE_SIZE
);
180 i915_gem_chipset_flush(to_i915(obj
->base
.dev
));
182 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
186 if (sg_alloc_table(st
, 1, GFP_KERNEL
)) {
193 sg
->length
= obj
->base
.size
;
195 sg_dma_address(sg
) = obj
->phys_handle
->busaddr
;
196 sg_dma_len(sg
) = obj
->base
.size
;
203 i915_gem_object_put_pages_phys(struct drm_i915_gem_object
*obj
)
207 BUG_ON(obj
->madv
== __I915_MADV_PURGED
);
209 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
211 /* In the event of a disaster, abandon all caches and
214 obj
->base
.read_domains
= obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
217 if (obj
->madv
== I915_MADV_DONTNEED
)
221 struct address_space
*mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
222 char *vaddr
= obj
->phys_handle
->vaddr
;
225 for (i
= 0; i
< obj
->base
.size
/ PAGE_SIZE
; i
++) {
229 page
= shmem_read_mapping_page(mapping
, i
);
233 dst
= kmap_atomic(page
);
234 drm_clflush_virt_range(vaddr
, PAGE_SIZE
);
235 memcpy(dst
, vaddr
, PAGE_SIZE
);
238 set_page_dirty(page
);
239 if (obj
->madv
== I915_MADV_WILLNEED
)
240 mark_page_accessed(page
);
247 sg_free_table(obj
->pages
);
252 i915_gem_object_release_phys(struct drm_i915_gem_object
*obj
)
254 drm_pci_free(obj
->base
.dev
, obj
->phys_handle
);
257 static const struct drm_i915_gem_object_ops i915_gem_phys_ops
= {
258 .get_pages
= i915_gem_object_get_pages_phys
,
259 .put_pages
= i915_gem_object_put_pages_phys
,
260 .release
= i915_gem_object_release_phys
,
264 drop_pages(struct drm_i915_gem_object
*obj
)
266 struct i915_vma
*vma
, *next
;
269 drm_gem_object_reference(&obj
->base
);
270 list_for_each_entry_safe(vma
, next
, &obj
->vma_list
, obj_link
)
271 if (i915_vma_unbind(vma
))
274 ret
= i915_gem_object_put_pages(obj
);
275 drm_gem_object_unreference(&obj
->base
);
281 i915_gem_object_attach_phys(struct drm_i915_gem_object
*obj
,
284 drm_dma_handle_t
*phys
;
287 if (obj
->phys_handle
) {
288 if ((unsigned long)obj
->phys_handle
->vaddr
& (align
-1))
294 if (obj
->madv
!= I915_MADV_WILLNEED
)
297 if (obj
->base
.filp
== NULL
)
300 ret
= drop_pages(obj
);
304 /* create a new object */
305 phys
= drm_pci_alloc(obj
->base
.dev
, obj
->base
.size
, align
);
309 obj
->phys_handle
= phys
;
310 obj
->ops
= &i915_gem_phys_ops
;
312 return i915_gem_object_get_pages(obj
);
316 i915_gem_phys_pwrite(struct drm_i915_gem_object
*obj
,
317 struct drm_i915_gem_pwrite
*args
,
318 struct drm_file
*file_priv
)
320 struct drm_device
*dev
= obj
->base
.dev
;
321 void *vaddr
= obj
->phys_handle
->vaddr
+ args
->offset
;
322 char __user
*user_data
= to_user_ptr(args
->data_ptr
);
325 /* We manually control the domain here and pretend that it
326 * remains coherent i.e. in the GTT domain, like shmem_pwrite.
328 ret
= i915_gem_object_wait_rendering(obj
, false);
332 intel_fb_obj_invalidate(obj
, ORIGIN_CPU
);
333 if (__copy_from_user_inatomic_nocache(vaddr
, user_data
, args
->size
)) {
334 unsigned long unwritten
;
336 /* The physical object once assigned is fixed for the lifetime
337 * of the obj, so we can safely drop the lock and continue
340 mutex_unlock(&dev
->struct_mutex
);
341 unwritten
= copy_from_user(vaddr
, user_data
, args
->size
);
342 mutex_lock(&dev
->struct_mutex
);
349 drm_clflush_virt_range(vaddr
, args
->size
);
350 i915_gem_chipset_flush(to_i915(dev
));
353 intel_fb_obj_flush(obj
, false, ORIGIN_CPU
);
357 void *i915_gem_object_alloc(struct drm_device
*dev
)
359 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
360 return kmem_cache_zalloc(dev_priv
->objects
, GFP_KERNEL
);
363 void i915_gem_object_free(struct drm_i915_gem_object
*obj
)
365 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
366 kmem_cache_free(dev_priv
->objects
, obj
);
370 i915_gem_create(struct drm_file
*file
,
371 struct drm_device
*dev
,
375 struct drm_i915_gem_object
*obj
;
379 size
= roundup(size
, PAGE_SIZE
);
383 /* Allocate the new object */
384 obj
= i915_gem_object_create(dev
, size
);
388 ret
= drm_gem_handle_create(file
, &obj
->base
, &handle
);
389 /* drop reference from allocate - handle holds it now */
390 drm_gem_object_unreference_unlocked(&obj
->base
);
399 i915_gem_dumb_create(struct drm_file
*file
,
400 struct drm_device
*dev
,
401 struct drm_mode_create_dumb
*args
)
403 /* have to work out size/pitch and return them */
404 args
->pitch
= ALIGN(args
->width
* DIV_ROUND_UP(args
->bpp
, 8), 64);
405 args
->size
= args
->pitch
* args
->height
;
406 return i915_gem_create(file
, dev
,
407 args
->size
, &args
->handle
);
411 * Creates a new mm object and returns a handle to it.
414 i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
415 struct drm_file
*file
)
417 struct drm_i915_gem_create
*args
= data
;
419 return i915_gem_create(file
, dev
,
420 args
->size
, &args
->handle
);
424 __copy_to_user_swizzled(char __user
*cpu_vaddr
,
425 const char *gpu_vaddr
, int gpu_offset
,
428 int ret
, cpu_offset
= 0;
431 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
432 int this_length
= min(cacheline_end
- gpu_offset
, length
);
433 int swizzled_gpu_offset
= gpu_offset
^ 64;
435 ret
= __copy_to_user(cpu_vaddr
+ cpu_offset
,
436 gpu_vaddr
+ swizzled_gpu_offset
,
441 cpu_offset
+= this_length
;
442 gpu_offset
+= this_length
;
443 length
-= this_length
;
450 __copy_from_user_swizzled(char *gpu_vaddr
, int gpu_offset
,
451 const char __user
*cpu_vaddr
,
454 int ret
, cpu_offset
= 0;
457 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
458 int this_length
= min(cacheline_end
- gpu_offset
, length
);
459 int swizzled_gpu_offset
= gpu_offset
^ 64;
461 ret
= __copy_from_user(gpu_vaddr
+ swizzled_gpu_offset
,
462 cpu_vaddr
+ cpu_offset
,
467 cpu_offset
+= this_length
;
468 gpu_offset
+= this_length
;
469 length
-= this_length
;
476 * Pins the specified object's pages and synchronizes the object with
477 * GPU accesses. Sets needs_clflush to non-zero if the caller should
478 * flush the object from the CPU cache.
480 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object
*obj
,
487 if (WARN_ON((obj
->ops
->flags
& I915_GEM_OBJECT_HAS_STRUCT_PAGE
) == 0))
490 if (!(obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
)) {
491 /* If we're not in the cpu read domain, set ourself into the gtt
492 * read domain and manually flush cachelines (if required). This
493 * optimizes for the case when the gpu will dirty the data
494 * anyway again before the next pread happens. */
495 *needs_clflush
= !cpu_cache_is_coherent(obj
->base
.dev
,
497 ret
= i915_gem_object_wait_rendering(obj
, true);
502 ret
= i915_gem_object_get_pages(obj
);
506 i915_gem_object_pin_pages(obj
);
511 /* Per-page copy function for the shmem pread fastpath.
512 * Flushes invalid cachelines before reading the target if
513 * needs_clflush is set. */
515 shmem_pread_fast(struct page
*page
, int shmem_page_offset
, int page_length
,
516 char __user
*user_data
,
517 bool page_do_bit17_swizzling
, bool needs_clflush
)
522 if (unlikely(page_do_bit17_swizzling
))
525 vaddr
= kmap_atomic(page
);
527 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
529 ret
= __copy_to_user_inatomic(user_data
,
530 vaddr
+ shmem_page_offset
,
532 kunmap_atomic(vaddr
);
534 return ret
? -EFAULT
: 0;
538 shmem_clflush_swizzled_range(char *addr
, unsigned long length
,
541 if (unlikely(swizzled
)) {
542 unsigned long start
= (unsigned long) addr
;
543 unsigned long end
= (unsigned long) addr
+ length
;
545 /* For swizzling simply ensure that we always flush both
546 * channels. Lame, but simple and it works. Swizzled
547 * pwrite/pread is far from a hotpath - current userspace
548 * doesn't use it at all. */
549 start
= round_down(start
, 128);
550 end
= round_up(end
, 128);
552 drm_clflush_virt_range((void *)start
, end
- start
);
554 drm_clflush_virt_range(addr
, length
);
559 /* Only difference to the fast-path function is that this can handle bit17
560 * and uses non-atomic copy and kmap functions. */
562 shmem_pread_slow(struct page
*page
, int shmem_page_offset
, int page_length
,
563 char __user
*user_data
,
564 bool page_do_bit17_swizzling
, bool needs_clflush
)
571 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
573 page_do_bit17_swizzling
);
575 if (page_do_bit17_swizzling
)
576 ret
= __copy_to_user_swizzled(user_data
,
577 vaddr
, shmem_page_offset
,
580 ret
= __copy_to_user(user_data
,
581 vaddr
+ shmem_page_offset
,
585 return ret
? - EFAULT
: 0;
589 i915_gem_shmem_pread(struct drm_device
*dev
,
590 struct drm_i915_gem_object
*obj
,
591 struct drm_i915_gem_pread
*args
,
592 struct drm_file
*file
)
594 char __user
*user_data
;
597 int shmem_page_offset
, page_length
, ret
= 0;
598 int obj_do_bit17_swizzling
, page_do_bit17_swizzling
;
600 int needs_clflush
= 0;
601 struct sg_page_iter sg_iter
;
603 user_data
= to_user_ptr(args
->data_ptr
);
606 obj_do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
608 ret
= i915_gem_obj_prepare_shmem_read(obj
, &needs_clflush
);
612 offset
= args
->offset
;
614 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
,
615 offset
>> PAGE_SHIFT
) {
616 struct page
*page
= sg_page_iter_page(&sg_iter
);
621 /* Operation in this page
623 * shmem_page_offset = offset within page in shmem file
624 * page_length = bytes to copy for this page
626 shmem_page_offset
= offset_in_page(offset
);
627 page_length
= remain
;
628 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
629 page_length
= PAGE_SIZE
- shmem_page_offset
;
631 page_do_bit17_swizzling
= obj_do_bit17_swizzling
&&
632 (page_to_phys(page
) & (1 << 17)) != 0;
634 ret
= shmem_pread_fast(page
, shmem_page_offset
, page_length
,
635 user_data
, page_do_bit17_swizzling
,
640 mutex_unlock(&dev
->struct_mutex
);
642 if (likely(!i915
.prefault_disable
) && !prefaulted
) {
643 ret
= fault_in_multipages_writeable(user_data
, remain
);
644 /* Userspace is tricking us, but we've already clobbered
645 * its pages with the prefault and promised to write the
646 * data up to the first fault. Hence ignore any errors
647 * and just continue. */
652 ret
= shmem_pread_slow(page
, shmem_page_offset
, page_length
,
653 user_data
, page_do_bit17_swizzling
,
656 mutex_lock(&dev
->struct_mutex
);
662 remain
-= page_length
;
663 user_data
+= page_length
;
664 offset
+= page_length
;
668 i915_gem_object_unpin_pages(obj
);
674 * Reads data from the object referenced by handle.
676 * On error, the contents of *data are undefined.
679 i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
680 struct drm_file
*file
)
682 struct drm_i915_gem_pread
*args
= data
;
683 struct drm_i915_gem_object
*obj
;
689 if (!access_ok(VERIFY_WRITE
,
690 to_user_ptr(args
->data_ptr
),
694 ret
= i915_mutex_lock_interruptible(dev
);
698 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
699 if (&obj
->base
== NULL
) {
704 /* Bounds check source. */
705 if (args
->offset
> obj
->base
.size
||
706 args
->size
> obj
->base
.size
- args
->offset
) {
711 /* prime objects have no backing filp to GEM pread/pwrite
714 if (!obj
->base
.filp
) {
719 trace_i915_gem_object_pread(obj
, args
->offset
, args
->size
);
721 ret
= i915_gem_shmem_pread(dev
, obj
, args
, file
);
724 drm_gem_object_unreference(&obj
->base
);
726 mutex_unlock(&dev
->struct_mutex
);
730 /* This is the fast write path which cannot handle
731 * page faults in the source data
735 fast_user_write(struct io_mapping
*mapping
,
736 loff_t page_base
, int page_offset
,
737 char __user
*user_data
,
740 void __iomem
*vaddr_atomic
;
742 unsigned long unwritten
;
744 vaddr_atomic
= io_mapping_map_atomic_wc(mapping
, page_base
);
745 /* We can use the cpu mem copy function because this is X86. */
746 vaddr
= (void __force
*)vaddr_atomic
+ page_offset
;
747 unwritten
= __copy_from_user_inatomic_nocache(vaddr
,
749 io_mapping_unmap_atomic(vaddr_atomic
);
754 * This is the fast pwrite path, where we copy the data directly from the
755 * user into the GTT, uncached.
758 i915_gem_gtt_pwrite_fast(struct drm_device
*dev
,
759 struct drm_i915_gem_object
*obj
,
760 struct drm_i915_gem_pwrite
*args
,
761 struct drm_file
*file
)
763 struct drm_i915_private
*dev_priv
= to_i915(dev
);
764 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
766 loff_t offset
, page_base
;
767 char __user
*user_data
;
768 int page_offset
, page_length
, ret
;
770 ret
= i915_gem_obj_ggtt_pin(obj
, 0, PIN_MAPPABLE
| PIN_NONBLOCK
);
774 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
778 ret
= i915_gem_object_put_fence(obj
);
782 user_data
= to_user_ptr(args
->data_ptr
);
785 offset
= i915_gem_obj_ggtt_offset(obj
) + args
->offset
;
787 intel_fb_obj_invalidate(obj
, ORIGIN_GTT
);
790 /* Operation in this page
792 * page_base = page offset within aperture
793 * page_offset = offset within page
794 * page_length = bytes to copy for this page
796 page_base
= offset
& PAGE_MASK
;
797 page_offset
= offset_in_page(offset
);
798 page_length
= remain
;
799 if ((page_offset
+ remain
) > PAGE_SIZE
)
800 page_length
= PAGE_SIZE
- page_offset
;
802 /* If we get a fault while copying data, then (presumably) our
803 * source page isn't available. Return the error and we'll
804 * retry in the slow path.
806 if (fast_user_write(ggtt
->mappable
, page_base
,
807 page_offset
, user_data
, page_length
)) {
812 remain
-= page_length
;
813 user_data
+= page_length
;
814 offset
+= page_length
;
818 intel_fb_obj_flush(obj
, false, ORIGIN_GTT
);
820 i915_gem_object_ggtt_unpin(obj
);
825 /* Per-page copy function for the shmem pwrite fastpath.
826 * Flushes invalid cachelines before writing to the target if
827 * needs_clflush_before is set and flushes out any written cachelines after
828 * writing if needs_clflush is set. */
830 shmem_pwrite_fast(struct page
*page
, int shmem_page_offset
, int page_length
,
831 char __user
*user_data
,
832 bool page_do_bit17_swizzling
,
833 bool needs_clflush_before
,
834 bool needs_clflush_after
)
839 if (unlikely(page_do_bit17_swizzling
))
842 vaddr
= kmap_atomic(page
);
843 if (needs_clflush_before
)
844 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
846 ret
= __copy_from_user_inatomic(vaddr
+ shmem_page_offset
,
847 user_data
, page_length
);
848 if (needs_clflush_after
)
849 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
851 kunmap_atomic(vaddr
);
853 return ret
? -EFAULT
: 0;
856 /* Only difference to the fast-path function is that this can handle bit17
857 * and uses non-atomic copy and kmap functions. */
859 shmem_pwrite_slow(struct page
*page
, int shmem_page_offset
, int page_length
,
860 char __user
*user_data
,
861 bool page_do_bit17_swizzling
,
862 bool needs_clflush_before
,
863 bool needs_clflush_after
)
869 if (unlikely(needs_clflush_before
|| page_do_bit17_swizzling
))
870 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
872 page_do_bit17_swizzling
);
873 if (page_do_bit17_swizzling
)
874 ret
= __copy_from_user_swizzled(vaddr
, shmem_page_offset
,
878 ret
= __copy_from_user(vaddr
+ shmem_page_offset
,
881 if (needs_clflush_after
)
882 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
884 page_do_bit17_swizzling
);
887 return ret
? -EFAULT
: 0;
891 i915_gem_shmem_pwrite(struct drm_device
*dev
,
892 struct drm_i915_gem_object
*obj
,
893 struct drm_i915_gem_pwrite
*args
,
894 struct drm_file
*file
)
898 char __user
*user_data
;
899 int shmem_page_offset
, page_length
, ret
= 0;
900 int obj_do_bit17_swizzling
, page_do_bit17_swizzling
;
901 int hit_slowpath
= 0;
902 int needs_clflush_after
= 0;
903 int needs_clflush_before
= 0;
904 struct sg_page_iter sg_iter
;
906 user_data
= to_user_ptr(args
->data_ptr
);
909 obj_do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
911 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
912 /* If we're not in the cpu write domain, set ourself into the gtt
913 * write domain and manually flush cachelines (if required). This
914 * optimizes for the case when the gpu will use the data
915 * right away and we therefore have to clflush anyway. */
916 needs_clflush_after
= cpu_write_needs_clflush(obj
);
917 ret
= i915_gem_object_wait_rendering(obj
, false);
921 /* Same trick applies to invalidate partially written cachelines read
923 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) == 0)
924 needs_clflush_before
=
925 !cpu_cache_is_coherent(dev
, obj
->cache_level
);
927 ret
= i915_gem_object_get_pages(obj
);
931 intel_fb_obj_invalidate(obj
, ORIGIN_CPU
);
933 i915_gem_object_pin_pages(obj
);
935 offset
= args
->offset
;
938 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
,
939 offset
>> PAGE_SHIFT
) {
940 struct page
*page
= sg_page_iter_page(&sg_iter
);
941 int partial_cacheline_write
;
946 /* Operation in this page
948 * shmem_page_offset = offset within page in shmem file
949 * page_length = bytes to copy for this page
951 shmem_page_offset
= offset_in_page(offset
);
953 page_length
= remain
;
954 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
955 page_length
= PAGE_SIZE
- shmem_page_offset
;
957 /* If we don't overwrite a cacheline completely we need to be
958 * careful to have up-to-date data by first clflushing. Don't
959 * overcomplicate things and flush the entire patch. */
960 partial_cacheline_write
= needs_clflush_before
&&
961 ((shmem_page_offset
| page_length
)
962 & (boot_cpu_data
.x86_clflush_size
- 1));
964 page_do_bit17_swizzling
= obj_do_bit17_swizzling
&&
965 (page_to_phys(page
) & (1 << 17)) != 0;
967 ret
= shmem_pwrite_fast(page
, shmem_page_offset
, page_length
,
968 user_data
, page_do_bit17_swizzling
,
969 partial_cacheline_write
,
970 needs_clflush_after
);
975 mutex_unlock(&dev
->struct_mutex
);
976 ret
= shmem_pwrite_slow(page
, shmem_page_offset
, page_length
,
977 user_data
, page_do_bit17_swizzling
,
978 partial_cacheline_write
,
979 needs_clflush_after
);
981 mutex_lock(&dev
->struct_mutex
);
987 remain
-= page_length
;
988 user_data
+= page_length
;
989 offset
+= page_length
;
993 i915_gem_object_unpin_pages(obj
);
997 * Fixup: Flush cpu caches in case we didn't flush the dirty
998 * cachelines in-line while writing and the object moved
999 * out of the cpu write domain while we've dropped the lock.
1001 if (!needs_clflush_after
&&
1002 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
1003 if (i915_gem_clflush_object(obj
, obj
->pin_display
))
1004 needs_clflush_after
= true;
1008 if (needs_clflush_after
)
1009 i915_gem_chipset_flush(to_i915(dev
));
1011 obj
->cache_dirty
= true;
1013 intel_fb_obj_flush(obj
, false, ORIGIN_CPU
);
1018 * Writes data to the object referenced by handle.
1020 * On error, the contents of the buffer that were to be modified are undefined.
1023 i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
1024 struct drm_file
*file
)
1026 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1027 struct drm_i915_gem_pwrite
*args
= data
;
1028 struct drm_i915_gem_object
*obj
;
1031 if (args
->size
== 0)
1034 if (!access_ok(VERIFY_READ
,
1035 to_user_ptr(args
->data_ptr
),
1039 if (likely(!i915
.prefault_disable
)) {
1040 ret
= fault_in_multipages_readable(to_user_ptr(args
->data_ptr
),
1046 intel_runtime_pm_get(dev_priv
);
1048 ret
= i915_mutex_lock_interruptible(dev
);
1052 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1053 if (&obj
->base
== NULL
) {
1058 /* Bounds check destination. */
1059 if (args
->offset
> obj
->base
.size
||
1060 args
->size
> obj
->base
.size
- args
->offset
) {
1065 /* prime objects have no backing filp to GEM pread/pwrite
1068 if (!obj
->base
.filp
) {
1073 trace_i915_gem_object_pwrite(obj
, args
->offset
, args
->size
);
1076 /* We can only do the GTT pwrite on untiled buffers, as otherwise
1077 * it would end up going through the fenced access, and we'll get
1078 * different detiling behavior between reading and writing.
1079 * pread/pwrite currently are reading and writing from the CPU
1080 * perspective, requiring manual detiling by the client.
1082 if (obj
->tiling_mode
== I915_TILING_NONE
&&
1083 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
&&
1084 cpu_write_needs_clflush(obj
)) {
1085 ret
= i915_gem_gtt_pwrite_fast(dev
, obj
, args
, file
);
1086 /* Note that the gtt paths might fail with non-page-backed user
1087 * pointers (e.g. gtt mappings when moving data between
1088 * textures). Fallback to the shmem path in that case. */
1091 if (ret
== -EFAULT
|| ret
== -ENOSPC
) {
1092 if (obj
->phys_handle
)
1093 ret
= i915_gem_phys_pwrite(obj
, args
, file
);
1095 ret
= i915_gem_shmem_pwrite(dev
, obj
, args
, file
);
1099 drm_gem_object_unreference(&obj
->base
);
1101 mutex_unlock(&dev
->struct_mutex
);
1103 intel_runtime_pm_put(dev_priv
);
1109 i915_gem_check_wedge(unsigned reset_counter
, bool interruptible
)
1111 if (__i915_terminally_wedged(reset_counter
))
1114 if (__i915_reset_in_progress(reset_counter
)) {
1115 /* Non-interruptible callers can't handle -EAGAIN, hence return
1116 * -EIO unconditionally for these. */
1126 static void fake_irq(unsigned long data
)
1128 wake_up_process((struct task_struct
*)data
);
1131 static bool missed_irq(struct drm_i915_private
*dev_priv
,
1132 struct intel_engine_cs
*engine
)
1134 return test_bit(engine
->id
, &dev_priv
->gpu_error
.missed_irq_rings
);
1137 static unsigned long local_clock_us(unsigned *cpu
)
1141 /* Cheaply and approximately convert from nanoseconds to microseconds.
1142 * The result and subsequent calculations are also defined in the same
1143 * approximate microseconds units. The principal source of timing
1144 * error here is from the simple truncation.
1146 * Note that local_clock() is only defined wrt to the current CPU;
1147 * the comparisons are no longer valid if we switch CPUs. Instead of
1148 * blocking preemption for the entire busywait, we can detect the CPU
1149 * switch and use that as indicator of system load and a reason to
1150 * stop busywaiting, see busywait_stop().
1153 t
= local_clock() >> 10;
1159 static bool busywait_stop(unsigned long timeout
, unsigned cpu
)
1163 if (time_after(local_clock_us(&this_cpu
), timeout
))
1166 return this_cpu
!= cpu
;
1169 static int __i915_spin_request(struct drm_i915_gem_request
*req
, int state
)
1171 unsigned long timeout
;
1174 /* When waiting for high frequency requests, e.g. during synchronous
1175 * rendering split between the CPU and GPU, the finite amount of time
1176 * required to set up the irq and wait upon it limits the response
1177 * rate. By busywaiting on the request completion for a short while we
1178 * can service the high frequency waits as quick as possible. However,
1179 * if it is a slow request, we want to sleep as quickly as possible.
1180 * The tradeoff between waiting and sleeping is roughly the time it
1181 * takes to sleep on a request, on the order of a microsecond.
1184 if (req
->engine
->irq_refcount
)
1187 /* Only spin if we know the GPU is processing this request */
1188 if (!i915_gem_request_started(req
, true))
1191 timeout
= local_clock_us(&cpu
) + 5;
1192 while (!need_resched()) {
1193 if (i915_gem_request_completed(req
, true))
1196 if (signal_pending_state(state
, current
))
1199 if (busywait_stop(timeout
, cpu
))
1202 cpu_relax_lowlatency();
1205 if (i915_gem_request_completed(req
, false))
1212 * __i915_wait_request - wait until execution of request has finished
1214 * @interruptible: do an interruptible wait (normally yes)
1215 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
1217 * Note: It is of utmost importance that the passed in seqno and reset_counter
1218 * values have been read by the caller in an smp safe manner. Where read-side
1219 * locks are involved, it is sufficient to read the reset_counter before
1220 * unlocking the lock that protects the seqno. For lockless tricks, the
1221 * reset_counter _must_ be read before, and an appropriate smp_rmb must be
1224 * Returns 0 if the request was found within the alloted time. Else returns the
1225 * errno with remaining time filled in timeout argument.
1227 int __i915_wait_request(struct drm_i915_gem_request
*req
,
1230 struct intel_rps_client
*rps
)
1232 struct intel_engine_cs
*engine
= i915_gem_request_get_engine(req
);
1233 struct drm_i915_private
*dev_priv
= req
->i915
;
1234 const bool irq_test_in_progress
=
1235 ACCESS_ONCE(dev_priv
->gpu_error
.test_irq_rings
) & intel_engine_flag(engine
);
1236 int state
= interruptible
? TASK_INTERRUPTIBLE
: TASK_UNINTERRUPTIBLE
;
1238 unsigned long timeout_expire
;
1239 s64 before
= 0; /* Only to silence a compiler warning. */
1242 WARN(!intel_irqs_enabled(dev_priv
), "IRQs disabled");
1244 if (list_empty(&req
->list
))
1247 if (i915_gem_request_completed(req
, true))
1252 if (WARN_ON(*timeout
< 0))
1258 timeout_expire
= jiffies
+ nsecs_to_jiffies_timeout(*timeout
);
1261 * Record current time in case interrupted by signal, or wedged.
1263 before
= ktime_get_raw_ns();
1266 if (INTEL_INFO(dev_priv
)->gen
>= 6)
1267 gen6_rps_boost(dev_priv
, rps
, req
->emitted_jiffies
);
1269 trace_i915_gem_request_wait_begin(req
);
1271 /* Optimistic spin for the next jiffie before touching IRQs */
1272 ret
= __i915_spin_request(req
, state
);
1276 if (!irq_test_in_progress
&& WARN_ON(!engine
->irq_get(engine
))) {
1282 struct timer_list timer
;
1284 prepare_to_wait(&engine
->irq_queue
, &wait
, state
);
1286 /* We need to check whether any gpu reset happened in between
1287 * the request being submitted and now. If a reset has occurred,
1288 * the request is effectively complete (we either are in the
1289 * process of or have discarded the rendering and completely
1290 * reset the GPU. The results of the request are lost and we
1291 * are free to continue on with the original operation.
1293 if (req
->reset_counter
!= i915_reset_counter(&dev_priv
->gpu_error
)) {
1298 if (i915_gem_request_completed(req
, false)) {
1303 if (signal_pending_state(state
, current
)) {
1308 if (timeout
&& time_after_eq(jiffies
, timeout_expire
)) {
1313 timer
.function
= NULL
;
1314 if (timeout
|| missed_irq(dev_priv
, engine
)) {
1315 unsigned long expire
;
1317 setup_timer_on_stack(&timer
, fake_irq
, (unsigned long)current
);
1318 expire
= missed_irq(dev_priv
, engine
) ? jiffies
+ 1 : timeout_expire
;
1319 mod_timer(&timer
, expire
);
1324 if (timer
.function
) {
1325 del_singleshot_timer_sync(&timer
);
1326 destroy_timer_on_stack(&timer
);
1329 if (!irq_test_in_progress
)
1330 engine
->irq_put(engine
);
1332 finish_wait(&engine
->irq_queue
, &wait
);
1335 trace_i915_gem_request_wait_end(req
);
1338 s64 tres
= *timeout
- (ktime_get_raw_ns() - before
);
1340 *timeout
= tres
< 0 ? 0 : tres
;
1343 * Apparently ktime isn't accurate enough and occasionally has a
1344 * bit of mismatch in the jiffies<->nsecs<->ktime loop. So patch
1345 * things up to make the test happy. We allow up to 1 jiffy.
1347 * This is a regrssion from the timespec->ktime conversion.
1349 if (ret
== -ETIME
&& *timeout
< jiffies_to_usecs(1)*1000)
1356 int i915_gem_request_add_to_client(struct drm_i915_gem_request
*req
,
1357 struct drm_file
*file
)
1359 struct drm_i915_file_private
*file_priv
;
1361 WARN_ON(!req
|| !file
|| req
->file_priv
);
1369 file_priv
= file
->driver_priv
;
1371 spin_lock(&file_priv
->mm
.lock
);
1372 req
->file_priv
= file_priv
;
1373 list_add_tail(&req
->client_list
, &file_priv
->mm
.request_list
);
1374 spin_unlock(&file_priv
->mm
.lock
);
1376 req
->pid
= get_pid(task_pid(current
));
1382 i915_gem_request_remove_from_client(struct drm_i915_gem_request
*request
)
1384 struct drm_i915_file_private
*file_priv
= request
->file_priv
;
1389 spin_lock(&file_priv
->mm
.lock
);
1390 list_del(&request
->client_list
);
1391 request
->file_priv
= NULL
;
1392 spin_unlock(&file_priv
->mm
.lock
);
1394 put_pid(request
->pid
);
1395 request
->pid
= NULL
;
1398 static void i915_gem_request_retire(struct drm_i915_gem_request
*request
)
1400 trace_i915_gem_request_retire(request
);
1402 /* We know the GPU must have read the request to have
1403 * sent us the seqno + interrupt, so use the position
1404 * of tail of the request to update the last known position
1407 * Note this requires that we are always called in request
1410 request
->ringbuf
->last_retired_head
= request
->postfix
;
1412 list_del_init(&request
->list
);
1413 i915_gem_request_remove_from_client(request
);
1415 if (request
->previous_context
) {
1416 if (i915
.enable_execlists
)
1417 intel_lr_context_unpin(request
->previous_context
,
1421 i915_gem_context_unreference(request
->ctx
);
1422 i915_gem_request_unreference(request
);
1426 __i915_gem_request_retire__upto(struct drm_i915_gem_request
*req
)
1428 struct intel_engine_cs
*engine
= req
->engine
;
1429 struct drm_i915_gem_request
*tmp
;
1431 lockdep_assert_held(&engine
->i915
->dev
->struct_mutex
);
1433 if (list_empty(&req
->list
))
1437 tmp
= list_first_entry(&engine
->request_list
,
1438 typeof(*tmp
), list
);
1440 i915_gem_request_retire(tmp
);
1441 } while (tmp
!= req
);
1443 WARN_ON(i915_verify_lists(engine
->dev
));
1447 * Waits for a request to be signaled, and cleans up the
1448 * request and object lists appropriately for that event.
1451 i915_wait_request(struct drm_i915_gem_request
*req
)
1453 struct drm_i915_private
*dev_priv
= req
->i915
;
1457 interruptible
= dev_priv
->mm
.interruptible
;
1459 BUG_ON(!mutex_is_locked(&dev_priv
->dev
->struct_mutex
));
1461 ret
= __i915_wait_request(req
, interruptible
, NULL
, NULL
);
1465 __i915_gem_request_retire__upto(req
);
1470 * Ensures that all rendering to the object has completed and the object is
1471 * safe to unbind from the GTT or access from the CPU.
1474 i915_gem_object_wait_rendering(struct drm_i915_gem_object
*obj
,
1483 if (obj
->last_write_req
!= NULL
) {
1484 ret
= i915_wait_request(obj
->last_write_req
);
1488 i
= obj
->last_write_req
->engine
->id
;
1489 if (obj
->last_read_req
[i
] == obj
->last_write_req
)
1490 i915_gem_object_retire__read(obj
, i
);
1492 i915_gem_object_retire__write(obj
);
1495 for (i
= 0; i
< I915_NUM_ENGINES
; i
++) {
1496 if (obj
->last_read_req
[i
] == NULL
)
1499 ret
= i915_wait_request(obj
->last_read_req
[i
]);
1503 i915_gem_object_retire__read(obj
, i
);
1505 GEM_BUG_ON(obj
->active
);
1512 i915_gem_object_retire_request(struct drm_i915_gem_object
*obj
,
1513 struct drm_i915_gem_request
*req
)
1515 int ring
= req
->engine
->id
;
1517 if (obj
->last_read_req
[ring
] == req
)
1518 i915_gem_object_retire__read(obj
, ring
);
1519 else if (obj
->last_write_req
== req
)
1520 i915_gem_object_retire__write(obj
);
1522 __i915_gem_request_retire__upto(req
);
1525 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1526 * as the object state may change during this call.
1528 static __must_check
int
1529 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object
*obj
,
1530 struct intel_rps_client
*rps
,
1533 struct drm_device
*dev
= obj
->base
.dev
;
1534 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1535 struct drm_i915_gem_request
*requests
[I915_NUM_ENGINES
];
1538 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
1539 BUG_ON(!dev_priv
->mm
.interruptible
);
1545 struct drm_i915_gem_request
*req
;
1547 req
= obj
->last_write_req
;
1551 requests
[n
++] = i915_gem_request_reference(req
);
1553 for (i
= 0; i
< I915_NUM_ENGINES
; i
++) {
1554 struct drm_i915_gem_request
*req
;
1556 req
= obj
->last_read_req
[i
];
1560 requests
[n
++] = i915_gem_request_reference(req
);
1564 mutex_unlock(&dev
->struct_mutex
);
1566 for (i
= 0; ret
== 0 && i
< n
; i
++)
1567 ret
= __i915_wait_request(requests
[i
], true, NULL
, rps
);
1568 mutex_lock(&dev
->struct_mutex
);
1570 for (i
= 0; i
< n
; i
++) {
1572 i915_gem_object_retire_request(obj
, requests
[i
]);
1573 i915_gem_request_unreference(requests
[i
]);
1579 static struct intel_rps_client
*to_rps_client(struct drm_file
*file
)
1581 struct drm_i915_file_private
*fpriv
= file
->driver_priv
;
1586 * Called when user space prepares to use an object with the CPU, either
1587 * through the mmap ioctl's mapping or a GTT mapping.
1590 i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
1591 struct drm_file
*file
)
1593 struct drm_i915_gem_set_domain
*args
= data
;
1594 struct drm_i915_gem_object
*obj
;
1595 uint32_t read_domains
= args
->read_domains
;
1596 uint32_t write_domain
= args
->write_domain
;
1599 /* Only handle setting domains to types used by the CPU. */
1600 if (write_domain
& I915_GEM_GPU_DOMAINS
)
1603 if (read_domains
& I915_GEM_GPU_DOMAINS
)
1606 /* Having something in the write domain implies it's in the read
1607 * domain, and only that read domain. Enforce that in the request.
1609 if (write_domain
!= 0 && read_domains
!= write_domain
)
1612 ret
= i915_mutex_lock_interruptible(dev
);
1616 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1617 if (&obj
->base
== NULL
) {
1622 /* Try to flush the object off the GPU without holding the lock.
1623 * We will repeat the flush holding the lock in the normal manner
1624 * to catch cases where we are gazumped.
1626 ret
= i915_gem_object_wait_rendering__nonblocking(obj
,
1627 to_rps_client(file
),
1632 if (read_domains
& I915_GEM_DOMAIN_GTT
)
1633 ret
= i915_gem_object_set_to_gtt_domain(obj
, write_domain
!= 0);
1635 ret
= i915_gem_object_set_to_cpu_domain(obj
, write_domain
!= 0);
1637 if (write_domain
!= 0)
1638 intel_fb_obj_invalidate(obj
,
1639 write_domain
== I915_GEM_DOMAIN_GTT
?
1640 ORIGIN_GTT
: ORIGIN_CPU
);
1643 drm_gem_object_unreference(&obj
->base
);
1645 mutex_unlock(&dev
->struct_mutex
);
1650 * Called when user space has done writes to this buffer
1653 i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1654 struct drm_file
*file
)
1656 struct drm_i915_gem_sw_finish
*args
= data
;
1657 struct drm_i915_gem_object
*obj
;
1660 ret
= i915_mutex_lock_interruptible(dev
);
1664 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1665 if (&obj
->base
== NULL
) {
1670 /* Pinned buffers may be scanout, so flush the cache */
1671 if (obj
->pin_display
)
1672 i915_gem_object_flush_cpu_write_domain(obj
);
1674 drm_gem_object_unreference(&obj
->base
);
1676 mutex_unlock(&dev
->struct_mutex
);
1681 * Maps the contents of an object, returning the address it is mapped
1684 * While the mapping holds a reference on the contents of the object, it doesn't
1685 * imply a ref on the object itself.
1689 * DRM driver writers who look a this function as an example for how to do GEM
1690 * mmap support, please don't implement mmap support like here. The modern way
1691 * to implement DRM mmap support is with an mmap offset ioctl (like
1692 * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly.
1693 * That way debug tooling like valgrind will understand what's going on, hiding
1694 * the mmap call in a driver private ioctl will break that. The i915 driver only
1695 * does cpu mmaps this way because we didn't know better.
1698 i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1699 struct drm_file
*file
)
1701 struct drm_i915_gem_mmap
*args
= data
;
1702 struct drm_gem_object
*obj
;
1705 if (args
->flags
& ~(I915_MMAP_WC
))
1708 if (args
->flags
& I915_MMAP_WC
&& !cpu_has_pat
)
1711 obj
= drm_gem_object_lookup(dev
, file
, args
->handle
);
1715 /* prime objects have no backing filp to GEM mmap
1719 drm_gem_object_unreference_unlocked(obj
);
1723 addr
= vm_mmap(obj
->filp
, 0, args
->size
,
1724 PROT_READ
| PROT_WRITE
, MAP_SHARED
,
1726 if (args
->flags
& I915_MMAP_WC
) {
1727 struct mm_struct
*mm
= current
->mm
;
1728 struct vm_area_struct
*vma
;
1730 down_write(&mm
->mmap_sem
);
1731 vma
= find_vma(mm
, addr
);
1734 pgprot_writecombine(vm_get_page_prot(vma
->vm_flags
));
1737 up_write(&mm
->mmap_sem
);
1739 drm_gem_object_unreference_unlocked(obj
);
1740 if (IS_ERR((void *)addr
))
1743 args
->addr_ptr
= (uint64_t) addr
;
1749 * i915_gem_fault - fault a page into the GTT
1750 * @vma: VMA in question
1753 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1754 * from userspace. The fault handler takes care of binding the object to
1755 * the GTT (if needed), allocating and programming a fence register (again,
1756 * only if needed based on whether the old reg is still valid or the object
1757 * is tiled) and inserting a new PTE into the faulting process.
1759 * Note that the faulting process may involve evicting existing objects
1760 * from the GTT and/or fence registers to make room. So performance may
1761 * suffer if the GTT working set is large or there are few fence registers
1764 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
)
1766 struct drm_i915_gem_object
*obj
= to_intel_bo(vma
->vm_private_data
);
1767 struct drm_device
*dev
= obj
->base
.dev
;
1768 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1769 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
1770 struct i915_ggtt_view view
= i915_ggtt_view_normal
;
1771 pgoff_t page_offset
;
1774 bool write
= !!(vmf
->flags
& FAULT_FLAG_WRITE
);
1776 intel_runtime_pm_get(dev_priv
);
1778 /* We don't use vmf->pgoff since that has the fake offset */
1779 page_offset
= ((unsigned long)vmf
->virtual_address
- vma
->vm_start
) >>
1782 ret
= i915_mutex_lock_interruptible(dev
);
1786 trace_i915_gem_object_fault(obj
, page_offset
, true, write
);
1788 /* Try to flush the object off the GPU first without holding the lock.
1789 * Upon reacquiring the lock, we will perform our sanity checks and then
1790 * repeat the flush holding the lock in the normal manner to catch cases
1791 * where we are gazumped.
1793 ret
= i915_gem_object_wait_rendering__nonblocking(obj
, NULL
, !write
);
1797 /* Access to snoopable pages through the GTT is incoherent. */
1798 if (obj
->cache_level
!= I915_CACHE_NONE
&& !HAS_LLC(dev
)) {
1803 /* Use a partial view if the object is bigger than the aperture. */
1804 if (obj
->base
.size
>= ggtt
->mappable_end
&&
1805 obj
->tiling_mode
== I915_TILING_NONE
) {
1806 static const unsigned int chunk_size
= 256; // 1 MiB
1808 memset(&view
, 0, sizeof(view
));
1809 view
.type
= I915_GGTT_VIEW_PARTIAL
;
1810 view
.params
.partial
.offset
= rounddown(page_offset
, chunk_size
);
1811 view
.params
.partial
.size
=
1814 (vma
->vm_end
- vma
->vm_start
)/PAGE_SIZE
-
1815 view
.params
.partial
.offset
);
1818 /* Now pin it into the GTT if needed */
1819 ret
= i915_gem_object_ggtt_pin(obj
, &view
, 0, PIN_MAPPABLE
);
1823 ret
= i915_gem_object_set_to_gtt_domain(obj
, write
);
1827 ret
= i915_gem_object_get_fence(obj
);
1831 /* Finally, remap it using the new GTT offset */
1832 pfn
= ggtt
->mappable_base
+
1833 i915_gem_obj_ggtt_offset_view(obj
, &view
);
1836 if (unlikely(view
.type
== I915_GGTT_VIEW_PARTIAL
)) {
1837 /* Overriding existing pages in partial view does not cause
1838 * us any trouble as TLBs are still valid because the fault
1839 * is due to userspace losing part of the mapping or never
1840 * having accessed it before (at this partials' range).
1842 unsigned long base
= vma
->vm_start
+
1843 (view
.params
.partial
.offset
<< PAGE_SHIFT
);
1846 for (i
= 0; i
< view
.params
.partial
.size
; i
++) {
1847 ret
= vm_insert_pfn(vma
, base
+ i
* PAGE_SIZE
, pfn
+ i
);
1852 obj
->fault_mappable
= true;
1854 if (!obj
->fault_mappable
) {
1855 unsigned long size
= min_t(unsigned long,
1856 vma
->vm_end
- vma
->vm_start
,
1860 for (i
= 0; i
< size
>> PAGE_SHIFT
; i
++) {
1861 ret
= vm_insert_pfn(vma
,
1862 (unsigned long)vma
->vm_start
+ i
* PAGE_SIZE
,
1868 obj
->fault_mappable
= true;
1870 ret
= vm_insert_pfn(vma
,
1871 (unsigned long)vmf
->virtual_address
,
1875 i915_gem_object_ggtt_unpin_view(obj
, &view
);
1877 mutex_unlock(&dev
->struct_mutex
);
1882 * We eat errors when the gpu is terminally wedged to avoid
1883 * userspace unduly crashing (gl has no provisions for mmaps to
1884 * fail). But any other -EIO isn't ours (e.g. swap in failure)
1885 * and so needs to be reported.
1887 if (!i915_terminally_wedged(&dev_priv
->gpu_error
)) {
1888 ret
= VM_FAULT_SIGBUS
;
1893 * EAGAIN means the gpu is hung and we'll wait for the error
1894 * handler to reset everything when re-faulting in
1895 * i915_mutex_lock_interruptible.
1902 * EBUSY is ok: this just means that another thread
1903 * already did the job.
1905 ret
= VM_FAULT_NOPAGE
;
1912 ret
= VM_FAULT_SIGBUS
;
1915 WARN_ONCE(ret
, "unhandled error in i915_gem_fault: %i\n", ret
);
1916 ret
= VM_FAULT_SIGBUS
;
1920 intel_runtime_pm_put(dev_priv
);
1925 * i915_gem_release_mmap - remove physical page mappings
1926 * @obj: obj in question
1928 * Preserve the reservation of the mmapping with the DRM core code, but
1929 * relinquish ownership of the pages back to the system.
1931 * It is vital that we remove the page mapping if we have mapped a tiled
1932 * object through the GTT and then lose the fence register due to
1933 * resource pressure. Similarly if the object has been moved out of the
1934 * aperture, than pages mapped into userspace must be revoked. Removing the
1935 * mapping will then trigger a page fault on the next user access, allowing
1936 * fixup by i915_gem_fault().
1939 i915_gem_release_mmap(struct drm_i915_gem_object
*obj
)
1941 /* Serialisation between user GTT access and our code depends upon
1942 * revoking the CPU's PTE whilst the mutex is held. The next user
1943 * pagefault then has to wait until we release the mutex.
1945 lockdep_assert_held(&obj
->base
.dev
->struct_mutex
);
1947 if (!obj
->fault_mappable
)
1950 drm_vma_node_unmap(&obj
->base
.vma_node
,
1951 obj
->base
.dev
->anon_inode
->i_mapping
);
1953 /* Ensure that the CPU's PTE are revoked and there are not outstanding
1954 * memory transactions from userspace before we return. The TLB
1955 * flushing implied above by changing the PTE above *should* be
1956 * sufficient, an extra barrier here just provides us with a bit
1957 * of paranoid documentation about our requirement to serialise
1958 * memory writes before touching registers / GSM.
1962 obj
->fault_mappable
= false;
1966 i915_gem_release_all_mmaps(struct drm_i915_private
*dev_priv
)
1968 struct drm_i915_gem_object
*obj
;
1970 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
)
1971 i915_gem_release_mmap(obj
);
1975 i915_gem_get_gtt_size(struct drm_device
*dev
, uint32_t size
, int tiling_mode
)
1979 if (INTEL_INFO(dev
)->gen
>= 4 ||
1980 tiling_mode
== I915_TILING_NONE
)
1983 /* Previous chips need a power-of-two fence region when tiling */
1984 if (INTEL_INFO(dev
)->gen
== 3)
1985 gtt_size
= 1024*1024;
1987 gtt_size
= 512*1024;
1989 while (gtt_size
< size
)
1996 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1997 * @obj: object to check
1999 * Return the required GTT alignment for an object, taking into account
2000 * potential fence register mapping.
2003 i915_gem_get_gtt_alignment(struct drm_device
*dev
, uint32_t size
,
2004 int tiling_mode
, bool fenced
)
2007 * Minimum alignment is 4k (GTT page size), but might be greater
2008 * if a fence register is needed for the object.
2010 if (INTEL_INFO(dev
)->gen
>= 4 || (!fenced
&& IS_G33(dev
)) ||
2011 tiling_mode
== I915_TILING_NONE
)
2015 * Previous chips need to be aligned to the size of the smallest
2016 * fence register that can contain the object.
2018 return i915_gem_get_gtt_size(dev
, size
, tiling_mode
);
2021 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object
*obj
)
2023 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2026 if (drm_vma_node_has_offset(&obj
->base
.vma_node
))
2029 dev_priv
->mm
.shrinker_no_lock_stealing
= true;
2031 ret
= drm_gem_create_mmap_offset(&obj
->base
);
2035 /* Badly fragmented mmap space? The only way we can recover
2036 * space is by destroying unwanted objects. We can't randomly release
2037 * mmap_offsets as userspace expects them to be persistent for the
2038 * lifetime of the objects. The closest we can is to release the
2039 * offsets on purgeable objects by truncating it and marking it purged,
2040 * which prevents userspace from ever using that object again.
2042 i915_gem_shrink(dev_priv
,
2043 obj
->base
.size
>> PAGE_SHIFT
,
2045 I915_SHRINK_UNBOUND
|
2046 I915_SHRINK_PURGEABLE
);
2047 ret
= drm_gem_create_mmap_offset(&obj
->base
);
2051 i915_gem_shrink_all(dev_priv
);
2052 ret
= drm_gem_create_mmap_offset(&obj
->base
);
2054 dev_priv
->mm
.shrinker_no_lock_stealing
= false;
2059 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object
*obj
)
2061 drm_gem_free_mmap_offset(&obj
->base
);
2065 i915_gem_mmap_gtt(struct drm_file
*file
,
2066 struct drm_device
*dev
,
2070 struct drm_i915_gem_object
*obj
;
2073 ret
= i915_mutex_lock_interruptible(dev
);
2077 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, handle
));
2078 if (&obj
->base
== NULL
) {
2083 if (obj
->madv
!= I915_MADV_WILLNEED
) {
2084 DRM_DEBUG("Attempting to mmap a purgeable buffer\n");
2089 ret
= i915_gem_object_create_mmap_offset(obj
);
2093 *offset
= drm_vma_node_offset_addr(&obj
->base
.vma_node
);
2096 drm_gem_object_unreference(&obj
->base
);
2098 mutex_unlock(&dev
->struct_mutex
);
2103 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
2105 * @data: GTT mapping ioctl data
2106 * @file: GEM object info
2108 * Simply returns the fake offset to userspace so it can mmap it.
2109 * The mmap call will end up in drm_gem_mmap(), which will set things
2110 * up so we can get faults in the handler above.
2112 * The fault handler will take care of binding the object into the GTT
2113 * (since it may have been evicted to make room for something), allocating
2114 * a fence register, and mapping the appropriate aperture address into
2118 i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
2119 struct drm_file
*file
)
2121 struct drm_i915_gem_mmap_gtt
*args
= data
;
2123 return i915_gem_mmap_gtt(file
, dev
, args
->handle
, &args
->offset
);
2126 /* Immediately discard the backing storage */
2128 i915_gem_object_truncate(struct drm_i915_gem_object
*obj
)
2130 i915_gem_object_free_mmap_offset(obj
);
2132 if (obj
->base
.filp
== NULL
)
2135 /* Our goal here is to return as much of the memory as
2136 * is possible back to the system as we are called from OOM.
2137 * To do this we must instruct the shmfs to drop all of its
2138 * backing pages, *now*.
2140 shmem_truncate_range(file_inode(obj
->base
.filp
), 0, (loff_t
)-1);
2141 obj
->madv
= __I915_MADV_PURGED
;
2144 /* Try to discard unwanted pages */
2146 i915_gem_object_invalidate(struct drm_i915_gem_object
*obj
)
2148 struct address_space
*mapping
;
2150 switch (obj
->madv
) {
2151 case I915_MADV_DONTNEED
:
2152 i915_gem_object_truncate(obj
);
2153 case __I915_MADV_PURGED
:
2157 if (obj
->base
.filp
== NULL
)
2160 mapping
= file_inode(obj
->base
.filp
)->i_mapping
,
2161 invalidate_mapping_pages(mapping
, 0, (loff_t
)-1);
2165 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object
*obj
)
2167 struct sg_page_iter sg_iter
;
2170 BUG_ON(obj
->madv
== __I915_MADV_PURGED
);
2172 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
2174 /* In the event of a disaster, abandon all caches and
2175 * hope for the best.
2177 i915_gem_clflush_object(obj
, true);
2178 obj
->base
.read_domains
= obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
2181 i915_gem_gtt_finish_object(obj
);
2183 if (i915_gem_object_needs_bit17_swizzle(obj
))
2184 i915_gem_object_save_bit_17_swizzle(obj
);
2186 if (obj
->madv
== I915_MADV_DONTNEED
)
2189 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
, 0) {
2190 struct page
*page
= sg_page_iter_page(&sg_iter
);
2193 set_page_dirty(page
);
2195 if (obj
->madv
== I915_MADV_WILLNEED
)
2196 mark_page_accessed(page
);
2202 sg_free_table(obj
->pages
);
2207 i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
)
2209 const struct drm_i915_gem_object_ops
*ops
= obj
->ops
;
2211 if (obj
->pages
== NULL
)
2214 if (obj
->pages_pin_count
)
2217 BUG_ON(i915_gem_obj_bound_any(obj
));
2219 /* ->put_pages might need to allocate memory for the bit17 swizzle
2220 * array, hence protect them from being reaped by removing them from gtt
2222 list_del(&obj
->global_list
);
2225 if (is_vmalloc_addr(obj
->mapping
))
2226 vunmap(obj
->mapping
);
2228 kunmap(kmap_to_page(obj
->mapping
));
2229 obj
->mapping
= NULL
;
2232 ops
->put_pages(obj
);
2235 i915_gem_object_invalidate(obj
);
2241 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object
*obj
)
2243 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2245 struct address_space
*mapping
;
2246 struct sg_table
*st
;
2247 struct scatterlist
*sg
;
2248 struct sg_page_iter sg_iter
;
2250 unsigned long last_pfn
= 0; /* suppress gcc warning */
2254 /* Assert that the object is not currently in any GPU domain. As it
2255 * wasn't in the GTT, there shouldn't be any way it could have been in
2258 BUG_ON(obj
->base
.read_domains
& I915_GEM_GPU_DOMAINS
);
2259 BUG_ON(obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
);
2261 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
2265 page_count
= obj
->base
.size
/ PAGE_SIZE
;
2266 if (sg_alloc_table(st
, page_count
, GFP_KERNEL
)) {
2271 /* Get the list of pages out of our struct file. They'll be pinned
2272 * at this point until we release them.
2274 * Fail silently without starting the shrinker
2276 mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
2277 gfp
= mapping_gfp_constraint(mapping
, ~(__GFP_IO
| __GFP_RECLAIM
));
2278 gfp
|= __GFP_NORETRY
| __GFP_NOWARN
;
2281 for (i
= 0; i
< page_count
; i
++) {
2282 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
2284 i915_gem_shrink(dev_priv
,
2287 I915_SHRINK_UNBOUND
|
2288 I915_SHRINK_PURGEABLE
);
2289 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
2292 /* We've tried hard to allocate the memory by reaping
2293 * our own buffer, now let the real VM do its job and
2294 * go down in flames if truly OOM.
2296 i915_gem_shrink_all(dev_priv
);
2297 page
= shmem_read_mapping_page(mapping
, i
);
2299 ret
= PTR_ERR(page
);
2303 #ifdef CONFIG_SWIOTLB
2304 if (swiotlb_nr_tbl()) {
2306 sg_set_page(sg
, page
, PAGE_SIZE
, 0);
2311 if (!i
|| page_to_pfn(page
) != last_pfn
+ 1) {
2315 sg_set_page(sg
, page
, PAGE_SIZE
, 0);
2317 sg
->length
+= PAGE_SIZE
;
2319 last_pfn
= page_to_pfn(page
);
2321 /* Check that the i965g/gm workaround works. */
2322 WARN_ON((gfp
& __GFP_DMA32
) && (last_pfn
>= 0x00100000UL
));
2324 #ifdef CONFIG_SWIOTLB
2325 if (!swiotlb_nr_tbl())
2330 ret
= i915_gem_gtt_prepare_object(obj
);
2334 if (i915_gem_object_needs_bit17_swizzle(obj
))
2335 i915_gem_object_do_bit_17_swizzle(obj
);
2337 if (obj
->tiling_mode
!= I915_TILING_NONE
&&
2338 dev_priv
->quirks
& QUIRK_PIN_SWIZZLED_PAGES
)
2339 i915_gem_object_pin_pages(obj
);
2345 for_each_sg_page(st
->sgl
, &sg_iter
, st
->nents
, 0)
2346 put_page(sg_page_iter_page(&sg_iter
));
2350 /* shmemfs first checks if there is enough memory to allocate the page
2351 * and reports ENOSPC should there be insufficient, along with the usual
2352 * ENOMEM for a genuine allocation failure.
2354 * We use ENOSPC in our driver to mean that we have run out of aperture
2355 * space and so want to translate the error from shmemfs back to our
2356 * usual understanding of ENOMEM.
2364 /* Ensure that the associated pages are gathered from the backing storage
2365 * and pinned into our object. i915_gem_object_get_pages() may be called
2366 * multiple times before they are released by a single call to
2367 * i915_gem_object_put_pages() - once the pages are no longer referenced
2368 * either as a result of memory pressure (reaping pages under the shrinker)
2369 * or as the object is itself released.
2372 i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
)
2374 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2375 const struct drm_i915_gem_object_ops
*ops
= obj
->ops
;
2381 if (obj
->madv
!= I915_MADV_WILLNEED
) {
2382 DRM_DEBUG("Attempting to obtain a purgeable object\n");
2386 BUG_ON(obj
->pages_pin_count
);
2388 ret
= ops
->get_pages(obj
);
2392 list_add_tail(&obj
->global_list
, &dev_priv
->mm
.unbound_list
);
2394 obj
->get_page
.sg
= obj
->pages
->sgl
;
2395 obj
->get_page
.last
= 0;
2400 void *i915_gem_object_pin_map(struct drm_i915_gem_object
*obj
)
2404 lockdep_assert_held(&obj
->base
.dev
->struct_mutex
);
2406 ret
= i915_gem_object_get_pages(obj
);
2408 return ERR_PTR(ret
);
2410 i915_gem_object_pin_pages(obj
);
2412 if (obj
->mapping
== NULL
) {
2413 struct page
**pages
;
2416 if (obj
->base
.size
== PAGE_SIZE
)
2417 obj
->mapping
= kmap(sg_page(obj
->pages
->sgl
));
2419 pages
= drm_malloc_gfp(obj
->base
.size
>> PAGE_SHIFT
,
2422 if (pages
!= NULL
) {
2423 struct sg_page_iter sg_iter
;
2427 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
,
2428 obj
->pages
->nents
, 0)
2429 pages
[n
++] = sg_page_iter_page(&sg_iter
);
2431 obj
->mapping
= vmap(pages
, n
, 0, PAGE_KERNEL
);
2432 drm_free_large(pages
);
2434 if (obj
->mapping
== NULL
) {
2435 i915_gem_object_unpin_pages(obj
);
2436 return ERR_PTR(-ENOMEM
);
2440 return obj
->mapping
;
2443 void i915_vma_move_to_active(struct i915_vma
*vma
,
2444 struct drm_i915_gem_request
*req
)
2446 struct drm_i915_gem_object
*obj
= vma
->obj
;
2447 struct intel_engine_cs
*engine
;
2449 engine
= i915_gem_request_get_engine(req
);
2451 /* Add a reference if we're newly entering the active list. */
2452 if (obj
->active
== 0)
2453 drm_gem_object_reference(&obj
->base
);
2454 obj
->active
|= intel_engine_flag(engine
);
2456 list_move_tail(&obj
->engine_list
[engine
->id
], &engine
->active_list
);
2457 i915_gem_request_assign(&obj
->last_read_req
[engine
->id
], req
);
2459 list_move_tail(&vma
->vm_link
, &vma
->vm
->active_list
);
2463 i915_gem_object_retire__write(struct drm_i915_gem_object
*obj
)
2465 GEM_BUG_ON(obj
->last_write_req
== NULL
);
2466 GEM_BUG_ON(!(obj
->active
& intel_engine_flag(obj
->last_write_req
->engine
)));
2468 i915_gem_request_assign(&obj
->last_write_req
, NULL
);
2469 intel_fb_obj_flush(obj
, true, ORIGIN_CS
);
2473 i915_gem_object_retire__read(struct drm_i915_gem_object
*obj
, int ring
)
2475 struct i915_vma
*vma
;
2477 GEM_BUG_ON(obj
->last_read_req
[ring
] == NULL
);
2478 GEM_BUG_ON(!(obj
->active
& (1 << ring
)));
2480 list_del_init(&obj
->engine_list
[ring
]);
2481 i915_gem_request_assign(&obj
->last_read_req
[ring
], NULL
);
2483 if (obj
->last_write_req
&& obj
->last_write_req
->engine
->id
== ring
)
2484 i915_gem_object_retire__write(obj
);
2486 obj
->active
&= ~(1 << ring
);
2490 /* Bump our place on the bound list to keep it roughly in LRU order
2491 * so that we don't steal from recently used but inactive objects
2492 * (unless we are forced to ofc!)
2494 list_move_tail(&obj
->global_list
,
2495 &to_i915(obj
->base
.dev
)->mm
.bound_list
);
2497 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
) {
2498 if (!list_empty(&vma
->vm_link
))
2499 list_move_tail(&vma
->vm_link
, &vma
->vm
->inactive_list
);
2502 i915_gem_request_assign(&obj
->last_fenced_req
, NULL
);
2503 drm_gem_object_unreference(&obj
->base
);
2507 i915_gem_init_seqno(struct drm_i915_private
*dev_priv
, u32 seqno
)
2509 struct intel_engine_cs
*engine
;
2512 /* Carefully retire all requests without writing to the rings */
2513 for_each_engine(engine
, dev_priv
) {
2514 ret
= intel_engine_idle(engine
);
2518 i915_gem_retire_requests(dev_priv
);
2520 /* Finally reset hw state */
2521 for_each_engine(engine
, dev_priv
)
2522 intel_ring_init_seqno(engine
, seqno
);
2527 int i915_gem_set_seqno(struct drm_device
*dev
, u32 seqno
)
2529 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2535 /* HWS page needs to be set less than what we
2536 * will inject to ring
2538 ret
= i915_gem_init_seqno(dev_priv
, seqno
- 1);
2542 /* Carefully set the last_seqno value so that wrap
2543 * detection still works
2545 dev_priv
->next_seqno
= seqno
;
2546 dev_priv
->last_seqno
= seqno
- 1;
2547 if (dev_priv
->last_seqno
== 0)
2548 dev_priv
->last_seqno
--;
2554 i915_gem_get_seqno(struct drm_i915_private
*dev_priv
, u32
*seqno
)
2556 /* reserve 0 for non-seqno */
2557 if (dev_priv
->next_seqno
== 0) {
2558 int ret
= i915_gem_init_seqno(dev_priv
, 0);
2562 dev_priv
->next_seqno
= 1;
2565 *seqno
= dev_priv
->last_seqno
= dev_priv
->next_seqno
++;
2570 * NB: This function is not allowed to fail. Doing so would mean the the
2571 * request is not being tracked for completion but the work itself is
2572 * going to happen on the hardware. This would be a Bad Thing(tm).
2574 void __i915_add_request(struct drm_i915_gem_request
*request
,
2575 struct drm_i915_gem_object
*obj
,
2578 struct intel_engine_cs
*engine
;
2579 struct drm_i915_private
*dev_priv
;
2580 struct intel_ringbuffer
*ringbuf
;
2585 if (WARN_ON(request
== NULL
))
2588 engine
= request
->engine
;
2589 dev_priv
= request
->i915
;
2590 ringbuf
= request
->ringbuf
;
2593 * To ensure that this call will not fail, space for its emissions
2594 * should already have been reserved in the ring buffer. Let the ring
2595 * know that it is time to use that space up.
2597 request_start
= intel_ring_get_tail(ringbuf
);
2598 reserved_tail
= request
->reserved_space
;
2599 request
->reserved_space
= 0;
2602 * Emit any outstanding flushes - execbuf can fail to emit the flush
2603 * after having emitted the batchbuffer command. Hence we need to fix
2604 * things up similar to emitting the lazy request. The difference here
2605 * is that the flush _must_ happen before the next request, no matter
2609 if (i915
.enable_execlists
)
2610 ret
= logical_ring_flush_all_caches(request
);
2612 ret
= intel_ring_flush_all_caches(request
);
2613 /* Not allowed to fail! */
2614 WARN(ret
, "*_ring_flush_all_caches failed: %d!\n", ret
);
2617 trace_i915_gem_request_add(request
);
2619 request
->head
= request_start
;
2621 /* Whilst this request exists, batch_obj will be on the
2622 * active_list, and so will hold the active reference. Only when this
2623 * request is retired will the the batch_obj be moved onto the
2624 * inactive_list and lose its active reference. Hence we do not need
2625 * to explicitly hold another reference here.
2627 request
->batch_obj
= obj
;
2629 /* Seal the request and mark it as pending execution. Note that
2630 * we may inspect this state, without holding any locks, during
2631 * hangcheck. Hence we apply the barrier to ensure that we do not
2632 * see a more recent value in the hws than we are tracking.
2634 request
->emitted_jiffies
= jiffies
;
2635 request
->previous_seqno
= engine
->last_submitted_seqno
;
2636 smp_store_mb(engine
->last_submitted_seqno
, request
->seqno
);
2637 list_add_tail(&request
->list
, &engine
->request_list
);
2639 /* Record the position of the start of the request so that
2640 * should we detect the updated seqno part-way through the
2641 * GPU processing the request, we never over-estimate the
2642 * position of the head.
2644 request
->postfix
= intel_ring_get_tail(ringbuf
);
2646 if (i915
.enable_execlists
)
2647 ret
= engine
->emit_request(request
);
2649 ret
= engine
->add_request(request
);
2651 request
->tail
= intel_ring_get_tail(ringbuf
);
2653 /* Not allowed to fail! */
2654 WARN(ret
, "emit|add_request failed: %d!\n", ret
);
2656 i915_queue_hangcheck(engine
->i915
);
2658 queue_delayed_work(dev_priv
->wq
,
2659 &dev_priv
->mm
.retire_work
,
2660 round_jiffies_up_relative(HZ
));
2661 intel_mark_busy(dev_priv
);
2663 /* Sanity check that the reserved size was large enough. */
2664 ret
= intel_ring_get_tail(ringbuf
) - request_start
;
2666 ret
+= ringbuf
->size
;
2667 WARN_ONCE(ret
> reserved_tail
,
2668 "Not enough space reserved (%d bytes) "
2669 "for adding the request (%d bytes)\n",
2670 reserved_tail
, ret
);
2673 static bool i915_context_is_banned(struct drm_i915_private
*dev_priv
,
2674 const struct intel_context
*ctx
)
2676 unsigned long elapsed
;
2678 elapsed
= get_seconds() - ctx
->hang_stats
.guilty_ts
;
2680 if (ctx
->hang_stats
.banned
)
2683 if (ctx
->hang_stats
.ban_period_seconds
&&
2684 elapsed
<= ctx
->hang_stats
.ban_period_seconds
) {
2685 if (!i915_gem_context_is_default(ctx
)) {
2686 DRM_DEBUG("context hanging too fast, banning!\n");
2688 } else if (i915_stop_ring_allow_ban(dev_priv
)) {
2689 if (i915_stop_ring_allow_warn(dev_priv
))
2690 DRM_ERROR("gpu hanging too fast, banning!\n");
2698 static void i915_set_reset_status(struct drm_i915_private
*dev_priv
,
2699 struct intel_context
*ctx
,
2702 struct i915_ctx_hang_stats
*hs
;
2707 hs
= &ctx
->hang_stats
;
2710 hs
->banned
= i915_context_is_banned(dev_priv
, ctx
);
2712 hs
->guilty_ts
= get_seconds();
2714 hs
->batch_pending
++;
2718 void i915_gem_request_free(struct kref
*req_ref
)
2720 struct drm_i915_gem_request
*req
= container_of(req_ref
,
2722 kmem_cache_free(req
->i915
->requests
, req
);
2726 __i915_gem_request_alloc(struct intel_engine_cs
*engine
,
2727 struct intel_context
*ctx
,
2728 struct drm_i915_gem_request
**req_out
)
2730 struct drm_i915_private
*dev_priv
= engine
->i915
;
2731 unsigned reset_counter
= i915_reset_counter(&dev_priv
->gpu_error
);
2732 struct drm_i915_gem_request
*req
;
2740 /* ABI: Before userspace accesses the GPU (e.g. execbuffer), report
2741 * EIO if the GPU is already wedged, or EAGAIN to drop the struct_mutex
2744 ret
= i915_gem_check_wedge(reset_counter
, dev_priv
->mm
.interruptible
);
2748 req
= kmem_cache_zalloc(dev_priv
->requests
, GFP_KERNEL
);
2752 ret
= i915_gem_get_seqno(engine
->i915
, &req
->seqno
);
2756 kref_init(&req
->ref
);
2757 req
->i915
= dev_priv
;
2758 req
->engine
= engine
;
2759 req
->reset_counter
= reset_counter
;
2761 i915_gem_context_reference(req
->ctx
);
2764 * Reserve space in the ring buffer for all the commands required to
2765 * eventually emit this request. This is to guarantee that the
2766 * i915_add_request() call can't fail. Note that the reserve may need
2767 * to be redone if the request is not actually submitted straight
2768 * away, e.g. because a GPU scheduler has deferred it.
2770 req
->reserved_space
= MIN_SPACE_FOR_ADD_REQUEST
;
2772 if (i915
.enable_execlists
)
2773 ret
= intel_logical_ring_alloc_request_extras(req
);
2775 ret
= intel_ring_alloc_request_extras(req
);
2783 i915_gem_context_unreference(ctx
);
2785 kmem_cache_free(dev_priv
->requests
, req
);
2790 * i915_gem_request_alloc - allocate a request structure
2792 * @engine: engine that we wish to issue the request on.
2793 * @ctx: context that the request will be associated with.
2794 * This can be NULL if the request is not directly related to
2795 * any specific user context, in which case this function will
2796 * choose an appropriate context to use.
2798 * Returns a pointer to the allocated request if successful,
2799 * or an error code if not.
2801 struct drm_i915_gem_request
*
2802 i915_gem_request_alloc(struct intel_engine_cs
*engine
,
2803 struct intel_context
*ctx
)
2805 struct drm_i915_gem_request
*req
;
2809 ctx
= engine
->i915
->kernel_context
;
2810 err
= __i915_gem_request_alloc(engine
, ctx
, &req
);
2811 return err
? ERR_PTR(err
) : req
;
2814 struct drm_i915_gem_request
*
2815 i915_gem_find_active_request(struct intel_engine_cs
*engine
)
2817 struct drm_i915_gem_request
*request
;
2819 list_for_each_entry(request
, &engine
->request_list
, list
) {
2820 if (i915_gem_request_completed(request
, false))
2829 static void i915_gem_reset_engine_status(struct drm_i915_private
*dev_priv
,
2830 struct intel_engine_cs
*engine
)
2832 struct drm_i915_gem_request
*request
;
2835 request
= i915_gem_find_active_request(engine
);
2837 if (request
== NULL
)
2840 ring_hung
= engine
->hangcheck
.score
>= HANGCHECK_SCORE_RING_HUNG
;
2842 i915_set_reset_status(dev_priv
, request
->ctx
, ring_hung
);
2844 list_for_each_entry_continue(request
, &engine
->request_list
, list
)
2845 i915_set_reset_status(dev_priv
, request
->ctx
, false);
2848 static void i915_gem_reset_engine_cleanup(struct drm_i915_private
*dev_priv
,
2849 struct intel_engine_cs
*engine
)
2851 struct intel_ringbuffer
*buffer
;
2853 while (!list_empty(&engine
->active_list
)) {
2854 struct drm_i915_gem_object
*obj
;
2856 obj
= list_first_entry(&engine
->active_list
,
2857 struct drm_i915_gem_object
,
2858 engine_list
[engine
->id
]);
2860 i915_gem_object_retire__read(obj
, engine
->id
);
2864 * Clear the execlists queue up before freeing the requests, as those
2865 * are the ones that keep the context and ringbuffer backing objects
2869 if (i915
.enable_execlists
) {
2870 /* Ensure irq handler finishes or is cancelled. */
2871 tasklet_kill(&engine
->irq_tasklet
);
2873 intel_execlists_cancel_requests(engine
);
2877 * We must free the requests after all the corresponding objects have
2878 * been moved off active lists. Which is the same order as the normal
2879 * retire_requests function does. This is important if object hold
2880 * implicit references on things like e.g. ppgtt address spaces through
2883 while (!list_empty(&engine
->request_list
)) {
2884 struct drm_i915_gem_request
*request
;
2886 request
= list_first_entry(&engine
->request_list
,
2887 struct drm_i915_gem_request
,
2890 i915_gem_request_retire(request
);
2893 /* Having flushed all requests from all queues, we know that all
2894 * ringbuffers must now be empty. However, since we do not reclaim
2895 * all space when retiring the request (to prevent HEADs colliding
2896 * with rapid ringbuffer wraparound) the amount of available space
2897 * upon reset is less than when we start. Do one more pass over
2898 * all the ringbuffers to reset last_retired_head.
2900 list_for_each_entry(buffer
, &engine
->buffers
, link
) {
2901 buffer
->last_retired_head
= buffer
->tail
;
2902 intel_ring_update_space(buffer
);
2905 intel_ring_init_seqno(engine
, engine
->last_submitted_seqno
);
2908 void i915_gem_reset(struct drm_device
*dev
)
2910 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2911 struct intel_engine_cs
*engine
;
2914 * Before we free the objects from the requests, we need to inspect
2915 * them for finding the guilty party. As the requests only borrow
2916 * their reference to the objects, the inspection must be done first.
2918 for_each_engine(engine
, dev_priv
)
2919 i915_gem_reset_engine_status(dev_priv
, engine
);
2921 for_each_engine(engine
, dev_priv
)
2922 i915_gem_reset_engine_cleanup(dev_priv
, engine
);
2924 i915_gem_context_reset(dev
);
2926 i915_gem_restore_fences(dev
);
2928 WARN_ON(i915_verify_lists(dev
));
2932 * This function clears the request list as sequence numbers are passed.
2935 i915_gem_retire_requests_ring(struct intel_engine_cs
*engine
)
2937 WARN_ON(i915_verify_lists(engine
->dev
));
2939 /* Retire requests first as we use it above for the early return.
2940 * If we retire requests last, we may use a later seqno and so clear
2941 * the requests lists without clearing the active list, leading to
2944 while (!list_empty(&engine
->request_list
)) {
2945 struct drm_i915_gem_request
*request
;
2947 request
= list_first_entry(&engine
->request_list
,
2948 struct drm_i915_gem_request
,
2951 if (!i915_gem_request_completed(request
, true))
2954 i915_gem_request_retire(request
);
2957 /* Move any buffers on the active list that are no longer referenced
2958 * by the ringbuffer to the flushing/inactive lists as appropriate,
2959 * before we free the context associated with the requests.
2961 while (!list_empty(&engine
->active_list
)) {
2962 struct drm_i915_gem_object
*obj
;
2964 obj
= list_first_entry(&engine
->active_list
,
2965 struct drm_i915_gem_object
,
2966 engine_list
[engine
->id
]);
2968 if (!list_empty(&obj
->last_read_req
[engine
->id
]->list
))
2971 i915_gem_object_retire__read(obj
, engine
->id
);
2974 if (unlikely(engine
->trace_irq_req
&&
2975 i915_gem_request_completed(engine
->trace_irq_req
, true))) {
2976 engine
->irq_put(engine
);
2977 i915_gem_request_assign(&engine
->trace_irq_req
, NULL
);
2980 WARN_ON(i915_verify_lists(engine
->dev
));
2984 i915_gem_retire_requests(struct drm_i915_private
*dev_priv
)
2986 struct intel_engine_cs
*engine
;
2989 for_each_engine(engine
, dev_priv
) {
2990 i915_gem_retire_requests_ring(engine
);
2991 idle
&= list_empty(&engine
->request_list
);
2992 if (i915
.enable_execlists
) {
2993 spin_lock_bh(&engine
->execlist_lock
);
2994 idle
&= list_empty(&engine
->execlist_queue
);
2995 spin_unlock_bh(&engine
->execlist_lock
);
3000 mod_delayed_work(dev_priv
->wq
,
3001 &dev_priv
->mm
.idle_work
,
3002 msecs_to_jiffies(100));
3008 i915_gem_retire_work_handler(struct work_struct
*work
)
3010 struct drm_i915_private
*dev_priv
=
3011 container_of(work
, typeof(*dev_priv
), mm
.retire_work
.work
);
3012 struct drm_device
*dev
= dev_priv
->dev
;
3015 /* Come back later if the device is busy... */
3017 if (mutex_trylock(&dev
->struct_mutex
)) {
3018 idle
= i915_gem_retire_requests(dev_priv
);
3019 mutex_unlock(&dev
->struct_mutex
);
3022 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
,
3023 round_jiffies_up_relative(HZ
));
3027 i915_gem_idle_work_handler(struct work_struct
*work
)
3029 struct drm_i915_private
*dev_priv
=
3030 container_of(work
, typeof(*dev_priv
), mm
.idle_work
.work
);
3031 struct drm_device
*dev
= dev_priv
->dev
;
3032 struct intel_engine_cs
*engine
;
3034 for_each_engine(engine
, dev_priv
)
3035 if (!list_empty(&engine
->request_list
))
3038 /* we probably should sync with hangcheck here, using cancel_work_sync.
3039 * Also locking seems to be fubar here, engine->request_list is protected
3040 * by dev->struct_mutex. */
3042 intel_mark_idle(dev_priv
);
3044 if (mutex_trylock(&dev
->struct_mutex
)) {
3045 for_each_engine(engine
, dev_priv
)
3046 i915_gem_batch_pool_fini(&engine
->batch_pool
);
3048 mutex_unlock(&dev
->struct_mutex
);
3053 * Ensures that an object will eventually get non-busy by flushing any required
3054 * write domains, emitting any outstanding lazy request and retiring and
3055 * completed requests.
3058 i915_gem_object_flush_active(struct drm_i915_gem_object
*obj
)
3065 for (i
= 0; i
< I915_NUM_ENGINES
; i
++) {
3066 struct drm_i915_gem_request
*req
;
3068 req
= obj
->last_read_req
[i
];
3072 if (list_empty(&req
->list
))
3075 if (i915_gem_request_completed(req
, true)) {
3076 __i915_gem_request_retire__upto(req
);
3078 i915_gem_object_retire__read(obj
, i
);
3086 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
3087 * @DRM_IOCTL_ARGS: standard ioctl arguments
3089 * Returns 0 if successful, else an error is returned with the remaining time in
3090 * the timeout parameter.
3091 * -ETIME: object is still busy after timeout
3092 * -ERESTARTSYS: signal interrupted the wait
3093 * -ENONENT: object doesn't exist
3094 * Also possible, but rare:
3095 * -EAGAIN: GPU wedged
3097 * -ENODEV: Internal IRQ fail
3098 * -E?: The add request failed
3100 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
3101 * non-zero timeout parameter the wait ioctl will wait for the given number of
3102 * nanoseconds on an object becoming unbusy. Since the wait itself does so
3103 * without holding struct_mutex the object may become re-busied before this
3104 * function completes. A similar but shorter * race condition exists in the busy
3108 i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
, struct drm_file
*file
)
3110 struct drm_i915_gem_wait
*args
= data
;
3111 struct drm_i915_gem_object
*obj
;
3112 struct drm_i915_gem_request
*req
[I915_NUM_ENGINES
];
3116 if (args
->flags
!= 0)
3119 ret
= i915_mutex_lock_interruptible(dev
);
3123 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->bo_handle
));
3124 if (&obj
->base
== NULL
) {
3125 mutex_unlock(&dev
->struct_mutex
);
3129 /* Need to make sure the object gets inactive eventually. */
3130 ret
= i915_gem_object_flush_active(obj
);
3137 /* Do this after OLR check to make sure we make forward progress polling
3138 * on this IOCTL with a timeout == 0 (like busy ioctl)
3140 if (args
->timeout_ns
== 0) {
3145 drm_gem_object_unreference(&obj
->base
);
3147 for (i
= 0; i
< I915_NUM_ENGINES
; i
++) {
3148 if (obj
->last_read_req
[i
] == NULL
)
3151 req
[n
++] = i915_gem_request_reference(obj
->last_read_req
[i
]);
3154 mutex_unlock(&dev
->struct_mutex
);
3156 for (i
= 0; i
< n
; i
++) {
3158 ret
= __i915_wait_request(req
[i
], true,
3159 args
->timeout_ns
> 0 ? &args
->timeout_ns
: NULL
,
3160 to_rps_client(file
));
3161 i915_gem_request_unreference(req
[i
]);
3166 drm_gem_object_unreference(&obj
->base
);
3167 mutex_unlock(&dev
->struct_mutex
);
3172 __i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
3173 struct intel_engine_cs
*to
,
3174 struct drm_i915_gem_request
*from_req
,
3175 struct drm_i915_gem_request
**to_req
)
3177 struct intel_engine_cs
*from
;
3180 from
= i915_gem_request_get_engine(from_req
);
3184 if (i915_gem_request_completed(from_req
, true))
3187 if (!i915_semaphore_is_enabled(to_i915(obj
->base
.dev
))) {
3188 struct drm_i915_private
*i915
= to_i915(obj
->base
.dev
);
3189 ret
= __i915_wait_request(from_req
,
3190 i915
->mm
.interruptible
,
3192 &i915
->rps
.semaphores
);
3196 i915_gem_object_retire_request(obj
, from_req
);
3198 int idx
= intel_ring_sync_index(from
, to
);
3199 u32 seqno
= i915_gem_request_get_seqno(from_req
);
3203 if (seqno
<= from
->semaphore
.sync_seqno
[idx
])
3206 if (*to_req
== NULL
) {
3207 struct drm_i915_gem_request
*req
;
3209 req
= i915_gem_request_alloc(to
, NULL
);
3211 return PTR_ERR(req
);
3216 trace_i915_gem_ring_sync_to(*to_req
, from
, from_req
);
3217 ret
= to
->semaphore
.sync_to(*to_req
, from
, seqno
);
3221 /* We use last_read_req because sync_to()
3222 * might have just caused seqno wrap under
3225 from
->semaphore
.sync_seqno
[idx
] =
3226 i915_gem_request_get_seqno(obj
->last_read_req
[from
->id
]);
3233 * i915_gem_object_sync - sync an object to a ring.
3235 * @obj: object which may be in use on another ring.
3236 * @to: ring we wish to use the object on. May be NULL.
3237 * @to_req: request we wish to use the object for. See below.
3238 * This will be allocated and returned if a request is
3239 * required but not passed in.
3241 * This code is meant to abstract object synchronization with the GPU.
3242 * Calling with NULL implies synchronizing the object with the CPU
3243 * rather than a particular GPU ring. Conceptually we serialise writes
3244 * between engines inside the GPU. We only allow one engine to write
3245 * into a buffer at any time, but multiple readers. To ensure each has
3246 * a coherent view of memory, we must:
3248 * - If there is an outstanding write request to the object, the new
3249 * request must wait for it to complete (either CPU or in hw, requests
3250 * on the same ring will be naturally ordered).
3252 * - If we are a write request (pending_write_domain is set), the new
3253 * request must wait for outstanding read requests to complete.
3255 * For CPU synchronisation (NULL to) no request is required. For syncing with
3256 * rings to_req must be non-NULL. However, a request does not have to be
3257 * pre-allocated. If *to_req is NULL and sync commands will be emitted then a
3258 * request will be allocated automatically and returned through *to_req. Note
3259 * that it is not guaranteed that commands will be emitted (because the system
3260 * might already be idle). Hence there is no need to create a request that
3261 * might never have any work submitted. Note further that if a request is
3262 * returned in *to_req, it is the responsibility of the caller to submit
3263 * that request (after potentially adding more work to it).
3265 * Returns 0 if successful, else propagates up the lower layer error.
3268 i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
3269 struct intel_engine_cs
*to
,
3270 struct drm_i915_gem_request
**to_req
)
3272 const bool readonly
= obj
->base
.pending_write_domain
== 0;
3273 struct drm_i915_gem_request
*req
[I915_NUM_ENGINES
];
3280 return i915_gem_object_wait_rendering(obj
, readonly
);
3284 if (obj
->last_write_req
)
3285 req
[n
++] = obj
->last_write_req
;
3287 for (i
= 0; i
< I915_NUM_ENGINES
; i
++)
3288 if (obj
->last_read_req
[i
])
3289 req
[n
++] = obj
->last_read_req
[i
];
3291 for (i
= 0; i
< n
; i
++) {
3292 ret
= __i915_gem_object_sync(obj
, to
, req
[i
], to_req
);
3300 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object
*obj
)
3302 u32 old_write_domain
, old_read_domains
;
3304 /* Force a pagefault for domain tracking on next user access */
3305 i915_gem_release_mmap(obj
);
3307 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
) == 0)
3310 old_read_domains
= obj
->base
.read_domains
;
3311 old_write_domain
= obj
->base
.write_domain
;
3313 obj
->base
.read_domains
&= ~I915_GEM_DOMAIN_GTT
;
3314 obj
->base
.write_domain
&= ~I915_GEM_DOMAIN_GTT
;
3316 trace_i915_gem_object_change_domain(obj
,
3321 static void __i915_vma_iounmap(struct i915_vma
*vma
)
3323 GEM_BUG_ON(vma
->pin_count
);
3325 if (vma
->iomap
== NULL
)
3328 io_mapping_unmap(vma
->iomap
);
3332 static int __i915_vma_unbind(struct i915_vma
*vma
, bool wait
)
3334 struct drm_i915_gem_object
*obj
= vma
->obj
;
3335 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
3338 if (list_empty(&vma
->obj_link
))
3341 if (!drm_mm_node_allocated(&vma
->node
)) {
3342 i915_gem_vma_destroy(vma
);
3349 BUG_ON(obj
->pages
== NULL
);
3352 ret
= i915_gem_object_wait_rendering(obj
, false);
3357 if (vma
->is_ggtt
&& vma
->ggtt_view
.type
== I915_GGTT_VIEW_NORMAL
) {
3358 i915_gem_object_finish_gtt(obj
);
3360 /* release the fence reg _after_ flushing */
3361 ret
= i915_gem_object_put_fence(obj
);
3365 __i915_vma_iounmap(vma
);
3368 trace_i915_vma_unbind(vma
);
3370 vma
->vm
->unbind_vma(vma
);
3373 list_del_init(&vma
->vm_link
);
3375 if (vma
->ggtt_view
.type
== I915_GGTT_VIEW_NORMAL
) {
3376 obj
->map_and_fenceable
= false;
3377 } else if (vma
->ggtt_view
.pages
) {
3378 sg_free_table(vma
->ggtt_view
.pages
);
3379 kfree(vma
->ggtt_view
.pages
);
3381 vma
->ggtt_view
.pages
= NULL
;
3384 drm_mm_remove_node(&vma
->node
);
3385 i915_gem_vma_destroy(vma
);
3387 /* Since the unbound list is global, only move to that list if
3388 * no more VMAs exist. */
3389 if (list_empty(&obj
->vma_list
))
3390 list_move_tail(&obj
->global_list
, &dev_priv
->mm
.unbound_list
);
3392 /* And finally now the object is completely decoupled from this vma,
3393 * we can drop its hold on the backing storage and allow it to be
3394 * reaped by the shrinker.
3396 i915_gem_object_unpin_pages(obj
);
3401 int i915_vma_unbind(struct i915_vma
*vma
)
3403 return __i915_vma_unbind(vma
, true);
3406 int __i915_vma_unbind_no_wait(struct i915_vma
*vma
)
3408 return __i915_vma_unbind(vma
, false);
3411 int i915_gpu_idle(struct drm_device
*dev
)
3413 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3414 struct intel_engine_cs
*engine
;
3417 /* Flush everything onto the inactive list. */
3418 for_each_engine(engine
, dev_priv
) {
3419 if (!i915
.enable_execlists
) {
3420 struct drm_i915_gem_request
*req
;
3422 req
= i915_gem_request_alloc(engine
, NULL
);
3424 return PTR_ERR(req
);
3426 ret
= i915_switch_context(req
);
3427 i915_add_request_no_flush(req
);
3432 ret
= intel_engine_idle(engine
);
3437 WARN_ON(i915_verify_lists(dev
));
3441 static bool i915_gem_valid_gtt_space(struct i915_vma
*vma
,
3442 unsigned long cache_level
)
3444 struct drm_mm_node
*gtt_space
= &vma
->node
;
3445 struct drm_mm_node
*other
;
3448 * On some machines we have to be careful when putting differing types
3449 * of snoopable memory together to avoid the prefetcher crossing memory
3450 * domains and dying. During vm initialisation, we decide whether or not
3451 * these constraints apply and set the drm_mm.color_adjust
3454 if (vma
->vm
->mm
.color_adjust
== NULL
)
3457 if (!drm_mm_node_allocated(gtt_space
))
3460 if (list_empty(>t_space
->node_list
))
3463 other
= list_entry(gtt_space
->node_list
.prev
, struct drm_mm_node
, node_list
);
3464 if (other
->allocated
&& !other
->hole_follows
&& other
->color
!= cache_level
)
3467 other
= list_entry(gtt_space
->node_list
.next
, struct drm_mm_node
, node_list
);
3468 if (other
->allocated
&& !gtt_space
->hole_follows
&& other
->color
!= cache_level
)
3475 * Finds free space in the GTT aperture and binds the object or a view of it
3478 static struct i915_vma
*
3479 i915_gem_object_bind_to_vm(struct drm_i915_gem_object
*obj
,
3480 struct i915_address_space
*vm
,
3481 const struct i915_ggtt_view
*ggtt_view
,
3485 struct drm_device
*dev
= obj
->base
.dev
;
3486 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3487 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
3488 u32 fence_alignment
, unfenced_alignment
;
3489 u32 search_flag
, alloc_flag
;
3491 u64 size
, fence_size
;
3492 struct i915_vma
*vma
;
3495 if (i915_is_ggtt(vm
)) {
3498 if (WARN_ON(!ggtt_view
))
3499 return ERR_PTR(-EINVAL
);
3501 view_size
= i915_ggtt_view_size(obj
, ggtt_view
);
3503 fence_size
= i915_gem_get_gtt_size(dev
,
3506 fence_alignment
= i915_gem_get_gtt_alignment(dev
,
3510 unfenced_alignment
= i915_gem_get_gtt_alignment(dev
,
3514 size
= flags
& PIN_MAPPABLE
? fence_size
: view_size
;
3516 fence_size
= i915_gem_get_gtt_size(dev
,
3519 fence_alignment
= i915_gem_get_gtt_alignment(dev
,
3523 unfenced_alignment
=
3524 i915_gem_get_gtt_alignment(dev
,
3528 size
= flags
& PIN_MAPPABLE
? fence_size
: obj
->base
.size
;
3531 start
= flags
& PIN_OFFSET_BIAS
? flags
& PIN_OFFSET_MASK
: 0;
3533 if (flags
& PIN_MAPPABLE
)
3534 end
= min_t(u64
, end
, ggtt
->mappable_end
);
3535 if (flags
& PIN_ZONE_4G
)
3536 end
= min_t(u64
, end
, (1ULL << 32) - PAGE_SIZE
);
3539 alignment
= flags
& PIN_MAPPABLE
? fence_alignment
:
3541 if (flags
& PIN_MAPPABLE
&& alignment
& (fence_alignment
- 1)) {
3542 DRM_DEBUG("Invalid object (view type=%u) alignment requested %u\n",
3543 ggtt_view
? ggtt_view
->type
: 0,
3545 return ERR_PTR(-EINVAL
);
3548 /* If binding the object/GGTT view requires more space than the entire
3549 * aperture has, reject it early before evicting everything in a vain
3550 * attempt to find space.
3553 DRM_DEBUG("Attempting to bind an object (view type=%u) larger than the aperture: size=%llu > %s aperture=%llu\n",
3554 ggtt_view
? ggtt_view
->type
: 0,
3556 flags
& PIN_MAPPABLE
? "mappable" : "total",
3558 return ERR_PTR(-E2BIG
);
3561 ret
= i915_gem_object_get_pages(obj
);
3563 return ERR_PTR(ret
);
3565 i915_gem_object_pin_pages(obj
);
3567 vma
= ggtt_view
? i915_gem_obj_lookup_or_create_ggtt_vma(obj
, ggtt_view
) :
3568 i915_gem_obj_lookup_or_create_vma(obj
, vm
);
3573 if (flags
& PIN_OFFSET_FIXED
) {
3574 uint64_t offset
= flags
& PIN_OFFSET_MASK
;
3576 if (offset
& (alignment
- 1) || offset
+ size
> end
) {
3580 vma
->node
.start
= offset
;
3581 vma
->node
.size
= size
;
3582 vma
->node
.color
= obj
->cache_level
;
3583 ret
= drm_mm_reserve_node(&vm
->mm
, &vma
->node
);
3585 ret
= i915_gem_evict_for_vma(vma
);
3587 ret
= drm_mm_reserve_node(&vm
->mm
, &vma
->node
);
3592 if (flags
& PIN_HIGH
) {
3593 search_flag
= DRM_MM_SEARCH_BELOW
;
3594 alloc_flag
= DRM_MM_CREATE_TOP
;
3596 search_flag
= DRM_MM_SEARCH_DEFAULT
;
3597 alloc_flag
= DRM_MM_CREATE_DEFAULT
;
3601 ret
= drm_mm_insert_node_in_range_generic(&vm
->mm
, &vma
->node
,
3608 ret
= i915_gem_evict_something(dev
, vm
, size
, alignment
,
3618 if (WARN_ON(!i915_gem_valid_gtt_space(vma
, obj
->cache_level
))) {
3620 goto err_remove_node
;
3623 trace_i915_vma_bind(vma
, flags
);
3624 ret
= i915_vma_bind(vma
, obj
->cache_level
, flags
);
3626 goto err_remove_node
;
3628 list_move_tail(&obj
->global_list
, &dev_priv
->mm
.bound_list
);
3629 list_add_tail(&vma
->vm_link
, &vm
->inactive_list
);
3634 drm_mm_remove_node(&vma
->node
);
3636 i915_gem_vma_destroy(vma
);
3639 i915_gem_object_unpin_pages(obj
);
3644 i915_gem_clflush_object(struct drm_i915_gem_object
*obj
,
3647 /* If we don't have a page list set up, then we're not pinned
3648 * to GPU, and we can ignore the cache flush because it'll happen
3649 * again at bind time.
3651 if (obj
->pages
== NULL
)
3655 * Stolen memory is always coherent with the GPU as it is explicitly
3656 * marked as wc by the system, or the system is cache-coherent.
3658 if (obj
->stolen
|| obj
->phys_handle
)
3661 /* If the GPU is snooping the contents of the CPU cache,
3662 * we do not need to manually clear the CPU cache lines. However,
3663 * the caches are only snooped when the render cache is
3664 * flushed/invalidated. As we always have to emit invalidations
3665 * and flushes when moving into and out of the RENDER domain, correct
3666 * snooping behaviour occurs naturally as the result of our domain
3669 if (!force
&& cpu_cache_is_coherent(obj
->base
.dev
, obj
->cache_level
)) {
3670 obj
->cache_dirty
= true;
3674 trace_i915_gem_object_clflush(obj
);
3675 drm_clflush_sg(obj
->pages
);
3676 obj
->cache_dirty
= false;
3681 /** Flushes the GTT write domain for the object if it's dirty. */
3683 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
)
3685 uint32_t old_write_domain
;
3687 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_GTT
)
3690 /* No actual flushing is required for the GTT write domain. Writes
3691 * to it immediately go to main memory as far as we know, so there's
3692 * no chipset flush. It also doesn't land in render cache.
3694 * However, we do have to enforce the order so that all writes through
3695 * the GTT land before any writes to the device, such as updates to
3700 old_write_domain
= obj
->base
.write_domain
;
3701 obj
->base
.write_domain
= 0;
3703 intel_fb_obj_flush(obj
, false, ORIGIN_GTT
);
3705 trace_i915_gem_object_change_domain(obj
,
3706 obj
->base
.read_domains
,
3710 /** Flushes the CPU write domain for the object if it's dirty. */
3712 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
)
3714 uint32_t old_write_domain
;
3716 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
)
3719 if (i915_gem_clflush_object(obj
, obj
->pin_display
))
3720 i915_gem_chipset_flush(to_i915(obj
->base
.dev
));
3722 old_write_domain
= obj
->base
.write_domain
;
3723 obj
->base
.write_domain
= 0;
3725 intel_fb_obj_flush(obj
, false, ORIGIN_CPU
);
3727 trace_i915_gem_object_change_domain(obj
,
3728 obj
->base
.read_domains
,
3733 * Moves a single object to the GTT read, and possibly write domain.
3735 * This function returns when the move is complete, including waiting on
3739 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
, bool write
)
3741 struct drm_device
*dev
= obj
->base
.dev
;
3742 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3743 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
3744 uint32_t old_write_domain
, old_read_domains
;
3745 struct i915_vma
*vma
;
3748 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_GTT
)
3751 ret
= i915_gem_object_wait_rendering(obj
, !write
);
3755 /* Flush and acquire obj->pages so that we are coherent through
3756 * direct access in memory with previous cached writes through
3757 * shmemfs and that our cache domain tracking remains valid.
3758 * For example, if the obj->filp was moved to swap without us
3759 * being notified and releasing the pages, we would mistakenly
3760 * continue to assume that the obj remained out of the CPU cached
3763 ret
= i915_gem_object_get_pages(obj
);
3767 i915_gem_object_flush_cpu_write_domain(obj
);
3769 /* Serialise direct access to this object with the barriers for
3770 * coherent writes from the GPU, by effectively invalidating the
3771 * GTT domain upon first access.
3773 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
) == 0)
3776 old_write_domain
= obj
->base
.write_domain
;
3777 old_read_domains
= obj
->base
.read_domains
;
3779 /* It should now be out of any other write domains, and we can update
3780 * the domain values for our changes.
3782 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
3783 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
3785 obj
->base
.read_domains
= I915_GEM_DOMAIN_GTT
;
3786 obj
->base
.write_domain
= I915_GEM_DOMAIN_GTT
;
3790 trace_i915_gem_object_change_domain(obj
,
3794 /* And bump the LRU for this access */
3795 vma
= i915_gem_obj_to_ggtt(obj
);
3796 if (vma
&& drm_mm_node_allocated(&vma
->node
) && !obj
->active
)
3797 list_move_tail(&vma
->vm_link
,
3798 &ggtt
->base
.inactive_list
);
3804 * Changes the cache-level of an object across all VMA.
3806 * After this function returns, the object will be in the new cache-level
3807 * across all GTT and the contents of the backing storage will be coherent,
3808 * with respect to the new cache-level. In order to keep the backing storage
3809 * coherent for all users, we only allow a single cache level to be set
3810 * globally on the object and prevent it from being changed whilst the
3811 * hardware is reading from the object. That is if the object is currently
3812 * on the scanout it will be set to uncached (or equivalent display
3813 * cache coherency) and all non-MOCS GPU access will also be uncached so
3814 * that all direct access to the scanout remains coherent.
3816 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
3817 enum i915_cache_level cache_level
)
3819 struct drm_device
*dev
= obj
->base
.dev
;
3820 struct i915_vma
*vma
, *next
;
3824 if (obj
->cache_level
== cache_level
)
3827 /* Inspect the list of currently bound VMA and unbind any that would
3828 * be invalid given the new cache-level. This is principally to
3829 * catch the issue of the CS prefetch crossing page boundaries and
3830 * reading an invalid PTE on older architectures.
3832 list_for_each_entry_safe(vma
, next
, &obj
->vma_list
, obj_link
) {
3833 if (!drm_mm_node_allocated(&vma
->node
))
3836 if (vma
->pin_count
) {
3837 DRM_DEBUG("can not change the cache level of pinned objects\n");
3841 if (!i915_gem_valid_gtt_space(vma
, cache_level
)) {
3842 ret
= i915_vma_unbind(vma
);
3849 /* We can reuse the existing drm_mm nodes but need to change the
3850 * cache-level on the PTE. We could simply unbind them all and
3851 * rebind with the correct cache-level on next use. However since
3852 * we already have a valid slot, dma mapping, pages etc, we may as
3853 * rewrite the PTE in the belief that doing so tramples upon less
3854 * state and so involves less work.
3857 /* Before we change the PTE, the GPU must not be accessing it.
3858 * If we wait upon the object, we know that all the bound
3859 * VMA are no longer active.
3861 ret
= i915_gem_object_wait_rendering(obj
, false);
3865 if (!HAS_LLC(dev
) && cache_level
!= I915_CACHE_NONE
) {
3866 /* Access to snoopable pages through the GTT is
3867 * incoherent and on some machines causes a hard
3868 * lockup. Relinquish the CPU mmaping to force
3869 * userspace to refault in the pages and we can
3870 * then double check if the GTT mapping is still
3871 * valid for that pointer access.
3873 i915_gem_release_mmap(obj
);
3875 /* As we no longer need a fence for GTT access,
3876 * we can relinquish it now (and so prevent having
3877 * to steal a fence from someone else on the next
3878 * fence request). Note GPU activity would have
3879 * dropped the fence as all snoopable access is
3880 * supposed to be linear.
3882 ret
= i915_gem_object_put_fence(obj
);
3886 /* We either have incoherent backing store and
3887 * so no GTT access or the architecture is fully
3888 * coherent. In such cases, existing GTT mmaps
3889 * ignore the cache bit in the PTE and we can
3890 * rewrite it without confusing the GPU or having
3891 * to force userspace to fault back in its mmaps.
3895 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
) {
3896 if (!drm_mm_node_allocated(&vma
->node
))
3899 ret
= i915_vma_bind(vma
, cache_level
, PIN_UPDATE
);
3905 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
)
3906 vma
->node
.color
= cache_level
;
3907 obj
->cache_level
= cache_level
;
3910 /* Flush the dirty CPU caches to the backing storage so that the
3911 * object is now coherent at its new cache level (with respect
3912 * to the access domain).
3914 if (obj
->cache_dirty
&&
3915 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
&&
3916 cpu_write_needs_clflush(obj
)) {
3917 if (i915_gem_clflush_object(obj
, true))
3918 i915_gem_chipset_flush(to_i915(obj
->base
.dev
));
3924 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
3925 struct drm_file
*file
)
3927 struct drm_i915_gem_caching
*args
= data
;
3928 struct drm_i915_gem_object
*obj
;
3930 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3931 if (&obj
->base
== NULL
)
3934 switch (obj
->cache_level
) {
3935 case I915_CACHE_LLC
:
3936 case I915_CACHE_L3_LLC
:
3937 args
->caching
= I915_CACHING_CACHED
;
3941 args
->caching
= I915_CACHING_DISPLAY
;
3945 args
->caching
= I915_CACHING_NONE
;
3949 drm_gem_object_unreference_unlocked(&obj
->base
);
3953 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
3954 struct drm_file
*file
)
3956 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3957 struct drm_i915_gem_caching
*args
= data
;
3958 struct drm_i915_gem_object
*obj
;
3959 enum i915_cache_level level
;
3962 switch (args
->caching
) {
3963 case I915_CACHING_NONE
:
3964 level
= I915_CACHE_NONE
;
3966 case I915_CACHING_CACHED
:
3968 * Due to a HW issue on BXT A stepping, GPU stores via a
3969 * snooped mapping may leave stale data in a corresponding CPU
3970 * cacheline, whereas normally such cachelines would get
3973 if (!HAS_LLC(dev
) && !HAS_SNOOP(dev
))
3976 level
= I915_CACHE_LLC
;
3978 case I915_CACHING_DISPLAY
:
3979 level
= HAS_WT(dev
) ? I915_CACHE_WT
: I915_CACHE_NONE
;
3985 intel_runtime_pm_get(dev_priv
);
3987 ret
= i915_mutex_lock_interruptible(dev
);
3991 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3992 if (&obj
->base
== NULL
) {
3997 ret
= i915_gem_object_set_cache_level(obj
, level
);
3999 drm_gem_object_unreference(&obj
->base
);
4001 mutex_unlock(&dev
->struct_mutex
);
4003 intel_runtime_pm_put(dev_priv
);
4009 * Prepare buffer for display plane (scanout, cursors, etc).
4010 * Can be called from an uninterruptible phase (modesetting) and allows
4011 * any flushes to be pipelined (for pageflips).
4014 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
4016 const struct i915_ggtt_view
*view
)
4018 u32 old_read_domains
, old_write_domain
;
4021 /* Mark the pin_display early so that we account for the
4022 * display coherency whilst setting up the cache domains.
4026 /* The display engine is not coherent with the LLC cache on gen6. As
4027 * a result, we make sure that the pinning that is about to occur is
4028 * done with uncached PTEs. This is lowest common denominator for all
4031 * However for gen6+, we could do better by using the GFDT bit instead
4032 * of uncaching, which would allow us to flush all the LLC-cached data
4033 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
4035 ret
= i915_gem_object_set_cache_level(obj
,
4036 HAS_WT(obj
->base
.dev
) ? I915_CACHE_WT
: I915_CACHE_NONE
);
4038 goto err_unpin_display
;
4040 /* As the user may map the buffer once pinned in the display plane
4041 * (e.g. libkms for the bootup splash), we have to ensure that we
4042 * always use map_and_fenceable for all scanout buffers.
4044 ret
= i915_gem_object_ggtt_pin(obj
, view
, alignment
,
4045 view
->type
== I915_GGTT_VIEW_NORMAL
?
4048 goto err_unpin_display
;
4050 i915_gem_object_flush_cpu_write_domain(obj
);
4052 old_write_domain
= obj
->base
.write_domain
;
4053 old_read_domains
= obj
->base
.read_domains
;
4055 /* It should now be out of any other write domains, and we can update
4056 * the domain values for our changes.
4058 obj
->base
.write_domain
= 0;
4059 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
4061 trace_i915_gem_object_change_domain(obj
,
4073 i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object
*obj
,
4074 const struct i915_ggtt_view
*view
)
4076 if (WARN_ON(obj
->pin_display
== 0))
4079 i915_gem_object_ggtt_unpin_view(obj
, view
);
4085 * Moves a single object to the CPU read, and possibly write domain.
4087 * This function returns when the move is complete, including waiting on
4091 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
)
4093 uint32_t old_write_domain
, old_read_domains
;
4096 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_CPU
)
4099 ret
= i915_gem_object_wait_rendering(obj
, !write
);
4103 i915_gem_object_flush_gtt_write_domain(obj
);
4105 old_write_domain
= obj
->base
.write_domain
;
4106 old_read_domains
= obj
->base
.read_domains
;
4108 /* Flush the CPU cache if it's still invalid. */
4109 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) == 0) {
4110 i915_gem_clflush_object(obj
, false);
4112 obj
->base
.read_domains
|= I915_GEM_DOMAIN_CPU
;
4115 /* It should now be out of any other write domains, and we can update
4116 * the domain values for our changes.
4118 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
4120 /* If we're writing through the CPU, then the GPU read domains will
4121 * need to be invalidated at next use.
4124 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
4125 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
4128 trace_i915_gem_object_change_domain(obj
,
4135 /* Throttle our rendering by waiting until the ring has completed our requests
4136 * emitted over 20 msec ago.
4138 * Note that if we were to use the current jiffies each time around the loop,
4139 * we wouldn't escape the function with any frames outstanding if the time to
4140 * render a frame was over 20ms.
4142 * This should get us reasonable parallelism between CPU and GPU but also
4143 * relatively low latency when blocking on a particular request to finish.
4146 i915_gem_ring_throttle(struct drm_device
*dev
, struct drm_file
*file
)
4148 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4149 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
4150 unsigned long recent_enough
= jiffies
- DRM_I915_THROTTLE_JIFFIES
;
4151 struct drm_i915_gem_request
*request
, *target
= NULL
;
4154 ret
= i915_gem_wait_for_error(&dev_priv
->gpu_error
);
4158 /* ABI: return -EIO if already wedged */
4159 if (i915_terminally_wedged(&dev_priv
->gpu_error
))
4162 spin_lock(&file_priv
->mm
.lock
);
4163 list_for_each_entry(request
, &file_priv
->mm
.request_list
, client_list
) {
4164 if (time_after_eq(request
->emitted_jiffies
, recent_enough
))
4168 * Note that the request might not have been submitted yet.
4169 * In which case emitted_jiffies will be zero.
4171 if (!request
->emitted_jiffies
)
4177 i915_gem_request_reference(target
);
4178 spin_unlock(&file_priv
->mm
.lock
);
4183 ret
= __i915_wait_request(target
, true, NULL
, NULL
);
4185 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, 0);
4187 i915_gem_request_unreference(target
);
4193 i915_vma_misplaced(struct i915_vma
*vma
, uint32_t alignment
, uint64_t flags
)
4195 struct drm_i915_gem_object
*obj
= vma
->obj
;
4198 vma
->node
.start
& (alignment
- 1))
4201 if (flags
& PIN_MAPPABLE
&& !obj
->map_and_fenceable
)
4204 if (flags
& PIN_OFFSET_BIAS
&&
4205 vma
->node
.start
< (flags
& PIN_OFFSET_MASK
))
4208 if (flags
& PIN_OFFSET_FIXED
&&
4209 vma
->node
.start
!= (flags
& PIN_OFFSET_MASK
))
4215 void __i915_vma_set_map_and_fenceable(struct i915_vma
*vma
)
4217 struct drm_i915_gem_object
*obj
= vma
->obj
;
4218 bool mappable
, fenceable
;
4219 u32 fence_size
, fence_alignment
;
4221 fence_size
= i915_gem_get_gtt_size(obj
->base
.dev
,
4224 fence_alignment
= i915_gem_get_gtt_alignment(obj
->base
.dev
,
4229 fenceable
= (vma
->node
.size
== fence_size
&&
4230 (vma
->node
.start
& (fence_alignment
- 1)) == 0);
4232 mappable
= (vma
->node
.start
+ fence_size
<=
4233 to_i915(obj
->base
.dev
)->ggtt
.mappable_end
);
4235 obj
->map_and_fenceable
= mappable
&& fenceable
;
4239 i915_gem_object_do_pin(struct drm_i915_gem_object
*obj
,
4240 struct i915_address_space
*vm
,
4241 const struct i915_ggtt_view
*ggtt_view
,
4245 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
4246 struct i915_vma
*vma
;
4250 if (WARN_ON(vm
== &dev_priv
->mm
.aliasing_ppgtt
->base
))
4253 if (WARN_ON(flags
& (PIN_GLOBAL
| PIN_MAPPABLE
) && !i915_is_ggtt(vm
)))
4256 if (WARN_ON((flags
& (PIN_MAPPABLE
| PIN_GLOBAL
)) == PIN_MAPPABLE
))
4259 if (WARN_ON(i915_is_ggtt(vm
) != !!ggtt_view
))
4262 vma
= ggtt_view
? i915_gem_obj_to_ggtt_view(obj
, ggtt_view
) :
4263 i915_gem_obj_to_vma(obj
, vm
);
4266 if (WARN_ON(vma
->pin_count
== DRM_I915_GEM_OBJECT_MAX_PIN_COUNT
))
4269 if (i915_vma_misplaced(vma
, alignment
, flags
)) {
4270 WARN(vma
->pin_count
,
4271 "bo is already pinned in %s with incorrect alignment:"
4272 " offset=%08x %08x, req.alignment=%x, req.map_and_fenceable=%d,"
4273 " obj->map_and_fenceable=%d\n",
4274 ggtt_view
? "ggtt" : "ppgtt",
4275 upper_32_bits(vma
->node
.start
),
4276 lower_32_bits(vma
->node
.start
),
4278 !!(flags
& PIN_MAPPABLE
),
4279 obj
->map_and_fenceable
);
4280 ret
= i915_vma_unbind(vma
);
4288 bound
= vma
? vma
->bound
: 0;
4289 if (vma
== NULL
|| !drm_mm_node_allocated(&vma
->node
)) {
4290 vma
= i915_gem_object_bind_to_vm(obj
, vm
, ggtt_view
, alignment
,
4293 return PTR_ERR(vma
);
4295 ret
= i915_vma_bind(vma
, obj
->cache_level
, flags
);
4300 if (ggtt_view
&& ggtt_view
->type
== I915_GGTT_VIEW_NORMAL
&&
4301 (bound
^ vma
->bound
) & GLOBAL_BIND
) {
4302 __i915_vma_set_map_and_fenceable(vma
);
4303 WARN_ON(flags
& PIN_MAPPABLE
&& !obj
->map_and_fenceable
);
4311 i915_gem_object_pin(struct drm_i915_gem_object
*obj
,
4312 struct i915_address_space
*vm
,
4316 return i915_gem_object_do_pin(obj
, vm
,
4317 i915_is_ggtt(vm
) ? &i915_ggtt_view_normal
: NULL
,
4322 i915_gem_object_ggtt_pin(struct drm_i915_gem_object
*obj
,
4323 const struct i915_ggtt_view
*view
,
4327 struct drm_device
*dev
= obj
->base
.dev
;
4328 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4329 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
4333 return i915_gem_object_do_pin(obj
, &ggtt
->base
, view
,
4334 alignment
, flags
| PIN_GLOBAL
);
4338 i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object
*obj
,
4339 const struct i915_ggtt_view
*view
)
4341 struct i915_vma
*vma
= i915_gem_obj_to_ggtt_view(obj
, view
);
4343 WARN_ON(vma
->pin_count
== 0);
4344 WARN_ON(!i915_gem_obj_ggtt_bound_view(obj
, view
));
4350 i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
4351 struct drm_file
*file
)
4353 struct drm_i915_gem_busy
*args
= data
;
4354 struct drm_i915_gem_object
*obj
;
4357 ret
= i915_mutex_lock_interruptible(dev
);
4361 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
4362 if (&obj
->base
== NULL
) {
4367 /* Count all active objects as busy, even if they are currently not used
4368 * by the gpu. Users of this interface expect objects to eventually
4369 * become non-busy without any further actions, therefore emit any
4370 * necessary flushes here.
4372 ret
= i915_gem_object_flush_active(obj
);
4380 for (i
= 0; i
< I915_NUM_ENGINES
; i
++) {
4381 struct drm_i915_gem_request
*req
;
4383 req
= obj
->last_read_req
[i
];
4385 args
->busy
|= 1 << (16 + req
->engine
->exec_id
);
4387 if (obj
->last_write_req
)
4388 args
->busy
|= obj
->last_write_req
->engine
->exec_id
;
4392 drm_gem_object_unreference(&obj
->base
);
4394 mutex_unlock(&dev
->struct_mutex
);
4399 i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
4400 struct drm_file
*file_priv
)
4402 return i915_gem_ring_throttle(dev
, file_priv
);
4406 i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
4407 struct drm_file
*file_priv
)
4409 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4410 struct drm_i915_gem_madvise
*args
= data
;
4411 struct drm_i915_gem_object
*obj
;
4414 switch (args
->madv
) {
4415 case I915_MADV_DONTNEED
:
4416 case I915_MADV_WILLNEED
:
4422 ret
= i915_mutex_lock_interruptible(dev
);
4426 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file_priv
, args
->handle
));
4427 if (&obj
->base
== NULL
) {
4432 if (i915_gem_obj_is_pinned(obj
)) {
4438 obj
->tiling_mode
!= I915_TILING_NONE
&&
4439 dev_priv
->quirks
& QUIRK_PIN_SWIZZLED_PAGES
) {
4440 if (obj
->madv
== I915_MADV_WILLNEED
)
4441 i915_gem_object_unpin_pages(obj
);
4442 if (args
->madv
== I915_MADV_WILLNEED
)
4443 i915_gem_object_pin_pages(obj
);
4446 if (obj
->madv
!= __I915_MADV_PURGED
)
4447 obj
->madv
= args
->madv
;
4449 /* if the object is no longer attached, discard its backing storage */
4450 if (obj
->madv
== I915_MADV_DONTNEED
&& obj
->pages
== NULL
)
4451 i915_gem_object_truncate(obj
);
4453 args
->retained
= obj
->madv
!= __I915_MADV_PURGED
;
4456 drm_gem_object_unreference(&obj
->base
);
4458 mutex_unlock(&dev
->struct_mutex
);
4462 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
4463 const struct drm_i915_gem_object_ops
*ops
)
4467 INIT_LIST_HEAD(&obj
->global_list
);
4468 for (i
= 0; i
< I915_NUM_ENGINES
; i
++)
4469 INIT_LIST_HEAD(&obj
->engine_list
[i
]);
4470 INIT_LIST_HEAD(&obj
->obj_exec_link
);
4471 INIT_LIST_HEAD(&obj
->vma_list
);
4472 INIT_LIST_HEAD(&obj
->batch_pool_link
);
4476 obj
->fence_reg
= I915_FENCE_REG_NONE
;
4477 obj
->madv
= I915_MADV_WILLNEED
;
4479 i915_gem_info_add_obj(obj
->base
.dev
->dev_private
, obj
->base
.size
);
4482 static const struct drm_i915_gem_object_ops i915_gem_object_ops
= {
4483 .flags
= I915_GEM_OBJECT_HAS_STRUCT_PAGE
,
4484 .get_pages
= i915_gem_object_get_pages_gtt
,
4485 .put_pages
= i915_gem_object_put_pages_gtt
,
4488 struct drm_i915_gem_object
*i915_gem_object_create(struct drm_device
*dev
,
4491 struct drm_i915_gem_object
*obj
;
4492 struct address_space
*mapping
;
4496 obj
= i915_gem_object_alloc(dev
);
4498 return ERR_PTR(-ENOMEM
);
4500 ret
= drm_gem_object_init(dev
, &obj
->base
, size
);
4504 mask
= GFP_HIGHUSER
| __GFP_RECLAIMABLE
;
4505 if (IS_CRESTLINE(dev
) || IS_BROADWATER(dev
)) {
4506 /* 965gm cannot relocate objects above 4GiB. */
4507 mask
&= ~__GFP_HIGHMEM
;
4508 mask
|= __GFP_DMA32
;
4511 mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
4512 mapping_set_gfp_mask(mapping
, mask
);
4514 i915_gem_object_init(obj
, &i915_gem_object_ops
);
4516 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
4517 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
4520 /* On some devices, we can have the GPU use the LLC (the CPU
4521 * cache) for about a 10% performance improvement
4522 * compared to uncached. Graphics requests other than
4523 * display scanout are coherent with the CPU in
4524 * accessing this cache. This means in this mode we
4525 * don't need to clflush on the CPU side, and on the
4526 * GPU side we only need to flush internal caches to
4527 * get data visible to the CPU.
4529 * However, we maintain the display planes as UC, and so
4530 * need to rebind when first used as such.
4532 obj
->cache_level
= I915_CACHE_LLC
;
4534 obj
->cache_level
= I915_CACHE_NONE
;
4536 trace_i915_gem_object_create(obj
);
4541 i915_gem_object_free(obj
);
4543 return ERR_PTR(ret
);
4546 static bool discard_backing_storage(struct drm_i915_gem_object
*obj
)
4548 /* If we are the last user of the backing storage (be it shmemfs
4549 * pages or stolen etc), we know that the pages are going to be
4550 * immediately released. In this case, we can then skip copying
4551 * back the contents from the GPU.
4554 if (obj
->madv
!= I915_MADV_WILLNEED
)
4557 if (obj
->base
.filp
== NULL
)
4560 /* At first glance, this looks racy, but then again so would be
4561 * userspace racing mmap against close. However, the first external
4562 * reference to the filp can only be obtained through the
4563 * i915_gem_mmap_ioctl() which safeguards us against the user
4564 * acquiring such a reference whilst we are in the middle of
4565 * freeing the object.
4567 return atomic_long_read(&obj
->base
.filp
->f_count
) == 1;
4570 void i915_gem_free_object(struct drm_gem_object
*gem_obj
)
4572 struct drm_i915_gem_object
*obj
= to_intel_bo(gem_obj
);
4573 struct drm_device
*dev
= obj
->base
.dev
;
4574 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4575 struct i915_vma
*vma
, *next
;
4577 intel_runtime_pm_get(dev_priv
);
4579 trace_i915_gem_object_destroy(obj
);
4581 list_for_each_entry_safe(vma
, next
, &obj
->vma_list
, obj_link
) {
4585 ret
= i915_vma_unbind(vma
);
4586 if (WARN_ON(ret
== -ERESTARTSYS
)) {
4587 bool was_interruptible
;
4589 was_interruptible
= dev_priv
->mm
.interruptible
;
4590 dev_priv
->mm
.interruptible
= false;
4592 WARN_ON(i915_vma_unbind(vma
));
4594 dev_priv
->mm
.interruptible
= was_interruptible
;
4598 /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
4599 * before progressing. */
4601 i915_gem_object_unpin_pages(obj
);
4603 WARN_ON(obj
->frontbuffer_bits
);
4605 if (obj
->pages
&& obj
->madv
== I915_MADV_WILLNEED
&&
4606 dev_priv
->quirks
& QUIRK_PIN_SWIZZLED_PAGES
&&
4607 obj
->tiling_mode
!= I915_TILING_NONE
)
4608 i915_gem_object_unpin_pages(obj
);
4610 if (WARN_ON(obj
->pages_pin_count
))
4611 obj
->pages_pin_count
= 0;
4612 if (discard_backing_storage(obj
))
4613 obj
->madv
= I915_MADV_DONTNEED
;
4614 i915_gem_object_put_pages(obj
);
4615 i915_gem_object_free_mmap_offset(obj
);
4619 if (obj
->base
.import_attach
)
4620 drm_prime_gem_destroy(&obj
->base
, NULL
);
4622 if (obj
->ops
->release
)
4623 obj
->ops
->release(obj
);
4625 drm_gem_object_release(&obj
->base
);
4626 i915_gem_info_remove_obj(dev_priv
, obj
->base
.size
);
4629 i915_gem_object_free(obj
);
4631 intel_runtime_pm_put(dev_priv
);
4634 struct i915_vma
*i915_gem_obj_to_vma(struct drm_i915_gem_object
*obj
,
4635 struct i915_address_space
*vm
)
4637 struct i915_vma
*vma
;
4638 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
) {
4639 if (vma
->ggtt_view
.type
== I915_GGTT_VIEW_NORMAL
&&
4646 struct i915_vma
*i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object
*obj
,
4647 const struct i915_ggtt_view
*view
)
4649 struct i915_vma
*vma
;
4653 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
)
4654 if (vma
->is_ggtt
&& i915_ggtt_view_equal(&vma
->ggtt_view
, view
))
4659 void i915_gem_vma_destroy(struct i915_vma
*vma
)
4661 WARN_ON(vma
->node
.allocated
);
4663 /* Keep the vma as a placeholder in the execbuffer reservation lists */
4664 if (!list_empty(&vma
->exec_list
))
4668 i915_ppgtt_put(i915_vm_to_ppgtt(vma
->vm
));
4670 list_del(&vma
->obj_link
);
4672 kmem_cache_free(to_i915(vma
->obj
->base
.dev
)->vmas
, vma
);
4676 i915_gem_stop_engines(struct drm_device
*dev
)
4678 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4679 struct intel_engine_cs
*engine
;
4681 for_each_engine(engine
, dev_priv
)
4682 dev_priv
->gt
.stop_engine(engine
);
4686 i915_gem_suspend(struct drm_device
*dev
)
4688 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4691 mutex_lock(&dev
->struct_mutex
);
4692 ret
= i915_gpu_idle(dev
);
4696 i915_gem_retire_requests(dev_priv
);
4698 i915_gem_stop_engines(dev
);
4699 i915_gem_context_lost(dev_priv
);
4700 mutex_unlock(&dev
->struct_mutex
);
4702 cancel_delayed_work_sync(&dev_priv
->gpu_error
.hangcheck_work
);
4703 cancel_delayed_work_sync(&dev_priv
->mm
.retire_work
);
4704 flush_delayed_work(&dev_priv
->mm
.idle_work
);
4706 /* Assert that we sucessfully flushed all the work and
4707 * reset the GPU back to its idle, low power state.
4709 WARN_ON(dev_priv
->mm
.busy
);
4714 mutex_unlock(&dev
->struct_mutex
);
4718 void i915_gem_init_swizzling(struct drm_device
*dev
)
4720 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4722 if (INTEL_INFO(dev
)->gen
< 5 ||
4723 dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_NONE
)
4726 I915_WRITE(DISP_ARB_CTL
, I915_READ(DISP_ARB_CTL
) |
4727 DISP_TILE_SURFACE_SWIZZLING
);
4732 I915_WRITE(TILECTL
, I915_READ(TILECTL
) | TILECTL_SWZCTL
);
4734 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB
));
4735 else if (IS_GEN7(dev
))
4736 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB
));
4737 else if (IS_GEN8(dev
))
4738 I915_WRITE(GAMTARBMODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW
));
4743 static void init_unused_ring(struct drm_device
*dev
, u32 base
)
4745 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4747 I915_WRITE(RING_CTL(base
), 0);
4748 I915_WRITE(RING_HEAD(base
), 0);
4749 I915_WRITE(RING_TAIL(base
), 0);
4750 I915_WRITE(RING_START(base
), 0);
4753 static void init_unused_rings(struct drm_device
*dev
)
4756 init_unused_ring(dev
, PRB1_BASE
);
4757 init_unused_ring(dev
, SRB0_BASE
);
4758 init_unused_ring(dev
, SRB1_BASE
);
4759 init_unused_ring(dev
, SRB2_BASE
);
4760 init_unused_ring(dev
, SRB3_BASE
);
4761 } else if (IS_GEN2(dev
)) {
4762 init_unused_ring(dev
, SRB0_BASE
);
4763 init_unused_ring(dev
, SRB1_BASE
);
4764 } else if (IS_GEN3(dev
)) {
4765 init_unused_ring(dev
, PRB1_BASE
);
4766 init_unused_ring(dev
, PRB2_BASE
);
4770 int i915_gem_init_engines(struct drm_device
*dev
)
4772 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4775 ret
= intel_init_render_ring_buffer(dev
);
4780 ret
= intel_init_bsd_ring_buffer(dev
);
4782 goto cleanup_render_ring
;
4786 ret
= intel_init_blt_ring_buffer(dev
);
4788 goto cleanup_bsd_ring
;
4791 if (HAS_VEBOX(dev
)) {
4792 ret
= intel_init_vebox_ring_buffer(dev
);
4794 goto cleanup_blt_ring
;
4797 if (HAS_BSD2(dev
)) {
4798 ret
= intel_init_bsd2_ring_buffer(dev
);
4800 goto cleanup_vebox_ring
;
4806 intel_cleanup_engine(&dev_priv
->engine
[VECS
]);
4808 intel_cleanup_engine(&dev_priv
->engine
[BCS
]);
4810 intel_cleanup_engine(&dev_priv
->engine
[VCS
]);
4811 cleanup_render_ring
:
4812 intel_cleanup_engine(&dev_priv
->engine
[RCS
]);
4818 i915_gem_init_hw(struct drm_device
*dev
)
4820 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4821 struct intel_engine_cs
*engine
;
4824 if (INTEL_INFO(dev
)->gen
< 6 && !intel_enable_gtt())
4827 /* Double layer security blanket, see i915_gem_init() */
4828 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
4830 if (HAS_EDRAM(dev
) && INTEL_GEN(dev_priv
) < 9)
4831 I915_WRITE(HSW_IDICR
, I915_READ(HSW_IDICR
) | IDIHASHMSK(0xf));
4833 if (IS_HASWELL(dev
))
4834 I915_WRITE(MI_PREDICATE_RESULT_2
, IS_HSW_GT3(dev
) ?
4835 LOWER_SLICE_ENABLED
: LOWER_SLICE_DISABLED
);
4837 if (HAS_PCH_NOP(dev
)) {
4838 if (IS_IVYBRIDGE(dev
)) {
4839 u32 temp
= I915_READ(GEN7_MSG_CTL
);
4840 temp
&= ~(WAIT_FOR_PCH_FLR_ACK
| WAIT_FOR_PCH_RESET_ACK
);
4841 I915_WRITE(GEN7_MSG_CTL
, temp
);
4842 } else if (INTEL_INFO(dev
)->gen
>= 7) {
4843 u32 temp
= I915_READ(HSW_NDE_RSTWRN_OPT
);
4844 temp
&= ~RESET_PCH_HANDSHAKE_ENABLE
;
4845 I915_WRITE(HSW_NDE_RSTWRN_OPT
, temp
);
4849 i915_gem_init_swizzling(dev
);
4852 * At least 830 can leave some of the unused rings
4853 * "active" (ie. head != tail) after resume which
4854 * will prevent c3 entry. Makes sure all unused rings
4857 init_unused_rings(dev
);
4859 BUG_ON(!dev_priv
->kernel_context
);
4861 ret
= i915_ppgtt_init_hw(dev
);
4863 DRM_ERROR("PPGTT enable HW failed %d\n", ret
);
4867 /* Need to do basic initialisation of all rings first: */
4868 for_each_engine(engine
, dev_priv
) {
4869 ret
= engine
->init_hw(engine
);
4874 intel_mocs_init_l3cc_table(dev
);
4876 /* We can't enable contexts until all firmware is loaded */
4877 if (HAS_GUC_UCODE(dev
)) {
4878 ret
= intel_guc_ucode_load(dev
);
4880 DRM_ERROR("Failed to initialize GuC, error %d\n", ret
);
4887 * Increment the next seqno by 0x100 so we have a visible break
4888 * on re-initialisation
4890 ret
= i915_gem_set_seqno(dev
, dev_priv
->next_seqno
+0x100);
4893 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
4897 int i915_gem_init(struct drm_device
*dev
)
4899 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4902 mutex_lock(&dev
->struct_mutex
);
4904 if (!i915
.enable_execlists
) {
4905 dev_priv
->gt
.execbuf_submit
= i915_gem_ringbuffer_submission
;
4906 dev_priv
->gt
.init_engines
= i915_gem_init_engines
;
4907 dev_priv
->gt
.cleanup_engine
= intel_cleanup_engine
;
4908 dev_priv
->gt
.stop_engine
= intel_stop_engine
;
4910 dev_priv
->gt
.execbuf_submit
= intel_execlists_submission
;
4911 dev_priv
->gt
.init_engines
= intel_logical_rings_init
;
4912 dev_priv
->gt
.cleanup_engine
= intel_logical_ring_cleanup
;
4913 dev_priv
->gt
.stop_engine
= intel_logical_ring_stop
;
4916 /* This is just a security blanket to placate dragons.
4917 * On some systems, we very sporadically observe that the first TLBs
4918 * used by the CS may be stale, despite us poking the TLB reset. If
4919 * we hold the forcewake during initialisation these problems
4920 * just magically go away.
4922 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
4924 ret
= i915_gem_init_userptr(dev
);
4928 i915_gem_init_ggtt(dev
);
4930 ret
= i915_gem_context_init(dev
);
4934 ret
= dev_priv
->gt
.init_engines(dev
);
4938 ret
= i915_gem_init_hw(dev
);
4940 /* Allow ring initialisation to fail by marking the GPU as
4941 * wedged. But we only want to do this where the GPU is angry,
4942 * for all other failure, such as an allocation failure, bail.
4944 DRM_ERROR("Failed to initialize GPU, declaring it wedged\n");
4945 atomic_or(I915_WEDGED
, &dev_priv
->gpu_error
.reset_counter
);
4950 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
4951 mutex_unlock(&dev
->struct_mutex
);
4957 i915_gem_cleanup_engines(struct drm_device
*dev
)
4959 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4960 struct intel_engine_cs
*engine
;
4962 for_each_engine(engine
, dev_priv
)
4963 dev_priv
->gt
.cleanup_engine(engine
);
4967 init_engine_lists(struct intel_engine_cs
*engine
)
4969 INIT_LIST_HEAD(&engine
->active_list
);
4970 INIT_LIST_HEAD(&engine
->request_list
);
4974 i915_gem_load_init_fences(struct drm_i915_private
*dev_priv
)
4976 struct drm_device
*dev
= dev_priv
->dev
;
4978 if (INTEL_INFO(dev_priv
)->gen
>= 7 && !IS_VALLEYVIEW(dev_priv
) &&
4979 !IS_CHERRYVIEW(dev_priv
))
4980 dev_priv
->num_fence_regs
= 32;
4981 else if (INTEL_INFO(dev_priv
)->gen
>= 4 || IS_I945G(dev_priv
) ||
4982 IS_I945GM(dev_priv
) || IS_G33(dev_priv
))
4983 dev_priv
->num_fence_regs
= 16;
4985 dev_priv
->num_fence_regs
= 8;
4987 if (intel_vgpu_active(dev_priv
))
4988 dev_priv
->num_fence_regs
=
4989 I915_READ(vgtif_reg(avail_rs
.fence_num
));
4991 /* Initialize fence registers to zero */
4992 i915_gem_restore_fences(dev
);
4994 i915_gem_detect_bit_6_swizzle(dev
);
4998 i915_gem_load_init(struct drm_device
*dev
)
5000 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5004 kmem_cache_create("i915_gem_object",
5005 sizeof(struct drm_i915_gem_object
), 0,
5009 kmem_cache_create("i915_gem_vma",
5010 sizeof(struct i915_vma
), 0,
5013 dev_priv
->requests
=
5014 kmem_cache_create("i915_gem_request",
5015 sizeof(struct drm_i915_gem_request
), 0,
5019 INIT_LIST_HEAD(&dev_priv
->vm_list
);
5020 INIT_LIST_HEAD(&dev_priv
->context_list
);
5021 INIT_LIST_HEAD(&dev_priv
->mm
.unbound_list
);
5022 INIT_LIST_HEAD(&dev_priv
->mm
.bound_list
);
5023 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
5024 for (i
= 0; i
< I915_NUM_ENGINES
; i
++)
5025 init_engine_lists(&dev_priv
->engine
[i
]);
5026 for (i
= 0; i
< I915_MAX_NUM_FENCES
; i
++)
5027 INIT_LIST_HEAD(&dev_priv
->fence_regs
[i
].lru_list
);
5028 INIT_DELAYED_WORK(&dev_priv
->mm
.retire_work
,
5029 i915_gem_retire_work_handler
);
5030 INIT_DELAYED_WORK(&dev_priv
->mm
.idle_work
,
5031 i915_gem_idle_work_handler
);
5032 init_waitqueue_head(&dev_priv
->gpu_error
.reset_queue
);
5034 dev_priv
->relative_constants_mode
= I915_EXEC_CONSTANTS_REL_GENERAL
;
5037 * Set initial sequence number for requests.
5038 * Using this number allows the wraparound to happen early,
5039 * catching any obvious problems.
5041 dev_priv
->next_seqno
= ((u32
)~0 - 0x1100);
5042 dev_priv
->last_seqno
= ((u32
)~0 - 0x1101);
5044 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
5046 init_waitqueue_head(&dev_priv
->pending_flip_queue
);
5048 dev_priv
->mm
.interruptible
= true;
5050 mutex_init(&dev_priv
->fb_tracking
.lock
);
5053 void i915_gem_load_cleanup(struct drm_device
*dev
)
5055 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5057 kmem_cache_destroy(dev_priv
->requests
);
5058 kmem_cache_destroy(dev_priv
->vmas
);
5059 kmem_cache_destroy(dev_priv
->objects
);
5062 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
)
5064 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
5066 /* Clean up our request list when the client is going away, so that
5067 * later retire_requests won't dereference our soon-to-be-gone
5070 spin_lock(&file_priv
->mm
.lock
);
5071 while (!list_empty(&file_priv
->mm
.request_list
)) {
5072 struct drm_i915_gem_request
*request
;
5074 request
= list_first_entry(&file_priv
->mm
.request_list
,
5075 struct drm_i915_gem_request
,
5077 list_del(&request
->client_list
);
5078 request
->file_priv
= NULL
;
5080 spin_unlock(&file_priv
->mm
.lock
);
5082 if (!list_empty(&file_priv
->rps
.link
)) {
5083 spin_lock(&to_i915(dev
)->rps
.client_lock
);
5084 list_del(&file_priv
->rps
.link
);
5085 spin_unlock(&to_i915(dev
)->rps
.client_lock
);
5089 int i915_gem_open(struct drm_device
*dev
, struct drm_file
*file
)
5091 struct drm_i915_file_private
*file_priv
;
5094 DRM_DEBUG_DRIVER("\n");
5096 file_priv
= kzalloc(sizeof(*file_priv
), GFP_KERNEL
);
5100 file
->driver_priv
= file_priv
;
5101 file_priv
->dev_priv
= dev
->dev_private
;
5102 file_priv
->file
= file
;
5103 INIT_LIST_HEAD(&file_priv
->rps
.link
);
5105 spin_lock_init(&file_priv
->mm
.lock
);
5106 INIT_LIST_HEAD(&file_priv
->mm
.request_list
);
5108 file_priv
->bsd_ring
= -1;
5110 ret
= i915_gem_context_open(dev
, file
);
5118 * i915_gem_track_fb - update frontbuffer tracking
5119 * @old: current GEM buffer for the frontbuffer slots
5120 * @new: new GEM buffer for the frontbuffer slots
5121 * @frontbuffer_bits: bitmask of frontbuffer slots
5123 * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them
5124 * from @old and setting them in @new. Both @old and @new can be NULL.
5126 void i915_gem_track_fb(struct drm_i915_gem_object
*old
,
5127 struct drm_i915_gem_object
*new,
5128 unsigned frontbuffer_bits
)
5131 WARN_ON(!mutex_is_locked(&old
->base
.dev
->struct_mutex
));
5132 WARN_ON(!(old
->frontbuffer_bits
& frontbuffer_bits
));
5133 old
->frontbuffer_bits
&= ~frontbuffer_bits
;
5137 WARN_ON(!mutex_is_locked(&new->base
.dev
->struct_mutex
));
5138 WARN_ON(new->frontbuffer_bits
& frontbuffer_bits
);
5139 new->frontbuffer_bits
|= frontbuffer_bits
;
5143 /* All the new VM stuff */
5144 u64
i915_gem_obj_offset(struct drm_i915_gem_object
*o
,
5145 struct i915_address_space
*vm
)
5147 struct drm_i915_private
*dev_priv
= o
->base
.dev
->dev_private
;
5148 struct i915_vma
*vma
;
5150 WARN_ON(vm
== &dev_priv
->mm
.aliasing_ppgtt
->base
);
5152 list_for_each_entry(vma
, &o
->vma_list
, obj_link
) {
5154 vma
->ggtt_view
.type
!= I915_GGTT_VIEW_NORMAL
)
5157 return vma
->node
.start
;
5160 WARN(1, "%s vma for this object not found.\n",
5161 i915_is_ggtt(vm
) ? "global" : "ppgtt");
5165 u64
i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object
*o
,
5166 const struct i915_ggtt_view
*view
)
5168 struct i915_vma
*vma
;
5170 list_for_each_entry(vma
, &o
->vma_list
, obj_link
)
5171 if (vma
->is_ggtt
&& i915_ggtt_view_equal(&vma
->ggtt_view
, view
))
5172 return vma
->node
.start
;
5174 WARN(1, "global vma for this object not found. (view=%u)\n", view
->type
);
5178 bool i915_gem_obj_bound(struct drm_i915_gem_object
*o
,
5179 struct i915_address_space
*vm
)
5181 struct i915_vma
*vma
;
5183 list_for_each_entry(vma
, &o
->vma_list
, obj_link
) {
5185 vma
->ggtt_view
.type
!= I915_GGTT_VIEW_NORMAL
)
5187 if (vma
->vm
== vm
&& drm_mm_node_allocated(&vma
->node
))
5194 bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object
*o
,
5195 const struct i915_ggtt_view
*view
)
5197 struct i915_vma
*vma
;
5199 list_for_each_entry(vma
, &o
->vma_list
, obj_link
)
5201 i915_ggtt_view_equal(&vma
->ggtt_view
, view
) &&
5202 drm_mm_node_allocated(&vma
->node
))
5208 bool i915_gem_obj_bound_any(struct drm_i915_gem_object
*o
)
5210 struct i915_vma
*vma
;
5212 list_for_each_entry(vma
, &o
->vma_list
, obj_link
)
5213 if (drm_mm_node_allocated(&vma
->node
))
5219 unsigned long i915_gem_obj_ggtt_size(struct drm_i915_gem_object
*o
)
5221 struct i915_vma
*vma
;
5223 GEM_BUG_ON(list_empty(&o
->vma_list
));
5225 list_for_each_entry(vma
, &o
->vma_list
, obj_link
) {
5227 vma
->ggtt_view
.type
== I915_GGTT_VIEW_NORMAL
)
5228 return vma
->node
.size
;
5234 bool i915_gem_obj_is_pinned(struct drm_i915_gem_object
*obj
)
5236 struct i915_vma
*vma
;
5237 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
)
5238 if (vma
->pin_count
> 0)
5244 /* Like i915_gem_object_get_page(), but mark the returned page dirty */
5246 i915_gem_object_get_dirty_page(struct drm_i915_gem_object
*obj
, int n
)
5250 /* Only default objects have per-page dirty tracking */
5251 if (WARN_ON((obj
->ops
->flags
& I915_GEM_OBJECT_HAS_STRUCT_PAGE
) == 0))
5254 page
= i915_gem_object_get_page(obj
, n
);
5255 set_page_dirty(page
);
5259 /* Allocate a new GEM object and fill it with the supplied data */
5260 struct drm_i915_gem_object
*
5261 i915_gem_object_create_from_data(struct drm_device
*dev
,
5262 const void *data
, size_t size
)
5264 struct drm_i915_gem_object
*obj
;
5265 struct sg_table
*sg
;
5269 obj
= i915_gem_object_create(dev
, round_up(size
, PAGE_SIZE
));
5273 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
5277 ret
= i915_gem_object_get_pages(obj
);
5281 i915_gem_object_pin_pages(obj
);
5283 bytes
= sg_copy_from_buffer(sg
->sgl
, sg
->nents
, (void *)data
, size
);
5284 obj
->dirty
= 1; /* Backing store is now out of date */
5285 i915_gem_object_unpin_pages(obj
);
5287 if (WARN_ON(bytes
!= size
)) {
5288 DRM_ERROR("Incomplete copy, wrote %zu of %zu", bytes
, size
);
5296 drm_gem_object_unreference(&obj
->base
);
5297 return ERR_PTR(ret
);