2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/shmem_fs.h>
35 #include <linux/slab.h>
36 #include <linux/swap.h>
37 #include <linux/pci.h>
39 static __must_check
int i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object
*obj
);
40 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
);
41 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
);
42 static __must_check
int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object
*obj
,
44 bool map_and_fenceable
);
45 static int i915_gem_phys_pwrite(struct drm_device
*dev
,
46 struct drm_i915_gem_object
*obj
,
47 struct drm_i915_gem_pwrite
*args
,
48 struct drm_file
*file
);
49 static void i915_gem_free_object_tail(struct drm_i915_gem_object
*obj
);
51 static void i915_gem_write_fence(struct drm_device
*dev
, int reg
,
52 struct drm_i915_gem_object
*obj
);
53 static void i915_gem_object_update_fence(struct drm_i915_gem_object
*obj
,
54 struct drm_i915_fence_reg
*fence
,
57 static int i915_gem_inactive_shrink(struct shrinker
*shrinker
,
58 struct shrink_control
*sc
);
59 static void i915_gem_object_truncate(struct drm_i915_gem_object
*obj
);
61 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object
*obj
)
64 i915_gem_release_mmap(obj
);
66 /* As we do not have an associated fence register, we will force
67 * a tiling change if we ever need to acquire one.
69 obj
->tiling_changed
= false;
70 obj
->fence_reg
= I915_FENCE_REG_NONE
;
73 /* some bookkeeping */
74 static void i915_gem_info_add_obj(struct drm_i915_private
*dev_priv
,
77 dev_priv
->mm
.object_count
++;
78 dev_priv
->mm
.object_memory
+= size
;
81 static void i915_gem_info_remove_obj(struct drm_i915_private
*dev_priv
,
84 dev_priv
->mm
.object_count
--;
85 dev_priv
->mm
.object_memory
-= size
;
89 i915_gem_wait_for_error(struct drm_device
*dev
)
91 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
92 struct completion
*x
= &dev_priv
->error_completion
;
96 if (!atomic_read(&dev_priv
->mm
.wedged
))
99 ret
= wait_for_completion_interruptible(x
);
103 if (atomic_read(&dev_priv
->mm
.wedged
)) {
104 /* GPU is hung, bump the completion count to account for
105 * the token we just consumed so that we never hit zero and
106 * end up waiting upon a subsequent completion event that
109 spin_lock_irqsave(&x
->wait
.lock
, flags
);
111 spin_unlock_irqrestore(&x
->wait
.lock
, flags
);
116 int i915_mutex_lock_interruptible(struct drm_device
*dev
)
120 ret
= i915_gem_wait_for_error(dev
);
124 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
128 WARN_ON(i915_verify_lists(dev
));
133 i915_gem_object_is_inactive(struct drm_i915_gem_object
*obj
)
135 return obj
->gtt_space
&& !obj
->active
&& obj
->pin_count
== 0;
139 i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
140 struct drm_file
*file
)
142 struct drm_i915_gem_init
*args
= data
;
144 if (args
->gtt_start
>= args
->gtt_end
||
145 (args
->gtt_end
| args
->gtt_start
) & (PAGE_SIZE
- 1))
148 /* GEM with user mode setting was never supported on ilk and later. */
149 if (INTEL_INFO(dev
)->gen
>= 5)
152 mutex_lock(&dev
->struct_mutex
);
153 i915_gem_init_global_gtt(dev
, args
->gtt_start
,
154 args
->gtt_end
, args
->gtt_end
);
155 mutex_unlock(&dev
->struct_mutex
);
161 i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
162 struct drm_file
*file
)
164 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
165 struct drm_i915_gem_get_aperture
*args
= data
;
166 struct drm_i915_gem_object
*obj
;
169 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
173 mutex_lock(&dev
->struct_mutex
);
174 list_for_each_entry(obj
, &dev_priv
->mm
.pinned_list
, mm_list
)
175 pinned
+= obj
->gtt_space
->size
;
176 mutex_unlock(&dev
->struct_mutex
);
178 args
->aper_size
= dev_priv
->mm
.gtt_total
;
179 args
->aper_available_size
= args
->aper_size
- pinned
;
185 i915_gem_create(struct drm_file
*file
,
186 struct drm_device
*dev
,
190 struct drm_i915_gem_object
*obj
;
194 size
= roundup(size
, PAGE_SIZE
);
198 /* Allocate the new object */
199 obj
= i915_gem_alloc_object(dev
, size
);
203 ret
= drm_gem_handle_create(file
, &obj
->base
, &handle
);
205 drm_gem_object_release(&obj
->base
);
206 i915_gem_info_remove_obj(dev
->dev_private
, obj
->base
.size
);
211 /* drop reference from allocate - handle holds it now */
212 drm_gem_object_unreference(&obj
->base
);
213 trace_i915_gem_object_create(obj
);
220 i915_gem_dumb_create(struct drm_file
*file
,
221 struct drm_device
*dev
,
222 struct drm_mode_create_dumb
*args
)
224 /* have to work out size/pitch and return them */
225 args
->pitch
= ALIGN(args
->width
* ((args
->bpp
+ 7) / 8), 64);
226 args
->size
= args
->pitch
* args
->height
;
227 return i915_gem_create(file
, dev
,
228 args
->size
, &args
->handle
);
231 int i915_gem_dumb_destroy(struct drm_file
*file
,
232 struct drm_device
*dev
,
235 return drm_gem_handle_delete(file
, handle
);
239 * Creates a new mm object and returns a handle to it.
242 i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
243 struct drm_file
*file
)
245 struct drm_i915_gem_create
*args
= data
;
246 return i915_gem_create(file
, dev
,
247 args
->size
, &args
->handle
);
250 static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object
*obj
)
252 drm_i915_private_t
*dev_priv
= obj
->base
.dev
->dev_private
;
254 return dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_9_10_17
&&
255 obj
->tiling_mode
!= I915_TILING_NONE
;
259 __copy_to_user_swizzled(char __user
*cpu_vaddr
,
260 const char *gpu_vaddr
, int gpu_offset
,
263 int ret
, cpu_offset
= 0;
266 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
267 int this_length
= min(cacheline_end
- gpu_offset
, length
);
268 int swizzled_gpu_offset
= gpu_offset
^ 64;
270 ret
= __copy_to_user(cpu_vaddr
+ cpu_offset
,
271 gpu_vaddr
+ swizzled_gpu_offset
,
276 cpu_offset
+= this_length
;
277 gpu_offset
+= this_length
;
278 length
-= this_length
;
285 __copy_from_user_swizzled(char __user
*gpu_vaddr
, int gpu_offset
,
286 const char *cpu_vaddr
,
289 int ret
, cpu_offset
= 0;
292 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
293 int this_length
= min(cacheline_end
- gpu_offset
, length
);
294 int swizzled_gpu_offset
= gpu_offset
^ 64;
296 ret
= __copy_from_user(gpu_vaddr
+ swizzled_gpu_offset
,
297 cpu_vaddr
+ cpu_offset
,
302 cpu_offset
+= this_length
;
303 gpu_offset
+= this_length
;
304 length
-= this_length
;
310 /* Per-page copy function for the shmem pread fastpath.
311 * Flushes invalid cachelines before reading the target if
312 * needs_clflush is set. */
314 shmem_pread_fast(struct page
*page
, int shmem_page_offset
, int page_length
,
315 char __user
*user_data
,
316 bool page_do_bit17_swizzling
, bool needs_clflush
)
321 if (unlikely(page_do_bit17_swizzling
))
324 vaddr
= kmap_atomic(page
);
326 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
328 ret
= __copy_to_user_inatomic(user_data
,
329 vaddr
+ shmem_page_offset
,
331 kunmap_atomic(vaddr
);
337 shmem_clflush_swizzled_range(char *addr
, unsigned long length
,
340 if (unlikely(swizzled
)) {
341 unsigned long start
= (unsigned long) addr
;
342 unsigned long end
= (unsigned long) addr
+ length
;
344 /* For swizzling simply ensure that we always flush both
345 * channels. Lame, but simple and it works. Swizzled
346 * pwrite/pread is far from a hotpath - current userspace
347 * doesn't use it at all. */
348 start
= round_down(start
, 128);
349 end
= round_up(end
, 128);
351 drm_clflush_virt_range((void *)start
, end
- start
);
353 drm_clflush_virt_range(addr
, length
);
358 /* Only difference to the fast-path function is that this can handle bit17
359 * and uses non-atomic copy and kmap functions. */
361 shmem_pread_slow(struct page
*page
, int shmem_page_offset
, int page_length
,
362 char __user
*user_data
,
363 bool page_do_bit17_swizzling
, bool needs_clflush
)
370 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
372 page_do_bit17_swizzling
);
374 if (page_do_bit17_swizzling
)
375 ret
= __copy_to_user_swizzled(user_data
,
376 vaddr
, shmem_page_offset
,
379 ret
= __copy_to_user(user_data
,
380 vaddr
+ shmem_page_offset
,
388 i915_gem_shmem_pread(struct drm_device
*dev
,
389 struct drm_i915_gem_object
*obj
,
390 struct drm_i915_gem_pread
*args
,
391 struct drm_file
*file
)
393 struct address_space
*mapping
= obj
->base
.filp
->f_path
.dentry
->d_inode
->i_mapping
;
394 char __user
*user_data
;
397 int shmem_page_offset
, page_length
, ret
= 0;
398 int obj_do_bit17_swizzling
, page_do_bit17_swizzling
;
399 int hit_slowpath
= 0;
401 int needs_clflush
= 0;
404 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
407 obj_do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
409 if (!(obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
)) {
410 /* If we're not in the cpu read domain, set ourself into the gtt
411 * read domain and manually flush cachelines (if required). This
412 * optimizes for the case when the gpu will dirty the data
413 * anyway again before the next pread happens. */
414 if (obj
->cache_level
== I915_CACHE_NONE
)
416 ret
= i915_gem_object_set_to_gtt_domain(obj
, false);
421 offset
= args
->offset
;
426 /* Operation in this page
428 * shmem_page_offset = offset within page in shmem file
429 * page_length = bytes to copy for this page
431 shmem_page_offset
= offset_in_page(offset
);
432 page_length
= remain
;
433 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
434 page_length
= PAGE_SIZE
- shmem_page_offset
;
437 page
= obj
->pages
[offset
>> PAGE_SHIFT
];
440 page
= shmem_read_mapping_page(mapping
, offset
>> PAGE_SHIFT
);
448 page_do_bit17_swizzling
= obj_do_bit17_swizzling
&&
449 (page_to_phys(page
) & (1 << 17)) != 0;
451 ret
= shmem_pread_fast(page
, shmem_page_offset
, page_length
,
452 user_data
, page_do_bit17_swizzling
,
458 page_cache_get(page
);
459 mutex_unlock(&dev
->struct_mutex
);
462 ret
= fault_in_multipages_writeable(user_data
, remain
);
463 /* Userspace is tricking us, but we've already clobbered
464 * its pages with the prefault and promised to write the
465 * data up to the first fault. Hence ignore any errors
466 * and just continue. */
471 ret
= shmem_pread_slow(page
, shmem_page_offset
, page_length
,
472 user_data
, page_do_bit17_swizzling
,
475 mutex_lock(&dev
->struct_mutex
);
476 page_cache_release(page
);
478 mark_page_accessed(page
);
480 page_cache_release(page
);
487 remain
-= page_length
;
488 user_data
+= page_length
;
489 offset
+= page_length
;
494 /* Fixup: Kill any reinstated backing storage pages */
495 if (obj
->madv
== __I915_MADV_PURGED
)
496 i915_gem_object_truncate(obj
);
503 * Reads data from the object referenced by handle.
505 * On error, the contents of *data are undefined.
508 i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
509 struct drm_file
*file
)
511 struct drm_i915_gem_pread
*args
= data
;
512 struct drm_i915_gem_object
*obj
;
518 if (!access_ok(VERIFY_WRITE
,
519 (char __user
*)(uintptr_t)args
->data_ptr
,
523 ret
= i915_mutex_lock_interruptible(dev
);
527 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
528 if (&obj
->base
== NULL
) {
533 /* Bounds check source. */
534 if (args
->offset
> obj
->base
.size
||
535 args
->size
> obj
->base
.size
- args
->offset
) {
540 trace_i915_gem_object_pread(obj
, args
->offset
, args
->size
);
542 ret
= i915_gem_shmem_pread(dev
, obj
, args
, file
);
545 drm_gem_object_unreference(&obj
->base
);
547 mutex_unlock(&dev
->struct_mutex
);
551 /* This is the fast write path which cannot handle
552 * page faults in the source data
556 fast_user_write(struct io_mapping
*mapping
,
557 loff_t page_base
, int page_offset
,
558 char __user
*user_data
,
562 unsigned long unwritten
;
564 vaddr_atomic
= io_mapping_map_atomic_wc(mapping
, page_base
);
565 unwritten
= __copy_from_user_inatomic_nocache(vaddr_atomic
+ page_offset
,
567 io_mapping_unmap_atomic(vaddr_atomic
);
572 * This is the fast pwrite path, where we copy the data directly from the
573 * user into the GTT, uncached.
576 i915_gem_gtt_pwrite_fast(struct drm_device
*dev
,
577 struct drm_i915_gem_object
*obj
,
578 struct drm_i915_gem_pwrite
*args
,
579 struct drm_file
*file
)
581 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
583 loff_t offset
, page_base
;
584 char __user
*user_data
;
585 int page_offset
, page_length
, ret
;
587 ret
= i915_gem_object_pin(obj
, 0, true);
591 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
595 ret
= i915_gem_object_put_fence(obj
);
599 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
602 offset
= obj
->gtt_offset
+ args
->offset
;
605 /* Operation in this page
607 * page_base = page offset within aperture
608 * page_offset = offset within page
609 * page_length = bytes to copy for this page
611 page_base
= offset
& PAGE_MASK
;
612 page_offset
= offset_in_page(offset
);
613 page_length
= remain
;
614 if ((page_offset
+ remain
) > PAGE_SIZE
)
615 page_length
= PAGE_SIZE
- page_offset
;
617 /* If we get a fault while copying data, then (presumably) our
618 * source page isn't available. Return the error and we'll
619 * retry in the slow path.
621 if (fast_user_write(dev_priv
->mm
.gtt_mapping
, page_base
,
622 page_offset
, user_data
, page_length
)) {
627 remain
-= page_length
;
628 user_data
+= page_length
;
629 offset
+= page_length
;
633 i915_gem_object_unpin(obj
);
638 /* Per-page copy function for the shmem pwrite fastpath.
639 * Flushes invalid cachelines before writing to the target if
640 * needs_clflush_before is set and flushes out any written cachelines after
641 * writing if needs_clflush is set. */
643 shmem_pwrite_fast(struct page
*page
, int shmem_page_offset
, int page_length
,
644 char __user
*user_data
,
645 bool page_do_bit17_swizzling
,
646 bool needs_clflush_before
,
647 bool needs_clflush_after
)
652 if (unlikely(page_do_bit17_swizzling
))
655 vaddr
= kmap_atomic(page
);
656 if (needs_clflush_before
)
657 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
659 ret
= __copy_from_user_inatomic_nocache(vaddr
+ shmem_page_offset
,
662 if (needs_clflush_after
)
663 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
665 kunmap_atomic(vaddr
);
670 /* Only difference to the fast-path function is that this can handle bit17
671 * and uses non-atomic copy and kmap functions. */
673 shmem_pwrite_slow(struct page
*page
, int shmem_page_offset
, int page_length
,
674 char __user
*user_data
,
675 bool page_do_bit17_swizzling
,
676 bool needs_clflush_before
,
677 bool needs_clflush_after
)
683 if (unlikely(needs_clflush_before
|| page_do_bit17_swizzling
))
684 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
686 page_do_bit17_swizzling
);
687 if (page_do_bit17_swizzling
)
688 ret
= __copy_from_user_swizzled(vaddr
, shmem_page_offset
,
692 ret
= __copy_from_user(vaddr
+ shmem_page_offset
,
695 if (needs_clflush_after
)
696 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
698 page_do_bit17_swizzling
);
705 i915_gem_shmem_pwrite(struct drm_device
*dev
,
706 struct drm_i915_gem_object
*obj
,
707 struct drm_i915_gem_pwrite
*args
,
708 struct drm_file
*file
)
710 struct address_space
*mapping
= obj
->base
.filp
->f_path
.dentry
->d_inode
->i_mapping
;
713 char __user
*user_data
;
714 int shmem_page_offset
, page_length
, ret
= 0;
715 int obj_do_bit17_swizzling
, page_do_bit17_swizzling
;
716 int hit_slowpath
= 0;
717 int needs_clflush_after
= 0;
718 int needs_clflush_before
= 0;
721 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
724 obj_do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
726 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
727 /* If we're not in the cpu write domain, set ourself into the gtt
728 * write domain and manually flush cachelines (if required). This
729 * optimizes for the case when the gpu will use the data
730 * right away and we therefore have to clflush anyway. */
731 if (obj
->cache_level
== I915_CACHE_NONE
)
732 needs_clflush_after
= 1;
733 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
737 /* Same trick applies for invalidate partially written cachelines before
739 if (!(obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
)
740 && obj
->cache_level
== I915_CACHE_NONE
)
741 needs_clflush_before
= 1;
743 offset
= args
->offset
;
748 int partial_cacheline_write
;
750 /* Operation in this page
752 * shmem_page_offset = offset within page in shmem file
753 * page_length = bytes to copy for this page
755 shmem_page_offset
= offset_in_page(offset
);
757 page_length
= remain
;
758 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
759 page_length
= PAGE_SIZE
- shmem_page_offset
;
761 /* If we don't overwrite a cacheline completely we need to be
762 * careful to have up-to-date data by first clflushing. Don't
763 * overcomplicate things and flush the entire patch. */
764 partial_cacheline_write
= needs_clflush_before
&&
765 ((shmem_page_offset
| page_length
)
766 & (boot_cpu_data
.x86_clflush_size
- 1));
769 page
= obj
->pages
[offset
>> PAGE_SHIFT
];
772 page
= shmem_read_mapping_page(mapping
, offset
>> PAGE_SHIFT
);
780 page_do_bit17_swizzling
= obj_do_bit17_swizzling
&&
781 (page_to_phys(page
) & (1 << 17)) != 0;
783 ret
= shmem_pwrite_fast(page
, shmem_page_offset
, page_length
,
784 user_data
, page_do_bit17_swizzling
,
785 partial_cacheline_write
,
786 needs_clflush_after
);
791 page_cache_get(page
);
792 mutex_unlock(&dev
->struct_mutex
);
794 ret
= shmem_pwrite_slow(page
, shmem_page_offset
, page_length
,
795 user_data
, page_do_bit17_swizzling
,
796 partial_cacheline_write
,
797 needs_clflush_after
);
799 mutex_lock(&dev
->struct_mutex
);
800 page_cache_release(page
);
802 set_page_dirty(page
);
803 mark_page_accessed(page
);
805 page_cache_release(page
);
812 remain
-= page_length
;
813 user_data
+= page_length
;
814 offset
+= page_length
;
819 /* Fixup: Kill any reinstated backing storage pages */
820 if (obj
->madv
== __I915_MADV_PURGED
)
821 i915_gem_object_truncate(obj
);
822 /* and flush dirty cachelines in case the object isn't in the cpu write
824 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
825 i915_gem_clflush_object(obj
);
826 intel_gtt_chipset_flush();
830 if (needs_clflush_after
)
831 intel_gtt_chipset_flush();
837 * Writes data to the object referenced by handle.
839 * On error, the contents of the buffer that were to be modified are undefined.
842 i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
843 struct drm_file
*file
)
845 struct drm_i915_gem_pwrite
*args
= data
;
846 struct drm_i915_gem_object
*obj
;
852 if (!access_ok(VERIFY_READ
,
853 (char __user
*)(uintptr_t)args
->data_ptr
,
857 ret
= fault_in_multipages_readable((char __user
*)(uintptr_t)args
->data_ptr
,
862 ret
= i915_mutex_lock_interruptible(dev
);
866 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
867 if (&obj
->base
== NULL
) {
872 /* Bounds check destination. */
873 if (args
->offset
> obj
->base
.size
||
874 args
->size
> obj
->base
.size
- args
->offset
) {
879 trace_i915_gem_object_pwrite(obj
, args
->offset
, args
->size
);
882 /* We can only do the GTT pwrite on untiled buffers, as otherwise
883 * it would end up going through the fenced access, and we'll get
884 * different detiling behavior between reading and writing.
885 * pread/pwrite currently are reading and writing from the CPU
886 * perspective, requiring manual detiling by the client.
889 ret
= i915_gem_phys_pwrite(dev
, obj
, args
, file
);
893 if (obj
->gtt_space
&&
894 obj
->cache_level
== I915_CACHE_NONE
&&
895 obj
->tiling_mode
== I915_TILING_NONE
&&
896 obj
->map_and_fenceable
&&
897 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
898 ret
= i915_gem_gtt_pwrite_fast(dev
, obj
, args
, file
);
899 /* Note that the gtt paths might fail with non-page-backed user
900 * pointers (e.g. gtt mappings when moving data between
901 * textures). Fallback to the shmem path in that case. */
905 ret
= i915_gem_shmem_pwrite(dev
, obj
, args
, file
);
908 drm_gem_object_unreference(&obj
->base
);
910 mutex_unlock(&dev
->struct_mutex
);
915 * Called when user space prepares to use an object with the CPU, either
916 * through the mmap ioctl's mapping or a GTT mapping.
919 i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
920 struct drm_file
*file
)
922 struct drm_i915_gem_set_domain
*args
= data
;
923 struct drm_i915_gem_object
*obj
;
924 uint32_t read_domains
= args
->read_domains
;
925 uint32_t write_domain
= args
->write_domain
;
928 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
931 /* Only handle setting domains to types used by the CPU. */
932 if (write_domain
& I915_GEM_GPU_DOMAINS
)
935 if (read_domains
& I915_GEM_GPU_DOMAINS
)
938 /* Having something in the write domain implies it's in the read
939 * domain, and only that read domain. Enforce that in the request.
941 if (write_domain
!= 0 && read_domains
!= write_domain
)
944 ret
= i915_mutex_lock_interruptible(dev
);
948 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
949 if (&obj
->base
== NULL
) {
954 if (read_domains
& I915_GEM_DOMAIN_GTT
) {
955 ret
= i915_gem_object_set_to_gtt_domain(obj
, write_domain
!= 0);
957 /* Silently promote "you're not bound, there was nothing to do"
958 * to success, since the client was just asking us to
959 * make sure everything was done.
964 ret
= i915_gem_object_set_to_cpu_domain(obj
, write_domain
!= 0);
967 drm_gem_object_unreference(&obj
->base
);
969 mutex_unlock(&dev
->struct_mutex
);
974 * Called when user space has done writes to this buffer
977 i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
978 struct drm_file
*file
)
980 struct drm_i915_gem_sw_finish
*args
= data
;
981 struct drm_i915_gem_object
*obj
;
984 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
987 ret
= i915_mutex_lock_interruptible(dev
);
991 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
992 if (&obj
->base
== NULL
) {
997 /* Pinned buffers may be scanout, so flush the cache */
999 i915_gem_object_flush_cpu_write_domain(obj
);
1001 drm_gem_object_unreference(&obj
->base
);
1003 mutex_unlock(&dev
->struct_mutex
);
1008 * Maps the contents of an object, returning the address it is mapped
1011 * While the mapping holds a reference on the contents of the object, it doesn't
1012 * imply a ref on the object itself.
1015 i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1016 struct drm_file
*file
)
1018 struct drm_i915_gem_mmap
*args
= data
;
1019 struct drm_gem_object
*obj
;
1022 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1025 obj
= drm_gem_object_lookup(dev
, file
, args
->handle
);
1029 addr
= vm_mmap(obj
->filp
, 0, args
->size
,
1030 PROT_READ
| PROT_WRITE
, MAP_SHARED
,
1032 drm_gem_object_unreference_unlocked(obj
);
1033 if (IS_ERR((void *)addr
))
1036 args
->addr_ptr
= (uint64_t) addr
;
1042 * i915_gem_fault - fault a page into the GTT
1043 * vma: VMA in question
1046 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1047 * from userspace. The fault handler takes care of binding the object to
1048 * the GTT (if needed), allocating and programming a fence register (again,
1049 * only if needed based on whether the old reg is still valid or the object
1050 * is tiled) and inserting a new PTE into the faulting process.
1052 * Note that the faulting process may involve evicting existing objects
1053 * from the GTT and/or fence registers to make room. So performance may
1054 * suffer if the GTT working set is large or there are few fence registers
1057 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
)
1059 struct drm_i915_gem_object
*obj
= to_intel_bo(vma
->vm_private_data
);
1060 struct drm_device
*dev
= obj
->base
.dev
;
1061 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1062 pgoff_t page_offset
;
1065 bool write
= !!(vmf
->flags
& FAULT_FLAG_WRITE
);
1067 /* We don't use vmf->pgoff since that has the fake offset */
1068 page_offset
= ((unsigned long)vmf
->virtual_address
- vma
->vm_start
) >>
1071 ret
= i915_mutex_lock_interruptible(dev
);
1075 trace_i915_gem_object_fault(obj
, page_offset
, true, write
);
1077 /* Now bind it into the GTT if needed */
1078 if (!obj
->map_and_fenceable
) {
1079 ret
= i915_gem_object_unbind(obj
);
1083 if (!obj
->gtt_space
) {
1084 ret
= i915_gem_object_bind_to_gtt(obj
, 0, true);
1088 ret
= i915_gem_object_set_to_gtt_domain(obj
, write
);
1093 if (!obj
->has_global_gtt_mapping
)
1094 i915_gem_gtt_bind_object(obj
, obj
->cache_level
);
1096 ret
= i915_gem_object_get_fence(obj
);
1100 if (i915_gem_object_is_inactive(obj
))
1101 list_move_tail(&obj
->mm_list
, &dev_priv
->mm
.inactive_list
);
1103 obj
->fault_mappable
= true;
1105 pfn
= ((dev
->agp
->base
+ obj
->gtt_offset
) >> PAGE_SHIFT
) +
1108 /* Finally, remap it using the new GTT offset */
1109 ret
= vm_insert_pfn(vma
, (unsigned long)vmf
->virtual_address
, pfn
);
1111 mutex_unlock(&dev
->struct_mutex
);
1116 /* Give the error handler a chance to run and move the
1117 * objects off the GPU active list. Next time we service the
1118 * fault, we should be able to transition the page into the
1119 * GTT without touching the GPU (and so avoid further
1120 * EIO/EGAIN). If the GPU is wedged, then there is no issue
1121 * with coherency, just lost writes.
1127 return VM_FAULT_NOPAGE
;
1129 return VM_FAULT_OOM
;
1131 return VM_FAULT_SIGBUS
;
1136 * i915_gem_release_mmap - remove physical page mappings
1137 * @obj: obj in question
1139 * Preserve the reservation of the mmapping with the DRM core code, but
1140 * relinquish ownership of the pages back to the system.
1142 * It is vital that we remove the page mapping if we have mapped a tiled
1143 * object through the GTT and then lose the fence register due to
1144 * resource pressure. Similarly if the object has been moved out of the
1145 * aperture, than pages mapped into userspace must be revoked. Removing the
1146 * mapping will then trigger a page fault on the next user access, allowing
1147 * fixup by i915_gem_fault().
1150 i915_gem_release_mmap(struct drm_i915_gem_object
*obj
)
1152 if (!obj
->fault_mappable
)
1155 if (obj
->base
.dev
->dev_mapping
)
1156 unmap_mapping_range(obj
->base
.dev
->dev_mapping
,
1157 (loff_t
)obj
->base
.map_list
.hash
.key
<<PAGE_SHIFT
,
1160 obj
->fault_mappable
= false;
1164 i915_gem_get_gtt_size(struct drm_device
*dev
, uint32_t size
, int tiling_mode
)
1168 if (INTEL_INFO(dev
)->gen
>= 4 ||
1169 tiling_mode
== I915_TILING_NONE
)
1172 /* Previous chips need a power-of-two fence region when tiling */
1173 if (INTEL_INFO(dev
)->gen
== 3)
1174 gtt_size
= 1024*1024;
1176 gtt_size
= 512*1024;
1178 while (gtt_size
< size
)
1185 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1186 * @obj: object to check
1188 * Return the required GTT alignment for an object, taking into account
1189 * potential fence register mapping.
1192 i915_gem_get_gtt_alignment(struct drm_device
*dev
,
1197 * Minimum alignment is 4k (GTT page size), but might be greater
1198 * if a fence register is needed for the object.
1200 if (INTEL_INFO(dev
)->gen
>= 4 ||
1201 tiling_mode
== I915_TILING_NONE
)
1205 * Previous chips need to be aligned to the size of the smallest
1206 * fence register that can contain the object.
1208 return i915_gem_get_gtt_size(dev
, size
, tiling_mode
);
1212 * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an
1215 * @size: size of the object
1216 * @tiling_mode: tiling mode of the object
1218 * Return the required GTT alignment for an object, only taking into account
1219 * unfenced tiled surface requirements.
1222 i915_gem_get_unfenced_gtt_alignment(struct drm_device
*dev
,
1227 * Minimum alignment is 4k (GTT page size) for sane hw.
1229 if (INTEL_INFO(dev
)->gen
>= 4 || IS_G33(dev
) ||
1230 tiling_mode
== I915_TILING_NONE
)
1233 /* Previous hardware however needs to be aligned to a power-of-two
1234 * tile height. The simplest method for determining this is to reuse
1235 * the power-of-tile object size.
1237 return i915_gem_get_gtt_size(dev
, size
, tiling_mode
);
1241 i915_gem_mmap_gtt(struct drm_file
*file
,
1242 struct drm_device
*dev
,
1246 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1247 struct drm_i915_gem_object
*obj
;
1250 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1253 ret
= i915_mutex_lock_interruptible(dev
);
1257 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, handle
));
1258 if (&obj
->base
== NULL
) {
1263 if (obj
->base
.size
> dev_priv
->mm
.gtt_mappable_end
) {
1268 if (obj
->madv
!= I915_MADV_WILLNEED
) {
1269 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1274 if (!obj
->base
.map_list
.map
) {
1275 ret
= drm_gem_create_mmap_offset(&obj
->base
);
1280 *offset
= (u64
)obj
->base
.map_list
.hash
.key
<< PAGE_SHIFT
;
1283 drm_gem_object_unreference(&obj
->base
);
1285 mutex_unlock(&dev
->struct_mutex
);
1290 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1292 * @data: GTT mapping ioctl data
1293 * @file: GEM object info
1295 * Simply returns the fake offset to userspace so it can mmap it.
1296 * The mmap call will end up in drm_gem_mmap(), which will set things
1297 * up so we can get faults in the handler above.
1299 * The fault handler will take care of binding the object into the GTT
1300 * (since it may have been evicted to make room for something), allocating
1301 * a fence register, and mapping the appropriate aperture address into
1305 i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
1306 struct drm_file
*file
)
1308 struct drm_i915_gem_mmap_gtt
*args
= data
;
1310 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1313 return i915_gem_mmap_gtt(file
, dev
, args
->handle
, &args
->offset
);
1318 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object
*obj
,
1322 struct address_space
*mapping
;
1323 struct inode
*inode
;
1326 /* Get the list of pages out of our struct file. They'll be pinned
1327 * at this point until we release them.
1329 page_count
= obj
->base
.size
/ PAGE_SIZE
;
1330 BUG_ON(obj
->pages
!= NULL
);
1331 obj
->pages
= drm_malloc_ab(page_count
, sizeof(struct page
*));
1332 if (obj
->pages
== NULL
)
1335 inode
= obj
->base
.filp
->f_path
.dentry
->d_inode
;
1336 mapping
= inode
->i_mapping
;
1337 gfpmask
|= mapping_gfp_mask(mapping
);
1339 for (i
= 0; i
< page_count
; i
++) {
1340 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfpmask
);
1344 obj
->pages
[i
] = page
;
1347 if (i915_gem_object_needs_bit17_swizzle(obj
))
1348 i915_gem_object_do_bit_17_swizzle(obj
);
1354 page_cache_release(obj
->pages
[i
]);
1356 drm_free_large(obj
->pages
);
1358 return PTR_ERR(page
);
1362 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object
*obj
)
1364 int page_count
= obj
->base
.size
/ PAGE_SIZE
;
1367 BUG_ON(obj
->madv
== __I915_MADV_PURGED
);
1369 if (i915_gem_object_needs_bit17_swizzle(obj
))
1370 i915_gem_object_save_bit_17_swizzle(obj
);
1372 if (obj
->madv
== I915_MADV_DONTNEED
)
1375 for (i
= 0; i
< page_count
; i
++) {
1377 set_page_dirty(obj
->pages
[i
]);
1379 if (obj
->madv
== I915_MADV_WILLNEED
)
1380 mark_page_accessed(obj
->pages
[i
]);
1382 page_cache_release(obj
->pages
[i
]);
1386 drm_free_large(obj
->pages
);
1391 i915_gem_object_move_to_active(struct drm_i915_gem_object
*obj
,
1392 struct intel_ring_buffer
*ring
,
1395 struct drm_device
*dev
= obj
->base
.dev
;
1396 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1398 BUG_ON(ring
== NULL
);
1401 /* Add a reference if we're newly entering the active list. */
1403 drm_gem_object_reference(&obj
->base
);
1407 /* Move from whatever list we were on to the tail of execution. */
1408 list_move_tail(&obj
->mm_list
, &dev_priv
->mm
.active_list
);
1409 list_move_tail(&obj
->ring_list
, &ring
->active_list
);
1411 obj
->last_rendering_seqno
= seqno
;
1413 if (obj
->fenced_gpu_access
) {
1414 obj
->last_fenced_seqno
= seqno
;
1416 /* Bump MRU to take account of the delayed flush */
1417 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
1418 struct drm_i915_fence_reg
*reg
;
1420 reg
= &dev_priv
->fence_regs
[obj
->fence_reg
];
1421 list_move_tail(®
->lru_list
,
1422 &dev_priv
->mm
.fence_list
);
1428 i915_gem_object_move_off_active(struct drm_i915_gem_object
*obj
)
1430 list_del_init(&obj
->ring_list
);
1431 obj
->last_rendering_seqno
= 0;
1432 obj
->last_fenced_seqno
= 0;
1436 i915_gem_object_move_to_flushing(struct drm_i915_gem_object
*obj
)
1438 struct drm_device
*dev
= obj
->base
.dev
;
1439 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1441 BUG_ON(!obj
->active
);
1442 list_move_tail(&obj
->mm_list
, &dev_priv
->mm
.flushing_list
);
1444 i915_gem_object_move_off_active(obj
);
1448 i915_gem_object_move_to_inactive(struct drm_i915_gem_object
*obj
)
1450 struct drm_device
*dev
= obj
->base
.dev
;
1451 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1453 if (obj
->pin_count
!= 0)
1454 list_move_tail(&obj
->mm_list
, &dev_priv
->mm
.pinned_list
);
1456 list_move_tail(&obj
->mm_list
, &dev_priv
->mm
.inactive_list
);
1458 BUG_ON(!list_empty(&obj
->gpu_write_list
));
1459 BUG_ON(!obj
->active
);
1462 i915_gem_object_move_off_active(obj
);
1463 obj
->fenced_gpu_access
= false;
1466 obj
->pending_gpu_write
= false;
1467 drm_gem_object_unreference(&obj
->base
);
1469 WARN_ON(i915_verify_lists(dev
));
1472 /* Immediately discard the backing storage */
1474 i915_gem_object_truncate(struct drm_i915_gem_object
*obj
)
1476 struct inode
*inode
;
1478 /* Our goal here is to return as much of the memory as
1479 * is possible back to the system as we are called from OOM.
1480 * To do this we must instruct the shmfs to drop all of its
1481 * backing pages, *now*.
1483 inode
= obj
->base
.filp
->f_path
.dentry
->d_inode
;
1484 shmem_truncate_range(inode
, 0, (loff_t
)-1);
1486 if (obj
->base
.map_list
.map
)
1487 drm_gem_free_mmap_offset(&obj
->base
);
1489 obj
->madv
= __I915_MADV_PURGED
;
1493 i915_gem_object_is_purgeable(struct drm_i915_gem_object
*obj
)
1495 return obj
->madv
== I915_MADV_DONTNEED
;
1499 i915_gem_process_flushing_list(struct intel_ring_buffer
*ring
,
1500 uint32_t flush_domains
)
1502 struct drm_i915_gem_object
*obj
, *next
;
1504 list_for_each_entry_safe(obj
, next
,
1505 &ring
->gpu_write_list
,
1507 if (obj
->base
.write_domain
& flush_domains
) {
1508 uint32_t old_write_domain
= obj
->base
.write_domain
;
1510 obj
->base
.write_domain
= 0;
1511 list_del_init(&obj
->gpu_write_list
);
1512 i915_gem_object_move_to_active(obj
, ring
,
1513 i915_gem_next_request_seqno(ring
));
1515 trace_i915_gem_object_change_domain(obj
,
1516 obj
->base
.read_domains
,
1523 i915_gem_get_seqno(struct drm_device
*dev
)
1525 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1526 u32 seqno
= dev_priv
->next_seqno
;
1528 /* reserve 0 for non-seqno */
1529 if (++dev_priv
->next_seqno
== 0)
1530 dev_priv
->next_seqno
= 1;
1536 i915_gem_next_request_seqno(struct intel_ring_buffer
*ring
)
1538 if (ring
->outstanding_lazy_request
== 0)
1539 ring
->outstanding_lazy_request
= i915_gem_get_seqno(ring
->dev
);
1541 return ring
->outstanding_lazy_request
;
1545 i915_add_request(struct intel_ring_buffer
*ring
,
1546 struct drm_file
*file
,
1547 struct drm_i915_gem_request
*request
)
1549 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
1551 u32 request_ring_position
;
1555 BUG_ON(request
== NULL
);
1556 seqno
= i915_gem_next_request_seqno(ring
);
1558 /* Record the position of the start of the request so that
1559 * should we detect the updated seqno part-way through the
1560 * GPU processing the request, we never over-estimate the
1561 * position of the head.
1563 request_ring_position
= intel_ring_get_tail(ring
);
1565 ret
= ring
->add_request(ring
, &seqno
);
1569 trace_i915_gem_request_add(ring
, seqno
);
1571 request
->seqno
= seqno
;
1572 request
->ring
= ring
;
1573 request
->tail
= request_ring_position
;
1574 request
->emitted_jiffies
= jiffies
;
1575 was_empty
= list_empty(&ring
->request_list
);
1576 list_add_tail(&request
->list
, &ring
->request_list
);
1579 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
1581 spin_lock(&file_priv
->mm
.lock
);
1582 request
->file_priv
= file_priv
;
1583 list_add_tail(&request
->client_list
,
1584 &file_priv
->mm
.request_list
);
1585 spin_unlock(&file_priv
->mm
.lock
);
1588 ring
->outstanding_lazy_request
= 0;
1590 if (!dev_priv
->mm
.suspended
) {
1591 if (i915_enable_hangcheck
) {
1592 mod_timer(&dev_priv
->hangcheck_timer
,
1594 msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD
));
1597 queue_delayed_work(dev_priv
->wq
,
1598 &dev_priv
->mm
.retire_work
, HZ
);
1604 i915_gem_request_remove_from_client(struct drm_i915_gem_request
*request
)
1606 struct drm_i915_file_private
*file_priv
= request
->file_priv
;
1611 spin_lock(&file_priv
->mm
.lock
);
1612 if (request
->file_priv
) {
1613 list_del(&request
->client_list
);
1614 request
->file_priv
= NULL
;
1616 spin_unlock(&file_priv
->mm
.lock
);
1619 static void i915_gem_reset_ring_lists(struct drm_i915_private
*dev_priv
,
1620 struct intel_ring_buffer
*ring
)
1622 while (!list_empty(&ring
->request_list
)) {
1623 struct drm_i915_gem_request
*request
;
1625 request
= list_first_entry(&ring
->request_list
,
1626 struct drm_i915_gem_request
,
1629 list_del(&request
->list
);
1630 i915_gem_request_remove_from_client(request
);
1634 while (!list_empty(&ring
->active_list
)) {
1635 struct drm_i915_gem_object
*obj
;
1637 obj
= list_first_entry(&ring
->active_list
,
1638 struct drm_i915_gem_object
,
1641 obj
->base
.write_domain
= 0;
1642 list_del_init(&obj
->gpu_write_list
);
1643 i915_gem_object_move_to_inactive(obj
);
1647 static void i915_gem_reset_fences(struct drm_device
*dev
)
1649 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1652 for (i
= 0; i
< dev_priv
->num_fence_regs
; i
++) {
1653 struct drm_i915_fence_reg
*reg
= &dev_priv
->fence_regs
[i
];
1655 i915_gem_write_fence(dev
, i
, NULL
);
1658 i915_gem_object_fence_lost(reg
->obj
);
1662 INIT_LIST_HEAD(®
->lru_list
);
1665 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
1668 void i915_gem_reset(struct drm_device
*dev
)
1670 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1671 struct drm_i915_gem_object
*obj
;
1674 for (i
= 0; i
< I915_NUM_RINGS
; i
++)
1675 i915_gem_reset_ring_lists(dev_priv
, &dev_priv
->ring
[i
]);
1677 /* Remove anything from the flushing lists. The GPU cache is likely
1678 * to be lost on reset along with the data, so simply move the
1679 * lost bo to the inactive list.
1681 while (!list_empty(&dev_priv
->mm
.flushing_list
)) {
1682 obj
= list_first_entry(&dev_priv
->mm
.flushing_list
,
1683 struct drm_i915_gem_object
,
1686 obj
->base
.write_domain
= 0;
1687 list_del_init(&obj
->gpu_write_list
);
1688 i915_gem_object_move_to_inactive(obj
);
1691 /* Move everything out of the GPU domains to ensure we do any
1692 * necessary invalidation upon reuse.
1694 list_for_each_entry(obj
,
1695 &dev_priv
->mm
.inactive_list
,
1698 obj
->base
.read_domains
&= ~I915_GEM_GPU_DOMAINS
;
1701 /* The fence registers are invalidated so clear them out */
1702 i915_gem_reset_fences(dev
);
1706 * This function clears the request list as sequence numbers are passed.
1709 i915_gem_retire_requests_ring(struct intel_ring_buffer
*ring
)
1714 if (list_empty(&ring
->request_list
))
1717 WARN_ON(i915_verify_lists(ring
->dev
));
1719 seqno
= ring
->get_seqno(ring
);
1721 for (i
= 0; i
< ARRAY_SIZE(ring
->sync_seqno
); i
++)
1722 if (seqno
>= ring
->sync_seqno
[i
])
1723 ring
->sync_seqno
[i
] = 0;
1725 while (!list_empty(&ring
->request_list
)) {
1726 struct drm_i915_gem_request
*request
;
1728 request
= list_first_entry(&ring
->request_list
,
1729 struct drm_i915_gem_request
,
1732 if (!i915_seqno_passed(seqno
, request
->seqno
))
1735 trace_i915_gem_request_retire(ring
, request
->seqno
);
1736 /* We know the GPU must have read the request to have
1737 * sent us the seqno + interrupt, so use the position
1738 * of tail of the request to update the last known position
1741 ring
->last_retired_head
= request
->tail
;
1743 list_del(&request
->list
);
1744 i915_gem_request_remove_from_client(request
);
1748 /* Move any buffers on the active list that are no longer referenced
1749 * by the ringbuffer to the flushing/inactive lists as appropriate.
1751 while (!list_empty(&ring
->active_list
)) {
1752 struct drm_i915_gem_object
*obj
;
1754 obj
= list_first_entry(&ring
->active_list
,
1755 struct drm_i915_gem_object
,
1758 if (!i915_seqno_passed(seqno
, obj
->last_rendering_seqno
))
1761 if (obj
->base
.write_domain
!= 0)
1762 i915_gem_object_move_to_flushing(obj
);
1764 i915_gem_object_move_to_inactive(obj
);
1767 if (unlikely(ring
->trace_irq_seqno
&&
1768 i915_seqno_passed(seqno
, ring
->trace_irq_seqno
))) {
1769 ring
->irq_put(ring
);
1770 ring
->trace_irq_seqno
= 0;
1773 WARN_ON(i915_verify_lists(ring
->dev
));
1777 i915_gem_retire_requests(struct drm_device
*dev
)
1779 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1782 if (!list_empty(&dev_priv
->mm
.deferred_free_list
)) {
1783 struct drm_i915_gem_object
*obj
, *next
;
1785 /* We must be careful that during unbind() we do not
1786 * accidentally infinitely recurse into retire requests.
1788 * retire -> free -> unbind -> wait -> retire_ring
1790 list_for_each_entry_safe(obj
, next
,
1791 &dev_priv
->mm
.deferred_free_list
,
1793 i915_gem_free_object_tail(obj
);
1796 for (i
= 0; i
< I915_NUM_RINGS
; i
++)
1797 i915_gem_retire_requests_ring(&dev_priv
->ring
[i
]);
1801 i915_gem_retire_work_handler(struct work_struct
*work
)
1803 drm_i915_private_t
*dev_priv
;
1804 struct drm_device
*dev
;
1808 dev_priv
= container_of(work
, drm_i915_private_t
,
1809 mm
.retire_work
.work
);
1810 dev
= dev_priv
->dev
;
1812 /* Come back later if the device is busy... */
1813 if (!mutex_trylock(&dev
->struct_mutex
)) {
1814 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, HZ
);
1818 i915_gem_retire_requests(dev
);
1820 /* Send a periodic flush down the ring so we don't hold onto GEM
1821 * objects indefinitely.
1824 for (i
= 0; i
< I915_NUM_RINGS
; i
++) {
1825 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[i
];
1827 if (!list_empty(&ring
->gpu_write_list
)) {
1828 struct drm_i915_gem_request
*request
;
1831 ret
= i915_gem_flush_ring(ring
,
1832 0, I915_GEM_GPU_DOMAINS
);
1833 request
= kzalloc(sizeof(*request
), GFP_KERNEL
);
1834 if (ret
|| request
== NULL
||
1835 i915_add_request(ring
, NULL
, request
))
1839 idle
&= list_empty(&ring
->request_list
);
1842 if (!dev_priv
->mm
.suspended
&& !idle
)
1843 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, HZ
);
1845 mutex_unlock(&dev
->struct_mutex
);
1849 * Waits for a sequence number to be signaled, and cleans up the
1850 * request and object lists appropriately for that event.
1853 i915_wait_request(struct intel_ring_buffer
*ring
,
1857 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
1863 if (atomic_read(&dev_priv
->mm
.wedged
)) {
1864 struct completion
*x
= &dev_priv
->error_completion
;
1865 bool recovery_complete
;
1866 unsigned long flags
;
1868 /* Give the error handler a chance to run. */
1869 spin_lock_irqsave(&x
->wait
.lock
, flags
);
1870 recovery_complete
= x
->done
> 0;
1871 spin_unlock_irqrestore(&x
->wait
.lock
, flags
);
1873 return recovery_complete
? -EIO
: -EAGAIN
;
1876 if (seqno
== ring
->outstanding_lazy_request
) {
1877 struct drm_i915_gem_request
*request
;
1879 request
= kzalloc(sizeof(*request
), GFP_KERNEL
);
1880 if (request
== NULL
)
1883 ret
= i915_add_request(ring
, NULL
, request
);
1889 seqno
= request
->seqno
;
1892 if (!i915_seqno_passed(ring
->get_seqno(ring
), seqno
)) {
1893 if (HAS_PCH_SPLIT(ring
->dev
))
1894 ier
= I915_READ(DEIER
) | I915_READ(GTIER
);
1895 else if (IS_VALLEYVIEW(ring
->dev
))
1896 ier
= I915_READ(GTIER
) | I915_READ(VLV_IER
);
1898 ier
= I915_READ(IER
);
1900 DRM_ERROR("something (likely vbetool) disabled "
1901 "interrupts, re-enabling\n");
1902 ring
->dev
->driver
->irq_preinstall(ring
->dev
);
1903 ring
->dev
->driver
->irq_postinstall(ring
->dev
);
1906 trace_i915_gem_request_wait_begin(ring
, seqno
);
1908 ring
->waiting_seqno
= seqno
;
1909 if (ring
->irq_get(ring
)) {
1910 if (dev_priv
->mm
.interruptible
)
1911 ret
= wait_event_interruptible(ring
->irq_queue
,
1912 i915_seqno_passed(ring
->get_seqno(ring
), seqno
)
1913 || atomic_read(&dev_priv
->mm
.wedged
));
1915 wait_event(ring
->irq_queue
,
1916 i915_seqno_passed(ring
->get_seqno(ring
), seqno
)
1917 || atomic_read(&dev_priv
->mm
.wedged
));
1919 ring
->irq_put(ring
);
1920 } else if (wait_for_atomic(i915_seqno_passed(ring
->get_seqno(ring
),
1922 atomic_read(&dev_priv
->mm
.wedged
), 3000))
1924 ring
->waiting_seqno
= 0;
1926 trace_i915_gem_request_wait_end(ring
, seqno
);
1928 if (atomic_read(&dev_priv
->mm
.wedged
))
1931 /* Directly dispatch request retiring. While we have the work queue
1932 * to handle this, the waiter on a request often wants an associated
1933 * buffer to have made it to the inactive list, and we would need
1934 * a separate wait queue to handle that.
1936 if (ret
== 0 && do_retire
)
1937 i915_gem_retire_requests_ring(ring
);
1943 * Ensures that all rendering to the object has completed and the object is
1944 * safe to unbind from the GTT or access from the CPU.
1947 i915_gem_object_wait_rendering(struct drm_i915_gem_object
*obj
)
1951 /* This function only exists to support waiting for existing rendering,
1952 * not for emitting required flushes.
1954 BUG_ON((obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
) != 0);
1956 /* If there is rendering queued on the buffer being evicted, wait for
1960 ret
= i915_wait_request(obj
->ring
, obj
->last_rendering_seqno
,
1970 * i915_gem_object_sync - sync an object to a ring.
1972 * @obj: object which may be in use on another ring.
1973 * @to: ring we wish to use the object on. May be NULL.
1975 * This code is meant to abstract object synchronization with the GPU.
1976 * Calling with NULL implies synchronizing the object with the CPU
1977 * rather than a particular GPU ring.
1979 * Returns 0 if successful, else propagates up the lower layer error.
1982 i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
1983 struct intel_ring_buffer
*to
)
1985 struct intel_ring_buffer
*from
= obj
->ring
;
1989 if (from
== NULL
|| to
== from
)
1992 if (to
== NULL
|| !i915_semaphore_is_enabled(obj
->base
.dev
))
1993 return i915_gem_object_wait_rendering(obj
);
1995 idx
= intel_ring_sync_index(from
, to
);
1997 seqno
= obj
->last_rendering_seqno
;
1998 if (seqno
<= from
->sync_seqno
[idx
])
2001 if (seqno
== from
->outstanding_lazy_request
) {
2002 struct drm_i915_gem_request
*request
;
2004 request
= kzalloc(sizeof(*request
), GFP_KERNEL
);
2005 if (request
== NULL
)
2008 ret
= i915_add_request(from
, NULL
, request
);
2014 seqno
= request
->seqno
;
2018 ret
= to
->sync_to(to
, from
, seqno
);
2020 from
->sync_seqno
[idx
] = seqno
;
2025 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object
*obj
)
2027 u32 old_write_domain
, old_read_domains
;
2029 /* Act a barrier for all accesses through the GTT */
2032 /* Force a pagefault for domain tracking on next user access */
2033 i915_gem_release_mmap(obj
);
2035 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
) == 0)
2038 old_read_domains
= obj
->base
.read_domains
;
2039 old_write_domain
= obj
->base
.write_domain
;
2041 obj
->base
.read_domains
&= ~I915_GEM_DOMAIN_GTT
;
2042 obj
->base
.write_domain
&= ~I915_GEM_DOMAIN_GTT
;
2044 trace_i915_gem_object_change_domain(obj
,
2050 * Unbinds an object from the GTT aperture.
2053 i915_gem_object_unbind(struct drm_i915_gem_object
*obj
)
2055 drm_i915_private_t
*dev_priv
= obj
->base
.dev
->dev_private
;
2058 if (obj
->gtt_space
== NULL
)
2061 if (obj
->pin_count
!= 0) {
2062 DRM_ERROR("Attempting to unbind pinned buffer\n");
2066 ret
= i915_gem_object_finish_gpu(obj
);
2067 if (ret
== -ERESTARTSYS
)
2069 /* Continue on if we fail due to EIO, the GPU is hung so we
2070 * should be safe and we need to cleanup or else we might
2071 * cause memory corruption through use-after-free.
2074 i915_gem_object_finish_gtt(obj
);
2076 /* Move the object to the CPU domain to ensure that
2077 * any possible CPU writes while it's not in the GTT
2078 * are flushed when we go to remap it.
2081 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
2082 if (ret
== -ERESTARTSYS
)
2085 /* In the event of a disaster, abandon all caches and
2086 * hope for the best.
2088 i915_gem_clflush_object(obj
);
2089 obj
->base
.read_domains
= obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
2092 /* release the fence reg _after_ flushing */
2093 ret
= i915_gem_object_put_fence(obj
);
2094 if (ret
== -ERESTARTSYS
)
2097 trace_i915_gem_object_unbind(obj
);
2099 if (obj
->has_global_gtt_mapping
)
2100 i915_gem_gtt_unbind_object(obj
);
2101 if (obj
->has_aliasing_ppgtt_mapping
) {
2102 i915_ppgtt_unbind_object(dev_priv
->mm
.aliasing_ppgtt
, obj
);
2103 obj
->has_aliasing_ppgtt_mapping
= 0;
2105 i915_gem_gtt_finish_object(obj
);
2107 i915_gem_object_put_pages_gtt(obj
);
2109 list_del_init(&obj
->gtt_list
);
2110 list_del_init(&obj
->mm_list
);
2111 /* Avoid an unnecessary call to unbind on rebind. */
2112 obj
->map_and_fenceable
= true;
2114 drm_mm_put_block(obj
->gtt_space
);
2115 obj
->gtt_space
= NULL
;
2116 obj
->gtt_offset
= 0;
2118 if (i915_gem_object_is_purgeable(obj
))
2119 i915_gem_object_truncate(obj
);
2125 i915_gem_flush_ring(struct intel_ring_buffer
*ring
,
2126 uint32_t invalidate_domains
,
2127 uint32_t flush_domains
)
2131 if (((invalidate_domains
| flush_domains
) & I915_GEM_GPU_DOMAINS
) == 0)
2134 trace_i915_gem_ring_flush(ring
, invalidate_domains
, flush_domains
);
2136 ret
= ring
->flush(ring
, invalidate_domains
, flush_domains
);
2140 if (flush_domains
& I915_GEM_GPU_DOMAINS
)
2141 i915_gem_process_flushing_list(ring
, flush_domains
);
2146 static int i915_ring_idle(struct intel_ring_buffer
*ring
, bool do_retire
)
2150 if (list_empty(&ring
->gpu_write_list
) && list_empty(&ring
->active_list
))
2153 if (!list_empty(&ring
->gpu_write_list
)) {
2154 ret
= i915_gem_flush_ring(ring
,
2155 I915_GEM_GPU_DOMAINS
, I915_GEM_GPU_DOMAINS
);
2160 return i915_wait_request(ring
, i915_gem_next_request_seqno(ring
),
2164 int i915_gpu_idle(struct drm_device
*dev
, bool do_retire
)
2166 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2169 /* Flush everything onto the inactive list. */
2170 for (i
= 0; i
< I915_NUM_RINGS
; i
++) {
2171 ret
= i915_ring_idle(&dev_priv
->ring
[i
], do_retire
);
2179 static void sandybridge_write_fence_reg(struct drm_device
*dev
, int reg
,
2180 struct drm_i915_gem_object
*obj
)
2182 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2186 u32 size
= obj
->gtt_space
->size
;
2188 val
= (uint64_t)((obj
->gtt_offset
+ size
- 4096) &
2190 val
|= obj
->gtt_offset
& 0xfffff000;
2191 val
|= (uint64_t)((obj
->stride
/ 128) - 1) <<
2192 SANDYBRIDGE_FENCE_PITCH_SHIFT
;
2194 if (obj
->tiling_mode
== I915_TILING_Y
)
2195 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
2196 val
|= I965_FENCE_REG_VALID
;
2200 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0
+ reg
* 8, val
);
2201 POSTING_READ(FENCE_REG_SANDYBRIDGE_0
+ reg
* 8);
2204 static void i965_write_fence_reg(struct drm_device
*dev
, int reg
,
2205 struct drm_i915_gem_object
*obj
)
2207 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2211 u32 size
= obj
->gtt_space
->size
;
2213 val
= (uint64_t)((obj
->gtt_offset
+ size
- 4096) &
2215 val
|= obj
->gtt_offset
& 0xfffff000;
2216 val
|= ((obj
->stride
/ 128) - 1) << I965_FENCE_PITCH_SHIFT
;
2217 if (obj
->tiling_mode
== I915_TILING_Y
)
2218 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
2219 val
|= I965_FENCE_REG_VALID
;
2223 I915_WRITE64(FENCE_REG_965_0
+ reg
* 8, val
);
2224 POSTING_READ(FENCE_REG_965_0
+ reg
* 8);
2227 static void i915_write_fence_reg(struct drm_device
*dev
, int reg
,
2228 struct drm_i915_gem_object
*obj
)
2230 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2234 u32 size
= obj
->gtt_space
->size
;
2238 WARN((obj
->gtt_offset
& ~I915_FENCE_START_MASK
) ||
2239 (size
& -size
) != size
||
2240 (obj
->gtt_offset
& (size
- 1)),
2241 "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2242 obj
->gtt_offset
, obj
->map_and_fenceable
, size
);
2244 if (obj
->tiling_mode
== I915_TILING_Y
&& HAS_128_BYTE_Y_TILING(dev
))
2249 /* Note: pitch better be a power of two tile widths */
2250 pitch_val
= obj
->stride
/ tile_width
;
2251 pitch_val
= ffs(pitch_val
) - 1;
2253 val
= obj
->gtt_offset
;
2254 if (obj
->tiling_mode
== I915_TILING_Y
)
2255 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2256 val
|= I915_FENCE_SIZE_BITS(size
);
2257 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2258 val
|= I830_FENCE_REG_VALID
;
2263 reg
= FENCE_REG_830_0
+ reg
* 4;
2265 reg
= FENCE_REG_945_8
+ (reg
- 8) * 4;
2267 I915_WRITE(reg
, val
);
2271 static void i830_write_fence_reg(struct drm_device
*dev
, int reg
,
2272 struct drm_i915_gem_object
*obj
)
2274 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2278 u32 size
= obj
->gtt_space
->size
;
2281 WARN((obj
->gtt_offset
& ~I830_FENCE_START_MASK
) ||
2282 (size
& -size
) != size
||
2283 (obj
->gtt_offset
& (size
- 1)),
2284 "object 0x%08x not 512K or pot-size 0x%08x aligned\n",
2285 obj
->gtt_offset
, size
);
2287 pitch_val
= obj
->stride
/ 128;
2288 pitch_val
= ffs(pitch_val
) - 1;
2290 val
= obj
->gtt_offset
;
2291 if (obj
->tiling_mode
== I915_TILING_Y
)
2292 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2293 val
|= I830_FENCE_SIZE_BITS(size
);
2294 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2295 val
|= I830_FENCE_REG_VALID
;
2299 I915_WRITE(FENCE_REG_830_0
+ reg
* 4, val
);
2300 POSTING_READ(FENCE_REG_830_0
+ reg
* 4);
2303 static void i915_gem_write_fence(struct drm_device
*dev
, int reg
,
2304 struct drm_i915_gem_object
*obj
)
2306 switch (INTEL_INFO(dev
)->gen
) {
2308 case 6: sandybridge_write_fence_reg(dev
, reg
, obj
); break;
2310 case 4: i965_write_fence_reg(dev
, reg
, obj
); break;
2311 case 3: i915_write_fence_reg(dev
, reg
, obj
); break;
2312 case 2: i830_write_fence_reg(dev
, reg
, obj
); break;
2317 static inline int fence_number(struct drm_i915_private
*dev_priv
,
2318 struct drm_i915_fence_reg
*fence
)
2320 return fence
- dev_priv
->fence_regs
;
2323 static void i915_gem_object_update_fence(struct drm_i915_gem_object
*obj
,
2324 struct drm_i915_fence_reg
*fence
,
2327 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2328 int reg
= fence_number(dev_priv
, fence
);
2330 i915_gem_write_fence(obj
->base
.dev
, reg
, enable
? obj
: NULL
);
2333 obj
->fence_reg
= reg
;
2335 list_move_tail(&fence
->lru_list
, &dev_priv
->mm
.fence_list
);
2337 obj
->fence_reg
= I915_FENCE_REG_NONE
;
2339 list_del_init(&fence
->lru_list
);
2344 i915_gem_object_flush_fence(struct drm_i915_gem_object
*obj
)
2348 if (obj
->fenced_gpu_access
) {
2349 if (obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
) {
2350 ret
= i915_gem_flush_ring(obj
->ring
,
2351 0, obj
->base
.write_domain
);
2356 obj
->fenced_gpu_access
= false;
2359 if (obj
->last_fenced_seqno
) {
2360 ret
= i915_wait_request(obj
->ring
,
2361 obj
->last_fenced_seqno
,
2366 obj
->last_fenced_seqno
= 0;
2369 /* Ensure that all CPU reads are completed before installing a fence
2370 * and all writes before removing the fence.
2372 if (obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
)
2379 i915_gem_object_put_fence(struct drm_i915_gem_object
*obj
)
2381 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2384 ret
= i915_gem_object_flush_fence(obj
);
2388 if (obj
->fence_reg
== I915_FENCE_REG_NONE
)
2391 i915_gem_object_update_fence(obj
,
2392 &dev_priv
->fence_regs
[obj
->fence_reg
],
2394 i915_gem_object_fence_lost(obj
);
2399 static struct drm_i915_fence_reg
*
2400 i915_find_fence_reg(struct drm_device
*dev
)
2402 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2403 struct drm_i915_fence_reg
*reg
, *avail
;
2406 /* First try to find a free reg */
2408 for (i
= dev_priv
->fence_reg_start
; i
< dev_priv
->num_fence_regs
; i
++) {
2409 reg
= &dev_priv
->fence_regs
[i
];
2413 if (!reg
->pin_count
)
2420 /* None available, try to steal one or wait for a user to finish */
2421 list_for_each_entry(reg
, &dev_priv
->mm
.fence_list
, lru_list
) {
2432 * i915_gem_object_get_fence - set up fencing for an object
2433 * @obj: object to map through a fence reg
2435 * When mapping objects through the GTT, userspace wants to be able to write
2436 * to them without having to worry about swizzling if the object is tiled.
2437 * This function walks the fence regs looking for a free one for @obj,
2438 * stealing one if it can't find any.
2440 * It then sets up the reg based on the object's properties: address, pitch
2441 * and tiling format.
2443 * For an untiled surface, this removes any existing fence.
2446 i915_gem_object_get_fence(struct drm_i915_gem_object
*obj
)
2448 struct drm_device
*dev
= obj
->base
.dev
;
2449 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2450 bool enable
= obj
->tiling_mode
!= I915_TILING_NONE
;
2451 struct drm_i915_fence_reg
*reg
;
2454 /* Have we updated the tiling parameters upon the object and so
2455 * will need to serialise the write to the associated fence register?
2457 if (obj
->tiling_changed
) {
2458 ret
= i915_gem_object_flush_fence(obj
);
2463 /* Just update our place in the LRU if our fence is getting reused. */
2464 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
2465 reg
= &dev_priv
->fence_regs
[obj
->fence_reg
];
2466 if (!obj
->tiling_changed
) {
2467 list_move_tail(®
->lru_list
,
2468 &dev_priv
->mm
.fence_list
);
2471 } else if (enable
) {
2472 reg
= i915_find_fence_reg(dev
);
2477 struct drm_i915_gem_object
*old
= reg
->obj
;
2479 ret
= i915_gem_object_flush_fence(old
);
2483 i915_gem_object_fence_lost(old
);
2488 i915_gem_object_update_fence(obj
, reg
, enable
);
2489 obj
->tiling_changed
= false;
2495 * Finds free space in the GTT aperture and binds the object there.
2498 i915_gem_object_bind_to_gtt(struct drm_i915_gem_object
*obj
,
2500 bool map_and_fenceable
)
2502 struct drm_device
*dev
= obj
->base
.dev
;
2503 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2504 struct drm_mm_node
*free_space
;
2505 gfp_t gfpmask
= __GFP_NORETRY
| __GFP_NOWARN
;
2506 u32 size
, fence_size
, fence_alignment
, unfenced_alignment
;
2507 bool mappable
, fenceable
;
2510 if (obj
->madv
!= I915_MADV_WILLNEED
) {
2511 DRM_ERROR("Attempting to bind a purgeable object\n");
2515 fence_size
= i915_gem_get_gtt_size(dev
,
2518 fence_alignment
= i915_gem_get_gtt_alignment(dev
,
2521 unfenced_alignment
=
2522 i915_gem_get_unfenced_gtt_alignment(dev
,
2527 alignment
= map_and_fenceable
? fence_alignment
:
2529 if (map_and_fenceable
&& alignment
& (fence_alignment
- 1)) {
2530 DRM_ERROR("Invalid object alignment requested %u\n", alignment
);
2534 size
= map_and_fenceable
? fence_size
: obj
->base
.size
;
2536 /* If the object is bigger than the entire aperture, reject it early
2537 * before evicting everything in a vain attempt to find space.
2539 if (obj
->base
.size
>
2540 (map_and_fenceable
? dev_priv
->mm
.gtt_mappable_end
: dev_priv
->mm
.gtt_total
)) {
2541 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2546 if (map_and_fenceable
)
2548 drm_mm_search_free_in_range(&dev_priv
->mm
.gtt_space
,
2550 dev_priv
->mm
.gtt_mappable_end
,
2553 free_space
= drm_mm_search_free(&dev_priv
->mm
.gtt_space
,
2554 size
, alignment
, 0);
2556 if (free_space
!= NULL
) {
2557 if (map_and_fenceable
)
2559 drm_mm_get_block_range_generic(free_space
,
2561 dev_priv
->mm
.gtt_mappable_end
,
2565 drm_mm_get_block(free_space
, size
, alignment
);
2567 if (obj
->gtt_space
== NULL
) {
2568 /* If the gtt is empty and we're still having trouble
2569 * fitting our object in, we're out of memory.
2571 ret
= i915_gem_evict_something(dev
, size
, alignment
,
2579 ret
= i915_gem_object_get_pages_gtt(obj
, gfpmask
);
2581 drm_mm_put_block(obj
->gtt_space
);
2582 obj
->gtt_space
= NULL
;
2584 if (ret
== -ENOMEM
) {
2585 /* first try to reclaim some memory by clearing the GTT */
2586 ret
= i915_gem_evict_everything(dev
, false);
2588 /* now try to shrink everyone else */
2603 ret
= i915_gem_gtt_prepare_object(obj
);
2605 i915_gem_object_put_pages_gtt(obj
);
2606 drm_mm_put_block(obj
->gtt_space
);
2607 obj
->gtt_space
= NULL
;
2609 if (i915_gem_evict_everything(dev
, false))
2615 if (!dev_priv
->mm
.aliasing_ppgtt
)
2616 i915_gem_gtt_bind_object(obj
, obj
->cache_level
);
2618 list_add_tail(&obj
->gtt_list
, &dev_priv
->mm
.gtt_list
);
2619 list_add_tail(&obj
->mm_list
, &dev_priv
->mm
.inactive_list
);
2621 /* Assert that the object is not currently in any GPU domain. As it
2622 * wasn't in the GTT, there shouldn't be any way it could have been in
2625 BUG_ON(obj
->base
.read_domains
& I915_GEM_GPU_DOMAINS
);
2626 BUG_ON(obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
);
2628 obj
->gtt_offset
= obj
->gtt_space
->start
;
2631 obj
->gtt_space
->size
== fence_size
&&
2632 (obj
->gtt_space
->start
& (fence_alignment
- 1)) == 0;
2635 obj
->gtt_offset
+ obj
->base
.size
<= dev_priv
->mm
.gtt_mappable_end
;
2637 obj
->map_and_fenceable
= mappable
&& fenceable
;
2639 trace_i915_gem_object_bind(obj
, map_and_fenceable
);
2644 i915_gem_clflush_object(struct drm_i915_gem_object
*obj
)
2646 /* If we don't have a page list set up, then we're not pinned
2647 * to GPU, and we can ignore the cache flush because it'll happen
2648 * again at bind time.
2650 if (obj
->pages
== NULL
)
2653 /* If the GPU is snooping the contents of the CPU cache,
2654 * we do not need to manually clear the CPU cache lines. However,
2655 * the caches are only snooped when the render cache is
2656 * flushed/invalidated. As we always have to emit invalidations
2657 * and flushes when moving into and out of the RENDER domain, correct
2658 * snooping behaviour occurs naturally as the result of our domain
2661 if (obj
->cache_level
!= I915_CACHE_NONE
)
2664 trace_i915_gem_object_clflush(obj
);
2666 drm_clflush_pages(obj
->pages
, obj
->base
.size
/ PAGE_SIZE
);
2669 /** Flushes any GPU write domain for the object if it's dirty. */
2671 i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object
*obj
)
2673 if ((obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
) == 0)
2676 /* Queue the GPU write cache flushing we need. */
2677 return i915_gem_flush_ring(obj
->ring
, 0, obj
->base
.write_domain
);
2680 /** Flushes the GTT write domain for the object if it's dirty. */
2682 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
)
2684 uint32_t old_write_domain
;
2686 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_GTT
)
2689 /* No actual flushing is required for the GTT write domain. Writes
2690 * to it immediately go to main memory as far as we know, so there's
2691 * no chipset flush. It also doesn't land in render cache.
2693 * However, we do have to enforce the order so that all writes through
2694 * the GTT land before any writes to the device, such as updates to
2699 old_write_domain
= obj
->base
.write_domain
;
2700 obj
->base
.write_domain
= 0;
2702 trace_i915_gem_object_change_domain(obj
,
2703 obj
->base
.read_domains
,
2707 /** Flushes the CPU write domain for the object if it's dirty. */
2709 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
)
2711 uint32_t old_write_domain
;
2713 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
)
2716 i915_gem_clflush_object(obj
);
2717 intel_gtt_chipset_flush();
2718 old_write_domain
= obj
->base
.write_domain
;
2719 obj
->base
.write_domain
= 0;
2721 trace_i915_gem_object_change_domain(obj
,
2722 obj
->base
.read_domains
,
2727 * Moves a single object to the GTT read, and possibly write domain.
2729 * This function returns when the move is complete, including waiting on
2733 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
, bool write
)
2735 uint32_t old_write_domain
, old_read_domains
;
2738 /* Not valid to be called on unbound objects. */
2739 if (obj
->gtt_space
== NULL
)
2742 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_GTT
)
2745 ret
= i915_gem_object_flush_gpu_write_domain(obj
);
2749 if (obj
->pending_gpu_write
|| write
) {
2750 ret
= i915_gem_object_wait_rendering(obj
);
2755 i915_gem_object_flush_cpu_write_domain(obj
);
2757 old_write_domain
= obj
->base
.write_domain
;
2758 old_read_domains
= obj
->base
.read_domains
;
2760 /* It should now be out of any other write domains, and we can update
2761 * the domain values for our changes.
2763 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
2764 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
2766 obj
->base
.read_domains
= I915_GEM_DOMAIN_GTT
;
2767 obj
->base
.write_domain
= I915_GEM_DOMAIN_GTT
;
2771 trace_i915_gem_object_change_domain(obj
,
2778 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
2779 enum i915_cache_level cache_level
)
2781 struct drm_device
*dev
= obj
->base
.dev
;
2782 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2785 if (obj
->cache_level
== cache_level
)
2788 if (obj
->pin_count
) {
2789 DRM_DEBUG("can not change the cache level of pinned objects\n");
2793 if (obj
->gtt_space
) {
2794 ret
= i915_gem_object_finish_gpu(obj
);
2798 i915_gem_object_finish_gtt(obj
);
2800 /* Before SandyBridge, you could not use tiling or fence
2801 * registers with snooped memory, so relinquish any fences
2802 * currently pointing to our region in the aperture.
2804 if (INTEL_INFO(obj
->base
.dev
)->gen
< 6) {
2805 ret
= i915_gem_object_put_fence(obj
);
2810 if (obj
->has_global_gtt_mapping
)
2811 i915_gem_gtt_bind_object(obj
, cache_level
);
2812 if (obj
->has_aliasing_ppgtt_mapping
)
2813 i915_ppgtt_bind_object(dev_priv
->mm
.aliasing_ppgtt
,
2817 if (cache_level
== I915_CACHE_NONE
) {
2818 u32 old_read_domains
, old_write_domain
;
2820 /* If we're coming from LLC cached, then we haven't
2821 * actually been tracking whether the data is in the
2822 * CPU cache or not, since we only allow one bit set
2823 * in obj->write_domain and have been skipping the clflushes.
2824 * Just set it to the CPU cache for now.
2826 WARN_ON(obj
->base
.write_domain
& ~I915_GEM_DOMAIN_CPU
);
2827 WARN_ON(obj
->base
.read_domains
& ~I915_GEM_DOMAIN_CPU
);
2829 old_read_domains
= obj
->base
.read_domains
;
2830 old_write_domain
= obj
->base
.write_domain
;
2832 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
2833 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
2835 trace_i915_gem_object_change_domain(obj
,
2840 obj
->cache_level
= cache_level
;
2845 * Prepare buffer for display plane (scanout, cursors, etc).
2846 * Can be called from an uninterruptible phase (modesetting) and allows
2847 * any flushes to be pipelined (for pageflips).
2850 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
2852 struct intel_ring_buffer
*pipelined
)
2854 u32 old_read_domains
, old_write_domain
;
2857 ret
= i915_gem_object_flush_gpu_write_domain(obj
);
2861 if (pipelined
!= obj
->ring
) {
2862 ret
= i915_gem_object_sync(obj
, pipelined
);
2867 /* The display engine is not coherent with the LLC cache on gen6. As
2868 * a result, we make sure that the pinning that is about to occur is
2869 * done with uncached PTEs. This is lowest common denominator for all
2872 * However for gen6+, we could do better by using the GFDT bit instead
2873 * of uncaching, which would allow us to flush all the LLC-cached data
2874 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
2876 ret
= i915_gem_object_set_cache_level(obj
, I915_CACHE_NONE
);
2880 /* As the user may map the buffer once pinned in the display plane
2881 * (e.g. libkms for the bootup splash), we have to ensure that we
2882 * always use map_and_fenceable for all scanout buffers.
2884 ret
= i915_gem_object_pin(obj
, alignment
, true);
2888 i915_gem_object_flush_cpu_write_domain(obj
);
2890 old_write_domain
= obj
->base
.write_domain
;
2891 old_read_domains
= obj
->base
.read_domains
;
2893 /* It should now be out of any other write domains, and we can update
2894 * the domain values for our changes.
2896 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
2897 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
2899 trace_i915_gem_object_change_domain(obj
,
2907 i915_gem_object_finish_gpu(struct drm_i915_gem_object
*obj
)
2911 if ((obj
->base
.read_domains
& I915_GEM_GPU_DOMAINS
) == 0)
2914 if (obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
) {
2915 ret
= i915_gem_flush_ring(obj
->ring
, 0, obj
->base
.write_domain
);
2920 ret
= i915_gem_object_wait_rendering(obj
);
2924 /* Ensure that we invalidate the GPU's caches and TLBs. */
2925 obj
->base
.read_domains
&= ~I915_GEM_GPU_DOMAINS
;
2930 * Moves a single object to the CPU read, and possibly write domain.
2932 * This function returns when the move is complete, including waiting on
2936 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
)
2938 uint32_t old_write_domain
, old_read_domains
;
2941 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_CPU
)
2944 ret
= i915_gem_object_flush_gpu_write_domain(obj
);
2948 if (write
|| obj
->pending_gpu_write
) {
2949 ret
= i915_gem_object_wait_rendering(obj
);
2954 i915_gem_object_flush_gtt_write_domain(obj
);
2956 old_write_domain
= obj
->base
.write_domain
;
2957 old_read_domains
= obj
->base
.read_domains
;
2959 /* Flush the CPU cache if it's still invalid. */
2960 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) == 0) {
2961 i915_gem_clflush_object(obj
);
2963 obj
->base
.read_domains
|= I915_GEM_DOMAIN_CPU
;
2966 /* It should now be out of any other write domains, and we can update
2967 * the domain values for our changes.
2969 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
2971 /* If we're writing through the CPU, then the GPU read domains will
2972 * need to be invalidated at next use.
2975 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
2976 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
2979 trace_i915_gem_object_change_domain(obj
,
2986 /* Throttle our rendering by waiting until the ring has completed our requests
2987 * emitted over 20 msec ago.
2989 * Note that if we were to use the current jiffies each time around the loop,
2990 * we wouldn't escape the function with any frames outstanding if the time to
2991 * render a frame was over 20ms.
2993 * This should get us reasonable parallelism between CPU and GPU but also
2994 * relatively low latency when blocking on a particular request to finish.
2997 i915_gem_ring_throttle(struct drm_device
*dev
, struct drm_file
*file
)
2999 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3000 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
3001 unsigned long recent_enough
= jiffies
- msecs_to_jiffies(20);
3002 struct drm_i915_gem_request
*request
;
3003 struct intel_ring_buffer
*ring
= NULL
;
3007 if (atomic_read(&dev_priv
->mm
.wedged
))
3010 spin_lock(&file_priv
->mm
.lock
);
3011 list_for_each_entry(request
, &file_priv
->mm
.request_list
, client_list
) {
3012 if (time_after_eq(request
->emitted_jiffies
, recent_enough
))
3015 ring
= request
->ring
;
3016 seqno
= request
->seqno
;
3018 spin_unlock(&file_priv
->mm
.lock
);
3024 if (!i915_seqno_passed(ring
->get_seqno(ring
), seqno
)) {
3025 /* And wait for the seqno passing without holding any locks and
3026 * causing extra latency for others. This is safe as the irq
3027 * generation is designed to be run atomically and so is
3030 if (ring
->irq_get(ring
)) {
3031 ret
= wait_event_interruptible(ring
->irq_queue
,
3032 i915_seqno_passed(ring
->get_seqno(ring
), seqno
)
3033 || atomic_read(&dev_priv
->mm
.wedged
));
3034 ring
->irq_put(ring
);
3036 if (ret
== 0 && atomic_read(&dev_priv
->mm
.wedged
))
3038 } else if (wait_for_atomic(i915_seqno_passed(ring
->get_seqno(ring
),
3040 atomic_read(&dev_priv
->mm
.wedged
), 3000)) {
3046 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, 0);
3052 i915_gem_object_pin(struct drm_i915_gem_object
*obj
,
3054 bool map_and_fenceable
)
3056 struct drm_device
*dev
= obj
->base
.dev
;
3057 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3060 BUG_ON(obj
->pin_count
== DRM_I915_GEM_OBJECT_MAX_PIN_COUNT
);
3061 WARN_ON(i915_verify_lists(dev
));
3063 if (obj
->gtt_space
!= NULL
) {
3064 if ((alignment
&& obj
->gtt_offset
& (alignment
- 1)) ||
3065 (map_and_fenceable
&& !obj
->map_and_fenceable
)) {
3066 WARN(obj
->pin_count
,
3067 "bo is already pinned with incorrect alignment:"
3068 " offset=%x, req.alignment=%x, req.map_and_fenceable=%d,"
3069 " obj->map_and_fenceable=%d\n",
3070 obj
->gtt_offset
, alignment
,
3072 obj
->map_and_fenceable
);
3073 ret
= i915_gem_object_unbind(obj
);
3079 if (obj
->gtt_space
== NULL
) {
3080 ret
= i915_gem_object_bind_to_gtt(obj
, alignment
,
3086 if (!obj
->has_global_gtt_mapping
&& map_and_fenceable
)
3087 i915_gem_gtt_bind_object(obj
, obj
->cache_level
);
3089 if (obj
->pin_count
++ == 0) {
3091 list_move_tail(&obj
->mm_list
,
3092 &dev_priv
->mm
.pinned_list
);
3094 obj
->pin_mappable
|= map_and_fenceable
;
3096 WARN_ON(i915_verify_lists(dev
));
3101 i915_gem_object_unpin(struct drm_i915_gem_object
*obj
)
3103 struct drm_device
*dev
= obj
->base
.dev
;
3104 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3106 WARN_ON(i915_verify_lists(dev
));
3107 BUG_ON(obj
->pin_count
== 0);
3108 BUG_ON(obj
->gtt_space
== NULL
);
3110 if (--obj
->pin_count
== 0) {
3112 list_move_tail(&obj
->mm_list
,
3113 &dev_priv
->mm
.inactive_list
);
3114 obj
->pin_mappable
= false;
3116 WARN_ON(i915_verify_lists(dev
));
3120 i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
3121 struct drm_file
*file
)
3123 struct drm_i915_gem_pin
*args
= data
;
3124 struct drm_i915_gem_object
*obj
;
3127 ret
= i915_mutex_lock_interruptible(dev
);
3131 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3132 if (&obj
->base
== NULL
) {
3137 if (obj
->madv
!= I915_MADV_WILLNEED
) {
3138 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3143 if (obj
->pin_filp
!= NULL
&& obj
->pin_filp
!= file
) {
3144 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3150 obj
->user_pin_count
++;
3151 obj
->pin_filp
= file
;
3152 if (obj
->user_pin_count
== 1) {
3153 ret
= i915_gem_object_pin(obj
, args
->alignment
, true);
3158 /* XXX - flush the CPU caches for pinned objects
3159 * as the X server doesn't manage domains yet
3161 i915_gem_object_flush_cpu_write_domain(obj
);
3162 args
->offset
= obj
->gtt_offset
;
3164 drm_gem_object_unreference(&obj
->base
);
3166 mutex_unlock(&dev
->struct_mutex
);
3171 i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
3172 struct drm_file
*file
)
3174 struct drm_i915_gem_pin
*args
= data
;
3175 struct drm_i915_gem_object
*obj
;
3178 ret
= i915_mutex_lock_interruptible(dev
);
3182 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3183 if (&obj
->base
== NULL
) {
3188 if (obj
->pin_filp
!= file
) {
3189 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3194 obj
->user_pin_count
--;
3195 if (obj
->user_pin_count
== 0) {
3196 obj
->pin_filp
= NULL
;
3197 i915_gem_object_unpin(obj
);
3201 drm_gem_object_unreference(&obj
->base
);
3203 mutex_unlock(&dev
->struct_mutex
);
3208 i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
3209 struct drm_file
*file
)
3211 struct drm_i915_gem_busy
*args
= data
;
3212 struct drm_i915_gem_object
*obj
;
3215 ret
= i915_mutex_lock_interruptible(dev
);
3219 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3220 if (&obj
->base
== NULL
) {
3225 /* Count all active objects as busy, even if they are currently not used
3226 * by the gpu. Users of this interface expect objects to eventually
3227 * become non-busy without any further actions, therefore emit any
3228 * necessary flushes here.
3230 args
->busy
= obj
->active
;
3232 /* Unconditionally flush objects, even when the gpu still uses this
3233 * object. Userspace calling this function indicates that it wants to
3234 * use this buffer rather sooner than later, so issuing the required
3235 * flush earlier is beneficial.
3237 if (obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
) {
3238 ret
= i915_gem_flush_ring(obj
->ring
,
3239 0, obj
->base
.write_domain
);
3240 } else if (obj
->ring
->outstanding_lazy_request
==
3241 obj
->last_rendering_seqno
) {
3242 struct drm_i915_gem_request
*request
;
3244 /* This ring is not being cleared by active usage,
3245 * so emit a request to do so.
3247 request
= kzalloc(sizeof(*request
), GFP_KERNEL
);
3249 ret
= i915_add_request(obj
->ring
, NULL
, request
);
3256 /* Update the active list for the hardware's current position.
3257 * Otherwise this only updates on a delayed timer or when irqs
3258 * are actually unmasked, and our working set ends up being
3259 * larger than required.
3261 i915_gem_retire_requests_ring(obj
->ring
);
3263 args
->busy
= obj
->active
;
3266 drm_gem_object_unreference(&obj
->base
);
3268 mutex_unlock(&dev
->struct_mutex
);
3273 i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
3274 struct drm_file
*file_priv
)
3276 return i915_gem_ring_throttle(dev
, file_priv
);
3280 i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
3281 struct drm_file
*file_priv
)
3283 struct drm_i915_gem_madvise
*args
= data
;
3284 struct drm_i915_gem_object
*obj
;
3287 switch (args
->madv
) {
3288 case I915_MADV_DONTNEED
:
3289 case I915_MADV_WILLNEED
:
3295 ret
= i915_mutex_lock_interruptible(dev
);
3299 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file_priv
, args
->handle
));
3300 if (&obj
->base
== NULL
) {
3305 if (obj
->pin_count
) {
3310 if (obj
->madv
!= __I915_MADV_PURGED
)
3311 obj
->madv
= args
->madv
;
3313 /* if the object is no longer bound, discard its backing storage */
3314 if (i915_gem_object_is_purgeable(obj
) &&
3315 obj
->gtt_space
== NULL
)
3316 i915_gem_object_truncate(obj
);
3318 args
->retained
= obj
->madv
!= __I915_MADV_PURGED
;
3321 drm_gem_object_unreference(&obj
->base
);
3323 mutex_unlock(&dev
->struct_mutex
);
3327 struct drm_i915_gem_object
*i915_gem_alloc_object(struct drm_device
*dev
,
3330 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3331 struct drm_i915_gem_object
*obj
;
3332 struct address_space
*mapping
;
3334 obj
= kzalloc(sizeof(*obj
), GFP_KERNEL
);
3338 if (drm_gem_object_init(dev
, &obj
->base
, size
) != 0) {
3343 mapping
= obj
->base
.filp
->f_path
.dentry
->d_inode
->i_mapping
;
3344 mapping_set_gfp_mask(mapping
, GFP_HIGHUSER
| __GFP_RECLAIMABLE
);
3346 i915_gem_info_add_obj(dev_priv
, size
);
3348 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
3349 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
3352 /* On some devices, we can have the GPU use the LLC (the CPU
3353 * cache) for about a 10% performance improvement
3354 * compared to uncached. Graphics requests other than
3355 * display scanout are coherent with the CPU in
3356 * accessing this cache. This means in this mode we
3357 * don't need to clflush on the CPU side, and on the
3358 * GPU side we only need to flush internal caches to
3359 * get data visible to the CPU.
3361 * However, we maintain the display planes as UC, and so
3362 * need to rebind when first used as such.
3364 obj
->cache_level
= I915_CACHE_LLC
;
3366 obj
->cache_level
= I915_CACHE_NONE
;
3368 obj
->base
.driver_private
= NULL
;
3369 obj
->fence_reg
= I915_FENCE_REG_NONE
;
3370 INIT_LIST_HEAD(&obj
->mm_list
);
3371 INIT_LIST_HEAD(&obj
->gtt_list
);
3372 INIT_LIST_HEAD(&obj
->ring_list
);
3373 INIT_LIST_HEAD(&obj
->exec_list
);
3374 INIT_LIST_HEAD(&obj
->gpu_write_list
);
3375 obj
->madv
= I915_MADV_WILLNEED
;
3376 /* Avoid an unnecessary call to unbind on the first bind. */
3377 obj
->map_and_fenceable
= true;
3382 int i915_gem_init_object(struct drm_gem_object
*obj
)
3389 static void i915_gem_free_object_tail(struct drm_i915_gem_object
*obj
)
3391 struct drm_device
*dev
= obj
->base
.dev
;
3392 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3395 ret
= i915_gem_object_unbind(obj
);
3396 if (ret
== -ERESTARTSYS
) {
3397 list_move(&obj
->mm_list
,
3398 &dev_priv
->mm
.deferred_free_list
);
3402 trace_i915_gem_object_destroy(obj
);
3404 if (obj
->base
.map_list
.map
)
3405 drm_gem_free_mmap_offset(&obj
->base
);
3407 drm_gem_object_release(&obj
->base
);
3408 i915_gem_info_remove_obj(dev_priv
, obj
->base
.size
);
3414 void i915_gem_free_object(struct drm_gem_object
*gem_obj
)
3416 struct drm_i915_gem_object
*obj
= to_intel_bo(gem_obj
);
3417 struct drm_device
*dev
= obj
->base
.dev
;
3419 while (obj
->pin_count
> 0)
3420 i915_gem_object_unpin(obj
);
3423 i915_gem_detach_phys_object(dev
, obj
);
3425 i915_gem_free_object_tail(obj
);
3429 i915_gem_idle(struct drm_device
*dev
)
3431 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3434 mutex_lock(&dev
->struct_mutex
);
3436 if (dev_priv
->mm
.suspended
) {
3437 mutex_unlock(&dev
->struct_mutex
);
3441 ret
= i915_gpu_idle(dev
, true);
3443 mutex_unlock(&dev
->struct_mutex
);
3447 /* Under UMS, be paranoid and evict. */
3448 if (!drm_core_check_feature(dev
, DRIVER_MODESET
)) {
3449 ret
= i915_gem_evict_inactive(dev
, false);
3451 mutex_unlock(&dev
->struct_mutex
);
3456 i915_gem_reset_fences(dev
);
3458 /* Hack! Don't let anybody do execbuf while we don't control the chip.
3459 * We need to replace this with a semaphore, or something.
3460 * And not confound mm.suspended!
3462 dev_priv
->mm
.suspended
= 1;
3463 del_timer_sync(&dev_priv
->hangcheck_timer
);
3465 i915_kernel_lost_context(dev
);
3466 i915_gem_cleanup_ringbuffer(dev
);
3468 mutex_unlock(&dev
->struct_mutex
);
3470 /* Cancel the retire work handler, which should be idle now. */
3471 cancel_delayed_work_sync(&dev_priv
->mm
.retire_work
);
3476 void i915_gem_init_swizzling(struct drm_device
*dev
)
3478 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3480 if (INTEL_INFO(dev
)->gen
< 5 ||
3481 dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_NONE
)
3484 I915_WRITE(DISP_ARB_CTL
, I915_READ(DISP_ARB_CTL
) |
3485 DISP_TILE_SURFACE_SWIZZLING
);
3490 I915_WRITE(TILECTL
, I915_READ(TILECTL
) | TILECTL_SWZCTL
);
3492 I915_WRITE(ARB_MODE
, ARB_MODE_ENABLE(ARB_MODE_SWIZZLE_SNB
));
3494 I915_WRITE(ARB_MODE
, ARB_MODE_ENABLE(ARB_MODE_SWIZZLE_IVB
));
3497 void i915_gem_init_ppgtt(struct drm_device
*dev
)
3499 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3501 struct intel_ring_buffer
*ring
;
3502 struct i915_hw_ppgtt
*ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
3503 uint32_t __iomem
*pd_addr
;
3507 if (!dev_priv
->mm
.aliasing_ppgtt
)
3511 pd_addr
= dev_priv
->mm
.gtt
->gtt
+ ppgtt
->pd_offset
/sizeof(uint32_t);
3512 for (i
= 0; i
< ppgtt
->num_pd_entries
; i
++) {
3515 if (dev_priv
->mm
.gtt
->needs_dmar
)
3516 pt_addr
= ppgtt
->pt_dma_addr
[i
];
3518 pt_addr
= page_to_phys(ppgtt
->pt_pages
[i
]);
3520 pd_entry
= GEN6_PDE_ADDR_ENCODE(pt_addr
);
3521 pd_entry
|= GEN6_PDE_VALID
;
3523 writel(pd_entry
, pd_addr
+ i
);
3527 pd_offset
= ppgtt
->pd_offset
;
3528 pd_offset
/= 64; /* in cachelines, */
3531 if (INTEL_INFO(dev
)->gen
== 6) {
3532 uint32_t ecochk
, gab_ctl
, ecobits
;
3534 ecobits
= I915_READ(GAC_ECO_BITS
);
3535 I915_WRITE(GAC_ECO_BITS
, ecobits
| ECOBITS_PPGTT_CACHE64B
);
3537 gab_ctl
= I915_READ(GAB_CTL
);
3538 I915_WRITE(GAB_CTL
, gab_ctl
| GAB_CTL_CONT_AFTER_PAGEFAULT
);
3540 ecochk
= I915_READ(GAM_ECOCHK
);
3541 I915_WRITE(GAM_ECOCHK
, ecochk
| ECOCHK_SNB_BIT
|
3542 ECOCHK_PPGTT_CACHE64B
);
3543 I915_WRITE(GFX_MODE
, GFX_MODE_ENABLE(GFX_PPGTT_ENABLE
));
3544 } else if (INTEL_INFO(dev
)->gen
>= 7) {
3545 I915_WRITE(GAM_ECOCHK
, ECOCHK_PPGTT_CACHE64B
);
3546 /* GFX_MODE is per-ring on gen7+ */
3549 for (i
= 0; i
< I915_NUM_RINGS
; i
++) {
3550 ring
= &dev_priv
->ring
[i
];
3552 if (INTEL_INFO(dev
)->gen
>= 7)
3553 I915_WRITE(RING_MODE_GEN7(ring
),
3554 GFX_MODE_ENABLE(GFX_PPGTT_ENABLE
));
3556 I915_WRITE(RING_PP_DIR_DCLV(ring
), PP_DIR_DCLV_2G
);
3557 I915_WRITE(RING_PP_DIR_BASE(ring
), pd_offset
);
3562 i915_gem_init_hw(struct drm_device
*dev
)
3564 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3567 i915_gem_init_swizzling(dev
);
3569 ret
= intel_init_render_ring_buffer(dev
);
3574 ret
= intel_init_bsd_ring_buffer(dev
);
3576 goto cleanup_render_ring
;
3580 ret
= intel_init_blt_ring_buffer(dev
);
3582 goto cleanup_bsd_ring
;
3585 dev_priv
->next_seqno
= 1;
3587 i915_gem_init_ppgtt(dev
);
3592 intel_cleanup_ring_buffer(&dev_priv
->ring
[VCS
]);
3593 cleanup_render_ring
:
3594 intel_cleanup_ring_buffer(&dev_priv
->ring
[RCS
]);
3599 i915_gem_cleanup_ringbuffer(struct drm_device
*dev
)
3601 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3604 for (i
= 0; i
< I915_NUM_RINGS
; i
++)
3605 intel_cleanup_ring_buffer(&dev_priv
->ring
[i
]);
3609 i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
3610 struct drm_file
*file_priv
)
3612 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3615 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
3618 if (atomic_read(&dev_priv
->mm
.wedged
)) {
3619 DRM_ERROR("Reenabling wedged hardware, good luck\n");
3620 atomic_set(&dev_priv
->mm
.wedged
, 0);
3623 mutex_lock(&dev
->struct_mutex
);
3624 dev_priv
->mm
.suspended
= 0;
3626 ret
= i915_gem_init_hw(dev
);
3628 mutex_unlock(&dev
->struct_mutex
);
3632 BUG_ON(!list_empty(&dev_priv
->mm
.active_list
));
3633 BUG_ON(!list_empty(&dev_priv
->mm
.flushing_list
));
3634 BUG_ON(!list_empty(&dev_priv
->mm
.inactive_list
));
3635 for (i
= 0; i
< I915_NUM_RINGS
; i
++) {
3636 BUG_ON(!list_empty(&dev_priv
->ring
[i
].active_list
));
3637 BUG_ON(!list_empty(&dev_priv
->ring
[i
].request_list
));
3639 mutex_unlock(&dev
->struct_mutex
);
3641 ret
= drm_irq_install(dev
);
3643 goto cleanup_ringbuffer
;
3648 mutex_lock(&dev
->struct_mutex
);
3649 i915_gem_cleanup_ringbuffer(dev
);
3650 dev_priv
->mm
.suspended
= 1;
3651 mutex_unlock(&dev
->struct_mutex
);
3657 i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
3658 struct drm_file
*file_priv
)
3660 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
3663 drm_irq_uninstall(dev
);
3664 return i915_gem_idle(dev
);
3668 i915_gem_lastclose(struct drm_device
*dev
)
3672 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
3675 ret
= i915_gem_idle(dev
);
3677 DRM_ERROR("failed to idle hardware: %d\n", ret
);
3681 init_ring_lists(struct intel_ring_buffer
*ring
)
3683 INIT_LIST_HEAD(&ring
->active_list
);
3684 INIT_LIST_HEAD(&ring
->request_list
);
3685 INIT_LIST_HEAD(&ring
->gpu_write_list
);
3689 i915_gem_load(struct drm_device
*dev
)
3692 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3694 INIT_LIST_HEAD(&dev_priv
->mm
.active_list
);
3695 INIT_LIST_HEAD(&dev_priv
->mm
.flushing_list
);
3696 INIT_LIST_HEAD(&dev_priv
->mm
.inactive_list
);
3697 INIT_LIST_HEAD(&dev_priv
->mm
.pinned_list
);
3698 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
3699 INIT_LIST_HEAD(&dev_priv
->mm
.deferred_free_list
);
3700 INIT_LIST_HEAD(&dev_priv
->mm
.gtt_list
);
3701 for (i
= 0; i
< I915_NUM_RINGS
; i
++)
3702 init_ring_lists(&dev_priv
->ring
[i
]);
3703 for (i
= 0; i
< I915_MAX_NUM_FENCES
; i
++)
3704 INIT_LIST_HEAD(&dev_priv
->fence_regs
[i
].lru_list
);
3705 INIT_DELAYED_WORK(&dev_priv
->mm
.retire_work
,
3706 i915_gem_retire_work_handler
);
3707 init_completion(&dev_priv
->error_completion
);
3709 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
3711 u32 tmp
= I915_READ(MI_ARB_STATE
);
3712 if (!(tmp
& MI_ARB_C3_LP_WRITE_ENABLE
)) {
3713 /* arb state is a masked write, so set bit + bit in mask */
3714 tmp
= MI_ARB_C3_LP_WRITE_ENABLE
| (MI_ARB_C3_LP_WRITE_ENABLE
<< MI_ARB_MASK_SHIFT
);
3715 I915_WRITE(MI_ARB_STATE
, tmp
);
3719 dev_priv
->relative_constants_mode
= I915_EXEC_CONSTANTS_REL_GENERAL
;
3721 /* Old X drivers will take 0-2 for front, back, depth buffers */
3722 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
3723 dev_priv
->fence_reg_start
= 3;
3725 if (INTEL_INFO(dev
)->gen
>= 4 || IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
3726 dev_priv
->num_fence_regs
= 16;
3728 dev_priv
->num_fence_regs
= 8;
3730 /* Initialize fence registers to zero */
3731 i915_gem_reset_fences(dev
);
3733 i915_gem_detect_bit_6_swizzle(dev
);
3734 init_waitqueue_head(&dev_priv
->pending_flip_queue
);
3736 dev_priv
->mm
.interruptible
= true;
3738 dev_priv
->mm
.inactive_shrinker
.shrink
= i915_gem_inactive_shrink
;
3739 dev_priv
->mm
.inactive_shrinker
.seeks
= DEFAULT_SEEKS
;
3740 register_shrinker(&dev_priv
->mm
.inactive_shrinker
);
3744 * Create a physically contiguous memory object for this object
3745 * e.g. for cursor + overlay regs
3747 static int i915_gem_init_phys_object(struct drm_device
*dev
,
3748 int id
, int size
, int align
)
3750 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3751 struct drm_i915_gem_phys_object
*phys_obj
;
3754 if (dev_priv
->mm
.phys_objs
[id
- 1] || !size
)
3757 phys_obj
= kzalloc(sizeof(struct drm_i915_gem_phys_object
), GFP_KERNEL
);
3763 phys_obj
->handle
= drm_pci_alloc(dev
, size
, align
);
3764 if (!phys_obj
->handle
) {
3769 set_memory_wc((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
3772 dev_priv
->mm
.phys_objs
[id
- 1] = phys_obj
;
3780 static void i915_gem_free_phys_object(struct drm_device
*dev
, int id
)
3782 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3783 struct drm_i915_gem_phys_object
*phys_obj
;
3785 if (!dev_priv
->mm
.phys_objs
[id
- 1])
3788 phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
3789 if (phys_obj
->cur_obj
) {
3790 i915_gem_detach_phys_object(dev
, phys_obj
->cur_obj
);
3794 set_memory_wb((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
3796 drm_pci_free(dev
, phys_obj
->handle
);
3798 dev_priv
->mm
.phys_objs
[id
- 1] = NULL
;
3801 void i915_gem_free_all_phys_object(struct drm_device
*dev
)
3805 for (i
= I915_GEM_PHYS_CURSOR_0
; i
<= I915_MAX_PHYS_OBJECT
; i
++)
3806 i915_gem_free_phys_object(dev
, i
);
3809 void i915_gem_detach_phys_object(struct drm_device
*dev
,
3810 struct drm_i915_gem_object
*obj
)
3812 struct address_space
*mapping
= obj
->base
.filp
->f_path
.dentry
->d_inode
->i_mapping
;
3819 vaddr
= obj
->phys_obj
->handle
->vaddr
;
3821 page_count
= obj
->base
.size
/ PAGE_SIZE
;
3822 for (i
= 0; i
< page_count
; i
++) {
3823 struct page
*page
= shmem_read_mapping_page(mapping
, i
);
3824 if (!IS_ERR(page
)) {
3825 char *dst
= kmap_atomic(page
);
3826 memcpy(dst
, vaddr
+ i
*PAGE_SIZE
, PAGE_SIZE
);
3829 drm_clflush_pages(&page
, 1);
3831 set_page_dirty(page
);
3832 mark_page_accessed(page
);
3833 page_cache_release(page
);
3836 intel_gtt_chipset_flush();
3838 obj
->phys_obj
->cur_obj
= NULL
;
3839 obj
->phys_obj
= NULL
;
3843 i915_gem_attach_phys_object(struct drm_device
*dev
,
3844 struct drm_i915_gem_object
*obj
,
3848 struct address_space
*mapping
= obj
->base
.filp
->f_path
.dentry
->d_inode
->i_mapping
;
3849 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3854 if (id
> I915_MAX_PHYS_OBJECT
)
3857 if (obj
->phys_obj
) {
3858 if (obj
->phys_obj
->id
== id
)
3860 i915_gem_detach_phys_object(dev
, obj
);
3863 /* create a new object */
3864 if (!dev_priv
->mm
.phys_objs
[id
- 1]) {
3865 ret
= i915_gem_init_phys_object(dev
, id
,
3866 obj
->base
.size
, align
);
3868 DRM_ERROR("failed to init phys object %d size: %zu\n",
3869 id
, obj
->base
.size
);
3874 /* bind to the object */
3875 obj
->phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
3876 obj
->phys_obj
->cur_obj
= obj
;
3878 page_count
= obj
->base
.size
/ PAGE_SIZE
;
3880 for (i
= 0; i
< page_count
; i
++) {
3884 page
= shmem_read_mapping_page(mapping
, i
);
3886 return PTR_ERR(page
);
3888 src
= kmap_atomic(page
);
3889 dst
= obj
->phys_obj
->handle
->vaddr
+ (i
* PAGE_SIZE
);
3890 memcpy(dst
, src
, PAGE_SIZE
);
3893 mark_page_accessed(page
);
3894 page_cache_release(page
);
3901 i915_gem_phys_pwrite(struct drm_device
*dev
,
3902 struct drm_i915_gem_object
*obj
,
3903 struct drm_i915_gem_pwrite
*args
,
3904 struct drm_file
*file_priv
)
3906 void *vaddr
= obj
->phys_obj
->handle
->vaddr
+ args
->offset
;
3907 char __user
*user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
3909 if (__copy_from_user_inatomic_nocache(vaddr
, user_data
, args
->size
)) {
3910 unsigned long unwritten
;
3912 /* The physical object once assigned is fixed for the lifetime
3913 * of the obj, so we can safely drop the lock and continue
3916 mutex_unlock(&dev
->struct_mutex
);
3917 unwritten
= copy_from_user(vaddr
, user_data
, args
->size
);
3918 mutex_lock(&dev
->struct_mutex
);
3923 intel_gtt_chipset_flush();
3927 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
)
3929 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
3931 /* Clean up our request list when the client is going away, so that
3932 * later retire_requests won't dereference our soon-to-be-gone
3935 spin_lock(&file_priv
->mm
.lock
);
3936 while (!list_empty(&file_priv
->mm
.request_list
)) {
3937 struct drm_i915_gem_request
*request
;
3939 request
= list_first_entry(&file_priv
->mm
.request_list
,
3940 struct drm_i915_gem_request
,
3942 list_del(&request
->client_list
);
3943 request
->file_priv
= NULL
;
3945 spin_unlock(&file_priv
->mm
.lock
);
3949 i915_gpu_is_active(struct drm_device
*dev
)
3951 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3954 lists_empty
= list_empty(&dev_priv
->mm
.flushing_list
) &&
3955 list_empty(&dev_priv
->mm
.active_list
);
3957 return !lists_empty
;
3961 i915_gem_inactive_shrink(struct shrinker
*shrinker
, struct shrink_control
*sc
)
3963 struct drm_i915_private
*dev_priv
=
3964 container_of(shrinker
,
3965 struct drm_i915_private
,
3966 mm
.inactive_shrinker
);
3967 struct drm_device
*dev
= dev_priv
->dev
;
3968 struct drm_i915_gem_object
*obj
, *next
;
3969 int nr_to_scan
= sc
->nr_to_scan
;
3972 if (!mutex_trylock(&dev
->struct_mutex
))
3975 /* "fast-path" to count number of available objects */
3976 if (nr_to_scan
== 0) {
3978 list_for_each_entry(obj
,
3979 &dev_priv
->mm
.inactive_list
,
3982 mutex_unlock(&dev
->struct_mutex
);
3983 return cnt
/ 100 * sysctl_vfs_cache_pressure
;
3987 /* first scan for clean buffers */
3988 i915_gem_retire_requests(dev
);
3990 list_for_each_entry_safe(obj
, next
,
3991 &dev_priv
->mm
.inactive_list
,
3993 if (i915_gem_object_is_purgeable(obj
)) {
3994 if (i915_gem_object_unbind(obj
) == 0 &&
4000 /* second pass, evict/count anything still on the inactive list */
4002 list_for_each_entry_safe(obj
, next
,
4003 &dev_priv
->mm
.inactive_list
,
4006 i915_gem_object_unbind(obj
) == 0)
4012 if (nr_to_scan
&& i915_gpu_is_active(dev
)) {
4014 * We are desperate for pages, so as a last resort, wait
4015 * for the GPU to finish and discard whatever we can.
4016 * This has a dramatic impact to reduce the number of
4017 * OOM-killer events whilst running the GPU aggressively.
4019 if (i915_gpu_idle(dev
, true) == 0)
4022 mutex_unlock(&dev
->struct_mutex
);
4023 return cnt
/ 100 * sysctl_vfs_cache_pressure
;