2 * Copyright © 2008-2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/drm_vma_manager.h>
30 #include <drm/i915_drm.h>
32 #include "i915_vgpu.h"
33 #include "i915_trace.h"
34 #include "intel_drv.h"
35 #include "intel_mocs.h"
36 #include <linux/shmem_fs.h>
37 #include <linux/slab.h>
38 #include <linux/swap.h>
39 #include <linux/pci.h>
40 #include <linux/dma-buf.h>
42 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
);
43 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
);
45 i915_gem_object_retire__write(struct drm_i915_gem_object
*obj
);
47 i915_gem_object_retire__read(struct drm_i915_gem_object
*obj
, int ring
);
49 static bool cpu_cache_is_coherent(struct drm_device
*dev
,
50 enum i915_cache_level level
)
52 return HAS_LLC(dev
) || level
!= I915_CACHE_NONE
;
55 static bool cpu_write_needs_clflush(struct drm_i915_gem_object
*obj
)
57 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_CPU
)
60 if (!cpu_cache_is_coherent(obj
->base
.dev
, obj
->cache_level
))
63 return obj
->pin_display
;
67 insert_mappable_node(struct drm_i915_private
*i915
,
68 struct drm_mm_node
*node
, u32 size
)
70 memset(node
, 0, sizeof(*node
));
71 return drm_mm_insert_node_in_range_generic(&i915
->ggtt
.base
.mm
, node
,
73 i915
->ggtt
.mappable_end
,
74 DRM_MM_SEARCH_DEFAULT
,
75 DRM_MM_CREATE_DEFAULT
);
79 remove_mappable_node(struct drm_mm_node
*node
)
81 drm_mm_remove_node(node
);
84 /* some bookkeeping */
85 static void i915_gem_info_add_obj(struct drm_i915_private
*dev_priv
,
88 spin_lock(&dev_priv
->mm
.object_stat_lock
);
89 dev_priv
->mm
.object_count
++;
90 dev_priv
->mm
.object_memory
+= size
;
91 spin_unlock(&dev_priv
->mm
.object_stat_lock
);
94 static void i915_gem_info_remove_obj(struct drm_i915_private
*dev_priv
,
97 spin_lock(&dev_priv
->mm
.object_stat_lock
);
98 dev_priv
->mm
.object_count
--;
99 dev_priv
->mm
.object_memory
-= size
;
100 spin_unlock(&dev_priv
->mm
.object_stat_lock
);
104 i915_gem_wait_for_error(struct i915_gpu_error
*error
)
108 if (!i915_reset_in_progress(error
))
112 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
113 * userspace. If it takes that long something really bad is going on and
114 * we should simply try to bail out and fail as gracefully as possible.
116 ret
= wait_event_interruptible_timeout(error
->reset_queue
,
117 !i915_reset_in_progress(error
),
120 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
122 } else if (ret
< 0) {
129 int i915_mutex_lock_interruptible(struct drm_device
*dev
)
131 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
134 ret
= i915_gem_wait_for_error(&dev_priv
->gpu_error
);
138 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
142 WARN_ON(i915_verify_lists(dev
));
147 i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
148 struct drm_file
*file
)
150 struct drm_i915_private
*dev_priv
= to_i915(dev
);
151 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
152 struct drm_i915_gem_get_aperture
*args
= data
;
153 struct i915_vma
*vma
;
157 mutex_lock(&dev
->struct_mutex
);
158 list_for_each_entry(vma
, &ggtt
->base
.active_list
, vm_link
)
160 pinned
+= vma
->node
.size
;
161 list_for_each_entry(vma
, &ggtt
->base
.inactive_list
, vm_link
)
163 pinned
+= vma
->node
.size
;
164 mutex_unlock(&dev
->struct_mutex
);
166 args
->aper_size
= ggtt
->base
.total
;
167 args
->aper_available_size
= args
->aper_size
- pinned
;
173 i915_gem_object_get_pages_phys(struct drm_i915_gem_object
*obj
)
175 struct address_space
*mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
176 char *vaddr
= obj
->phys_handle
->vaddr
;
178 struct scatterlist
*sg
;
181 if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj
)))
184 for (i
= 0; i
< obj
->base
.size
/ PAGE_SIZE
; i
++) {
188 page
= shmem_read_mapping_page(mapping
, i
);
190 return PTR_ERR(page
);
192 src
= kmap_atomic(page
);
193 memcpy(vaddr
, src
, PAGE_SIZE
);
194 drm_clflush_virt_range(vaddr
, PAGE_SIZE
);
201 i915_gem_chipset_flush(to_i915(obj
->base
.dev
));
203 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
207 if (sg_alloc_table(st
, 1, GFP_KERNEL
)) {
214 sg
->length
= obj
->base
.size
;
216 sg_dma_address(sg
) = obj
->phys_handle
->busaddr
;
217 sg_dma_len(sg
) = obj
->base
.size
;
224 i915_gem_object_put_pages_phys(struct drm_i915_gem_object
*obj
)
228 BUG_ON(obj
->madv
== __I915_MADV_PURGED
);
230 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
232 /* In the event of a disaster, abandon all caches and
235 obj
->base
.read_domains
= obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
238 if (obj
->madv
== I915_MADV_DONTNEED
)
242 struct address_space
*mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
243 char *vaddr
= obj
->phys_handle
->vaddr
;
246 for (i
= 0; i
< obj
->base
.size
/ PAGE_SIZE
; i
++) {
250 page
= shmem_read_mapping_page(mapping
, i
);
254 dst
= kmap_atomic(page
);
255 drm_clflush_virt_range(vaddr
, PAGE_SIZE
);
256 memcpy(dst
, vaddr
, PAGE_SIZE
);
259 set_page_dirty(page
);
260 if (obj
->madv
== I915_MADV_WILLNEED
)
261 mark_page_accessed(page
);
268 sg_free_table(obj
->pages
);
273 i915_gem_object_release_phys(struct drm_i915_gem_object
*obj
)
275 drm_pci_free(obj
->base
.dev
, obj
->phys_handle
);
278 static const struct drm_i915_gem_object_ops i915_gem_phys_ops
= {
279 .get_pages
= i915_gem_object_get_pages_phys
,
280 .put_pages
= i915_gem_object_put_pages_phys
,
281 .release
= i915_gem_object_release_phys
,
285 drop_pages(struct drm_i915_gem_object
*obj
)
287 struct i915_vma
*vma
, *next
;
290 drm_gem_object_reference(&obj
->base
);
291 list_for_each_entry_safe(vma
, next
, &obj
->vma_list
, obj_link
)
292 if (i915_vma_unbind(vma
))
295 ret
= i915_gem_object_put_pages(obj
);
296 drm_gem_object_unreference(&obj
->base
);
302 i915_gem_object_attach_phys(struct drm_i915_gem_object
*obj
,
305 drm_dma_handle_t
*phys
;
308 if (obj
->phys_handle
) {
309 if ((unsigned long)obj
->phys_handle
->vaddr
& (align
-1))
315 if (obj
->madv
!= I915_MADV_WILLNEED
)
318 if (obj
->base
.filp
== NULL
)
321 ret
= drop_pages(obj
);
325 /* create a new object */
326 phys
= drm_pci_alloc(obj
->base
.dev
, obj
->base
.size
, align
);
330 obj
->phys_handle
= phys
;
331 obj
->ops
= &i915_gem_phys_ops
;
333 return i915_gem_object_get_pages(obj
);
337 i915_gem_phys_pwrite(struct drm_i915_gem_object
*obj
,
338 struct drm_i915_gem_pwrite
*args
,
339 struct drm_file
*file_priv
)
341 struct drm_device
*dev
= obj
->base
.dev
;
342 void *vaddr
= obj
->phys_handle
->vaddr
+ args
->offset
;
343 char __user
*user_data
= u64_to_user_ptr(args
->data_ptr
);
346 /* We manually control the domain here and pretend that it
347 * remains coherent i.e. in the GTT domain, like shmem_pwrite.
349 ret
= i915_gem_object_wait_rendering(obj
, false);
353 intel_fb_obj_invalidate(obj
, ORIGIN_CPU
);
354 if (__copy_from_user_inatomic_nocache(vaddr
, user_data
, args
->size
)) {
355 unsigned long unwritten
;
357 /* The physical object once assigned is fixed for the lifetime
358 * of the obj, so we can safely drop the lock and continue
361 mutex_unlock(&dev
->struct_mutex
);
362 unwritten
= copy_from_user(vaddr
, user_data
, args
->size
);
363 mutex_lock(&dev
->struct_mutex
);
370 drm_clflush_virt_range(vaddr
, args
->size
);
371 i915_gem_chipset_flush(to_i915(dev
));
374 intel_fb_obj_flush(obj
, false, ORIGIN_CPU
);
378 void *i915_gem_object_alloc(struct drm_device
*dev
)
380 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
381 return kmem_cache_zalloc(dev_priv
->objects
, GFP_KERNEL
);
384 void i915_gem_object_free(struct drm_i915_gem_object
*obj
)
386 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
387 kmem_cache_free(dev_priv
->objects
, obj
);
391 i915_gem_create(struct drm_file
*file
,
392 struct drm_device
*dev
,
396 struct drm_i915_gem_object
*obj
;
400 size
= roundup(size
, PAGE_SIZE
);
404 /* Allocate the new object */
405 obj
= i915_gem_object_create(dev
, size
);
409 ret
= drm_gem_handle_create(file
, &obj
->base
, &handle
);
410 /* drop reference from allocate - handle holds it now */
411 drm_gem_object_unreference_unlocked(&obj
->base
);
420 i915_gem_dumb_create(struct drm_file
*file
,
421 struct drm_device
*dev
,
422 struct drm_mode_create_dumb
*args
)
424 /* have to work out size/pitch and return them */
425 args
->pitch
= ALIGN(args
->width
* DIV_ROUND_UP(args
->bpp
, 8), 64);
426 args
->size
= args
->pitch
* args
->height
;
427 return i915_gem_create(file
, dev
,
428 args
->size
, &args
->handle
);
432 * Creates a new mm object and returns a handle to it.
433 * @dev: drm device pointer
434 * @data: ioctl data blob
435 * @file: drm file pointer
438 i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
439 struct drm_file
*file
)
441 struct drm_i915_gem_create
*args
= data
;
443 return i915_gem_create(file
, dev
,
444 args
->size
, &args
->handle
);
448 __copy_to_user_swizzled(char __user
*cpu_vaddr
,
449 const char *gpu_vaddr
, int gpu_offset
,
452 int ret
, cpu_offset
= 0;
455 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
456 int this_length
= min(cacheline_end
- gpu_offset
, length
);
457 int swizzled_gpu_offset
= gpu_offset
^ 64;
459 ret
= __copy_to_user(cpu_vaddr
+ cpu_offset
,
460 gpu_vaddr
+ swizzled_gpu_offset
,
465 cpu_offset
+= this_length
;
466 gpu_offset
+= this_length
;
467 length
-= this_length
;
474 __copy_from_user_swizzled(char *gpu_vaddr
, int gpu_offset
,
475 const char __user
*cpu_vaddr
,
478 int ret
, cpu_offset
= 0;
481 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
482 int this_length
= min(cacheline_end
- gpu_offset
, length
);
483 int swizzled_gpu_offset
= gpu_offset
^ 64;
485 ret
= __copy_from_user(gpu_vaddr
+ swizzled_gpu_offset
,
486 cpu_vaddr
+ cpu_offset
,
491 cpu_offset
+= this_length
;
492 gpu_offset
+= this_length
;
493 length
-= this_length
;
500 * Pins the specified object's pages and synchronizes the object with
501 * GPU accesses. Sets needs_clflush to non-zero if the caller should
502 * flush the object from the CPU cache.
504 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object
*obj
,
511 if (WARN_ON(!i915_gem_object_has_struct_page(obj
)))
514 if (!(obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
)) {
515 /* If we're not in the cpu read domain, set ourself into the gtt
516 * read domain and manually flush cachelines (if required). This
517 * optimizes for the case when the gpu will dirty the data
518 * anyway again before the next pread happens. */
519 *needs_clflush
= !cpu_cache_is_coherent(obj
->base
.dev
,
521 ret
= i915_gem_object_wait_rendering(obj
, true);
526 ret
= i915_gem_object_get_pages(obj
);
530 i915_gem_object_pin_pages(obj
);
535 /* Per-page copy function for the shmem pread fastpath.
536 * Flushes invalid cachelines before reading the target if
537 * needs_clflush is set. */
539 shmem_pread_fast(struct page
*page
, int shmem_page_offset
, int page_length
,
540 char __user
*user_data
,
541 bool page_do_bit17_swizzling
, bool needs_clflush
)
546 if (unlikely(page_do_bit17_swizzling
))
549 vaddr
= kmap_atomic(page
);
551 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
553 ret
= __copy_to_user_inatomic(user_data
,
554 vaddr
+ shmem_page_offset
,
556 kunmap_atomic(vaddr
);
558 return ret
? -EFAULT
: 0;
562 shmem_clflush_swizzled_range(char *addr
, unsigned long length
,
565 if (unlikely(swizzled
)) {
566 unsigned long start
= (unsigned long) addr
;
567 unsigned long end
= (unsigned long) addr
+ length
;
569 /* For swizzling simply ensure that we always flush both
570 * channels. Lame, but simple and it works. Swizzled
571 * pwrite/pread is far from a hotpath - current userspace
572 * doesn't use it at all. */
573 start
= round_down(start
, 128);
574 end
= round_up(end
, 128);
576 drm_clflush_virt_range((void *)start
, end
- start
);
578 drm_clflush_virt_range(addr
, length
);
583 /* Only difference to the fast-path function is that this can handle bit17
584 * and uses non-atomic copy and kmap functions. */
586 shmem_pread_slow(struct page
*page
, int shmem_page_offset
, int page_length
,
587 char __user
*user_data
,
588 bool page_do_bit17_swizzling
, bool needs_clflush
)
595 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
597 page_do_bit17_swizzling
);
599 if (page_do_bit17_swizzling
)
600 ret
= __copy_to_user_swizzled(user_data
,
601 vaddr
, shmem_page_offset
,
604 ret
= __copy_to_user(user_data
,
605 vaddr
+ shmem_page_offset
,
609 return ret
? - EFAULT
: 0;
612 static inline unsigned long
613 slow_user_access(struct io_mapping
*mapping
,
614 uint64_t page_base
, int page_offset
,
615 char __user
*user_data
,
616 unsigned long length
, bool pwrite
)
618 void __iomem
*ioaddr
;
622 ioaddr
= io_mapping_map_wc(mapping
, page_base
, PAGE_SIZE
);
623 /* We can use the cpu mem copy function because this is X86. */
624 vaddr
= (void __force
*)ioaddr
+ page_offset
;
626 unwritten
= __copy_from_user(vaddr
, user_data
, length
);
628 unwritten
= __copy_to_user(user_data
, vaddr
, length
);
630 io_mapping_unmap(ioaddr
);
635 i915_gem_gtt_pread(struct drm_device
*dev
,
636 struct drm_i915_gem_object
*obj
, uint64_t size
,
637 uint64_t data_offset
, uint64_t data_ptr
)
639 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
640 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
641 struct drm_mm_node node
;
642 char __user
*user_data
;
647 ret
= i915_gem_obj_ggtt_pin(obj
, 0, PIN_MAPPABLE
);
649 ret
= insert_mappable_node(dev_priv
, &node
, PAGE_SIZE
);
653 ret
= i915_gem_object_get_pages(obj
);
655 remove_mappable_node(&node
);
659 i915_gem_object_pin_pages(obj
);
661 node
.start
= i915_gem_obj_ggtt_offset(obj
);
662 node
.allocated
= false;
663 ret
= i915_gem_object_put_fence(obj
);
668 ret
= i915_gem_object_set_to_gtt_domain(obj
, false);
672 user_data
= u64_to_user_ptr(data_ptr
);
674 offset
= data_offset
;
676 mutex_unlock(&dev
->struct_mutex
);
677 if (likely(!i915
.prefault_disable
)) {
678 ret
= fault_in_multipages_writeable(user_data
, remain
);
680 mutex_lock(&dev
->struct_mutex
);
686 /* Operation in this page
688 * page_base = page offset within aperture
689 * page_offset = offset within page
690 * page_length = bytes to copy for this page
692 u32 page_base
= node
.start
;
693 unsigned page_offset
= offset_in_page(offset
);
694 unsigned page_length
= PAGE_SIZE
- page_offset
;
695 page_length
= remain
< page_length
? remain
: page_length
;
696 if (node
.allocated
) {
698 ggtt
->base
.insert_page(&ggtt
->base
,
699 i915_gem_object_get_dma_address(obj
, offset
>> PAGE_SHIFT
),
704 page_base
+= offset
& PAGE_MASK
;
706 /* This is a slow read/write as it tries to read from
707 * and write to user memory which may result into page
708 * faults, and so we cannot perform this under struct_mutex.
710 if (slow_user_access(ggtt
->mappable
, page_base
,
711 page_offset
, user_data
,
712 page_length
, false)) {
717 remain
-= page_length
;
718 user_data
+= page_length
;
719 offset
+= page_length
;
722 mutex_lock(&dev
->struct_mutex
);
723 if (ret
== 0 && (obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
) == 0) {
724 /* The user has modified the object whilst we tried
725 * reading from it, and we now have no idea what domain
726 * the pages should be in. As we have just been touching
727 * them directly, flush everything back to the GTT
730 ret
= i915_gem_object_set_to_gtt_domain(obj
, false);
734 if (node
.allocated
) {
736 ggtt
->base
.clear_range(&ggtt
->base
,
737 node
.start
, node
.size
,
739 i915_gem_object_unpin_pages(obj
);
740 remove_mappable_node(&node
);
742 i915_gem_object_ggtt_unpin(obj
);
749 i915_gem_shmem_pread(struct drm_device
*dev
,
750 struct drm_i915_gem_object
*obj
,
751 struct drm_i915_gem_pread
*args
,
752 struct drm_file
*file
)
754 char __user
*user_data
;
757 int shmem_page_offset
, page_length
, ret
= 0;
758 int obj_do_bit17_swizzling
, page_do_bit17_swizzling
;
760 int needs_clflush
= 0;
761 struct sg_page_iter sg_iter
;
763 if (!i915_gem_object_has_struct_page(obj
))
766 user_data
= u64_to_user_ptr(args
->data_ptr
);
769 obj_do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
771 ret
= i915_gem_obj_prepare_shmem_read(obj
, &needs_clflush
);
775 offset
= args
->offset
;
777 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
,
778 offset
>> PAGE_SHIFT
) {
779 struct page
*page
= sg_page_iter_page(&sg_iter
);
784 /* Operation in this page
786 * shmem_page_offset = offset within page in shmem file
787 * page_length = bytes to copy for this page
789 shmem_page_offset
= offset_in_page(offset
);
790 page_length
= remain
;
791 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
792 page_length
= PAGE_SIZE
- shmem_page_offset
;
794 page_do_bit17_swizzling
= obj_do_bit17_swizzling
&&
795 (page_to_phys(page
) & (1 << 17)) != 0;
797 ret
= shmem_pread_fast(page
, shmem_page_offset
, page_length
,
798 user_data
, page_do_bit17_swizzling
,
803 mutex_unlock(&dev
->struct_mutex
);
805 if (likely(!i915
.prefault_disable
) && !prefaulted
) {
806 ret
= fault_in_multipages_writeable(user_data
, remain
);
807 /* Userspace is tricking us, but we've already clobbered
808 * its pages with the prefault and promised to write the
809 * data up to the first fault. Hence ignore any errors
810 * and just continue. */
815 ret
= shmem_pread_slow(page
, shmem_page_offset
, page_length
,
816 user_data
, page_do_bit17_swizzling
,
819 mutex_lock(&dev
->struct_mutex
);
825 remain
-= page_length
;
826 user_data
+= page_length
;
827 offset
+= page_length
;
831 i915_gem_object_unpin_pages(obj
);
837 * Reads data from the object referenced by handle.
838 * @dev: drm device pointer
839 * @data: ioctl data blob
840 * @file: drm file pointer
842 * On error, the contents of *data are undefined.
845 i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
846 struct drm_file
*file
)
848 struct drm_i915_gem_pread
*args
= data
;
849 struct drm_i915_gem_object
*obj
;
855 if (!access_ok(VERIFY_WRITE
,
856 u64_to_user_ptr(args
->data_ptr
),
860 ret
= i915_mutex_lock_interruptible(dev
);
864 obj
= to_intel_bo(drm_gem_object_lookup(file
, args
->handle
));
865 if (&obj
->base
== NULL
) {
870 /* Bounds check source. */
871 if (args
->offset
> obj
->base
.size
||
872 args
->size
> obj
->base
.size
- args
->offset
) {
877 trace_i915_gem_object_pread(obj
, args
->offset
, args
->size
);
879 ret
= i915_gem_shmem_pread(dev
, obj
, args
, file
);
881 /* pread for non shmem backed objects */
882 if (ret
== -EFAULT
|| ret
== -ENODEV
)
883 ret
= i915_gem_gtt_pread(dev
, obj
, args
->size
,
884 args
->offset
, args
->data_ptr
);
887 drm_gem_object_unreference(&obj
->base
);
889 mutex_unlock(&dev
->struct_mutex
);
893 /* This is the fast write path which cannot handle
894 * page faults in the source data
898 fast_user_write(struct io_mapping
*mapping
,
899 loff_t page_base
, int page_offset
,
900 char __user
*user_data
,
903 void __iomem
*vaddr_atomic
;
905 unsigned long unwritten
;
907 vaddr_atomic
= io_mapping_map_atomic_wc(mapping
, page_base
);
908 /* We can use the cpu mem copy function because this is X86. */
909 vaddr
= (void __force
*)vaddr_atomic
+ page_offset
;
910 unwritten
= __copy_from_user_inatomic_nocache(vaddr
,
912 io_mapping_unmap_atomic(vaddr_atomic
);
917 * This is the fast pwrite path, where we copy the data directly from the
918 * user into the GTT, uncached.
919 * @dev: drm device pointer
920 * @obj: i915 gem object
921 * @args: pwrite arguments structure
922 * @file: drm file pointer
925 i915_gem_gtt_pwrite_fast(struct drm_i915_private
*i915
,
926 struct drm_i915_gem_object
*obj
,
927 struct drm_i915_gem_pwrite
*args
,
928 struct drm_file
*file
)
930 struct i915_ggtt
*ggtt
= &i915
->ggtt
;
931 struct drm_device
*dev
= obj
->base
.dev
;
932 struct drm_mm_node node
;
933 uint64_t remain
, offset
;
934 char __user
*user_data
;
936 bool hit_slow_path
= false;
938 if (obj
->tiling_mode
!= I915_TILING_NONE
)
941 ret
= i915_gem_obj_ggtt_pin(obj
, 0, PIN_MAPPABLE
| PIN_NONBLOCK
);
943 ret
= insert_mappable_node(i915
, &node
, PAGE_SIZE
);
947 ret
= i915_gem_object_get_pages(obj
);
949 remove_mappable_node(&node
);
953 i915_gem_object_pin_pages(obj
);
955 node
.start
= i915_gem_obj_ggtt_offset(obj
);
956 node
.allocated
= false;
957 ret
= i915_gem_object_put_fence(obj
);
962 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
966 intel_fb_obj_invalidate(obj
, ORIGIN_GTT
);
969 user_data
= u64_to_user_ptr(args
->data_ptr
);
970 offset
= args
->offset
;
973 /* Operation in this page
975 * page_base = page offset within aperture
976 * page_offset = offset within page
977 * page_length = bytes to copy for this page
979 u32 page_base
= node
.start
;
980 unsigned page_offset
= offset_in_page(offset
);
981 unsigned page_length
= PAGE_SIZE
- page_offset
;
982 page_length
= remain
< page_length
? remain
: page_length
;
983 if (node
.allocated
) {
984 wmb(); /* flush the write before we modify the GGTT */
985 ggtt
->base
.insert_page(&ggtt
->base
,
986 i915_gem_object_get_dma_address(obj
, offset
>> PAGE_SHIFT
),
987 node
.start
, I915_CACHE_NONE
, 0);
988 wmb(); /* flush modifications to the GGTT (insert_page) */
990 page_base
+= offset
& PAGE_MASK
;
992 /* If we get a fault while copying data, then (presumably) our
993 * source page isn't available. Return the error and we'll
994 * retry in the slow path.
995 * If the object is non-shmem backed, we retry again with the
996 * path that handles page fault.
998 if (fast_user_write(ggtt
->mappable
, page_base
,
999 page_offset
, user_data
, page_length
)) {
1000 hit_slow_path
= true;
1001 mutex_unlock(&dev
->struct_mutex
);
1002 if (slow_user_access(ggtt
->mappable
,
1004 page_offset
, user_data
,
1005 page_length
, true)) {
1007 mutex_lock(&dev
->struct_mutex
);
1011 mutex_lock(&dev
->struct_mutex
);
1014 remain
-= page_length
;
1015 user_data
+= page_length
;
1016 offset
+= page_length
;
1020 if (hit_slow_path
) {
1022 (obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
) == 0) {
1023 /* The user has modified the object whilst we tried
1024 * reading from it, and we now have no idea what domain
1025 * the pages should be in. As we have just been touching
1026 * them directly, flush everything back to the GTT
1029 ret
= i915_gem_object_set_to_gtt_domain(obj
, false);
1033 intel_fb_obj_flush(obj
, false, ORIGIN_GTT
);
1035 if (node
.allocated
) {
1037 ggtt
->base
.clear_range(&ggtt
->base
,
1038 node
.start
, node
.size
,
1040 i915_gem_object_unpin_pages(obj
);
1041 remove_mappable_node(&node
);
1043 i915_gem_object_ggtt_unpin(obj
);
1049 /* Per-page copy function for the shmem pwrite fastpath.
1050 * Flushes invalid cachelines before writing to the target if
1051 * needs_clflush_before is set and flushes out any written cachelines after
1052 * writing if needs_clflush is set. */
1054 shmem_pwrite_fast(struct page
*page
, int shmem_page_offset
, int page_length
,
1055 char __user
*user_data
,
1056 bool page_do_bit17_swizzling
,
1057 bool needs_clflush_before
,
1058 bool needs_clflush_after
)
1063 if (unlikely(page_do_bit17_swizzling
))
1066 vaddr
= kmap_atomic(page
);
1067 if (needs_clflush_before
)
1068 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
1070 ret
= __copy_from_user_inatomic(vaddr
+ shmem_page_offset
,
1071 user_data
, page_length
);
1072 if (needs_clflush_after
)
1073 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
1075 kunmap_atomic(vaddr
);
1077 return ret
? -EFAULT
: 0;
1080 /* Only difference to the fast-path function is that this can handle bit17
1081 * and uses non-atomic copy and kmap functions. */
1083 shmem_pwrite_slow(struct page
*page
, int shmem_page_offset
, int page_length
,
1084 char __user
*user_data
,
1085 bool page_do_bit17_swizzling
,
1086 bool needs_clflush_before
,
1087 bool needs_clflush_after
)
1093 if (unlikely(needs_clflush_before
|| page_do_bit17_swizzling
))
1094 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
1096 page_do_bit17_swizzling
);
1097 if (page_do_bit17_swizzling
)
1098 ret
= __copy_from_user_swizzled(vaddr
, shmem_page_offset
,
1102 ret
= __copy_from_user(vaddr
+ shmem_page_offset
,
1105 if (needs_clflush_after
)
1106 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
1108 page_do_bit17_swizzling
);
1111 return ret
? -EFAULT
: 0;
1115 i915_gem_shmem_pwrite(struct drm_device
*dev
,
1116 struct drm_i915_gem_object
*obj
,
1117 struct drm_i915_gem_pwrite
*args
,
1118 struct drm_file
*file
)
1122 char __user
*user_data
;
1123 int shmem_page_offset
, page_length
, ret
= 0;
1124 int obj_do_bit17_swizzling
, page_do_bit17_swizzling
;
1125 int hit_slowpath
= 0;
1126 int needs_clflush_after
= 0;
1127 int needs_clflush_before
= 0;
1128 struct sg_page_iter sg_iter
;
1130 user_data
= u64_to_user_ptr(args
->data_ptr
);
1131 remain
= args
->size
;
1133 obj_do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
1135 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
1136 /* If we're not in the cpu write domain, set ourself into the gtt
1137 * write domain and manually flush cachelines (if required). This
1138 * optimizes for the case when the gpu will use the data
1139 * right away and we therefore have to clflush anyway. */
1140 needs_clflush_after
= cpu_write_needs_clflush(obj
);
1141 ret
= i915_gem_object_wait_rendering(obj
, false);
1145 /* Same trick applies to invalidate partially written cachelines read
1146 * before writing. */
1147 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) == 0)
1148 needs_clflush_before
=
1149 !cpu_cache_is_coherent(dev
, obj
->cache_level
);
1151 ret
= i915_gem_object_get_pages(obj
);
1155 intel_fb_obj_invalidate(obj
, ORIGIN_CPU
);
1157 i915_gem_object_pin_pages(obj
);
1159 offset
= args
->offset
;
1162 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
,
1163 offset
>> PAGE_SHIFT
) {
1164 struct page
*page
= sg_page_iter_page(&sg_iter
);
1165 int partial_cacheline_write
;
1170 /* Operation in this page
1172 * shmem_page_offset = offset within page in shmem file
1173 * page_length = bytes to copy for this page
1175 shmem_page_offset
= offset_in_page(offset
);
1177 page_length
= remain
;
1178 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
1179 page_length
= PAGE_SIZE
- shmem_page_offset
;
1181 /* If we don't overwrite a cacheline completely we need to be
1182 * careful to have up-to-date data by first clflushing. Don't
1183 * overcomplicate things and flush the entire patch. */
1184 partial_cacheline_write
= needs_clflush_before
&&
1185 ((shmem_page_offset
| page_length
)
1186 & (boot_cpu_data
.x86_clflush_size
- 1));
1188 page_do_bit17_swizzling
= obj_do_bit17_swizzling
&&
1189 (page_to_phys(page
) & (1 << 17)) != 0;
1191 ret
= shmem_pwrite_fast(page
, shmem_page_offset
, page_length
,
1192 user_data
, page_do_bit17_swizzling
,
1193 partial_cacheline_write
,
1194 needs_clflush_after
);
1199 mutex_unlock(&dev
->struct_mutex
);
1200 ret
= shmem_pwrite_slow(page
, shmem_page_offset
, page_length
,
1201 user_data
, page_do_bit17_swizzling
,
1202 partial_cacheline_write
,
1203 needs_clflush_after
);
1205 mutex_lock(&dev
->struct_mutex
);
1211 remain
-= page_length
;
1212 user_data
+= page_length
;
1213 offset
+= page_length
;
1217 i915_gem_object_unpin_pages(obj
);
1221 * Fixup: Flush cpu caches in case we didn't flush the dirty
1222 * cachelines in-line while writing and the object moved
1223 * out of the cpu write domain while we've dropped the lock.
1225 if (!needs_clflush_after
&&
1226 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
1227 if (i915_gem_clflush_object(obj
, obj
->pin_display
))
1228 needs_clflush_after
= true;
1232 if (needs_clflush_after
)
1233 i915_gem_chipset_flush(to_i915(dev
));
1235 obj
->cache_dirty
= true;
1237 intel_fb_obj_flush(obj
, false, ORIGIN_CPU
);
1242 * Writes data to the object referenced by handle.
1244 * @data: ioctl data blob
1247 * On error, the contents of the buffer that were to be modified are undefined.
1250 i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
1251 struct drm_file
*file
)
1253 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1254 struct drm_i915_gem_pwrite
*args
= data
;
1255 struct drm_i915_gem_object
*obj
;
1258 if (args
->size
== 0)
1261 if (!access_ok(VERIFY_READ
,
1262 u64_to_user_ptr(args
->data_ptr
),
1266 if (likely(!i915
.prefault_disable
)) {
1267 ret
= fault_in_multipages_readable(u64_to_user_ptr(args
->data_ptr
),
1273 intel_runtime_pm_get(dev_priv
);
1275 ret
= i915_mutex_lock_interruptible(dev
);
1279 obj
= to_intel_bo(drm_gem_object_lookup(file
, args
->handle
));
1280 if (&obj
->base
== NULL
) {
1285 /* Bounds check destination. */
1286 if (args
->offset
> obj
->base
.size
||
1287 args
->size
> obj
->base
.size
- args
->offset
) {
1292 trace_i915_gem_object_pwrite(obj
, args
->offset
, args
->size
);
1295 /* We can only do the GTT pwrite on untiled buffers, as otherwise
1296 * it would end up going through the fenced access, and we'll get
1297 * different detiling behavior between reading and writing.
1298 * pread/pwrite currently are reading and writing from the CPU
1299 * perspective, requiring manual detiling by the client.
1301 if (!i915_gem_object_has_struct_page(obj
) ||
1302 cpu_write_needs_clflush(obj
)) {
1303 ret
= i915_gem_gtt_pwrite_fast(dev_priv
, obj
, args
, file
);
1304 /* Note that the gtt paths might fail with non-page-backed user
1305 * pointers (e.g. gtt mappings when moving data between
1306 * textures). Fallback to the shmem path in that case. */
1309 if (ret
== -EFAULT
) {
1310 if (obj
->phys_handle
)
1311 ret
= i915_gem_phys_pwrite(obj
, args
, file
);
1312 else if (i915_gem_object_has_struct_page(obj
))
1313 ret
= i915_gem_shmem_pwrite(dev
, obj
, args
, file
);
1319 drm_gem_object_unreference(&obj
->base
);
1321 mutex_unlock(&dev
->struct_mutex
);
1323 intel_runtime_pm_put(dev_priv
);
1329 i915_gem_check_wedge(unsigned reset_counter
, bool interruptible
)
1331 if (__i915_terminally_wedged(reset_counter
))
1334 if (__i915_reset_in_progress(reset_counter
)) {
1335 /* Non-interruptible callers can't handle -EAGAIN, hence return
1336 * -EIO unconditionally for these. */
1346 static void fake_irq(unsigned long data
)
1348 wake_up_process((struct task_struct
*)data
);
1351 static bool missed_irq(struct drm_i915_private
*dev_priv
,
1352 struct intel_engine_cs
*engine
)
1354 return test_bit(engine
->id
, &dev_priv
->gpu_error
.missed_irq_rings
);
1357 static unsigned long local_clock_us(unsigned *cpu
)
1361 /* Cheaply and approximately convert from nanoseconds to microseconds.
1362 * The result and subsequent calculations are also defined in the same
1363 * approximate microseconds units. The principal source of timing
1364 * error here is from the simple truncation.
1366 * Note that local_clock() is only defined wrt to the current CPU;
1367 * the comparisons are no longer valid if we switch CPUs. Instead of
1368 * blocking preemption for the entire busywait, we can detect the CPU
1369 * switch and use that as indicator of system load and a reason to
1370 * stop busywaiting, see busywait_stop().
1373 t
= local_clock() >> 10;
1379 static bool busywait_stop(unsigned long timeout
, unsigned cpu
)
1383 if (time_after(local_clock_us(&this_cpu
), timeout
))
1386 return this_cpu
!= cpu
;
1389 static int __i915_spin_request(struct drm_i915_gem_request
*req
, int state
)
1391 unsigned long timeout
;
1394 /* When waiting for high frequency requests, e.g. during synchronous
1395 * rendering split between the CPU and GPU, the finite amount of time
1396 * required to set up the irq and wait upon it limits the response
1397 * rate. By busywaiting on the request completion for a short while we
1398 * can service the high frequency waits as quick as possible. However,
1399 * if it is a slow request, we want to sleep as quickly as possible.
1400 * The tradeoff between waiting and sleeping is roughly the time it
1401 * takes to sleep on a request, on the order of a microsecond.
1404 if (req
->engine
->irq_refcount
)
1407 /* Only spin if we know the GPU is processing this request */
1408 if (!i915_gem_request_started(req
, true))
1411 timeout
= local_clock_us(&cpu
) + 5;
1412 while (!need_resched()) {
1413 if (i915_gem_request_completed(req
, true))
1416 if (signal_pending_state(state
, current
))
1419 if (busywait_stop(timeout
, cpu
))
1422 cpu_relax_lowlatency();
1425 if (i915_gem_request_completed(req
, false))
1432 * __i915_wait_request - wait until execution of request has finished
1434 * @interruptible: do an interruptible wait (normally yes)
1435 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
1438 * Note: It is of utmost importance that the passed in seqno and reset_counter
1439 * values have been read by the caller in an smp safe manner. Where read-side
1440 * locks are involved, it is sufficient to read the reset_counter before
1441 * unlocking the lock that protects the seqno. For lockless tricks, the
1442 * reset_counter _must_ be read before, and an appropriate smp_rmb must be
1445 * Returns 0 if the request was found within the alloted time. Else returns the
1446 * errno with remaining time filled in timeout argument.
1448 int __i915_wait_request(struct drm_i915_gem_request
*req
,
1451 struct intel_rps_client
*rps
)
1453 struct intel_engine_cs
*engine
= i915_gem_request_get_engine(req
);
1454 struct drm_i915_private
*dev_priv
= req
->i915
;
1455 const bool irq_test_in_progress
=
1456 ACCESS_ONCE(dev_priv
->gpu_error
.test_irq_rings
) & intel_engine_flag(engine
);
1457 int state
= interruptible
? TASK_INTERRUPTIBLE
: TASK_UNINTERRUPTIBLE
;
1459 unsigned long timeout_expire
;
1460 s64 before
= 0; /* Only to silence a compiler warning. */
1463 WARN(!intel_irqs_enabled(dev_priv
), "IRQs disabled");
1465 if (list_empty(&req
->list
))
1468 if (i915_gem_request_completed(req
, true))
1473 if (WARN_ON(*timeout
< 0))
1479 timeout_expire
= jiffies
+ nsecs_to_jiffies_timeout(*timeout
);
1482 * Record current time in case interrupted by signal, or wedged.
1484 before
= ktime_get_raw_ns();
1487 if (INTEL_INFO(dev_priv
)->gen
>= 6)
1488 gen6_rps_boost(dev_priv
, rps
, req
->emitted_jiffies
);
1490 trace_i915_gem_request_wait_begin(req
);
1492 /* Optimistic spin for the next jiffie before touching IRQs */
1493 ret
= __i915_spin_request(req
, state
);
1497 if (!irq_test_in_progress
&& WARN_ON(!engine
->irq_get(engine
))) {
1503 struct timer_list timer
;
1505 prepare_to_wait(&engine
->irq_queue
, &wait
, state
);
1507 /* We need to check whether any gpu reset happened in between
1508 * the request being submitted and now. If a reset has occurred,
1509 * the seqno will have been advance past ours and our request
1510 * is complete. If we are in the process of handling a reset,
1511 * the request is effectively complete as the rendering will
1512 * be discarded, but we need to return in order to drop the
1515 if (i915_reset_in_progress(&dev_priv
->gpu_error
)) {
1520 if (i915_gem_request_completed(req
, false)) {
1525 if (signal_pending_state(state
, current
)) {
1530 if (timeout
&& time_after_eq(jiffies
, timeout_expire
)) {
1535 /* Ensure that even if the GPU hangs, we get woken up.
1537 * However, note that if no one is waiting, we never notice
1538 * a gpu hang. Eventually, we will have to wait for a resource
1539 * held by the GPU and so trigger a hangcheck. In the most
1540 * pathological case, this will be upon memory starvation!
1542 i915_queue_hangcheck(dev_priv
);
1544 timer
.function
= NULL
;
1545 if (timeout
|| missed_irq(dev_priv
, engine
)) {
1546 unsigned long expire
;
1548 setup_timer_on_stack(&timer
, fake_irq
, (unsigned long)current
);
1549 expire
= missed_irq(dev_priv
, engine
) ? jiffies
+ 1 : timeout_expire
;
1550 mod_timer(&timer
, expire
);
1555 if (timer
.function
) {
1556 del_singleshot_timer_sync(&timer
);
1557 destroy_timer_on_stack(&timer
);
1560 if (!irq_test_in_progress
)
1561 engine
->irq_put(engine
);
1563 finish_wait(&engine
->irq_queue
, &wait
);
1566 trace_i915_gem_request_wait_end(req
);
1569 s64 tres
= *timeout
- (ktime_get_raw_ns() - before
);
1571 *timeout
= tres
< 0 ? 0 : tres
;
1574 * Apparently ktime isn't accurate enough and occasionally has a
1575 * bit of mismatch in the jiffies<->nsecs<->ktime loop. So patch
1576 * things up to make the test happy. We allow up to 1 jiffy.
1578 * This is a regrssion from the timespec->ktime conversion.
1580 if (ret
== -ETIME
&& *timeout
< jiffies_to_usecs(1)*1000)
1587 int i915_gem_request_add_to_client(struct drm_i915_gem_request
*req
,
1588 struct drm_file
*file
)
1590 struct drm_i915_file_private
*file_priv
;
1592 WARN_ON(!req
|| !file
|| req
->file_priv
);
1600 file_priv
= file
->driver_priv
;
1602 spin_lock(&file_priv
->mm
.lock
);
1603 req
->file_priv
= file_priv
;
1604 list_add_tail(&req
->client_list
, &file_priv
->mm
.request_list
);
1605 spin_unlock(&file_priv
->mm
.lock
);
1607 req
->pid
= get_pid(task_pid(current
));
1613 i915_gem_request_remove_from_client(struct drm_i915_gem_request
*request
)
1615 struct drm_i915_file_private
*file_priv
= request
->file_priv
;
1620 spin_lock(&file_priv
->mm
.lock
);
1621 list_del(&request
->client_list
);
1622 request
->file_priv
= NULL
;
1623 spin_unlock(&file_priv
->mm
.lock
);
1625 put_pid(request
->pid
);
1626 request
->pid
= NULL
;
1629 static void i915_gem_request_retire(struct drm_i915_gem_request
*request
)
1631 trace_i915_gem_request_retire(request
);
1633 /* We know the GPU must have read the request to have
1634 * sent us the seqno + interrupt, so use the position
1635 * of tail of the request to update the last known position
1638 * Note this requires that we are always called in request
1641 request
->ringbuf
->last_retired_head
= request
->postfix
;
1643 list_del_init(&request
->list
);
1644 i915_gem_request_remove_from_client(request
);
1646 if (request
->previous_context
) {
1647 if (i915
.enable_execlists
)
1648 intel_lr_context_unpin(request
->previous_context
,
1652 i915_gem_context_unreference(request
->ctx
);
1653 i915_gem_request_unreference(request
);
1657 __i915_gem_request_retire__upto(struct drm_i915_gem_request
*req
)
1659 struct intel_engine_cs
*engine
= req
->engine
;
1660 struct drm_i915_gem_request
*tmp
;
1662 lockdep_assert_held(&engine
->i915
->dev
->struct_mutex
);
1664 if (list_empty(&req
->list
))
1668 tmp
= list_first_entry(&engine
->request_list
,
1669 typeof(*tmp
), list
);
1671 i915_gem_request_retire(tmp
);
1672 } while (tmp
!= req
);
1674 WARN_ON(i915_verify_lists(engine
->dev
));
1678 * Waits for a request to be signaled, and cleans up the
1679 * request and object lists appropriately for that event.
1680 * @req: request to wait on
1683 i915_wait_request(struct drm_i915_gem_request
*req
)
1685 struct drm_i915_private
*dev_priv
= req
->i915
;
1689 interruptible
= dev_priv
->mm
.interruptible
;
1691 BUG_ON(!mutex_is_locked(&dev_priv
->dev
->struct_mutex
));
1693 ret
= __i915_wait_request(req
, interruptible
, NULL
, NULL
);
1697 /* If the GPU hung, we want to keep the requests to find the guilty. */
1698 if (!i915_reset_in_progress(&dev_priv
->gpu_error
))
1699 __i915_gem_request_retire__upto(req
);
1705 * Ensures that all rendering to the object has completed and the object is
1706 * safe to unbind from the GTT or access from the CPU.
1707 * @obj: i915 gem object
1708 * @readonly: waiting for read access or write
1711 i915_gem_object_wait_rendering(struct drm_i915_gem_object
*obj
,
1720 if (obj
->last_write_req
!= NULL
) {
1721 ret
= i915_wait_request(obj
->last_write_req
);
1725 i
= obj
->last_write_req
->engine
->id
;
1726 if (obj
->last_read_req
[i
] == obj
->last_write_req
)
1727 i915_gem_object_retire__read(obj
, i
);
1729 i915_gem_object_retire__write(obj
);
1732 for (i
= 0; i
< I915_NUM_ENGINES
; i
++) {
1733 if (obj
->last_read_req
[i
] == NULL
)
1736 ret
= i915_wait_request(obj
->last_read_req
[i
]);
1740 i915_gem_object_retire__read(obj
, i
);
1742 GEM_BUG_ON(obj
->active
);
1749 i915_gem_object_retire_request(struct drm_i915_gem_object
*obj
,
1750 struct drm_i915_gem_request
*req
)
1752 int ring
= req
->engine
->id
;
1754 if (obj
->last_read_req
[ring
] == req
)
1755 i915_gem_object_retire__read(obj
, ring
);
1756 else if (obj
->last_write_req
== req
)
1757 i915_gem_object_retire__write(obj
);
1759 if (!i915_reset_in_progress(&req
->i915
->gpu_error
))
1760 __i915_gem_request_retire__upto(req
);
1763 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1764 * as the object state may change during this call.
1766 static __must_check
int
1767 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object
*obj
,
1768 struct intel_rps_client
*rps
,
1771 struct drm_device
*dev
= obj
->base
.dev
;
1772 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1773 struct drm_i915_gem_request
*requests
[I915_NUM_ENGINES
];
1776 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
1777 BUG_ON(!dev_priv
->mm
.interruptible
);
1783 struct drm_i915_gem_request
*req
;
1785 req
= obj
->last_write_req
;
1789 requests
[n
++] = i915_gem_request_reference(req
);
1791 for (i
= 0; i
< I915_NUM_ENGINES
; i
++) {
1792 struct drm_i915_gem_request
*req
;
1794 req
= obj
->last_read_req
[i
];
1798 requests
[n
++] = i915_gem_request_reference(req
);
1802 mutex_unlock(&dev
->struct_mutex
);
1804 for (i
= 0; ret
== 0 && i
< n
; i
++)
1805 ret
= __i915_wait_request(requests
[i
], true, NULL
, rps
);
1806 mutex_lock(&dev
->struct_mutex
);
1808 for (i
= 0; i
< n
; i
++) {
1810 i915_gem_object_retire_request(obj
, requests
[i
]);
1811 i915_gem_request_unreference(requests
[i
]);
1817 static struct intel_rps_client
*to_rps_client(struct drm_file
*file
)
1819 struct drm_i915_file_private
*fpriv
= file
->driver_priv
;
1823 static enum fb_op_origin
1824 write_origin(struct drm_i915_gem_object
*obj
, unsigned domain
)
1826 return domain
== I915_GEM_DOMAIN_GTT
&& !obj
->has_wc_mmap
?
1827 ORIGIN_GTT
: ORIGIN_CPU
;
1831 * Called when user space prepares to use an object with the CPU, either
1832 * through the mmap ioctl's mapping or a GTT mapping.
1834 * @data: ioctl data blob
1838 i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
1839 struct drm_file
*file
)
1841 struct drm_i915_gem_set_domain
*args
= data
;
1842 struct drm_i915_gem_object
*obj
;
1843 uint32_t read_domains
= args
->read_domains
;
1844 uint32_t write_domain
= args
->write_domain
;
1847 /* Only handle setting domains to types used by the CPU. */
1848 if (write_domain
& I915_GEM_GPU_DOMAINS
)
1851 if (read_domains
& I915_GEM_GPU_DOMAINS
)
1854 /* Having something in the write domain implies it's in the read
1855 * domain, and only that read domain. Enforce that in the request.
1857 if (write_domain
!= 0 && read_domains
!= write_domain
)
1860 ret
= i915_mutex_lock_interruptible(dev
);
1864 obj
= to_intel_bo(drm_gem_object_lookup(file
, args
->handle
));
1865 if (&obj
->base
== NULL
) {
1870 /* Try to flush the object off the GPU without holding the lock.
1871 * We will repeat the flush holding the lock in the normal manner
1872 * to catch cases where we are gazumped.
1874 ret
= i915_gem_object_wait_rendering__nonblocking(obj
,
1875 to_rps_client(file
),
1880 if (read_domains
& I915_GEM_DOMAIN_GTT
)
1881 ret
= i915_gem_object_set_to_gtt_domain(obj
, write_domain
!= 0);
1883 ret
= i915_gem_object_set_to_cpu_domain(obj
, write_domain
!= 0);
1885 if (write_domain
!= 0)
1886 intel_fb_obj_invalidate(obj
, write_origin(obj
, write_domain
));
1889 drm_gem_object_unreference(&obj
->base
);
1891 mutex_unlock(&dev
->struct_mutex
);
1896 * Called when user space has done writes to this buffer
1898 * @data: ioctl data blob
1902 i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1903 struct drm_file
*file
)
1905 struct drm_i915_gem_sw_finish
*args
= data
;
1906 struct drm_i915_gem_object
*obj
;
1909 ret
= i915_mutex_lock_interruptible(dev
);
1913 obj
= to_intel_bo(drm_gem_object_lookup(file
, args
->handle
));
1914 if (&obj
->base
== NULL
) {
1919 /* Pinned buffers may be scanout, so flush the cache */
1920 if (obj
->pin_display
)
1921 i915_gem_object_flush_cpu_write_domain(obj
);
1923 drm_gem_object_unreference(&obj
->base
);
1925 mutex_unlock(&dev
->struct_mutex
);
1930 * i915_gem_mmap_ioctl - Maps the contents of an object, returning the address
1933 * @data: ioctl data blob
1936 * While the mapping holds a reference on the contents of the object, it doesn't
1937 * imply a ref on the object itself.
1941 * DRM driver writers who look a this function as an example for how to do GEM
1942 * mmap support, please don't implement mmap support like here. The modern way
1943 * to implement DRM mmap support is with an mmap offset ioctl (like
1944 * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly.
1945 * That way debug tooling like valgrind will understand what's going on, hiding
1946 * the mmap call in a driver private ioctl will break that. The i915 driver only
1947 * does cpu mmaps this way because we didn't know better.
1950 i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1951 struct drm_file
*file
)
1953 struct drm_i915_gem_mmap
*args
= data
;
1954 struct drm_gem_object
*obj
;
1957 if (args
->flags
& ~(I915_MMAP_WC
))
1960 if (args
->flags
& I915_MMAP_WC
&& !boot_cpu_has(X86_FEATURE_PAT
))
1963 obj
= drm_gem_object_lookup(file
, args
->handle
);
1967 /* prime objects have no backing filp to GEM mmap
1971 drm_gem_object_unreference_unlocked(obj
);
1975 addr
= vm_mmap(obj
->filp
, 0, args
->size
,
1976 PROT_READ
| PROT_WRITE
, MAP_SHARED
,
1978 if (args
->flags
& I915_MMAP_WC
) {
1979 struct mm_struct
*mm
= current
->mm
;
1980 struct vm_area_struct
*vma
;
1982 if (down_write_killable(&mm
->mmap_sem
)) {
1983 drm_gem_object_unreference_unlocked(obj
);
1986 vma
= find_vma(mm
, addr
);
1989 pgprot_writecombine(vm_get_page_prot(vma
->vm_flags
));
1992 up_write(&mm
->mmap_sem
);
1994 /* This may race, but that's ok, it only gets set */
1995 WRITE_ONCE(to_intel_bo(obj
)->has_wc_mmap
, true);
1997 drm_gem_object_unreference_unlocked(obj
);
1998 if (IS_ERR((void *)addr
))
2001 args
->addr_ptr
= (uint64_t) addr
;
2007 * i915_gem_fault - fault a page into the GTT
2008 * @vma: VMA in question
2011 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
2012 * from userspace. The fault handler takes care of binding the object to
2013 * the GTT (if needed), allocating and programming a fence register (again,
2014 * only if needed based on whether the old reg is still valid or the object
2015 * is tiled) and inserting a new PTE into the faulting process.
2017 * Note that the faulting process may involve evicting existing objects
2018 * from the GTT and/or fence registers to make room. So performance may
2019 * suffer if the GTT working set is large or there are few fence registers
2022 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
)
2024 struct drm_i915_gem_object
*obj
= to_intel_bo(vma
->vm_private_data
);
2025 struct drm_device
*dev
= obj
->base
.dev
;
2026 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2027 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
2028 struct i915_ggtt_view view
= i915_ggtt_view_normal
;
2029 pgoff_t page_offset
;
2032 bool write
= !!(vmf
->flags
& FAULT_FLAG_WRITE
);
2034 intel_runtime_pm_get(dev_priv
);
2036 /* We don't use vmf->pgoff since that has the fake offset */
2037 page_offset
= ((unsigned long)vmf
->virtual_address
- vma
->vm_start
) >>
2040 ret
= i915_mutex_lock_interruptible(dev
);
2044 trace_i915_gem_object_fault(obj
, page_offset
, true, write
);
2046 /* Try to flush the object off the GPU first without holding the lock.
2047 * Upon reacquiring the lock, we will perform our sanity checks and then
2048 * repeat the flush holding the lock in the normal manner to catch cases
2049 * where we are gazumped.
2051 ret
= i915_gem_object_wait_rendering__nonblocking(obj
, NULL
, !write
);
2055 /* Access to snoopable pages through the GTT is incoherent. */
2056 if (obj
->cache_level
!= I915_CACHE_NONE
&& !HAS_LLC(dev
)) {
2061 /* Use a partial view if the object is bigger than the aperture. */
2062 if (obj
->base
.size
>= ggtt
->mappable_end
&&
2063 obj
->tiling_mode
== I915_TILING_NONE
) {
2064 static const unsigned int chunk_size
= 256; // 1 MiB
2066 memset(&view
, 0, sizeof(view
));
2067 view
.type
= I915_GGTT_VIEW_PARTIAL
;
2068 view
.params
.partial
.offset
= rounddown(page_offset
, chunk_size
);
2069 view
.params
.partial
.size
=
2072 (vma
->vm_end
- vma
->vm_start
)/PAGE_SIZE
-
2073 view
.params
.partial
.offset
);
2076 /* Now pin it into the GTT if needed */
2077 ret
= i915_gem_object_ggtt_pin(obj
, &view
, 0, PIN_MAPPABLE
);
2081 ret
= i915_gem_object_set_to_gtt_domain(obj
, write
);
2085 ret
= i915_gem_object_get_fence(obj
);
2089 /* Finally, remap it using the new GTT offset */
2090 pfn
= ggtt
->mappable_base
+
2091 i915_gem_obj_ggtt_offset_view(obj
, &view
);
2094 if (unlikely(view
.type
== I915_GGTT_VIEW_PARTIAL
)) {
2095 /* Overriding existing pages in partial view does not cause
2096 * us any trouble as TLBs are still valid because the fault
2097 * is due to userspace losing part of the mapping or never
2098 * having accessed it before (at this partials' range).
2100 unsigned long base
= vma
->vm_start
+
2101 (view
.params
.partial
.offset
<< PAGE_SHIFT
);
2104 for (i
= 0; i
< view
.params
.partial
.size
; i
++) {
2105 ret
= vm_insert_pfn(vma
, base
+ i
* PAGE_SIZE
, pfn
+ i
);
2110 obj
->fault_mappable
= true;
2112 if (!obj
->fault_mappable
) {
2113 unsigned long size
= min_t(unsigned long,
2114 vma
->vm_end
- vma
->vm_start
,
2118 for (i
= 0; i
< size
>> PAGE_SHIFT
; i
++) {
2119 ret
= vm_insert_pfn(vma
,
2120 (unsigned long)vma
->vm_start
+ i
* PAGE_SIZE
,
2126 obj
->fault_mappable
= true;
2128 ret
= vm_insert_pfn(vma
,
2129 (unsigned long)vmf
->virtual_address
,
2133 i915_gem_object_ggtt_unpin_view(obj
, &view
);
2135 mutex_unlock(&dev
->struct_mutex
);
2140 * We eat errors when the gpu is terminally wedged to avoid
2141 * userspace unduly crashing (gl has no provisions for mmaps to
2142 * fail). But any other -EIO isn't ours (e.g. swap in failure)
2143 * and so needs to be reported.
2145 if (!i915_terminally_wedged(&dev_priv
->gpu_error
)) {
2146 ret
= VM_FAULT_SIGBUS
;
2151 * EAGAIN means the gpu is hung and we'll wait for the error
2152 * handler to reset everything when re-faulting in
2153 * i915_mutex_lock_interruptible.
2160 * EBUSY is ok: this just means that another thread
2161 * already did the job.
2163 ret
= VM_FAULT_NOPAGE
;
2170 ret
= VM_FAULT_SIGBUS
;
2173 WARN_ONCE(ret
, "unhandled error in i915_gem_fault: %i\n", ret
);
2174 ret
= VM_FAULT_SIGBUS
;
2178 intel_runtime_pm_put(dev_priv
);
2183 * i915_gem_release_mmap - remove physical page mappings
2184 * @obj: obj in question
2186 * Preserve the reservation of the mmapping with the DRM core code, but
2187 * relinquish ownership of the pages back to the system.
2189 * It is vital that we remove the page mapping if we have mapped a tiled
2190 * object through the GTT and then lose the fence register due to
2191 * resource pressure. Similarly if the object has been moved out of the
2192 * aperture, than pages mapped into userspace must be revoked. Removing the
2193 * mapping will then trigger a page fault on the next user access, allowing
2194 * fixup by i915_gem_fault().
2197 i915_gem_release_mmap(struct drm_i915_gem_object
*obj
)
2199 /* Serialisation between user GTT access and our code depends upon
2200 * revoking the CPU's PTE whilst the mutex is held. The next user
2201 * pagefault then has to wait until we release the mutex.
2203 lockdep_assert_held(&obj
->base
.dev
->struct_mutex
);
2205 if (!obj
->fault_mappable
)
2208 drm_vma_node_unmap(&obj
->base
.vma_node
,
2209 obj
->base
.dev
->anon_inode
->i_mapping
);
2211 /* Ensure that the CPU's PTE are revoked and there are not outstanding
2212 * memory transactions from userspace before we return. The TLB
2213 * flushing implied above by changing the PTE above *should* be
2214 * sufficient, an extra barrier here just provides us with a bit
2215 * of paranoid documentation about our requirement to serialise
2216 * memory writes before touching registers / GSM.
2220 obj
->fault_mappable
= false;
2224 i915_gem_release_all_mmaps(struct drm_i915_private
*dev_priv
)
2226 struct drm_i915_gem_object
*obj
;
2228 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
)
2229 i915_gem_release_mmap(obj
);
2233 i915_gem_get_gtt_size(struct drm_device
*dev
, uint32_t size
, int tiling_mode
)
2237 if (INTEL_INFO(dev
)->gen
>= 4 ||
2238 tiling_mode
== I915_TILING_NONE
)
2241 /* Previous chips need a power-of-two fence region when tiling */
2243 gtt_size
= 1024*1024;
2245 gtt_size
= 512*1024;
2247 while (gtt_size
< size
)
2254 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
2256 * @size: object size
2257 * @tiling_mode: tiling mode
2258 * @fenced: is fenced alignemned required or not
2260 * Return the required GTT alignment for an object, taking into account
2261 * potential fence register mapping.
2264 i915_gem_get_gtt_alignment(struct drm_device
*dev
, uint32_t size
,
2265 int tiling_mode
, bool fenced
)
2268 * Minimum alignment is 4k (GTT page size), but might be greater
2269 * if a fence register is needed for the object.
2271 if (INTEL_INFO(dev
)->gen
>= 4 || (!fenced
&& IS_G33(dev
)) ||
2272 tiling_mode
== I915_TILING_NONE
)
2276 * Previous chips need to be aligned to the size of the smallest
2277 * fence register that can contain the object.
2279 return i915_gem_get_gtt_size(dev
, size
, tiling_mode
);
2282 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object
*obj
)
2284 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2287 dev_priv
->mm
.shrinker_no_lock_stealing
= true;
2289 ret
= drm_gem_create_mmap_offset(&obj
->base
);
2293 /* Badly fragmented mmap space? The only way we can recover
2294 * space is by destroying unwanted objects. We can't randomly release
2295 * mmap_offsets as userspace expects them to be persistent for the
2296 * lifetime of the objects. The closest we can is to release the
2297 * offsets on purgeable objects by truncating it and marking it purged,
2298 * which prevents userspace from ever using that object again.
2300 i915_gem_shrink(dev_priv
,
2301 obj
->base
.size
>> PAGE_SHIFT
,
2303 I915_SHRINK_UNBOUND
|
2304 I915_SHRINK_PURGEABLE
);
2305 ret
= drm_gem_create_mmap_offset(&obj
->base
);
2309 i915_gem_shrink_all(dev_priv
);
2310 ret
= drm_gem_create_mmap_offset(&obj
->base
);
2312 dev_priv
->mm
.shrinker_no_lock_stealing
= false;
2317 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object
*obj
)
2319 drm_gem_free_mmap_offset(&obj
->base
);
2323 i915_gem_mmap_gtt(struct drm_file
*file
,
2324 struct drm_device
*dev
,
2328 struct drm_i915_gem_object
*obj
;
2331 ret
= i915_mutex_lock_interruptible(dev
);
2335 obj
= to_intel_bo(drm_gem_object_lookup(file
, handle
));
2336 if (&obj
->base
== NULL
) {
2341 if (obj
->madv
!= I915_MADV_WILLNEED
) {
2342 DRM_DEBUG("Attempting to mmap a purgeable buffer\n");
2347 ret
= i915_gem_object_create_mmap_offset(obj
);
2351 *offset
= drm_vma_node_offset_addr(&obj
->base
.vma_node
);
2354 drm_gem_object_unreference(&obj
->base
);
2356 mutex_unlock(&dev
->struct_mutex
);
2361 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
2363 * @data: GTT mapping ioctl data
2364 * @file: GEM object info
2366 * Simply returns the fake offset to userspace so it can mmap it.
2367 * The mmap call will end up in drm_gem_mmap(), which will set things
2368 * up so we can get faults in the handler above.
2370 * The fault handler will take care of binding the object into the GTT
2371 * (since it may have been evicted to make room for something), allocating
2372 * a fence register, and mapping the appropriate aperture address into
2376 i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
2377 struct drm_file
*file
)
2379 struct drm_i915_gem_mmap_gtt
*args
= data
;
2381 return i915_gem_mmap_gtt(file
, dev
, args
->handle
, &args
->offset
);
2384 /* Immediately discard the backing storage */
2386 i915_gem_object_truncate(struct drm_i915_gem_object
*obj
)
2388 i915_gem_object_free_mmap_offset(obj
);
2390 if (obj
->base
.filp
== NULL
)
2393 /* Our goal here is to return as much of the memory as
2394 * is possible back to the system as we are called from OOM.
2395 * To do this we must instruct the shmfs to drop all of its
2396 * backing pages, *now*.
2398 shmem_truncate_range(file_inode(obj
->base
.filp
), 0, (loff_t
)-1);
2399 obj
->madv
= __I915_MADV_PURGED
;
2402 /* Try to discard unwanted pages */
2404 i915_gem_object_invalidate(struct drm_i915_gem_object
*obj
)
2406 struct address_space
*mapping
;
2408 switch (obj
->madv
) {
2409 case I915_MADV_DONTNEED
:
2410 i915_gem_object_truncate(obj
);
2411 case __I915_MADV_PURGED
:
2415 if (obj
->base
.filp
== NULL
)
2418 mapping
= file_inode(obj
->base
.filp
)->i_mapping
,
2419 invalidate_mapping_pages(mapping
, 0, (loff_t
)-1);
2423 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object
*obj
)
2425 struct sgt_iter sgt_iter
;
2429 BUG_ON(obj
->madv
== __I915_MADV_PURGED
);
2431 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
2433 /* In the event of a disaster, abandon all caches and
2434 * hope for the best.
2436 i915_gem_clflush_object(obj
, true);
2437 obj
->base
.read_domains
= obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
2440 i915_gem_gtt_finish_object(obj
);
2442 if (i915_gem_object_needs_bit17_swizzle(obj
))
2443 i915_gem_object_save_bit_17_swizzle(obj
);
2445 if (obj
->madv
== I915_MADV_DONTNEED
)
2448 for_each_sgt_page(page
, sgt_iter
, obj
->pages
) {
2450 set_page_dirty(page
);
2452 if (obj
->madv
== I915_MADV_WILLNEED
)
2453 mark_page_accessed(page
);
2459 sg_free_table(obj
->pages
);
2464 i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
)
2466 const struct drm_i915_gem_object_ops
*ops
= obj
->ops
;
2468 if (obj
->pages
== NULL
)
2471 if (obj
->pages_pin_count
)
2474 BUG_ON(i915_gem_obj_bound_any(obj
));
2476 /* ->put_pages might need to allocate memory for the bit17 swizzle
2477 * array, hence protect them from being reaped by removing them from gtt
2479 list_del(&obj
->global_list
);
2482 if (is_vmalloc_addr(obj
->mapping
))
2483 vunmap(obj
->mapping
);
2485 kunmap(kmap_to_page(obj
->mapping
));
2486 obj
->mapping
= NULL
;
2489 ops
->put_pages(obj
);
2492 i915_gem_object_invalidate(obj
);
2498 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object
*obj
)
2500 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2502 struct address_space
*mapping
;
2503 struct sg_table
*st
;
2504 struct scatterlist
*sg
;
2505 struct sgt_iter sgt_iter
;
2507 unsigned long last_pfn
= 0; /* suppress gcc warning */
2511 /* Assert that the object is not currently in any GPU domain. As it
2512 * wasn't in the GTT, there shouldn't be any way it could have been in
2515 BUG_ON(obj
->base
.read_domains
& I915_GEM_GPU_DOMAINS
);
2516 BUG_ON(obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
);
2518 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
2522 page_count
= obj
->base
.size
/ PAGE_SIZE
;
2523 if (sg_alloc_table(st
, page_count
, GFP_KERNEL
)) {
2528 /* Get the list of pages out of our struct file. They'll be pinned
2529 * at this point until we release them.
2531 * Fail silently without starting the shrinker
2533 mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
2534 gfp
= mapping_gfp_constraint(mapping
, ~(__GFP_IO
| __GFP_RECLAIM
));
2535 gfp
|= __GFP_NORETRY
| __GFP_NOWARN
;
2538 for (i
= 0; i
< page_count
; i
++) {
2539 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
2541 i915_gem_shrink(dev_priv
,
2544 I915_SHRINK_UNBOUND
|
2545 I915_SHRINK_PURGEABLE
);
2546 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
2549 /* We've tried hard to allocate the memory by reaping
2550 * our own buffer, now let the real VM do its job and
2551 * go down in flames if truly OOM.
2553 i915_gem_shrink_all(dev_priv
);
2554 page
= shmem_read_mapping_page(mapping
, i
);
2556 ret
= PTR_ERR(page
);
2560 #ifdef CONFIG_SWIOTLB
2561 if (swiotlb_nr_tbl()) {
2563 sg_set_page(sg
, page
, PAGE_SIZE
, 0);
2568 if (!i
|| page_to_pfn(page
) != last_pfn
+ 1) {
2572 sg_set_page(sg
, page
, PAGE_SIZE
, 0);
2574 sg
->length
+= PAGE_SIZE
;
2576 last_pfn
= page_to_pfn(page
);
2578 /* Check that the i965g/gm workaround works. */
2579 WARN_ON((gfp
& __GFP_DMA32
) && (last_pfn
>= 0x00100000UL
));
2581 #ifdef CONFIG_SWIOTLB
2582 if (!swiotlb_nr_tbl())
2587 ret
= i915_gem_gtt_prepare_object(obj
);
2591 if (i915_gem_object_needs_bit17_swizzle(obj
))
2592 i915_gem_object_do_bit_17_swizzle(obj
);
2594 if (obj
->tiling_mode
!= I915_TILING_NONE
&&
2595 dev_priv
->quirks
& QUIRK_PIN_SWIZZLED_PAGES
)
2596 i915_gem_object_pin_pages(obj
);
2602 for_each_sgt_page(page
, sgt_iter
, st
)
2607 /* shmemfs first checks if there is enough memory to allocate the page
2608 * and reports ENOSPC should there be insufficient, along with the usual
2609 * ENOMEM for a genuine allocation failure.
2611 * We use ENOSPC in our driver to mean that we have run out of aperture
2612 * space and so want to translate the error from shmemfs back to our
2613 * usual understanding of ENOMEM.
2621 /* Ensure that the associated pages are gathered from the backing storage
2622 * and pinned into our object. i915_gem_object_get_pages() may be called
2623 * multiple times before they are released by a single call to
2624 * i915_gem_object_put_pages() - once the pages are no longer referenced
2625 * either as a result of memory pressure (reaping pages under the shrinker)
2626 * or as the object is itself released.
2629 i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
)
2631 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2632 const struct drm_i915_gem_object_ops
*ops
= obj
->ops
;
2638 if (obj
->madv
!= I915_MADV_WILLNEED
) {
2639 DRM_DEBUG("Attempting to obtain a purgeable object\n");
2643 BUG_ON(obj
->pages_pin_count
);
2645 ret
= ops
->get_pages(obj
);
2649 list_add_tail(&obj
->global_list
, &dev_priv
->mm
.unbound_list
);
2651 obj
->get_page
.sg
= obj
->pages
->sgl
;
2652 obj
->get_page
.last
= 0;
2657 /* The 'mapping' part of i915_gem_object_pin_map() below */
2658 static void *i915_gem_object_map(const struct drm_i915_gem_object
*obj
)
2660 unsigned long n_pages
= obj
->base
.size
>> PAGE_SHIFT
;
2661 struct sg_table
*sgt
= obj
->pages
;
2662 struct sgt_iter sgt_iter
;
2664 struct page
*stack_pages
[32];
2665 struct page
**pages
= stack_pages
;
2666 unsigned long i
= 0;
2669 /* A single page can always be kmapped */
2671 return kmap(sg_page(sgt
->sgl
));
2673 if (n_pages
> ARRAY_SIZE(stack_pages
)) {
2674 /* Too big for stack -- allocate temporary array instead */
2675 pages
= drm_malloc_gfp(n_pages
, sizeof(*pages
), GFP_TEMPORARY
);
2680 for_each_sgt_page(page
, sgt_iter
, sgt
)
2683 /* Check that we have the expected number of pages */
2684 GEM_BUG_ON(i
!= n_pages
);
2686 addr
= vmap(pages
, n_pages
, 0, PAGE_KERNEL
);
2688 if (pages
!= stack_pages
)
2689 drm_free_large(pages
);
2694 /* get, pin, and map the pages of the object into kernel space */
2695 void *i915_gem_object_pin_map(struct drm_i915_gem_object
*obj
)
2699 lockdep_assert_held(&obj
->base
.dev
->struct_mutex
);
2701 ret
= i915_gem_object_get_pages(obj
);
2703 return ERR_PTR(ret
);
2705 i915_gem_object_pin_pages(obj
);
2707 if (!obj
->mapping
) {
2708 obj
->mapping
= i915_gem_object_map(obj
);
2709 if (!obj
->mapping
) {
2710 i915_gem_object_unpin_pages(obj
);
2711 return ERR_PTR(-ENOMEM
);
2715 return obj
->mapping
;
2718 void i915_vma_move_to_active(struct i915_vma
*vma
,
2719 struct drm_i915_gem_request
*req
)
2721 struct drm_i915_gem_object
*obj
= vma
->obj
;
2722 struct intel_engine_cs
*engine
;
2724 engine
= i915_gem_request_get_engine(req
);
2726 /* Add a reference if we're newly entering the active list. */
2727 if (obj
->active
== 0)
2728 drm_gem_object_reference(&obj
->base
);
2729 obj
->active
|= intel_engine_flag(engine
);
2731 list_move_tail(&obj
->engine_list
[engine
->id
], &engine
->active_list
);
2732 i915_gem_request_assign(&obj
->last_read_req
[engine
->id
], req
);
2734 list_move_tail(&vma
->vm_link
, &vma
->vm
->active_list
);
2738 i915_gem_object_retire__write(struct drm_i915_gem_object
*obj
)
2740 GEM_BUG_ON(obj
->last_write_req
== NULL
);
2741 GEM_BUG_ON(!(obj
->active
& intel_engine_flag(obj
->last_write_req
->engine
)));
2743 i915_gem_request_assign(&obj
->last_write_req
, NULL
);
2744 intel_fb_obj_flush(obj
, true, ORIGIN_CS
);
2748 i915_gem_object_retire__read(struct drm_i915_gem_object
*obj
, int ring
)
2750 struct i915_vma
*vma
;
2752 GEM_BUG_ON(obj
->last_read_req
[ring
] == NULL
);
2753 GEM_BUG_ON(!(obj
->active
& (1 << ring
)));
2755 list_del_init(&obj
->engine_list
[ring
]);
2756 i915_gem_request_assign(&obj
->last_read_req
[ring
], NULL
);
2758 if (obj
->last_write_req
&& obj
->last_write_req
->engine
->id
== ring
)
2759 i915_gem_object_retire__write(obj
);
2761 obj
->active
&= ~(1 << ring
);
2765 /* Bump our place on the bound list to keep it roughly in LRU order
2766 * so that we don't steal from recently used but inactive objects
2767 * (unless we are forced to ofc!)
2769 list_move_tail(&obj
->global_list
,
2770 &to_i915(obj
->base
.dev
)->mm
.bound_list
);
2772 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
) {
2773 if (!list_empty(&vma
->vm_link
))
2774 list_move_tail(&vma
->vm_link
, &vma
->vm
->inactive_list
);
2777 i915_gem_request_assign(&obj
->last_fenced_req
, NULL
);
2778 drm_gem_object_unreference(&obj
->base
);
2782 i915_gem_init_seqno(struct drm_i915_private
*dev_priv
, u32 seqno
)
2784 struct intel_engine_cs
*engine
;
2787 /* Carefully retire all requests without writing to the rings */
2788 for_each_engine(engine
, dev_priv
) {
2789 ret
= intel_engine_idle(engine
);
2793 i915_gem_retire_requests(dev_priv
);
2795 /* Finally reset hw state */
2796 for_each_engine(engine
, dev_priv
)
2797 intel_ring_init_seqno(engine
, seqno
);
2802 int i915_gem_set_seqno(struct drm_device
*dev
, u32 seqno
)
2804 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2810 /* HWS page needs to be set less than what we
2811 * will inject to ring
2813 ret
= i915_gem_init_seqno(dev_priv
, seqno
- 1);
2817 /* Carefully set the last_seqno value so that wrap
2818 * detection still works
2820 dev_priv
->next_seqno
= seqno
;
2821 dev_priv
->last_seqno
= seqno
- 1;
2822 if (dev_priv
->last_seqno
== 0)
2823 dev_priv
->last_seqno
--;
2829 i915_gem_get_seqno(struct drm_i915_private
*dev_priv
, u32
*seqno
)
2831 /* reserve 0 for non-seqno */
2832 if (dev_priv
->next_seqno
== 0) {
2833 int ret
= i915_gem_init_seqno(dev_priv
, 0);
2837 dev_priv
->next_seqno
= 1;
2840 *seqno
= dev_priv
->last_seqno
= dev_priv
->next_seqno
++;
2845 * NB: This function is not allowed to fail. Doing so would mean the the
2846 * request is not being tracked for completion but the work itself is
2847 * going to happen on the hardware. This would be a Bad Thing(tm).
2849 void __i915_add_request(struct drm_i915_gem_request
*request
,
2850 struct drm_i915_gem_object
*obj
,
2853 struct intel_engine_cs
*engine
;
2854 struct drm_i915_private
*dev_priv
;
2855 struct intel_ringbuffer
*ringbuf
;
2860 if (WARN_ON(request
== NULL
))
2863 engine
= request
->engine
;
2864 dev_priv
= request
->i915
;
2865 ringbuf
= request
->ringbuf
;
2868 * To ensure that this call will not fail, space for its emissions
2869 * should already have been reserved in the ring buffer. Let the ring
2870 * know that it is time to use that space up.
2872 request_start
= intel_ring_get_tail(ringbuf
);
2873 reserved_tail
= request
->reserved_space
;
2874 request
->reserved_space
= 0;
2877 * Emit any outstanding flushes - execbuf can fail to emit the flush
2878 * after having emitted the batchbuffer command. Hence we need to fix
2879 * things up similar to emitting the lazy request. The difference here
2880 * is that the flush _must_ happen before the next request, no matter
2884 if (i915
.enable_execlists
)
2885 ret
= logical_ring_flush_all_caches(request
);
2887 ret
= intel_ring_flush_all_caches(request
);
2888 /* Not allowed to fail! */
2889 WARN(ret
, "*_ring_flush_all_caches failed: %d!\n", ret
);
2892 trace_i915_gem_request_add(request
);
2894 request
->head
= request_start
;
2896 /* Whilst this request exists, batch_obj will be on the
2897 * active_list, and so will hold the active reference. Only when this
2898 * request is retired will the the batch_obj be moved onto the
2899 * inactive_list and lose its active reference. Hence we do not need
2900 * to explicitly hold another reference here.
2902 request
->batch_obj
= obj
;
2904 /* Seal the request and mark it as pending execution. Note that
2905 * we may inspect this state, without holding any locks, during
2906 * hangcheck. Hence we apply the barrier to ensure that we do not
2907 * see a more recent value in the hws than we are tracking.
2909 request
->emitted_jiffies
= jiffies
;
2910 request
->previous_seqno
= engine
->last_submitted_seqno
;
2911 smp_store_mb(engine
->last_submitted_seqno
, request
->seqno
);
2912 list_add_tail(&request
->list
, &engine
->request_list
);
2914 /* Record the position of the start of the request so that
2915 * should we detect the updated seqno part-way through the
2916 * GPU processing the request, we never over-estimate the
2917 * position of the head.
2919 request
->postfix
= intel_ring_get_tail(ringbuf
);
2921 if (i915
.enable_execlists
)
2922 ret
= engine
->emit_request(request
);
2924 ret
= engine
->add_request(request
);
2926 request
->tail
= intel_ring_get_tail(ringbuf
);
2928 /* Not allowed to fail! */
2929 WARN(ret
, "emit|add_request failed: %d!\n", ret
);
2931 queue_delayed_work(dev_priv
->wq
,
2932 &dev_priv
->mm
.retire_work
,
2933 round_jiffies_up_relative(HZ
));
2934 intel_mark_busy(dev_priv
);
2936 /* Sanity check that the reserved size was large enough. */
2937 ret
= intel_ring_get_tail(ringbuf
) - request_start
;
2939 ret
+= ringbuf
->size
;
2940 WARN_ONCE(ret
> reserved_tail
,
2941 "Not enough space reserved (%d bytes) "
2942 "for adding the request (%d bytes)\n",
2943 reserved_tail
, ret
);
2946 static bool i915_context_is_banned(struct drm_i915_private
*dev_priv
,
2947 const struct i915_gem_context
*ctx
)
2949 unsigned long elapsed
;
2951 elapsed
= get_seconds() - ctx
->hang_stats
.guilty_ts
;
2953 if (ctx
->hang_stats
.banned
)
2956 if (ctx
->hang_stats
.ban_period_seconds
&&
2957 elapsed
<= ctx
->hang_stats
.ban_period_seconds
) {
2958 if (!i915_gem_context_is_default(ctx
)) {
2959 DRM_DEBUG("context hanging too fast, banning!\n");
2961 } else if (i915_stop_ring_allow_ban(dev_priv
)) {
2962 if (i915_stop_ring_allow_warn(dev_priv
))
2963 DRM_ERROR("gpu hanging too fast, banning!\n");
2971 static void i915_set_reset_status(struct drm_i915_private
*dev_priv
,
2972 struct i915_gem_context
*ctx
,
2975 struct i915_ctx_hang_stats
*hs
;
2980 hs
= &ctx
->hang_stats
;
2983 hs
->banned
= i915_context_is_banned(dev_priv
, ctx
);
2985 hs
->guilty_ts
= get_seconds();
2987 hs
->batch_pending
++;
2991 void i915_gem_request_free(struct kref
*req_ref
)
2993 struct drm_i915_gem_request
*req
= container_of(req_ref
,
2995 kmem_cache_free(req
->i915
->requests
, req
);
2999 __i915_gem_request_alloc(struct intel_engine_cs
*engine
,
3000 struct i915_gem_context
*ctx
,
3001 struct drm_i915_gem_request
**req_out
)
3003 struct drm_i915_private
*dev_priv
= engine
->i915
;
3004 unsigned reset_counter
= i915_reset_counter(&dev_priv
->gpu_error
);
3005 struct drm_i915_gem_request
*req
;
3013 /* ABI: Before userspace accesses the GPU (e.g. execbuffer), report
3014 * EIO if the GPU is already wedged, or EAGAIN to drop the struct_mutex
3017 ret
= i915_gem_check_wedge(reset_counter
, dev_priv
->mm
.interruptible
);
3021 req
= kmem_cache_zalloc(dev_priv
->requests
, GFP_KERNEL
);
3025 ret
= i915_gem_get_seqno(engine
->i915
, &req
->seqno
);
3029 kref_init(&req
->ref
);
3030 req
->i915
= dev_priv
;
3031 req
->engine
= engine
;
3033 i915_gem_context_reference(req
->ctx
);
3036 * Reserve space in the ring buffer for all the commands required to
3037 * eventually emit this request. This is to guarantee that the
3038 * i915_add_request() call can't fail. Note that the reserve may need
3039 * to be redone if the request is not actually submitted straight
3040 * away, e.g. because a GPU scheduler has deferred it.
3042 req
->reserved_space
= MIN_SPACE_FOR_ADD_REQUEST
;
3044 if (i915
.enable_execlists
)
3045 ret
= intel_logical_ring_alloc_request_extras(req
);
3047 ret
= intel_ring_alloc_request_extras(req
);
3055 i915_gem_context_unreference(ctx
);
3057 kmem_cache_free(dev_priv
->requests
, req
);
3062 * i915_gem_request_alloc - allocate a request structure
3064 * @engine: engine that we wish to issue the request on.
3065 * @ctx: context that the request will be associated with.
3066 * This can be NULL if the request is not directly related to
3067 * any specific user context, in which case this function will
3068 * choose an appropriate context to use.
3070 * Returns a pointer to the allocated request if successful,
3071 * or an error code if not.
3073 struct drm_i915_gem_request
*
3074 i915_gem_request_alloc(struct intel_engine_cs
*engine
,
3075 struct i915_gem_context
*ctx
)
3077 struct drm_i915_gem_request
*req
;
3081 ctx
= engine
->i915
->kernel_context
;
3082 err
= __i915_gem_request_alloc(engine
, ctx
, &req
);
3083 return err
? ERR_PTR(err
) : req
;
3086 struct drm_i915_gem_request
*
3087 i915_gem_find_active_request(struct intel_engine_cs
*engine
)
3089 struct drm_i915_gem_request
*request
;
3091 list_for_each_entry(request
, &engine
->request_list
, list
) {
3092 if (i915_gem_request_completed(request
, false))
3101 static void i915_gem_reset_engine_status(struct drm_i915_private
*dev_priv
,
3102 struct intel_engine_cs
*engine
)
3104 struct drm_i915_gem_request
*request
;
3107 request
= i915_gem_find_active_request(engine
);
3109 if (request
== NULL
)
3112 ring_hung
= engine
->hangcheck
.score
>= HANGCHECK_SCORE_RING_HUNG
;
3114 i915_set_reset_status(dev_priv
, request
->ctx
, ring_hung
);
3116 list_for_each_entry_continue(request
, &engine
->request_list
, list
)
3117 i915_set_reset_status(dev_priv
, request
->ctx
, false);
3120 static void i915_gem_reset_engine_cleanup(struct drm_i915_private
*dev_priv
,
3121 struct intel_engine_cs
*engine
)
3123 struct intel_ringbuffer
*buffer
;
3125 while (!list_empty(&engine
->active_list
)) {
3126 struct drm_i915_gem_object
*obj
;
3128 obj
= list_first_entry(&engine
->active_list
,
3129 struct drm_i915_gem_object
,
3130 engine_list
[engine
->id
]);
3132 i915_gem_object_retire__read(obj
, engine
->id
);
3136 * Clear the execlists queue up before freeing the requests, as those
3137 * are the ones that keep the context and ringbuffer backing objects
3141 if (i915
.enable_execlists
) {
3142 /* Ensure irq handler finishes or is cancelled. */
3143 tasklet_kill(&engine
->irq_tasklet
);
3145 intel_execlists_cancel_requests(engine
);
3149 * We must free the requests after all the corresponding objects have
3150 * been moved off active lists. Which is the same order as the normal
3151 * retire_requests function does. This is important if object hold
3152 * implicit references on things like e.g. ppgtt address spaces through
3155 while (!list_empty(&engine
->request_list
)) {
3156 struct drm_i915_gem_request
*request
;
3158 request
= list_first_entry(&engine
->request_list
,
3159 struct drm_i915_gem_request
,
3162 i915_gem_request_retire(request
);
3165 /* Having flushed all requests from all queues, we know that all
3166 * ringbuffers must now be empty. However, since we do not reclaim
3167 * all space when retiring the request (to prevent HEADs colliding
3168 * with rapid ringbuffer wraparound) the amount of available space
3169 * upon reset is less than when we start. Do one more pass over
3170 * all the ringbuffers to reset last_retired_head.
3172 list_for_each_entry(buffer
, &engine
->buffers
, link
) {
3173 buffer
->last_retired_head
= buffer
->tail
;
3174 intel_ring_update_space(buffer
);
3177 intel_ring_init_seqno(engine
, engine
->last_submitted_seqno
);
3180 void i915_gem_reset(struct drm_device
*dev
)
3182 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3183 struct intel_engine_cs
*engine
;
3186 * Before we free the objects from the requests, we need to inspect
3187 * them for finding the guilty party. As the requests only borrow
3188 * their reference to the objects, the inspection must be done first.
3190 for_each_engine(engine
, dev_priv
)
3191 i915_gem_reset_engine_status(dev_priv
, engine
);
3193 for_each_engine(engine
, dev_priv
)
3194 i915_gem_reset_engine_cleanup(dev_priv
, engine
);
3196 i915_gem_context_reset(dev
);
3198 i915_gem_restore_fences(dev
);
3200 WARN_ON(i915_verify_lists(dev
));
3204 * This function clears the request list as sequence numbers are passed.
3205 * @engine: engine to retire requests on
3208 i915_gem_retire_requests_ring(struct intel_engine_cs
*engine
)
3210 WARN_ON(i915_verify_lists(engine
->dev
));
3212 /* Retire requests first as we use it above for the early return.
3213 * If we retire requests last, we may use a later seqno and so clear
3214 * the requests lists without clearing the active list, leading to
3217 while (!list_empty(&engine
->request_list
)) {
3218 struct drm_i915_gem_request
*request
;
3220 request
= list_first_entry(&engine
->request_list
,
3221 struct drm_i915_gem_request
,
3224 if (!i915_gem_request_completed(request
, true))
3227 i915_gem_request_retire(request
);
3230 /* Move any buffers on the active list that are no longer referenced
3231 * by the ringbuffer to the flushing/inactive lists as appropriate,
3232 * before we free the context associated with the requests.
3234 while (!list_empty(&engine
->active_list
)) {
3235 struct drm_i915_gem_object
*obj
;
3237 obj
= list_first_entry(&engine
->active_list
,
3238 struct drm_i915_gem_object
,
3239 engine_list
[engine
->id
]);
3241 if (!list_empty(&obj
->last_read_req
[engine
->id
]->list
))
3244 i915_gem_object_retire__read(obj
, engine
->id
);
3247 if (unlikely(engine
->trace_irq_req
&&
3248 i915_gem_request_completed(engine
->trace_irq_req
, true))) {
3249 engine
->irq_put(engine
);
3250 i915_gem_request_assign(&engine
->trace_irq_req
, NULL
);
3253 WARN_ON(i915_verify_lists(engine
->dev
));
3257 i915_gem_retire_requests(struct drm_i915_private
*dev_priv
)
3259 struct intel_engine_cs
*engine
;
3262 for_each_engine(engine
, dev_priv
) {
3263 i915_gem_retire_requests_ring(engine
);
3264 idle
&= list_empty(&engine
->request_list
);
3265 if (i915
.enable_execlists
) {
3266 spin_lock_bh(&engine
->execlist_lock
);
3267 idle
&= list_empty(&engine
->execlist_queue
);
3268 spin_unlock_bh(&engine
->execlist_lock
);
3273 mod_delayed_work(dev_priv
->wq
,
3274 &dev_priv
->mm
.idle_work
,
3275 msecs_to_jiffies(100));
3281 i915_gem_retire_work_handler(struct work_struct
*work
)
3283 struct drm_i915_private
*dev_priv
=
3284 container_of(work
, typeof(*dev_priv
), mm
.retire_work
.work
);
3285 struct drm_device
*dev
= dev_priv
->dev
;
3288 /* Come back later if the device is busy... */
3290 if (mutex_trylock(&dev
->struct_mutex
)) {
3291 idle
= i915_gem_retire_requests(dev_priv
);
3292 mutex_unlock(&dev
->struct_mutex
);
3295 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
,
3296 round_jiffies_up_relative(HZ
));
3300 i915_gem_idle_work_handler(struct work_struct
*work
)
3302 struct drm_i915_private
*dev_priv
=
3303 container_of(work
, typeof(*dev_priv
), mm
.idle_work
.work
);
3304 struct drm_device
*dev
= dev_priv
->dev
;
3305 struct intel_engine_cs
*engine
;
3307 for_each_engine(engine
, dev_priv
)
3308 if (!list_empty(&engine
->request_list
))
3311 /* we probably should sync with hangcheck here, using cancel_work_sync.
3312 * Also locking seems to be fubar here, engine->request_list is protected
3313 * by dev->struct_mutex. */
3315 intel_mark_idle(dev_priv
);
3317 if (mutex_trylock(&dev
->struct_mutex
)) {
3318 for_each_engine(engine
, dev_priv
)
3319 i915_gem_batch_pool_fini(&engine
->batch_pool
);
3321 mutex_unlock(&dev
->struct_mutex
);
3326 * Ensures that an object will eventually get non-busy by flushing any required
3327 * write domains, emitting any outstanding lazy request and retiring and
3328 * completed requests.
3329 * @obj: object to flush
3332 i915_gem_object_flush_active(struct drm_i915_gem_object
*obj
)
3339 for (i
= 0; i
< I915_NUM_ENGINES
; i
++) {
3340 struct drm_i915_gem_request
*req
;
3342 req
= obj
->last_read_req
[i
];
3346 if (i915_gem_request_completed(req
, true))
3347 i915_gem_object_retire__read(obj
, i
);
3354 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
3355 * @dev: drm device pointer
3356 * @data: ioctl data blob
3357 * @file: drm file pointer
3359 * Returns 0 if successful, else an error is returned with the remaining time in
3360 * the timeout parameter.
3361 * -ETIME: object is still busy after timeout
3362 * -ERESTARTSYS: signal interrupted the wait
3363 * -ENONENT: object doesn't exist
3364 * Also possible, but rare:
3365 * -EAGAIN: GPU wedged
3367 * -ENODEV: Internal IRQ fail
3368 * -E?: The add request failed
3370 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
3371 * non-zero timeout parameter the wait ioctl will wait for the given number of
3372 * nanoseconds on an object becoming unbusy. Since the wait itself does so
3373 * without holding struct_mutex the object may become re-busied before this
3374 * function completes. A similar but shorter * race condition exists in the busy
3378 i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
, struct drm_file
*file
)
3380 struct drm_i915_gem_wait
*args
= data
;
3381 struct drm_i915_gem_object
*obj
;
3382 struct drm_i915_gem_request
*req
[I915_NUM_ENGINES
];
3386 if (args
->flags
!= 0)
3389 ret
= i915_mutex_lock_interruptible(dev
);
3393 obj
= to_intel_bo(drm_gem_object_lookup(file
, args
->bo_handle
));
3394 if (&obj
->base
== NULL
) {
3395 mutex_unlock(&dev
->struct_mutex
);
3399 /* Need to make sure the object gets inactive eventually. */
3400 ret
= i915_gem_object_flush_active(obj
);
3407 /* Do this after OLR check to make sure we make forward progress polling
3408 * on this IOCTL with a timeout == 0 (like busy ioctl)
3410 if (args
->timeout_ns
== 0) {
3415 drm_gem_object_unreference(&obj
->base
);
3417 for (i
= 0; i
< I915_NUM_ENGINES
; i
++) {
3418 if (obj
->last_read_req
[i
] == NULL
)
3421 req
[n
++] = i915_gem_request_reference(obj
->last_read_req
[i
]);
3424 mutex_unlock(&dev
->struct_mutex
);
3426 for (i
= 0; i
< n
; i
++) {
3428 ret
= __i915_wait_request(req
[i
], true,
3429 args
->timeout_ns
> 0 ? &args
->timeout_ns
: NULL
,
3430 to_rps_client(file
));
3431 i915_gem_request_unreference(req
[i
]);
3436 drm_gem_object_unreference(&obj
->base
);
3437 mutex_unlock(&dev
->struct_mutex
);
3442 __i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
3443 struct intel_engine_cs
*to
,
3444 struct drm_i915_gem_request
*from_req
,
3445 struct drm_i915_gem_request
**to_req
)
3447 struct intel_engine_cs
*from
;
3450 from
= i915_gem_request_get_engine(from_req
);
3454 if (i915_gem_request_completed(from_req
, true))
3457 if (!i915_semaphore_is_enabled(to_i915(obj
->base
.dev
))) {
3458 struct drm_i915_private
*i915
= to_i915(obj
->base
.dev
);
3459 ret
= __i915_wait_request(from_req
,
3460 i915
->mm
.interruptible
,
3462 &i915
->rps
.semaphores
);
3466 i915_gem_object_retire_request(obj
, from_req
);
3468 int idx
= intel_ring_sync_index(from
, to
);
3469 u32 seqno
= i915_gem_request_get_seqno(from_req
);
3473 if (seqno
<= from
->semaphore
.sync_seqno
[idx
])
3476 if (*to_req
== NULL
) {
3477 struct drm_i915_gem_request
*req
;
3479 req
= i915_gem_request_alloc(to
, NULL
);
3481 return PTR_ERR(req
);
3486 trace_i915_gem_ring_sync_to(*to_req
, from
, from_req
);
3487 ret
= to
->semaphore
.sync_to(*to_req
, from
, seqno
);
3491 /* We use last_read_req because sync_to()
3492 * might have just caused seqno wrap under
3495 from
->semaphore
.sync_seqno
[idx
] =
3496 i915_gem_request_get_seqno(obj
->last_read_req
[from
->id
]);
3503 * i915_gem_object_sync - sync an object to a ring.
3505 * @obj: object which may be in use on another ring.
3506 * @to: ring we wish to use the object on. May be NULL.
3507 * @to_req: request we wish to use the object for. See below.
3508 * This will be allocated and returned if a request is
3509 * required but not passed in.
3511 * This code is meant to abstract object synchronization with the GPU.
3512 * Calling with NULL implies synchronizing the object with the CPU
3513 * rather than a particular GPU ring. Conceptually we serialise writes
3514 * between engines inside the GPU. We only allow one engine to write
3515 * into a buffer at any time, but multiple readers. To ensure each has
3516 * a coherent view of memory, we must:
3518 * - If there is an outstanding write request to the object, the new
3519 * request must wait for it to complete (either CPU or in hw, requests
3520 * on the same ring will be naturally ordered).
3522 * - If we are a write request (pending_write_domain is set), the new
3523 * request must wait for outstanding read requests to complete.
3525 * For CPU synchronisation (NULL to) no request is required. For syncing with
3526 * rings to_req must be non-NULL. However, a request does not have to be
3527 * pre-allocated. If *to_req is NULL and sync commands will be emitted then a
3528 * request will be allocated automatically and returned through *to_req. Note
3529 * that it is not guaranteed that commands will be emitted (because the system
3530 * might already be idle). Hence there is no need to create a request that
3531 * might never have any work submitted. Note further that if a request is
3532 * returned in *to_req, it is the responsibility of the caller to submit
3533 * that request (after potentially adding more work to it).
3535 * Returns 0 if successful, else propagates up the lower layer error.
3538 i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
3539 struct intel_engine_cs
*to
,
3540 struct drm_i915_gem_request
**to_req
)
3542 const bool readonly
= obj
->base
.pending_write_domain
== 0;
3543 struct drm_i915_gem_request
*req
[I915_NUM_ENGINES
];
3550 return i915_gem_object_wait_rendering(obj
, readonly
);
3554 if (obj
->last_write_req
)
3555 req
[n
++] = obj
->last_write_req
;
3557 for (i
= 0; i
< I915_NUM_ENGINES
; i
++)
3558 if (obj
->last_read_req
[i
])
3559 req
[n
++] = obj
->last_read_req
[i
];
3561 for (i
= 0; i
< n
; i
++) {
3562 ret
= __i915_gem_object_sync(obj
, to
, req
[i
], to_req
);
3570 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object
*obj
)
3572 u32 old_write_domain
, old_read_domains
;
3574 /* Force a pagefault for domain tracking on next user access */
3575 i915_gem_release_mmap(obj
);
3577 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
) == 0)
3580 old_read_domains
= obj
->base
.read_domains
;
3581 old_write_domain
= obj
->base
.write_domain
;
3583 obj
->base
.read_domains
&= ~I915_GEM_DOMAIN_GTT
;
3584 obj
->base
.write_domain
&= ~I915_GEM_DOMAIN_GTT
;
3586 trace_i915_gem_object_change_domain(obj
,
3591 static void __i915_vma_iounmap(struct i915_vma
*vma
)
3593 GEM_BUG_ON(vma
->pin_count
);
3595 if (vma
->iomap
== NULL
)
3598 io_mapping_unmap(vma
->iomap
);
3602 static int __i915_vma_unbind(struct i915_vma
*vma
, bool wait
)
3604 struct drm_i915_gem_object
*obj
= vma
->obj
;
3605 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
3608 if (list_empty(&vma
->obj_link
))
3611 if (!drm_mm_node_allocated(&vma
->node
)) {
3612 i915_gem_vma_destroy(vma
);
3619 BUG_ON(obj
->pages
== NULL
);
3622 ret
= i915_gem_object_wait_rendering(obj
, false);
3627 if (vma
->is_ggtt
&& vma
->ggtt_view
.type
== I915_GGTT_VIEW_NORMAL
) {
3628 i915_gem_object_finish_gtt(obj
);
3630 /* release the fence reg _after_ flushing */
3631 ret
= i915_gem_object_put_fence(obj
);
3635 __i915_vma_iounmap(vma
);
3638 trace_i915_vma_unbind(vma
);
3640 vma
->vm
->unbind_vma(vma
);
3643 list_del_init(&vma
->vm_link
);
3645 if (vma
->ggtt_view
.type
== I915_GGTT_VIEW_NORMAL
) {
3646 obj
->map_and_fenceable
= false;
3647 } else if (vma
->ggtt_view
.pages
) {
3648 sg_free_table(vma
->ggtt_view
.pages
);
3649 kfree(vma
->ggtt_view
.pages
);
3651 vma
->ggtt_view
.pages
= NULL
;
3654 drm_mm_remove_node(&vma
->node
);
3655 i915_gem_vma_destroy(vma
);
3657 /* Since the unbound list is global, only move to that list if
3658 * no more VMAs exist. */
3659 if (list_empty(&obj
->vma_list
))
3660 list_move_tail(&obj
->global_list
, &dev_priv
->mm
.unbound_list
);
3662 /* And finally now the object is completely decoupled from this vma,
3663 * we can drop its hold on the backing storage and allow it to be
3664 * reaped by the shrinker.
3666 i915_gem_object_unpin_pages(obj
);
3671 int i915_vma_unbind(struct i915_vma
*vma
)
3673 return __i915_vma_unbind(vma
, true);
3676 int __i915_vma_unbind_no_wait(struct i915_vma
*vma
)
3678 return __i915_vma_unbind(vma
, false);
3681 int i915_gem_wait_for_idle(struct drm_i915_private
*dev_priv
)
3683 struct intel_engine_cs
*engine
;
3686 lockdep_assert_held(&dev_priv
->dev
->struct_mutex
);
3688 for_each_engine(engine
, dev_priv
) {
3689 if (engine
->last_context
== NULL
)
3692 ret
= intel_engine_idle(engine
);
3697 WARN_ON(i915_verify_lists(dev
));
3701 static bool i915_gem_valid_gtt_space(struct i915_vma
*vma
,
3702 unsigned long cache_level
)
3704 struct drm_mm_node
*gtt_space
= &vma
->node
;
3705 struct drm_mm_node
*other
;
3708 * On some machines we have to be careful when putting differing types
3709 * of snoopable memory together to avoid the prefetcher crossing memory
3710 * domains and dying. During vm initialisation, we decide whether or not
3711 * these constraints apply and set the drm_mm.color_adjust
3714 if (vma
->vm
->mm
.color_adjust
== NULL
)
3717 if (!drm_mm_node_allocated(gtt_space
))
3720 if (list_empty(>t_space
->node_list
))
3723 other
= list_entry(gtt_space
->node_list
.prev
, struct drm_mm_node
, node_list
);
3724 if (other
->allocated
&& !other
->hole_follows
&& other
->color
!= cache_level
)
3727 other
= list_entry(gtt_space
->node_list
.next
, struct drm_mm_node
, node_list
);
3728 if (other
->allocated
&& !gtt_space
->hole_follows
&& other
->color
!= cache_level
)
3735 * Finds free space in the GTT aperture and binds the object or a view of it
3737 * @obj: object to bind
3738 * @vm: address space to bind into
3739 * @ggtt_view: global gtt view if applicable
3740 * @alignment: requested alignment
3741 * @flags: mask of PIN_* flags to use
3743 static struct i915_vma
*
3744 i915_gem_object_bind_to_vm(struct drm_i915_gem_object
*obj
,
3745 struct i915_address_space
*vm
,
3746 const struct i915_ggtt_view
*ggtt_view
,
3750 struct drm_device
*dev
= obj
->base
.dev
;
3751 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3752 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
3753 u32 fence_alignment
, unfenced_alignment
;
3754 u32 search_flag
, alloc_flag
;
3756 u64 size
, fence_size
;
3757 struct i915_vma
*vma
;
3760 if (i915_is_ggtt(vm
)) {
3763 if (WARN_ON(!ggtt_view
))
3764 return ERR_PTR(-EINVAL
);
3766 view_size
= i915_ggtt_view_size(obj
, ggtt_view
);
3768 fence_size
= i915_gem_get_gtt_size(dev
,
3771 fence_alignment
= i915_gem_get_gtt_alignment(dev
,
3775 unfenced_alignment
= i915_gem_get_gtt_alignment(dev
,
3779 size
= flags
& PIN_MAPPABLE
? fence_size
: view_size
;
3781 fence_size
= i915_gem_get_gtt_size(dev
,
3784 fence_alignment
= i915_gem_get_gtt_alignment(dev
,
3788 unfenced_alignment
=
3789 i915_gem_get_gtt_alignment(dev
,
3793 size
= flags
& PIN_MAPPABLE
? fence_size
: obj
->base
.size
;
3796 start
= flags
& PIN_OFFSET_BIAS
? flags
& PIN_OFFSET_MASK
: 0;
3798 if (flags
& PIN_MAPPABLE
)
3799 end
= min_t(u64
, end
, ggtt
->mappable_end
);
3800 if (flags
& PIN_ZONE_4G
)
3801 end
= min_t(u64
, end
, (1ULL << 32) - PAGE_SIZE
);
3804 alignment
= flags
& PIN_MAPPABLE
? fence_alignment
:
3806 if (flags
& PIN_MAPPABLE
&& alignment
& (fence_alignment
- 1)) {
3807 DRM_DEBUG("Invalid object (view type=%u) alignment requested %u\n",
3808 ggtt_view
? ggtt_view
->type
: 0,
3810 return ERR_PTR(-EINVAL
);
3813 /* If binding the object/GGTT view requires more space than the entire
3814 * aperture has, reject it early before evicting everything in a vain
3815 * attempt to find space.
3818 DRM_DEBUG("Attempting to bind an object (view type=%u) larger than the aperture: size=%llu > %s aperture=%llu\n",
3819 ggtt_view
? ggtt_view
->type
: 0,
3821 flags
& PIN_MAPPABLE
? "mappable" : "total",
3823 return ERR_PTR(-E2BIG
);
3826 ret
= i915_gem_object_get_pages(obj
);
3828 return ERR_PTR(ret
);
3830 i915_gem_object_pin_pages(obj
);
3832 vma
= ggtt_view
? i915_gem_obj_lookup_or_create_ggtt_vma(obj
, ggtt_view
) :
3833 i915_gem_obj_lookup_or_create_vma(obj
, vm
);
3838 if (flags
& PIN_OFFSET_FIXED
) {
3839 uint64_t offset
= flags
& PIN_OFFSET_MASK
;
3841 if (offset
& (alignment
- 1) || offset
+ size
> end
) {
3845 vma
->node
.start
= offset
;
3846 vma
->node
.size
= size
;
3847 vma
->node
.color
= obj
->cache_level
;
3848 ret
= drm_mm_reserve_node(&vm
->mm
, &vma
->node
);
3850 ret
= i915_gem_evict_for_vma(vma
);
3852 ret
= drm_mm_reserve_node(&vm
->mm
, &vma
->node
);
3857 if (flags
& PIN_HIGH
) {
3858 search_flag
= DRM_MM_SEARCH_BELOW
;
3859 alloc_flag
= DRM_MM_CREATE_TOP
;
3861 search_flag
= DRM_MM_SEARCH_DEFAULT
;
3862 alloc_flag
= DRM_MM_CREATE_DEFAULT
;
3866 ret
= drm_mm_insert_node_in_range_generic(&vm
->mm
, &vma
->node
,
3873 ret
= i915_gem_evict_something(dev
, vm
, size
, alignment
,
3883 if (WARN_ON(!i915_gem_valid_gtt_space(vma
, obj
->cache_level
))) {
3885 goto err_remove_node
;
3888 trace_i915_vma_bind(vma
, flags
);
3889 ret
= i915_vma_bind(vma
, obj
->cache_level
, flags
);
3891 goto err_remove_node
;
3893 list_move_tail(&obj
->global_list
, &dev_priv
->mm
.bound_list
);
3894 list_add_tail(&vma
->vm_link
, &vm
->inactive_list
);
3899 drm_mm_remove_node(&vma
->node
);
3901 i915_gem_vma_destroy(vma
);
3904 i915_gem_object_unpin_pages(obj
);
3909 i915_gem_clflush_object(struct drm_i915_gem_object
*obj
,
3912 /* If we don't have a page list set up, then we're not pinned
3913 * to GPU, and we can ignore the cache flush because it'll happen
3914 * again at bind time.
3916 if (obj
->pages
== NULL
)
3920 * Stolen memory is always coherent with the GPU as it is explicitly
3921 * marked as wc by the system, or the system is cache-coherent.
3923 if (obj
->stolen
|| obj
->phys_handle
)
3926 /* If the GPU is snooping the contents of the CPU cache,
3927 * we do not need to manually clear the CPU cache lines. However,
3928 * the caches are only snooped when the render cache is
3929 * flushed/invalidated. As we always have to emit invalidations
3930 * and flushes when moving into and out of the RENDER domain, correct
3931 * snooping behaviour occurs naturally as the result of our domain
3934 if (!force
&& cpu_cache_is_coherent(obj
->base
.dev
, obj
->cache_level
)) {
3935 obj
->cache_dirty
= true;
3939 trace_i915_gem_object_clflush(obj
);
3940 drm_clflush_sg(obj
->pages
);
3941 obj
->cache_dirty
= false;
3946 /** Flushes the GTT write domain for the object if it's dirty. */
3948 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
)
3950 uint32_t old_write_domain
;
3952 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_GTT
)
3955 /* No actual flushing is required for the GTT write domain. Writes
3956 * to it immediately go to main memory as far as we know, so there's
3957 * no chipset flush. It also doesn't land in render cache.
3959 * However, we do have to enforce the order so that all writes through
3960 * the GTT land before any writes to the device, such as updates to
3965 old_write_domain
= obj
->base
.write_domain
;
3966 obj
->base
.write_domain
= 0;
3968 intel_fb_obj_flush(obj
, false, ORIGIN_GTT
);
3970 trace_i915_gem_object_change_domain(obj
,
3971 obj
->base
.read_domains
,
3975 /** Flushes the CPU write domain for the object if it's dirty. */
3977 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
)
3979 uint32_t old_write_domain
;
3981 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
)
3984 if (i915_gem_clflush_object(obj
, obj
->pin_display
))
3985 i915_gem_chipset_flush(to_i915(obj
->base
.dev
));
3987 old_write_domain
= obj
->base
.write_domain
;
3988 obj
->base
.write_domain
= 0;
3990 intel_fb_obj_flush(obj
, false, ORIGIN_CPU
);
3992 trace_i915_gem_object_change_domain(obj
,
3993 obj
->base
.read_domains
,
3998 * Moves a single object to the GTT read, and possibly write domain.
3999 * @obj: object to act on
4000 * @write: ask for write access or read only
4002 * This function returns when the move is complete, including waiting on
4006 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
, bool write
)
4008 struct drm_device
*dev
= obj
->base
.dev
;
4009 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4010 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
4011 uint32_t old_write_domain
, old_read_domains
;
4012 struct i915_vma
*vma
;
4015 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_GTT
)
4018 ret
= i915_gem_object_wait_rendering(obj
, !write
);
4022 /* Flush and acquire obj->pages so that we are coherent through
4023 * direct access in memory with previous cached writes through
4024 * shmemfs and that our cache domain tracking remains valid.
4025 * For example, if the obj->filp was moved to swap without us
4026 * being notified and releasing the pages, we would mistakenly
4027 * continue to assume that the obj remained out of the CPU cached
4030 ret
= i915_gem_object_get_pages(obj
);
4034 i915_gem_object_flush_cpu_write_domain(obj
);
4036 /* Serialise direct access to this object with the barriers for
4037 * coherent writes from the GPU, by effectively invalidating the
4038 * GTT domain upon first access.
4040 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
) == 0)
4043 old_write_domain
= obj
->base
.write_domain
;
4044 old_read_domains
= obj
->base
.read_domains
;
4046 /* It should now be out of any other write domains, and we can update
4047 * the domain values for our changes.
4049 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
4050 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
4052 obj
->base
.read_domains
= I915_GEM_DOMAIN_GTT
;
4053 obj
->base
.write_domain
= I915_GEM_DOMAIN_GTT
;
4057 trace_i915_gem_object_change_domain(obj
,
4061 /* And bump the LRU for this access */
4062 vma
= i915_gem_obj_to_ggtt(obj
);
4063 if (vma
&& drm_mm_node_allocated(&vma
->node
) && !obj
->active
)
4064 list_move_tail(&vma
->vm_link
,
4065 &ggtt
->base
.inactive_list
);
4071 * Changes the cache-level of an object across all VMA.
4072 * @obj: object to act on
4073 * @cache_level: new cache level to set for the object
4075 * After this function returns, the object will be in the new cache-level
4076 * across all GTT and the contents of the backing storage will be coherent,
4077 * with respect to the new cache-level. In order to keep the backing storage
4078 * coherent for all users, we only allow a single cache level to be set
4079 * globally on the object and prevent it from being changed whilst the
4080 * hardware is reading from the object. That is if the object is currently
4081 * on the scanout it will be set to uncached (or equivalent display
4082 * cache coherency) and all non-MOCS GPU access will also be uncached so
4083 * that all direct access to the scanout remains coherent.
4085 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
4086 enum i915_cache_level cache_level
)
4088 struct drm_device
*dev
= obj
->base
.dev
;
4089 struct i915_vma
*vma
, *next
;
4093 if (obj
->cache_level
== cache_level
)
4096 /* Inspect the list of currently bound VMA and unbind any that would
4097 * be invalid given the new cache-level. This is principally to
4098 * catch the issue of the CS prefetch crossing page boundaries and
4099 * reading an invalid PTE on older architectures.
4101 list_for_each_entry_safe(vma
, next
, &obj
->vma_list
, obj_link
) {
4102 if (!drm_mm_node_allocated(&vma
->node
))
4105 if (vma
->pin_count
) {
4106 DRM_DEBUG("can not change the cache level of pinned objects\n");
4110 if (!i915_gem_valid_gtt_space(vma
, cache_level
)) {
4111 ret
= i915_vma_unbind(vma
);
4118 /* We can reuse the existing drm_mm nodes but need to change the
4119 * cache-level on the PTE. We could simply unbind them all and
4120 * rebind with the correct cache-level on next use. However since
4121 * we already have a valid slot, dma mapping, pages etc, we may as
4122 * rewrite the PTE in the belief that doing so tramples upon less
4123 * state and so involves less work.
4126 /* Before we change the PTE, the GPU must not be accessing it.
4127 * If we wait upon the object, we know that all the bound
4128 * VMA are no longer active.
4130 ret
= i915_gem_object_wait_rendering(obj
, false);
4134 if (!HAS_LLC(dev
) && cache_level
!= I915_CACHE_NONE
) {
4135 /* Access to snoopable pages through the GTT is
4136 * incoherent and on some machines causes a hard
4137 * lockup. Relinquish the CPU mmaping to force
4138 * userspace to refault in the pages and we can
4139 * then double check if the GTT mapping is still
4140 * valid for that pointer access.
4142 i915_gem_release_mmap(obj
);
4144 /* As we no longer need a fence for GTT access,
4145 * we can relinquish it now (and so prevent having
4146 * to steal a fence from someone else on the next
4147 * fence request). Note GPU activity would have
4148 * dropped the fence as all snoopable access is
4149 * supposed to be linear.
4151 ret
= i915_gem_object_put_fence(obj
);
4155 /* We either have incoherent backing store and
4156 * so no GTT access or the architecture is fully
4157 * coherent. In such cases, existing GTT mmaps
4158 * ignore the cache bit in the PTE and we can
4159 * rewrite it without confusing the GPU or having
4160 * to force userspace to fault back in its mmaps.
4164 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
) {
4165 if (!drm_mm_node_allocated(&vma
->node
))
4168 ret
= i915_vma_bind(vma
, cache_level
, PIN_UPDATE
);
4174 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
)
4175 vma
->node
.color
= cache_level
;
4176 obj
->cache_level
= cache_level
;
4179 /* Flush the dirty CPU caches to the backing storage so that the
4180 * object is now coherent at its new cache level (with respect
4181 * to the access domain).
4183 if (obj
->cache_dirty
&& cpu_write_needs_clflush(obj
)) {
4184 if (i915_gem_clflush_object(obj
, true))
4185 i915_gem_chipset_flush(to_i915(obj
->base
.dev
));
4191 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
4192 struct drm_file
*file
)
4194 struct drm_i915_gem_caching
*args
= data
;
4195 struct drm_i915_gem_object
*obj
;
4197 obj
= to_intel_bo(drm_gem_object_lookup(file
, args
->handle
));
4198 if (&obj
->base
== NULL
)
4201 switch (obj
->cache_level
) {
4202 case I915_CACHE_LLC
:
4203 case I915_CACHE_L3_LLC
:
4204 args
->caching
= I915_CACHING_CACHED
;
4208 args
->caching
= I915_CACHING_DISPLAY
;
4212 args
->caching
= I915_CACHING_NONE
;
4216 drm_gem_object_unreference_unlocked(&obj
->base
);
4220 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
4221 struct drm_file
*file
)
4223 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4224 struct drm_i915_gem_caching
*args
= data
;
4225 struct drm_i915_gem_object
*obj
;
4226 enum i915_cache_level level
;
4229 switch (args
->caching
) {
4230 case I915_CACHING_NONE
:
4231 level
= I915_CACHE_NONE
;
4233 case I915_CACHING_CACHED
:
4235 * Due to a HW issue on BXT A stepping, GPU stores via a
4236 * snooped mapping may leave stale data in a corresponding CPU
4237 * cacheline, whereas normally such cachelines would get
4240 if (!HAS_LLC(dev
) && !HAS_SNOOP(dev
))
4243 level
= I915_CACHE_LLC
;
4245 case I915_CACHING_DISPLAY
:
4246 level
= HAS_WT(dev
) ? I915_CACHE_WT
: I915_CACHE_NONE
;
4252 intel_runtime_pm_get(dev_priv
);
4254 ret
= i915_mutex_lock_interruptible(dev
);
4258 obj
= to_intel_bo(drm_gem_object_lookup(file
, args
->handle
));
4259 if (&obj
->base
== NULL
) {
4264 ret
= i915_gem_object_set_cache_level(obj
, level
);
4266 drm_gem_object_unreference(&obj
->base
);
4268 mutex_unlock(&dev
->struct_mutex
);
4270 intel_runtime_pm_put(dev_priv
);
4276 * Prepare buffer for display plane (scanout, cursors, etc).
4277 * Can be called from an uninterruptible phase (modesetting) and allows
4278 * any flushes to be pipelined (for pageflips).
4281 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
4283 const struct i915_ggtt_view
*view
)
4285 u32 old_read_domains
, old_write_domain
;
4288 /* Mark the pin_display early so that we account for the
4289 * display coherency whilst setting up the cache domains.
4293 /* The display engine is not coherent with the LLC cache on gen6. As
4294 * a result, we make sure that the pinning that is about to occur is
4295 * done with uncached PTEs. This is lowest common denominator for all
4298 * However for gen6+, we could do better by using the GFDT bit instead
4299 * of uncaching, which would allow us to flush all the LLC-cached data
4300 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
4302 ret
= i915_gem_object_set_cache_level(obj
,
4303 HAS_WT(obj
->base
.dev
) ? I915_CACHE_WT
: I915_CACHE_NONE
);
4305 goto err_unpin_display
;
4307 /* As the user may map the buffer once pinned in the display plane
4308 * (e.g. libkms for the bootup splash), we have to ensure that we
4309 * always use map_and_fenceable for all scanout buffers.
4311 ret
= i915_gem_object_ggtt_pin(obj
, view
, alignment
,
4312 view
->type
== I915_GGTT_VIEW_NORMAL
?
4315 goto err_unpin_display
;
4317 i915_gem_object_flush_cpu_write_domain(obj
);
4319 old_write_domain
= obj
->base
.write_domain
;
4320 old_read_domains
= obj
->base
.read_domains
;
4322 /* It should now be out of any other write domains, and we can update
4323 * the domain values for our changes.
4325 obj
->base
.write_domain
= 0;
4326 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
4328 trace_i915_gem_object_change_domain(obj
,
4340 i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object
*obj
,
4341 const struct i915_ggtt_view
*view
)
4343 if (WARN_ON(obj
->pin_display
== 0))
4346 i915_gem_object_ggtt_unpin_view(obj
, view
);
4352 * Moves a single object to the CPU read, and possibly write domain.
4353 * @obj: object to act on
4354 * @write: requesting write or read-only access
4356 * This function returns when the move is complete, including waiting on
4360 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
)
4362 uint32_t old_write_domain
, old_read_domains
;
4365 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_CPU
)
4368 ret
= i915_gem_object_wait_rendering(obj
, !write
);
4372 i915_gem_object_flush_gtt_write_domain(obj
);
4374 old_write_domain
= obj
->base
.write_domain
;
4375 old_read_domains
= obj
->base
.read_domains
;
4377 /* Flush the CPU cache if it's still invalid. */
4378 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) == 0) {
4379 i915_gem_clflush_object(obj
, false);
4381 obj
->base
.read_domains
|= I915_GEM_DOMAIN_CPU
;
4384 /* It should now be out of any other write domains, and we can update
4385 * the domain values for our changes.
4387 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
4389 /* If we're writing through the CPU, then the GPU read domains will
4390 * need to be invalidated at next use.
4393 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
4394 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
4397 trace_i915_gem_object_change_domain(obj
,
4404 /* Throttle our rendering by waiting until the ring has completed our requests
4405 * emitted over 20 msec ago.
4407 * Note that if we were to use the current jiffies each time around the loop,
4408 * we wouldn't escape the function with any frames outstanding if the time to
4409 * render a frame was over 20ms.
4411 * This should get us reasonable parallelism between CPU and GPU but also
4412 * relatively low latency when blocking on a particular request to finish.
4415 i915_gem_ring_throttle(struct drm_device
*dev
, struct drm_file
*file
)
4417 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4418 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
4419 unsigned long recent_enough
= jiffies
- DRM_I915_THROTTLE_JIFFIES
;
4420 struct drm_i915_gem_request
*request
, *target
= NULL
;
4423 ret
= i915_gem_wait_for_error(&dev_priv
->gpu_error
);
4427 /* ABI: return -EIO if already wedged */
4428 if (i915_terminally_wedged(&dev_priv
->gpu_error
))
4431 spin_lock(&file_priv
->mm
.lock
);
4432 list_for_each_entry(request
, &file_priv
->mm
.request_list
, client_list
) {
4433 if (time_after_eq(request
->emitted_jiffies
, recent_enough
))
4437 * Note that the request might not have been submitted yet.
4438 * In which case emitted_jiffies will be zero.
4440 if (!request
->emitted_jiffies
)
4446 i915_gem_request_reference(target
);
4447 spin_unlock(&file_priv
->mm
.lock
);
4452 ret
= __i915_wait_request(target
, true, NULL
, NULL
);
4454 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, 0);
4456 i915_gem_request_unreference(target
);
4462 i915_vma_misplaced(struct i915_vma
*vma
, uint32_t alignment
, uint64_t flags
)
4464 struct drm_i915_gem_object
*obj
= vma
->obj
;
4467 vma
->node
.start
& (alignment
- 1))
4470 if (flags
& PIN_MAPPABLE
&& !obj
->map_and_fenceable
)
4473 if (flags
& PIN_OFFSET_BIAS
&&
4474 vma
->node
.start
< (flags
& PIN_OFFSET_MASK
))
4477 if (flags
& PIN_OFFSET_FIXED
&&
4478 vma
->node
.start
!= (flags
& PIN_OFFSET_MASK
))
4484 void __i915_vma_set_map_and_fenceable(struct i915_vma
*vma
)
4486 struct drm_i915_gem_object
*obj
= vma
->obj
;
4487 bool mappable
, fenceable
;
4488 u32 fence_size
, fence_alignment
;
4490 fence_size
= i915_gem_get_gtt_size(obj
->base
.dev
,
4493 fence_alignment
= i915_gem_get_gtt_alignment(obj
->base
.dev
,
4498 fenceable
= (vma
->node
.size
== fence_size
&&
4499 (vma
->node
.start
& (fence_alignment
- 1)) == 0);
4501 mappable
= (vma
->node
.start
+ fence_size
<=
4502 to_i915(obj
->base
.dev
)->ggtt
.mappable_end
);
4504 obj
->map_and_fenceable
= mappable
&& fenceable
;
4508 i915_gem_object_do_pin(struct drm_i915_gem_object
*obj
,
4509 struct i915_address_space
*vm
,
4510 const struct i915_ggtt_view
*ggtt_view
,
4514 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
4515 struct i915_vma
*vma
;
4519 if (WARN_ON(vm
== &dev_priv
->mm
.aliasing_ppgtt
->base
))
4522 if (WARN_ON(flags
& (PIN_GLOBAL
| PIN_MAPPABLE
) && !i915_is_ggtt(vm
)))
4525 if (WARN_ON((flags
& (PIN_MAPPABLE
| PIN_GLOBAL
)) == PIN_MAPPABLE
))
4528 if (WARN_ON(i915_is_ggtt(vm
) != !!ggtt_view
))
4531 vma
= ggtt_view
? i915_gem_obj_to_ggtt_view(obj
, ggtt_view
) :
4532 i915_gem_obj_to_vma(obj
, vm
);
4535 if (WARN_ON(vma
->pin_count
== DRM_I915_GEM_OBJECT_MAX_PIN_COUNT
))
4538 if (i915_vma_misplaced(vma
, alignment
, flags
)) {
4539 WARN(vma
->pin_count
,
4540 "bo is already pinned in %s with incorrect alignment:"
4541 " offset=%08x %08x, req.alignment=%x, req.map_and_fenceable=%d,"
4542 " obj->map_and_fenceable=%d\n",
4543 ggtt_view
? "ggtt" : "ppgtt",
4544 upper_32_bits(vma
->node
.start
),
4545 lower_32_bits(vma
->node
.start
),
4547 !!(flags
& PIN_MAPPABLE
),
4548 obj
->map_and_fenceable
);
4549 ret
= i915_vma_unbind(vma
);
4557 bound
= vma
? vma
->bound
: 0;
4558 if (vma
== NULL
|| !drm_mm_node_allocated(&vma
->node
)) {
4559 vma
= i915_gem_object_bind_to_vm(obj
, vm
, ggtt_view
, alignment
,
4562 return PTR_ERR(vma
);
4564 ret
= i915_vma_bind(vma
, obj
->cache_level
, flags
);
4569 if (ggtt_view
&& ggtt_view
->type
== I915_GGTT_VIEW_NORMAL
&&
4570 (bound
^ vma
->bound
) & GLOBAL_BIND
) {
4571 __i915_vma_set_map_and_fenceable(vma
);
4572 WARN_ON(flags
& PIN_MAPPABLE
&& !obj
->map_and_fenceable
);
4580 i915_gem_object_pin(struct drm_i915_gem_object
*obj
,
4581 struct i915_address_space
*vm
,
4585 return i915_gem_object_do_pin(obj
, vm
,
4586 i915_is_ggtt(vm
) ? &i915_ggtt_view_normal
: NULL
,
4591 i915_gem_object_ggtt_pin(struct drm_i915_gem_object
*obj
,
4592 const struct i915_ggtt_view
*view
,
4596 struct drm_device
*dev
= obj
->base
.dev
;
4597 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4598 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
4602 return i915_gem_object_do_pin(obj
, &ggtt
->base
, view
,
4603 alignment
, flags
| PIN_GLOBAL
);
4607 i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object
*obj
,
4608 const struct i915_ggtt_view
*view
)
4610 struct i915_vma
*vma
= i915_gem_obj_to_ggtt_view(obj
, view
);
4612 WARN_ON(vma
->pin_count
== 0);
4613 WARN_ON(!i915_gem_obj_ggtt_bound_view(obj
, view
));
4619 i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
4620 struct drm_file
*file
)
4622 struct drm_i915_gem_busy
*args
= data
;
4623 struct drm_i915_gem_object
*obj
;
4626 ret
= i915_mutex_lock_interruptible(dev
);
4630 obj
= to_intel_bo(drm_gem_object_lookup(file
, args
->handle
));
4631 if (&obj
->base
== NULL
) {
4636 /* Count all active objects as busy, even if they are currently not used
4637 * by the gpu. Users of this interface expect objects to eventually
4638 * become non-busy without any further actions, therefore emit any
4639 * necessary flushes here.
4641 ret
= i915_gem_object_flush_active(obj
);
4649 for (i
= 0; i
< I915_NUM_ENGINES
; i
++) {
4650 struct drm_i915_gem_request
*req
;
4652 req
= obj
->last_read_req
[i
];
4654 args
->busy
|= 1 << (16 + req
->engine
->exec_id
);
4656 if (obj
->last_write_req
)
4657 args
->busy
|= obj
->last_write_req
->engine
->exec_id
;
4661 drm_gem_object_unreference(&obj
->base
);
4663 mutex_unlock(&dev
->struct_mutex
);
4668 i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
4669 struct drm_file
*file_priv
)
4671 return i915_gem_ring_throttle(dev
, file_priv
);
4675 i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
4676 struct drm_file
*file_priv
)
4678 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4679 struct drm_i915_gem_madvise
*args
= data
;
4680 struct drm_i915_gem_object
*obj
;
4683 switch (args
->madv
) {
4684 case I915_MADV_DONTNEED
:
4685 case I915_MADV_WILLNEED
:
4691 ret
= i915_mutex_lock_interruptible(dev
);
4695 obj
= to_intel_bo(drm_gem_object_lookup(file_priv
, args
->handle
));
4696 if (&obj
->base
== NULL
) {
4701 if (i915_gem_obj_is_pinned(obj
)) {
4707 obj
->tiling_mode
!= I915_TILING_NONE
&&
4708 dev_priv
->quirks
& QUIRK_PIN_SWIZZLED_PAGES
) {
4709 if (obj
->madv
== I915_MADV_WILLNEED
)
4710 i915_gem_object_unpin_pages(obj
);
4711 if (args
->madv
== I915_MADV_WILLNEED
)
4712 i915_gem_object_pin_pages(obj
);
4715 if (obj
->madv
!= __I915_MADV_PURGED
)
4716 obj
->madv
= args
->madv
;
4718 /* if the object is no longer attached, discard its backing storage */
4719 if (obj
->madv
== I915_MADV_DONTNEED
&& obj
->pages
== NULL
)
4720 i915_gem_object_truncate(obj
);
4722 args
->retained
= obj
->madv
!= __I915_MADV_PURGED
;
4725 drm_gem_object_unreference(&obj
->base
);
4727 mutex_unlock(&dev
->struct_mutex
);
4731 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
4732 const struct drm_i915_gem_object_ops
*ops
)
4736 INIT_LIST_HEAD(&obj
->global_list
);
4737 for (i
= 0; i
< I915_NUM_ENGINES
; i
++)
4738 INIT_LIST_HEAD(&obj
->engine_list
[i
]);
4739 INIT_LIST_HEAD(&obj
->obj_exec_link
);
4740 INIT_LIST_HEAD(&obj
->vma_list
);
4741 INIT_LIST_HEAD(&obj
->batch_pool_link
);
4745 obj
->fence_reg
= I915_FENCE_REG_NONE
;
4746 obj
->madv
= I915_MADV_WILLNEED
;
4748 i915_gem_info_add_obj(obj
->base
.dev
->dev_private
, obj
->base
.size
);
4751 static const struct drm_i915_gem_object_ops i915_gem_object_ops
= {
4752 .flags
= I915_GEM_OBJECT_HAS_STRUCT_PAGE
,
4753 .get_pages
= i915_gem_object_get_pages_gtt
,
4754 .put_pages
= i915_gem_object_put_pages_gtt
,
4757 struct drm_i915_gem_object
*i915_gem_object_create(struct drm_device
*dev
,
4760 struct drm_i915_gem_object
*obj
;
4761 struct address_space
*mapping
;
4765 obj
= i915_gem_object_alloc(dev
);
4767 return ERR_PTR(-ENOMEM
);
4769 ret
= drm_gem_object_init(dev
, &obj
->base
, size
);
4773 mask
= GFP_HIGHUSER
| __GFP_RECLAIMABLE
;
4774 if (IS_CRESTLINE(dev
) || IS_BROADWATER(dev
)) {
4775 /* 965gm cannot relocate objects above 4GiB. */
4776 mask
&= ~__GFP_HIGHMEM
;
4777 mask
|= __GFP_DMA32
;
4780 mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
4781 mapping_set_gfp_mask(mapping
, mask
);
4783 i915_gem_object_init(obj
, &i915_gem_object_ops
);
4785 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
4786 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
4789 /* On some devices, we can have the GPU use the LLC (the CPU
4790 * cache) for about a 10% performance improvement
4791 * compared to uncached. Graphics requests other than
4792 * display scanout are coherent with the CPU in
4793 * accessing this cache. This means in this mode we
4794 * don't need to clflush on the CPU side, and on the
4795 * GPU side we only need to flush internal caches to
4796 * get data visible to the CPU.
4798 * However, we maintain the display planes as UC, and so
4799 * need to rebind when first used as such.
4801 obj
->cache_level
= I915_CACHE_LLC
;
4803 obj
->cache_level
= I915_CACHE_NONE
;
4805 trace_i915_gem_object_create(obj
);
4810 i915_gem_object_free(obj
);
4812 return ERR_PTR(ret
);
4815 static bool discard_backing_storage(struct drm_i915_gem_object
*obj
)
4817 /* If we are the last user of the backing storage (be it shmemfs
4818 * pages or stolen etc), we know that the pages are going to be
4819 * immediately released. In this case, we can then skip copying
4820 * back the contents from the GPU.
4823 if (obj
->madv
!= I915_MADV_WILLNEED
)
4826 if (obj
->base
.filp
== NULL
)
4829 /* At first glance, this looks racy, but then again so would be
4830 * userspace racing mmap against close. However, the first external
4831 * reference to the filp can only be obtained through the
4832 * i915_gem_mmap_ioctl() which safeguards us against the user
4833 * acquiring such a reference whilst we are in the middle of
4834 * freeing the object.
4836 return atomic_long_read(&obj
->base
.filp
->f_count
) == 1;
4839 void i915_gem_free_object(struct drm_gem_object
*gem_obj
)
4841 struct drm_i915_gem_object
*obj
= to_intel_bo(gem_obj
);
4842 struct drm_device
*dev
= obj
->base
.dev
;
4843 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4844 struct i915_vma
*vma
, *next
;
4846 intel_runtime_pm_get(dev_priv
);
4848 trace_i915_gem_object_destroy(obj
);
4850 list_for_each_entry_safe(vma
, next
, &obj
->vma_list
, obj_link
) {
4854 ret
= i915_vma_unbind(vma
);
4855 if (WARN_ON(ret
== -ERESTARTSYS
)) {
4856 bool was_interruptible
;
4858 was_interruptible
= dev_priv
->mm
.interruptible
;
4859 dev_priv
->mm
.interruptible
= false;
4861 WARN_ON(i915_vma_unbind(vma
));
4863 dev_priv
->mm
.interruptible
= was_interruptible
;
4867 /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
4868 * before progressing. */
4870 i915_gem_object_unpin_pages(obj
);
4872 WARN_ON(obj
->frontbuffer_bits
);
4874 if (obj
->pages
&& obj
->madv
== I915_MADV_WILLNEED
&&
4875 dev_priv
->quirks
& QUIRK_PIN_SWIZZLED_PAGES
&&
4876 obj
->tiling_mode
!= I915_TILING_NONE
)
4877 i915_gem_object_unpin_pages(obj
);
4879 if (WARN_ON(obj
->pages_pin_count
))
4880 obj
->pages_pin_count
= 0;
4881 if (discard_backing_storage(obj
))
4882 obj
->madv
= I915_MADV_DONTNEED
;
4883 i915_gem_object_put_pages(obj
);
4884 i915_gem_object_free_mmap_offset(obj
);
4888 if (obj
->base
.import_attach
)
4889 drm_prime_gem_destroy(&obj
->base
, NULL
);
4891 if (obj
->ops
->release
)
4892 obj
->ops
->release(obj
);
4894 drm_gem_object_release(&obj
->base
);
4895 i915_gem_info_remove_obj(dev_priv
, obj
->base
.size
);
4898 i915_gem_object_free(obj
);
4900 intel_runtime_pm_put(dev_priv
);
4903 struct i915_vma
*i915_gem_obj_to_vma(struct drm_i915_gem_object
*obj
,
4904 struct i915_address_space
*vm
)
4906 struct i915_vma
*vma
;
4907 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
) {
4908 if (vma
->ggtt_view
.type
== I915_GGTT_VIEW_NORMAL
&&
4915 struct i915_vma
*i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object
*obj
,
4916 const struct i915_ggtt_view
*view
)
4918 struct i915_vma
*vma
;
4922 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
)
4923 if (vma
->is_ggtt
&& i915_ggtt_view_equal(&vma
->ggtt_view
, view
))
4928 void i915_gem_vma_destroy(struct i915_vma
*vma
)
4930 WARN_ON(vma
->node
.allocated
);
4932 /* Keep the vma as a placeholder in the execbuffer reservation lists */
4933 if (!list_empty(&vma
->exec_list
))
4937 i915_ppgtt_put(i915_vm_to_ppgtt(vma
->vm
));
4939 list_del(&vma
->obj_link
);
4941 kmem_cache_free(to_i915(vma
->obj
->base
.dev
)->vmas
, vma
);
4945 i915_gem_stop_engines(struct drm_device
*dev
)
4947 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4948 struct intel_engine_cs
*engine
;
4950 for_each_engine(engine
, dev_priv
)
4951 dev_priv
->gt
.stop_engine(engine
);
4955 i915_gem_suspend(struct drm_device
*dev
)
4957 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4960 mutex_lock(&dev
->struct_mutex
);
4961 ret
= i915_gem_wait_for_idle(dev_priv
);
4965 i915_gem_retire_requests(dev_priv
);
4967 i915_gem_stop_engines(dev
);
4968 i915_gem_context_lost(dev_priv
);
4969 mutex_unlock(&dev
->struct_mutex
);
4971 cancel_delayed_work_sync(&dev_priv
->gpu_error
.hangcheck_work
);
4972 cancel_delayed_work_sync(&dev_priv
->mm
.retire_work
);
4973 flush_delayed_work(&dev_priv
->mm
.idle_work
);
4975 /* Assert that we sucessfully flushed all the work and
4976 * reset the GPU back to its idle, low power state.
4978 WARN_ON(dev_priv
->mm
.busy
);
4983 mutex_unlock(&dev
->struct_mutex
);
4987 void i915_gem_init_swizzling(struct drm_device
*dev
)
4989 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4991 if (INTEL_INFO(dev
)->gen
< 5 ||
4992 dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_NONE
)
4995 I915_WRITE(DISP_ARB_CTL
, I915_READ(DISP_ARB_CTL
) |
4996 DISP_TILE_SURFACE_SWIZZLING
);
5001 I915_WRITE(TILECTL
, I915_READ(TILECTL
) | TILECTL_SWZCTL
);
5003 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB
));
5004 else if (IS_GEN7(dev
))
5005 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB
));
5006 else if (IS_GEN8(dev
))
5007 I915_WRITE(GAMTARBMODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW
));
5012 static void init_unused_ring(struct drm_device
*dev
, u32 base
)
5014 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5016 I915_WRITE(RING_CTL(base
), 0);
5017 I915_WRITE(RING_HEAD(base
), 0);
5018 I915_WRITE(RING_TAIL(base
), 0);
5019 I915_WRITE(RING_START(base
), 0);
5022 static void init_unused_rings(struct drm_device
*dev
)
5025 init_unused_ring(dev
, PRB1_BASE
);
5026 init_unused_ring(dev
, SRB0_BASE
);
5027 init_unused_ring(dev
, SRB1_BASE
);
5028 init_unused_ring(dev
, SRB2_BASE
);
5029 init_unused_ring(dev
, SRB3_BASE
);
5030 } else if (IS_GEN2(dev
)) {
5031 init_unused_ring(dev
, SRB0_BASE
);
5032 init_unused_ring(dev
, SRB1_BASE
);
5033 } else if (IS_GEN3(dev
)) {
5034 init_unused_ring(dev
, PRB1_BASE
);
5035 init_unused_ring(dev
, PRB2_BASE
);
5039 int i915_gem_init_engines(struct drm_device
*dev
)
5041 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5044 ret
= intel_init_render_ring_buffer(dev
);
5049 ret
= intel_init_bsd_ring_buffer(dev
);
5051 goto cleanup_render_ring
;
5055 ret
= intel_init_blt_ring_buffer(dev
);
5057 goto cleanup_bsd_ring
;
5060 if (HAS_VEBOX(dev
)) {
5061 ret
= intel_init_vebox_ring_buffer(dev
);
5063 goto cleanup_blt_ring
;
5066 if (HAS_BSD2(dev
)) {
5067 ret
= intel_init_bsd2_ring_buffer(dev
);
5069 goto cleanup_vebox_ring
;
5075 intel_cleanup_engine(&dev_priv
->engine
[VECS
]);
5077 intel_cleanup_engine(&dev_priv
->engine
[BCS
]);
5079 intel_cleanup_engine(&dev_priv
->engine
[VCS
]);
5080 cleanup_render_ring
:
5081 intel_cleanup_engine(&dev_priv
->engine
[RCS
]);
5087 i915_gem_init_hw(struct drm_device
*dev
)
5089 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5090 struct intel_engine_cs
*engine
;
5093 /* Double layer security blanket, see i915_gem_init() */
5094 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
5096 if (HAS_EDRAM(dev
) && INTEL_GEN(dev_priv
) < 9)
5097 I915_WRITE(HSW_IDICR
, I915_READ(HSW_IDICR
) | IDIHASHMSK(0xf));
5099 if (IS_HASWELL(dev
))
5100 I915_WRITE(MI_PREDICATE_RESULT_2
, IS_HSW_GT3(dev
) ?
5101 LOWER_SLICE_ENABLED
: LOWER_SLICE_DISABLED
);
5103 if (HAS_PCH_NOP(dev
)) {
5104 if (IS_IVYBRIDGE(dev
)) {
5105 u32 temp
= I915_READ(GEN7_MSG_CTL
);
5106 temp
&= ~(WAIT_FOR_PCH_FLR_ACK
| WAIT_FOR_PCH_RESET_ACK
);
5107 I915_WRITE(GEN7_MSG_CTL
, temp
);
5108 } else if (INTEL_INFO(dev
)->gen
>= 7) {
5109 u32 temp
= I915_READ(HSW_NDE_RSTWRN_OPT
);
5110 temp
&= ~RESET_PCH_HANDSHAKE_ENABLE
;
5111 I915_WRITE(HSW_NDE_RSTWRN_OPT
, temp
);
5115 i915_gem_init_swizzling(dev
);
5118 * At least 830 can leave some of the unused rings
5119 * "active" (ie. head != tail) after resume which
5120 * will prevent c3 entry. Makes sure all unused rings
5123 init_unused_rings(dev
);
5125 BUG_ON(!dev_priv
->kernel_context
);
5127 ret
= i915_ppgtt_init_hw(dev
);
5129 DRM_ERROR("PPGTT enable HW failed %d\n", ret
);
5133 /* Need to do basic initialisation of all rings first: */
5134 for_each_engine(engine
, dev_priv
) {
5135 ret
= engine
->init_hw(engine
);
5140 intel_mocs_init_l3cc_table(dev
);
5142 /* We can't enable contexts until all firmware is loaded */
5143 ret
= intel_guc_setup(dev
);
5148 * Increment the next seqno by 0x100 so we have a visible break
5149 * on re-initialisation
5151 ret
= i915_gem_set_seqno(dev
, dev_priv
->next_seqno
+0x100);
5154 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
5158 int i915_gem_init(struct drm_device
*dev
)
5160 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5163 mutex_lock(&dev
->struct_mutex
);
5165 if (!i915
.enable_execlists
) {
5166 dev_priv
->gt
.execbuf_submit
= i915_gem_ringbuffer_submission
;
5167 dev_priv
->gt
.init_engines
= i915_gem_init_engines
;
5168 dev_priv
->gt
.cleanup_engine
= intel_cleanup_engine
;
5169 dev_priv
->gt
.stop_engine
= intel_stop_engine
;
5171 dev_priv
->gt
.execbuf_submit
= intel_execlists_submission
;
5172 dev_priv
->gt
.init_engines
= intel_logical_rings_init
;
5173 dev_priv
->gt
.cleanup_engine
= intel_logical_ring_cleanup
;
5174 dev_priv
->gt
.stop_engine
= intel_logical_ring_stop
;
5177 /* This is just a security blanket to placate dragons.
5178 * On some systems, we very sporadically observe that the first TLBs
5179 * used by the CS may be stale, despite us poking the TLB reset. If
5180 * we hold the forcewake during initialisation these problems
5181 * just magically go away.
5183 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
5185 i915_gem_init_userptr(dev_priv
);
5186 i915_gem_init_ggtt(dev
);
5188 ret
= i915_gem_context_init(dev
);
5192 ret
= dev_priv
->gt
.init_engines(dev
);
5196 ret
= i915_gem_init_hw(dev
);
5198 /* Allow ring initialisation to fail by marking the GPU as
5199 * wedged. But we only want to do this where the GPU is angry,
5200 * for all other failure, such as an allocation failure, bail.
5202 DRM_ERROR("Failed to initialize GPU, declaring it wedged\n");
5203 atomic_or(I915_WEDGED
, &dev_priv
->gpu_error
.reset_counter
);
5208 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
5209 mutex_unlock(&dev
->struct_mutex
);
5215 i915_gem_cleanup_engines(struct drm_device
*dev
)
5217 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5218 struct intel_engine_cs
*engine
;
5220 for_each_engine(engine
, dev_priv
)
5221 dev_priv
->gt
.cleanup_engine(engine
);
5225 init_engine_lists(struct intel_engine_cs
*engine
)
5227 INIT_LIST_HEAD(&engine
->active_list
);
5228 INIT_LIST_HEAD(&engine
->request_list
);
5232 i915_gem_load_init_fences(struct drm_i915_private
*dev_priv
)
5234 struct drm_device
*dev
= dev_priv
->dev
;
5236 if (INTEL_INFO(dev_priv
)->gen
>= 7 && !IS_VALLEYVIEW(dev_priv
) &&
5237 !IS_CHERRYVIEW(dev_priv
))
5238 dev_priv
->num_fence_regs
= 32;
5239 else if (INTEL_INFO(dev_priv
)->gen
>= 4 || IS_I945G(dev_priv
) ||
5240 IS_I945GM(dev_priv
) || IS_G33(dev_priv
))
5241 dev_priv
->num_fence_regs
= 16;
5243 dev_priv
->num_fence_regs
= 8;
5245 if (intel_vgpu_active(dev_priv
))
5246 dev_priv
->num_fence_regs
=
5247 I915_READ(vgtif_reg(avail_rs
.fence_num
));
5249 /* Initialize fence registers to zero */
5250 i915_gem_restore_fences(dev
);
5252 i915_gem_detect_bit_6_swizzle(dev
);
5256 i915_gem_load_init(struct drm_device
*dev
)
5258 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5262 kmem_cache_create("i915_gem_object",
5263 sizeof(struct drm_i915_gem_object
), 0,
5267 kmem_cache_create("i915_gem_vma",
5268 sizeof(struct i915_vma
), 0,
5271 dev_priv
->requests
=
5272 kmem_cache_create("i915_gem_request",
5273 sizeof(struct drm_i915_gem_request
), 0,
5277 INIT_LIST_HEAD(&dev_priv
->vm_list
);
5278 INIT_LIST_HEAD(&dev_priv
->context_list
);
5279 INIT_LIST_HEAD(&dev_priv
->mm
.unbound_list
);
5280 INIT_LIST_HEAD(&dev_priv
->mm
.bound_list
);
5281 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
5282 for (i
= 0; i
< I915_NUM_ENGINES
; i
++)
5283 init_engine_lists(&dev_priv
->engine
[i
]);
5284 for (i
= 0; i
< I915_MAX_NUM_FENCES
; i
++)
5285 INIT_LIST_HEAD(&dev_priv
->fence_regs
[i
].lru_list
);
5286 INIT_DELAYED_WORK(&dev_priv
->mm
.retire_work
,
5287 i915_gem_retire_work_handler
);
5288 INIT_DELAYED_WORK(&dev_priv
->mm
.idle_work
,
5289 i915_gem_idle_work_handler
);
5290 init_waitqueue_head(&dev_priv
->gpu_error
.reset_queue
);
5292 dev_priv
->relative_constants_mode
= I915_EXEC_CONSTANTS_REL_GENERAL
;
5295 * Set initial sequence number for requests.
5296 * Using this number allows the wraparound to happen early,
5297 * catching any obvious problems.
5299 dev_priv
->next_seqno
= ((u32
)~0 - 0x1100);
5300 dev_priv
->last_seqno
= ((u32
)~0 - 0x1101);
5302 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
5304 init_waitqueue_head(&dev_priv
->pending_flip_queue
);
5306 dev_priv
->mm
.interruptible
= true;
5308 mutex_init(&dev_priv
->fb_tracking
.lock
);
5311 void i915_gem_load_cleanup(struct drm_device
*dev
)
5313 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5315 kmem_cache_destroy(dev_priv
->requests
);
5316 kmem_cache_destroy(dev_priv
->vmas
);
5317 kmem_cache_destroy(dev_priv
->objects
);
5320 int i915_gem_freeze_late(struct drm_i915_private
*dev_priv
)
5322 struct drm_i915_gem_object
*obj
;
5324 /* Called just before we write the hibernation image.
5326 * We need to update the domain tracking to reflect that the CPU
5327 * will be accessing all the pages to create and restore from the
5328 * hibernation, and so upon restoration those pages will be in the
5331 * To make sure the hibernation image contains the latest state,
5332 * we update that state just before writing out the image.
5335 list_for_each_entry(obj
, &dev_priv
->mm
.unbound_list
, global_list
) {
5336 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
5337 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
5340 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
5341 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
5342 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
5348 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
)
5350 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
5352 /* Clean up our request list when the client is going away, so that
5353 * later retire_requests won't dereference our soon-to-be-gone
5356 spin_lock(&file_priv
->mm
.lock
);
5357 while (!list_empty(&file_priv
->mm
.request_list
)) {
5358 struct drm_i915_gem_request
*request
;
5360 request
= list_first_entry(&file_priv
->mm
.request_list
,
5361 struct drm_i915_gem_request
,
5363 list_del(&request
->client_list
);
5364 request
->file_priv
= NULL
;
5366 spin_unlock(&file_priv
->mm
.lock
);
5368 if (!list_empty(&file_priv
->rps
.link
)) {
5369 spin_lock(&to_i915(dev
)->rps
.client_lock
);
5370 list_del(&file_priv
->rps
.link
);
5371 spin_unlock(&to_i915(dev
)->rps
.client_lock
);
5375 int i915_gem_open(struct drm_device
*dev
, struct drm_file
*file
)
5377 struct drm_i915_file_private
*file_priv
;
5380 DRM_DEBUG_DRIVER("\n");
5382 file_priv
= kzalloc(sizeof(*file_priv
), GFP_KERNEL
);
5386 file
->driver_priv
= file_priv
;
5387 file_priv
->dev_priv
= dev
->dev_private
;
5388 file_priv
->file
= file
;
5389 INIT_LIST_HEAD(&file_priv
->rps
.link
);
5391 spin_lock_init(&file_priv
->mm
.lock
);
5392 INIT_LIST_HEAD(&file_priv
->mm
.request_list
);
5394 file_priv
->bsd_ring
= -1;
5396 ret
= i915_gem_context_open(dev
, file
);
5404 * i915_gem_track_fb - update frontbuffer tracking
5405 * @old: current GEM buffer for the frontbuffer slots
5406 * @new: new GEM buffer for the frontbuffer slots
5407 * @frontbuffer_bits: bitmask of frontbuffer slots
5409 * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them
5410 * from @old and setting them in @new. Both @old and @new can be NULL.
5412 void i915_gem_track_fb(struct drm_i915_gem_object
*old
,
5413 struct drm_i915_gem_object
*new,
5414 unsigned frontbuffer_bits
)
5417 WARN_ON(!mutex_is_locked(&old
->base
.dev
->struct_mutex
));
5418 WARN_ON(!(old
->frontbuffer_bits
& frontbuffer_bits
));
5419 old
->frontbuffer_bits
&= ~frontbuffer_bits
;
5423 WARN_ON(!mutex_is_locked(&new->base
.dev
->struct_mutex
));
5424 WARN_ON(new->frontbuffer_bits
& frontbuffer_bits
);
5425 new->frontbuffer_bits
|= frontbuffer_bits
;
5429 /* All the new VM stuff */
5430 u64
i915_gem_obj_offset(struct drm_i915_gem_object
*o
,
5431 struct i915_address_space
*vm
)
5433 struct drm_i915_private
*dev_priv
= o
->base
.dev
->dev_private
;
5434 struct i915_vma
*vma
;
5436 WARN_ON(vm
== &dev_priv
->mm
.aliasing_ppgtt
->base
);
5438 list_for_each_entry(vma
, &o
->vma_list
, obj_link
) {
5440 vma
->ggtt_view
.type
!= I915_GGTT_VIEW_NORMAL
)
5443 return vma
->node
.start
;
5446 WARN(1, "%s vma for this object not found.\n",
5447 i915_is_ggtt(vm
) ? "global" : "ppgtt");
5451 u64
i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object
*o
,
5452 const struct i915_ggtt_view
*view
)
5454 struct i915_vma
*vma
;
5456 list_for_each_entry(vma
, &o
->vma_list
, obj_link
)
5457 if (vma
->is_ggtt
&& i915_ggtt_view_equal(&vma
->ggtt_view
, view
))
5458 return vma
->node
.start
;
5460 WARN(1, "global vma for this object not found. (view=%u)\n", view
->type
);
5464 bool i915_gem_obj_bound(struct drm_i915_gem_object
*o
,
5465 struct i915_address_space
*vm
)
5467 struct i915_vma
*vma
;
5469 list_for_each_entry(vma
, &o
->vma_list
, obj_link
) {
5471 vma
->ggtt_view
.type
!= I915_GGTT_VIEW_NORMAL
)
5473 if (vma
->vm
== vm
&& drm_mm_node_allocated(&vma
->node
))
5480 bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object
*o
,
5481 const struct i915_ggtt_view
*view
)
5483 struct i915_vma
*vma
;
5485 list_for_each_entry(vma
, &o
->vma_list
, obj_link
)
5487 i915_ggtt_view_equal(&vma
->ggtt_view
, view
) &&
5488 drm_mm_node_allocated(&vma
->node
))
5494 bool i915_gem_obj_bound_any(struct drm_i915_gem_object
*o
)
5496 struct i915_vma
*vma
;
5498 list_for_each_entry(vma
, &o
->vma_list
, obj_link
)
5499 if (drm_mm_node_allocated(&vma
->node
))
5505 unsigned long i915_gem_obj_ggtt_size(struct drm_i915_gem_object
*o
)
5507 struct i915_vma
*vma
;
5509 GEM_BUG_ON(list_empty(&o
->vma_list
));
5511 list_for_each_entry(vma
, &o
->vma_list
, obj_link
) {
5513 vma
->ggtt_view
.type
== I915_GGTT_VIEW_NORMAL
)
5514 return vma
->node
.size
;
5520 bool i915_gem_obj_is_pinned(struct drm_i915_gem_object
*obj
)
5522 struct i915_vma
*vma
;
5523 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
)
5524 if (vma
->pin_count
> 0)
5530 /* Like i915_gem_object_get_page(), but mark the returned page dirty */
5532 i915_gem_object_get_dirty_page(struct drm_i915_gem_object
*obj
, int n
)
5536 /* Only default objects have per-page dirty tracking */
5537 if (WARN_ON(!i915_gem_object_has_struct_page(obj
)))
5540 page
= i915_gem_object_get_page(obj
, n
);
5541 set_page_dirty(page
);
5545 /* Allocate a new GEM object and fill it with the supplied data */
5546 struct drm_i915_gem_object
*
5547 i915_gem_object_create_from_data(struct drm_device
*dev
,
5548 const void *data
, size_t size
)
5550 struct drm_i915_gem_object
*obj
;
5551 struct sg_table
*sg
;
5555 obj
= i915_gem_object_create(dev
, round_up(size
, PAGE_SIZE
));
5559 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
5563 ret
= i915_gem_object_get_pages(obj
);
5567 i915_gem_object_pin_pages(obj
);
5569 bytes
= sg_copy_from_buffer(sg
->sgl
, sg
->nents
, (void *)data
, size
);
5570 obj
->dirty
= 1; /* Backing store is now out of date */
5571 i915_gem_object_unpin_pages(obj
);
5573 if (WARN_ON(bytes
!= size
)) {
5574 DRM_ERROR("Incomplete copy, wrote %zu of %zu", bytes
, size
);
5582 drm_gem_object_unreference(&obj
->base
);
5583 return ERR_PTR(ret
);