2 * Copyright © 2008-2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/drm_vma_manager.h>
30 #include <drm/i915_drm.h>
32 #include "i915_vgpu.h"
33 #include "i915_trace.h"
34 #include "intel_drv.h"
35 #include <linux/shmem_fs.h>
36 #include <linux/slab.h>
37 #include <linux/swap.h>
38 #include <linux/pci.h>
39 #include <linux/dma-buf.h>
41 #define RQ_BUG_ON(expr)
43 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
);
44 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
);
46 i915_gem_object_retire__write(struct drm_i915_gem_object
*obj
);
48 i915_gem_object_retire__read(struct drm_i915_gem_object
*obj
, int ring
);
50 static bool cpu_cache_is_coherent(struct drm_device
*dev
,
51 enum i915_cache_level level
)
53 return HAS_LLC(dev
) || level
!= I915_CACHE_NONE
;
56 static bool cpu_write_needs_clflush(struct drm_i915_gem_object
*obj
)
58 if (!cpu_cache_is_coherent(obj
->base
.dev
, obj
->cache_level
))
61 return obj
->pin_display
;
64 /* some bookkeeping */
65 static void i915_gem_info_add_obj(struct drm_i915_private
*dev_priv
,
68 spin_lock(&dev_priv
->mm
.object_stat_lock
);
69 dev_priv
->mm
.object_count
++;
70 dev_priv
->mm
.object_memory
+= size
;
71 spin_unlock(&dev_priv
->mm
.object_stat_lock
);
74 static void i915_gem_info_remove_obj(struct drm_i915_private
*dev_priv
,
77 spin_lock(&dev_priv
->mm
.object_stat_lock
);
78 dev_priv
->mm
.object_count
--;
79 dev_priv
->mm
.object_memory
-= size
;
80 spin_unlock(&dev_priv
->mm
.object_stat_lock
);
84 i915_gem_wait_for_error(struct i915_gpu_error
*error
)
88 #define EXIT_COND (!i915_reset_in_progress(error) || \
89 i915_terminally_wedged(error))
94 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
95 * userspace. If it takes that long something really bad is going on and
96 * we should simply try to bail out and fail as gracefully as possible.
98 ret
= wait_event_interruptible_timeout(error
->reset_queue
,
102 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
104 } else if (ret
< 0) {
112 int i915_mutex_lock_interruptible(struct drm_device
*dev
)
114 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
117 ret
= i915_gem_wait_for_error(&dev_priv
->gpu_error
);
121 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
125 WARN_ON(i915_verify_lists(dev
));
130 i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
131 struct drm_file
*file
)
133 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
134 struct drm_i915_gem_get_aperture
*args
= data
;
135 struct i915_gtt
*ggtt
= &dev_priv
->gtt
;
136 struct i915_vma
*vma
;
140 mutex_lock(&dev
->struct_mutex
);
141 list_for_each_entry(vma
, &ggtt
->base
.active_list
, mm_list
)
143 pinned
+= vma
->node
.size
;
144 list_for_each_entry(vma
, &ggtt
->base
.inactive_list
, mm_list
)
146 pinned
+= vma
->node
.size
;
147 mutex_unlock(&dev
->struct_mutex
);
149 args
->aper_size
= dev_priv
->gtt
.base
.total
;
150 args
->aper_available_size
= args
->aper_size
- pinned
;
156 i915_gem_object_get_pages_phys(struct drm_i915_gem_object
*obj
)
158 struct address_space
*mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
159 char *vaddr
= obj
->phys_handle
->vaddr
;
161 struct scatterlist
*sg
;
164 if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj
)))
167 for (i
= 0; i
< obj
->base
.size
/ PAGE_SIZE
; i
++) {
171 page
= shmem_read_mapping_page(mapping
, i
);
173 return PTR_ERR(page
);
175 src
= kmap_atomic(page
);
176 memcpy(vaddr
, src
, PAGE_SIZE
);
177 drm_clflush_virt_range(vaddr
, PAGE_SIZE
);
180 page_cache_release(page
);
184 i915_gem_chipset_flush(obj
->base
.dev
);
186 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
190 if (sg_alloc_table(st
, 1, GFP_KERNEL
)) {
197 sg
->length
= obj
->base
.size
;
199 sg_dma_address(sg
) = obj
->phys_handle
->busaddr
;
200 sg_dma_len(sg
) = obj
->base
.size
;
207 i915_gem_object_put_pages_phys(struct drm_i915_gem_object
*obj
)
211 BUG_ON(obj
->madv
== __I915_MADV_PURGED
);
213 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
215 /* In the event of a disaster, abandon all caches and
218 WARN_ON(ret
!= -EIO
);
219 obj
->base
.read_domains
= obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
222 if (obj
->madv
== I915_MADV_DONTNEED
)
226 struct address_space
*mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
227 char *vaddr
= obj
->phys_handle
->vaddr
;
230 for (i
= 0; i
< obj
->base
.size
/ PAGE_SIZE
; i
++) {
234 page
= shmem_read_mapping_page(mapping
, i
);
238 dst
= kmap_atomic(page
);
239 drm_clflush_virt_range(vaddr
, PAGE_SIZE
);
240 memcpy(dst
, vaddr
, PAGE_SIZE
);
243 set_page_dirty(page
);
244 if (obj
->madv
== I915_MADV_WILLNEED
)
245 mark_page_accessed(page
);
246 page_cache_release(page
);
252 sg_free_table(obj
->pages
);
257 i915_gem_object_release_phys(struct drm_i915_gem_object
*obj
)
259 drm_pci_free(obj
->base
.dev
, obj
->phys_handle
);
262 static const struct drm_i915_gem_object_ops i915_gem_phys_ops
= {
263 .get_pages
= i915_gem_object_get_pages_phys
,
264 .put_pages
= i915_gem_object_put_pages_phys
,
265 .release
= i915_gem_object_release_phys
,
269 drop_pages(struct drm_i915_gem_object
*obj
)
271 struct i915_vma
*vma
, *next
;
274 drm_gem_object_reference(&obj
->base
);
275 list_for_each_entry_safe(vma
, next
, &obj
->vma_list
, vma_link
)
276 if (i915_vma_unbind(vma
))
279 ret
= i915_gem_object_put_pages(obj
);
280 drm_gem_object_unreference(&obj
->base
);
286 i915_gem_object_attach_phys(struct drm_i915_gem_object
*obj
,
289 drm_dma_handle_t
*phys
;
292 if (obj
->phys_handle
) {
293 if ((unsigned long)obj
->phys_handle
->vaddr
& (align
-1))
299 if (obj
->madv
!= I915_MADV_WILLNEED
)
302 if (obj
->base
.filp
== NULL
)
305 ret
= drop_pages(obj
);
309 /* create a new object */
310 phys
= drm_pci_alloc(obj
->base
.dev
, obj
->base
.size
, align
);
314 obj
->phys_handle
= phys
;
315 obj
->ops
= &i915_gem_phys_ops
;
317 return i915_gem_object_get_pages(obj
);
321 i915_gem_phys_pwrite(struct drm_i915_gem_object
*obj
,
322 struct drm_i915_gem_pwrite
*args
,
323 struct drm_file
*file_priv
)
325 struct drm_device
*dev
= obj
->base
.dev
;
326 void *vaddr
= obj
->phys_handle
->vaddr
+ args
->offset
;
327 char __user
*user_data
= to_user_ptr(args
->data_ptr
);
330 /* We manually control the domain here and pretend that it
331 * remains coherent i.e. in the GTT domain, like shmem_pwrite.
333 ret
= i915_gem_object_wait_rendering(obj
, false);
337 intel_fb_obj_invalidate(obj
, ORIGIN_CPU
);
338 if (__copy_from_user_inatomic_nocache(vaddr
, user_data
, args
->size
)) {
339 unsigned long unwritten
;
341 /* The physical object once assigned is fixed for the lifetime
342 * of the obj, so we can safely drop the lock and continue
345 mutex_unlock(&dev
->struct_mutex
);
346 unwritten
= copy_from_user(vaddr
, user_data
, args
->size
);
347 mutex_lock(&dev
->struct_mutex
);
354 drm_clflush_virt_range(vaddr
, args
->size
);
355 i915_gem_chipset_flush(dev
);
358 intel_fb_obj_flush(obj
, false, ORIGIN_CPU
);
362 void *i915_gem_object_alloc(struct drm_device
*dev
)
364 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
365 return kmem_cache_zalloc(dev_priv
->objects
, GFP_KERNEL
);
368 void i915_gem_object_free(struct drm_i915_gem_object
*obj
)
370 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
371 kmem_cache_free(dev_priv
->objects
, obj
);
375 i915_gem_create(struct drm_file
*file
,
376 struct drm_device
*dev
,
380 struct drm_i915_gem_object
*obj
;
384 size
= roundup(size
, PAGE_SIZE
);
388 /* Allocate the new object */
389 obj
= i915_gem_alloc_object(dev
, size
);
393 ret
= drm_gem_handle_create(file
, &obj
->base
, &handle
);
394 /* drop reference from allocate - handle holds it now */
395 drm_gem_object_unreference_unlocked(&obj
->base
);
404 i915_gem_dumb_create(struct drm_file
*file
,
405 struct drm_device
*dev
,
406 struct drm_mode_create_dumb
*args
)
408 /* have to work out size/pitch and return them */
409 args
->pitch
= ALIGN(args
->width
* DIV_ROUND_UP(args
->bpp
, 8), 64);
410 args
->size
= args
->pitch
* args
->height
;
411 return i915_gem_create(file
, dev
,
412 args
->size
, &args
->handle
);
416 * Creates a new mm object and returns a handle to it.
419 i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
420 struct drm_file
*file
)
422 struct drm_i915_gem_create
*args
= data
;
424 return i915_gem_create(file
, dev
,
425 args
->size
, &args
->handle
);
429 __copy_to_user_swizzled(char __user
*cpu_vaddr
,
430 const char *gpu_vaddr
, int gpu_offset
,
433 int ret
, cpu_offset
= 0;
436 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
437 int this_length
= min(cacheline_end
- gpu_offset
, length
);
438 int swizzled_gpu_offset
= gpu_offset
^ 64;
440 ret
= __copy_to_user(cpu_vaddr
+ cpu_offset
,
441 gpu_vaddr
+ swizzled_gpu_offset
,
446 cpu_offset
+= this_length
;
447 gpu_offset
+= this_length
;
448 length
-= this_length
;
455 __copy_from_user_swizzled(char *gpu_vaddr
, int gpu_offset
,
456 const char __user
*cpu_vaddr
,
459 int ret
, cpu_offset
= 0;
462 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
463 int this_length
= min(cacheline_end
- gpu_offset
, length
);
464 int swizzled_gpu_offset
= gpu_offset
^ 64;
466 ret
= __copy_from_user(gpu_vaddr
+ swizzled_gpu_offset
,
467 cpu_vaddr
+ cpu_offset
,
472 cpu_offset
+= this_length
;
473 gpu_offset
+= this_length
;
474 length
-= this_length
;
481 * Pins the specified object's pages and synchronizes the object with
482 * GPU accesses. Sets needs_clflush to non-zero if the caller should
483 * flush the object from the CPU cache.
485 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object
*obj
,
495 if (!(obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
)) {
496 /* If we're not in the cpu read domain, set ourself into the gtt
497 * read domain and manually flush cachelines (if required). This
498 * optimizes for the case when the gpu will dirty the data
499 * anyway again before the next pread happens. */
500 *needs_clflush
= !cpu_cache_is_coherent(obj
->base
.dev
,
502 ret
= i915_gem_object_wait_rendering(obj
, true);
507 ret
= i915_gem_object_get_pages(obj
);
511 i915_gem_object_pin_pages(obj
);
516 /* Per-page copy function for the shmem pread fastpath.
517 * Flushes invalid cachelines before reading the target if
518 * needs_clflush is set. */
520 shmem_pread_fast(struct page
*page
, int shmem_page_offset
, int page_length
,
521 char __user
*user_data
,
522 bool page_do_bit17_swizzling
, bool needs_clflush
)
527 if (unlikely(page_do_bit17_swizzling
))
530 vaddr
= kmap_atomic(page
);
532 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
534 ret
= __copy_to_user_inatomic(user_data
,
535 vaddr
+ shmem_page_offset
,
537 kunmap_atomic(vaddr
);
539 return ret
? -EFAULT
: 0;
543 shmem_clflush_swizzled_range(char *addr
, unsigned long length
,
546 if (unlikely(swizzled
)) {
547 unsigned long start
= (unsigned long) addr
;
548 unsigned long end
= (unsigned long) addr
+ length
;
550 /* For swizzling simply ensure that we always flush both
551 * channels. Lame, but simple and it works. Swizzled
552 * pwrite/pread is far from a hotpath - current userspace
553 * doesn't use it at all. */
554 start
= round_down(start
, 128);
555 end
= round_up(end
, 128);
557 drm_clflush_virt_range((void *)start
, end
- start
);
559 drm_clflush_virt_range(addr
, length
);
564 /* Only difference to the fast-path function is that this can handle bit17
565 * and uses non-atomic copy and kmap functions. */
567 shmem_pread_slow(struct page
*page
, int shmem_page_offset
, int page_length
,
568 char __user
*user_data
,
569 bool page_do_bit17_swizzling
, bool needs_clflush
)
576 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
578 page_do_bit17_swizzling
);
580 if (page_do_bit17_swizzling
)
581 ret
= __copy_to_user_swizzled(user_data
,
582 vaddr
, shmem_page_offset
,
585 ret
= __copy_to_user(user_data
,
586 vaddr
+ shmem_page_offset
,
590 return ret
? - EFAULT
: 0;
594 i915_gem_shmem_pread(struct drm_device
*dev
,
595 struct drm_i915_gem_object
*obj
,
596 struct drm_i915_gem_pread
*args
,
597 struct drm_file
*file
)
599 char __user
*user_data
;
602 int shmem_page_offset
, page_length
, ret
= 0;
603 int obj_do_bit17_swizzling
, page_do_bit17_swizzling
;
605 int needs_clflush
= 0;
606 struct sg_page_iter sg_iter
;
608 user_data
= to_user_ptr(args
->data_ptr
);
611 obj_do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
613 ret
= i915_gem_obj_prepare_shmem_read(obj
, &needs_clflush
);
617 offset
= args
->offset
;
619 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
,
620 offset
>> PAGE_SHIFT
) {
621 struct page
*page
= sg_page_iter_page(&sg_iter
);
626 /* Operation in this page
628 * shmem_page_offset = offset within page in shmem file
629 * page_length = bytes to copy for this page
631 shmem_page_offset
= offset_in_page(offset
);
632 page_length
= remain
;
633 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
634 page_length
= PAGE_SIZE
- shmem_page_offset
;
636 page_do_bit17_swizzling
= obj_do_bit17_swizzling
&&
637 (page_to_phys(page
) & (1 << 17)) != 0;
639 ret
= shmem_pread_fast(page
, shmem_page_offset
, page_length
,
640 user_data
, page_do_bit17_swizzling
,
645 mutex_unlock(&dev
->struct_mutex
);
647 if (likely(!i915
.prefault_disable
) && !prefaulted
) {
648 ret
= fault_in_multipages_writeable(user_data
, remain
);
649 /* Userspace is tricking us, but we've already clobbered
650 * its pages with the prefault and promised to write the
651 * data up to the first fault. Hence ignore any errors
652 * and just continue. */
657 ret
= shmem_pread_slow(page
, shmem_page_offset
, page_length
,
658 user_data
, page_do_bit17_swizzling
,
661 mutex_lock(&dev
->struct_mutex
);
667 remain
-= page_length
;
668 user_data
+= page_length
;
669 offset
+= page_length
;
673 i915_gem_object_unpin_pages(obj
);
679 * Reads data from the object referenced by handle.
681 * On error, the contents of *data are undefined.
684 i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
685 struct drm_file
*file
)
687 struct drm_i915_gem_pread
*args
= data
;
688 struct drm_i915_gem_object
*obj
;
694 if (!access_ok(VERIFY_WRITE
,
695 to_user_ptr(args
->data_ptr
),
699 ret
= i915_mutex_lock_interruptible(dev
);
703 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
704 if (&obj
->base
== NULL
) {
709 /* Bounds check source. */
710 if (args
->offset
> obj
->base
.size
||
711 args
->size
> obj
->base
.size
- args
->offset
) {
716 /* prime objects have no backing filp to GEM pread/pwrite
719 if (!obj
->base
.filp
) {
724 trace_i915_gem_object_pread(obj
, args
->offset
, args
->size
);
726 ret
= i915_gem_shmem_pread(dev
, obj
, args
, file
);
729 drm_gem_object_unreference(&obj
->base
);
731 mutex_unlock(&dev
->struct_mutex
);
735 /* This is the fast write path which cannot handle
736 * page faults in the source data
740 fast_user_write(struct io_mapping
*mapping
,
741 loff_t page_base
, int page_offset
,
742 char __user
*user_data
,
745 void __iomem
*vaddr_atomic
;
747 unsigned long unwritten
;
749 vaddr_atomic
= io_mapping_map_atomic_wc(mapping
, page_base
);
750 /* We can use the cpu mem copy function because this is X86. */
751 vaddr
= (void __force
*)vaddr_atomic
+ page_offset
;
752 unwritten
= __copy_from_user_inatomic_nocache(vaddr
,
754 io_mapping_unmap_atomic(vaddr_atomic
);
759 * This is the fast pwrite path, where we copy the data directly from the
760 * user into the GTT, uncached.
763 i915_gem_gtt_pwrite_fast(struct drm_device
*dev
,
764 struct drm_i915_gem_object
*obj
,
765 struct drm_i915_gem_pwrite
*args
,
766 struct drm_file
*file
)
768 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
770 loff_t offset
, page_base
;
771 char __user
*user_data
;
772 int page_offset
, page_length
, ret
;
774 ret
= i915_gem_obj_ggtt_pin(obj
, 0, PIN_MAPPABLE
| PIN_NONBLOCK
);
778 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
782 ret
= i915_gem_object_put_fence(obj
);
786 user_data
= to_user_ptr(args
->data_ptr
);
789 offset
= i915_gem_obj_ggtt_offset(obj
) + args
->offset
;
791 intel_fb_obj_invalidate(obj
, ORIGIN_GTT
);
794 /* Operation in this page
796 * page_base = page offset within aperture
797 * page_offset = offset within page
798 * page_length = bytes to copy for this page
800 page_base
= offset
& PAGE_MASK
;
801 page_offset
= offset_in_page(offset
);
802 page_length
= remain
;
803 if ((page_offset
+ remain
) > PAGE_SIZE
)
804 page_length
= PAGE_SIZE
- page_offset
;
806 /* If we get a fault while copying data, then (presumably) our
807 * source page isn't available. Return the error and we'll
808 * retry in the slow path.
810 if (fast_user_write(dev_priv
->gtt
.mappable
, page_base
,
811 page_offset
, user_data
, page_length
)) {
816 remain
-= page_length
;
817 user_data
+= page_length
;
818 offset
+= page_length
;
822 intel_fb_obj_flush(obj
, false, ORIGIN_GTT
);
824 i915_gem_object_ggtt_unpin(obj
);
829 /* Per-page copy function for the shmem pwrite fastpath.
830 * Flushes invalid cachelines before writing to the target if
831 * needs_clflush_before is set and flushes out any written cachelines after
832 * writing if needs_clflush is set. */
834 shmem_pwrite_fast(struct page
*page
, int shmem_page_offset
, int page_length
,
835 char __user
*user_data
,
836 bool page_do_bit17_swizzling
,
837 bool needs_clflush_before
,
838 bool needs_clflush_after
)
843 if (unlikely(page_do_bit17_swizzling
))
846 vaddr
= kmap_atomic(page
);
847 if (needs_clflush_before
)
848 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
850 ret
= __copy_from_user_inatomic(vaddr
+ shmem_page_offset
,
851 user_data
, page_length
);
852 if (needs_clflush_after
)
853 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
855 kunmap_atomic(vaddr
);
857 return ret
? -EFAULT
: 0;
860 /* Only difference to the fast-path function is that this can handle bit17
861 * and uses non-atomic copy and kmap functions. */
863 shmem_pwrite_slow(struct page
*page
, int shmem_page_offset
, int page_length
,
864 char __user
*user_data
,
865 bool page_do_bit17_swizzling
,
866 bool needs_clflush_before
,
867 bool needs_clflush_after
)
873 if (unlikely(needs_clflush_before
|| page_do_bit17_swizzling
))
874 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
876 page_do_bit17_swizzling
);
877 if (page_do_bit17_swizzling
)
878 ret
= __copy_from_user_swizzled(vaddr
, shmem_page_offset
,
882 ret
= __copy_from_user(vaddr
+ shmem_page_offset
,
885 if (needs_clflush_after
)
886 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
888 page_do_bit17_swizzling
);
891 return ret
? -EFAULT
: 0;
895 i915_gem_shmem_pwrite(struct drm_device
*dev
,
896 struct drm_i915_gem_object
*obj
,
897 struct drm_i915_gem_pwrite
*args
,
898 struct drm_file
*file
)
902 char __user
*user_data
;
903 int shmem_page_offset
, page_length
, ret
= 0;
904 int obj_do_bit17_swizzling
, page_do_bit17_swizzling
;
905 int hit_slowpath
= 0;
906 int needs_clflush_after
= 0;
907 int needs_clflush_before
= 0;
908 struct sg_page_iter sg_iter
;
910 user_data
= to_user_ptr(args
->data_ptr
);
913 obj_do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
915 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
916 /* If we're not in the cpu write domain, set ourself into the gtt
917 * write domain and manually flush cachelines (if required). This
918 * optimizes for the case when the gpu will use the data
919 * right away and we therefore have to clflush anyway. */
920 needs_clflush_after
= cpu_write_needs_clflush(obj
);
921 ret
= i915_gem_object_wait_rendering(obj
, false);
925 /* Same trick applies to invalidate partially written cachelines read
927 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) == 0)
928 needs_clflush_before
=
929 !cpu_cache_is_coherent(dev
, obj
->cache_level
);
931 ret
= i915_gem_object_get_pages(obj
);
935 intel_fb_obj_invalidate(obj
, ORIGIN_CPU
);
937 i915_gem_object_pin_pages(obj
);
939 offset
= args
->offset
;
942 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
,
943 offset
>> PAGE_SHIFT
) {
944 struct page
*page
= sg_page_iter_page(&sg_iter
);
945 int partial_cacheline_write
;
950 /* Operation in this page
952 * shmem_page_offset = offset within page in shmem file
953 * page_length = bytes to copy for this page
955 shmem_page_offset
= offset_in_page(offset
);
957 page_length
= remain
;
958 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
959 page_length
= PAGE_SIZE
- shmem_page_offset
;
961 /* If we don't overwrite a cacheline completely we need to be
962 * careful to have up-to-date data by first clflushing. Don't
963 * overcomplicate things and flush the entire patch. */
964 partial_cacheline_write
= needs_clflush_before
&&
965 ((shmem_page_offset
| page_length
)
966 & (boot_cpu_data
.x86_clflush_size
- 1));
968 page_do_bit17_swizzling
= obj_do_bit17_swizzling
&&
969 (page_to_phys(page
) & (1 << 17)) != 0;
971 ret
= shmem_pwrite_fast(page
, shmem_page_offset
, page_length
,
972 user_data
, page_do_bit17_swizzling
,
973 partial_cacheline_write
,
974 needs_clflush_after
);
979 mutex_unlock(&dev
->struct_mutex
);
980 ret
= shmem_pwrite_slow(page
, shmem_page_offset
, page_length
,
981 user_data
, page_do_bit17_swizzling
,
982 partial_cacheline_write
,
983 needs_clflush_after
);
985 mutex_lock(&dev
->struct_mutex
);
991 remain
-= page_length
;
992 user_data
+= page_length
;
993 offset
+= page_length
;
997 i915_gem_object_unpin_pages(obj
);
1001 * Fixup: Flush cpu caches in case we didn't flush the dirty
1002 * cachelines in-line while writing and the object moved
1003 * out of the cpu write domain while we've dropped the lock.
1005 if (!needs_clflush_after
&&
1006 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
1007 if (i915_gem_clflush_object(obj
, obj
->pin_display
))
1008 needs_clflush_after
= true;
1012 if (needs_clflush_after
)
1013 i915_gem_chipset_flush(dev
);
1015 obj
->cache_dirty
= true;
1017 intel_fb_obj_flush(obj
, false, ORIGIN_CPU
);
1022 * Writes data to the object referenced by handle.
1024 * On error, the contents of the buffer that were to be modified are undefined.
1027 i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
1028 struct drm_file
*file
)
1030 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1031 struct drm_i915_gem_pwrite
*args
= data
;
1032 struct drm_i915_gem_object
*obj
;
1035 if (args
->size
== 0)
1038 if (!access_ok(VERIFY_READ
,
1039 to_user_ptr(args
->data_ptr
),
1043 if (likely(!i915
.prefault_disable
)) {
1044 ret
= fault_in_multipages_readable(to_user_ptr(args
->data_ptr
),
1050 intel_runtime_pm_get(dev_priv
);
1052 ret
= i915_mutex_lock_interruptible(dev
);
1056 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1057 if (&obj
->base
== NULL
) {
1062 /* Bounds check destination. */
1063 if (args
->offset
> obj
->base
.size
||
1064 args
->size
> obj
->base
.size
- args
->offset
) {
1069 /* prime objects have no backing filp to GEM pread/pwrite
1072 if (!obj
->base
.filp
) {
1077 trace_i915_gem_object_pwrite(obj
, args
->offset
, args
->size
);
1080 /* We can only do the GTT pwrite on untiled buffers, as otherwise
1081 * it would end up going through the fenced access, and we'll get
1082 * different detiling behavior between reading and writing.
1083 * pread/pwrite currently are reading and writing from the CPU
1084 * perspective, requiring manual detiling by the client.
1086 if (obj
->tiling_mode
== I915_TILING_NONE
&&
1087 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
&&
1088 cpu_write_needs_clflush(obj
)) {
1089 ret
= i915_gem_gtt_pwrite_fast(dev
, obj
, args
, file
);
1090 /* Note that the gtt paths might fail with non-page-backed user
1091 * pointers (e.g. gtt mappings when moving data between
1092 * textures). Fallback to the shmem path in that case. */
1095 if (ret
== -EFAULT
|| ret
== -ENOSPC
) {
1096 if (obj
->phys_handle
)
1097 ret
= i915_gem_phys_pwrite(obj
, args
, file
);
1099 ret
= i915_gem_shmem_pwrite(dev
, obj
, args
, file
);
1103 drm_gem_object_unreference(&obj
->base
);
1105 mutex_unlock(&dev
->struct_mutex
);
1107 intel_runtime_pm_put(dev_priv
);
1113 i915_gem_check_wedge(struct i915_gpu_error
*error
,
1116 if (i915_reset_in_progress(error
)) {
1117 /* Non-interruptible callers can't handle -EAGAIN, hence return
1118 * -EIO unconditionally for these. */
1122 /* Recovery complete, but the reset failed ... */
1123 if (i915_terminally_wedged(error
))
1127 * Check if GPU Reset is in progress - we need intel_ring_begin
1128 * to work properly to reinit the hw state while the gpu is
1129 * still marked as reset-in-progress. Handle this with a flag.
1131 if (!error
->reload_in_reset
)
1138 static void fake_irq(unsigned long data
)
1140 wake_up_process((struct task_struct
*)data
);
1143 static bool missed_irq(struct drm_i915_private
*dev_priv
,
1144 struct intel_engine_cs
*ring
)
1146 return test_bit(ring
->id
, &dev_priv
->gpu_error
.missed_irq_rings
);
1149 static int __i915_spin_request(struct drm_i915_gem_request
*req
)
1151 unsigned long timeout
;
1153 if (i915_gem_request_get_ring(req
)->irq_refcount
)
1156 timeout
= jiffies
+ 1;
1157 while (!need_resched()) {
1158 if (i915_gem_request_completed(req
, true))
1161 if (time_after_eq(jiffies
, timeout
))
1164 cpu_relax_lowlatency();
1166 if (i915_gem_request_completed(req
, false))
1173 * __i915_wait_request - wait until execution of request has finished
1175 * @reset_counter: reset sequence associated with the given request
1176 * @interruptible: do an interruptible wait (normally yes)
1177 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
1179 * Note: It is of utmost importance that the passed in seqno and reset_counter
1180 * values have been read by the caller in an smp safe manner. Where read-side
1181 * locks are involved, it is sufficient to read the reset_counter before
1182 * unlocking the lock that protects the seqno. For lockless tricks, the
1183 * reset_counter _must_ be read before, and an appropriate smp_rmb must be
1186 * Returns 0 if the request was found within the alloted time. Else returns the
1187 * errno with remaining time filled in timeout argument.
1189 int __i915_wait_request(struct drm_i915_gem_request
*req
,
1190 unsigned reset_counter
,
1193 struct intel_rps_client
*rps
)
1195 struct intel_engine_cs
*ring
= i915_gem_request_get_ring(req
);
1196 struct drm_device
*dev
= ring
->dev
;
1197 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1198 const bool irq_test_in_progress
=
1199 ACCESS_ONCE(dev_priv
->gpu_error
.test_irq_rings
) & intel_ring_flag(ring
);
1201 unsigned long timeout_expire
;
1205 WARN(!intel_irqs_enabled(dev_priv
), "IRQs disabled");
1207 if (list_empty(&req
->list
))
1210 if (i915_gem_request_completed(req
, true))
1215 if (WARN_ON(*timeout
< 0))
1221 timeout_expire
= jiffies
+ nsecs_to_jiffies_timeout(*timeout
);
1224 if (INTEL_INFO(dev_priv
)->gen
>= 6)
1225 gen6_rps_boost(dev_priv
, rps
, req
->emitted_jiffies
);
1227 /* Record current time in case interrupted by signal, or wedged */
1228 trace_i915_gem_request_wait_begin(req
);
1229 before
= ktime_get_raw_ns();
1231 /* Optimistic spin for the next jiffie before touching IRQs */
1232 ret
= __i915_spin_request(req
);
1236 if (!irq_test_in_progress
&& WARN_ON(!ring
->irq_get(ring
))) {
1242 struct timer_list timer
;
1244 prepare_to_wait(&ring
->irq_queue
, &wait
,
1245 interruptible
? TASK_INTERRUPTIBLE
: TASK_UNINTERRUPTIBLE
);
1247 /* We need to check whether any gpu reset happened in between
1248 * the caller grabbing the seqno and now ... */
1249 if (reset_counter
!= atomic_read(&dev_priv
->gpu_error
.reset_counter
)) {
1250 /* ... but upgrade the -EAGAIN to an -EIO if the gpu
1251 * is truely gone. */
1252 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, interruptible
);
1258 if (i915_gem_request_completed(req
, false)) {
1263 if (interruptible
&& signal_pending(current
)) {
1268 if (timeout
&& time_after_eq(jiffies
, timeout_expire
)) {
1273 timer
.function
= NULL
;
1274 if (timeout
|| missed_irq(dev_priv
, ring
)) {
1275 unsigned long expire
;
1277 setup_timer_on_stack(&timer
, fake_irq
, (unsigned long)current
);
1278 expire
= missed_irq(dev_priv
, ring
) ? jiffies
+ 1 : timeout_expire
;
1279 mod_timer(&timer
, expire
);
1284 if (timer
.function
) {
1285 del_singleshot_timer_sync(&timer
);
1286 destroy_timer_on_stack(&timer
);
1289 if (!irq_test_in_progress
)
1290 ring
->irq_put(ring
);
1292 finish_wait(&ring
->irq_queue
, &wait
);
1295 now
= ktime_get_raw_ns();
1296 trace_i915_gem_request_wait_end(req
);
1299 s64 tres
= *timeout
- (now
- before
);
1301 *timeout
= tres
< 0 ? 0 : tres
;
1304 * Apparently ktime isn't accurate enough and occasionally has a
1305 * bit of mismatch in the jiffies<->nsecs<->ktime loop. So patch
1306 * things up to make the test happy. We allow up to 1 jiffy.
1308 * This is a regrssion from the timespec->ktime conversion.
1310 if (ret
== -ETIME
&& *timeout
< jiffies_to_usecs(1)*1000)
1317 int i915_gem_request_add_to_client(struct drm_i915_gem_request
*req
,
1318 struct drm_file
*file
)
1320 struct drm_i915_private
*dev_private
;
1321 struct drm_i915_file_private
*file_priv
;
1323 WARN_ON(!req
|| !file
|| req
->file_priv
);
1331 dev_private
= req
->ring
->dev
->dev_private
;
1332 file_priv
= file
->driver_priv
;
1334 spin_lock(&file_priv
->mm
.lock
);
1335 req
->file_priv
= file_priv
;
1336 list_add_tail(&req
->client_list
, &file_priv
->mm
.request_list
);
1337 spin_unlock(&file_priv
->mm
.lock
);
1339 req
->pid
= get_pid(task_pid(current
));
1345 i915_gem_request_remove_from_client(struct drm_i915_gem_request
*request
)
1347 struct drm_i915_file_private
*file_priv
= request
->file_priv
;
1352 spin_lock(&file_priv
->mm
.lock
);
1353 list_del(&request
->client_list
);
1354 request
->file_priv
= NULL
;
1355 spin_unlock(&file_priv
->mm
.lock
);
1357 put_pid(request
->pid
);
1358 request
->pid
= NULL
;
1361 static void i915_gem_request_retire(struct drm_i915_gem_request
*request
)
1363 trace_i915_gem_request_retire(request
);
1365 /* We know the GPU must have read the request to have
1366 * sent us the seqno + interrupt, so use the position
1367 * of tail of the request to update the last known position
1370 * Note this requires that we are always called in request
1373 request
->ringbuf
->last_retired_head
= request
->postfix
;
1375 list_del_init(&request
->list
);
1376 i915_gem_request_remove_from_client(request
);
1378 i915_gem_request_unreference(request
);
1382 __i915_gem_request_retire__upto(struct drm_i915_gem_request
*req
)
1384 struct intel_engine_cs
*engine
= req
->ring
;
1385 struct drm_i915_gem_request
*tmp
;
1387 lockdep_assert_held(&engine
->dev
->struct_mutex
);
1389 if (list_empty(&req
->list
))
1393 tmp
= list_first_entry(&engine
->request_list
,
1394 typeof(*tmp
), list
);
1396 i915_gem_request_retire(tmp
);
1397 } while (tmp
!= req
);
1399 WARN_ON(i915_verify_lists(engine
->dev
));
1403 * Waits for a request to be signaled, and cleans up the
1404 * request and object lists appropriately for that event.
1407 i915_wait_request(struct drm_i915_gem_request
*req
)
1409 struct drm_device
*dev
;
1410 struct drm_i915_private
*dev_priv
;
1414 BUG_ON(req
== NULL
);
1416 dev
= req
->ring
->dev
;
1417 dev_priv
= dev
->dev_private
;
1418 interruptible
= dev_priv
->mm
.interruptible
;
1420 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
1422 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, interruptible
);
1426 ret
= __i915_wait_request(req
,
1427 atomic_read(&dev_priv
->gpu_error
.reset_counter
),
1428 interruptible
, NULL
, NULL
);
1432 __i915_gem_request_retire__upto(req
);
1437 * Ensures that all rendering to the object has completed and the object is
1438 * safe to unbind from the GTT or access from the CPU.
1441 i915_gem_object_wait_rendering(struct drm_i915_gem_object
*obj
,
1450 if (obj
->last_write_req
!= NULL
) {
1451 ret
= i915_wait_request(obj
->last_write_req
);
1455 i
= obj
->last_write_req
->ring
->id
;
1456 if (obj
->last_read_req
[i
] == obj
->last_write_req
)
1457 i915_gem_object_retire__read(obj
, i
);
1459 i915_gem_object_retire__write(obj
);
1462 for (i
= 0; i
< I915_NUM_RINGS
; i
++) {
1463 if (obj
->last_read_req
[i
] == NULL
)
1466 ret
= i915_wait_request(obj
->last_read_req
[i
]);
1470 i915_gem_object_retire__read(obj
, i
);
1472 RQ_BUG_ON(obj
->active
);
1479 i915_gem_object_retire_request(struct drm_i915_gem_object
*obj
,
1480 struct drm_i915_gem_request
*req
)
1482 int ring
= req
->ring
->id
;
1484 if (obj
->last_read_req
[ring
] == req
)
1485 i915_gem_object_retire__read(obj
, ring
);
1486 else if (obj
->last_write_req
== req
)
1487 i915_gem_object_retire__write(obj
);
1489 __i915_gem_request_retire__upto(req
);
1492 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1493 * as the object state may change during this call.
1495 static __must_check
int
1496 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object
*obj
,
1497 struct intel_rps_client
*rps
,
1500 struct drm_device
*dev
= obj
->base
.dev
;
1501 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1502 struct drm_i915_gem_request
*requests
[I915_NUM_RINGS
];
1503 unsigned reset_counter
;
1506 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
1507 BUG_ON(!dev_priv
->mm
.interruptible
);
1512 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, true);
1516 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
1519 struct drm_i915_gem_request
*req
;
1521 req
= obj
->last_write_req
;
1525 requests
[n
++] = i915_gem_request_reference(req
);
1527 for (i
= 0; i
< I915_NUM_RINGS
; i
++) {
1528 struct drm_i915_gem_request
*req
;
1530 req
= obj
->last_read_req
[i
];
1534 requests
[n
++] = i915_gem_request_reference(req
);
1538 mutex_unlock(&dev
->struct_mutex
);
1539 for (i
= 0; ret
== 0 && i
< n
; i
++)
1540 ret
= __i915_wait_request(requests
[i
], reset_counter
, true,
1542 mutex_lock(&dev
->struct_mutex
);
1544 for (i
= 0; i
< n
; i
++) {
1546 i915_gem_object_retire_request(obj
, requests
[i
]);
1547 i915_gem_request_unreference(requests
[i
]);
1553 static struct intel_rps_client
*to_rps_client(struct drm_file
*file
)
1555 struct drm_i915_file_private
*fpriv
= file
->driver_priv
;
1560 * Called when user space prepares to use an object with the CPU, either
1561 * through the mmap ioctl's mapping or a GTT mapping.
1564 i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
1565 struct drm_file
*file
)
1567 struct drm_i915_gem_set_domain
*args
= data
;
1568 struct drm_i915_gem_object
*obj
;
1569 uint32_t read_domains
= args
->read_domains
;
1570 uint32_t write_domain
= args
->write_domain
;
1573 /* Only handle setting domains to types used by the CPU. */
1574 if (write_domain
& I915_GEM_GPU_DOMAINS
)
1577 if (read_domains
& I915_GEM_GPU_DOMAINS
)
1580 /* Having something in the write domain implies it's in the read
1581 * domain, and only that read domain. Enforce that in the request.
1583 if (write_domain
!= 0 && read_domains
!= write_domain
)
1586 ret
= i915_mutex_lock_interruptible(dev
);
1590 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1591 if (&obj
->base
== NULL
) {
1596 /* Try to flush the object off the GPU without holding the lock.
1597 * We will repeat the flush holding the lock in the normal manner
1598 * to catch cases where we are gazumped.
1600 ret
= i915_gem_object_wait_rendering__nonblocking(obj
,
1601 to_rps_client(file
),
1606 if (read_domains
& I915_GEM_DOMAIN_GTT
)
1607 ret
= i915_gem_object_set_to_gtt_domain(obj
, write_domain
!= 0);
1609 ret
= i915_gem_object_set_to_cpu_domain(obj
, write_domain
!= 0);
1611 if (write_domain
!= 0)
1612 intel_fb_obj_invalidate(obj
,
1613 write_domain
== I915_GEM_DOMAIN_GTT
?
1614 ORIGIN_GTT
: ORIGIN_CPU
);
1617 drm_gem_object_unreference(&obj
->base
);
1619 mutex_unlock(&dev
->struct_mutex
);
1624 * Called when user space has done writes to this buffer
1627 i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1628 struct drm_file
*file
)
1630 struct drm_i915_gem_sw_finish
*args
= data
;
1631 struct drm_i915_gem_object
*obj
;
1634 ret
= i915_mutex_lock_interruptible(dev
);
1638 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1639 if (&obj
->base
== NULL
) {
1644 /* Pinned buffers may be scanout, so flush the cache */
1645 if (obj
->pin_display
)
1646 i915_gem_object_flush_cpu_write_domain(obj
);
1648 drm_gem_object_unreference(&obj
->base
);
1650 mutex_unlock(&dev
->struct_mutex
);
1655 * Maps the contents of an object, returning the address it is mapped
1658 * While the mapping holds a reference on the contents of the object, it doesn't
1659 * imply a ref on the object itself.
1663 * DRM driver writers who look a this function as an example for how to do GEM
1664 * mmap support, please don't implement mmap support like here. The modern way
1665 * to implement DRM mmap support is with an mmap offset ioctl (like
1666 * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly.
1667 * That way debug tooling like valgrind will understand what's going on, hiding
1668 * the mmap call in a driver private ioctl will break that. The i915 driver only
1669 * does cpu mmaps this way because we didn't know better.
1672 i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1673 struct drm_file
*file
)
1675 struct drm_i915_gem_mmap
*args
= data
;
1676 struct drm_gem_object
*obj
;
1679 if (args
->flags
& ~(I915_MMAP_WC
))
1682 if (args
->flags
& I915_MMAP_WC
&& !cpu_has_pat
)
1685 obj
= drm_gem_object_lookup(dev
, file
, args
->handle
);
1689 /* prime objects have no backing filp to GEM mmap
1693 drm_gem_object_unreference_unlocked(obj
);
1697 addr
= vm_mmap(obj
->filp
, 0, args
->size
,
1698 PROT_READ
| PROT_WRITE
, MAP_SHARED
,
1700 if (args
->flags
& I915_MMAP_WC
) {
1701 struct mm_struct
*mm
= current
->mm
;
1702 struct vm_area_struct
*vma
;
1704 down_write(&mm
->mmap_sem
);
1705 vma
= find_vma(mm
, addr
);
1708 pgprot_writecombine(vm_get_page_prot(vma
->vm_flags
));
1711 up_write(&mm
->mmap_sem
);
1713 drm_gem_object_unreference_unlocked(obj
);
1714 if (IS_ERR((void *)addr
))
1717 args
->addr_ptr
= (uint64_t) addr
;
1723 * i915_gem_fault - fault a page into the GTT
1724 * @vma: VMA in question
1727 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1728 * from userspace. The fault handler takes care of binding the object to
1729 * the GTT (if needed), allocating and programming a fence register (again,
1730 * only if needed based on whether the old reg is still valid or the object
1731 * is tiled) and inserting a new PTE into the faulting process.
1733 * Note that the faulting process may involve evicting existing objects
1734 * from the GTT and/or fence registers to make room. So performance may
1735 * suffer if the GTT working set is large or there are few fence registers
1738 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
)
1740 struct drm_i915_gem_object
*obj
= to_intel_bo(vma
->vm_private_data
);
1741 struct drm_device
*dev
= obj
->base
.dev
;
1742 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1743 struct i915_ggtt_view view
= i915_ggtt_view_normal
;
1744 pgoff_t page_offset
;
1747 bool write
= !!(vmf
->flags
& FAULT_FLAG_WRITE
);
1749 intel_runtime_pm_get(dev_priv
);
1751 /* We don't use vmf->pgoff since that has the fake offset */
1752 page_offset
= ((unsigned long)vmf
->virtual_address
- vma
->vm_start
) >>
1755 ret
= i915_mutex_lock_interruptible(dev
);
1759 trace_i915_gem_object_fault(obj
, page_offset
, true, write
);
1761 /* Try to flush the object off the GPU first without holding the lock.
1762 * Upon reacquiring the lock, we will perform our sanity checks and then
1763 * repeat the flush holding the lock in the normal manner to catch cases
1764 * where we are gazumped.
1766 ret
= i915_gem_object_wait_rendering__nonblocking(obj
, NULL
, !write
);
1770 /* Access to snoopable pages through the GTT is incoherent. */
1771 if (obj
->cache_level
!= I915_CACHE_NONE
&& !HAS_LLC(dev
)) {
1776 /* Use a partial view if the object is bigger than the aperture. */
1777 if (obj
->base
.size
>= dev_priv
->gtt
.mappable_end
&&
1778 obj
->tiling_mode
== I915_TILING_NONE
) {
1779 static const unsigned int chunk_size
= 256; // 1 MiB
1781 memset(&view
, 0, sizeof(view
));
1782 view
.type
= I915_GGTT_VIEW_PARTIAL
;
1783 view
.params
.partial
.offset
= rounddown(page_offset
, chunk_size
);
1784 view
.params
.partial
.size
=
1787 (vma
->vm_end
- vma
->vm_start
)/PAGE_SIZE
-
1788 view
.params
.partial
.offset
);
1791 /* Now pin it into the GTT if needed */
1792 ret
= i915_gem_object_ggtt_pin(obj
, &view
, 0, PIN_MAPPABLE
);
1796 ret
= i915_gem_object_set_to_gtt_domain(obj
, write
);
1800 ret
= i915_gem_object_get_fence(obj
);
1804 /* Finally, remap it using the new GTT offset */
1805 pfn
= dev_priv
->gtt
.mappable_base
+
1806 i915_gem_obj_ggtt_offset_view(obj
, &view
);
1809 if (unlikely(view
.type
== I915_GGTT_VIEW_PARTIAL
)) {
1810 /* Overriding existing pages in partial view does not cause
1811 * us any trouble as TLBs are still valid because the fault
1812 * is due to userspace losing part of the mapping or never
1813 * having accessed it before (at this partials' range).
1815 unsigned long base
= vma
->vm_start
+
1816 (view
.params
.partial
.offset
<< PAGE_SHIFT
);
1819 for (i
= 0; i
< view
.params
.partial
.size
; i
++) {
1820 ret
= vm_insert_pfn(vma
, base
+ i
* PAGE_SIZE
, pfn
+ i
);
1825 obj
->fault_mappable
= true;
1827 if (!obj
->fault_mappable
) {
1828 unsigned long size
= min_t(unsigned long,
1829 vma
->vm_end
- vma
->vm_start
,
1833 for (i
= 0; i
< size
>> PAGE_SHIFT
; i
++) {
1834 ret
= vm_insert_pfn(vma
,
1835 (unsigned long)vma
->vm_start
+ i
* PAGE_SIZE
,
1841 obj
->fault_mappable
= true;
1843 ret
= vm_insert_pfn(vma
,
1844 (unsigned long)vmf
->virtual_address
,
1848 i915_gem_object_ggtt_unpin_view(obj
, &view
);
1850 mutex_unlock(&dev
->struct_mutex
);
1855 * We eat errors when the gpu is terminally wedged to avoid
1856 * userspace unduly crashing (gl has no provisions for mmaps to
1857 * fail). But any other -EIO isn't ours (e.g. swap in failure)
1858 * and so needs to be reported.
1860 if (!i915_terminally_wedged(&dev_priv
->gpu_error
)) {
1861 ret
= VM_FAULT_SIGBUS
;
1866 * EAGAIN means the gpu is hung and we'll wait for the error
1867 * handler to reset everything when re-faulting in
1868 * i915_mutex_lock_interruptible.
1875 * EBUSY is ok: this just means that another thread
1876 * already did the job.
1878 ret
= VM_FAULT_NOPAGE
;
1885 ret
= VM_FAULT_SIGBUS
;
1888 WARN_ONCE(ret
, "unhandled error in i915_gem_fault: %i\n", ret
);
1889 ret
= VM_FAULT_SIGBUS
;
1893 intel_runtime_pm_put(dev_priv
);
1898 * i915_gem_release_mmap - remove physical page mappings
1899 * @obj: obj in question
1901 * Preserve the reservation of the mmapping with the DRM core code, but
1902 * relinquish ownership of the pages back to the system.
1904 * It is vital that we remove the page mapping if we have mapped a tiled
1905 * object through the GTT and then lose the fence register due to
1906 * resource pressure. Similarly if the object has been moved out of the
1907 * aperture, than pages mapped into userspace must be revoked. Removing the
1908 * mapping will then trigger a page fault on the next user access, allowing
1909 * fixup by i915_gem_fault().
1912 i915_gem_release_mmap(struct drm_i915_gem_object
*obj
)
1914 if (!obj
->fault_mappable
)
1917 drm_vma_node_unmap(&obj
->base
.vma_node
,
1918 obj
->base
.dev
->anon_inode
->i_mapping
);
1919 obj
->fault_mappable
= false;
1923 i915_gem_release_all_mmaps(struct drm_i915_private
*dev_priv
)
1925 struct drm_i915_gem_object
*obj
;
1927 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
)
1928 i915_gem_release_mmap(obj
);
1932 i915_gem_get_gtt_size(struct drm_device
*dev
, uint32_t size
, int tiling_mode
)
1936 if (INTEL_INFO(dev
)->gen
>= 4 ||
1937 tiling_mode
== I915_TILING_NONE
)
1940 /* Previous chips need a power-of-two fence region when tiling */
1941 if (INTEL_INFO(dev
)->gen
== 3)
1942 gtt_size
= 1024*1024;
1944 gtt_size
= 512*1024;
1946 while (gtt_size
< size
)
1953 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1954 * @obj: object to check
1956 * Return the required GTT alignment for an object, taking into account
1957 * potential fence register mapping.
1960 i915_gem_get_gtt_alignment(struct drm_device
*dev
, uint32_t size
,
1961 int tiling_mode
, bool fenced
)
1964 * Minimum alignment is 4k (GTT page size), but might be greater
1965 * if a fence register is needed for the object.
1967 if (INTEL_INFO(dev
)->gen
>= 4 || (!fenced
&& IS_G33(dev
)) ||
1968 tiling_mode
== I915_TILING_NONE
)
1972 * Previous chips need to be aligned to the size of the smallest
1973 * fence register that can contain the object.
1975 return i915_gem_get_gtt_size(dev
, size
, tiling_mode
);
1978 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object
*obj
)
1980 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
1983 if (drm_vma_node_has_offset(&obj
->base
.vma_node
))
1986 dev_priv
->mm
.shrinker_no_lock_stealing
= true;
1988 ret
= drm_gem_create_mmap_offset(&obj
->base
);
1992 /* Badly fragmented mmap space? The only way we can recover
1993 * space is by destroying unwanted objects. We can't randomly release
1994 * mmap_offsets as userspace expects them to be persistent for the
1995 * lifetime of the objects. The closest we can is to release the
1996 * offsets on purgeable objects by truncating it and marking it purged,
1997 * which prevents userspace from ever using that object again.
1999 i915_gem_shrink(dev_priv
,
2000 obj
->base
.size
>> PAGE_SHIFT
,
2002 I915_SHRINK_UNBOUND
|
2003 I915_SHRINK_PURGEABLE
);
2004 ret
= drm_gem_create_mmap_offset(&obj
->base
);
2008 i915_gem_shrink_all(dev_priv
);
2009 ret
= drm_gem_create_mmap_offset(&obj
->base
);
2011 dev_priv
->mm
.shrinker_no_lock_stealing
= false;
2016 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object
*obj
)
2018 drm_gem_free_mmap_offset(&obj
->base
);
2022 i915_gem_mmap_gtt(struct drm_file
*file
,
2023 struct drm_device
*dev
,
2027 struct drm_i915_gem_object
*obj
;
2030 ret
= i915_mutex_lock_interruptible(dev
);
2034 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, handle
));
2035 if (&obj
->base
== NULL
) {
2040 if (obj
->madv
!= I915_MADV_WILLNEED
) {
2041 DRM_DEBUG("Attempting to mmap a purgeable buffer\n");
2046 ret
= i915_gem_object_create_mmap_offset(obj
);
2050 *offset
= drm_vma_node_offset_addr(&obj
->base
.vma_node
);
2053 drm_gem_object_unreference(&obj
->base
);
2055 mutex_unlock(&dev
->struct_mutex
);
2060 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
2062 * @data: GTT mapping ioctl data
2063 * @file: GEM object info
2065 * Simply returns the fake offset to userspace so it can mmap it.
2066 * The mmap call will end up in drm_gem_mmap(), which will set things
2067 * up so we can get faults in the handler above.
2069 * The fault handler will take care of binding the object into the GTT
2070 * (since it may have been evicted to make room for something), allocating
2071 * a fence register, and mapping the appropriate aperture address into
2075 i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
2076 struct drm_file
*file
)
2078 struct drm_i915_gem_mmap_gtt
*args
= data
;
2080 return i915_gem_mmap_gtt(file
, dev
, args
->handle
, &args
->offset
);
2083 /* Immediately discard the backing storage */
2085 i915_gem_object_truncate(struct drm_i915_gem_object
*obj
)
2087 i915_gem_object_free_mmap_offset(obj
);
2089 if (obj
->base
.filp
== NULL
)
2092 /* Our goal here is to return as much of the memory as
2093 * is possible back to the system as we are called from OOM.
2094 * To do this we must instruct the shmfs to drop all of its
2095 * backing pages, *now*.
2097 shmem_truncate_range(file_inode(obj
->base
.filp
), 0, (loff_t
)-1);
2098 obj
->madv
= __I915_MADV_PURGED
;
2101 /* Try to discard unwanted pages */
2103 i915_gem_object_invalidate(struct drm_i915_gem_object
*obj
)
2105 struct address_space
*mapping
;
2107 switch (obj
->madv
) {
2108 case I915_MADV_DONTNEED
:
2109 i915_gem_object_truncate(obj
);
2110 case __I915_MADV_PURGED
:
2114 if (obj
->base
.filp
== NULL
)
2117 mapping
= file_inode(obj
->base
.filp
)->i_mapping
,
2118 invalidate_mapping_pages(mapping
, 0, (loff_t
)-1);
2122 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object
*obj
)
2124 struct sg_page_iter sg_iter
;
2127 BUG_ON(obj
->madv
== __I915_MADV_PURGED
);
2129 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
2131 /* In the event of a disaster, abandon all caches and
2132 * hope for the best.
2134 WARN_ON(ret
!= -EIO
);
2135 i915_gem_clflush_object(obj
, true);
2136 obj
->base
.read_domains
= obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
2139 i915_gem_gtt_finish_object(obj
);
2141 if (i915_gem_object_needs_bit17_swizzle(obj
))
2142 i915_gem_object_save_bit_17_swizzle(obj
);
2144 if (obj
->madv
== I915_MADV_DONTNEED
)
2147 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
, 0) {
2148 struct page
*page
= sg_page_iter_page(&sg_iter
);
2151 set_page_dirty(page
);
2153 if (obj
->madv
== I915_MADV_WILLNEED
)
2154 mark_page_accessed(page
);
2156 page_cache_release(page
);
2160 sg_free_table(obj
->pages
);
2165 i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
)
2167 const struct drm_i915_gem_object_ops
*ops
= obj
->ops
;
2169 if (obj
->pages
== NULL
)
2172 if (obj
->pages_pin_count
)
2175 BUG_ON(i915_gem_obj_bound_any(obj
));
2177 /* ->put_pages might need to allocate memory for the bit17 swizzle
2178 * array, hence protect them from being reaped by removing them from gtt
2180 list_del(&obj
->global_list
);
2182 ops
->put_pages(obj
);
2185 i915_gem_object_invalidate(obj
);
2191 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object
*obj
)
2193 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2195 struct address_space
*mapping
;
2196 struct sg_table
*st
;
2197 struct scatterlist
*sg
;
2198 struct sg_page_iter sg_iter
;
2200 unsigned long last_pfn
= 0; /* suppress gcc warning */
2204 /* Assert that the object is not currently in any GPU domain. As it
2205 * wasn't in the GTT, there shouldn't be any way it could have been in
2208 BUG_ON(obj
->base
.read_domains
& I915_GEM_GPU_DOMAINS
);
2209 BUG_ON(obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
);
2211 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
2215 page_count
= obj
->base
.size
/ PAGE_SIZE
;
2216 if (sg_alloc_table(st
, page_count
, GFP_KERNEL
)) {
2221 /* Get the list of pages out of our struct file. They'll be pinned
2222 * at this point until we release them.
2224 * Fail silently without starting the shrinker
2226 mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
2227 gfp
= mapping_gfp_constraint(mapping
, ~(__GFP_IO
| __GFP_RECLAIM
));
2228 gfp
|= __GFP_NORETRY
| __GFP_NOWARN
;
2231 for (i
= 0; i
< page_count
; i
++) {
2232 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
2234 i915_gem_shrink(dev_priv
,
2237 I915_SHRINK_UNBOUND
|
2238 I915_SHRINK_PURGEABLE
);
2239 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
2242 /* We've tried hard to allocate the memory by reaping
2243 * our own buffer, now let the real VM do its job and
2244 * go down in flames if truly OOM.
2246 i915_gem_shrink_all(dev_priv
);
2247 page
= shmem_read_mapping_page(mapping
, i
);
2249 ret
= PTR_ERR(page
);
2253 #ifdef CONFIG_SWIOTLB
2254 if (swiotlb_nr_tbl()) {
2256 sg_set_page(sg
, page
, PAGE_SIZE
, 0);
2261 if (!i
|| page_to_pfn(page
) != last_pfn
+ 1) {
2265 sg_set_page(sg
, page
, PAGE_SIZE
, 0);
2267 sg
->length
+= PAGE_SIZE
;
2269 last_pfn
= page_to_pfn(page
);
2271 /* Check that the i965g/gm workaround works. */
2272 WARN_ON((gfp
& __GFP_DMA32
) && (last_pfn
>= 0x00100000UL
));
2274 #ifdef CONFIG_SWIOTLB
2275 if (!swiotlb_nr_tbl())
2280 ret
= i915_gem_gtt_prepare_object(obj
);
2284 if (i915_gem_object_needs_bit17_swizzle(obj
))
2285 i915_gem_object_do_bit_17_swizzle(obj
);
2287 if (obj
->tiling_mode
!= I915_TILING_NONE
&&
2288 dev_priv
->quirks
& QUIRK_PIN_SWIZZLED_PAGES
)
2289 i915_gem_object_pin_pages(obj
);
2295 for_each_sg_page(st
->sgl
, &sg_iter
, st
->nents
, 0)
2296 page_cache_release(sg_page_iter_page(&sg_iter
));
2300 /* shmemfs first checks if there is enough memory to allocate the page
2301 * and reports ENOSPC should there be insufficient, along with the usual
2302 * ENOMEM for a genuine allocation failure.
2304 * We use ENOSPC in our driver to mean that we have run out of aperture
2305 * space and so want to translate the error from shmemfs back to our
2306 * usual understanding of ENOMEM.
2314 /* Ensure that the associated pages are gathered from the backing storage
2315 * and pinned into our object. i915_gem_object_get_pages() may be called
2316 * multiple times before they are released by a single call to
2317 * i915_gem_object_put_pages() - once the pages are no longer referenced
2318 * either as a result of memory pressure (reaping pages under the shrinker)
2319 * or as the object is itself released.
2322 i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
)
2324 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2325 const struct drm_i915_gem_object_ops
*ops
= obj
->ops
;
2331 if (obj
->madv
!= I915_MADV_WILLNEED
) {
2332 DRM_DEBUG("Attempting to obtain a purgeable object\n");
2336 BUG_ON(obj
->pages_pin_count
);
2338 ret
= ops
->get_pages(obj
);
2342 list_add_tail(&obj
->global_list
, &dev_priv
->mm
.unbound_list
);
2344 obj
->get_page
.sg
= obj
->pages
->sgl
;
2345 obj
->get_page
.last
= 0;
2350 void i915_vma_move_to_active(struct i915_vma
*vma
,
2351 struct drm_i915_gem_request
*req
)
2353 struct drm_i915_gem_object
*obj
= vma
->obj
;
2354 struct intel_engine_cs
*ring
;
2356 ring
= i915_gem_request_get_ring(req
);
2358 /* Add a reference if we're newly entering the active list. */
2359 if (obj
->active
== 0)
2360 drm_gem_object_reference(&obj
->base
);
2361 obj
->active
|= intel_ring_flag(ring
);
2363 list_move_tail(&obj
->ring_list
[ring
->id
], &ring
->active_list
);
2364 i915_gem_request_assign(&obj
->last_read_req
[ring
->id
], req
);
2366 list_move_tail(&vma
->mm_list
, &vma
->vm
->active_list
);
2370 i915_gem_object_retire__write(struct drm_i915_gem_object
*obj
)
2372 RQ_BUG_ON(obj
->last_write_req
== NULL
);
2373 RQ_BUG_ON(!(obj
->active
& intel_ring_flag(obj
->last_write_req
->ring
)));
2375 i915_gem_request_assign(&obj
->last_write_req
, NULL
);
2376 intel_fb_obj_flush(obj
, true, ORIGIN_CS
);
2380 i915_gem_object_retire__read(struct drm_i915_gem_object
*obj
, int ring
)
2382 struct i915_vma
*vma
;
2384 RQ_BUG_ON(obj
->last_read_req
[ring
] == NULL
);
2385 RQ_BUG_ON(!(obj
->active
& (1 << ring
)));
2387 list_del_init(&obj
->ring_list
[ring
]);
2388 i915_gem_request_assign(&obj
->last_read_req
[ring
], NULL
);
2390 if (obj
->last_write_req
&& obj
->last_write_req
->ring
->id
== ring
)
2391 i915_gem_object_retire__write(obj
);
2393 obj
->active
&= ~(1 << ring
);
2397 /* Bump our place on the bound list to keep it roughly in LRU order
2398 * so that we don't steal from recently used but inactive objects
2399 * (unless we are forced to ofc!)
2401 list_move_tail(&obj
->global_list
,
2402 &to_i915(obj
->base
.dev
)->mm
.bound_list
);
2404 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
) {
2405 if (!list_empty(&vma
->mm_list
))
2406 list_move_tail(&vma
->mm_list
, &vma
->vm
->inactive_list
);
2409 i915_gem_request_assign(&obj
->last_fenced_req
, NULL
);
2410 drm_gem_object_unreference(&obj
->base
);
2414 i915_gem_init_seqno(struct drm_device
*dev
, u32 seqno
)
2416 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2417 struct intel_engine_cs
*ring
;
2420 /* Carefully retire all requests without writing to the rings */
2421 for_each_ring(ring
, dev_priv
, i
) {
2422 ret
= intel_ring_idle(ring
);
2426 i915_gem_retire_requests(dev
);
2428 /* Finally reset hw state */
2429 for_each_ring(ring
, dev_priv
, i
) {
2430 intel_ring_init_seqno(ring
, seqno
);
2432 for (j
= 0; j
< ARRAY_SIZE(ring
->semaphore
.sync_seqno
); j
++)
2433 ring
->semaphore
.sync_seqno
[j
] = 0;
2439 int i915_gem_set_seqno(struct drm_device
*dev
, u32 seqno
)
2441 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2447 /* HWS page needs to be set less than what we
2448 * will inject to ring
2450 ret
= i915_gem_init_seqno(dev
, seqno
- 1);
2454 /* Carefully set the last_seqno value so that wrap
2455 * detection still works
2457 dev_priv
->next_seqno
= seqno
;
2458 dev_priv
->last_seqno
= seqno
- 1;
2459 if (dev_priv
->last_seqno
== 0)
2460 dev_priv
->last_seqno
--;
2466 i915_gem_get_seqno(struct drm_device
*dev
, u32
*seqno
)
2468 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2470 /* reserve 0 for non-seqno */
2471 if (dev_priv
->next_seqno
== 0) {
2472 int ret
= i915_gem_init_seqno(dev
, 0);
2476 dev_priv
->next_seqno
= 1;
2479 *seqno
= dev_priv
->last_seqno
= dev_priv
->next_seqno
++;
2484 * NB: This function is not allowed to fail. Doing so would mean the the
2485 * request is not being tracked for completion but the work itself is
2486 * going to happen on the hardware. This would be a Bad Thing(tm).
2488 void __i915_add_request(struct drm_i915_gem_request
*request
,
2489 struct drm_i915_gem_object
*obj
,
2492 struct intel_engine_cs
*ring
;
2493 struct drm_i915_private
*dev_priv
;
2494 struct intel_ringbuffer
*ringbuf
;
2498 if (WARN_ON(request
== NULL
))
2501 ring
= request
->ring
;
2502 dev_priv
= ring
->dev
->dev_private
;
2503 ringbuf
= request
->ringbuf
;
2506 * To ensure that this call will not fail, space for its emissions
2507 * should already have been reserved in the ring buffer. Let the ring
2508 * know that it is time to use that space up.
2510 intel_ring_reserved_space_use(ringbuf
);
2512 request_start
= intel_ring_get_tail(ringbuf
);
2514 * Emit any outstanding flushes - execbuf can fail to emit the flush
2515 * after having emitted the batchbuffer command. Hence we need to fix
2516 * things up similar to emitting the lazy request. The difference here
2517 * is that the flush _must_ happen before the next request, no matter
2521 if (i915
.enable_execlists
)
2522 ret
= logical_ring_flush_all_caches(request
);
2524 ret
= intel_ring_flush_all_caches(request
);
2525 /* Not allowed to fail! */
2526 WARN(ret
, "*_ring_flush_all_caches failed: %d!\n", ret
);
2529 /* Record the position of the start of the request so that
2530 * should we detect the updated seqno part-way through the
2531 * GPU processing the request, we never over-estimate the
2532 * position of the head.
2534 request
->postfix
= intel_ring_get_tail(ringbuf
);
2536 if (i915
.enable_execlists
)
2537 ret
= ring
->emit_request(request
);
2539 ret
= ring
->add_request(request
);
2541 request
->tail
= intel_ring_get_tail(ringbuf
);
2543 /* Not allowed to fail! */
2544 WARN(ret
, "emit|add_request failed: %d!\n", ret
);
2546 request
->head
= request_start
;
2548 /* Whilst this request exists, batch_obj will be on the
2549 * active_list, and so will hold the active reference. Only when this
2550 * request is retired will the the batch_obj be moved onto the
2551 * inactive_list and lose its active reference. Hence we do not need
2552 * to explicitly hold another reference here.
2554 request
->batch_obj
= obj
;
2556 request
->emitted_jiffies
= jiffies
;
2557 ring
->last_submitted_seqno
= request
->seqno
;
2558 list_add_tail(&request
->list
, &ring
->request_list
);
2560 trace_i915_gem_request_add(request
);
2562 i915_queue_hangcheck(ring
->dev
);
2564 queue_delayed_work(dev_priv
->wq
,
2565 &dev_priv
->mm
.retire_work
,
2566 round_jiffies_up_relative(HZ
));
2567 intel_mark_busy(dev_priv
->dev
);
2569 /* Sanity check that the reserved size was large enough. */
2570 intel_ring_reserved_space_end(ringbuf
);
2573 static bool i915_context_is_banned(struct drm_i915_private
*dev_priv
,
2574 const struct intel_context
*ctx
)
2576 unsigned long elapsed
;
2578 elapsed
= get_seconds() - ctx
->hang_stats
.guilty_ts
;
2580 if (ctx
->hang_stats
.banned
)
2583 if (ctx
->hang_stats
.ban_period_seconds
&&
2584 elapsed
<= ctx
->hang_stats
.ban_period_seconds
) {
2585 if (!i915_gem_context_is_default(ctx
)) {
2586 DRM_DEBUG("context hanging too fast, banning!\n");
2588 } else if (i915_stop_ring_allow_ban(dev_priv
)) {
2589 if (i915_stop_ring_allow_warn(dev_priv
))
2590 DRM_ERROR("gpu hanging too fast, banning!\n");
2598 static void i915_set_reset_status(struct drm_i915_private
*dev_priv
,
2599 struct intel_context
*ctx
,
2602 struct i915_ctx_hang_stats
*hs
;
2607 hs
= &ctx
->hang_stats
;
2610 hs
->banned
= i915_context_is_banned(dev_priv
, ctx
);
2612 hs
->guilty_ts
= get_seconds();
2614 hs
->batch_pending
++;
2618 void i915_gem_request_free(struct kref
*req_ref
)
2620 struct drm_i915_gem_request
*req
= container_of(req_ref
,
2622 struct intel_context
*ctx
= req
->ctx
;
2625 i915_gem_request_remove_from_client(req
);
2628 if (i915
.enable_execlists
) {
2629 if (ctx
!= req
->ring
->default_context
)
2630 intel_lr_context_unpin(req
);
2633 i915_gem_context_unreference(ctx
);
2636 kmem_cache_free(req
->i915
->requests
, req
);
2639 int i915_gem_request_alloc(struct intel_engine_cs
*ring
,
2640 struct intel_context
*ctx
,
2641 struct drm_i915_gem_request
**req_out
)
2643 struct drm_i915_private
*dev_priv
= to_i915(ring
->dev
);
2644 struct drm_i915_gem_request
*req
;
2652 req
= kmem_cache_zalloc(dev_priv
->requests
, GFP_KERNEL
);
2656 ret
= i915_gem_get_seqno(ring
->dev
, &req
->seqno
);
2660 kref_init(&req
->ref
);
2661 req
->i915
= dev_priv
;
2664 i915_gem_context_reference(req
->ctx
);
2666 if (i915
.enable_execlists
)
2667 ret
= intel_logical_ring_alloc_request_extras(req
);
2669 ret
= intel_ring_alloc_request_extras(req
);
2671 i915_gem_context_unreference(req
->ctx
);
2676 * Reserve space in the ring buffer for all the commands required to
2677 * eventually emit this request. This is to guarantee that the
2678 * i915_add_request() call can't fail. Note that the reserve may need
2679 * to be redone if the request is not actually submitted straight
2680 * away, e.g. because a GPU scheduler has deferred it.
2682 if (i915
.enable_execlists
)
2683 ret
= intel_logical_ring_reserve_space(req
);
2685 ret
= intel_ring_reserve_space(req
);
2688 * At this point, the request is fully allocated even if not
2689 * fully prepared. Thus it can be cleaned up using the proper
2692 i915_gem_request_cancel(req
);
2700 kmem_cache_free(dev_priv
->requests
, req
);
2704 void i915_gem_request_cancel(struct drm_i915_gem_request
*req
)
2706 intel_ring_reserved_space_cancel(req
->ringbuf
);
2708 i915_gem_request_unreference(req
);
2711 struct drm_i915_gem_request
*
2712 i915_gem_find_active_request(struct intel_engine_cs
*ring
)
2714 struct drm_i915_gem_request
*request
;
2716 list_for_each_entry(request
, &ring
->request_list
, list
) {
2717 if (i915_gem_request_completed(request
, false))
2726 static void i915_gem_reset_ring_status(struct drm_i915_private
*dev_priv
,
2727 struct intel_engine_cs
*ring
)
2729 struct drm_i915_gem_request
*request
;
2732 request
= i915_gem_find_active_request(ring
);
2734 if (request
== NULL
)
2737 ring_hung
= ring
->hangcheck
.score
>= HANGCHECK_SCORE_RING_HUNG
;
2739 i915_set_reset_status(dev_priv
, request
->ctx
, ring_hung
);
2741 list_for_each_entry_continue(request
, &ring
->request_list
, list
)
2742 i915_set_reset_status(dev_priv
, request
->ctx
, false);
2745 static void i915_gem_reset_ring_cleanup(struct drm_i915_private
*dev_priv
,
2746 struct intel_engine_cs
*ring
)
2748 struct intel_ringbuffer
*buffer
;
2750 while (!list_empty(&ring
->active_list
)) {
2751 struct drm_i915_gem_object
*obj
;
2753 obj
= list_first_entry(&ring
->active_list
,
2754 struct drm_i915_gem_object
,
2755 ring_list
[ring
->id
]);
2757 i915_gem_object_retire__read(obj
, ring
->id
);
2761 * Clear the execlists queue up before freeing the requests, as those
2762 * are the ones that keep the context and ringbuffer backing objects
2766 if (i915
.enable_execlists
) {
2767 spin_lock_irq(&ring
->execlist_lock
);
2769 /* list_splice_tail_init checks for empty lists */
2770 list_splice_tail_init(&ring
->execlist_queue
,
2771 &ring
->execlist_retired_req_list
);
2773 spin_unlock_irq(&ring
->execlist_lock
);
2774 intel_execlists_retire_requests(ring
);
2778 * We must free the requests after all the corresponding objects have
2779 * been moved off active lists. Which is the same order as the normal
2780 * retire_requests function does. This is important if object hold
2781 * implicit references on things like e.g. ppgtt address spaces through
2784 while (!list_empty(&ring
->request_list
)) {
2785 struct drm_i915_gem_request
*request
;
2787 request
= list_first_entry(&ring
->request_list
,
2788 struct drm_i915_gem_request
,
2791 i915_gem_request_retire(request
);
2794 /* Having flushed all requests from all queues, we know that all
2795 * ringbuffers must now be empty. However, since we do not reclaim
2796 * all space when retiring the request (to prevent HEADs colliding
2797 * with rapid ringbuffer wraparound) the amount of available space
2798 * upon reset is less than when we start. Do one more pass over
2799 * all the ringbuffers to reset last_retired_head.
2801 list_for_each_entry(buffer
, &ring
->buffers
, link
) {
2802 buffer
->last_retired_head
= buffer
->tail
;
2803 intel_ring_update_space(buffer
);
2807 void i915_gem_reset(struct drm_device
*dev
)
2809 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2810 struct intel_engine_cs
*ring
;
2814 * Before we free the objects from the requests, we need to inspect
2815 * them for finding the guilty party. As the requests only borrow
2816 * their reference to the objects, the inspection must be done first.
2818 for_each_ring(ring
, dev_priv
, i
)
2819 i915_gem_reset_ring_status(dev_priv
, ring
);
2821 for_each_ring(ring
, dev_priv
, i
)
2822 i915_gem_reset_ring_cleanup(dev_priv
, ring
);
2824 i915_gem_context_reset(dev
);
2826 i915_gem_restore_fences(dev
);
2828 WARN_ON(i915_verify_lists(dev
));
2832 * This function clears the request list as sequence numbers are passed.
2835 i915_gem_retire_requests_ring(struct intel_engine_cs
*ring
)
2837 WARN_ON(i915_verify_lists(ring
->dev
));
2839 /* Retire requests first as we use it above for the early return.
2840 * If we retire requests last, we may use a later seqno and so clear
2841 * the requests lists without clearing the active list, leading to
2844 while (!list_empty(&ring
->request_list
)) {
2845 struct drm_i915_gem_request
*request
;
2847 request
= list_first_entry(&ring
->request_list
,
2848 struct drm_i915_gem_request
,
2851 if (!i915_gem_request_completed(request
, true))
2854 i915_gem_request_retire(request
);
2857 /* Move any buffers on the active list that are no longer referenced
2858 * by the ringbuffer to the flushing/inactive lists as appropriate,
2859 * before we free the context associated with the requests.
2861 while (!list_empty(&ring
->active_list
)) {
2862 struct drm_i915_gem_object
*obj
;
2864 obj
= list_first_entry(&ring
->active_list
,
2865 struct drm_i915_gem_object
,
2866 ring_list
[ring
->id
]);
2868 if (!list_empty(&obj
->last_read_req
[ring
->id
]->list
))
2871 i915_gem_object_retire__read(obj
, ring
->id
);
2874 if (unlikely(ring
->trace_irq_req
&&
2875 i915_gem_request_completed(ring
->trace_irq_req
, true))) {
2876 ring
->irq_put(ring
);
2877 i915_gem_request_assign(&ring
->trace_irq_req
, NULL
);
2880 WARN_ON(i915_verify_lists(ring
->dev
));
2884 i915_gem_retire_requests(struct drm_device
*dev
)
2886 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2887 struct intel_engine_cs
*ring
;
2891 for_each_ring(ring
, dev_priv
, i
) {
2892 i915_gem_retire_requests_ring(ring
);
2893 idle
&= list_empty(&ring
->request_list
);
2894 if (i915
.enable_execlists
) {
2895 unsigned long flags
;
2897 spin_lock_irqsave(&ring
->execlist_lock
, flags
);
2898 idle
&= list_empty(&ring
->execlist_queue
);
2899 spin_unlock_irqrestore(&ring
->execlist_lock
, flags
);
2901 intel_execlists_retire_requests(ring
);
2906 mod_delayed_work(dev_priv
->wq
,
2907 &dev_priv
->mm
.idle_work
,
2908 msecs_to_jiffies(100));
2914 i915_gem_retire_work_handler(struct work_struct
*work
)
2916 struct drm_i915_private
*dev_priv
=
2917 container_of(work
, typeof(*dev_priv
), mm
.retire_work
.work
);
2918 struct drm_device
*dev
= dev_priv
->dev
;
2921 /* Come back later if the device is busy... */
2923 if (mutex_trylock(&dev
->struct_mutex
)) {
2924 idle
= i915_gem_retire_requests(dev
);
2925 mutex_unlock(&dev
->struct_mutex
);
2928 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
,
2929 round_jiffies_up_relative(HZ
));
2933 i915_gem_idle_work_handler(struct work_struct
*work
)
2935 struct drm_i915_private
*dev_priv
=
2936 container_of(work
, typeof(*dev_priv
), mm
.idle_work
.work
);
2937 struct drm_device
*dev
= dev_priv
->dev
;
2938 struct intel_engine_cs
*ring
;
2941 for_each_ring(ring
, dev_priv
, i
)
2942 if (!list_empty(&ring
->request_list
))
2945 intel_mark_idle(dev
);
2947 if (mutex_trylock(&dev
->struct_mutex
)) {
2948 struct intel_engine_cs
*ring
;
2951 for_each_ring(ring
, dev_priv
, i
)
2952 i915_gem_batch_pool_fini(&ring
->batch_pool
);
2954 mutex_unlock(&dev
->struct_mutex
);
2959 * Ensures that an object will eventually get non-busy by flushing any required
2960 * write domains, emitting any outstanding lazy request and retiring and
2961 * completed requests.
2964 i915_gem_object_flush_active(struct drm_i915_gem_object
*obj
)
2971 for (i
= 0; i
< I915_NUM_RINGS
; i
++) {
2972 struct drm_i915_gem_request
*req
;
2974 req
= obj
->last_read_req
[i
];
2978 if (list_empty(&req
->list
))
2981 if (i915_gem_request_completed(req
, true)) {
2982 __i915_gem_request_retire__upto(req
);
2984 i915_gem_object_retire__read(obj
, i
);
2992 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2993 * @DRM_IOCTL_ARGS: standard ioctl arguments
2995 * Returns 0 if successful, else an error is returned with the remaining time in
2996 * the timeout parameter.
2997 * -ETIME: object is still busy after timeout
2998 * -ERESTARTSYS: signal interrupted the wait
2999 * -ENONENT: object doesn't exist
3000 * Also possible, but rare:
3001 * -EAGAIN: GPU wedged
3003 * -ENODEV: Internal IRQ fail
3004 * -E?: The add request failed
3006 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
3007 * non-zero timeout parameter the wait ioctl will wait for the given number of
3008 * nanoseconds on an object becoming unbusy. Since the wait itself does so
3009 * without holding struct_mutex the object may become re-busied before this
3010 * function completes. A similar but shorter * race condition exists in the busy
3014 i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
, struct drm_file
*file
)
3016 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3017 struct drm_i915_gem_wait
*args
= data
;
3018 struct drm_i915_gem_object
*obj
;
3019 struct drm_i915_gem_request
*req
[I915_NUM_RINGS
];
3020 unsigned reset_counter
;
3024 if (args
->flags
!= 0)
3027 ret
= i915_mutex_lock_interruptible(dev
);
3031 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->bo_handle
));
3032 if (&obj
->base
== NULL
) {
3033 mutex_unlock(&dev
->struct_mutex
);
3037 /* Need to make sure the object gets inactive eventually. */
3038 ret
= i915_gem_object_flush_active(obj
);
3045 /* Do this after OLR check to make sure we make forward progress polling
3046 * on this IOCTL with a timeout == 0 (like busy ioctl)
3048 if (args
->timeout_ns
== 0) {
3053 drm_gem_object_unreference(&obj
->base
);
3054 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
3056 for (i
= 0; i
< I915_NUM_RINGS
; i
++) {
3057 if (obj
->last_read_req
[i
] == NULL
)
3060 req
[n
++] = i915_gem_request_reference(obj
->last_read_req
[i
]);
3063 mutex_unlock(&dev
->struct_mutex
);
3065 for (i
= 0; i
< n
; i
++) {
3067 ret
= __i915_wait_request(req
[i
], reset_counter
, true,
3068 args
->timeout_ns
> 0 ? &args
->timeout_ns
: NULL
,
3069 to_rps_client(file
));
3070 i915_gem_request_unreference__unlocked(req
[i
]);
3075 drm_gem_object_unreference(&obj
->base
);
3076 mutex_unlock(&dev
->struct_mutex
);
3081 __i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
3082 struct intel_engine_cs
*to
,
3083 struct drm_i915_gem_request
*from_req
,
3084 struct drm_i915_gem_request
**to_req
)
3086 struct intel_engine_cs
*from
;
3089 from
= i915_gem_request_get_ring(from_req
);
3093 if (i915_gem_request_completed(from_req
, true))
3096 if (!i915_semaphore_is_enabled(obj
->base
.dev
)) {
3097 struct drm_i915_private
*i915
= to_i915(obj
->base
.dev
);
3098 ret
= __i915_wait_request(from_req
,
3099 atomic_read(&i915
->gpu_error
.reset_counter
),
3100 i915
->mm
.interruptible
,
3102 &i915
->rps
.semaphores
);
3106 i915_gem_object_retire_request(obj
, from_req
);
3108 int idx
= intel_ring_sync_index(from
, to
);
3109 u32 seqno
= i915_gem_request_get_seqno(from_req
);
3113 if (seqno
<= from
->semaphore
.sync_seqno
[idx
])
3116 if (*to_req
== NULL
) {
3117 ret
= i915_gem_request_alloc(to
, to
->default_context
, to_req
);
3122 trace_i915_gem_ring_sync_to(*to_req
, from
, from_req
);
3123 ret
= to
->semaphore
.sync_to(*to_req
, from
, seqno
);
3127 /* We use last_read_req because sync_to()
3128 * might have just caused seqno wrap under
3131 from
->semaphore
.sync_seqno
[idx
] =
3132 i915_gem_request_get_seqno(obj
->last_read_req
[from
->id
]);
3139 * i915_gem_object_sync - sync an object to a ring.
3141 * @obj: object which may be in use on another ring.
3142 * @to: ring we wish to use the object on. May be NULL.
3143 * @to_req: request we wish to use the object for. See below.
3144 * This will be allocated and returned if a request is
3145 * required but not passed in.
3147 * This code is meant to abstract object synchronization with the GPU.
3148 * Calling with NULL implies synchronizing the object with the CPU
3149 * rather than a particular GPU ring. Conceptually we serialise writes
3150 * between engines inside the GPU. We only allow one engine to write
3151 * into a buffer at any time, but multiple readers. To ensure each has
3152 * a coherent view of memory, we must:
3154 * - If there is an outstanding write request to the object, the new
3155 * request must wait for it to complete (either CPU or in hw, requests
3156 * on the same ring will be naturally ordered).
3158 * - If we are a write request (pending_write_domain is set), the new
3159 * request must wait for outstanding read requests to complete.
3161 * For CPU synchronisation (NULL to) no request is required. For syncing with
3162 * rings to_req must be non-NULL. However, a request does not have to be
3163 * pre-allocated. If *to_req is NULL and sync commands will be emitted then a
3164 * request will be allocated automatically and returned through *to_req. Note
3165 * that it is not guaranteed that commands will be emitted (because the system
3166 * might already be idle). Hence there is no need to create a request that
3167 * might never have any work submitted. Note further that if a request is
3168 * returned in *to_req, it is the responsibility of the caller to submit
3169 * that request (after potentially adding more work to it).
3171 * Returns 0 if successful, else propagates up the lower layer error.
3174 i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
3175 struct intel_engine_cs
*to
,
3176 struct drm_i915_gem_request
**to_req
)
3178 const bool readonly
= obj
->base
.pending_write_domain
== 0;
3179 struct drm_i915_gem_request
*req
[I915_NUM_RINGS
];
3186 return i915_gem_object_wait_rendering(obj
, readonly
);
3190 if (obj
->last_write_req
)
3191 req
[n
++] = obj
->last_write_req
;
3193 for (i
= 0; i
< I915_NUM_RINGS
; i
++)
3194 if (obj
->last_read_req
[i
])
3195 req
[n
++] = obj
->last_read_req
[i
];
3197 for (i
= 0; i
< n
; i
++) {
3198 ret
= __i915_gem_object_sync(obj
, to
, req
[i
], to_req
);
3206 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object
*obj
)
3208 u32 old_write_domain
, old_read_domains
;
3210 /* Force a pagefault for domain tracking on next user access */
3211 i915_gem_release_mmap(obj
);
3213 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
) == 0)
3216 /* Wait for any direct GTT access to complete */
3219 old_read_domains
= obj
->base
.read_domains
;
3220 old_write_domain
= obj
->base
.write_domain
;
3222 obj
->base
.read_domains
&= ~I915_GEM_DOMAIN_GTT
;
3223 obj
->base
.write_domain
&= ~I915_GEM_DOMAIN_GTT
;
3225 trace_i915_gem_object_change_domain(obj
,
3230 static int __i915_vma_unbind(struct i915_vma
*vma
, bool wait
)
3232 struct drm_i915_gem_object
*obj
= vma
->obj
;
3233 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
3236 if (list_empty(&vma
->vma_link
))
3239 if (!drm_mm_node_allocated(&vma
->node
)) {
3240 i915_gem_vma_destroy(vma
);
3247 BUG_ON(obj
->pages
== NULL
);
3250 ret
= i915_gem_object_wait_rendering(obj
, false);
3255 if (i915_is_ggtt(vma
->vm
) &&
3256 vma
->ggtt_view
.type
== I915_GGTT_VIEW_NORMAL
) {
3257 i915_gem_object_finish_gtt(obj
);
3259 /* release the fence reg _after_ flushing */
3260 ret
= i915_gem_object_put_fence(obj
);
3265 trace_i915_vma_unbind(vma
);
3267 vma
->vm
->unbind_vma(vma
);
3270 list_del_init(&vma
->mm_list
);
3271 if (i915_is_ggtt(vma
->vm
)) {
3272 if (vma
->ggtt_view
.type
== I915_GGTT_VIEW_NORMAL
) {
3273 obj
->map_and_fenceable
= false;
3274 } else if (vma
->ggtt_view
.pages
) {
3275 sg_free_table(vma
->ggtt_view
.pages
);
3276 kfree(vma
->ggtt_view
.pages
);
3278 vma
->ggtt_view
.pages
= NULL
;
3281 drm_mm_remove_node(&vma
->node
);
3282 i915_gem_vma_destroy(vma
);
3284 /* Since the unbound list is global, only move to that list if
3285 * no more VMAs exist. */
3286 if (list_empty(&obj
->vma_list
))
3287 list_move_tail(&obj
->global_list
, &dev_priv
->mm
.unbound_list
);
3289 /* And finally now the object is completely decoupled from this vma,
3290 * we can drop its hold on the backing storage and allow it to be
3291 * reaped by the shrinker.
3293 i915_gem_object_unpin_pages(obj
);
3298 int i915_vma_unbind(struct i915_vma
*vma
)
3300 return __i915_vma_unbind(vma
, true);
3303 int __i915_vma_unbind_no_wait(struct i915_vma
*vma
)
3305 return __i915_vma_unbind(vma
, false);
3308 int i915_gpu_idle(struct drm_device
*dev
)
3310 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3311 struct intel_engine_cs
*ring
;
3314 /* Flush everything onto the inactive list. */
3315 for_each_ring(ring
, dev_priv
, i
) {
3316 if (!i915
.enable_execlists
) {
3317 struct drm_i915_gem_request
*req
;
3319 ret
= i915_gem_request_alloc(ring
, ring
->default_context
, &req
);
3323 ret
= i915_switch_context(req
);
3325 i915_gem_request_cancel(req
);
3329 i915_add_request_no_flush(req
);
3332 ret
= intel_ring_idle(ring
);
3337 WARN_ON(i915_verify_lists(dev
));
3341 static bool i915_gem_valid_gtt_space(struct i915_vma
*vma
,
3342 unsigned long cache_level
)
3344 struct drm_mm_node
*gtt_space
= &vma
->node
;
3345 struct drm_mm_node
*other
;
3348 * On some machines we have to be careful when putting differing types
3349 * of snoopable memory together to avoid the prefetcher crossing memory
3350 * domains and dying. During vm initialisation, we decide whether or not
3351 * these constraints apply and set the drm_mm.color_adjust
3354 if (vma
->vm
->mm
.color_adjust
== NULL
)
3357 if (!drm_mm_node_allocated(gtt_space
))
3360 if (list_empty(>t_space
->node_list
))
3363 other
= list_entry(gtt_space
->node_list
.prev
, struct drm_mm_node
, node_list
);
3364 if (other
->allocated
&& !other
->hole_follows
&& other
->color
!= cache_level
)
3367 other
= list_entry(gtt_space
->node_list
.next
, struct drm_mm_node
, node_list
);
3368 if (other
->allocated
&& !gtt_space
->hole_follows
&& other
->color
!= cache_level
)
3375 * Finds free space in the GTT aperture and binds the object or a view of it
3378 static struct i915_vma
*
3379 i915_gem_object_bind_to_vm(struct drm_i915_gem_object
*obj
,
3380 struct i915_address_space
*vm
,
3381 const struct i915_ggtt_view
*ggtt_view
,
3385 struct drm_device
*dev
= obj
->base
.dev
;
3386 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3387 u32 fence_alignment
, unfenced_alignment
;
3388 u32 search_flag
, alloc_flag
;
3390 u64 size
, fence_size
;
3391 struct i915_vma
*vma
;
3394 if (i915_is_ggtt(vm
)) {
3397 if (WARN_ON(!ggtt_view
))
3398 return ERR_PTR(-EINVAL
);
3400 view_size
= i915_ggtt_view_size(obj
, ggtt_view
);
3402 fence_size
= i915_gem_get_gtt_size(dev
,
3405 fence_alignment
= i915_gem_get_gtt_alignment(dev
,
3409 unfenced_alignment
= i915_gem_get_gtt_alignment(dev
,
3413 size
= flags
& PIN_MAPPABLE
? fence_size
: view_size
;
3415 fence_size
= i915_gem_get_gtt_size(dev
,
3418 fence_alignment
= i915_gem_get_gtt_alignment(dev
,
3422 unfenced_alignment
=
3423 i915_gem_get_gtt_alignment(dev
,
3427 size
= flags
& PIN_MAPPABLE
? fence_size
: obj
->base
.size
;
3430 start
= flags
& PIN_OFFSET_BIAS
? flags
& PIN_OFFSET_MASK
: 0;
3432 if (flags
& PIN_MAPPABLE
)
3433 end
= min_t(u64
, end
, dev_priv
->gtt
.mappable_end
);
3434 if (flags
& PIN_ZONE_4G
)
3435 end
= min_t(u64
, end
, (1ULL << 32));
3438 alignment
= flags
& PIN_MAPPABLE
? fence_alignment
:
3440 if (flags
& PIN_MAPPABLE
&& alignment
& (fence_alignment
- 1)) {
3441 DRM_DEBUG("Invalid object (view type=%u) alignment requested %u\n",
3442 ggtt_view
? ggtt_view
->type
: 0,
3444 return ERR_PTR(-EINVAL
);
3447 /* If binding the object/GGTT view requires more space than the entire
3448 * aperture has, reject it early before evicting everything in a vain
3449 * attempt to find space.
3452 DRM_DEBUG("Attempting to bind an object (view type=%u) larger than the aperture: size=%llu > %s aperture=%llu\n",
3453 ggtt_view
? ggtt_view
->type
: 0,
3455 flags
& PIN_MAPPABLE
? "mappable" : "total",
3457 return ERR_PTR(-E2BIG
);
3460 ret
= i915_gem_object_get_pages(obj
);
3462 return ERR_PTR(ret
);
3464 i915_gem_object_pin_pages(obj
);
3466 vma
= ggtt_view
? i915_gem_obj_lookup_or_create_ggtt_vma(obj
, ggtt_view
) :
3467 i915_gem_obj_lookup_or_create_vma(obj
, vm
);
3472 if (flags
& PIN_OFFSET_FIXED
) {
3473 uint64_t offset
= flags
& PIN_OFFSET_MASK
;
3475 if (offset
& (alignment
- 1) || offset
+ size
> end
) {
3479 vma
->node
.start
= offset
;
3480 vma
->node
.size
= size
;
3481 vma
->node
.color
= obj
->cache_level
;
3482 ret
= drm_mm_reserve_node(&vm
->mm
, &vma
->node
);
3484 ret
= i915_gem_evict_for_vma(vma
);
3486 ret
= drm_mm_reserve_node(&vm
->mm
, &vma
->node
);
3491 if (flags
& PIN_HIGH
) {
3492 search_flag
= DRM_MM_SEARCH_BELOW
;
3493 alloc_flag
= DRM_MM_CREATE_TOP
;
3495 search_flag
= DRM_MM_SEARCH_DEFAULT
;
3496 alloc_flag
= DRM_MM_CREATE_DEFAULT
;
3500 ret
= drm_mm_insert_node_in_range_generic(&vm
->mm
, &vma
->node
,
3507 ret
= i915_gem_evict_something(dev
, vm
, size
, alignment
,
3517 if (WARN_ON(!i915_gem_valid_gtt_space(vma
, obj
->cache_level
))) {
3519 goto err_remove_node
;
3522 trace_i915_vma_bind(vma
, flags
);
3523 ret
= i915_vma_bind(vma
, obj
->cache_level
, flags
);
3525 goto err_remove_node
;
3527 list_move_tail(&obj
->global_list
, &dev_priv
->mm
.bound_list
);
3528 list_add_tail(&vma
->mm_list
, &vm
->inactive_list
);
3533 drm_mm_remove_node(&vma
->node
);
3535 i915_gem_vma_destroy(vma
);
3538 i915_gem_object_unpin_pages(obj
);
3543 i915_gem_clflush_object(struct drm_i915_gem_object
*obj
,
3546 /* If we don't have a page list set up, then we're not pinned
3547 * to GPU, and we can ignore the cache flush because it'll happen
3548 * again at bind time.
3550 if (obj
->pages
== NULL
)
3554 * Stolen memory is always coherent with the GPU as it is explicitly
3555 * marked as wc by the system, or the system is cache-coherent.
3557 if (obj
->stolen
|| obj
->phys_handle
)
3560 /* If the GPU is snooping the contents of the CPU cache,
3561 * we do not need to manually clear the CPU cache lines. However,
3562 * the caches are only snooped when the render cache is
3563 * flushed/invalidated. As we always have to emit invalidations
3564 * and flushes when moving into and out of the RENDER domain, correct
3565 * snooping behaviour occurs naturally as the result of our domain
3568 if (!force
&& cpu_cache_is_coherent(obj
->base
.dev
, obj
->cache_level
)) {
3569 obj
->cache_dirty
= true;
3573 trace_i915_gem_object_clflush(obj
);
3574 drm_clflush_sg(obj
->pages
);
3575 obj
->cache_dirty
= false;
3580 /** Flushes the GTT write domain for the object if it's dirty. */
3582 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
)
3584 uint32_t old_write_domain
;
3586 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_GTT
)
3589 /* No actual flushing is required for the GTT write domain. Writes
3590 * to it immediately go to main memory as far as we know, so there's
3591 * no chipset flush. It also doesn't land in render cache.
3593 * However, we do have to enforce the order so that all writes through
3594 * the GTT land before any writes to the device, such as updates to
3599 old_write_domain
= obj
->base
.write_domain
;
3600 obj
->base
.write_domain
= 0;
3602 intel_fb_obj_flush(obj
, false, ORIGIN_GTT
);
3604 trace_i915_gem_object_change_domain(obj
,
3605 obj
->base
.read_domains
,
3609 /** Flushes the CPU write domain for the object if it's dirty. */
3611 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
)
3613 uint32_t old_write_domain
;
3615 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
)
3618 if (i915_gem_clflush_object(obj
, obj
->pin_display
))
3619 i915_gem_chipset_flush(obj
->base
.dev
);
3621 old_write_domain
= obj
->base
.write_domain
;
3622 obj
->base
.write_domain
= 0;
3624 intel_fb_obj_flush(obj
, false, ORIGIN_CPU
);
3626 trace_i915_gem_object_change_domain(obj
,
3627 obj
->base
.read_domains
,
3632 * Moves a single object to the GTT read, and possibly write domain.
3634 * This function returns when the move is complete, including waiting on
3638 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
, bool write
)
3640 uint32_t old_write_domain
, old_read_domains
;
3641 struct i915_vma
*vma
;
3644 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_GTT
)
3647 ret
= i915_gem_object_wait_rendering(obj
, !write
);
3651 /* Flush and acquire obj->pages so that we are coherent through
3652 * direct access in memory with previous cached writes through
3653 * shmemfs and that our cache domain tracking remains valid.
3654 * For example, if the obj->filp was moved to swap without us
3655 * being notified and releasing the pages, we would mistakenly
3656 * continue to assume that the obj remained out of the CPU cached
3659 ret
= i915_gem_object_get_pages(obj
);
3663 i915_gem_object_flush_cpu_write_domain(obj
);
3665 /* Serialise direct access to this object with the barriers for
3666 * coherent writes from the GPU, by effectively invalidating the
3667 * GTT domain upon first access.
3669 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
) == 0)
3672 old_write_domain
= obj
->base
.write_domain
;
3673 old_read_domains
= obj
->base
.read_domains
;
3675 /* It should now be out of any other write domains, and we can update
3676 * the domain values for our changes.
3678 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
3679 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
3681 obj
->base
.read_domains
= I915_GEM_DOMAIN_GTT
;
3682 obj
->base
.write_domain
= I915_GEM_DOMAIN_GTT
;
3686 trace_i915_gem_object_change_domain(obj
,
3690 /* And bump the LRU for this access */
3691 vma
= i915_gem_obj_to_ggtt(obj
);
3692 if (vma
&& drm_mm_node_allocated(&vma
->node
) && !obj
->active
)
3693 list_move_tail(&vma
->mm_list
,
3694 &to_i915(obj
->base
.dev
)->gtt
.base
.inactive_list
);
3700 * Changes the cache-level of an object across all VMA.
3702 * After this function returns, the object will be in the new cache-level
3703 * across all GTT and the contents of the backing storage will be coherent,
3704 * with respect to the new cache-level. In order to keep the backing storage
3705 * coherent for all users, we only allow a single cache level to be set
3706 * globally on the object and prevent it from being changed whilst the
3707 * hardware is reading from the object. That is if the object is currently
3708 * on the scanout it will be set to uncached (or equivalent display
3709 * cache coherency) and all non-MOCS GPU access will also be uncached so
3710 * that all direct access to the scanout remains coherent.
3712 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
3713 enum i915_cache_level cache_level
)
3715 struct drm_device
*dev
= obj
->base
.dev
;
3716 struct i915_vma
*vma
, *next
;
3720 if (obj
->cache_level
== cache_level
)
3723 /* Inspect the list of currently bound VMA and unbind any that would
3724 * be invalid given the new cache-level. This is principally to
3725 * catch the issue of the CS prefetch crossing page boundaries and
3726 * reading an invalid PTE on older architectures.
3728 list_for_each_entry_safe(vma
, next
, &obj
->vma_list
, vma_link
) {
3729 if (!drm_mm_node_allocated(&vma
->node
))
3732 if (vma
->pin_count
) {
3733 DRM_DEBUG("can not change the cache level of pinned objects\n");
3737 if (!i915_gem_valid_gtt_space(vma
, cache_level
)) {
3738 ret
= i915_vma_unbind(vma
);
3745 /* We can reuse the existing drm_mm nodes but need to change the
3746 * cache-level on the PTE. We could simply unbind them all and
3747 * rebind with the correct cache-level on next use. However since
3748 * we already have a valid slot, dma mapping, pages etc, we may as
3749 * rewrite the PTE in the belief that doing so tramples upon less
3750 * state and so involves less work.
3753 /* Before we change the PTE, the GPU must not be accessing it.
3754 * If we wait upon the object, we know that all the bound
3755 * VMA are no longer active.
3757 ret
= i915_gem_object_wait_rendering(obj
, false);
3761 if (!HAS_LLC(dev
) && cache_level
!= I915_CACHE_NONE
) {
3762 /* Access to snoopable pages through the GTT is
3763 * incoherent and on some machines causes a hard
3764 * lockup. Relinquish the CPU mmaping to force
3765 * userspace to refault in the pages and we can
3766 * then double check if the GTT mapping is still
3767 * valid for that pointer access.
3769 i915_gem_release_mmap(obj
);
3771 /* As we no longer need a fence for GTT access,
3772 * we can relinquish it now (and so prevent having
3773 * to steal a fence from someone else on the next
3774 * fence request). Note GPU activity would have
3775 * dropped the fence as all snoopable access is
3776 * supposed to be linear.
3778 ret
= i915_gem_object_put_fence(obj
);
3782 /* We either have incoherent backing store and
3783 * so no GTT access or the architecture is fully
3784 * coherent. In such cases, existing GTT mmaps
3785 * ignore the cache bit in the PTE and we can
3786 * rewrite it without confusing the GPU or having
3787 * to force userspace to fault back in its mmaps.
3791 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
) {
3792 if (!drm_mm_node_allocated(&vma
->node
))
3795 ret
= i915_vma_bind(vma
, cache_level
, PIN_UPDATE
);
3801 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
3802 vma
->node
.color
= cache_level
;
3803 obj
->cache_level
= cache_level
;
3806 /* Flush the dirty CPU caches to the backing storage so that the
3807 * object is now coherent at its new cache level (with respect
3808 * to the access domain).
3810 if (obj
->cache_dirty
&&
3811 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
&&
3812 cpu_write_needs_clflush(obj
)) {
3813 if (i915_gem_clflush_object(obj
, true))
3814 i915_gem_chipset_flush(obj
->base
.dev
);
3820 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
3821 struct drm_file
*file
)
3823 struct drm_i915_gem_caching
*args
= data
;
3824 struct drm_i915_gem_object
*obj
;
3826 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3827 if (&obj
->base
== NULL
)
3830 switch (obj
->cache_level
) {
3831 case I915_CACHE_LLC
:
3832 case I915_CACHE_L3_LLC
:
3833 args
->caching
= I915_CACHING_CACHED
;
3837 args
->caching
= I915_CACHING_DISPLAY
;
3841 args
->caching
= I915_CACHING_NONE
;
3845 drm_gem_object_unreference_unlocked(&obj
->base
);
3849 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
3850 struct drm_file
*file
)
3852 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3853 struct drm_i915_gem_caching
*args
= data
;
3854 struct drm_i915_gem_object
*obj
;
3855 enum i915_cache_level level
;
3858 switch (args
->caching
) {
3859 case I915_CACHING_NONE
:
3860 level
= I915_CACHE_NONE
;
3862 case I915_CACHING_CACHED
:
3864 * Due to a HW issue on BXT A stepping, GPU stores via a
3865 * snooped mapping may leave stale data in a corresponding CPU
3866 * cacheline, whereas normally such cachelines would get
3869 if (IS_BXT_REVID(dev
, 0, BXT_REVID_A1
))
3872 level
= I915_CACHE_LLC
;
3874 case I915_CACHING_DISPLAY
:
3875 level
= HAS_WT(dev
) ? I915_CACHE_WT
: I915_CACHE_NONE
;
3881 intel_runtime_pm_get(dev_priv
);
3883 ret
= i915_mutex_lock_interruptible(dev
);
3887 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3888 if (&obj
->base
== NULL
) {
3893 ret
= i915_gem_object_set_cache_level(obj
, level
);
3895 drm_gem_object_unreference(&obj
->base
);
3897 mutex_unlock(&dev
->struct_mutex
);
3899 intel_runtime_pm_put(dev_priv
);
3905 * Prepare buffer for display plane (scanout, cursors, etc).
3906 * Can be called from an uninterruptible phase (modesetting) and allows
3907 * any flushes to be pipelined (for pageflips).
3910 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
3912 const struct i915_ggtt_view
*view
)
3914 u32 old_read_domains
, old_write_domain
;
3917 /* Mark the pin_display early so that we account for the
3918 * display coherency whilst setting up the cache domains.
3922 /* The display engine is not coherent with the LLC cache on gen6. As
3923 * a result, we make sure that the pinning that is about to occur is
3924 * done with uncached PTEs. This is lowest common denominator for all
3927 * However for gen6+, we could do better by using the GFDT bit instead
3928 * of uncaching, which would allow us to flush all the LLC-cached data
3929 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3931 ret
= i915_gem_object_set_cache_level(obj
,
3932 HAS_WT(obj
->base
.dev
) ? I915_CACHE_WT
: I915_CACHE_NONE
);
3934 goto err_unpin_display
;
3936 /* As the user may map the buffer once pinned in the display plane
3937 * (e.g. libkms for the bootup splash), we have to ensure that we
3938 * always use map_and_fenceable for all scanout buffers.
3940 ret
= i915_gem_object_ggtt_pin(obj
, view
, alignment
,
3941 view
->type
== I915_GGTT_VIEW_NORMAL
?
3944 goto err_unpin_display
;
3946 i915_gem_object_flush_cpu_write_domain(obj
);
3948 old_write_domain
= obj
->base
.write_domain
;
3949 old_read_domains
= obj
->base
.read_domains
;
3951 /* It should now be out of any other write domains, and we can update
3952 * the domain values for our changes.
3954 obj
->base
.write_domain
= 0;
3955 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
3957 trace_i915_gem_object_change_domain(obj
,
3969 i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object
*obj
,
3970 const struct i915_ggtt_view
*view
)
3972 if (WARN_ON(obj
->pin_display
== 0))
3975 i915_gem_object_ggtt_unpin_view(obj
, view
);
3981 * Moves a single object to the CPU read, and possibly write domain.
3983 * This function returns when the move is complete, including waiting on
3987 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
)
3989 uint32_t old_write_domain
, old_read_domains
;
3992 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_CPU
)
3995 ret
= i915_gem_object_wait_rendering(obj
, !write
);
3999 i915_gem_object_flush_gtt_write_domain(obj
);
4001 old_write_domain
= obj
->base
.write_domain
;
4002 old_read_domains
= obj
->base
.read_domains
;
4004 /* Flush the CPU cache if it's still invalid. */
4005 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) == 0) {
4006 i915_gem_clflush_object(obj
, false);
4008 obj
->base
.read_domains
|= I915_GEM_DOMAIN_CPU
;
4011 /* It should now be out of any other write domains, and we can update
4012 * the domain values for our changes.
4014 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
4016 /* If we're writing through the CPU, then the GPU read domains will
4017 * need to be invalidated at next use.
4020 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
4021 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
4024 trace_i915_gem_object_change_domain(obj
,
4031 /* Throttle our rendering by waiting until the ring has completed our requests
4032 * emitted over 20 msec ago.
4034 * Note that if we were to use the current jiffies each time around the loop,
4035 * we wouldn't escape the function with any frames outstanding if the time to
4036 * render a frame was over 20ms.
4038 * This should get us reasonable parallelism between CPU and GPU but also
4039 * relatively low latency when blocking on a particular request to finish.
4042 i915_gem_ring_throttle(struct drm_device
*dev
, struct drm_file
*file
)
4044 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4045 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
4046 unsigned long recent_enough
= jiffies
- DRM_I915_THROTTLE_JIFFIES
;
4047 struct drm_i915_gem_request
*request
, *target
= NULL
;
4048 unsigned reset_counter
;
4051 ret
= i915_gem_wait_for_error(&dev_priv
->gpu_error
);
4055 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, false);
4059 spin_lock(&file_priv
->mm
.lock
);
4060 list_for_each_entry(request
, &file_priv
->mm
.request_list
, client_list
) {
4061 if (time_after_eq(request
->emitted_jiffies
, recent_enough
))
4065 * Note that the request might not have been submitted yet.
4066 * In which case emitted_jiffies will be zero.
4068 if (!request
->emitted_jiffies
)
4073 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
4075 i915_gem_request_reference(target
);
4076 spin_unlock(&file_priv
->mm
.lock
);
4081 ret
= __i915_wait_request(target
, reset_counter
, true, NULL
, NULL
);
4083 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, 0);
4085 i915_gem_request_unreference__unlocked(target
);
4091 i915_vma_misplaced(struct i915_vma
*vma
, uint32_t alignment
, uint64_t flags
)
4093 struct drm_i915_gem_object
*obj
= vma
->obj
;
4096 vma
->node
.start
& (alignment
- 1))
4099 if (flags
& PIN_MAPPABLE
&& !obj
->map_and_fenceable
)
4102 if (flags
& PIN_OFFSET_BIAS
&&
4103 vma
->node
.start
< (flags
& PIN_OFFSET_MASK
))
4106 if (flags
& PIN_OFFSET_FIXED
&&
4107 vma
->node
.start
!= (flags
& PIN_OFFSET_MASK
))
4114 i915_gem_object_do_pin(struct drm_i915_gem_object
*obj
,
4115 struct i915_address_space
*vm
,
4116 const struct i915_ggtt_view
*ggtt_view
,
4120 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
4121 struct i915_vma
*vma
;
4125 if (WARN_ON(vm
== &dev_priv
->mm
.aliasing_ppgtt
->base
))
4128 if (WARN_ON(flags
& (PIN_GLOBAL
| PIN_MAPPABLE
) && !i915_is_ggtt(vm
)))
4131 if (WARN_ON((flags
& (PIN_MAPPABLE
| PIN_GLOBAL
)) == PIN_MAPPABLE
))
4134 if (WARN_ON(i915_is_ggtt(vm
) != !!ggtt_view
))
4137 vma
= ggtt_view
? i915_gem_obj_to_ggtt_view(obj
, ggtt_view
) :
4138 i915_gem_obj_to_vma(obj
, vm
);
4141 return PTR_ERR(vma
);
4144 if (WARN_ON(vma
->pin_count
== DRM_I915_GEM_OBJECT_MAX_PIN_COUNT
))
4147 if (i915_vma_misplaced(vma
, alignment
, flags
)) {
4148 WARN(vma
->pin_count
,
4149 "bo is already pinned in %s with incorrect alignment:"
4150 " offset=%08x %08x, req.alignment=%x, req.map_and_fenceable=%d,"
4151 " obj->map_and_fenceable=%d\n",
4152 ggtt_view
? "ggtt" : "ppgtt",
4153 upper_32_bits(vma
->node
.start
),
4154 lower_32_bits(vma
->node
.start
),
4156 !!(flags
& PIN_MAPPABLE
),
4157 obj
->map_and_fenceable
);
4158 ret
= i915_vma_unbind(vma
);
4166 bound
= vma
? vma
->bound
: 0;
4167 if (vma
== NULL
|| !drm_mm_node_allocated(&vma
->node
)) {
4168 vma
= i915_gem_object_bind_to_vm(obj
, vm
, ggtt_view
, alignment
,
4171 return PTR_ERR(vma
);
4173 ret
= i915_vma_bind(vma
, obj
->cache_level
, flags
);
4178 if (ggtt_view
&& ggtt_view
->type
== I915_GGTT_VIEW_NORMAL
&&
4179 (bound
^ vma
->bound
) & GLOBAL_BIND
) {
4180 bool mappable
, fenceable
;
4181 u32 fence_size
, fence_alignment
;
4183 fence_size
= i915_gem_get_gtt_size(obj
->base
.dev
,
4186 fence_alignment
= i915_gem_get_gtt_alignment(obj
->base
.dev
,
4191 fenceable
= (vma
->node
.size
== fence_size
&&
4192 (vma
->node
.start
& (fence_alignment
- 1)) == 0);
4194 mappable
= (vma
->node
.start
+ fence_size
<=
4195 dev_priv
->gtt
.mappable_end
);
4197 obj
->map_and_fenceable
= mappable
&& fenceable
;
4199 WARN_ON(flags
& PIN_MAPPABLE
&& !obj
->map_and_fenceable
);
4207 i915_gem_object_pin(struct drm_i915_gem_object
*obj
,
4208 struct i915_address_space
*vm
,
4212 return i915_gem_object_do_pin(obj
, vm
,
4213 i915_is_ggtt(vm
) ? &i915_ggtt_view_normal
: NULL
,
4218 i915_gem_object_ggtt_pin(struct drm_i915_gem_object
*obj
,
4219 const struct i915_ggtt_view
*view
,
4223 if (WARN_ONCE(!view
, "no view specified"))
4226 return i915_gem_object_do_pin(obj
, i915_obj_to_ggtt(obj
), view
,
4227 alignment
, flags
| PIN_GLOBAL
);
4231 i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object
*obj
,
4232 const struct i915_ggtt_view
*view
)
4234 struct i915_vma
*vma
= i915_gem_obj_to_ggtt_view(obj
, view
);
4237 WARN_ON(vma
->pin_count
== 0);
4238 WARN_ON(!i915_gem_obj_ggtt_bound_view(obj
, view
));
4244 i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
4245 struct drm_file
*file
)
4247 struct drm_i915_gem_busy
*args
= data
;
4248 struct drm_i915_gem_object
*obj
;
4251 ret
= i915_mutex_lock_interruptible(dev
);
4255 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
4256 if (&obj
->base
== NULL
) {
4261 /* Count all active objects as busy, even if they are currently not used
4262 * by the gpu. Users of this interface expect objects to eventually
4263 * become non-busy without any further actions, therefore emit any
4264 * necessary flushes here.
4266 ret
= i915_gem_object_flush_active(obj
);
4270 BUILD_BUG_ON(I915_NUM_RINGS
> 16);
4271 args
->busy
= obj
->active
<< 16;
4272 if (obj
->last_write_req
)
4273 args
->busy
|= obj
->last_write_req
->ring
->id
;
4276 drm_gem_object_unreference(&obj
->base
);
4278 mutex_unlock(&dev
->struct_mutex
);
4283 i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
4284 struct drm_file
*file_priv
)
4286 return i915_gem_ring_throttle(dev
, file_priv
);
4290 i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
4291 struct drm_file
*file_priv
)
4293 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4294 struct drm_i915_gem_madvise
*args
= data
;
4295 struct drm_i915_gem_object
*obj
;
4298 switch (args
->madv
) {
4299 case I915_MADV_DONTNEED
:
4300 case I915_MADV_WILLNEED
:
4306 ret
= i915_mutex_lock_interruptible(dev
);
4310 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file_priv
, args
->handle
));
4311 if (&obj
->base
== NULL
) {
4316 if (i915_gem_obj_is_pinned(obj
)) {
4322 obj
->tiling_mode
!= I915_TILING_NONE
&&
4323 dev_priv
->quirks
& QUIRK_PIN_SWIZZLED_PAGES
) {
4324 if (obj
->madv
== I915_MADV_WILLNEED
)
4325 i915_gem_object_unpin_pages(obj
);
4326 if (args
->madv
== I915_MADV_WILLNEED
)
4327 i915_gem_object_pin_pages(obj
);
4330 if (obj
->madv
!= __I915_MADV_PURGED
)
4331 obj
->madv
= args
->madv
;
4333 /* if the object is no longer attached, discard its backing storage */
4334 if (obj
->madv
== I915_MADV_DONTNEED
&& obj
->pages
== NULL
)
4335 i915_gem_object_truncate(obj
);
4337 args
->retained
= obj
->madv
!= __I915_MADV_PURGED
;
4340 drm_gem_object_unreference(&obj
->base
);
4342 mutex_unlock(&dev
->struct_mutex
);
4346 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
4347 const struct drm_i915_gem_object_ops
*ops
)
4351 INIT_LIST_HEAD(&obj
->global_list
);
4352 for (i
= 0; i
< I915_NUM_RINGS
; i
++)
4353 INIT_LIST_HEAD(&obj
->ring_list
[i
]);
4354 INIT_LIST_HEAD(&obj
->obj_exec_link
);
4355 INIT_LIST_HEAD(&obj
->vma_list
);
4356 INIT_LIST_HEAD(&obj
->batch_pool_link
);
4360 obj
->fence_reg
= I915_FENCE_REG_NONE
;
4361 obj
->madv
= I915_MADV_WILLNEED
;
4363 i915_gem_info_add_obj(obj
->base
.dev
->dev_private
, obj
->base
.size
);
4366 static const struct drm_i915_gem_object_ops i915_gem_object_ops
= {
4367 .get_pages
= i915_gem_object_get_pages_gtt
,
4368 .put_pages
= i915_gem_object_put_pages_gtt
,
4371 struct drm_i915_gem_object
*i915_gem_alloc_object(struct drm_device
*dev
,
4374 struct drm_i915_gem_object
*obj
;
4375 struct address_space
*mapping
;
4378 obj
= i915_gem_object_alloc(dev
);
4382 if (drm_gem_object_init(dev
, &obj
->base
, size
) != 0) {
4383 i915_gem_object_free(obj
);
4387 mask
= GFP_HIGHUSER
| __GFP_RECLAIMABLE
;
4388 if (IS_CRESTLINE(dev
) || IS_BROADWATER(dev
)) {
4389 /* 965gm cannot relocate objects above 4GiB. */
4390 mask
&= ~__GFP_HIGHMEM
;
4391 mask
|= __GFP_DMA32
;
4394 mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
4395 mapping_set_gfp_mask(mapping
, mask
);
4397 i915_gem_object_init(obj
, &i915_gem_object_ops
);
4399 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
4400 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
4403 /* On some devices, we can have the GPU use the LLC (the CPU
4404 * cache) for about a 10% performance improvement
4405 * compared to uncached. Graphics requests other than
4406 * display scanout are coherent with the CPU in
4407 * accessing this cache. This means in this mode we
4408 * don't need to clflush on the CPU side, and on the
4409 * GPU side we only need to flush internal caches to
4410 * get data visible to the CPU.
4412 * However, we maintain the display planes as UC, and so
4413 * need to rebind when first used as such.
4415 obj
->cache_level
= I915_CACHE_LLC
;
4417 obj
->cache_level
= I915_CACHE_NONE
;
4419 trace_i915_gem_object_create(obj
);
4424 static bool discard_backing_storage(struct drm_i915_gem_object
*obj
)
4426 /* If we are the last user of the backing storage (be it shmemfs
4427 * pages or stolen etc), we know that the pages are going to be
4428 * immediately released. In this case, we can then skip copying
4429 * back the contents from the GPU.
4432 if (obj
->madv
!= I915_MADV_WILLNEED
)
4435 if (obj
->base
.filp
== NULL
)
4438 /* At first glance, this looks racy, but then again so would be
4439 * userspace racing mmap against close. However, the first external
4440 * reference to the filp can only be obtained through the
4441 * i915_gem_mmap_ioctl() which safeguards us against the user
4442 * acquiring such a reference whilst we are in the middle of
4443 * freeing the object.
4445 return atomic_long_read(&obj
->base
.filp
->f_count
) == 1;
4448 void i915_gem_free_object(struct drm_gem_object
*gem_obj
)
4450 struct drm_i915_gem_object
*obj
= to_intel_bo(gem_obj
);
4451 struct drm_device
*dev
= obj
->base
.dev
;
4452 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4453 struct i915_vma
*vma
, *next
;
4455 intel_runtime_pm_get(dev_priv
);
4457 trace_i915_gem_object_destroy(obj
);
4459 list_for_each_entry_safe(vma
, next
, &obj
->vma_list
, vma_link
) {
4463 ret
= i915_vma_unbind(vma
);
4464 if (WARN_ON(ret
== -ERESTARTSYS
)) {
4465 bool was_interruptible
;
4467 was_interruptible
= dev_priv
->mm
.interruptible
;
4468 dev_priv
->mm
.interruptible
= false;
4470 WARN_ON(i915_vma_unbind(vma
));
4472 dev_priv
->mm
.interruptible
= was_interruptible
;
4476 /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
4477 * before progressing. */
4479 i915_gem_object_unpin_pages(obj
);
4481 WARN_ON(obj
->frontbuffer_bits
);
4483 if (obj
->pages
&& obj
->madv
== I915_MADV_WILLNEED
&&
4484 dev_priv
->quirks
& QUIRK_PIN_SWIZZLED_PAGES
&&
4485 obj
->tiling_mode
!= I915_TILING_NONE
)
4486 i915_gem_object_unpin_pages(obj
);
4488 if (WARN_ON(obj
->pages_pin_count
))
4489 obj
->pages_pin_count
= 0;
4490 if (discard_backing_storage(obj
))
4491 obj
->madv
= I915_MADV_DONTNEED
;
4492 i915_gem_object_put_pages(obj
);
4493 i915_gem_object_free_mmap_offset(obj
);
4497 if (obj
->base
.import_attach
)
4498 drm_prime_gem_destroy(&obj
->base
, NULL
);
4500 if (obj
->ops
->release
)
4501 obj
->ops
->release(obj
);
4503 drm_gem_object_release(&obj
->base
);
4504 i915_gem_info_remove_obj(dev_priv
, obj
->base
.size
);
4507 i915_gem_object_free(obj
);
4509 intel_runtime_pm_put(dev_priv
);
4512 struct i915_vma
*i915_gem_obj_to_vma(struct drm_i915_gem_object
*obj
,
4513 struct i915_address_space
*vm
)
4515 struct i915_vma
*vma
;
4516 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
) {
4517 if (vma
->ggtt_view
.type
== I915_GGTT_VIEW_NORMAL
&&
4524 struct i915_vma
*i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object
*obj
,
4525 const struct i915_ggtt_view
*view
)
4527 struct i915_address_space
*ggtt
= i915_obj_to_ggtt(obj
);
4528 struct i915_vma
*vma
;
4530 if (WARN_ONCE(!view
, "no view specified"))
4531 return ERR_PTR(-EINVAL
);
4533 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
4534 if (vma
->vm
== ggtt
&&
4535 i915_ggtt_view_equal(&vma
->ggtt_view
, view
))
4540 void i915_gem_vma_destroy(struct i915_vma
*vma
)
4542 struct i915_address_space
*vm
= NULL
;
4543 WARN_ON(vma
->node
.allocated
);
4545 /* Keep the vma as a placeholder in the execbuffer reservation lists */
4546 if (!list_empty(&vma
->exec_list
))
4551 if (!i915_is_ggtt(vm
))
4552 i915_ppgtt_put(i915_vm_to_ppgtt(vm
));
4554 list_del(&vma
->vma_link
);
4556 kmem_cache_free(to_i915(vma
->obj
->base
.dev
)->vmas
, vma
);
4560 i915_gem_stop_ringbuffers(struct drm_device
*dev
)
4562 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4563 struct intel_engine_cs
*ring
;
4566 for_each_ring(ring
, dev_priv
, i
)
4567 dev_priv
->gt
.stop_ring(ring
);
4571 i915_gem_suspend(struct drm_device
*dev
)
4573 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4576 mutex_lock(&dev
->struct_mutex
);
4577 ret
= i915_gpu_idle(dev
);
4581 i915_gem_retire_requests(dev
);
4583 i915_gem_stop_ringbuffers(dev
);
4584 mutex_unlock(&dev
->struct_mutex
);
4586 cancel_delayed_work_sync(&dev_priv
->gpu_error
.hangcheck_work
);
4587 cancel_delayed_work_sync(&dev_priv
->mm
.retire_work
);
4588 flush_delayed_work(&dev_priv
->mm
.idle_work
);
4590 /* Assert that we sucessfully flushed all the work and
4591 * reset the GPU back to its idle, low power state.
4593 WARN_ON(dev_priv
->mm
.busy
);
4598 mutex_unlock(&dev
->struct_mutex
);
4602 int i915_gem_l3_remap(struct drm_i915_gem_request
*req
, int slice
)
4604 struct intel_engine_cs
*ring
= req
->ring
;
4605 struct drm_device
*dev
= ring
->dev
;
4606 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4607 u32
*remap_info
= dev_priv
->l3_parity
.remap_info
[slice
];
4610 if (!HAS_L3_DPF(dev
) || !remap_info
)
4613 ret
= intel_ring_begin(req
, GEN7_L3LOG_SIZE
/ 4 * 3);
4618 * Note: We do not worry about the concurrent register cacheline hang
4619 * here because no other code should access these registers other than
4620 * at initialization time.
4622 for (i
= 0; i
< GEN7_L3LOG_SIZE
/ 4; i
++) {
4623 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
4624 intel_ring_emit_reg(ring
, GEN7_L3LOG(slice
, i
));
4625 intel_ring_emit(ring
, remap_info
[i
]);
4628 intel_ring_advance(ring
);
4633 void i915_gem_init_swizzling(struct drm_device
*dev
)
4635 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4637 if (INTEL_INFO(dev
)->gen
< 5 ||
4638 dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_NONE
)
4641 I915_WRITE(DISP_ARB_CTL
, I915_READ(DISP_ARB_CTL
) |
4642 DISP_TILE_SURFACE_SWIZZLING
);
4647 I915_WRITE(TILECTL
, I915_READ(TILECTL
) | TILECTL_SWZCTL
);
4649 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB
));
4650 else if (IS_GEN7(dev
))
4651 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB
));
4652 else if (IS_GEN8(dev
))
4653 I915_WRITE(GAMTARBMODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW
));
4658 static void init_unused_ring(struct drm_device
*dev
, u32 base
)
4660 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4662 I915_WRITE(RING_CTL(base
), 0);
4663 I915_WRITE(RING_HEAD(base
), 0);
4664 I915_WRITE(RING_TAIL(base
), 0);
4665 I915_WRITE(RING_START(base
), 0);
4668 static void init_unused_rings(struct drm_device
*dev
)
4671 init_unused_ring(dev
, PRB1_BASE
);
4672 init_unused_ring(dev
, SRB0_BASE
);
4673 init_unused_ring(dev
, SRB1_BASE
);
4674 init_unused_ring(dev
, SRB2_BASE
);
4675 init_unused_ring(dev
, SRB3_BASE
);
4676 } else if (IS_GEN2(dev
)) {
4677 init_unused_ring(dev
, SRB0_BASE
);
4678 init_unused_ring(dev
, SRB1_BASE
);
4679 } else if (IS_GEN3(dev
)) {
4680 init_unused_ring(dev
, PRB1_BASE
);
4681 init_unused_ring(dev
, PRB2_BASE
);
4685 int i915_gem_init_rings(struct drm_device
*dev
)
4687 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4690 ret
= intel_init_render_ring_buffer(dev
);
4695 ret
= intel_init_bsd_ring_buffer(dev
);
4697 goto cleanup_render_ring
;
4701 ret
= intel_init_blt_ring_buffer(dev
);
4703 goto cleanup_bsd_ring
;
4706 if (HAS_VEBOX(dev
)) {
4707 ret
= intel_init_vebox_ring_buffer(dev
);
4709 goto cleanup_blt_ring
;
4712 if (HAS_BSD2(dev
)) {
4713 ret
= intel_init_bsd2_ring_buffer(dev
);
4715 goto cleanup_vebox_ring
;
4721 intel_cleanup_ring_buffer(&dev_priv
->ring
[VECS
]);
4723 intel_cleanup_ring_buffer(&dev_priv
->ring
[BCS
]);
4725 intel_cleanup_ring_buffer(&dev_priv
->ring
[VCS
]);
4726 cleanup_render_ring
:
4727 intel_cleanup_ring_buffer(&dev_priv
->ring
[RCS
]);
4733 i915_gem_init_hw(struct drm_device
*dev
)
4735 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4736 struct intel_engine_cs
*ring
;
4739 if (INTEL_INFO(dev
)->gen
< 6 && !intel_enable_gtt())
4742 /* Double layer security blanket, see i915_gem_init() */
4743 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
4745 if (dev_priv
->ellc_size
)
4746 I915_WRITE(HSW_IDICR
, I915_READ(HSW_IDICR
) | IDIHASHMSK(0xf));
4748 if (IS_HASWELL(dev
))
4749 I915_WRITE(MI_PREDICATE_RESULT_2
, IS_HSW_GT3(dev
) ?
4750 LOWER_SLICE_ENABLED
: LOWER_SLICE_DISABLED
);
4752 if (HAS_PCH_NOP(dev
)) {
4753 if (IS_IVYBRIDGE(dev
)) {
4754 u32 temp
= I915_READ(GEN7_MSG_CTL
);
4755 temp
&= ~(WAIT_FOR_PCH_FLR_ACK
| WAIT_FOR_PCH_RESET_ACK
);
4756 I915_WRITE(GEN7_MSG_CTL
, temp
);
4757 } else if (INTEL_INFO(dev
)->gen
>= 7) {
4758 u32 temp
= I915_READ(HSW_NDE_RSTWRN_OPT
);
4759 temp
&= ~RESET_PCH_HANDSHAKE_ENABLE
;
4760 I915_WRITE(HSW_NDE_RSTWRN_OPT
, temp
);
4764 i915_gem_init_swizzling(dev
);
4767 * At least 830 can leave some of the unused rings
4768 * "active" (ie. head != tail) after resume which
4769 * will prevent c3 entry. Makes sure all unused rings
4772 init_unused_rings(dev
);
4774 BUG_ON(!dev_priv
->ring
[RCS
].default_context
);
4776 ret
= i915_ppgtt_init_hw(dev
);
4778 DRM_ERROR("PPGTT enable HW failed %d\n", ret
);
4782 /* Need to do basic initialisation of all rings first: */
4783 for_each_ring(ring
, dev_priv
, i
) {
4784 ret
= ring
->init_hw(ring
);
4789 /* We can't enable contexts until all firmware is loaded */
4790 if (HAS_GUC_UCODE(dev
)) {
4791 ret
= intel_guc_ucode_load(dev
);
4793 DRM_ERROR("Failed to initialize GuC, error %d\n", ret
);
4800 * Increment the next seqno by 0x100 so we have a visible break
4801 * on re-initialisation
4803 ret
= i915_gem_set_seqno(dev
, dev_priv
->next_seqno
+0x100);
4807 /* Now it is safe to go back round and do everything else: */
4808 for_each_ring(ring
, dev_priv
, i
) {
4809 struct drm_i915_gem_request
*req
;
4811 WARN_ON(!ring
->default_context
);
4813 ret
= i915_gem_request_alloc(ring
, ring
->default_context
, &req
);
4815 i915_gem_cleanup_ringbuffer(dev
);
4819 if (ring
->id
== RCS
) {
4820 for (j
= 0; j
< NUM_L3_SLICES(dev
); j
++)
4821 i915_gem_l3_remap(req
, j
);
4824 ret
= i915_ppgtt_init_ring(req
);
4825 if (ret
&& ret
!= -EIO
) {
4826 DRM_ERROR("PPGTT enable ring #%d failed %d\n", i
, ret
);
4827 i915_gem_request_cancel(req
);
4828 i915_gem_cleanup_ringbuffer(dev
);
4832 ret
= i915_gem_context_enable(req
);
4833 if (ret
&& ret
!= -EIO
) {
4834 DRM_ERROR("Context enable ring #%d failed %d\n", i
, ret
);
4835 i915_gem_request_cancel(req
);
4836 i915_gem_cleanup_ringbuffer(dev
);
4840 i915_add_request_no_flush(req
);
4844 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
4848 int i915_gem_init(struct drm_device
*dev
)
4850 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4853 i915
.enable_execlists
= intel_sanitize_enable_execlists(dev
,
4854 i915
.enable_execlists
);
4856 mutex_lock(&dev
->struct_mutex
);
4858 if (!i915
.enable_execlists
) {
4859 dev_priv
->gt
.execbuf_submit
= i915_gem_ringbuffer_submission
;
4860 dev_priv
->gt
.init_rings
= i915_gem_init_rings
;
4861 dev_priv
->gt
.cleanup_ring
= intel_cleanup_ring_buffer
;
4862 dev_priv
->gt
.stop_ring
= intel_stop_ring_buffer
;
4864 dev_priv
->gt
.execbuf_submit
= intel_execlists_submission
;
4865 dev_priv
->gt
.init_rings
= intel_logical_rings_init
;
4866 dev_priv
->gt
.cleanup_ring
= intel_logical_ring_cleanup
;
4867 dev_priv
->gt
.stop_ring
= intel_logical_ring_stop
;
4870 /* This is just a security blanket to placate dragons.
4871 * On some systems, we very sporadically observe that the first TLBs
4872 * used by the CS may be stale, despite us poking the TLB reset. If
4873 * we hold the forcewake during initialisation these problems
4874 * just magically go away.
4876 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
4878 ret
= i915_gem_init_userptr(dev
);
4882 i915_gem_init_global_gtt(dev
);
4884 ret
= i915_gem_context_init(dev
);
4888 ret
= dev_priv
->gt
.init_rings(dev
);
4892 ret
= i915_gem_init_hw(dev
);
4894 /* Allow ring initialisation to fail by marking the GPU as
4895 * wedged. But we only want to do this where the GPU is angry,
4896 * for all other failure, such as an allocation failure, bail.
4898 DRM_ERROR("Failed to initialize GPU, declaring it wedged\n");
4899 atomic_or(I915_WEDGED
, &dev_priv
->gpu_error
.reset_counter
);
4904 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
4905 mutex_unlock(&dev
->struct_mutex
);
4911 i915_gem_cleanup_ringbuffer(struct drm_device
*dev
)
4913 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4914 struct intel_engine_cs
*ring
;
4917 for_each_ring(ring
, dev_priv
, i
)
4918 dev_priv
->gt
.cleanup_ring(ring
);
4920 if (i915
.enable_execlists
)
4922 * Neither the BIOS, ourselves or any other kernel
4923 * expects the system to be in execlists mode on startup,
4924 * so we need to reset the GPU back to legacy mode.
4926 intel_gpu_reset(dev
);
4930 init_ring_lists(struct intel_engine_cs
*ring
)
4932 INIT_LIST_HEAD(&ring
->active_list
);
4933 INIT_LIST_HEAD(&ring
->request_list
);
4937 i915_gem_load(struct drm_device
*dev
)
4939 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4943 kmem_cache_create("i915_gem_object",
4944 sizeof(struct drm_i915_gem_object
), 0,
4948 kmem_cache_create("i915_gem_vma",
4949 sizeof(struct i915_vma
), 0,
4952 dev_priv
->requests
=
4953 kmem_cache_create("i915_gem_request",
4954 sizeof(struct drm_i915_gem_request
), 0,
4958 INIT_LIST_HEAD(&dev_priv
->vm_list
);
4959 INIT_LIST_HEAD(&dev_priv
->context_list
);
4960 INIT_LIST_HEAD(&dev_priv
->mm
.unbound_list
);
4961 INIT_LIST_HEAD(&dev_priv
->mm
.bound_list
);
4962 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
4963 for (i
= 0; i
< I915_NUM_RINGS
; i
++)
4964 init_ring_lists(&dev_priv
->ring
[i
]);
4965 for (i
= 0; i
< I915_MAX_NUM_FENCES
; i
++)
4966 INIT_LIST_HEAD(&dev_priv
->fence_regs
[i
].lru_list
);
4967 INIT_DELAYED_WORK(&dev_priv
->mm
.retire_work
,
4968 i915_gem_retire_work_handler
);
4969 INIT_DELAYED_WORK(&dev_priv
->mm
.idle_work
,
4970 i915_gem_idle_work_handler
);
4971 init_waitqueue_head(&dev_priv
->gpu_error
.reset_queue
);
4973 dev_priv
->relative_constants_mode
= I915_EXEC_CONSTANTS_REL_GENERAL
;
4975 if (INTEL_INFO(dev
)->gen
>= 7 && !IS_VALLEYVIEW(dev
) && !IS_CHERRYVIEW(dev
))
4976 dev_priv
->num_fence_regs
= 32;
4977 else if (INTEL_INFO(dev
)->gen
>= 4 || IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
4978 dev_priv
->num_fence_regs
= 16;
4980 dev_priv
->num_fence_regs
= 8;
4982 if (intel_vgpu_active(dev
))
4983 dev_priv
->num_fence_regs
=
4984 I915_READ(vgtif_reg(avail_rs
.fence_num
));
4987 * Set initial sequence number for requests.
4988 * Using this number allows the wraparound to happen early,
4989 * catching any obvious problems.
4991 dev_priv
->next_seqno
= ((u32
)~0 - 0x1100);
4992 dev_priv
->last_seqno
= ((u32
)~0 - 0x1101);
4994 /* Initialize fence registers to zero */
4995 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
4996 i915_gem_restore_fences(dev
);
4998 i915_gem_detect_bit_6_swizzle(dev
);
4999 init_waitqueue_head(&dev_priv
->pending_flip_queue
);
5001 dev_priv
->mm
.interruptible
= true;
5003 i915_gem_shrinker_init(dev_priv
);
5005 mutex_init(&dev_priv
->fb_tracking
.lock
);
5008 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
)
5010 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
5012 /* Clean up our request list when the client is going away, so that
5013 * later retire_requests won't dereference our soon-to-be-gone
5016 spin_lock(&file_priv
->mm
.lock
);
5017 while (!list_empty(&file_priv
->mm
.request_list
)) {
5018 struct drm_i915_gem_request
*request
;
5020 request
= list_first_entry(&file_priv
->mm
.request_list
,
5021 struct drm_i915_gem_request
,
5023 list_del(&request
->client_list
);
5024 request
->file_priv
= NULL
;
5026 spin_unlock(&file_priv
->mm
.lock
);
5028 if (!list_empty(&file_priv
->rps
.link
)) {
5029 spin_lock(&to_i915(dev
)->rps
.client_lock
);
5030 list_del(&file_priv
->rps
.link
);
5031 spin_unlock(&to_i915(dev
)->rps
.client_lock
);
5035 int i915_gem_open(struct drm_device
*dev
, struct drm_file
*file
)
5037 struct drm_i915_file_private
*file_priv
;
5040 DRM_DEBUG_DRIVER("\n");
5042 file_priv
= kzalloc(sizeof(*file_priv
), GFP_KERNEL
);
5046 file
->driver_priv
= file_priv
;
5047 file_priv
->dev_priv
= dev
->dev_private
;
5048 file_priv
->file
= file
;
5049 INIT_LIST_HEAD(&file_priv
->rps
.link
);
5051 spin_lock_init(&file_priv
->mm
.lock
);
5052 INIT_LIST_HEAD(&file_priv
->mm
.request_list
);
5054 ret
= i915_gem_context_open(dev
, file
);
5062 * i915_gem_track_fb - update frontbuffer tracking
5063 * @old: current GEM buffer for the frontbuffer slots
5064 * @new: new GEM buffer for the frontbuffer slots
5065 * @frontbuffer_bits: bitmask of frontbuffer slots
5067 * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them
5068 * from @old and setting them in @new. Both @old and @new can be NULL.
5070 void i915_gem_track_fb(struct drm_i915_gem_object
*old
,
5071 struct drm_i915_gem_object
*new,
5072 unsigned frontbuffer_bits
)
5075 WARN_ON(!mutex_is_locked(&old
->base
.dev
->struct_mutex
));
5076 WARN_ON(!(old
->frontbuffer_bits
& frontbuffer_bits
));
5077 old
->frontbuffer_bits
&= ~frontbuffer_bits
;
5081 WARN_ON(!mutex_is_locked(&new->base
.dev
->struct_mutex
));
5082 WARN_ON(new->frontbuffer_bits
& frontbuffer_bits
);
5083 new->frontbuffer_bits
|= frontbuffer_bits
;
5087 /* All the new VM stuff */
5088 u64
i915_gem_obj_offset(struct drm_i915_gem_object
*o
,
5089 struct i915_address_space
*vm
)
5091 struct drm_i915_private
*dev_priv
= o
->base
.dev
->dev_private
;
5092 struct i915_vma
*vma
;
5094 WARN_ON(vm
== &dev_priv
->mm
.aliasing_ppgtt
->base
);
5096 list_for_each_entry(vma
, &o
->vma_list
, vma_link
) {
5097 if (i915_is_ggtt(vma
->vm
) &&
5098 vma
->ggtt_view
.type
!= I915_GGTT_VIEW_NORMAL
)
5101 return vma
->node
.start
;
5104 WARN(1, "%s vma for this object not found.\n",
5105 i915_is_ggtt(vm
) ? "global" : "ppgtt");
5109 u64
i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object
*o
,
5110 const struct i915_ggtt_view
*view
)
5112 struct i915_address_space
*ggtt
= i915_obj_to_ggtt(o
);
5113 struct i915_vma
*vma
;
5115 list_for_each_entry(vma
, &o
->vma_list
, vma_link
)
5116 if (vma
->vm
== ggtt
&&
5117 i915_ggtt_view_equal(&vma
->ggtt_view
, view
))
5118 return vma
->node
.start
;
5120 WARN(1, "global vma for this object not found. (view=%u)\n", view
->type
);
5124 bool i915_gem_obj_bound(struct drm_i915_gem_object
*o
,
5125 struct i915_address_space
*vm
)
5127 struct i915_vma
*vma
;
5129 list_for_each_entry(vma
, &o
->vma_list
, vma_link
) {
5130 if (i915_is_ggtt(vma
->vm
) &&
5131 vma
->ggtt_view
.type
!= I915_GGTT_VIEW_NORMAL
)
5133 if (vma
->vm
== vm
&& drm_mm_node_allocated(&vma
->node
))
5140 bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object
*o
,
5141 const struct i915_ggtt_view
*view
)
5143 struct i915_address_space
*ggtt
= i915_obj_to_ggtt(o
);
5144 struct i915_vma
*vma
;
5146 list_for_each_entry(vma
, &o
->vma_list
, vma_link
)
5147 if (vma
->vm
== ggtt
&&
5148 i915_ggtt_view_equal(&vma
->ggtt_view
, view
) &&
5149 drm_mm_node_allocated(&vma
->node
))
5155 bool i915_gem_obj_bound_any(struct drm_i915_gem_object
*o
)
5157 struct i915_vma
*vma
;
5159 list_for_each_entry(vma
, &o
->vma_list
, vma_link
)
5160 if (drm_mm_node_allocated(&vma
->node
))
5166 unsigned long i915_gem_obj_size(struct drm_i915_gem_object
*o
,
5167 struct i915_address_space
*vm
)
5169 struct drm_i915_private
*dev_priv
= o
->base
.dev
->dev_private
;
5170 struct i915_vma
*vma
;
5172 WARN_ON(vm
== &dev_priv
->mm
.aliasing_ppgtt
->base
);
5174 BUG_ON(list_empty(&o
->vma_list
));
5176 list_for_each_entry(vma
, &o
->vma_list
, vma_link
) {
5177 if (i915_is_ggtt(vma
->vm
) &&
5178 vma
->ggtt_view
.type
!= I915_GGTT_VIEW_NORMAL
)
5181 return vma
->node
.size
;
5186 bool i915_gem_obj_is_pinned(struct drm_i915_gem_object
*obj
)
5188 struct i915_vma
*vma
;
5189 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
5190 if (vma
->pin_count
> 0)
5196 /* Like i915_gem_object_get_page(), but mark the returned page dirty */
5198 i915_gem_object_get_dirty_page(struct drm_i915_gem_object
*obj
, int n
)
5202 /* Only default objects have per-page dirty tracking */
5203 if (WARN_ON(obj
->ops
!= &i915_gem_object_ops
))
5206 page
= i915_gem_object_get_page(obj
, n
);
5207 set_page_dirty(page
);
5211 /* Allocate a new GEM object and fill it with the supplied data */
5212 struct drm_i915_gem_object
*
5213 i915_gem_object_create_from_data(struct drm_device
*dev
,
5214 const void *data
, size_t size
)
5216 struct drm_i915_gem_object
*obj
;
5217 struct sg_table
*sg
;
5221 obj
= i915_gem_alloc_object(dev
, round_up(size
, PAGE_SIZE
));
5222 if (IS_ERR_OR_NULL(obj
))
5225 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
5229 ret
= i915_gem_object_get_pages(obj
);
5233 i915_gem_object_pin_pages(obj
);
5235 bytes
= sg_copy_from_buffer(sg
->sgl
, sg
->nents
, (void *)data
, size
);
5236 obj
->dirty
= 1; /* Backing store is now out of date */
5237 i915_gem_object_unpin_pages(obj
);
5239 if (WARN_ON(bytes
!= size
)) {
5240 DRM_ERROR("Incomplete copy, wrote %zu of %zu", bytes
, size
);
5248 drm_gem_object_unreference(&obj
->base
);
5249 return ERR_PTR(ret
);