2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/slab.h>
35 #include <linux/swap.h>
36 #include <linux/pci.h>
37 #include <linux/intel-gtt.h>
39 struct change_domains
{
40 uint32_t invalidate_domains
;
41 uint32_t flush_domains
;
45 static uint32_t i915_gem_get_gtt_alignment(struct drm_i915_gem_object
*obj_priv
);
46 static uint32_t i915_gem_get_gtt_size(struct drm_i915_gem_object
*obj_priv
);
48 static int i915_gem_object_flush_gpu_write_domain(struct drm_gem_object
*obj
,
50 static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object
*obj
);
51 static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object
*obj
);
52 static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object
*obj
,
54 static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object
*obj
,
57 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object
*obj
);
58 static int i915_gem_object_wait_rendering(struct drm_gem_object
*obj
,
60 static int i915_gem_object_bind_to_gtt(struct drm_gem_object
*obj
,
62 bool map_and_fenceable
);
63 static void i915_gem_clear_fence_reg(struct drm_gem_object
*obj
);
64 static int i915_gem_phys_pwrite(struct drm_device
*dev
, struct drm_gem_object
*obj
,
65 struct drm_i915_gem_pwrite
*args
,
66 struct drm_file
*file_priv
);
67 static void i915_gem_free_object_tail(struct drm_gem_object
*obj
);
69 static int i915_gem_inactive_shrink(struct shrinker
*shrinker
,
74 /* some bookkeeping */
75 static void i915_gem_info_add_obj(struct drm_i915_private
*dev_priv
,
78 dev_priv
->mm
.object_count
++;
79 dev_priv
->mm
.object_memory
+= size
;
82 static void i915_gem_info_remove_obj(struct drm_i915_private
*dev_priv
,
85 dev_priv
->mm
.object_count
--;
86 dev_priv
->mm
.object_memory
-= size
;
89 static void i915_gem_info_add_gtt(struct drm_i915_private
*dev_priv
,
90 struct drm_i915_gem_object
*obj
)
92 dev_priv
->mm
.gtt_count
++;
93 dev_priv
->mm
.gtt_memory
+= obj
->gtt_space
->size
;
94 if (obj
->gtt_offset
< dev_priv
->mm
.gtt_mappable_end
) {
95 dev_priv
->mm
.mappable_gtt_used
+=
96 min_t(size_t, obj
->gtt_space
->size
,
97 dev_priv
->mm
.gtt_mappable_end
- obj
->gtt_offset
);
101 static void i915_gem_info_remove_gtt(struct drm_i915_private
*dev_priv
,
102 struct drm_i915_gem_object
*obj
)
104 dev_priv
->mm
.gtt_count
--;
105 dev_priv
->mm
.gtt_memory
-= obj
->gtt_space
->size
;
106 if (obj
->gtt_offset
< dev_priv
->mm
.gtt_mappable_end
) {
107 dev_priv
->mm
.mappable_gtt_used
-=
108 min_t(size_t, obj
->gtt_space
->size
,
109 dev_priv
->mm
.gtt_mappable_end
- obj
->gtt_offset
);
114 * Update the mappable working set counters. Call _only_ when there is a change
115 * in one of (pin|fault)_mappable and update *_mappable _before_ calling.
116 * @mappable: new state the changed mappable flag (either pin_ or fault_).
119 i915_gem_info_update_mappable(struct drm_i915_private
*dev_priv
,
120 struct drm_i915_gem_object
*obj
,
124 if (obj
->pin_mappable
&& obj
->fault_mappable
)
125 /* Combined state was already mappable. */
127 dev_priv
->mm
.gtt_mappable_count
++;
128 dev_priv
->mm
.gtt_mappable_memory
+= obj
->gtt_space
->size
;
130 if (obj
->pin_mappable
|| obj
->fault_mappable
)
131 /* Combined state still mappable. */
133 dev_priv
->mm
.gtt_mappable_count
--;
134 dev_priv
->mm
.gtt_mappable_memory
-= obj
->gtt_space
->size
;
138 static void i915_gem_info_add_pin(struct drm_i915_private
*dev_priv
,
139 struct drm_i915_gem_object
*obj
,
142 dev_priv
->mm
.pin_count
++;
143 dev_priv
->mm
.pin_memory
+= obj
->gtt_space
->size
;
145 obj
->pin_mappable
= true;
146 i915_gem_info_update_mappable(dev_priv
, obj
, true);
150 static void i915_gem_info_remove_pin(struct drm_i915_private
*dev_priv
,
151 struct drm_i915_gem_object
*obj
)
153 dev_priv
->mm
.pin_count
--;
154 dev_priv
->mm
.pin_memory
-= obj
->gtt_space
->size
;
155 if (obj
->pin_mappable
) {
156 obj
->pin_mappable
= false;
157 i915_gem_info_update_mappable(dev_priv
, obj
, false);
162 i915_gem_check_is_wedged(struct drm_device
*dev
)
164 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
165 struct completion
*x
= &dev_priv
->error_completion
;
169 if (!atomic_read(&dev_priv
->mm
.wedged
))
172 ret
= wait_for_completion_interruptible(x
);
176 /* Success, we reset the GPU! */
177 if (!atomic_read(&dev_priv
->mm
.wedged
))
180 /* GPU is hung, bump the completion count to account for
181 * the token we just consumed so that we never hit zero and
182 * end up waiting upon a subsequent completion event that
185 spin_lock_irqsave(&x
->wait
.lock
, flags
);
187 spin_unlock_irqrestore(&x
->wait
.lock
, flags
);
191 static int i915_mutex_lock_interruptible(struct drm_device
*dev
)
193 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
196 ret
= i915_gem_check_is_wedged(dev
);
200 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
204 if (atomic_read(&dev_priv
->mm
.wedged
)) {
205 mutex_unlock(&dev
->struct_mutex
);
209 WARN_ON(i915_verify_lists(dev
));
214 i915_gem_object_is_inactive(struct drm_i915_gem_object
*obj_priv
)
216 return obj_priv
->gtt_space
&&
218 obj_priv
->pin_count
== 0;
221 int i915_gem_do_init(struct drm_device
*dev
,
223 unsigned long mappable_end
,
226 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
229 (start
& (PAGE_SIZE
- 1)) != 0 ||
230 (end
& (PAGE_SIZE
- 1)) != 0) {
234 drm_mm_init(&dev_priv
->mm
.gtt_space
, start
,
237 dev_priv
->mm
.gtt_total
= end
- start
;
238 dev_priv
->mm
.mappable_gtt_total
= min(end
, mappable_end
) - start
;
239 dev_priv
->mm
.gtt_mappable_end
= mappable_end
;
245 i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
246 struct drm_file
*file_priv
)
248 struct drm_i915_gem_init
*args
= data
;
251 mutex_lock(&dev
->struct_mutex
);
252 ret
= i915_gem_do_init(dev
, args
->gtt_start
, args
->gtt_end
, args
->gtt_end
);
253 mutex_unlock(&dev
->struct_mutex
);
259 i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
260 struct drm_file
*file_priv
)
262 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
263 struct drm_i915_gem_get_aperture
*args
= data
;
265 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
268 mutex_lock(&dev
->struct_mutex
);
269 args
->aper_size
= dev_priv
->mm
.gtt_total
;
270 args
->aper_available_size
= args
->aper_size
- dev_priv
->mm
.pin_memory
;
271 mutex_unlock(&dev
->struct_mutex
);
278 * Creates a new mm object and returns a handle to it.
281 i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
282 struct drm_file
*file_priv
)
284 struct drm_i915_gem_create
*args
= data
;
285 struct drm_gem_object
*obj
;
289 args
->size
= roundup(args
->size
, PAGE_SIZE
);
291 /* Allocate the new object */
292 obj
= i915_gem_alloc_object(dev
, args
->size
);
296 ret
= drm_gem_handle_create(file_priv
, obj
, &handle
);
298 drm_gem_object_release(obj
);
299 i915_gem_info_remove_obj(dev
->dev_private
, obj
->size
);
304 /* drop reference from allocate - handle holds it now */
305 drm_gem_object_unreference(obj
);
306 trace_i915_gem_object_create(obj
);
308 args
->handle
= handle
;
312 static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object
*obj
)
314 drm_i915_private_t
*dev_priv
= obj
->dev
->dev_private
;
315 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
317 return dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_9_10_17
&&
318 obj_priv
->tiling_mode
!= I915_TILING_NONE
;
322 slow_shmem_copy(struct page
*dst_page
,
324 struct page
*src_page
,
328 char *dst_vaddr
, *src_vaddr
;
330 dst_vaddr
= kmap(dst_page
);
331 src_vaddr
= kmap(src_page
);
333 memcpy(dst_vaddr
+ dst_offset
, src_vaddr
+ src_offset
, length
);
340 slow_shmem_bit17_copy(struct page
*gpu_page
,
342 struct page
*cpu_page
,
347 char *gpu_vaddr
, *cpu_vaddr
;
349 /* Use the unswizzled path if this page isn't affected. */
350 if ((page_to_phys(gpu_page
) & (1 << 17)) == 0) {
352 return slow_shmem_copy(cpu_page
, cpu_offset
,
353 gpu_page
, gpu_offset
, length
);
355 return slow_shmem_copy(gpu_page
, gpu_offset
,
356 cpu_page
, cpu_offset
, length
);
359 gpu_vaddr
= kmap(gpu_page
);
360 cpu_vaddr
= kmap(cpu_page
);
362 /* Copy the data, XORing A6 with A17 (1). The user already knows he's
363 * XORing with the other bits (A9 for Y, A9 and A10 for X)
366 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
367 int this_length
= min(cacheline_end
- gpu_offset
, length
);
368 int swizzled_gpu_offset
= gpu_offset
^ 64;
371 memcpy(cpu_vaddr
+ cpu_offset
,
372 gpu_vaddr
+ swizzled_gpu_offset
,
375 memcpy(gpu_vaddr
+ swizzled_gpu_offset
,
376 cpu_vaddr
+ cpu_offset
,
379 cpu_offset
+= this_length
;
380 gpu_offset
+= this_length
;
381 length
-= this_length
;
389 * This is the fast shmem pread path, which attempts to copy_from_user directly
390 * from the backing pages of the object to the user's address space. On a
391 * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
394 i915_gem_shmem_pread_fast(struct drm_device
*dev
, struct drm_gem_object
*obj
,
395 struct drm_i915_gem_pread
*args
,
396 struct drm_file
*file_priv
)
398 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
399 struct address_space
*mapping
= obj
->filp
->f_path
.dentry
->d_inode
->i_mapping
;
402 char __user
*user_data
;
403 int page_offset
, page_length
;
405 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
408 obj_priv
= to_intel_bo(obj
);
409 offset
= args
->offset
;
416 /* Operation in this page
418 * page_offset = offset within page
419 * page_length = bytes to copy for this page
421 page_offset
= offset
& (PAGE_SIZE
-1);
422 page_length
= remain
;
423 if ((page_offset
+ remain
) > PAGE_SIZE
)
424 page_length
= PAGE_SIZE
- page_offset
;
426 page
= read_cache_page_gfp(mapping
, offset
>> PAGE_SHIFT
,
427 GFP_HIGHUSER
| __GFP_RECLAIMABLE
);
429 return PTR_ERR(page
);
431 vaddr
= kmap_atomic(page
);
432 ret
= __copy_to_user_inatomic(user_data
,
435 kunmap_atomic(vaddr
);
437 mark_page_accessed(page
);
438 page_cache_release(page
);
442 remain
-= page_length
;
443 user_data
+= page_length
;
444 offset
+= page_length
;
451 * This is the fallback shmem pread path, which allocates temporary storage
452 * in kernel space to copy_to_user into outside of the struct_mutex, so we
453 * can copy out of the object's backing pages while holding the struct mutex
454 * and not take page faults.
457 i915_gem_shmem_pread_slow(struct drm_device
*dev
, struct drm_gem_object
*obj
,
458 struct drm_i915_gem_pread
*args
,
459 struct drm_file
*file_priv
)
461 struct address_space
*mapping
= obj
->filp
->f_path
.dentry
->d_inode
->i_mapping
;
462 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
463 struct mm_struct
*mm
= current
->mm
;
464 struct page
**user_pages
;
466 loff_t offset
, pinned_pages
, i
;
467 loff_t first_data_page
, last_data_page
, num_pages
;
468 int shmem_page_offset
;
469 int data_page_index
, data_page_offset
;
472 uint64_t data_ptr
= args
->data_ptr
;
473 int do_bit17_swizzling
;
477 /* Pin the user pages containing the data. We can't fault while
478 * holding the struct mutex, yet we want to hold it while
479 * dereferencing the user data.
481 first_data_page
= data_ptr
/ PAGE_SIZE
;
482 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
483 num_pages
= last_data_page
- first_data_page
+ 1;
485 user_pages
= drm_malloc_ab(num_pages
, sizeof(struct page
*));
486 if (user_pages
== NULL
)
489 mutex_unlock(&dev
->struct_mutex
);
490 down_read(&mm
->mmap_sem
);
491 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
492 num_pages
, 1, 0, user_pages
, NULL
);
493 up_read(&mm
->mmap_sem
);
494 mutex_lock(&dev
->struct_mutex
);
495 if (pinned_pages
< num_pages
) {
500 ret
= i915_gem_object_set_cpu_read_domain_range(obj
,
506 do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
508 obj_priv
= to_intel_bo(obj
);
509 offset
= args
->offset
;
514 /* Operation in this page
516 * shmem_page_offset = offset within page in shmem file
517 * data_page_index = page number in get_user_pages return
518 * data_page_offset = offset with data_page_index page.
519 * page_length = bytes to copy for this page
521 shmem_page_offset
= offset
& ~PAGE_MASK
;
522 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
523 data_page_offset
= data_ptr
& ~PAGE_MASK
;
525 page_length
= remain
;
526 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
527 page_length
= PAGE_SIZE
- shmem_page_offset
;
528 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
529 page_length
= PAGE_SIZE
- data_page_offset
;
531 page
= read_cache_page_gfp(mapping
, offset
>> PAGE_SHIFT
,
532 GFP_HIGHUSER
| __GFP_RECLAIMABLE
);
534 return PTR_ERR(page
);
536 if (do_bit17_swizzling
) {
537 slow_shmem_bit17_copy(page
,
539 user_pages
[data_page_index
],
544 slow_shmem_copy(user_pages
[data_page_index
],
551 mark_page_accessed(page
);
552 page_cache_release(page
);
554 remain
-= page_length
;
555 data_ptr
+= page_length
;
556 offset
+= page_length
;
560 for (i
= 0; i
< pinned_pages
; i
++) {
561 SetPageDirty(user_pages
[i
]);
562 mark_page_accessed(user_pages
[i
]);
563 page_cache_release(user_pages
[i
]);
565 drm_free_large(user_pages
);
571 * Reads data from the object referenced by handle.
573 * On error, the contents of *data are undefined.
576 i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
577 struct drm_file
*file_priv
)
579 struct drm_i915_gem_pread
*args
= data
;
580 struct drm_gem_object
*obj
;
581 struct drm_i915_gem_object
*obj_priv
;
584 ret
= i915_mutex_lock_interruptible(dev
);
588 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
593 obj_priv
= to_intel_bo(obj
);
595 /* Bounds check source. */
596 if (args
->offset
> obj
->size
|| args
->size
> obj
->size
- args
->offset
) {
604 if (!access_ok(VERIFY_WRITE
,
605 (char __user
*)(uintptr_t)args
->data_ptr
,
611 ret
= fault_in_pages_writeable((char __user
*)(uintptr_t)args
->data_ptr
,
618 ret
= i915_gem_object_set_cpu_read_domain_range(obj
,
625 if (!i915_gem_object_needs_bit17_swizzle(obj
))
626 ret
= i915_gem_shmem_pread_fast(dev
, obj
, args
, file_priv
);
628 ret
= i915_gem_shmem_pread_slow(dev
, obj
, args
, file_priv
);
631 drm_gem_object_unreference(obj
);
633 mutex_unlock(&dev
->struct_mutex
);
637 /* This is the fast write path which cannot handle
638 * page faults in the source data
642 fast_user_write(struct io_mapping
*mapping
,
643 loff_t page_base
, int page_offset
,
644 char __user
*user_data
,
648 unsigned long unwritten
;
650 vaddr_atomic
= io_mapping_map_atomic_wc(mapping
, page_base
);
651 unwritten
= __copy_from_user_inatomic_nocache(vaddr_atomic
+ page_offset
,
653 io_mapping_unmap_atomic(vaddr_atomic
);
657 /* Here's the write path which can sleep for
662 slow_kernel_write(struct io_mapping
*mapping
,
663 loff_t gtt_base
, int gtt_offset
,
664 struct page
*user_page
, int user_offset
,
667 char __iomem
*dst_vaddr
;
670 dst_vaddr
= io_mapping_map_wc(mapping
, gtt_base
);
671 src_vaddr
= kmap(user_page
);
673 memcpy_toio(dst_vaddr
+ gtt_offset
,
674 src_vaddr
+ user_offset
,
678 io_mapping_unmap(dst_vaddr
);
682 * This is the fast pwrite path, where we copy the data directly from the
683 * user into the GTT, uncached.
686 i915_gem_gtt_pwrite_fast(struct drm_device
*dev
, struct drm_gem_object
*obj
,
687 struct drm_i915_gem_pwrite
*args
,
688 struct drm_file
*file_priv
)
690 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
691 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
693 loff_t offset
, page_base
;
694 char __user
*user_data
;
695 int page_offset
, page_length
;
697 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
700 obj_priv
= to_intel_bo(obj
);
701 offset
= obj_priv
->gtt_offset
+ args
->offset
;
704 /* Operation in this page
706 * page_base = page offset within aperture
707 * page_offset = offset within page
708 * page_length = bytes to copy for this page
710 page_base
= (offset
& ~(PAGE_SIZE
-1));
711 page_offset
= offset
& (PAGE_SIZE
-1);
712 page_length
= remain
;
713 if ((page_offset
+ remain
) > PAGE_SIZE
)
714 page_length
= PAGE_SIZE
- page_offset
;
716 /* If we get a fault while copying data, then (presumably) our
717 * source page isn't available. Return the error and we'll
718 * retry in the slow path.
720 if (fast_user_write(dev_priv
->mm
.gtt_mapping
, page_base
,
721 page_offset
, user_data
, page_length
))
725 remain
-= page_length
;
726 user_data
+= page_length
;
727 offset
+= page_length
;
734 * This is the fallback GTT pwrite path, which uses get_user_pages to pin
735 * the memory and maps it using kmap_atomic for copying.
737 * This code resulted in x11perf -rgb10text consuming about 10% more CPU
738 * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
741 i915_gem_gtt_pwrite_slow(struct drm_device
*dev
, struct drm_gem_object
*obj
,
742 struct drm_i915_gem_pwrite
*args
,
743 struct drm_file
*file_priv
)
745 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
746 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
748 loff_t gtt_page_base
, offset
;
749 loff_t first_data_page
, last_data_page
, num_pages
;
750 loff_t pinned_pages
, i
;
751 struct page
**user_pages
;
752 struct mm_struct
*mm
= current
->mm
;
753 int gtt_page_offset
, data_page_offset
, data_page_index
, page_length
;
755 uint64_t data_ptr
= args
->data_ptr
;
759 /* Pin the user pages containing the data. We can't fault while
760 * holding the struct mutex, and all of the pwrite implementations
761 * want to hold it while dereferencing the user data.
763 first_data_page
= data_ptr
/ PAGE_SIZE
;
764 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
765 num_pages
= last_data_page
- first_data_page
+ 1;
767 user_pages
= drm_malloc_ab(num_pages
, sizeof(struct page
*));
768 if (user_pages
== NULL
)
771 mutex_unlock(&dev
->struct_mutex
);
772 down_read(&mm
->mmap_sem
);
773 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
774 num_pages
, 0, 0, user_pages
, NULL
);
775 up_read(&mm
->mmap_sem
);
776 mutex_lock(&dev
->struct_mutex
);
777 if (pinned_pages
< num_pages
) {
779 goto out_unpin_pages
;
782 ret
= i915_gem_object_set_to_gtt_domain(obj
, 1);
784 goto out_unpin_pages
;
786 obj_priv
= to_intel_bo(obj
);
787 offset
= obj_priv
->gtt_offset
+ args
->offset
;
790 /* Operation in this page
792 * gtt_page_base = page offset within aperture
793 * gtt_page_offset = offset within page in aperture
794 * data_page_index = page number in get_user_pages return
795 * data_page_offset = offset with data_page_index page.
796 * page_length = bytes to copy for this page
798 gtt_page_base
= offset
& PAGE_MASK
;
799 gtt_page_offset
= offset
& ~PAGE_MASK
;
800 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
801 data_page_offset
= data_ptr
& ~PAGE_MASK
;
803 page_length
= remain
;
804 if ((gtt_page_offset
+ page_length
) > PAGE_SIZE
)
805 page_length
= PAGE_SIZE
- gtt_page_offset
;
806 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
807 page_length
= PAGE_SIZE
- data_page_offset
;
809 slow_kernel_write(dev_priv
->mm
.gtt_mapping
,
810 gtt_page_base
, gtt_page_offset
,
811 user_pages
[data_page_index
],
815 remain
-= page_length
;
816 offset
+= page_length
;
817 data_ptr
+= page_length
;
821 for (i
= 0; i
< pinned_pages
; i
++)
822 page_cache_release(user_pages
[i
]);
823 drm_free_large(user_pages
);
829 * This is the fast shmem pwrite path, which attempts to directly
830 * copy_from_user into the kmapped pages backing the object.
833 i915_gem_shmem_pwrite_fast(struct drm_device
*dev
, struct drm_gem_object
*obj
,
834 struct drm_i915_gem_pwrite
*args
,
835 struct drm_file
*file_priv
)
837 struct address_space
*mapping
= obj
->filp
->f_path
.dentry
->d_inode
->i_mapping
;
838 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
841 char __user
*user_data
;
842 int page_offset
, page_length
;
844 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
847 obj_priv
= to_intel_bo(obj
);
848 offset
= args
->offset
;
856 /* Operation in this page
858 * page_offset = offset within page
859 * page_length = bytes to copy for this page
861 page_offset
= offset
& (PAGE_SIZE
-1);
862 page_length
= remain
;
863 if ((page_offset
+ remain
) > PAGE_SIZE
)
864 page_length
= PAGE_SIZE
- page_offset
;
866 page
= read_cache_page_gfp(mapping
, offset
>> PAGE_SHIFT
,
867 GFP_HIGHUSER
| __GFP_RECLAIMABLE
);
869 return PTR_ERR(page
);
871 vaddr
= kmap_atomic(page
, KM_USER0
);
872 ret
= __copy_from_user_inatomic(vaddr
+ page_offset
,
875 kunmap_atomic(vaddr
, KM_USER0
);
877 set_page_dirty(page
);
878 mark_page_accessed(page
);
879 page_cache_release(page
);
881 /* If we get a fault while copying data, then (presumably) our
882 * source page isn't available. Return the error and we'll
883 * retry in the slow path.
888 remain
-= page_length
;
889 user_data
+= page_length
;
890 offset
+= page_length
;
897 * This is the fallback shmem pwrite path, which uses get_user_pages to pin
898 * the memory and maps it using kmap_atomic for copying.
900 * This avoids taking mmap_sem for faulting on the user's address while the
901 * struct_mutex is held.
904 i915_gem_shmem_pwrite_slow(struct drm_device
*dev
, struct drm_gem_object
*obj
,
905 struct drm_i915_gem_pwrite
*args
,
906 struct drm_file
*file_priv
)
908 struct address_space
*mapping
= obj
->filp
->f_path
.dentry
->d_inode
->i_mapping
;
909 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
910 struct mm_struct
*mm
= current
->mm
;
911 struct page
**user_pages
;
913 loff_t offset
, pinned_pages
, i
;
914 loff_t first_data_page
, last_data_page
, num_pages
;
915 int shmem_page_offset
;
916 int data_page_index
, data_page_offset
;
919 uint64_t data_ptr
= args
->data_ptr
;
920 int do_bit17_swizzling
;
924 /* Pin the user pages containing the data. We can't fault while
925 * holding the struct mutex, and all of the pwrite implementations
926 * want to hold it while dereferencing the user data.
928 first_data_page
= data_ptr
/ PAGE_SIZE
;
929 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
930 num_pages
= last_data_page
- first_data_page
+ 1;
932 user_pages
= drm_malloc_ab(num_pages
, sizeof(struct page
*));
933 if (user_pages
== NULL
)
936 mutex_unlock(&dev
->struct_mutex
);
937 down_read(&mm
->mmap_sem
);
938 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
939 num_pages
, 0, 0, user_pages
, NULL
);
940 up_read(&mm
->mmap_sem
);
941 mutex_lock(&dev
->struct_mutex
);
942 if (pinned_pages
< num_pages
) {
947 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
951 do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
953 obj_priv
= to_intel_bo(obj
);
954 offset
= args
->offset
;
960 /* Operation in this page
962 * shmem_page_offset = offset within page in shmem file
963 * data_page_index = page number in get_user_pages return
964 * data_page_offset = offset with data_page_index page.
965 * page_length = bytes to copy for this page
967 shmem_page_offset
= offset
& ~PAGE_MASK
;
968 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
969 data_page_offset
= data_ptr
& ~PAGE_MASK
;
971 page_length
= remain
;
972 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
973 page_length
= PAGE_SIZE
- shmem_page_offset
;
974 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
975 page_length
= PAGE_SIZE
- data_page_offset
;
977 page
= read_cache_page_gfp(mapping
, offset
>> PAGE_SHIFT
,
978 GFP_HIGHUSER
| __GFP_RECLAIMABLE
);
984 if (do_bit17_swizzling
) {
985 slow_shmem_bit17_copy(page
,
987 user_pages
[data_page_index
],
992 slow_shmem_copy(page
,
994 user_pages
[data_page_index
],
999 set_page_dirty(page
);
1000 mark_page_accessed(page
);
1001 page_cache_release(page
);
1003 remain
-= page_length
;
1004 data_ptr
+= page_length
;
1005 offset
+= page_length
;
1009 for (i
= 0; i
< pinned_pages
; i
++)
1010 page_cache_release(user_pages
[i
]);
1011 drm_free_large(user_pages
);
1017 * Writes data to the object referenced by handle.
1019 * On error, the contents of the buffer that were to be modified are undefined.
1022 i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
1023 struct drm_file
*file
)
1025 struct drm_i915_gem_pwrite
*args
= data
;
1026 struct drm_gem_object
*obj
;
1027 struct drm_i915_gem_object
*obj_priv
;
1030 ret
= i915_mutex_lock_interruptible(dev
);
1034 obj
= drm_gem_object_lookup(dev
, file
, args
->handle
);
1039 obj_priv
= to_intel_bo(obj
);
1042 /* Bounds check destination. */
1043 if (args
->offset
> obj
->size
|| args
->size
> obj
->size
- args
->offset
) {
1048 if (args
->size
== 0)
1051 if (!access_ok(VERIFY_READ
,
1052 (char __user
*)(uintptr_t)args
->data_ptr
,
1058 ret
= fault_in_pages_readable((char __user
*)(uintptr_t)args
->data_ptr
,
1065 /* We can only do the GTT pwrite on untiled buffers, as otherwise
1066 * it would end up going through the fenced access, and we'll get
1067 * different detiling behavior between reading and writing.
1068 * pread/pwrite currently are reading and writing from the CPU
1069 * perspective, requiring manual detiling by the client.
1071 if (obj_priv
->phys_obj
)
1072 ret
= i915_gem_phys_pwrite(dev
, obj
, args
, file
);
1073 else if (obj_priv
->tiling_mode
== I915_TILING_NONE
&&
1074 obj_priv
->gtt_space
&&
1075 obj
->write_domain
!= I915_GEM_DOMAIN_CPU
) {
1076 ret
= i915_gem_object_pin(obj
, 0, true);
1080 ret
= i915_gem_object_set_to_gtt_domain(obj
, 1);
1084 ret
= i915_gem_gtt_pwrite_fast(dev
, obj
, args
, file
);
1086 ret
= i915_gem_gtt_pwrite_slow(dev
, obj
, args
, file
);
1089 i915_gem_object_unpin(obj
);
1091 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
1096 if (!i915_gem_object_needs_bit17_swizzle(obj
))
1097 ret
= i915_gem_shmem_pwrite_fast(dev
, obj
, args
, file
);
1099 ret
= i915_gem_shmem_pwrite_slow(dev
, obj
, args
, file
);
1103 drm_gem_object_unreference(obj
);
1105 mutex_unlock(&dev
->struct_mutex
);
1110 * Called when user space prepares to use an object with the CPU, either
1111 * through the mmap ioctl's mapping or a GTT mapping.
1114 i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
1115 struct drm_file
*file_priv
)
1117 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1118 struct drm_i915_gem_set_domain
*args
= data
;
1119 struct drm_gem_object
*obj
;
1120 struct drm_i915_gem_object
*obj_priv
;
1121 uint32_t read_domains
= args
->read_domains
;
1122 uint32_t write_domain
= args
->write_domain
;
1125 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1128 /* Only handle setting domains to types used by the CPU. */
1129 if (write_domain
& I915_GEM_GPU_DOMAINS
)
1132 if (read_domains
& I915_GEM_GPU_DOMAINS
)
1135 /* Having something in the write domain implies it's in the read
1136 * domain, and only that read domain. Enforce that in the request.
1138 if (write_domain
!= 0 && read_domains
!= write_domain
)
1141 ret
= i915_mutex_lock_interruptible(dev
);
1145 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1150 obj_priv
= to_intel_bo(obj
);
1152 intel_mark_busy(dev
, obj
);
1154 if (read_domains
& I915_GEM_DOMAIN_GTT
) {
1155 ret
= i915_gem_object_set_to_gtt_domain(obj
, write_domain
!= 0);
1157 /* Update the LRU on the fence for the CPU access that's
1160 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
) {
1161 struct drm_i915_fence_reg
*reg
=
1162 &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
1163 list_move_tail(®
->lru_list
,
1164 &dev_priv
->mm
.fence_list
);
1167 /* Silently promote "you're not bound, there was nothing to do"
1168 * to success, since the client was just asking us to
1169 * make sure everything was done.
1174 ret
= i915_gem_object_set_to_cpu_domain(obj
, write_domain
!= 0);
1177 /* Maintain LRU order of "inactive" objects */
1178 if (ret
== 0 && i915_gem_object_is_inactive(obj_priv
))
1179 list_move_tail(&obj_priv
->mm_list
, &dev_priv
->mm
.inactive_list
);
1181 drm_gem_object_unreference(obj
);
1183 mutex_unlock(&dev
->struct_mutex
);
1188 * Called when user space has done writes to this buffer
1191 i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1192 struct drm_file
*file_priv
)
1194 struct drm_i915_gem_sw_finish
*args
= data
;
1195 struct drm_gem_object
*obj
;
1198 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1201 ret
= i915_mutex_lock_interruptible(dev
);
1205 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1211 /* Pinned buffers may be scanout, so flush the cache */
1212 if (to_intel_bo(obj
)->pin_count
)
1213 i915_gem_object_flush_cpu_write_domain(obj
);
1215 drm_gem_object_unreference(obj
);
1217 mutex_unlock(&dev
->struct_mutex
);
1222 * Maps the contents of an object, returning the address it is mapped
1225 * While the mapping holds a reference on the contents of the object, it doesn't
1226 * imply a ref on the object itself.
1229 i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1230 struct drm_file
*file_priv
)
1232 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1233 struct drm_i915_gem_mmap
*args
= data
;
1234 struct drm_gem_object
*obj
;
1238 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1241 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1245 if (obj
->size
> dev_priv
->mm
.gtt_mappable_end
) {
1246 drm_gem_object_unreference_unlocked(obj
);
1250 offset
= args
->offset
;
1252 down_write(¤t
->mm
->mmap_sem
);
1253 addr
= do_mmap(obj
->filp
, 0, args
->size
,
1254 PROT_READ
| PROT_WRITE
, MAP_SHARED
,
1256 up_write(¤t
->mm
->mmap_sem
);
1257 drm_gem_object_unreference_unlocked(obj
);
1258 if (IS_ERR((void *)addr
))
1261 args
->addr_ptr
= (uint64_t) addr
;
1267 * i915_gem_fault - fault a page into the GTT
1268 * vma: VMA in question
1271 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1272 * from userspace. The fault handler takes care of binding the object to
1273 * the GTT (if needed), allocating and programming a fence register (again,
1274 * only if needed based on whether the old reg is still valid or the object
1275 * is tiled) and inserting a new PTE into the faulting process.
1277 * Note that the faulting process may involve evicting existing objects
1278 * from the GTT and/or fence registers to make room. So performance may
1279 * suffer if the GTT working set is large or there are few fence registers
1282 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
)
1284 struct drm_gem_object
*obj
= vma
->vm_private_data
;
1285 struct drm_device
*dev
= obj
->dev
;
1286 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1287 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1288 pgoff_t page_offset
;
1291 bool write
= !!(vmf
->flags
& FAULT_FLAG_WRITE
);
1293 /* We don't use vmf->pgoff since that has the fake offset */
1294 page_offset
= ((unsigned long)vmf
->virtual_address
- vma
->vm_start
) >>
1297 /* Now bind it into the GTT if needed */
1298 mutex_lock(&dev
->struct_mutex
);
1299 BUG_ON(obj_priv
->pin_count
&& !obj_priv
->pin_mappable
);
1301 if (obj_priv
->gtt_space
) {
1302 if (!obj_priv
->map_and_fenceable
) {
1303 ret
= i915_gem_object_unbind(obj
);
1309 if (!obj_priv
->gtt_space
) {
1310 ret
= i915_gem_object_bind_to_gtt(obj
, 0, true);
1315 ret
= i915_gem_object_set_to_gtt_domain(obj
, write
);
1319 if (!obj_priv
->fault_mappable
) {
1320 obj_priv
->fault_mappable
= true;
1321 i915_gem_info_update_mappable(dev_priv
, obj_priv
, true);
1324 /* Need a new fence register? */
1325 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
) {
1326 ret
= i915_gem_object_get_fence_reg(obj
, true);
1331 if (i915_gem_object_is_inactive(obj_priv
))
1332 list_move_tail(&obj_priv
->mm_list
, &dev_priv
->mm
.inactive_list
);
1334 pfn
= ((dev
->agp
->base
+ obj_priv
->gtt_offset
) >> PAGE_SHIFT
) +
1337 /* Finally, remap it using the new GTT offset */
1338 ret
= vm_insert_pfn(vma
, (unsigned long)vmf
->virtual_address
, pfn
);
1340 mutex_unlock(&dev
->struct_mutex
);
1347 return VM_FAULT_NOPAGE
;
1349 return VM_FAULT_OOM
;
1351 return VM_FAULT_SIGBUS
;
1356 * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1357 * @obj: obj in question
1359 * GEM memory mapping works by handing back to userspace a fake mmap offset
1360 * it can use in a subsequent mmap(2) call. The DRM core code then looks
1361 * up the object based on the offset and sets up the various memory mapping
1364 * This routine allocates and attaches a fake offset for @obj.
1367 i915_gem_create_mmap_offset(struct drm_gem_object
*obj
)
1369 struct drm_device
*dev
= obj
->dev
;
1370 struct drm_gem_mm
*mm
= dev
->mm_private
;
1371 struct drm_map_list
*list
;
1372 struct drm_local_map
*map
;
1375 /* Set the object up for mmap'ing */
1376 list
= &obj
->map_list
;
1377 list
->map
= kzalloc(sizeof(struct drm_map_list
), GFP_KERNEL
);
1382 map
->type
= _DRM_GEM
;
1383 map
->size
= obj
->size
;
1386 /* Get a DRM GEM mmap offset allocated... */
1387 list
->file_offset_node
= drm_mm_search_free(&mm
->offset_manager
,
1388 obj
->size
/ PAGE_SIZE
, 0, 0);
1389 if (!list
->file_offset_node
) {
1390 DRM_ERROR("failed to allocate offset for bo %d\n", obj
->name
);
1395 list
->file_offset_node
= drm_mm_get_block(list
->file_offset_node
,
1396 obj
->size
/ PAGE_SIZE
, 0);
1397 if (!list
->file_offset_node
) {
1402 list
->hash
.key
= list
->file_offset_node
->start
;
1403 ret
= drm_ht_insert_item(&mm
->offset_hash
, &list
->hash
);
1405 DRM_ERROR("failed to add to map hash\n");
1412 drm_mm_put_block(list
->file_offset_node
);
1421 * i915_gem_release_mmap - remove physical page mappings
1422 * @obj: obj in question
1424 * Preserve the reservation of the mmapping with the DRM core code, but
1425 * relinquish ownership of the pages back to the system.
1427 * It is vital that we remove the page mapping if we have mapped a tiled
1428 * object through the GTT and then lose the fence register due to
1429 * resource pressure. Similarly if the object has been moved out of the
1430 * aperture, than pages mapped into userspace must be revoked. Removing the
1431 * mapping will then trigger a page fault on the next user access, allowing
1432 * fixup by i915_gem_fault().
1435 i915_gem_release_mmap(struct drm_gem_object
*obj
)
1437 struct drm_device
*dev
= obj
->dev
;
1438 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1439 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1441 if (unlikely(obj
->map_list
.map
&& dev
->dev_mapping
))
1442 unmap_mapping_range(dev
->dev_mapping
,
1443 (loff_t
)obj
->map_list
.hash
.key
<<PAGE_SHIFT
,
1446 if (obj_priv
->fault_mappable
) {
1447 obj_priv
->fault_mappable
= false;
1448 i915_gem_info_update_mappable(dev_priv
, obj_priv
, false);
1453 i915_gem_free_mmap_offset(struct drm_gem_object
*obj
)
1455 struct drm_device
*dev
= obj
->dev
;
1456 struct drm_gem_mm
*mm
= dev
->mm_private
;
1457 struct drm_map_list
*list
= &obj
->map_list
;
1459 drm_ht_remove_item(&mm
->offset_hash
, &list
->hash
);
1460 drm_mm_put_block(list
->file_offset_node
);
1466 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1467 * @obj: object to check
1469 * Return the required GTT alignment for an object, taking into account
1470 * potential fence register mapping if needed.
1473 i915_gem_get_gtt_alignment(struct drm_i915_gem_object
*obj_priv
)
1475 struct drm_device
*dev
= obj_priv
->base
.dev
;
1478 * Minimum alignment is 4k (GTT page size), but might be greater
1479 * if a fence register is needed for the object.
1481 if (INTEL_INFO(dev
)->gen
>= 4 ||
1482 obj_priv
->tiling_mode
== I915_TILING_NONE
)
1486 * Previous chips need to be aligned to the size of the smallest
1487 * fence register that can contain the object.
1489 return i915_gem_get_gtt_size(obj_priv
);
1493 i915_gem_get_gtt_size(struct drm_i915_gem_object
*obj_priv
)
1495 struct drm_device
*dev
= obj_priv
->base
.dev
;
1499 * Minimum alignment is 4k (GTT page size), but might be greater
1500 * if a fence register is needed for the object.
1502 if (INTEL_INFO(dev
)->gen
>= 4)
1503 return obj_priv
->base
.size
;
1506 * Previous chips need to be aligned to the size of the smallest
1507 * fence register that can contain the object.
1509 if (INTEL_INFO(dev
)->gen
== 3)
1514 while (size
< obj_priv
->base
.size
)
1521 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1523 * @data: GTT mapping ioctl data
1524 * @file_priv: GEM object info
1526 * Simply returns the fake offset to userspace so it can mmap it.
1527 * The mmap call will end up in drm_gem_mmap(), which will set things
1528 * up so we can get faults in the handler above.
1530 * The fault handler will take care of binding the object into the GTT
1531 * (since it may have been evicted to make room for something), allocating
1532 * a fence register, and mapping the appropriate aperture address into
1536 i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
1537 struct drm_file
*file_priv
)
1539 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1540 struct drm_i915_gem_mmap_gtt
*args
= data
;
1541 struct drm_gem_object
*obj
;
1542 struct drm_i915_gem_object
*obj_priv
;
1545 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1548 ret
= i915_mutex_lock_interruptible(dev
);
1552 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1557 obj_priv
= to_intel_bo(obj
);
1559 if (obj
->size
> dev_priv
->mm
.gtt_mappable_end
) {
1564 if (obj_priv
->madv
!= I915_MADV_WILLNEED
) {
1565 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1570 if (!obj
->map_list
.map
) {
1571 ret
= i915_gem_create_mmap_offset(obj
);
1576 args
->offset
= (u64
)obj
->map_list
.hash
.key
<< PAGE_SHIFT
;
1579 drm_gem_object_unreference(obj
);
1581 mutex_unlock(&dev
->struct_mutex
);
1586 i915_gem_object_get_pages_gtt(struct drm_gem_object
*obj
,
1589 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1591 struct address_space
*mapping
;
1592 struct inode
*inode
;
1595 /* Get the list of pages out of our struct file. They'll be pinned
1596 * at this point until we release them.
1598 page_count
= obj
->size
/ PAGE_SIZE
;
1599 BUG_ON(obj_priv
->pages
!= NULL
);
1600 obj_priv
->pages
= drm_malloc_ab(page_count
, sizeof(struct page
*));
1601 if (obj_priv
->pages
== NULL
)
1604 inode
= obj
->filp
->f_path
.dentry
->d_inode
;
1605 mapping
= inode
->i_mapping
;
1606 for (i
= 0; i
< page_count
; i
++) {
1607 page
= read_cache_page_gfp(mapping
, i
,
1615 obj_priv
->pages
[i
] = page
;
1618 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
)
1619 i915_gem_object_do_bit_17_swizzle(obj
);
1625 page_cache_release(obj_priv
->pages
[i
]);
1627 drm_free_large(obj_priv
->pages
);
1628 obj_priv
->pages
= NULL
;
1629 return PTR_ERR(page
);
1633 i915_gem_object_put_pages_gtt(struct drm_gem_object
*obj
)
1635 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1636 int page_count
= obj
->size
/ PAGE_SIZE
;
1639 BUG_ON(obj_priv
->madv
== __I915_MADV_PURGED
);
1641 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
)
1642 i915_gem_object_save_bit_17_swizzle(obj
);
1644 if (obj_priv
->madv
== I915_MADV_DONTNEED
)
1645 obj_priv
->dirty
= 0;
1647 for (i
= 0; i
< page_count
; i
++) {
1648 if (obj_priv
->dirty
)
1649 set_page_dirty(obj_priv
->pages
[i
]);
1651 if (obj_priv
->madv
== I915_MADV_WILLNEED
)
1652 mark_page_accessed(obj_priv
->pages
[i
]);
1654 page_cache_release(obj_priv
->pages
[i
]);
1656 obj_priv
->dirty
= 0;
1658 drm_free_large(obj_priv
->pages
);
1659 obj_priv
->pages
= NULL
;
1663 i915_gem_next_request_seqno(struct drm_device
*dev
,
1664 struct intel_ring_buffer
*ring
)
1666 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1668 ring
->outstanding_lazy_request
= true;
1669 return dev_priv
->next_seqno
;
1673 i915_gem_object_move_to_active(struct drm_gem_object
*obj
,
1674 struct intel_ring_buffer
*ring
)
1676 struct drm_device
*dev
= obj
->dev
;
1677 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1678 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1679 uint32_t seqno
= i915_gem_next_request_seqno(dev
, ring
);
1681 BUG_ON(ring
== NULL
);
1682 obj_priv
->ring
= ring
;
1684 /* Add a reference if we're newly entering the active list. */
1685 if (!obj_priv
->active
) {
1686 drm_gem_object_reference(obj
);
1687 obj_priv
->active
= 1;
1690 /* Move from whatever list we were on to the tail of execution. */
1691 list_move_tail(&obj_priv
->mm_list
, &dev_priv
->mm
.active_list
);
1692 list_move_tail(&obj_priv
->ring_list
, &ring
->active_list
);
1693 obj_priv
->last_rendering_seqno
= seqno
;
1697 i915_gem_object_move_to_flushing(struct drm_gem_object
*obj
)
1699 struct drm_device
*dev
= obj
->dev
;
1700 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1701 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1703 BUG_ON(!obj_priv
->active
);
1704 list_move_tail(&obj_priv
->mm_list
, &dev_priv
->mm
.flushing_list
);
1705 list_del_init(&obj_priv
->ring_list
);
1706 obj_priv
->last_rendering_seqno
= 0;
1709 /* Immediately discard the backing storage */
1711 i915_gem_object_truncate(struct drm_gem_object
*obj
)
1713 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1714 struct inode
*inode
;
1716 /* Our goal here is to return as much of the memory as
1717 * is possible back to the system as we are called from OOM.
1718 * To do this we must instruct the shmfs to drop all of its
1719 * backing pages, *now*. Here we mirror the actions taken
1720 * when by shmem_delete_inode() to release the backing store.
1722 inode
= obj
->filp
->f_path
.dentry
->d_inode
;
1723 truncate_inode_pages(inode
->i_mapping
, 0);
1724 if (inode
->i_op
->truncate_range
)
1725 inode
->i_op
->truncate_range(inode
, 0, (loff_t
)-1);
1727 obj_priv
->madv
= __I915_MADV_PURGED
;
1731 i915_gem_object_is_purgeable(struct drm_i915_gem_object
*obj_priv
)
1733 return obj_priv
->madv
== I915_MADV_DONTNEED
;
1737 i915_gem_object_move_to_inactive(struct drm_gem_object
*obj
)
1739 struct drm_device
*dev
= obj
->dev
;
1740 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1741 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1743 if (obj_priv
->pin_count
!= 0)
1744 list_move_tail(&obj_priv
->mm_list
, &dev_priv
->mm
.pinned_list
);
1746 list_move_tail(&obj_priv
->mm_list
, &dev_priv
->mm
.inactive_list
);
1747 list_del_init(&obj_priv
->ring_list
);
1749 BUG_ON(!list_empty(&obj_priv
->gpu_write_list
));
1751 obj_priv
->last_rendering_seqno
= 0;
1752 obj_priv
->ring
= NULL
;
1753 if (obj_priv
->active
) {
1754 obj_priv
->active
= 0;
1755 drm_gem_object_unreference(obj
);
1757 WARN_ON(i915_verify_lists(dev
));
1761 i915_gem_process_flushing_list(struct drm_device
*dev
,
1762 uint32_t flush_domains
,
1763 struct intel_ring_buffer
*ring
)
1765 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1766 struct drm_i915_gem_object
*obj_priv
, *next
;
1768 list_for_each_entry_safe(obj_priv
, next
,
1769 &ring
->gpu_write_list
,
1771 struct drm_gem_object
*obj
= &obj_priv
->base
;
1773 if (obj
->write_domain
& flush_domains
) {
1774 uint32_t old_write_domain
= obj
->write_domain
;
1776 obj
->write_domain
= 0;
1777 list_del_init(&obj_priv
->gpu_write_list
);
1778 i915_gem_object_move_to_active(obj
, ring
);
1780 /* update the fence lru list */
1781 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
) {
1782 struct drm_i915_fence_reg
*reg
=
1783 &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
1784 list_move_tail(®
->lru_list
,
1785 &dev_priv
->mm
.fence_list
);
1788 trace_i915_gem_object_change_domain(obj
,
1796 i915_add_request(struct drm_device
*dev
,
1797 struct drm_file
*file
,
1798 struct drm_i915_gem_request
*request
,
1799 struct intel_ring_buffer
*ring
)
1801 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1802 struct drm_i915_file_private
*file_priv
= NULL
;
1807 BUG_ON(request
== NULL
);
1810 file_priv
= file
->driver_priv
;
1812 ret
= ring
->add_request(ring
, &seqno
);
1816 ring
->outstanding_lazy_request
= false;
1818 request
->seqno
= seqno
;
1819 request
->ring
= ring
;
1820 request
->emitted_jiffies
= jiffies
;
1821 was_empty
= list_empty(&ring
->request_list
);
1822 list_add_tail(&request
->list
, &ring
->request_list
);
1825 spin_lock(&file_priv
->mm
.lock
);
1826 request
->file_priv
= file_priv
;
1827 list_add_tail(&request
->client_list
,
1828 &file_priv
->mm
.request_list
);
1829 spin_unlock(&file_priv
->mm
.lock
);
1832 if (!dev_priv
->mm
.suspended
) {
1833 mod_timer(&dev_priv
->hangcheck_timer
,
1834 jiffies
+ msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD
));
1836 queue_delayed_work(dev_priv
->wq
,
1837 &dev_priv
->mm
.retire_work
, HZ
);
1843 * Command execution barrier
1845 * Ensures that all commands in the ring are finished
1846 * before signalling the CPU
1849 i915_retire_commands(struct drm_device
*dev
, struct intel_ring_buffer
*ring
)
1851 uint32_t flush_domains
= 0;
1853 /* The sampler always gets flushed on i965 (sigh) */
1854 if (INTEL_INFO(dev
)->gen
>= 4)
1855 flush_domains
|= I915_GEM_DOMAIN_SAMPLER
;
1857 ring
->flush(ring
, I915_GEM_DOMAIN_COMMAND
, flush_domains
);
1861 i915_gem_request_remove_from_client(struct drm_i915_gem_request
*request
)
1863 struct drm_i915_file_private
*file_priv
= request
->file_priv
;
1868 spin_lock(&file_priv
->mm
.lock
);
1869 list_del(&request
->client_list
);
1870 request
->file_priv
= NULL
;
1871 spin_unlock(&file_priv
->mm
.lock
);
1874 static void i915_gem_reset_ring_lists(struct drm_i915_private
*dev_priv
,
1875 struct intel_ring_buffer
*ring
)
1877 while (!list_empty(&ring
->request_list
)) {
1878 struct drm_i915_gem_request
*request
;
1880 request
= list_first_entry(&ring
->request_list
,
1881 struct drm_i915_gem_request
,
1884 list_del(&request
->list
);
1885 i915_gem_request_remove_from_client(request
);
1889 while (!list_empty(&ring
->active_list
)) {
1890 struct drm_i915_gem_object
*obj_priv
;
1892 obj_priv
= list_first_entry(&ring
->active_list
,
1893 struct drm_i915_gem_object
,
1896 obj_priv
->base
.write_domain
= 0;
1897 list_del_init(&obj_priv
->gpu_write_list
);
1898 i915_gem_object_move_to_inactive(&obj_priv
->base
);
1902 void i915_gem_reset(struct drm_device
*dev
)
1904 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1905 struct drm_i915_gem_object
*obj_priv
;
1908 i915_gem_reset_ring_lists(dev_priv
, &dev_priv
->render_ring
);
1909 i915_gem_reset_ring_lists(dev_priv
, &dev_priv
->bsd_ring
);
1910 i915_gem_reset_ring_lists(dev_priv
, &dev_priv
->blt_ring
);
1912 /* Remove anything from the flushing lists. The GPU cache is likely
1913 * to be lost on reset along with the data, so simply move the
1914 * lost bo to the inactive list.
1916 while (!list_empty(&dev_priv
->mm
.flushing_list
)) {
1917 obj_priv
= list_first_entry(&dev_priv
->mm
.flushing_list
,
1918 struct drm_i915_gem_object
,
1921 obj_priv
->base
.write_domain
= 0;
1922 list_del_init(&obj_priv
->gpu_write_list
);
1923 i915_gem_object_move_to_inactive(&obj_priv
->base
);
1926 /* Move everything out of the GPU domains to ensure we do any
1927 * necessary invalidation upon reuse.
1929 list_for_each_entry(obj_priv
,
1930 &dev_priv
->mm
.inactive_list
,
1933 obj_priv
->base
.read_domains
&= ~I915_GEM_GPU_DOMAINS
;
1936 /* The fence registers are invalidated so clear them out */
1937 for (i
= 0; i
< 16; i
++) {
1938 struct drm_i915_fence_reg
*reg
;
1940 reg
= &dev_priv
->fence_regs
[i
];
1944 i915_gem_clear_fence_reg(reg
->obj
);
1949 * This function clears the request list as sequence numbers are passed.
1952 i915_gem_retire_requests_ring(struct drm_device
*dev
,
1953 struct intel_ring_buffer
*ring
)
1955 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1958 if (!ring
->status_page
.page_addr
||
1959 list_empty(&ring
->request_list
))
1962 WARN_ON(i915_verify_lists(dev
));
1964 seqno
= ring
->get_seqno(ring
);
1965 while (!list_empty(&ring
->request_list
)) {
1966 struct drm_i915_gem_request
*request
;
1968 request
= list_first_entry(&ring
->request_list
,
1969 struct drm_i915_gem_request
,
1972 if (!i915_seqno_passed(seqno
, request
->seqno
))
1975 trace_i915_gem_request_retire(dev
, request
->seqno
);
1977 list_del(&request
->list
);
1978 i915_gem_request_remove_from_client(request
);
1982 /* Move any buffers on the active list that are no longer referenced
1983 * by the ringbuffer to the flushing/inactive lists as appropriate.
1985 while (!list_empty(&ring
->active_list
)) {
1986 struct drm_gem_object
*obj
;
1987 struct drm_i915_gem_object
*obj_priv
;
1989 obj_priv
= list_first_entry(&ring
->active_list
,
1990 struct drm_i915_gem_object
,
1993 if (!i915_seqno_passed(seqno
, obj_priv
->last_rendering_seqno
))
1996 obj
= &obj_priv
->base
;
1997 if (obj
->write_domain
!= 0)
1998 i915_gem_object_move_to_flushing(obj
);
2000 i915_gem_object_move_to_inactive(obj
);
2003 if (unlikely (dev_priv
->trace_irq_seqno
&&
2004 i915_seqno_passed(dev_priv
->trace_irq_seqno
, seqno
))) {
2005 ring
->user_irq_put(ring
);
2006 dev_priv
->trace_irq_seqno
= 0;
2009 WARN_ON(i915_verify_lists(dev
));
2013 i915_gem_retire_requests(struct drm_device
*dev
)
2015 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2017 if (!list_empty(&dev_priv
->mm
.deferred_free_list
)) {
2018 struct drm_i915_gem_object
*obj_priv
, *tmp
;
2020 /* We must be careful that during unbind() we do not
2021 * accidentally infinitely recurse into retire requests.
2023 * retire -> free -> unbind -> wait -> retire_ring
2025 list_for_each_entry_safe(obj_priv
, tmp
,
2026 &dev_priv
->mm
.deferred_free_list
,
2028 i915_gem_free_object_tail(&obj_priv
->base
);
2031 i915_gem_retire_requests_ring(dev
, &dev_priv
->render_ring
);
2032 i915_gem_retire_requests_ring(dev
, &dev_priv
->bsd_ring
);
2033 i915_gem_retire_requests_ring(dev
, &dev_priv
->blt_ring
);
2037 i915_gem_retire_work_handler(struct work_struct
*work
)
2039 drm_i915_private_t
*dev_priv
;
2040 struct drm_device
*dev
;
2042 dev_priv
= container_of(work
, drm_i915_private_t
,
2043 mm
.retire_work
.work
);
2044 dev
= dev_priv
->dev
;
2046 /* Come back later if the device is busy... */
2047 if (!mutex_trylock(&dev
->struct_mutex
)) {
2048 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, HZ
);
2052 i915_gem_retire_requests(dev
);
2054 if (!dev_priv
->mm
.suspended
&&
2055 (!list_empty(&dev_priv
->render_ring
.request_list
) ||
2056 !list_empty(&dev_priv
->bsd_ring
.request_list
) ||
2057 !list_empty(&dev_priv
->blt_ring
.request_list
)))
2058 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, HZ
);
2059 mutex_unlock(&dev
->struct_mutex
);
2063 i915_do_wait_request(struct drm_device
*dev
, uint32_t seqno
,
2064 bool interruptible
, struct intel_ring_buffer
*ring
)
2066 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2072 if (atomic_read(&dev_priv
->mm
.wedged
))
2075 if (ring
->outstanding_lazy_request
) {
2076 struct drm_i915_gem_request
*request
;
2078 request
= kzalloc(sizeof(*request
), GFP_KERNEL
);
2079 if (request
== NULL
)
2082 ret
= i915_add_request(dev
, NULL
, request
, ring
);
2088 seqno
= request
->seqno
;
2090 BUG_ON(seqno
== dev_priv
->next_seqno
);
2092 if (!i915_seqno_passed(ring
->get_seqno(ring
), seqno
)) {
2093 if (HAS_PCH_SPLIT(dev
))
2094 ier
= I915_READ(DEIER
) | I915_READ(GTIER
);
2096 ier
= I915_READ(IER
);
2098 DRM_ERROR("something (likely vbetool) disabled "
2099 "interrupts, re-enabling\n");
2100 i915_driver_irq_preinstall(dev
);
2101 i915_driver_irq_postinstall(dev
);
2104 trace_i915_gem_request_wait_begin(dev
, seqno
);
2106 ring
->waiting_seqno
= seqno
;
2107 ring
->user_irq_get(ring
);
2109 ret
= wait_event_interruptible(ring
->irq_queue
,
2110 i915_seqno_passed(ring
->get_seqno(ring
), seqno
)
2111 || atomic_read(&dev_priv
->mm
.wedged
));
2113 wait_event(ring
->irq_queue
,
2114 i915_seqno_passed(ring
->get_seqno(ring
), seqno
)
2115 || atomic_read(&dev_priv
->mm
.wedged
));
2117 ring
->user_irq_put(ring
);
2118 ring
->waiting_seqno
= 0;
2120 trace_i915_gem_request_wait_end(dev
, seqno
);
2122 if (atomic_read(&dev_priv
->mm
.wedged
))
2125 if (ret
&& ret
!= -ERESTARTSYS
)
2126 DRM_ERROR("%s returns %d (awaiting %d at %d, next %d)\n",
2127 __func__
, ret
, seqno
, ring
->get_seqno(ring
),
2128 dev_priv
->next_seqno
);
2130 /* Directly dispatch request retiring. While we have the work queue
2131 * to handle this, the waiter on a request often wants an associated
2132 * buffer to have made it to the inactive list, and we would need
2133 * a separate wait queue to handle that.
2136 i915_gem_retire_requests_ring(dev
, ring
);
2142 * Waits for a sequence number to be signaled, and cleans up the
2143 * request and object lists appropriately for that event.
2146 i915_wait_request(struct drm_device
*dev
, uint32_t seqno
,
2147 struct intel_ring_buffer
*ring
)
2149 return i915_do_wait_request(dev
, seqno
, 1, ring
);
2153 i915_gem_flush_ring(struct drm_device
*dev
,
2154 struct drm_file
*file_priv
,
2155 struct intel_ring_buffer
*ring
,
2156 uint32_t invalidate_domains
,
2157 uint32_t flush_domains
)
2159 ring
->flush(ring
, invalidate_domains
, flush_domains
);
2160 i915_gem_process_flushing_list(dev
, flush_domains
, ring
);
2164 i915_gem_flush(struct drm_device
*dev
,
2165 struct drm_file
*file_priv
,
2166 uint32_t invalidate_domains
,
2167 uint32_t flush_domains
,
2168 uint32_t flush_rings
)
2170 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2172 if (flush_domains
& I915_GEM_DOMAIN_CPU
)
2173 drm_agp_chipset_flush(dev
);
2175 if ((flush_domains
| invalidate_domains
) & I915_GEM_GPU_DOMAINS
) {
2176 if (flush_rings
& RING_RENDER
)
2177 i915_gem_flush_ring(dev
, file_priv
,
2178 &dev_priv
->render_ring
,
2179 invalidate_domains
, flush_domains
);
2180 if (flush_rings
& RING_BSD
)
2181 i915_gem_flush_ring(dev
, file_priv
,
2182 &dev_priv
->bsd_ring
,
2183 invalidate_domains
, flush_domains
);
2184 if (flush_rings
& RING_BLT
)
2185 i915_gem_flush_ring(dev
, file_priv
,
2186 &dev_priv
->blt_ring
,
2187 invalidate_domains
, flush_domains
);
2192 * Ensures that all rendering to the object has completed and the object is
2193 * safe to unbind from the GTT or access from the CPU.
2196 i915_gem_object_wait_rendering(struct drm_gem_object
*obj
,
2199 struct drm_device
*dev
= obj
->dev
;
2200 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2203 /* This function only exists to support waiting for existing rendering,
2204 * not for emitting required flushes.
2206 BUG_ON((obj
->write_domain
& I915_GEM_GPU_DOMAINS
) != 0);
2208 /* If there is rendering queued on the buffer being evicted, wait for
2211 if (obj_priv
->active
) {
2212 ret
= i915_do_wait_request(dev
,
2213 obj_priv
->last_rendering_seqno
,
2224 * Unbinds an object from the GTT aperture.
2227 i915_gem_object_unbind(struct drm_gem_object
*obj
)
2229 struct drm_device
*dev
= obj
->dev
;
2230 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2231 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2234 if (obj_priv
->gtt_space
== NULL
)
2237 if (obj_priv
->pin_count
!= 0) {
2238 DRM_ERROR("Attempting to unbind pinned buffer\n");
2242 /* blow away mappings if mapped through GTT */
2243 i915_gem_release_mmap(obj
);
2245 /* Move the object to the CPU domain to ensure that
2246 * any possible CPU writes while it's not in the GTT
2247 * are flushed when we go to remap it. This will
2248 * also ensure that all pending GPU writes are finished
2251 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
2252 if (ret
== -ERESTARTSYS
)
2254 /* Continue on if we fail due to EIO, the GPU is hung so we
2255 * should be safe and we need to cleanup or else we might
2256 * cause memory corruption through use-after-free.
2259 i915_gem_clflush_object(obj
);
2260 obj
->read_domains
= obj
->write_domain
= I915_GEM_DOMAIN_CPU
;
2263 /* release the fence reg _after_ flushing */
2264 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
)
2265 i915_gem_clear_fence_reg(obj
);
2267 drm_unbind_agp(obj_priv
->agp_mem
);
2268 drm_free_agp(obj_priv
->agp_mem
, obj
->size
/ PAGE_SIZE
);
2270 i915_gem_object_put_pages_gtt(obj
);
2272 i915_gem_info_remove_gtt(dev_priv
, obj_priv
);
2273 list_del_init(&obj_priv
->mm_list
);
2274 /* Avoid an unnecessary call to unbind on rebind. */
2275 obj_priv
->map_and_fenceable
= true;
2277 drm_mm_put_block(obj_priv
->gtt_space
);
2278 obj_priv
->gtt_space
= NULL
;
2279 obj_priv
->gtt_offset
= 0;
2281 if (i915_gem_object_is_purgeable(obj_priv
))
2282 i915_gem_object_truncate(obj
);
2284 trace_i915_gem_object_unbind(obj
);
2289 static int i915_ring_idle(struct drm_device
*dev
,
2290 struct intel_ring_buffer
*ring
)
2292 if (list_empty(&ring
->gpu_write_list
) && list_empty(&ring
->active_list
))
2295 i915_gem_flush_ring(dev
, NULL
, ring
,
2296 I915_GEM_GPU_DOMAINS
, I915_GEM_GPU_DOMAINS
);
2297 return i915_wait_request(dev
,
2298 i915_gem_next_request_seqno(dev
, ring
),
2303 i915_gpu_idle(struct drm_device
*dev
)
2305 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2309 lists_empty
= (list_empty(&dev_priv
->mm
.flushing_list
) &&
2310 list_empty(&dev_priv
->mm
.active_list
));
2314 /* Flush everything onto the inactive list. */
2315 ret
= i915_ring_idle(dev
, &dev_priv
->render_ring
);
2319 ret
= i915_ring_idle(dev
, &dev_priv
->bsd_ring
);
2323 ret
= i915_ring_idle(dev
, &dev_priv
->blt_ring
);
2330 static void sandybridge_write_fence_reg(struct drm_gem_object
*obj
)
2332 struct drm_device
*dev
= obj
->dev
;
2333 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2334 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2335 u32 size
= i915_gem_get_gtt_size(obj_priv
);
2336 int regnum
= obj_priv
->fence_reg
;
2339 val
= (uint64_t)((obj_priv
->gtt_offset
+ size
- 4096) &
2341 val
|= obj_priv
->gtt_offset
& 0xfffff000;
2342 val
|= (uint64_t)((obj_priv
->stride
/ 128) - 1) <<
2343 SANDYBRIDGE_FENCE_PITCH_SHIFT
;
2345 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2346 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
2347 val
|= I965_FENCE_REG_VALID
;
2349 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0
+ (regnum
* 8), val
);
2352 static void i965_write_fence_reg(struct drm_gem_object
*obj
)
2354 struct drm_device
*dev
= obj
->dev
;
2355 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2356 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2357 u32 size
= i915_gem_get_gtt_size(obj_priv
);
2358 int regnum
= obj_priv
->fence_reg
;
2361 val
= (uint64_t)((obj_priv
->gtt_offset
+ size
- 4096) &
2363 val
|= obj_priv
->gtt_offset
& 0xfffff000;
2364 val
|= ((obj_priv
->stride
/ 128) - 1) << I965_FENCE_PITCH_SHIFT
;
2365 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2366 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
2367 val
|= I965_FENCE_REG_VALID
;
2369 I915_WRITE64(FENCE_REG_965_0
+ (regnum
* 8), val
);
2372 static void i915_write_fence_reg(struct drm_gem_object
*obj
)
2374 struct drm_device
*dev
= obj
->dev
;
2375 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2376 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2377 u32 size
= i915_gem_get_gtt_size(obj_priv
);
2378 uint32_t fence_reg
, val
, pitch_val
;
2381 if ((obj_priv
->gtt_offset
& ~I915_FENCE_START_MASK
) ||
2382 (obj_priv
->gtt_offset
& (size
- 1))) {
2383 WARN(1, "%s: object 0x%08x [fenceable? %d] not 1M or size (0x%08x) aligned [gtt_space offset=%lx, size=%lx]\n",
2384 __func__
, obj_priv
->gtt_offset
, obj_priv
->map_and_fenceable
, size
,
2385 obj_priv
->gtt_space
->start
, obj_priv
->gtt_space
->size
);
2389 if (obj_priv
->tiling_mode
== I915_TILING_Y
&&
2390 HAS_128_BYTE_Y_TILING(dev
))
2395 /* Note: pitch better be a power of two tile widths */
2396 pitch_val
= obj_priv
->stride
/ tile_width
;
2397 pitch_val
= ffs(pitch_val
) - 1;
2399 if (obj_priv
->tiling_mode
== I915_TILING_Y
&&
2400 HAS_128_BYTE_Y_TILING(dev
))
2401 WARN_ON(pitch_val
> I830_FENCE_MAX_PITCH_VAL
);
2403 WARN_ON(pitch_val
> I915_FENCE_MAX_PITCH_VAL
);
2405 val
= obj_priv
->gtt_offset
;
2406 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2407 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2408 val
|= I915_FENCE_SIZE_BITS(size
);
2409 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2410 val
|= I830_FENCE_REG_VALID
;
2412 fence_reg
= obj_priv
->fence_reg
;
2414 fence_reg
= FENCE_REG_830_0
+ fence_reg
* 4;
2416 fence_reg
= FENCE_REG_945_8
+ (fence_reg
- 8) * 4;
2417 I915_WRITE(fence_reg
, val
);
2420 static void i830_write_fence_reg(struct drm_gem_object
*obj
)
2422 struct drm_device
*dev
= obj
->dev
;
2423 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2424 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2425 u32 size
= i915_gem_get_gtt_size(obj_priv
);
2426 int regnum
= obj_priv
->fence_reg
;
2429 uint32_t fence_size_bits
;
2431 if ((obj_priv
->gtt_offset
& ~I830_FENCE_START_MASK
) ||
2432 (obj_priv
->gtt_offset
& (obj
->size
- 1))) {
2433 WARN(1, "%s: object 0x%08x not 512K or size aligned\n",
2434 __func__
, obj_priv
->gtt_offset
);
2438 pitch_val
= obj_priv
->stride
/ 128;
2439 pitch_val
= ffs(pitch_val
) - 1;
2440 WARN_ON(pitch_val
> I830_FENCE_MAX_PITCH_VAL
);
2442 val
= obj_priv
->gtt_offset
;
2443 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2444 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2445 fence_size_bits
= I830_FENCE_SIZE_BITS(size
);
2446 WARN_ON(fence_size_bits
& ~0x00000f00);
2447 val
|= fence_size_bits
;
2448 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2449 val
|= I830_FENCE_REG_VALID
;
2451 I915_WRITE(FENCE_REG_830_0
+ (regnum
* 4), val
);
2454 static int i915_find_fence_reg(struct drm_device
*dev
,
2457 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2458 struct drm_i915_fence_reg
*reg
;
2459 struct drm_i915_gem_object
*obj_priv
= NULL
;
2462 /* First try to find a free reg */
2464 for (i
= dev_priv
->fence_reg_start
; i
< dev_priv
->num_fence_regs
; i
++) {
2465 reg
= &dev_priv
->fence_regs
[i
];
2469 obj_priv
= to_intel_bo(reg
->obj
);
2470 if (!obj_priv
->pin_count
)
2477 /* None available, try to steal one or wait for a user to finish */
2478 avail
= I915_FENCE_REG_NONE
;
2479 list_for_each_entry(reg
, &dev_priv
->mm
.fence_list
,
2481 obj_priv
= to_intel_bo(reg
->obj
);
2482 if (obj_priv
->pin_count
)
2486 avail
= obj_priv
->fence_reg
;
2490 BUG_ON(avail
== I915_FENCE_REG_NONE
);
2492 /* We only have a reference on obj from the active list. put_fence_reg
2493 * might drop that one, causing a use-after-free in it. So hold a
2494 * private reference to obj like the other callers of put_fence_reg
2495 * (set_tiling ioctl) do. */
2496 drm_gem_object_reference(&obj_priv
->base
);
2497 ret
= i915_gem_object_put_fence_reg(&obj_priv
->base
, interruptible
);
2498 drm_gem_object_unreference(&obj_priv
->base
);
2506 * i915_gem_object_get_fence_reg - set up a fence reg for an object
2507 * @obj: object to map through a fence reg
2509 * When mapping objects through the GTT, userspace wants to be able to write
2510 * to them without having to worry about swizzling if the object is tiled.
2512 * This function walks the fence regs looking for a free one for @obj,
2513 * stealing one if it can't find any.
2515 * It then sets up the reg based on the object's properties: address, pitch
2516 * and tiling format.
2519 i915_gem_object_get_fence_reg(struct drm_gem_object
*obj
,
2522 struct drm_device
*dev
= obj
->dev
;
2523 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2524 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2525 struct drm_i915_fence_reg
*reg
= NULL
;
2528 /* Just update our place in the LRU if our fence is getting used. */
2529 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
) {
2530 reg
= &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
2531 list_move_tail(®
->lru_list
, &dev_priv
->mm
.fence_list
);
2535 switch (obj_priv
->tiling_mode
) {
2536 case I915_TILING_NONE
:
2537 WARN(1, "allocating a fence for non-tiled object?\n");
2540 if (!obj_priv
->stride
)
2542 WARN((obj_priv
->stride
& (512 - 1)),
2543 "object 0x%08x is X tiled but has non-512B pitch\n",
2544 obj_priv
->gtt_offset
);
2547 if (!obj_priv
->stride
)
2549 WARN((obj_priv
->stride
& (128 - 1)),
2550 "object 0x%08x is Y tiled but has non-128B pitch\n",
2551 obj_priv
->gtt_offset
);
2555 ret
= i915_find_fence_reg(dev
, interruptible
);
2559 obj_priv
->fence_reg
= ret
;
2560 reg
= &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
2561 list_add_tail(®
->lru_list
, &dev_priv
->mm
.fence_list
);
2565 switch (INTEL_INFO(dev
)->gen
) {
2567 sandybridge_write_fence_reg(obj
);
2571 i965_write_fence_reg(obj
);
2574 i915_write_fence_reg(obj
);
2577 i830_write_fence_reg(obj
);
2581 trace_i915_gem_object_get_fence(obj
,
2582 obj_priv
->fence_reg
,
2583 obj_priv
->tiling_mode
);
2589 * i915_gem_clear_fence_reg - clear out fence register info
2590 * @obj: object to clear
2592 * Zeroes out the fence register itself and clears out the associated
2593 * data structures in dev_priv and obj_priv.
2596 i915_gem_clear_fence_reg(struct drm_gem_object
*obj
)
2598 struct drm_device
*dev
= obj
->dev
;
2599 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2600 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2601 struct drm_i915_fence_reg
*reg
=
2602 &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
2605 switch (INTEL_INFO(dev
)->gen
) {
2607 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0
+
2608 (obj_priv
->fence_reg
* 8), 0);
2612 I915_WRITE64(FENCE_REG_965_0
+ (obj_priv
->fence_reg
* 8), 0);
2615 if (obj_priv
->fence_reg
>= 8)
2616 fence_reg
= FENCE_REG_945_8
+ (obj_priv
->fence_reg
- 8) * 4;
2619 fence_reg
= FENCE_REG_830_0
+ obj_priv
->fence_reg
* 4;
2621 I915_WRITE(fence_reg
, 0);
2626 obj_priv
->fence_reg
= I915_FENCE_REG_NONE
;
2627 list_del_init(®
->lru_list
);
2631 * i915_gem_object_put_fence_reg - waits on outstanding fenced access
2632 * to the buffer to finish, and then resets the fence register.
2633 * @obj: tiled object holding a fence register.
2634 * @bool: whether the wait upon the fence is interruptible
2636 * Zeroes out the fence register itself and clears out the associated
2637 * data structures in dev_priv and obj_priv.
2640 i915_gem_object_put_fence_reg(struct drm_gem_object
*obj
,
2643 struct drm_device
*dev
= obj
->dev
;
2644 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2645 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2646 struct drm_i915_fence_reg
*reg
;
2648 if (obj_priv
->fence_reg
== I915_FENCE_REG_NONE
)
2651 /* If we've changed tiling, GTT-mappings of the object
2652 * need to re-fault to ensure that the correct fence register
2653 * setup is in place.
2655 i915_gem_release_mmap(obj
);
2657 /* On the i915, GPU access to tiled buffers is via a fence,
2658 * therefore we must wait for any outstanding access to complete
2659 * before clearing the fence.
2661 reg
= &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
2665 ret
= i915_gem_object_flush_gpu_write_domain(obj
, true);
2669 ret
= i915_gem_object_wait_rendering(obj
, interruptible
);
2676 i915_gem_object_flush_gtt_write_domain(obj
);
2677 i915_gem_clear_fence_reg(obj
);
2683 * Finds free space in the GTT aperture and binds the object there.
2686 i915_gem_object_bind_to_gtt(struct drm_gem_object
*obj
,
2688 bool map_and_fenceable
)
2690 struct drm_device
*dev
= obj
->dev
;
2691 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2692 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2693 struct drm_mm_node
*free_space
;
2694 gfp_t gfpmask
= __GFP_NORETRY
| __GFP_NOWARN
;
2695 u32 size
, fence_size
, fence_alignment
;
2696 bool mappable
, fenceable
;
2699 if (obj_priv
->madv
!= I915_MADV_WILLNEED
) {
2700 DRM_ERROR("Attempting to bind a purgeable object\n");
2704 fence_size
= i915_gem_get_gtt_size(obj_priv
);
2705 fence_alignment
= i915_gem_get_gtt_alignment(obj_priv
);
2708 alignment
= map_and_fenceable
? fence_alignment
: 4096;
2709 if (map_and_fenceable
&& alignment
& (fence_alignment
- 1)) {
2710 DRM_ERROR("Invalid object alignment requested %u\n", alignment
);
2714 size
= map_and_fenceable
? fence_size
: obj
->size
;
2716 /* If the object is bigger than the entire aperture, reject it early
2717 * before evicting everything in a vain attempt to find space.
2720 (map_and_fenceable
? dev_priv
->mm
.gtt_mappable_end
: dev_priv
->mm
.gtt_total
)) {
2721 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2726 if (map_and_fenceable
)
2728 drm_mm_search_free_in_range(&dev_priv
->mm
.gtt_space
,
2730 dev_priv
->mm
.gtt_mappable_end
,
2733 free_space
= drm_mm_search_free(&dev_priv
->mm
.gtt_space
,
2734 size
, alignment
, 0);
2736 if (free_space
!= NULL
) {
2737 if (map_and_fenceable
)
2738 obj_priv
->gtt_space
=
2739 drm_mm_get_block_range_generic(free_space
,
2741 dev_priv
->mm
.gtt_mappable_end
,
2744 obj_priv
->gtt_space
=
2745 drm_mm_get_block(free_space
, size
, alignment
);
2747 if (obj_priv
->gtt_space
== NULL
) {
2748 /* If the gtt is empty and we're still having trouble
2749 * fitting our object in, we're out of memory.
2751 ret
= i915_gem_evict_something(dev
, size
, alignment
,
2759 ret
= i915_gem_object_get_pages_gtt(obj
, gfpmask
);
2761 drm_mm_put_block(obj_priv
->gtt_space
);
2762 obj_priv
->gtt_space
= NULL
;
2764 if (ret
== -ENOMEM
) {
2765 /* first try to clear up some space from the GTT */
2766 ret
= i915_gem_evict_something(dev
, size
,
2770 /* now try to shrink everyone else */
2785 /* Create an AGP memory structure pointing at our pages, and bind it
2788 obj_priv
->agp_mem
= drm_agp_bind_pages(dev
,
2790 obj
->size
>> PAGE_SHIFT
,
2791 obj_priv
->gtt_space
->start
,
2792 obj_priv
->agp_type
);
2793 if (obj_priv
->agp_mem
== NULL
) {
2794 i915_gem_object_put_pages_gtt(obj
);
2795 drm_mm_put_block(obj_priv
->gtt_space
);
2796 obj_priv
->gtt_space
= NULL
;
2798 ret
= i915_gem_evict_something(dev
, size
,
2799 alignment
, map_and_fenceable
);
2806 obj_priv
->gtt_offset
= obj_priv
->gtt_space
->start
;
2808 /* keep track of bounds object by adding it to the inactive list */
2809 list_add_tail(&obj_priv
->mm_list
, &dev_priv
->mm
.inactive_list
);
2810 i915_gem_info_add_gtt(dev_priv
, obj_priv
);
2812 /* Assert that the object is not currently in any GPU domain. As it
2813 * wasn't in the GTT, there shouldn't be any way it could have been in
2816 BUG_ON(obj
->read_domains
& I915_GEM_GPU_DOMAINS
);
2817 BUG_ON(obj
->write_domain
& I915_GEM_GPU_DOMAINS
);
2819 trace_i915_gem_object_bind(obj
, obj_priv
->gtt_offset
, map_and_fenceable
);
2822 obj_priv
->gtt_space
->size
== fence_size
&&
2823 (obj_priv
->gtt_space
->start
& (fence_alignment
-1)) == 0;
2826 obj_priv
->gtt_offset
+ obj
->size
<= dev_priv
->mm
.gtt_mappable_end
;
2828 obj_priv
->map_and_fenceable
= mappable
&& fenceable
;
2834 i915_gem_clflush_object(struct drm_gem_object
*obj
)
2836 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2838 /* If we don't have a page list set up, then we're not pinned
2839 * to GPU, and we can ignore the cache flush because it'll happen
2840 * again at bind time.
2842 if (obj_priv
->pages
== NULL
)
2845 trace_i915_gem_object_clflush(obj
);
2847 drm_clflush_pages(obj_priv
->pages
, obj
->size
/ PAGE_SIZE
);
2850 /** Flushes any GPU write domain for the object if it's dirty. */
2852 i915_gem_object_flush_gpu_write_domain(struct drm_gem_object
*obj
,
2855 struct drm_device
*dev
= obj
->dev
;
2857 if ((obj
->write_domain
& I915_GEM_GPU_DOMAINS
) == 0)
2860 /* Queue the GPU write cache flushing we need. */
2861 i915_gem_flush_ring(dev
, NULL
,
2862 to_intel_bo(obj
)->ring
,
2863 0, obj
->write_domain
);
2864 BUG_ON(obj
->write_domain
);
2869 return i915_gem_object_wait_rendering(obj
, true);
2872 /** Flushes the GTT write domain for the object if it's dirty. */
2874 i915_gem_object_flush_gtt_write_domain(struct drm_gem_object
*obj
)
2876 uint32_t old_write_domain
;
2878 if (obj
->write_domain
!= I915_GEM_DOMAIN_GTT
)
2881 /* No actual flushing is required for the GTT write domain. Writes
2882 * to it immediately go to main memory as far as we know, so there's
2883 * no chipset flush. It also doesn't land in render cache.
2885 i915_gem_release_mmap(obj
);
2887 old_write_domain
= obj
->write_domain
;
2888 obj
->write_domain
= 0;
2890 trace_i915_gem_object_change_domain(obj
,
2895 /** Flushes the CPU write domain for the object if it's dirty. */
2897 i915_gem_object_flush_cpu_write_domain(struct drm_gem_object
*obj
)
2899 struct drm_device
*dev
= obj
->dev
;
2900 uint32_t old_write_domain
;
2902 if (obj
->write_domain
!= I915_GEM_DOMAIN_CPU
)
2905 i915_gem_clflush_object(obj
);
2906 drm_agp_chipset_flush(dev
);
2907 old_write_domain
= obj
->write_domain
;
2908 obj
->write_domain
= 0;
2910 trace_i915_gem_object_change_domain(obj
,
2916 * Moves a single object to the GTT read, and possibly write domain.
2918 * This function returns when the move is complete, including waiting on
2922 i915_gem_object_set_to_gtt_domain(struct drm_gem_object
*obj
, int write
)
2924 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2925 uint32_t old_write_domain
, old_read_domains
;
2928 /* Not valid to be called on unbound objects. */
2929 if (obj_priv
->gtt_space
== NULL
)
2932 ret
= i915_gem_object_flush_gpu_write_domain(obj
, false);
2936 i915_gem_object_flush_cpu_write_domain(obj
);
2939 ret
= i915_gem_object_wait_rendering(obj
, true);
2944 old_write_domain
= obj
->write_domain
;
2945 old_read_domains
= obj
->read_domains
;
2947 /* It should now be out of any other write domains, and we can update
2948 * the domain values for our changes.
2950 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
2951 obj
->read_domains
|= I915_GEM_DOMAIN_GTT
;
2953 obj
->read_domains
= I915_GEM_DOMAIN_GTT
;
2954 obj
->write_domain
= I915_GEM_DOMAIN_GTT
;
2955 obj_priv
->dirty
= 1;
2958 trace_i915_gem_object_change_domain(obj
,
2966 * Prepare buffer for display plane. Use uninterruptible for possible flush
2967 * wait, as in modesetting process we're not supposed to be interrupted.
2970 i915_gem_object_set_to_display_plane(struct drm_gem_object
*obj
,
2973 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2974 uint32_t old_read_domains
;
2977 /* Not valid to be called on unbound objects. */
2978 if (obj_priv
->gtt_space
== NULL
)
2981 ret
= i915_gem_object_flush_gpu_write_domain(obj
, true);
2985 /* Currently, we are always called from an non-interruptible context. */
2987 ret
= i915_gem_object_wait_rendering(obj
, false);
2992 i915_gem_object_flush_cpu_write_domain(obj
);
2994 old_read_domains
= obj
->read_domains
;
2995 obj
->read_domains
|= I915_GEM_DOMAIN_GTT
;
2997 trace_i915_gem_object_change_domain(obj
,
3005 * Moves a single object to the CPU read, and possibly write domain.
3007 * This function returns when the move is complete, including waiting on
3011 i915_gem_object_set_to_cpu_domain(struct drm_gem_object
*obj
, int write
)
3013 uint32_t old_write_domain
, old_read_domains
;
3016 ret
= i915_gem_object_flush_gpu_write_domain(obj
, false);
3020 i915_gem_object_flush_gtt_write_domain(obj
);
3022 /* If we have a partially-valid cache of the object in the CPU,
3023 * finish invalidating it and free the per-page flags.
3025 i915_gem_object_set_to_full_cpu_read_domain(obj
);
3028 ret
= i915_gem_object_wait_rendering(obj
, true);
3033 old_write_domain
= obj
->write_domain
;
3034 old_read_domains
= obj
->read_domains
;
3036 /* Flush the CPU cache if it's still invalid. */
3037 if ((obj
->read_domains
& I915_GEM_DOMAIN_CPU
) == 0) {
3038 i915_gem_clflush_object(obj
);
3040 obj
->read_domains
|= I915_GEM_DOMAIN_CPU
;
3043 /* It should now be out of any other write domains, and we can update
3044 * the domain values for our changes.
3046 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
3048 /* If we're writing through the CPU, then the GPU read domains will
3049 * need to be invalidated at next use.
3052 obj
->read_domains
= I915_GEM_DOMAIN_CPU
;
3053 obj
->write_domain
= I915_GEM_DOMAIN_CPU
;
3056 trace_i915_gem_object_change_domain(obj
,
3064 * Set the next domain for the specified object. This
3065 * may not actually perform the necessary flushing/invaliding though,
3066 * as that may want to be batched with other set_domain operations
3068 * This is (we hope) the only really tricky part of gem. The goal
3069 * is fairly simple -- track which caches hold bits of the object
3070 * and make sure they remain coherent. A few concrete examples may
3071 * help to explain how it works. For shorthand, we use the notation
3072 * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
3073 * a pair of read and write domain masks.
3075 * Case 1: the batch buffer
3081 * 5. Unmapped from GTT
3084 * Let's take these a step at a time
3087 * Pages allocated from the kernel may still have
3088 * cache contents, so we set them to (CPU, CPU) always.
3089 * 2. Written by CPU (using pwrite)
3090 * The pwrite function calls set_domain (CPU, CPU) and
3091 * this function does nothing (as nothing changes)
3093 * This function asserts that the object is not
3094 * currently in any GPU-based read or write domains
3096 * i915_gem_execbuffer calls set_domain (COMMAND, 0).
3097 * As write_domain is zero, this function adds in the
3098 * current read domains (CPU+COMMAND, 0).
3099 * flush_domains is set to CPU.
3100 * invalidate_domains is set to COMMAND
3101 * clflush is run to get data out of the CPU caches
3102 * then i915_dev_set_domain calls i915_gem_flush to
3103 * emit an MI_FLUSH and drm_agp_chipset_flush
3104 * 5. Unmapped from GTT
3105 * i915_gem_object_unbind calls set_domain (CPU, CPU)
3106 * flush_domains and invalidate_domains end up both zero
3107 * so no flushing/invalidating happens
3111 * Case 2: The shared render buffer
3115 * 3. Read/written by GPU
3116 * 4. set_domain to (CPU,CPU)
3117 * 5. Read/written by CPU
3118 * 6. Read/written by GPU
3121 * Same as last example, (CPU, CPU)
3123 * Nothing changes (assertions find that it is not in the GPU)
3124 * 3. Read/written by GPU
3125 * execbuffer calls set_domain (RENDER, RENDER)
3126 * flush_domains gets CPU
3127 * invalidate_domains gets GPU
3129 * MI_FLUSH and drm_agp_chipset_flush
3130 * 4. set_domain (CPU, CPU)
3131 * flush_domains gets GPU
3132 * invalidate_domains gets CPU
3133 * wait_rendering (obj) to make sure all drawing is complete.
3134 * This will include an MI_FLUSH to get the data from GPU
3136 * clflush (obj) to invalidate the CPU cache
3137 * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
3138 * 5. Read/written by CPU
3139 * cache lines are loaded and dirtied
3140 * 6. Read written by GPU
3141 * Same as last GPU access
3143 * Case 3: The constant buffer
3148 * 4. Updated (written) by CPU again
3157 * flush_domains = CPU
3158 * invalidate_domains = RENDER
3161 * drm_agp_chipset_flush
3162 * 4. Updated (written) by CPU again
3164 * flush_domains = 0 (no previous write domain)
3165 * invalidate_domains = 0 (no new read domains)
3168 * flush_domains = CPU
3169 * invalidate_domains = RENDER
3172 * drm_agp_chipset_flush
3175 i915_gem_object_set_to_gpu_domain(struct drm_gem_object
*obj
,
3176 struct intel_ring_buffer
*ring
,
3177 struct change_domains
*cd
)
3179 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
3180 uint32_t invalidate_domains
= 0;
3181 uint32_t flush_domains
= 0;
3184 * If the object isn't moving to a new write domain,
3185 * let the object stay in multiple read domains
3187 if (obj
->pending_write_domain
== 0)
3188 obj
->pending_read_domains
|= obj
->read_domains
;
3191 * Flush the current write domain if
3192 * the new read domains don't match. Invalidate
3193 * any read domains which differ from the old
3196 if (obj
->write_domain
&&
3197 (obj
->write_domain
!= obj
->pending_read_domains
||
3198 obj_priv
->ring
!= ring
)) {
3199 flush_domains
|= obj
->write_domain
;
3200 invalidate_domains
|=
3201 obj
->pending_read_domains
& ~obj
->write_domain
;
3204 * Invalidate any read caches which may have
3205 * stale data. That is, any new read domains.
3207 invalidate_domains
|= obj
->pending_read_domains
& ~obj
->read_domains
;
3208 if ((flush_domains
| invalidate_domains
) & I915_GEM_DOMAIN_CPU
)
3209 i915_gem_clflush_object(obj
);
3211 /* blow away mappings if mapped through GTT */
3212 if ((flush_domains
| invalidate_domains
) & I915_GEM_DOMAIN_GTT
)
3213 i915_gem_release_mmap(obj
);
3215 /* The actual obj->write_domain will be updated with
3216 * pending_write_domain after we emit the accumulated flush for all
3217 * of our domain changes in execbuffers (which clears objects'
3218 * write_domains). So if we have a current write domain that we
3219 * aren't changing, set pending_write_domain to that.
3221 if (flush_domains
== 0 && obj
->pending_write_domain
== 0)
3222 obj
->pending_write_domain
= obj
->write_domain
;
3224 cd
->invalidate_domains
|= invalidate_domains
;
3225 cd
->flush_domains
|= flush_domains
;
3226 if (flush_domains
& I915_GEM_GPU_DOMAINS
)
3227 cd
->flush_rings
|= obj_priv
->ring
->id
;
3228 if (invalidate_domains
& I915_GEM_GPU_DOMAINS
)
3229 cd
->flush_rings
|= ring
->id
;
3233 * Moves the object from a partially CPU read to a full one.
3235 * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3236 * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
3239 i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object
*obj
)
3241 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
3243 if (!obj_priv
->page_cpu_valid
)
3246 /* If we're partially in the CPU read domain, finish moving it in.
3248 if (obj
->read_domains
& I915_GEM_DOMAIN_CPU
) {
3251 for (i
= 0; i
<= (obj
->size
- 1) / PAGE_SIZE
; i
++) {
3252 if (obj_priv
->page_cpu_valid
[i
])
3254 drm_clflush_pages(obj_priv
->pages
+ i
, 1);
3258 /* Free the page_cpu_valid mappings which are now stale, whether
3259 * or not we've got I915_GEM_DOMAIN_CPU.
3261 kfree(obj_priv
->page_cpu_valid
);
3262 obj_priv
->page_cpu_valid
= NULL
;
3266 * Set the CPU read domain on a range of the object.
3268 * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3269 * not entirely valid. The page_cpu_valid member of the object flags which
3270 * pages have been flushed, and will be respected by
3271 * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3272 * of the whole object.
3274 * This function returns when the move is complete, including waiting on
3278 i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object
*obj
,
3279 uint64_t offset
, uint64_t size
)
3281 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
3282 uint32_t old_read_domains
;
3285 if (offset
== 0 && size
== obj
->size
)
3286 return i915_gem_object_set_to_cpu_domain(obj
, 0);
3288 ret
= i915_gem_object_flush_gpu_write_domain(obj
, false);
3291 i915_gem_object_flush_gtt_write_domain(obj
);
3293 /* If we're already fully in the CPU read domain, we're done. */
3294 if (obj_priv
->page_cpu_valid
== NULL
&&
3295 (obj
->read_domains
& I915_GEM_DOMAIN_CPU
) != 0)
3298 /* Otherwise, create/clear the per-page CPU read domain flag if we're
3299 * newly adding I915_GEM_DOMAIN_CPU
3301 if (obj_priv
->page_cpu_valid
== NULL
) {
3302 obj_priv
->page_cpu_valid
= kzalloc(obj
->size
/ PAGE_SIZE
,
3304 if (obj_priv
->page_cpu_valid
== NULL
)
3306 } else if ((obj
->read_domains
& I915_GEM_DOMAIN_CPU
) == 0)
3307 memset(obj_priv
->page_cpu_valid
, 0, obj
->size
/ PAGE_SIZE
);
3309 /* Flush the cache on any pages that are still invalid from the CPU's
3312 for (i
= offset
/ PAGE_SIZE
; i
<= (offset
+ size
- 1) / PAGE_SIZE
;
3314 if (obj_priv
->page_cpu_valid
[i
])
3317 drm_clflush_pages(obj_priv
->pages
+ i
, 1);
3319 obj_priv
->page_cpu_valid
[i
] = 1;
3322 /* It should now be out of any other write domains, and we can update
3323 * the domain values for our changes.
3325 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
3327 old_read_domains
= obj
->read_domains
;
3328 obj
->read_domains
|= I915_GEM_DOMAIN_CPU
;
3330 trace_i915_gem_object_change_domain(obj
,
3338 * Pin an object to the GTT and evaluate the relocations landing in it.
3341 i915_gem_execbuffer_relocate(struct drm_i915_gem_object
*obj
,
3342 struct drm_file
*file_priv
,
3343 struct drm_i915_gem_exec_object2
*entry
)
3345 struct drm_device
*dev
= obj
->base
.dev
;
3346 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3347 struct drm_i915_gem_relocation_entry __user
*user_relocs
;
3348 struct drm_gem_object
*target_obj
= NULL
;
3349 uint32_t target_handle
= 0;
3352 user_relocs
= (void __user
*)(uintptr_t)entry
->relocs_ptr
;
3353 for (i
= 0; i
< entry
->relocation_count
; i
++) {
3354 struct drm_i915_gem_relocation_entry reloc
;
3355 uint32_t target_offset
;
3357 if (__copy_from_user_inatomic(&reloc
,
3364 if (reloc
.target_handle
!= target_handle
) {
3365 drm_gem_object_unreference(target_obj
);
3367 target_obj
= drm_gem_object_lookup(dev
, file_priv
,
3368 reloc
.target_handle
);
3369 if (target_obj
== NULL
) {
3374 target_handle
= reloc
.target_handle
;
3376 target_offset
= to_intel_bo(target_obj
)->gtt_offset
;
3379 DRM_INFO("%s: obj %p offset %08x target %d "
3380 "read %08x write %08x gtt %08x "
3381 "presumed %08x delta %08x\n",
3385 (int) reloc
.target_handle
,
3386 (int) reloc
.read_domains
,
3387 (int) reloc
.write_domain
,
3388 (int) target_offset
,
3389 (int) reloc
.presumed_offset
,
3393 /* The target buffer should have appeared before us in the
3394 * exec_object list, so it should have a GTT space bound by now.
3396 if (target_offset
== 0) {
3397 DRM_ERROR("No GTT space found for object %d\n",
3398 reloc
.target_handle
);
3403 /* Validate that the target is in a valid r/w GPU domain */
3404 if (reloc
.write_domain
& (reloc
.write_domain
- 1)) {
3405 DRM_ERROR("reloc with multiple write domains: "
3406 "obj %p target %d offset %d "
3407 "read %08x write %08x",
3408 obj
, reloc
.target_handle
,
3411 reloc
.write_domain
);
3415 if (reloc
.write_domain
& I915_GEM_DOMAIN_CPU
||
3416 reloc
.read_domains
& I915_GEM_DOMAIN_CPU
) {
3417 DRM_ERROR("reloc with read/write CPU domains: "
3418 "obj %p target %d offset %d "
3419 "read %08x write %08x",
3420 obj
, reloc
.target_handle
,
3423 reloc
.write_domain
);
3427 if (reloc
.write_domain
&& target_obj
->pending_write_domain
&&
3428 reloc
.write_domain
!= target_obj
->pending_write_domain
) {
3429 DRM_ERROR("Write domain conflict: "
3430 "obj %p target %d offset %d "
3431 "new %08x old %08x\n",
3432 obj
, reloc
.target_handle
,
3435 target_obj
->pending_write_domain
);
3440 target_obj
->pending_read_domains
|= reloc
.read_domains
;
3441 target_obj
->pending_write_domain
|= reloc
.write_domain
;
3443 /* If the relocation already has the right value in it, no
3444 * more work needs to be done.
3446 if (target_offset
== reloc
.presumed_offset
)
3449 /* Check that the relocation address is valid... */
3450 if (reloc
.offset
> obj
->base
.size
- 4) {
3451 DRM_ERROR("Relocation beyond object bounds: "
3452 "obj %p target %d offset %d size %d.\n",
3453 obj
, reloc
.target_handle
,
3454 (int) reloc
.offset
, (int) obj
->base
.size
);
3458 if (reloc
.offset
& 3) {
3459 DRM_ERROR("Relocation not 4-byte aligned: "
3460 "obj %p target %d offset %d.\n",
3461 obj
, reloc
.target_handle
,
3462 (int) reloc
.offset
);
3467 /* and points to somewhere within the target object. */
3468 if (reloc
.delta
>= target_obj
->size
) {
3469 DRM_ERROR("Relocation beyond target object bounds: "
3470 "obj %p target %d delta %d size %d.\n",
3471 obj
, reloc
.target_handle
,
3472 (int) reloc
.delta
, (int) target_obj
->size
);
3477 reloc
.delta
+= target_offset
;
3478 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_CPU
) {
3479 uint32_t page_offset
= reloc
.offset
& ~PAGE_MASK
;
3482 vaddr
= kmap_atomic(obj
->pages
[reloc
.offset
>> PAGE_SHIFT
]);
3483 *(uint32_t *)(vaddr
+ page_offset
) = reloc
.delta
;
3484 kunmap_atomic(vaddr
);
3486 uint32_t __iomem
*reloc_entry
;
3487 void __iomem
*reloc_page
;
3489 ret
= i915_gem_object_set_to_gtt_domain(&obj
->base
, 1);
3493 /* Map the page containing the relocation we're going to perform. */
3494 reloc
.offset
+= obj
->gtt_offset
;
3495 reloc_page
= io_mapping_map_atomic_wc(dev_priv
->mm
.gtt_mapping
,
3496 reloc
.offset
& PAGE_MASK
);
3497 reloc_entry
= (uint32_t __iomem
*)
3498 (reloc_page
+ (reloc
.offset
& ~PAGE_MASK
));
3499 iowrite32(reloc
.delta
, reloc_entry
);
3500 io_mapping_unmap_atomic(reloc_page
);
3503 /* and update the user's relocation entry */
3504 reloc
.presumed_offset
= target_offset
;
3505 if (__copy_to_user_inatomic(&user_relocs
[i
].presumed_offset
,
3506 &reloc
.presumed_offset
,
3507 sizeof(reloc
.presumed_offset
))) {
3513 drm_gem_object_unreference(target_obj
);
3518 i915_gem_execbuffer_pin(struct drm_device
*dev
,
3519 struct drm_file
*file
,
3520 struct drm_gem_object
**object_list
,
3521 struct drm_i915_gem_exec_object2
*exec_list
,
3524 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3527 /* attempt to pin all of the buffers into the GTT */
3531 for (i
= 0; i
< count
; i
++) {
3532 struct drm_i915_gem_exec_object2
*entry
= &exec_list
[i
];
3533 struct drm_i915_gem_object
*obj
= to_intel_bo(object_list
[i
]);
3535 entry
->flags
& EXEC_OBJECT_NEEDS_FENCE
&&
3536 obj
->tiling_mode
!= I915_TILING_NONE
;
3538 /* g33/pnv can't fence buffers in the unmappable part */
3539 bool need_mappable
=
3540 entry
->relocation_count
? true : need_fence
;
3542 /* Check fence reg constraints and rebind if necessary */
3543 if (need_mappable
&& !obj
->map_and_fenceable
) {
3544 ret
= i915_gem_object_unbind(&obj
->base
);
3549 ret
= i915_gem_object_pin(&obj
->base
,
3556 * Pre-965 chips need a fence register set up in order
3557 * to properly handle blits to/from tiled surfaces.
3560 ret
= i915_gem_object_get_fence_reg(&obj
->base
, true);
3562 i915_gem_object_unpin(&obj
->base
);
3566 dev_priv
->fence_regs
[obj
->fence_reg
].gpu
= true;
3569 entry
->offset
= obj
->gtt_offset
;
3573 i915_gem_object_unpin(object_list
[i
]);
3575 if (ret
!= -ENOSPC
|| retry
> 1)
3578 /* First attempt, just clear anything that is purgeable.
3579 * Second attempt, clear the entire GTT.
3581 ret
= i915_gem_evict_everything(dev
, retry
== 0);
3590 i915_gem_execbuffer_move_to_gpu(struct drm_device
*dev
,
3591 struct drm_file
*file
,
3592 struct intel_ring_buffer
*ring
,
3593 struct drm_gem_object
**objects
,
3596 struct change_domains cd
;
3599 cd
.invalidate_domains
= 0;
3600 cd
.flush_domains
= 0;
3602 for (i
= 0; i
< count
; i
++)
3603 i915_gem_object_set_to_gpu_domain(objects
[i
], ring
, &cd
);
3605 if (cd
.invalidate_domains
| cd
.flush_domains
) {
3607 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
3609 cd
.invalidate_domains
,
3612 i915_gem_flush(dev
, file
,
3613 cd
.invalidate_domains
,
3618 for (i
= 0; i
< count
; i
++) {
3619 struct drm_i915_gem_object
*obj
= to_intel_bo(objects
[i
]);
3620 /* XXX replace with semaphores */
3621 if (obj
->ring
&& ring
!= obj
->ring
) {
3622 ret
= i915_gem_object_wait_rendering(&obj
->base
, true);
3631 /* Throttle our rendering by waiting until the ring has completed our requests
3632 * emitted over 20 msec ago.
3634 * Note that if we were to use the current jiffies each time around the loop,
3635 * we wouldn't escape the function with any frames outstanding if the time to
3636 * render a frame was over 20ms.
3638 * This should get us reasonable parallelism between CPU and GPU but also
3639 * relatively low latency when blocking on a particular request to finish.
3642 i915_gem_ring_throttle(struct drm_device
*dev
, struct drm_file
*file
)
3644 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3645 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
3646 unsigned long recent_enough
= jiffies
- msecs_to_jiffies(20);
3647 struct drm_i915_gem_request
*request
;
3648 struct intel_ring_buffer
*ring
= NULL
;
3652 spin_lock(&file_priv
->mm
.lock
);
3653 list_for_each_entry(request
, &file_priv
->mm
.request_list
, client_list
) {
3654 if (time_after_eq(request
->emitted_jiffies
, recent_enough
))
3657 ring
= request
->ring
;
3658 seqno
= request
->seqno
;
3660 spin_unlock(&file_priv
->mm
.lock
);
3666 if (!i915_seqno_passed(ring
->get_seqno(ring
), seqno
)) {
3667 /* And wait for the seqno passing without holding any locks and
3668 * causing extra latency for others. This is safe as the irq
3669 * generation is designed to be run atomically and so is
3672 ring
->user_irq_get(ring
);
3673 ret
= wait_event_interruptible(ring
->irq_queue
,
3674 i915_seqno_passed(ring
->get_seqno(ring
), seqno
)
3675 || atomic_read(&dev_priv
->mm
.wedged
));
3676 ring
->user_irq_put(ring
);
3678 if (ret
== 0 && atomic_read(&dev_priv
->mm
.wedged
))
3683 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, 0);
3689 i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2
*exec
,
3690 uint64_t exec_offset
)
3692 uint32_t exec_start
, exec_len
;
3694 exec_start
= (uint32_t) exec_offset
+ exec
->batch_start_offset
;
3695 exec_len
= (uint32_t) exec
->batch_len
;
3697 if ((exec_start
| exec_len
) & 0x7)
3707 validate_exec_list(struct drm_i915_gem_exec_object2
*exec
,
3712 for (i
= 0; i
< count
; i
++) {
3713 char __user
*ptr
= (char __user
*)(uintptr_t)exec
[i
].relocs_ptr
;
3714 size_t length
= exec
[i
].relocation_count
* sizeof(struct drm_i915_gem_relocation_entry
);
3716 if (!access_ok(VERIFY_READ
, ptr
, length
))
3719 /* we may also need to update the presumed offsets */
3720 if (!access_ok(VERIFY_WRITE
, ptr
, length
))
3723 if (fault_in_pages_readable(ptr
, length
))
3731 i915_gem_do_execbuffer(struct drm_device
*dev
, void *data
,
3732 struct drm_file
*file
,
3733 struct drm_i915_gem_execbuffer2
*args
,
3734 struct drm_i915_gem_exec_object2
*exec_list
)
3736 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3737 struct drm_gem_object
**object_list
= NULL
;
3738 struct drm_gem_object
*batch_obj
;
3739 struct drm_clip_rect
*cliprects
= NULL
;
3740 struct drm_i915_gem_request
*request
= NULL
;
3742 uint64_t exec_offset
;
3744 struct intel_ring_buffer
*ring
= NULL
;
3746 ret
= i915_gem_check_is_wedged(dev
);
3750 ret
= validate_exec_list(exec_list
, args
->buffer_count
);
3755 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3756 (int) args
->buffers_ptr
, args
->buffer_count
, args
->batch_len
);
3758 switch (args
->flags
& I915_EXEC_RING_MASK
) {
3759 case I915_EXEC_DEFAULT
:
3760 case I915_EXEC_RENDER
:
3761 ring
= &dev_priv
->render_ring
;
3764 if (!HAS_BSD(dev
)) {
3765 DRM_ERROR("execbuf with invalid ring (BSD)\n");
3768 ring
= &dev_priv
->bsd_ring
;
3771 if (!HAS_BLT(dev
)) {
3772 DRM_ERROR("execbuf with invalid ring (BLT)\n");
3775 ring
= &dev_priv
->blt_ring
;
3778 DRM_ERROR("execbuf with unknown ring: %d\n",
3779 (int)(args
->flags
& I915_EXEC_RING_MASK
));
3783 if (args
->buffer_count
< 1) {
3784 DRM_ERROR("execbuf with %d buffers\n", args
->buffer_count
);
3787 object_list
= drm_malloc_ab(sizeof(*object_list
), args
->buffer_count
);
3788 if (object_list
== NULL
) {
3789 DRM_ERROR("Failed to allocate object list for %d buffers\n",
3790 args
->buffer_count
);
3795 if (args
->num_cliprects
!= 0) {
3796 cliprects
= kcalloc(args
->num_cliprects
, sizeof(*cliprects
),
3798 if (cliprects
== NULL
) {
3803 ret
= copy_from_user(cliprects
,
3804 (struct drm_clip_rect __user
*)
3805 (uintptr_t) args
->cliprects_ptr
,
3806 sizeof(*cliprects
) * args
->num_cliprects
);
3808 DRM_ERROR("copy %d cliprects failed: %d\n",
3809 args
->num_cliprects
, ret
);
3815 request
= kzalloc(sizeof(*request
), GFP_KERNEL
);
3816 if (request
== NULL
) {
3821 ret
= i915_mutex_lock_interruptible(dev
);
3825 if (dev_priv
->mm
.suspended
) {
3826 mutex_unlock(&dev
->struct_mutex
);
3831 /* Look up object handles */
3832 for (i
= 0; i
< args
->buffer_count
; i
++) {
3833 struct drm_i915_gem_object
*obj_priv
;
3835 object_list
[i
] = drm_gem_object_lookup(dev
, file
,
3836 exec_list
[i
].handle
);
3837 if (object_list
[i
] == NULL
) {
3838 DRM_ERROR("Invalid object handle %d at index %d\n",
3839 exec_list
[i
].handle
, i
);
3840 /* prevent error path from reading uninitialized data */
3841 args
->buffer_count
= i
+ 1;
3846 obj_priv
= to_intel_bo(object_list
[i
]);
3847 if (obj_priv
->in_execbuffer
) {
3848 DRM_ERROR("Object %p appears more than once in object list\n",
3850 /* prevent error path from reading uninitialized data */
3851 args
->buffer_count
= i
+ 1;
3855 obj_priv
->in_execbuffer
= true;
3858 /* Move the objects en-masse into the GTT, evicting if necessary. */
3859 ret
= i915_gem_execbuffer_pin(dev
, file
,
3860 object_list
, exec_list
,
3861 args
->buffer_count
);
3865 /* The objects are in their final locations, apply the relocations. */
3866 for (i
= 0; i
< args
->buffer_count
; i
++) {
3867 struct drm_i915_gem_object
*obj
= to_intel_bo(object_list
[i
]);
3868 obj
->base
.pending_read_domains
= 0;
3869 obj
->base
.pending_write_domain
= 0;
3870 ret
= i915_gem_execbuffer_relocate(obj
, file
, &exec_list
[i
]);
3875 /* Set the pending read domains for the batch buffer to COMMAND */
3876 batch_obj
= object_list
[args
->buffer_count
-1];
3877 if (batch_obj
->pending_write_domain
) {
3878 DRM_ERROR("Attempting to use self-modifying batch buffer\n");
3882 batch_obj
->pending_read_domains
|= I915_GEM_DOMAIN_COMMAND
;
3884 /* Sanity check the batch buffer */
3885 exec_offset
= to_intel_bo(batch_obj
)->gtt_offset
;
3886 ret
= i915_gem_check_execbuffer(args
, exec_offset
);
3888 DRM_ERROR("execbuf with invalid offset/length\n");
3892 ret
= i915_gem_execbuffer_move_to_gpu(dev
, file
, ring
,
3893 object_list
, args
->buffer_count
);
3898 for (i
= 0; i
< args
->buffer_count
; i
++) {
3899 i915_gem_object_check_coherency(object_list
[i
],
3900 exec_list
[i
].handle
);
3905 i915_gem_dump_object(batch_obj
,
3911 /* Check for any pending flips. As we only maintain a flip queue depth
3912 * of 1, we can simply insert a WAIT for the next display flip prior
3913 * to executing the batch and avoid stalling the CPU.
3916 for (i
= 0; i
< args
->buffer_count
; i
++) {
3917 if (object_list
[i
]->write_domain
)
3918 flips
|= atomic_read(&to_intel_bo(object_list
[i
])->pending_flip
);
3921 int plane
, flip_mask
;
3923 for (plane
= 0; flips
>> plane
; plane
++) {
3924 if (((flips
>> plane
) & 1) == 0)
3928 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
3930 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
3932 ret
= intel_ring_begin(ring
, 2);
3936 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
3937 intel_ring_emit(ring
, MI_NOOP
);
3938 intel_ring_advance(ring
);
3942 /* Exec the batchbuffer */
3943 ret
= ring
->dispatch_execbuffer(ring
, args
, cliprects
, exec_offset
);
3945 DRM_ERROR("dispatch failed %d\n", ret
);
3949 for (i
= 0; i
< args
->buffer_count
; i
++) {
3950 struct drm_gem_object
*obj
= object_list
[i
];
3952 obj
->read_domains
= obj
->pending_read_domains
;
3953 obj
->write_domain
= obj
->pending_write_domain
;
3955 i915_gem_object_move_to_active(obj
, ring
);
3956 if (obj
->write_domain
) {
3957 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
3958 obj_priv
->dirty
= 1;
3959 list_move_tail(&obj_priv
->gpu_write_list
,
3960 &ring
->gpu_write_list
);
3961 intel_mark_busy(dev
, obj
);
3964 trace_i915_gem_object_change_domain(obj
,
3970 * Ensure that the commands in the batch buffer are
3971 * finished before the interrupt fires
3973 i915_retire_commands(dev
, ring
);
3975 if (i915_add_request(dev
, file
, request
, ring
))
3976 ring
->outstanding_lazy_request
= true;
3981 for (i
= 0; i
< args
->buffer_count
; i
++) {
3982 if (object_list
[i
] == NULL
)
3985 to_intel_bo(object_list
[i
])->in_execbuffer
= false;
3986 drm_gem_object_unreference(object_list
[i
]);
3989 mutex_unlock(&dev
->struct_mutex
);
3992 drm_free_large(object_list
);
4000 * Legacy execbuffer just creates an exec2 list from the original exec object
4001 * list array and passes it to the real function.
4004 i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
4005 struct drm_file
*file_priv
)
4007 struct drm_i915_gem_execbuffer
*args
= data
;
4008 struct drm_i915_gem_execbuffer2 exec2
;
4009 struct drm_i915_gem_exec_object
*exec_list
= NULL
;
4010 struct drm_i915_gem_exec_object2
*exec2_list
= NULL
;
4014 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
4015 (int) args
->buffers_ptr
, args
->buffer_count
, args
->batch_len
);
4018 if (args
->buffer_count
< 1) {
4019 DRM_ERROR("execbuf with %d buffers\n", args
->buffer_count
);
4023 /* Copy in the exec list from userland */
4024 exec_list
= drm_malloc_ab(sizeof(*exec_list
), args
->buffer_count
);
4025 exec2_list
= drm_malloc_ab(sizeof(*exec2_list
), args
->buffer_count
);
4026 if (exec_list
== NULL
|| exec2_list
== NULL
) {
4027 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
4028 args
->buffer_count
);
4029 drm_free_large(exec_list
);
4030 drm_free_large(exec2_list
);
4033 ret
= copy_from_user(exec_list
,
4034 (struct drm_i915_relocation_entry __user
*)
4035 (uintptr_t) args
->buffers_ptr
,
4036 sizeof(*exec_list
) * args
->buffer_count
);
4038 DRM_ERROR("copy %d exec entries failed %d\n",
4039 args
->buffer_count
, ret
);
4040 drm_free_large(exec_list
);
4041 drm_free_large(exec2_list
);
4045 for (i
= 0; i
< args
->buffer_count
; i
++) {
4046 exec2_list
[i
].handle
= exec_list
[i
].handle
;
4047 exec2_list
[i
].relocation_count
= exec_list
[i
].relocation_count
;
4048 exec2_list
[i
].relocs_ptr
= exec_list
[i
].relocs_ptr
;
4049 exec2_list
[i
].alignment
= exec_list
[i
].alignment
;
4050 exec2_list
[i
].offset
= exec_list
[i
].offset
;
4051 if (INTEL_INFO(dev
)->gen
< 4)
4052 exec2_list
[i
].flags
= EXEC_OBJECT_NEEDS_FENCE
;
4054 exec2_list
[i
].flags
= 0;
4057 exec2
.buffers_ptr
= args
->buffers_ptr
;
4058 exec2
.buffer_count
= args
->buffer_count
;
4059 exec2
.batch_start_offset
= args
->batch_start_offset
;
4060 exec2
.batch_len
= args
->batch_len
;
4061 exec2
.DR1
= args
->DR1
;
4062 exec2
.DR4
= args
->DR4
;
4063 exec2
.num_cliprects
= args
->num_cliprects
;
4064 exec2
.cliprects_ptr
= args
->cliprects_ptr
;
4065 exec2
.flags
= I915_EXEC_RENDER
;
4067 ret
= i915_gem_do_execbuffer(dev
, data
, file_priv
, &exec2
, exec2_list
);
4069 /* Copy the new buffer offsets back to the user's exec list. */
4070 for (i
= 0; i
< args
->buffer_count
; i
++)
4071 exec_list
[i
].offset
= exec2_list
[i
].offset
;
4072 /* ... and back out to userspace */
4073 ret
= copy_to_user((struct drm_i915_relocation_entry __user
*)
4074 (uintptr_t) args
->buffers_ptr
,
4076 sizeof(*exec_list
) * args
->buffer_count
);
4079 DRM_ERROR("failed to copy %d exec entries "
4080 "back to user (%d)\n",
4081 args
->buffer_count
, ret
);
4085 drm_free_large(exec_list
);
4086 drm_free_large(exec2_list
);
4091 i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
4092 struct drm_file
*file_priv
)
4094 struct drm_i915_gem_execbuffer2
*args
= data
;
4095 struct drm_i915_gem_exec_object2
*exec2_list
= NULL
;
4099 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
4100 (int) args
->buffers_ptr
, args
->buffer_count
, args
->batch_len
);
4103 if (args
->buffer_count
< 1) {
4104 DRM_ERROR("execbuf2 with %d buffers\n", args
->buffer_count
);
4108 exec2_list
= drm_malloc_ab(sizeof(*exec2_list
), args
->buffer_count
);
4109 if (exec2_list
== NULL
) {
4110 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
4111 args
->buffer_count
);
4114 ret
= copy_from_user(exec2_list
,
4115 (struct drm_i915_relocation_entry __user
*)
4116 (uintptr_t) args
->buffers_ptr
,
4117 sizeof(*exec2_list
) * args
->buffer_count
);
4119 DRM_ERROR("copy %d exec entries failed %d\n",
4120 args
->buffer_count
, ret
);
4121 drm_free_large(exec2_list
);
4125 ret
= i915_gem_do_execbuffer(dev
, data
, file_priv
, args
, exec2_list
);
4127 /* Copy the new buffer offsets back to the user's exec list. */
4128 ret
= copy_to_user((struct drm_i915_relocation_entry __user
*)
4129 (uintptr_t) args
->buffers_ptr
,
4131 sizeof(*exec2_list
) * args
->buffer_count
);
4134 DRM_ERROR("failed to copy %d exec entries "
4135 "back to user (%d)\n",
4136 args
->buffer_count
, ret
);
4140 drm_free_large(exec2_list
);
4145 i915_gem_object_pin(struct drm_gem_object
*obj
, uint32_t alignment
,
4146 bool map_and_fenceable
)
4148 struct drm_device
*dev
= obj
->dev
;
4149 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4150 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
4153 BUG_ON(obj_priv
->pin_count
== DRM_I915_GEM_OBJECT_MAX_PIN_COUNT
);
4154 BUG_ON(map_and_fenceable
&& !map_and_fenceable
);
4155 WARN_ON(i915_verify_lists(dev
));
4157 if (obj_priv
->gtt_space
!= NULL
) {
4158 if ((alignment
&& obj_priv
->gtt_offset
& (alignment
- 1)) ||
4159 (map_and_fenceable
&& !obj_priv
->map_and_fenceable
)) {
4160 WARN(obj_priv
->pin_count
,
4161 "bo is already pinned with incorrect alignment:"
4162 " offset=%x, req.alignment=%x, req.map_and_fenceable=%d,"
4163 " obj->map_and_fenceable=%d\n",
4164 obj_priv
->gtt_offset
, alignment
,
4166 obj_priv
->map_and_fenceable
);
4167 ret
= i915_gem_object_unbind(obj
);
4173 if (obj_priv
->gtt_space
== NULL
) {
4174 ret
= i915_gem_object_bind_to_gtt(obj
, alignment
,
4180 if (obj_priv
->pin_count
++ == 0) {
4181 i915_gem_info_add_pin(dev_priv
, obj_priv
, map_and_fenceable
);
4182 if (!obj_priv
->active
)
4183 list_move_tail(&obj_priv
->mm_list
,
4184 &dev_priv
->mm
.pinned_list
);
4186 BUG_ON(!obj_priv
->pin_mappable
&& map_and_fenceable
);
4188 WARN_ON(i915_verify_lists(dev
));
4193 i915_gem_object_unpin(struct drm_gem_object
*obj
)
4195 struct drm_device
*dev
= obj
->dev
;
4196 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4197 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
4199 WARN_ON(i915_verify_lists(dev
));
4200 BUG_ON(obj_priv
->pin_count
== 0);
4201 BUG_ON(obj_priv
->gtt_space
== NULL
);
4203 if (--obj_priv
->pin_count
== 0) {
4204 if (!obj_priv
->active
)
4205 list_move_tail(&obj_priv
->mm_list
,
4206 &dev_priv
->mm
.inactive_list
);
4207 i915_gem_info_remove_pin(dev_priv
, obj_priv
);
4209 WARN_ON(i915_verify_lists(dev
));
4213 i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
4214 struct drm_file
*file_priv
)
4216 struct drm_i915_gem_pin
*args
= data
;
4217 struct drm_gem_object
*obj
;
4218 struct drm_i915_gem_object
*obj_priv
;
4221 ret
= i915_mutex_lock_interruptible(dev
);
4225 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4230 obj_priv
= to_intel_bo(obj
);
4232 if (obj_priv
->madv
!= I915_MADV_WILLNEED
) {
4233 DRM_ERROR("Attempting to pin a purgeable buffer\n");
4238 if (obj_priv
->pin_filp
!= NULL
&& obj_priv
->pin_filp
!= file_priv
) {
4239 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
4245 obj_priv
->user_pin_count
++;
4246 obj_priv
->pin_filp
= file_priv
;
4247 if (obj_priv
->user_pin_count
== 1) {
4248 ret
= i915_gem_object_pin(obj
, args
->alignment
, true);
4253 /* XXX - flush the CPU caches for pinned objects
4254 * as the X server doesn't manage domains yet
4256 i915_gem_object_flush_cpu_write_domain(obj
);
4257 args
->offset
= obj_priv
->gtt_offset
;
4259 drm_gem_object_unreference(obj
);
4261 mutex_unlock(&dev
->struct_mutex
);
4266 i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
4267 struct drm_file
*file_priv
)
4269 struct drm_i915_gem_pin
*args
= data
;
4270 struct drm_gem_object
*obj
;
4271 struct drm_i915_gem_object
*obj_priv
;
4274 ret
= i915_mutex_lock_interruptible(dev
);
4278 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4283 obj_priv
= to_intel_bo(obj
);
4285 if (obj_priv
->pin_filp
!= file_priv
) {
4286 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4291 obj_priv
->user_pin_count
--;
4292 if (obj_priv
->user_pin_count
== 0) {
4293 obj_priv
->pin_filp
= NULL
;
4294 i915_gem_object_unpin(obj
);
4298 drm_gem_object_unreference(obj
);
4300 mutex_unlock(&dev
->struct_mutex
);
4305 i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
4306 struct drm_file
*file_priv
)
4308 struct drm_i915_gem_busy
*args
= data
;
4309 struct drm_gem_object
*obj
;
4310 struct drm_i915_gem_object
*obj_priv
;
4313 ret
= i915_mutex_lock_interruptible(dev
);
4317 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4322 obj_priv
= to_intel_bo(obj
);
4324 /* Count all active objects as busy, even if they are currently not used
4325 * by the gpu. Users of this interface expect objects to eventually
4326 * become non-busy without any further actions, therefore emit any
4327 * necessary flushes here.
4329 args
->busy
= obj_priv
->active
;
4331 /* Unconditionally flush objects, even when the gpu still uses this
4332 * object. Userspace calling this function indicates that it wants to
4333 * use this buffer rather sooner than later, so issuing the required
4334 * flush earlier is beneficial.
4336 if (obj
->write_domain
& I915_GEM_GPU_DOMAINS
)
4337 i915_gem_flush_ring(dev
, file_priv
,
4339 0, obj
->write_domain
);
4341 /* Update the active list for the hardware's current position.
4342 * Otherwise this only updates on a delayed timer or when irqs
4343 * are actually unmasked, and our working set ends up being
4344 * larger than required.
4346 i915_gem_retire_requests_ring(dev
, obj_priv
->ring
);
4348 args
->busy
= obj_priv
->active
;
4351 drm_gem_object_unreference(obj
);
4353 mutex_unlock(&dev
->struct_mutex
);
4358 i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
4359 struct drm_file
*file_priv
)
4361 return i915_gem_ring_throttle(dev
, file_priv
);
4365 i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
4366 struct drm_file
*file_priv
)
4368 struct drm_i915_gem_madvise
*args
= data
;
4369 struct drm_gem_object
*obj
;
4370 struct drm_i915_gem_object
*obj_priv
;
4373 switch (args
->madv
) {
4374 case I915_MADV_DONTNEED
:
4375 case I915_MADV_WILLNEED
:
4381 ret
= i915_mutex_lock_interruptible(dev
);
4385 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4390 obj_priv
= to_intel_bo(obj
);
4392 if (obj_priv
->pin_count
) {
4397 if (obj_priv
->madv
!= __I915_MADV_PURGED
)
4398 obj_priv
->madv
= args
->madv
;
4400 /* if the object is no longer bound, discard its backing storage */
4401 if (i915_gem_object_is_purgeable(obj_priv
) &&
4402 obj_priv
->gtt_space
== NULL
)
4403 i915_gem_object_truncate(obj
);
4405 args
->retained
= obj_priv
->madv
!= __I915_MADV_PURGED
;
4408 drm_gem_object_unreference(obj
);
4410 mutex_unlock(&dev
->struct_mutex
);
4414 struct drm_gem_object
* i915_gem_alloc_object(struct drm_device
*dev
,
4417 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4418 struct drm_i915_gem_object
*obj
;
4420 obj
= kzalloc(sizeof(*obj
), GFP_KERNEL
);
4424 if (drm_gem_object_init(dev
, &obj
->base
, size
) != 0) {
4429 i915_gem_info_add_obj(dev_priv
, size
);
4431 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
4432 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
4434 obj
->agp_type
= AGP_USER_MEMORY
;
4435 obj
->base
.driver_private
= NULL
;
4436 obj
->fence_reg
= I915_FENCE_REG_NONE
;
4437 INIT_LIST_HEAD(&obj
->mm_list
);
4438 INIT_LIST_HEAD(&obj
->ring_list
);
4439 INIT_LIST_HEAD(&obj
->gpu_write_list
);
4440 obj
->madv
= I915_MADV_WILLNEED
;
4441 /* Avoid an unnecessary call to unbind on the first bind. */
4442 obj
->map_and_fenceable
= true;
4447 int i915_gem_init_object(struct drm_gem_object
*obj
)
4454 static void i915_gem_free_object_tail(struct drm_gem_object
*obj
)
4456 struct drm_device
*dev
= obj
->dev
;
4457 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4458 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
4461 ret
= i915_gem_object_unbind(obj
);
4462 if (ret
== -ERESTARTSYS
) {
4463 list_move(&obj_priv
->mm_list
,
4464 &dev_priv
->mm
.deferred_free_list
);
4468 if (obj
->map_list
.map
)
4469 i915_gem_free_mmap_offset(obj
);
4471 drm_gem_object_release(obj
);
4472 i915_gem_info_remove_obj(dev_priv
, obj
->size
);
4474 kfree(obj_priv
->page_cpu_valid
);
4475 kfree(obj_priv
->bit_17
);
4479 void i915_gem_free_object(struct drm_gem_object
*obj
)
4481 struct drm_device
*dev
= obj
->dev
;
4482 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
4484 trace_i915_gem_object_destroy(obj
);
4486 while (obj_priv
->pin_count
> 0)
4487 i915_gem_object_unpin(obj
);
4489 if (obj_priv
->phys_obj
)
4490 i915_gem_detach_phys_object(dev
, obj
);
4492 i915_gem_free_object_tail(obj
);
4496 i915_gem_idle(struct drm_device
*dev
)
4498 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4501 mutex_lock(&dev
->struct_mutex
);
4503 if (dev_priv
->mm
.suspended
) {
4504 mutex_unlock(&dev
->struct_mutex
);
4508 ret
= i915_gpu_idle(dev
);
4510 mutex_unlock(&dev
->struct_mutex
);
4514 /* Under UMS, be paranoid and evict. */
4515 if (!drm_core_check_feature(dev
, DRIVER_MODESET
)) {
4516 ret
= i915_gem_evict_inactive(dev
, false);
4518 mutex_unlock(&dev
->struct_mutex
);
4523 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4524 * We need to replace this with a semaphore, or something.
4525 * And not confound mm.suspended!
4527 dev_priv
->mm
.suspended
= 1;
4528 del_timer_sync(&dev_priv
->hangcheck_timer
);
4530 i915_kernel_lost_context(dev
);
4531 i915_gem_cleanup_ringbuffer(dev
);
4533 mutex_unlock(&dev
->struct_mutex
);
4535 /* Cancel the retire work handler, which should be idle now. */
4536 cancel_delayed_work_sync(&dev_priv
->mm
.retire_work
);
4542 * 965+ support PIPE_CONTROL commands, which provide finer grained control
4543 * over cache flushing.
4546 i915_gem_init_pipe_control(struct drm_device
*dev
)
4548 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4549 struct drm_gem_object
*obj
;
4550 struct drm_i915_gem_object
*obj_priv
;
4553 obj
= i915_gem_alloc_object(dev
, 4096);
4555 DRM_ERROR("Failed to allocate seqno page\n");
4559 obj_priv
= to_intel_bo(obj
);
4560 obj_priv
->agp_type
= AGP_USER_CACHED_MEMORY
;
4562 ret
= i915_gem_object_pin(obj
, 4096, true);
4566 dev_priv
->seqno_gfx_addr
= obj_priv
->gtt_offset
;
4567 dev_priv
->seqno_page
= kmap(obj_priv
->pages
[0]);
4568 if (dev_priv
->seqno_page
== NULL
)
4571 dev_priv
->seqno_obj
= obj
;
4572 memset(dev_priv
->seqno_page
, 0, PAGE_SIZE
);
4577 i915_gem_object_unpin(obj
);
4579 drm_gem_object_unreference(obj
);
4586 i915_gem_cleanup_pipe_control(struct drm_device
*dev
)
4588 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4589 struct drm_gem_object
*obj
;
4590 struct drm_i915_gem_object
*obj_priv
;
4592 obj
= dev_priv
->seqno_obj
;
4593 obj_priv
= to_intel_bo(obj
);
4594 kunmap(obj_priv
->pages
[0]);
4595 i915_gem_object_unpin(obj
);
4596 drm_gem_object_unreference(obj
);
4597 dev_priv
->seqno_obj
= NULL
;
4599 dev_priv
->seqno_page
= NULL
;
4603 i915_gem_init_ringbuffer(struct drm_device
*dev
)
4605 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4608 if (HAS_PIPE_CONTROL(dev
)) {
4609 ret
= i915_gem_init_pipe_control(dev
);
4614 ret
= intel_init_render_ring_buffer(dev
);
4616 goto cleanup_pipe_control
;
4619 ret
= intel_init_bsd_ring_buffer(dev
);
4621 goto cleanup_render_ring
;
4625 ret
= intel_init_blt_ring_buffer(dev
);
4627 goto cleanup_bsd_ring
;
4630 dev_priv
->next_seqno
= 1;
4635 intel_cleanup_ring_buffer(&dev_priv
->bsd_ring
);
4636 cleanup_render_ring
:
4637 intel_cleanup_ring_buffer(&dev_priv
->render_ring
);
4638 cleanup_pipe_control
:
4639 if (HAS_PIPE_CONTROL(dev
))
4640 i915_gem_cleanup_pipe_control(dev
);
4645 i915_gem_cleanup_ringbuffer(struct drm_device
*dev
)
4647 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4649 intel_cleanup_ring_buffer(&dev_priv
->render_ring
);
4650 intel_cleanup_ring_buffer(&dev_priv
->bsd_ring
);
4651 intel_cleanup_ring_buffer(&dev_priv
->blt_ring
);
4652 if (HAS_PIPE_CONTROL(dev
))
4653 i915_gem_cleanup_pipe_control(dev
);
4657 i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
4658 struct drm_file
*file_priv
)
4660 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4663 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4666 if (atomic_read(&dev_priv
->mm
.wedged
)) {
4667 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4668 atomic_set(&dev_priv
->mm
.wedged
, 0);
4671 mutex_lock(&dev
->struct_mutex
);
4672 dev_priv
->mm
.suspended
= 0;
4674 ret
= i915_gem_init_ringbuffer(dev
);
4676 mutex_unlock(&dev
->struct_mutex
);
4680 BUG_ON(!list_empty(&dev_priv
->mm
.active_list
));
4681 BUG_ON(!list_empty(&dev_priv
->render_ring
.active_list
));
4682 BUG_ON(!list_empty(&dev_priv
->bsd_ring
.active_list
));
4683 BUG_ON(!list_empty(&dev_priv
->blt_ring
.active_list
));
4684 BUG_ON(!list_empty(&dev_priv
->mm
.flushing_list
));
4685 BUG_ON(!list_empty(&dev_priv
->mm
.inactive_list
));
4686 BUG_ON(!list_empty(&dev_priv
->render_ring
.request_list
));
4687 BUG_ON(!list_empty(&dev_priv
->bsd_ring
.request_list
));
4688 BUG_ON(!list_empty(&dev_priv
->blt_ring
.request_list
));
4689 mutex_unlock(&dev
->struct_mutex
);
4691 ret
= drm_irq_install(dev
);
4693 goto cleanup_ringbuffer
;
4698 mutex_lock(&dev
->struct_mutex
);
4699 i915_gem_cleanup_ringbuffer(dev
);
4700 dev_priv
->mm
.suspended
= 1;
4701 mutex_unlock(&dev
->struct_mutex
);
4707 i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
4708 struct drm_file
*file_priv
)
4710 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4713 drm_irq_uninstall(dev
);
4714 return i915_gem_idle(dev
);
4718 i915_gem_lastclose(struct drm_device
*dev
)
4722 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4725 ret
= i915_gem_idle(dev
);
4727 DRM_ERROR("failed to idle hardware: %d\n", ret
);
4731 init_ring_lists(struct intel_ring_buffer
*ring
)
4733 INIT_LIST_HEAD(&ring
->active_list
);
4734 INIT_LIST_HEAD(&ring
->request_list
);
4735 INIT_LIST_HEAD(&ring
->gpu_write_list
);
4739 i915_gem_load(struct drm_device
*dev
)
4742 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4744 INIT_LIST_HEAD(&dev_priv
->mm
.active_list
);
4745 INIT_LIST_HEAD(&dev_priv
->mm
.flushing_list
);
4746 INIT_LIST_HEAD(&dev_priv
->mm
.inactive_list
);
4747 INIT_LIST_HEAD(&dev_priv
->mm
.pinned_list
);
4748 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
4749 INIT_LIST_HEAD(&dev_priv
->mm
.deferred_free_list
);
4750 init_ring_lists(&dev_priv
->render_ring
);
4751 init_ring_lists(&dev_priv
->bsd_ring
);
4752 init_ring_lists(&dev_priv
->blt_ring
);
4753 for (i
= 0; i
< 16; i
++)
4754 INIT_LIST_HEAD(&dev_priv
->fence_regs
[i
].lru_list
);
4755 INIT_DELAYED_WORK(&dev_priv
->mm
.retire_work
,
4756 i915_gem_retire_work_handler
);
4757 init_completion(&dev_priv
->error_completion
);
4759 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4761 u32 tmp
= I915_READ(MI_ARB_STATE
);
4762 if (!(tmp
& MI_ARB_C3_LP_WRITE_ENABLE
)) {
4763 /* arb state is a masked write, so set bit + bit in mask */
4764 tmp
= MI_ARB_C3_LP_WRITE_ENABLE
| (MI_ARB_C3_LP_WRITE_ENABLE
<< MI_ARB_MASK_SHIFT
);
4765 I915_WRITE(MI_ARB_STATE
, tmp
);
4769 /* Old X drivers will take 0-2 for front, back, depth buffers */
4770 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
4771 dev_priv
->fence_reg_start
= 3;
4773 if (INTEL_INFO(dev
)->gen
>= 4 || IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
4774 dev_priv
->num_fence_regs
= 16;
4776 dev_priv
->num_fence_regs
= 8;
4778 /* Initialize fence registers to zero */
4779 switch (INTEL_INFO(dev
)->gen
) {
4781 for (i
= 0; i
< 16; i
++)
4782 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0
+ (i
* 8), 0);
4786 for (i
= 0; i
< 16; i
++)
4787 I915_WRITE64(FENCE_REG_965_0
+ (i
* 8), 0);
4790 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
4791 for (i
= 0; i
< 8; i
++)
4792 I915_WRITE(FENCE_REG_945_8
+ (i
* 4), 0);
4794 for (i
= 0; i
< 8; i
++)
4795 I915_WRITE(FENCE_REG_830_0
+ (i
* 4), 0);
4798 i915_gem_detect_bit_6_swizzle(dev
);
4799 init_waitqueue_head(&dev_priv
->pending_flip_queue
);
4801 dev_priv
->mm
.inactive_shrinker
.shrink
= i915_gem_inactive_shrink
;
4802 dev_priv
->mm
.inactive_shrinker
.seeks
= DEFAULT_SEEKS
;
4803 register_shrinker(&dev_priv
->mm
.inactive_shrinker
);
4807 * Create a physically contiguous memory object for this object
4808 * e.g. for cursor + overlay regs
4810 static int i915_gem_init_phys_object(struct drm_device
*dev
,
4811 int id
, int size
, int align
)
4813 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4814 struct drm_i915_gem_phys_object
*phys_obj
;
4817 if (dev_priv
->mm
.phys_objs
[id
- 1] || !size
)
4820 phys_obj
= kzalloc(sizeof(struct drm_i915_gem_phys_object
), GFP_KERNEL
);
4826 phys_obj
->handle
= drm_pci_alloc(dev
, size
, align
);
4827 if (!phys_obj
->handle
) {
4832 set_memory_wc((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
4835 dev_priv
->mm
.phys_objs
[id
- 1] = phys_obj
;
4843 static void i915_gem_free_phys_object(struct drm_device
*dev
, int id
)
4845 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4846 struct drm_i915_gem_phys_object
*phys_obj
;
4848 if (!dev_priv
->mm
.phys_objs
[id
- 1])
4851 phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
4852 if (phys_obj
->cur_obj
) {
4853 i915_gem_detach_phys_object(dev
, phys_obj
->cur_obj
);
4857 set_memory_wb((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
4859 drm_pci_free(dev
, phys_obj
->handle
);
4861 dev_priv
->mm
.phys_objs
[id
- 1] = NULL
;
4864 void i915_gem_free_all_phys_object(struct drm_device
*dev
)
4868 for (i
= I915_GEM_PHYS_CURSOR_0
; i
<= I915_MAX_PHYS_OBJECT
; i
++)
4869 i915_gem_free_phys_object(dev
, i
);
4872 void i915_gem_detach_phys_object(struct drm_device
*dev
,
4873 struct drm_gem_object
*obj
)
4875 struct address_space
*mapping
= obj
->filp
->f_path
.dentry
->d_inode
->i_mapping
;
4876 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
4881 if (!obj_priv
->phys_obj
)
4883 vaddr
= obj_priv
->phys_obj
->handle
->vaddr
;
4885 page_count
= obj
->size
/ PAGE_SIZE
;
4887 for (i
= 0; i
< page_count
; i
++) {
4888 struct page
*page
= read_cache_page_gfp(mapping
, i
,
4889 GFP_HIGHUSER
| __GFP_RECLAIMABLE
);
4890 if (!IS_ERR(page
)) {
4891 char *dst
= kmap_atomic(page
);
4892 memcpy(dst
, vaddr
+ i
*PAGE_SIZE
, PAGE_SIZE
);
4895 drm_clflush_pages(&page
, 1);
4897 set_page_dirty(page
);
4898 mark_page_accessed(page
);
4899 page_cache_release(page
);
4902 drm_agp_chipset_flush(dev
);
4904 obj_priv
->phys_obj
->cur_obj
= NULL
;
4905 obj_priv
->phys_obj
= NULL
;
4909 i915_gem_attach_phys_object(struct drm_device
*dev
,
4910 struct drm_gem_object
*obj
,
4914 struct address_space
*mapping
= obj
->filp
->f_path
.dentry
->d_inode
->i_mapping
;
4915 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4916 struct drm_i915_gem_object
*obj_priv
;
4921 if (id
> I915_MAX_PHYS_OBJECT
)
4924 obj_priv
= to_intel_bo(obj
);
4926 if (obj_priv
->phys_obj
) {
4927 if (obj_priv
->phys_obj
->id
== id
)
4929 i915_gem_detach_phys_object(dev
, obj
);
4932 /* create a new object */
4933 if (!dev_priv
->mm
.phys_objs
[id
- 1]) {
4934 ret
= i915_gem_init_phys_object(dev
, id
,
4937 DRM_ERROR("failed to init phys object %d size: %zu\n", id
, obj
->size
);
4942 /* bind to the object */
4943 obj_priv
->phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
4944 obj_priv
->phys_obj
->cur_obj
= obj
;
4946 page_count
= obj
->size
/ PAGE_SIZE
;
4948 for (i
= 0; i
< page_count
; i
++) {
4952 page
= read_cache_page_gfp(mapping
, i
,
4953 GFP_HIGHUSER
| __GFP_RECLAIMABLE
);
4955 return PTR_ERR(page
);
4957 src
= kmap_atomic(page
);
4958 dst
= obj_priv
->phys_obj
->handle
->vaddr
+ (i
* PAGE_SIZE
);
4959 memcpy(dst
, src
, PAGE_SIZE
);
4962 mark_page_accessed(page
);
4963 page_cache_release(page
);
4970 i915_gem_phys_pwrite(struct drm_device
*dev
, struct drm_gem_object
*obj
,
4971 struct drm_i915_gem_pwrite
*args
,
4972 struct drm_file
*file_priv
)
4974 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
4977 char __user
*user_data
;
4979 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
4980 obj_addr
= obj_priv
->phys_obj
->handle
->vaddr
+ args
->offset
;
4982 DRM_DEBUG_DRIVER("obj_addr %p, %lld\n", obj_addr
, args
->size
);
4983 ret
= copy_from_user(obj_addr
, user_data
, args
->size
);
4987 drm_agp_chipset_flush(dev
);
4991 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
)
4993 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
4995 /* Clean up our request list when the client is going away, so that
4996 * later retire_requests won't dereference our soon-to-be-gone
4999 spin_lock(&file_priv
->mm
.lock
);
5000 while (!list_empty(&file_priv
->mm
.request_list
)) {
5001 struct drm_i915_gem_request
*request
;
5003 request
= list_first_entry(&file_priv
->mm
.request_list
,
5004 struct drm_i915_gem_request
,
5006 list_del(&request
->client_list
);
5007 request
->file_priv
= NULL
;
5009 spin_unlock(&file_priv
->mm
.lock
);
5013 i915_gpu_is_active(struct drm_device
*dev
)
5015 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
5018 lists_empty
= list_empty(&dev_priv
->mm
.flushing_list
) &&
5019 list_empty(&dev_priv
->mm
.active_list
);
5021 return !lists_empty
;
5025 i915_gem_inactive_shrink(struct shrinker
*shrinker
,
5029 struct drm_i915_private
*dev_priv
=
5030 container_of(shrinker
,
5031 struct drm_i915_private
,
5032 mm
.inactive_shrinker
);
5033 struct drm_device
*dev
= dev_priv
->dev
;
5034 struct drm_i915_gem_object
*obj
, *next
;
5037 if (!mutex_trylock(&dev
->struct_mutex
))
5040 /* "fast-path" to count number of available objects */
5041 if (nr_to_scan
== 0) {
5043 list_for_each_entry(obj
,
5044 &dev_priv
->mm
.inactive_list
,
5047 mutex_unlock(&dev
->struct_mutex
);
5048 return cnt
/ 100 * sysctl_vfs_cache_pressure
;
5052 /* first scan for clean buffers */
5053 i915_gem_retire_requests(dev
);
5055 list_for_each_entry_safe(obj
, next
,
5056 &dev_priv
->mm
.inactive_list
,
5058 if (i915_gem_object_is_purgeable(obj
)) {
5059 i915_gem_object_unbind(&obj
->base
);
5060 if (--nr_to_scan
== 0)
5065 /* second pass, evict/count anything still on the inactive list */
5067 list_for_each_entry_safe(obj
, next
,
5068 &dev_priv
->mm
.inactive_list
,
5071 i915_gem_object_unbind(&obj
->base
);
5077 if (nr_to_scan
&& i915_gpu_is_active(dev
)) {
5079 * We are desperate for pages, so as a last resort, wait
5080 * for the GPU to finish and discard whatever we can.
5081 * This has a dramatic impact to reduce the number of
5082 * OOM-killer events whilst running the GPU aggressively.
5084 if (i915_gpu_idle(dev
) == 0)
5087 mutex_unlock(&dev
->struct_mutex
);
5088 return cnt
/ 100 * sysctl_vfs_cache_pressure
;