2 * Copyright © 2008-2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/drm_vma_manager.h>
30 #include <drm/i915_drm.h>
32 #include "i915_vgpu.h"
33 #include "i915_trace.h"
34 #include "intel_drv.h"
35 #include "intel_mocs.h"
36 #include <linux/shmem_fs.h>
37 #include <linux/slab.h>
38 #include <linux/swap.h>
39 #include <linux/pci.h>
40 #include <linux/dma-buf.h>
42 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
);
43 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
);
45 i915_gem_object_retire__write(struct drm_i915_gem_object
*obj
);
47 i915_gem_object_retire__read(struct drm_i915_gem_object
*obj
, int ring
);
49 static bool cpu_cache_is_coherent(struct drm_device
*dev
,
50 enum i915_cache_level level
)
52 return HAS_LLC(dev
) || level
!= I915_CACHE_NONE
;
55 static bool cpu_write_needs_clflush(struct drm_i915_gem_object
*obj
)
57 if (!cpu_cache_is_coherent(obj
->base
.dev
, obj
->cache_level
))
60 return obj
->pin_display
;
63 /* some bookkeeping */
64 static void i915_gem_info_add_obj(struct drm_i915_private
*dev_priv
,
67 spin_lock(&dev_priv
->mm
.object_stat_lock
);
68 dev_priv
->mm
.object_count
++;
69 dev_priv
->mm
.object_memory
+= size
;
70 spin_unlock(&dev_priv
->mm
.object_stat_lock
);
73 static void i915_gem_info_remove_obj(struct drm_i915_private
*dev_priv
,
76 spin_lock(&dev_priv
->mm
.object_stat_lock
);
77 dev_priv
->mm
.object_count
--;
78 dev_priv
->mm
.object_memory
-= size
;
79 spin_unlock(&dev_priv
->mm
.object_stat_lock
);
83 i915_gem_wait_for_error(struct i915_gpu_error
*error
)
87 if (!i915_reset_in_progress(error
))
91 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
92 * userspace. If it takes that long something really bad is going on and
93 * we should simply try to bail out and fail as gracefully as possible.
95 ret
= wait_event_interruptible_timeout(error
->reset_queue
,
96 !i915_reset_in_progress(error
),
99 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
101 } else if (ret
< 0) {
108 int i915_mutex_lock_interruptible(struct drm_device
*dev
)
110 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
113 ret
= i915_gem_wait_for_error(&dev_priv
->gpu_error
);
117 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
121 WARN_ON(i915_verify_lists(dev
));
126 i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
127 struct drm_file
*file
)
129 struct drm_i915_private
*dev_priv
= to_i915(dev
);
130 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
131 struct drm_i915_gem_get_aperture
*args
= data
;
132 struct i915_vma
*vma
;
136 mutex_lock(&dev
->struct_mutex
);
137 list_for_each_entry(vma
, &ggtt
->base
.active_list
, vm_link
)
139 pinned
+= vma
->node
.size
;
140 list_for_each_entry(vma
, &ggtt
->base
.inactive_list
, vm_link
)
142 pinned
+= vma
->node
.size
;
143 mutex_unlock(&dev
->struct_mutex
);
145 args
->aper_size
= ggtt
->base
.total
;
146 args
->aper_available_size
= args
->aper_size
- pinned
;
152 i915_gem_object_get_pages_phys(struct drm_i915_gem_object
*obj
)
154 struct address_space
*mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
155 char *vaddr
= obj
->phys_handle
->vaddr
;
157 struct scatterlist
*sg
;
160 if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj
)))
163 for (i
= 0; i
< obj
->base
.size
/ PAGE_SIZE
; i
++) {
167 page
= shmem_read_mapping_page(mapping
, i
);
169 return PTR_ERR(page
);
171 src
= kmap_atomic(page
);
172 memcpy(vaddr
, src
, PAGE_SIZE
);
173 drm_clflush_virt_range(vaddr
, PAGE_SIZE
);
180 i915_gem_chipset_flush(obj
->base
.dev
);
182 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
186 if (sg_alloc_table(st
, 1, GFP_KERNEL
)) {
193 sg
->length
= obj
->base
.size
;
195 sg_dma_address(sg
) = obj
->phys_handle
->busaddr
;
196 sg_dma_len(sg
) = obj
->base
.size
;
203 i915_gem_object_put_pages_phys(struct drm_i915_gem_object
*obj
)
207 BUG_ON(obj
->madv
== __I915_MADV_PURGED
);
209 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
211 /* In the event of a disaster, abandon all caches and
214 obj
->base
.read_domains
= obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
217 if (obj
->madv
== I915_MADV_DONTNEED
)
221 struct address_space
*mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
222 char *vaddr
= obj
->phys_handle
->vaddr
;
225 for (i
= 0; i
< obj
->base
.size
/ PAGE_SIZE
; i
++) {
229 page
= shmem_read_mapping_page(mapping
, i
);
233 dst
= kmap_atomic(page
);
234 drm_clflush_virt_range(vaddr
, PAGE_SIZE
);
235 memcpy(dst
, vaddr
, PAGE_SIZE
);
238 set_page_dirty(page
);
239 if (obj
->madv
== I915_MADV_WILLNEED
)
240 mark_page_accessed(page
);
247 sg_free_table(obj
->pages
);
252 i915_gem_object_release_phys(struct drm_i915_gem_object
*obj
)
254 drm_pci_free(obj
->base
.dev
, obj
->phys_handle
);
257 static const struct drm_i915_gem_object_ops i915_gem_phys_ops
= {
258 .get_pages
= i915_gem_object_get_pages_phys
,
259 .put_pages
= i915_gem_object_put_pages_phys
,
260 .release
= i915_gem_object_release_phys
,
264 drop_pages(struct drm_i915_gem_object
*obj
)
266 struct i915_vma
*vma
, *next
;
269 drm_gem_object_reference(&obj
->base
);
270 list_for_each_entry_safe(vma
, next
, &obj
->vma_list
, obj_link
)
271 if (i915_vma_unbind(vma
))
274 ret
= i915_gem_object_put_pages(obj
);
275 drm_gem_object_unreference(&obj
->base
);
281 i915_gem_object_attach_phys(struct drm_i915_gem_object
*obj
,
284 drm_dma_handle_t
*phys
;
287 if (obj
->phys_handle
) {
288 if ((unsigned long)obj
->phys_handle
->vaddr
& (align
-1))
294 if (obj
->madv
!= I915_MADV_WILLNEED
)
297 if (obj
->base
.filp
== NULL
)
300 ret
= drop_pages(obj
);
304 /* create a new object */
305 phys
= drm_pci_alloc(obj
->base
.dev
, obj
->base
.size
, align
);
309 obj
->phys_handle
= phys
;
310 obj
->ops
= &i915_gem_phys_ops
;
312 return i915_gem_object_get_pages(obj
);
316 i915_gem_phys_pwrite(struct drm_i915_gem_object
*obj
,
317 struct drm_i915_gem_pwrite
*args
,
318 struct drm_file
*file_priv
)
320 struct drm_device
*dev
= obj
->base
.dev
;
321 void *vaddr
= obj
->phys_handle
->vaddr
+ args
->offset
;
322 char __user
*user_data
= u64_to_user_ptr(args
->data_ptr
);
325 /* We manually control the domain here and pretend that it
326 * remains coherent i.e. in the GTT domain, like shmem_pwrite.
328 ret
= i915_gem_object_wait_rendering(obj
, false);
332 intel_fb_obj_invalidate(obj
, ORIGIN_CPU
);
333 if (__copy_from_user_inatomic_nocache(vaddr
, user_data
, args
->size
)) {
334 unsigned long unwritten
;
336 /* The physical object once assigned is fixed for the lifetime
337 * of the obj, so we can safely drop the lock and continue
340 mutex_unlock(&dev
->struct_mutex
);
341 unwritten
= copy_from_user(vaddr
, user_data
, args
->size
);
342 mutex_lock(&dev
->struct_mutex
);
349 drm_clflush_virt_range(vaddr
, args
->size
);
350 i915_gem_chipset_flush(dev
);
353 intel_fb_obj_flush(obj
, false, ORIGIN_CPU
);
357 void *i915_gem_object_alloc(struct drm_device
*dev
)
359 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
360 return kmem_cache_zalloc(dev_priv
->objects
, GFP_KERNEL
);
363 void i915_gem_object_free(struct drm_i915_gem_object
*obj
)
365 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
366 kmem_cache_free(dev_priv
->objects
, obj
);
370 i915_gem_create(struct drm_file
*file
,
371 struct drm_device
*dev
,
375 struct drm_i915_gem_object
*obj
;
379 size
= roundup(size
, PAGE_SIZE
);
383 /* Allocate the new object */
384 obj
= i915_gem_alloc_object(dev
, size
);
388 ret
= drm_gem_handle_create(file
, &obj
->base
, &handle
);
389 /* drop reference from allocate - handle holds it now */
390 drm_gem_object_unreference_unlocked(&obj
->base
);
399 i915_gem_dumb_create(struct drm_file
*file
,
400 struct drm_device
*dev
,
401 struct drm_mode_create_dumb
*args
)
403 /* have to work out size/pitch and return them */
404 args
->pitch
= ALIGN(args
->width
* DIV_ROUND_UP(args
->bpp
, 8), 64);
405 args
->size
= args
->pitch
* args
->height
;
406 return i915_gem_create(file
, dev
,
407 args
->size
, &args
->handle
);
411 * Creates a new mm object and returns a handle to it.
414 i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
415 struct drm_file
*file
)
417 struct drm_i915_gem_create
*args
= data
;
419 return i915_gem_create(file
, dev
,
420 args
->size
, &args
->handle
);
424 __copy_to_user_swizzled(char __user
*cpu_vaddr
,
425 const char *gpu_vaddr
, int gpu_offset
,
428 int ret
, cpu_offset
= 0;
431 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
432 int this_length
= min(cacheline_end
- gpu_offset
, length
);
433 int swizzled_gpu_offset
= gpu_offset
^ 64;
435 ret
= __copy_to_user(cpu_vaddr
+ cpu_offset
,
436 gpu_vaddr
+ swizzled_gpu_offset
,
441 cpu_offset
+= this_length
;
442 gpu_offset
+= this_length
;
443 length
-= this_length
;
450 __copy_from_user_swizzled(char *gpu_vaddr
, int gpu_offset
,
451 const char __user
*cpu_vaddr
,
454 int ret
, cpu_offset
= 0;
457 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
458 int this_length
= min(cacheline_end
- gpu_offset
, length
);
459 int swizzled_gpu_offset
= gpu_offset
^ 64;
461 ret
= __copy_from_user(gpu_vaddr
+ swizzled_gpu_offset
,
462 cpu_vaddr
+ cpu_offset
,
467 cpu_offset
+= this_length
;
468 gpu_offset
+= this_length
;
469 length
-= this_length
;
476 * Pins the specified object's pages and synchronizes the object with
477 * GPU accesses. Sets needs_clflush to non-zero if the caller should
478 * flush the object from the CPU cache.
480 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object
*obj
,
487 if (WARN_ON((obj
->ops
->flags
& I915_GEM_OBJECT_HAS_STRUCT_PAGE
) == 0))
490 if (!(obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
)) {
491 /* If we're not in the cpu read domain, set ourself into the gtt
492 * read domain and manually flush cachelines (if required). This
493 * optimizes for the case when the gpu will dirty the data
494 * anyway again before the next pread happens. */
495 *needs_clflush
= !cpu_cache_is_coherent(obj
->base
.dev
,
497 ret
= i915_gem_object_wait_rendering(obj
, true);
502 ret
= i915_gem_object_get_pages(obj
);
506 i915_gem_object_pin_pages(obj
);
511 /* Per-page copy function for the shmem pread fastpath.
512 * Flushes invalid cachelines before reading the target if
513 * needs_clflush is set. */
515 shmem_pread_fast(struct page
*page
, int shmem_page_offset
, int page_length
,
516 char __user
*user_data
,
517 bool page_do_bit17_swizzling
, bool needs_clflush
)
522 if (unlikely(page_do_bit17_swizzling
))
525 vaddr
= kmap_atomic(page
);
527 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
529 ret
= __copy_to_user_inatomic(user_data
,
530 vaddr
+ shmem_page_offset
,
532 kunmap_atomic(vaddr
);
534 return ret
? -EFAULT
: 0;
538 shmem_clflush_swizzled_range(char *addr
, unsigned long length
,
541 if (unlikely(swizzled
)) {
542 unsigned long start
= (unsigned long) addr
;
543 unsigned long end
= (unsigned long) addr
+ length
;
545 /* For swizzling simply ensure that we always flush both
546 * channels. Lame, but simple and it works. Swizzled
547 * pwrite/pread is far from a hotpath - current userspace
548 * doesn't use it at all. */
549 start
= round_down(start
, 128);
550 end
= round_up(end
, 128);
552 drm_clflush_virt_range((void *)start
, end
- start
);
554 drm_clflush_virt_range(addr
, length
);
559 /* Only difference to the fast-path function is that this can handle bit17
560 * and uses non-atomic copy and kmap functions. */
562 shmem_pread_slow(struct page
*page
, int shmem_page_offset
, int page_length
,
563 char __user
*user_data
,
564 bool page_do_bit17_swizzling
, bool needs_clflush
)
571 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
573 page_do_bit17_swizzling
);
575 if (page_do_bit17_swizzling
)
576 ret
= __copy_to_user_swizzled(user_data
,
577 vaddr
, shmem_page_offset
,
580 ret
= __copy_to_user(user_data
,
581 vaddr
+ shmem_page_offset
,
585 return ret
? - EFAULT
: 0;
589 i915_gem_shmem_pread(struct drm_device
*dev
,
590 struct drm_i915_gem_object
*obj
,
591 struct drm_i915_gem_pread
*args
,
592 struct drm_file
*file
)
594 char __user
*user_data
;
597 int shmem_page_offset
, page_length
, ret
= 0;
598 int obj_do_bit17_swizzling
, page_do_bit17_swizzling
;
600 int needs_clflush
= 0;
601 struct sg_page_iter sg_iter
;
603 user_data
= u64_to_user_ptr(args
->data_ptr
);
606 obj_do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
608 ret
= i915_gem_obj_prepare_shmem_read(obj
, &needs_clflush
);
612 offset
= args
->offset
;
614 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
,
615 offset
>> PAGE_SHIFT
) {
616 struct page
*page
= sg_page_iter_page(&sg_iter
);
621 /* Operation in this page
623 * shmem_page_offset = offset within page in shmem file
624 * page_length = bytes to copy for this page
626 shmem_page_offset
= offset_in_page(offset
);
627 page_length
= remain
;
628 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
629 page_length
= PAGE_SIZE
- shmem_page_offset
;
631 page_do_bit17_swizzling
= obj_do_bit17_swizzling
&&
632 (page_to_phys(page
) & (1 << 17)) != 0;
634 ret
= shmem_pread_fast(page
, shmem_page_offset
, page_length
,
635 user_data
, page_do_bit17_swizzling
,
640 mutex_unlock(&dev
->struct_mutex
);
642 if (likely(!i915
.prefault_disable
) && !prefaulted
) {
643 ret
= fault_in_multipages_writeable(user_data
, remain
);
644 /* Userspace is tricking us, but we've already clobbered
645 * its pages with the prefault and promised to write the
646 * data up to the first fault. Hence ignore any errors
647 * and just continue. */
652 ret
= shmem_pread_slow(page
, shmem_page_offset
, page_length
,
653 user_data
, page_do_bit17_swizzling
,
656 mutex_lock(&dev
->struct_mutex
);
662 remain
-= page_length
;
663 user_data
+= page_length
;
664 offset
+= page_length
;
668 i915_gem_object_unpin_pages(obj
);
674 * Reads data from the object referenced by handle.
676 * On error, the contents of *data are undefined.
679 i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
680 struct drm_file
*file
)
682 struct drm_i915_gem_pread
*args
= data
;
683 struct drm_i915_gem_object
*obj
;
689 if (!access_ok(VERIFY_WRITE
,
690 u64_to_user_ptr(args
->data_ptr
),
694 ret
= i915_mutex_lock_interruptible(dev
);
698 obj
= to_intel_bo(drm_gem_object_lookup(file
, args
->handle
));
699 if (&obj
->base
== NULL
) {
704 /* Bounds check source. */
705 if (args
->offset
> obj
->base
.size
||
706 args
->size
> obj
->base
.size
- args
->offset
) {
711 /* prime objects have no backing filp to GEM pread/pwrite
714 if (!obj
->base
.filp
) {
719 trace_i915_gem_object_pread(obj
, args
->offset
, args
->size
);
721 ret
= i915_gem_shmem_pread(dev
, obj
, args
, file
);
724 drm_gem_object_unreference(&obj
->base
);
726 mutex_unlock(&dev
->struct_mutex
);
730 /* This is the fast write path which cannot handle
731 * page faults in the source data
735 fast_user_write(struct io_mapping
*mapping
,
736 loff_t page_base
, int page_offset
,
737 char __user
*user_data
,
740 void __iomem
*vaddr_atomic
;
742 unsigned long unwritten
;
744 vaddr_atomic
= io_mapping_map_atomic_wc(mapping
, page_base
);
745 /* We can use the cpu mem copy function because this is X86. */
746 vaddr
= (void __force
*)vaddr_atomic
+ page_offset
;
747 unwritten
= __copy_from_user_inatomic_nocache(vaddr
,
749 io_mapping_unmap_atomic(vaddr_atomic
);
754 * This is the fast pwrite path, where we copy the data directly from the
755 * user into the GTT, uncached.
758 i915_gem_gtt_pwrite_fast(struct drm_device
*dev
,
759 struct drm_i915_gem_object
*obj
,
760 struct drm_i915_gem_pwrite
*args
,
761 struct drm_file
*file
)
763 struct drm_i915_private
*dev_priv
= to_i915(dev
);
764 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
766 loff_t offset
, page_base
;
767 char __user
*user_data
;
768 int page_offset
, page_length
, ret
;
770 ret
= i915_gem_obj_ggtt_pin(obj
, 0, PIN_MAPPABLE
| PIN_NONBLOCK
);
774 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
778 ret
= i915_gem_object_put_fence(obj
);
782 user_data
= u64_to_user_ptr(args
->data_ptr
);
785 offset
= i915_gem_obj_ggtt_offset(obj
) + args
->offset
;
787 intel_fb_obj_invalidate(obj
, ORIGIN_GTT
);
790 /* Operation in this page
792 * page_base = page offset within aperture
793 * page_offset = offset within page
794 * page_length = bytes to copy for this page
796 page_base
= offset
& PAGE_MASK
;
797 page_offset
= offset_in_page(offset
);
798 page_length
= remain
;
799 if ((page_offset
+ remain
) > PAGE_SIZE
)
800 page_length
= PAGE_SIZE
- page_offset
;
802 /* If we get a fault while copying data, then (presumably) our
803 * source page isn't available. Return the error and we'll
804 * retry in the slow path.
806 if (fast_user_write(ggtt
->mappable
, page_base
,
807 page_offset
, user_data
, page_length
)) {
812 remain
-= page_length
;
813 user_data
+= page_length
;
814 offset
+= page_length
;
818 intel_fb_obj_flush(obj
, false, ORIGIN_GTT
);
820 i915_gem_object_ggtt_unpin(obj
);
825 /* Per-page copy function for the shmem pwrite fastpath.
826 * Flushes invalid cachelines before writing to the target if
827 * needs_clflush_before is set and flushes out any written cachelines after
828 * writing if needs_clflush is set. */
830 shmem_pwrite_fast(struct page
*page
, int shmem_page_offset
, int page_length
,
831 char __user
*user_data
,
832 bool page_do_bit17_swizzling
,
833 bool needs_clflush_before
,
834 bool needs_clflush_after
)
839 if (unlikely(page_do_bit17_swizzling
))
842 vaddr
= kmap_atomic(page
);
843 if (needs_clflush_before
)
844 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
846 ret
= __copy_from_user_inatomic(vaddr
+ shmem_page_offset
,
847 user_data
, page_length
);
848 if (needs_clflush_after
)
849 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
851 kunmap_atomic(vaddr
);
853 return ret
? -EFAULT
: 0;
856 /* Only difference to the fast-path function is that this can handle bit17
857 * and uses non-atomic copy and kmap functions. */
859 shmem_pwrite_slow(struct page
*page
, int shmem_page_offset
, int page_length
,
860 char __user
*user_data
,
861 bool page_do_bit17_swizzling
,
862 bool needs_clflush_before
,
863 bool needs_clflush_after
)
869 if (unlikely(needs_clflush_before
|| page_do_bit17_swizzling
))
870 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
872 page_do_bit17_swizzling
);
873 if (page_do_bit17_swizzling
)
874 ret
= __copy_from_user_swizzled(vaddr
, shmem_page_offset
,
878 ret
= __copy_from_user(vaddr
+ shmem_page_offset
,
881 if (needs_clflush_after
)
882 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
884 page_do_bit17_swizzling
);
887 return ret
? -EFAULT
: 0;
891 i915_gem_shmem_pwrite(struct drm_device
*dev
,
892 struct drm_i915_gem_object
*obj
,
893 struct drm_i915_gem_pwrite
*args
,
894 struct drm_file
*file
)
898 char __user
*user_data
;
899 int shmem_page_offset
, page_length
, ret
= 0;
900 int obj_do_bit17_swizzling
, page_do_bit17_swizzling
;
901 int hit_slowpath
= 0;
902 int needs_clflush_after
= 0;
903 int needs_clflush_before
= 0;
904 struct sg_page_iter sg_iter
;
906 user_data
= u64_to_user_ptr(args
->data_ptr
);
909 obj_do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
911 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
912 /* If we're not in the cpu write domain, set ourself into the gtt
913 * write domain and manually flush cachelines (if required). This
914 * optimizes for the case when the gpu will use the data
915 * right away and we therefore have to clflush anyway. */
916 needs_clflush_after
= cpu_write_needs_clflush(obj
);
917 ret
= i915_gem_object_wait_rendering(obj
, false);
921 /* Same trick applies to invalidate partially written cachelines read
923 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) == 0)
924 needs_clflush_before
=
925 !cpu_cache_is_coherent(dev
, obj
->cache_level
);
927 ret
= i915_gem_object_get_pages(obj
);
931 intel_fb_obj_invalidate(obj
, ORIGIN_CPU
);
933 i915_gem_object_pin_pages(obj
);
935 offset
= args
->offset
;
938 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
,
939 offset
>> PAGE_SHIFT
) {
940 struct page
*page
= sg_page_iter_page(&sg_iter
);
941 int partial_cacheline_write
;
946 /* Operation in this page
948 * shmem_page_offset = offset within page in shmem file
949 * page_length = bytes to copy for this page
951 shmem_page_offset
= offset_in_page(offset
);
953 page_length
= remain
;
954 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
955 page_length
= PAGE_SIZE
- shmem_page_offset
;
957 /* If we don't overwrite a cacheline completely we need to be
958 * careful to have up-to-date data by first clflushing. Don't
959 * overcomplicate things and flush the entire patch. */
960 partial_cacheline_write
= needs_clflush_before
&&
961 ((shmem_page_offset
| page_length
)
962 & (boot_cpu_data
.x86_clflush_size
- 1));
964 page_do_bit17_swizzling
= obj_do_bit17_swizzling
&&
965 (page_to_phys(page
) & (1 << 17)) != 0;
967 ret
= shmem_pwrite_fast(page
, shmem_page_offset
, page_length
,
968 user_data
, page_do_bit17_swizzling
,
969 partial_cacheline_write
,
970 needs_clflush_after
);
975 mutex_unlock(&dev
->struct_mutex
);
976 ret
= shmem_pwrite_slow(page
, shmem_page_offset
, page_length
,
977 user_data
, page_do_bit17_swizzling
,
978 partial_cacheline_write
,
979 needs_clflush_after
);
981 mutex_lock(&dev
->struct_mutex
);
987 remain
-= page_length
;
988 user_data
+= page_length
;
989 offset
+= page_length
;
993 i915_gem_object_unpin_pages(obj
);
997 * Fixup: Flush cpu caches in case we didn't flush the dirty
998 * cachelines in-line while writing and the object moved
999 * out of the cpu write domain while we've dropped the lock.
1001 if (!needs_clflush_after
&&
1002 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
1003 if (i915_gem_clflush_object(obj
, obj
->pin_display
))
1004 needs_clflush_after
= true;
1008 if (needs_clflush_after
)
1009 i915_gem_chipset_flush(dev
);
1011 obj
->cache_dirty
= true;
1013 intel_fb_obj_flush(obj
, false, ORIGIN_CPU
);
1018 * Writes data to the object referenced by handle.
1020 * On error, the contents of the buffer that were to be modified are undefined.
1023 i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
1024 struct drm_file
*file
)
1026 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1027 struct drm_i915_gem_pwrite
*args
= data
;
1028 struct drm_i915_gem_object
*obj
;
1031 if (args
->size
== 0)
1034 if (!access_ok(VERIFY_READ
,
1035 u64_to_user_ptr(args
->data_ptr
),
1039 if (likely(!i915
.prefault_disable
)) {
1040 ret
= fault_in_multipages_readable(u64_to_user_ptr(args
->data_ptr
),
1046 intel_runtime_pm_get(dev_priv
);
1048 ret
= i915_mutex_lock_interruptible(dev
);
1052 obj
= to_intel_bo(drm_gem_object_lookup(file
, args
->handle
));
1053 if (&obj
->base
== NULL
) {
1058 /* Bounds check destination. */
1059 if (args
->offset
> obj
->base
.size
||
1060 args
->size
> obj
->base
.size
- args
->offset
) {
1065 /* prime objects have no backing filp to GEM pread/pwrite
1068 if (!obj
->base
.filp
) {
1073 trace_i915_gem_object_pwrite(obj
, args
->offset
, args
->size
);
1076 /* We can only do the GTT pwrite on untiled buffers, as otherwise
1077 * it would end up going through the fenced access, and we'll get
1078 * different detiling behavior between reading and writing.
1079 * pread/pwrite currently are reading and writing from the CPU
1080 * perspective, requiring manual detiling by the client.
1082 if (obj
->tiling_mode
== I915_TILING_NONE
&&
1083 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
&&
1084 cpu_write_needs_clflush(obj
)) {
1085 ret
= i915_gem_gtt_pwrite_fast(dev
, obj
, args
, file
);
1086 /* Note that the gtt paths might fail with non-page-backed user
1087 * pointers (e.g. gtt mappings when moving data between
1088 * textures). Fallback to the shmem path in that case. */
1091 if (ret
== -EFAULT
|| ret
== -ENOSPC
) {
1092 if (obj
->phys_handle
)
1093 ret
= i915_gem_phys_pwrite(obj
, args
, file
);
1095 ret
= i915_gem_shmem_pwrite(dev
, obj
, args
, file
);
1099 drm_gem_object_unreference(&obj
->base
);
1101 mutex_unlock(&dev
->struct_mutex
);
1103 intel_runtime_pm_put(dev_priv
);
1109 i915_gem_check_wedge(unsigned reset_counter
, bool interruptible
)
1111 if (__i915_terminally_wedged(reset_counter
))
1114 if (__i915_reset_in_progress(reset_counter
)) {
1115 /* Non-interruptible callers can't handle -EAGAIN, hence return
1116 * -EIO unconditionally for these. */
1126 static void fake_irq(unsigned long data
)
1128 wake_up_process((struct task_struct
*)data
);
1131 static bool missed_irq(struct drm_i915_private
*dev_priv
,
1132 struct intel_engine_cs
*engine
)
1134 return test_bit(engine
->id
, &dev_priv
->gpu_error
.missed_irq_rings
);
1137 static unsigned long local_clock_us(unsigned *cpu
)
1141 /* Cheaply and approximately convert from nanoseconds to microseconds.
1142 * The result and subsequent calculations are also defined in the same
1143 * approximate microseconds units. The principal source of timing
1144 * error here is from the simple truncation.
1146 * Note that local_clock() is only defined wrt to the current CPU;
1147 * the comparisons are no longer valid if we switch CPUs. Instead of
1148 * blocking preemption for the entire busywait, we can detect the CPU
1149 * switch and use that as indicator of system load and a reason to
1150 * stop busywaiting, see busywait_stop().
1153 t
= local_clock() >> 10;
1159 static bool busywait_stop(unsigned long timeout
, unsigned cpu
)
1163 if (time_after(local_clock_us(&this_cpu
), timeout
))
1166 return this_cpu
!= cpu
;
1169 static int __i915_spin_request(struct drm_i915_gem_request
*req
, int state
)
1171 unsigned long timeout
;
1174 /* When waiting for high frequency requests, e.g. during synchronous
1175 * rendering split between the CPU and GPU, the finite amount of time
1176 * required to set up the irq and wait upon it limits the response
1177 * rate. By busywaiting on the request completion for a short while we
1178 * can service the high frequency waits as quick as possible. However,
1179 * if it is a slow request, we want to sleep as quickly as possible.
1180 * The tradeoff between waiting and sleeping is roughly the time it
1181 * takes to sleep on a request, on the order of a microsecond.
1184 if (req
->engine
->irq_refcount
)
1187 /* Only spin if we know the GPU is processing this request */
1188 if (!i915_gem_request_started(req
, true))
1191 timeout
= local_clock_us(&cpu
) + 5;
1192 while (!need_resched()) {
1193 if (i915_gem_request_completed(req
, true))
1196 if (signal_pending_state(state
, current
))
1199 if (busywait_stop(timeout
, cpu
))
1202 cpu_relax_lowlatency();
1205 if (i915_gem_request_completed(req
, false))
1212 * __i915_wait_request - wait until execution of request has finished
1214 * @interruptible: do an interruptible wait (normally yes)
1215 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
1217 * Note: It is of utmost importance that the passed in seqno and reset_counter
1218 * values have been read by the caller in an smp safe manner. Where read-side
1219 * locks are involved, it is sufficient to read the reset_counter before
1220 * unlocking the lock that protects the seqno. For lockless tricks, the
1221 * reset_counter _must_ be read before, and an appropriate smp_rmb must be
1224 * Returns 0 if the request was found within the alloted time. Else returns the
1225 * errno with remaining time filled in timeout argument.
1227 int __i915_wait_request(struct drm_i915_gem_request
*req
,
1230 struct intel_rps_client
*rps
)
1232 struct intel_engine_cs
*engine
= i915_gem_request_get_engine(req
);
1233 struct drm_device
*dev
= engine
->dev
;
1234 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1235 const bool irq_test_in_progress
=
1236 ACCESS_ONCE(dev_priv
->gpu_error
.test_irq_rings
) & intel_engine_flag(engine
);
1237 int state
= interruptible
? TASK_INTERRUPTIBLE
: TASK_UNINTERRUPTIBLE
;
1239 unsigned long timeout_expire
;
1240 s64 before
= 0; /* Only to silence a compiler warning. */
1243 WARN(!intel_irqs_enabled(dev_priv
), "IRQs disabled");
1245 if (list_empty(&req
->list
))
1248 if (i915_gem_request_completed(req
, true))
1253 if (WARN_ON(*timeout
< 0))
1259 timeout_expire
= jiffies
+ nsecs_to_jiffies_timeout(*timeout
);
1262 * Record current time in case interrupted by signal, or wedged.
1264 before
= ktime_get_raw_ns();
1267 if (INTEL_INFO(dev_priv
)->gen
>= 6)
1268 gen6_rps_boost(dev_priv
, rps
, req
->emitted_jiffies
);
1270 trace_i915_gem_request_wait_begin(req
);
1272 /* Optimistic spin for the next jiffie before touching IRQs */
1273 ret
= __i915_spin_request(req
, state
);
1277 if (!irq_test_in_progress
&& WARN_ON(!engine
->irq_get(engine
))) {
1283 struct timer_list timer
;
1285 prepare_to_wait(&engine
->irq_queue
, &wait
, state
);
1287 /* We need to check whether any gpu reset happened in between
1288 * the request being submitted and now. If a reset has occurred,
1289 * the request is effectively complete (we either are in the
1290 * process of or have discarded the rendering and completely
1291 * reset the GPU. The results of the request are lost and we
1292 * are free to continue on with the original operation.
1294 if (req
->reset_counter
!= i915_reset_counter(&dev_priv
->gpu_error
)) {
1299 if (i915_gem_request_completed(req
, false)) {
1304 if (signal_pending_state(state
, current
)) {
1309 if (timeout
&& time_after_eq(jiffies
, timeout_expire
)) {
1314 timer
.function
= NULL
;
1315 if (timeout
|| missed_irq(dev_priv
, engine
)) {
1316 unsigned long expire
;
1318 setup_timer_on_stack(&timer
, fake_irq
, (unsigned long)current
);
1319 expire
= missed_irq(dev_priv
, engine
) ? jiffies
+ 1 : timeout_expire
;
1320 mod_timer(&timer
, expire
);
1325 if (timer
.function
) {
1326 del_singleshot_timer_sync(&timer
);
1327 destroy_timer_on_stack(&timer
);
1330 if (!irq_test_in_progress
)
1331 engine
->irq_put(engine
);
1333 finish_wait(&engine
->irq_queue
, &wait
);
1336 trace_i915_gem_request_wait_end(req
);
1339 s64 tres
= *timeout
- (ktime_get_raw_ns() - before
);
1341 *timeout
= tres
< 0 ? 0 : tres
;
1344 * Apparently ktime isn't accurate enough and occasionally has a
1345 * bit of mismatch in the jiffies<->nsecs<->ktime loop. So patch
1346 * things up to make the test happy. We allow up to 1 jiffy.
1348 * This is a regrssion from the timespec->ktime conversion.
1350 if (ret
== -ETIME
&& *timeout
< jiffies_to_usecs(1)*1000)
1357 int i915_gem_request_add_to_client(struct drm_i915_gem_request
*req
,
1358 struct drm_file
*file
)
1360 struct drm_i915_file_private
*file_priv
;
1362 WARN_ON(!req
|| !file
|| req
->file_priv
);
1370 file_priv
= file
->driver_priv
;
1372 spin_lock(&file_priv
->mm
.lock
);
1373 req
->file_priv
= file_priv
;
1374 list_add_tail(&req
->client_list
, &file_priv
->mm
.request_list
);
1375 spin_unlock(&file_priv
->mm
.lock
);
1377 req
->pid
= get_pid(task_pid(current
));
1383 i915_gem_request_remove_from_client(struct drm_i915_gem_request
*request
)
1385 struct drm_i915_file_private
*file_priv
= request
->file_priv
;
1390 spin_lock(&file_priv
->mm
.lock
);
1391 list_del(&request
->client_list
);
1392 request
->file_priv
= NULL
;
1393 spin_unlock(&file_priv
->mm
.lock
);
1395 put_pid(request
->pid
);
1396 request
->pid
= NULL
;
1399 static void i915_gem_request_retire(struct drm_i915_gem_request
*request
)
1401 trace_i915_gem_request_retire(request
);
1403 /* We know the GPU must have read the request to have
1404 * sent us the seqno + interrupt, so use the position
1405 * of tail of the request to update the last known position
1408 * Note this requires that we are always called in request
1411 request
->ringbuf
->last_retired_head
= request
->postfix
;
1413 list_del_init(&request
->list
);
1414 i915_gem_request_remove_from_client(request
);
1416 i915_gem_request_unreference(request
);
1420 __i915_gem_request_retire__upto(struct drm_i915_gem_request
*req
)
1422 struct intel_engine_cs
*engine
= req
->engine
;
1423 struct drm_i915_gem_request
*tmp
;
1425 lockdep_assert_held(&engine
->dev
->struct_mutex
);
1427 if (list_empty(&req
->list
))
1431 tmp
= list_first_entry(&engine
->request_list
,
1432 typeof(*tmp
), list
);
1434 i915_gem_request_retire(tmp
);
1435 } while (tmp
!= req
);
1437 WARN_ON(i915_verify_lists(engine
->dev
));
1441 * Waits for a request to be signaled, and cleans up the
1442 * request and object lists appropriately for that event.
1445 i915_wait_request(struct drm_i915_gem_request
*req
)
1447 struct drm_i915_private
*dev_priv
= req
->i915
;
1451 interruptible
= dev_priv
->mm
.interruptible
;
1453 BUG_ON(!mutex_is_locked(&dev_priv
->dev
->struct_mutex
));
1455 ret
= __i915_wait_request(req
, interruptible
, NULL
, NULL
);
1459 __i915_gem_request_retire__upto(req
);
1464 * Ensures that all rendering to the object has completed and the object is
1465 * safe to unbind from the GTT or access from the CPU.
1468 i915_gem_object_wait_rendering(struct drm_i915_gem_object
*obj
,
1477 if (obj
->last_write_req
!= NULL
) {
1478 ret
= i915_wait_request(obj
->last_write_req
);
1482 i
= obj
->last_write_req
->engine
->id
;
1483 if (obj
->last_read_req
[i
] == obj
->last_write_req
)
1484 i915_gem_object_retire__read(obj
, i
);
1486 i915_gem_object_retire__write(obj
);
1489 for (i
= 0; i
< I915_NUM_ENGINES
; i
++) {
1490 if (obj
->last_read_req
[i
] == NULL
)
1493 ret
= i915_wait_request(obj
->last_read_req
[i
]);
1497 i915_gem_object_retire__read(obj
, i
);
1499 GEM_BUG_ON(obj
->active
);
1506 i915_gem_object_retire_request(struct drm_i915_gem_object
*obj
,
1507 struct drm_i915_gem_request
*req
)
1509 int ring
= req
->engine
->id
;
1511 if (obj
->last_read_req
[ring
] == req
)
1512 i915_gem_object_retire__read(obj
, ring
);
1513 else if (obj
->last_write_req
== req
)
1514 i915_gem_object_retire__write(obj
);
1516 __i915_gem_request_retire__upto(req
);
1519 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1520 * as the object state may change during this call.
1522 static __must_check
int
1523 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object
*obj
,
1524 struct intel_rps_client
*rps
,
1527 struct drm_device
*dev
= obj
->base
.dev
;
1528 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1529 struct drm_i915_gem_request
*requests
[I915_NUM_ENGINES
];
1532 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
1533 BUG_ON(!dev_priv
->mm
.interruptible
);
1539 struct drm_i915_gem_request
*req
;
1541 req
= obj
->last_write_req
;
1545 requests
[n
++] = i915_gem_request_reference(req
);
1547 for (i
= 0; i
< I915_NUM_ENGINES
; i
++) {
1548 struct drm_i915_gem_request
*req
;
1550 req
= obj
->last_read_req
[i
];
1554 requests
[n
++] = i915_gem_request_reference(req
);
1558 mutex_unlock(&dev
->struct_mutex
);
1560 for (i
= 0; ret
== 0 && i
< n
; i
++)
1561 ret
= __i915_wait_request(requests
[i
], true, NULL
, rps
);
1562 mutex_lock(&dev
->struct_mutex
);
1564 for (i
= 0; i
< n
; i
++) {
1566 i915_gem_object_retire_request(obj
, requests
[i
]);
1567 i915_gem_request_unreference(requests
[i
]);
1573 static struct intel_rps_client
*to_rps_client(struct drm_file
*file
)
1575 struct drm_i915_file_private
*fpriv
= file
->driver_priv
;
1580 * Called when user space prepares to use an object with the CPU, either
1581 * through the mmap ioctl's mapping or a GTT mapping.
1584 i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
1585 struct drm_file
*file
)
1587 struct drm_i915_gem_set_domain
*args
= data
;
1588 struct drm_i915_gem_object
*obj
;
1589 uint32_t read_domains
= args
->read_domains
;
1590 uint32_t write_domain
= args
->write_domain
;
1593 /* Only handle setting domains to types used by the CPU. */
1594 if (write_domain
& I915_GEM_GPU_DOMAINS
)
1597 if (read_domains
& I915_GEM_GPU_DOMAINS
)
1600 /* Having something in the write domain implies it's in the read
1601 * domain, and only that read domain. Enforce that in the request.
1603 if (write_domain
!= 0 && read_domains
!= write_domain
)
1606 ret
= i915_mutex_lock_interruptible(dev
);
1610 obj
= to_intel_bo(drm_gem_object_lookup(file
, args
->handle
));
1611 if (&obj
->base
== NULL
) {
1616 /* Try to flush the object off the GPU without holding the lock.
1617 * We will repeat the flush holding the lock in the normal manner
1618 * to catch cases where we are gazumped.
1620 ret
= i915_gem_object_wait_rendering__nonblocking(obj
,
1621 to_rps_client(file
),
1626 if (read_domains
& I915_GEM_DOMAIN_GTT
)
1627 ret
= i915_gem_object_set_to_gtt_domain(obj
, write_domain
!= 0);
1629 ret
= i915_gem_object_set_to_cpu_domain(obj
, write_domain
!= 0);
1631 if (write_domain
!= 0)
1632 intel_fb_obj_invalidate(obj
,
1633 write_domain
== I915_GEM_DOMAIN_GTT
?
1634 ORIGIN_GTT
: ORIGIN_CPU
);
1637 drm_gem_object_unreference(&obj
->base
);
1639 mutex_unlock(&dev
->struct_mutex
);
1644 * Called when user space has done writes to this buffer
1647 i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1648 struct drm_file
*file
)
1650 struct drm_i915_gem_sw_finish
*args
= data
;
1651 struct drm_i915_gem_object
*obj
;
1654 ret
= i915_mutex_lock_interruptible(dev
);
1658 obj
= to_intel_bo(drm_gem_object_lookup(file
, args
->handle
));
1659 if (&obj
->base
== NULL
) {
1664 /* Pinned buffers may be scanout, so flush the cache */
1665 if (obj
->pin_display
)
1666 i915_gem_object_flush_cpu_write_domain(obj
);
1668 drm_gem_object_unreference(&obj
->base
);
1670 mutex_unlock(&dev
->struct_mutex
);
1675 * Maps the contents of an object, returning the address it is mapped
1678 * While the mapping holds a reference on the contents of the object, it doesn't
1679 * imply a ref on the object itself.
1683 * DRM driver writers who look a this function as an example for how to do GEM
1684 * mmap support, please don't implement mmap support like here. The modern way
1685 * to implement DRM mmap support is with an mmap offset ioctl (like
1686 * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly.
1687 * That way debug tooling like valgrind will understand what's going on, hiding
1688 * the mmap call in a driver private ioctl will break that. The i915 driver only
1689 * does cpu mmaps this way because we didn't know better.
1692 i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1693 struct drm_file
*file
)
1695 struct drm_i915_gem_mmap
*args
= data
;
1696 struct drm_gem_object
*obj
;
1699 if (args
->flags
& ~(I915_MMAP_WC
))
1702 if (args
->flags
& I915_MMAP_WC
&& !boot_cpu_has(X86_FEATURE_PAT
))
1705 obj
= drm_gem_object_lookup(file
, args
->handle
);
1709 /* prime objects have no backing filp to GEM mmap
1713 drm_gem_object_unreference_unlocked(obj
);
1717 addr
= vm_mmap(obj
->filp
, 0, args
->size
,
1718 PROT_READ
| PROT_WRITE
, MAP_SHARED
,
1720 if (args
->flags
& I915_MMAP_WC
) {
1721 struct mm_struct
*mm
= current
->mm
;
1722 struct vm_area_struct
*vma
;
1724 if (down_write_killable(&mm
->mmap_sem
)) {
1725 drm_gem_object_unreference_unlocked(obj
);
1728 vma
= find_vma(mm
, addr
);
1731 pgprot_writecombine(vm_get_page_prot(vma
->vm_flags
));
1734 up_write(&mm
->mmap_sem
);
1736 drm_gem_object_unreference_unlocked(obj
);
1737 if (IS_ERR((void *)addr
))
1740 args
->addr_ptr
= (uint64_t) addr
;
1746 * i915_gem_fault - fault a page into the GTT
1747 * @vma: VMA in question
1750 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1751 * from userspace. The fault handler takes care of binding the object to
1752 * the GTT (if needed), allocating and programming a fence register (again,
1753 * only if needed based on whether the old reg is still valid or the object
1754 * is tiled) and inserting a new PTE into the faulting process.
1756 * Note that the faulting process may involve evicting existing objects
1757 * from the GTT and/or fence registers to make room. So performance may
1758 * suffer if the GTT working set is large or there are few fence registers
1761 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
)
1763 struct drm_i915_gem_object
*obj
= to_intel_bo(vma
->vm_private_data
);
1764 struct drm_device
*dev
= obj
->base
.dev
;
1765 struct drm_i915_private
*dev_priv
= to_i915(dev
);
1766 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
1767 struct i915_ggtt_view view
= i915_ggtt_view_normal
;
1768 pgoff_t page_offset
;
1771 bool write
= !!(vmf
->flags
& FAULT_FLAG_WRITE
);
1773 intel_runtime_pm_get(dev_priv
);
1775 /* We don't use vmf->pgoff since that has the fake offset */
1776 page_offset
= ((unsigned long)vmf
->virtual_address
- vma
->vm_start
) >>
1779 ret
= i915_mutex_lock_interruptible(dev
);
1783 trace_i915_gem_object_fault(obj
, page_offset
, true, write
);
1785 /* Try to flush the object off the GPU first without holding the lock.
1786 * Upon reacquiring the lock, we will perform our sanity checks and then
1787 * repeat the flush holding the lock in the normal manner to catch cases
1788 * where we are gazumped.
1790 ret
= i915_gem_object_wait_rendering__nonblocking(obj
, NULL
, !write
);
1794 /* Access to snoopable pages through the GTT is incoherent. */
1795 if (obj
->cache_level
!= I915_CACHE_NONE
&& !HAS_LLC(dev
)) {
1800 /* Use a partial view if the object is bigger than the aperture. */
1801 if (obj
->base
.size
>= ggtt
->mappable_end
&&
1802 obj
->tiling_mode
== I915_TILING_NONE
) {
1803 static const unsigned int chunk_size
= 256; // 1 MiB
1805 memset(&view
, 0, sizeof(view
));
1806 view
.type
= I915_GGTT_VIEW_PARTIAL
;
1807 view
.params
.partial
.offset
= rounddown(page_offset
, chunk_size
);
1808 view
.params
.partial
.size
=
1811 (vma
->vm_end
- vma
->vm_start
)/PAGE_SIZE
-
1812 view
.params
.partial
.offset
);
1815 /* Now pin it into the GTT if needed */
1816 ret
= i915_gem_object_ggtt_pin(obj
, &view
, 0, PIN_MAPPABLE
);
1820 ret
= i915_gem_object_set_to_gtt_domain(obj
, write
);
1824 ret
= i915_gem_object_get_fence(obj
);
1828 /* Finally, remap it using the new GTT offset */
1829 pfn
= ggtt
->mappable_base
+
1830 i915_gem_obj_ggtt_offset_view(obj
, &view
);
1833 if (unlikely(view
.type
== I915_GGTT_VIEW_PARTIAL
)) {
1834 /* Overriding existing pages in partial view does not cause
1835 * us any trouble as TLBs are still valid because the fault
1836 * is due to userspace losing part of the mapping or never
1837 * having accessed it before (at this partials' range).
1839 unsigned long base
= vma
->vm_start
+
1840 (view
.params
.partial
.offset
<< PAGE_SHIFT
);
1843 for (i
= 0; i
< view
.params
.partial
.size
; i
++) {
1844 ret
= vm_insert_pfn(vma
, base
+ i
* PAGE_SIZE
, pfn
+ i
);
1849 obj
->fault_mappable
= true;
1851 if (!obj
->fault_mappable
) {
1852 unsigned long size
= min_t(unsigned long,
1853 vma
->vm_end
- vma
->vm_start
,
1857 for (i
= 0; i
< size
>> PAGE_SHIFT
; i
++) {
1858 ret
= vm_insert_pfn(vma
,
1859 (unsigned long)vma
->vm_start
+ i
* PAGE_SIZE
,
1865 obj
->fault_mappable
= true;
1867 ret
= vm_insert_pfn(vma
,
1868 (unsigned long)vmf
->virtual_address
,
1872 i915_gem_object_ggtt_unpin_view(obj
, &view
);
1874 mutex_unlock(&dev
->struct_mutex
);
1879 * We eat errors when the gpu is terminally wedged to avoid
1880 * userspace unduly crashing (gl has no provisions for mmaps to
1881 * fail). But any other -EIO isn't ours (e.g. swap in failure)
1882 * and so needs to be reported.
1884 if (!i915_terminally_wedged(&dev_priv
->gpu_error
)) {
1885 ret
= VM_FAULT_SIGBUS
;
1890 * EAGAIN means the gpu is hung and we'll wait for the error
1891 * handler to reset everything when re-faulting in
1892 * i915_mutex_lock_interruptible.
1899 * EBUSY is ok: this just means that another thread
1900 * already did the job.
1902 ret
= VM_FAULT_NOPAGE
;
1909 ret
= VM_FAULT_SIGBUS
;
1912 WARN_ONCE(ret
, "unhandled error in i915_gem_fault: %i\n", ret
);
1913 ret
= VM_FAULT_SIGBUS
;
1917 intel_runtime_pm_put(dev_priv
);
1922 * i915_gem_release_mmap - remove physical page mappings
1923 * @obj: obj in question
1925 * Preserve the reservation of the mmapping with the DRM core code, but
1926 * relinquish ownership of the pages back to the system.
1928 * It is vital that we remove the page mapping if we have mapped a tiled
1929 * object through the GTT and then lose the fence register due to
1930 * resource pressure. Similarly if the object has been moved out of the
1931 * aperture, than pages mapped into userspace must be revoked. Removing the
1932 * mapping will then trigger a page fault on the next user access, allowing
1933 * fixup by i915_gem_fault().
1936 i915_gem_release_mmap(struct drm_i915_gem_object
*obj
)
1938 /* Serialisation between user GTT access and our code depends upon
1939 * revoking the CPU's PTE whilst the mutex is held. The next user
1940 * pagefault then has to wait until we release the mutex.
1942 lockdep_assert_held(&obj
->base
.dev
->struct_mutex
);
1944 if (!obj
->fault_mappable
)
1947 drm_vma_node_unmap(&obj
->base
.vma_node
,
1948 obj
->base
.dev
->anon_inode
->i_mapping
);
1950 /* Ensure that the CPU's PTE are revoked and there are not outstanding
1951 * memory transactions from userspace before we return. The TLB
1952 * flushing implied above by changing the PTE above *should* be
1953 * sufficient, an extra barrier here just provides us with a bit
1954 * of paranoid documentation about our requirement to serialise
1955 * memory writes before touching registers / GSM.
1959 obj
->fault_mappable
= false;
1963 i915_gem_release_all_mmaps(struct drm_i915_private
*dev_priv
)
1965 struct drm_i915_gem_object
*obj
;
1967 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
)
1968 i915_gem_release_mmap(obj
);
1972 i915_gem_get_gtt_size(struct drm_device
*dev
, uint32_t size
, int tiling_mode
)
1976 if (INTEL_INFO(dev
)->gen
>= 4 ||
1977 tiling_mode
== I915_TILING_NONE
)
1980 /* Previous chips need a power-of-two fence region when tiling */
1981 if (INTEL_INFO(dev
)->gen
== 3)
1982 gtt_size
= 1024*1024;
1984 gtt_size
= 512*1024;
1986 while (gtt_size
< size
)
1993 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1994 * @obj: object to check
1996 * Return the required GTT alignment for an object, taking into account
1997 * potential fence register mapping.
2000 i915_gem_get_gtt_alignment(struct drm_device
*dev
, uint32_t size
,
2001 int tiling_mode
, bool fenced
)
2004 * Minimum alignment is 4k (GTT page size), but might be greater
2005 * if a fence register is needed for the object.
2007 if (INTEL_INFO(dev
)->gen
>= 4 || (!fenced
&& IS_G33(dev
)) ||
2008 tiling_mode
== I915_TILING_NONE
)
2012 * Previous chips need to be aligned to the size of the smallest
2013 * fence register that can contain the object.
2015 return i915_gem_get_gtt_size(dev
, size
, tiling_mode
);
2018 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object
*obj
)
2020 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2023 dev_priv
->mm
.shrinker_no_lock_stealing
= true;
2025 ret
= drm_gem_create_mmap_offset(&obj
->base
);
2029 /* Badly fragmented mmap space? The only way we can recover
2030 * space is by destroying unwanted objects. We can't randomly release
2031 * mmap_offsets as userspace expects them to be persistent for the
2032 * lifetime of the objects. The closest we can is to release the
2033 * offsets on purgeable objects by truncating it and marking it purged,
2034 * which prevents userspace from ever using that object again.
2036 i915_gem_shrink(dev_priv
,
2037 obj
->base
.size
>> PAGE_SHIFT
,
2039 I915_SHRINK_UNBOUND
|
2040 I915_SHRINK_PURGEABLE
);
2041 ret
= drm_gem_create_mmap_offset(&obj
->base
);
2045 i915_gem_shrink_all(dev_priv
);
2046 ret
= drm_gem_create_mmap_offset(&obj
->base
);
2048 dev_priv
->mm
.shrinker_no_lock_stealing
= false;
2053 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object
*obj
)
2055 drm_gem_free_mmap_offset(&obj
->base
);
2059 i915_gem_mmap_gtt(struct drm_file
*file
,
2060 struct drm_device
*dev
,
2064 struct drm_i915_gem_object
*obj
;
2067 ret
= i915_mutex_lock_interruptible(dev
);
2071 obj
= to_intel_bo(drm_gem_object_lookup(file
, handle
));
2072 if (&obj
->base
== NULL
) {
2077 if (obj
->madv
!= I915_MADV_WILLNEED
) {
2078 DRM_DEBUG("Attempting to mmap a purgeable buffer\n");
2083 ret
= i915_gem_object_create_mmap_offset(obj
);
2087 *offset
= drm_vma_node_offset_addr(&obj
->base
.vma_node
);
2090 drm_gem_object_unreference(&obj
->base
);
2092 mutex_unlock(&dev
->struct_mutex
);
2097 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
2099 * @data: GTT mapping ioctl data
2100 * @file: GEM object info
2102 * Simply returns the fake offset to userspace so it can mmap it.
2103 * The mmap call will end up in drm_gem_mmap(), which will set things
2104 * up so we can get faults in the handler above.
2106 * The fault handler will take care of binding the object into the GTT
2107 * (since it may have been evicted to make room for something), allocating
2108 * a fence register, and mapping the appropriate aperture address into
2112 i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
2113 struct drm_file
*file
)
2115 struct drm_i915_gem_mmap_gtt
*args
= data
;
2117 return i915_gem_mmap_gtt(file
, dev
, args
->handle
, &args
->offset
);
2120 /* Immediately discard the backing storage */
2122 i915_gem_object_truncate(struct drm_i915_gem_object
*obj
)
2124 i915_gem_object_free_mmap_offset(obj
);
2126 if (obj
->base
.filp
== NULL
)
2129 /* Our goal here is to return as much of the memory as
2130 * is possible back to the system as we are called from OOM.
2131 * To do this we must instruct the shmfs to drop all of its
2132 * backing pages, *now*.
2134 shmem_truncate_range(file_inode(obj
->base
.filp
), 0, (loff_t
)-1);
2135 obj
->madv
= __I915_MADV_PURGED
;
2138 /* Try to discard unwanted pages */
2140 i915_gem_object_invalidate(struct drm_i915_gem_object
*obj
)
2142 struct address_space
*mapping
;
2144 switch (obj
->madv
) {
2145 case I915_MADV_DONTNEED
:
2146 i915_gem_object_truncate(obj
);
2147 case __I915_MADV_PURGED
:
2151 if (obj
->base
.filp
== NULL
)
2154 mapping
= file_inode(obj
->base
.filp
)->i_mapping
,
2155 invalidate_mapping_pages(mapping
, 0, (loff_t
)-1);
2159 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object
*obj
)
2161 struct sg_page_iter sg_iter
;
2164 BUG_ON(obj
->madv
== __I915_MADV_PURGED
);
2166 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
2168 /* In the event of a disaster, abandon all caches and
2169 * hope for the best.
2171 i915_gem_clflush_object(obj
, true);
2172 obj
->base
.read_domains
= obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
2175 i915_gem_gtt_finish_object(obj
);
2177 if (i915_gem_object_needs_bit17_swizzle(obj
))
2178 i915_gem_object_save_bit_17_swizzle(obj
);
2180 if (obj
->madv
== I915_MADV_DONTNEED
)
2183 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
, 0) {
2184 struct page
*page
= sg_page_iter_page(&sg_iter
);
2187 set_page_dirty(page
);
2189 if (obj
->madv
== I915_MADV_WILLNEED
)
2190 mark_page_accessed(page
);
2196 sg_free_table(obj
->pages
);
2201 i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
)
2203 const struct drm_i915_gem_object_ops
*ops
= obj
->ops
;
2205 if (obj
->pages
== NULL
)
2208 if (obj
->pages_pin_count
)
2211 BUG_ON(i915_gem_obj_bound_any(obj
));
2213 /* ->put_pages might need to allocate memory for the bit17 swizzle
2214 * array, hence protect them from being reaped by removing them from gtt
2216 list_del(&obj
->global_list
);
2219 if (is_vmalloc_addr(obj
->mapping
))
2220 vunmap(obj
->mapping
);
2222 kunmap(kmap_to_page(obj
->mapping
));
2223 obj
->mapping
= NULL
;
2226 ops
->put_pages(obj
);
2229 i915_gem_object_invalidate(obj
);
2235 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object
*obj
)
2237 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2239 struct address_space
*mapping
;
2240 struct sg_table
*st
;
2241 struct scatterlist
*sg
;
2242 struct sg_page_iter sg_iter
;
2244 unsigned long last_pfn
= 0; /* suppress gcc warning */
2248 /* Assert that the object is not currently in any GPU domain. As it
2249 * wasn't in the GTT, there shouldn't be any way it could have been in
2252 BUG_ON(obj
->base
.read_domains
& I915_GEM_GPU_DOMAINS
);
2253 BUG_ON(obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
);
2255 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
2259 page_count
= obj
->base
.size
/ PAGE_SIZE
;
2260 if (sg_alloc_table(st
, page_count
, GFP_KERNEL
)) {
2265 /* Get the list of pages out of our struct file. They'll be pinned
2266 * at this point until we release them.
2268 * Fail silently without starting the shrinker
2270 mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
2271 gfp
= mapping_gfp_constraint(mapping
, ~(__GFP_IO
| __GFP_RECLAIM
));
2272 gfp
|= __GFP_NORETRY
| __GFP_NOWARN
;
2275 for (i
= 0; i
< page_count
; i
++) {
2276 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
2278 i915_gem_shrink(dev_priv
,
2281 I915_SHRINK_UNBOUND
|
2282 I915_SHRINK_PURGEABLE
);
2283 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
2286 /* We've tried hard to allocate the memory by reaping
2287 * our own buffer, now let the real VM do its job and
2288 * go down in flames if truly OOM.
2290 i915_gem_shrink_all(dev_priv
);
2291 page
= shmem_read_mapping_page(mapping
, i
);
2293 ret
= PTR_ERR(page
);
2297 #ifdef CONFIG_SWIOTLB
2298 if (swiotlb_nr_tbl()) {
2300 sg_set_page(sg
, page
, PAGE_SIZE
, 0);
2305 if (!i
|| page_to_pfn(page
) != last_pfn
+ 1) {
2309 sg_set_page(sg
, page
, PAGE_SIZE
, 0);
2311 sg
->length
+= PAGE_SIZE
;
2313 last_pfn
= page_to_pfn(page
);
2315 /* Check that the i965g/gm workaround works. */
2316 WARN_ON((gfp
& __GFP_DMA32
) && (last_pfn
>= 0x00100000UL
));
2318 #ifdef CONFIG_SWIOTLB
2319 if (!swiotlb_nr_tbl())
2324 ret
= i915_gem_gtt_prepare_object(obj
);
2328 if (i915_gem_object_needs_bit17_swizzle(obj
))
2329 i915_gem_object_do_bit_17_swizzle(obj
);
2331 if (obj
->tiling_mode
!= I915_TILING_NONE
&&
2332 dev_priv
->quirks
& QUIRK_PIN_SWIZZLED_PAGES
)
2333 i915_gem_object_pin_pages(obj
);
2339 for_each_sg_page(st
->sgl
, &sg_iter
, st
->nents
, 0)
2340 put_page(sg_page_iter_page(&sg_iter
));
2344 /* shmemfs first checks if there is enough memory to allocate the page
2345 * and reports ENOSPC should there be insufficient, along with the usual
2346 * ENOMEM for a genuine allocation failure.
2348 * We use ENOSPC in our driver to mean that we have run out of aperture
2349 * space and so want to translate the error from shmemfs back to our
2350 * usual understanding of ENOMEM.
2358 /* Ensure that the associated pages are gathered from the backing storage
2359 * and pinned into our object. i915_gem_object_get_pages() may be called
2360 * multiple times before they are released by a single call to
2361 * i915_gem_object_put_pages() - once the pages are no longer referenced
2362 * either as a result of memory pressure (reaping pages under the shrinker)
2363 * or as the object is itself released.
2366 i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
)
2368 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2369 const struct drm_i915_gem_object_ops
*ops
= obj
->ops
;
2375 if (obj
->madv
!= I915_MADV_WILLNEED
) {
2376 DRM_DEBUG("Attempting to obtain a purgeable object\n");
2380 BUG_ON(obj
->pages_pin_count
);
2382 ret
= ops
->get_pages(obj
);
2386 list_add_tail(&obj
->global_list
, &dev_priv
->mm
.unbound_list
);
2388 obj
->get_page
.sg
= obj
->pages
->sgl
;
2389 obj
->get_page
.last
= 0;
2394 void *i915_gem_object_pin_map(struct drm_i915_gem_object
*obj
)
2398 lockdep_assert_held(&obj
->base
.dev
->struct_mutex
);
2400 ret
= i915_gem_object_get_pages(obj
);
2402 return ERR_PTR(ret
);
2404 i915_gem_object_pin_pages(obj
);
2406 if (obj
->mapping
== NULL
) {
2407 struct page
**pages
;
2410 if (obj
->base
.size
== PAGE_SIZE
)
2411 obj
->mapping
= kmap(sg_page(obj
->pages
->sgl
));
2413 pages
= drm_malloc_gfp(obj
->base
.size
>> PAGE_SHIFT
,
2416 if (pages
!= NULL
) {
2417 struct sg_page_iter sg_iter
;
2421 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
,
2422 obj
->pages
->nents
, 0)
2423 pages
[n
++] = sg_page_iter_page(&sg_iter
);
2425 obj
->mapping
= vmap(pages
, n
, 0, PAGE_KERNEL
);
2426 drm_free_large(pages
);
2428 if (obj
->mapping
== NULL
) {
2429 i915_gem_object_unpin_pages(obj
);
2430 return ERR_PTR(-ENOMEM
);
2434 return obj
->mapping
;
2437 void i915_vma_move_to_active(struct i915_vma
*vma
,
2438 struct drm_i915_gem_request
*req
)
2440 struct drm_i915_gem_object
*obj
= vma
->obj
;
2441 struct intel_engine_cs
*engine
;
2443 engine
= i915_gem_request_get_engine(req
);
2445 /* Add a reference if we're newly entering the active list. */
2446 if (obj
->active
== 0)
2447 drm_gem_object_reference(&obj
->base
);
2448 obj
->active
|= intel_engine_flag(engine
);
2450 list_move_tail(&obj
->engine_list
[engine
->id
], &engine
->active_list
);
2451 i915_gem_request_assign(&obj
->last_read_req
[engine
->id
], req
);
2453 list_move_tail(&vma
->vm_link
, &vma
->vm
->active_list
);
2457 i915_gem_object_retire__write(struct drm_i915_gem_object
*obj
)
2459 GEM_BUG_ON(obj
->last_write_req
== NULL
);
2460 GEM_BUG_ON(!(obj
->active
& intel_engine_flag(obj
->last_write_req
->engine
)));
2462 i915_gem_request_assign(&obj
->last_write_req
, NULL
);
2463 intel_fb_obj_flush(obj
, true, ORIGIN_CS
);
2467 i915_gem_object_retire__read(struct drm_i915_gem_object
*obj
, int ring
)
2469 struct i915_vma
*vma
;
2471 GEM_BUG_ON(obj
->last_read_req
[ring
] == NULL
);
2472 GEM_BUG_ON(!(obj
->active
& (1 << ring
)));
2474 list_del_init(&obj
->engine_list
[ring
]);
2475 i915_gem_request_assign(&obj
->last_read_req
[ring
], NULL
);
2477 if (obj
->last_write_req
&& obj
->last_write_req
->engine
->id
== ring
)
2478 i915_gem_object_retire__write(obj
);
2480 obj
->active
&= ~(1 << ring
);
2484 /* Bump our place on the bound list to keep it roughly in LRU order
2485 * so that we don't steal from recently used but inactive objects
2486 * (unless we are forced to ofc!)
2488 list_move_tail(&obj
->global_list
,
2489 &to_i915(obj
->base
.dev
)->mm
.bound_list
);
2491 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
) {
2492 if (!list_empty(&vma
->vm_link
))
2493 list_move_tail(&vma
->vm_link
, &vma
->vm
->inactive_list
);
2496 i915_gem_request_assign(&obj
->last_fenced_req
, NULL
);
2497 drm_gem_object_unreference(&obj
->base
);
2501 i915_gem_init_seqno(struct drm_device
*dev
, u32 seqno
)
2503 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2504 struct intel_engine_cs
*engine
;
2507 /* Carefully retire all requests without writing to the rings */
2508 for_each_engine(engine
, dev_priv
) {
2509 ret
= intel_engine_idle(engine
);
2513 i915_gem_retire_requests(dev
);
2515 /* Finally reset hw state */
2516 for_each_engine(engine
, dev_priv
)
2517 intel_ring_init_seqno(engine
, seqno
);
2522 int i915_gem_set_seqno(struct drm_device
*dev
, u32 seqno
)
2524 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2530 /* HWS page needs to be set less than what we
2531 * will inject to ring
2533 ret
= i915_gem_init_seqno(dev
, seqno
- 1);
2537 /* Carefully set the last_seqno value so that wrap
2538 * detection still works
2540 dev_priv
->next_seqno
= seqno
;
2541 dev_priv
->last_seqno
= seqno
- 1;
2542 if (dev_priv
->last_seqno
== 0)
2543 dev_priv
->last_seqno
--;
2549 i915_gem_get_seqno(struct drm_device
*dev
, u32
*seqno
)
2551 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2553 /* reserve 0 for non-seqno */
2554 if (dev_priv
->next_seqno
== 0) {
2555 int ret
= i915_gem_init_seqno(dev
, 0);
2559 dev_priv
->next_seqno
= 1;
2562 *seqno
= dev_priv
->last_seqno
= dev_priv
->next_seqno
++;
2567 * NB: This function is not allowed to fail. Doing so would mean the the
2568 * request is not being tracked for completion but the work itself is
2569 * going to happen on the hardware. This would be a Bad Thing(tm).
2571 void __i915_add_request(struct drm_i915_gem_request
*request
,
2572 struct drm_i915_gem_object
*obj
,
2575 struct intel_engine_cs
*engine
;
2576 struct drm_i915_private
*dev_priv
;
2577 struct intel_ringbuffer
*ringbuf
;
2581 if (WARN_ON(request
== NULL
))
2584 engine
= request
->engine
;
2585 dev_priv
= request
->i915
;
2586 ringbuf
= request
->ringbuf
;
2589 * To ensure that this call will not fail, space for its emissions
2590 * should already have been reserved in the ring buffer. Let the ring
2591 * know that it is time to use that space up.
2593 intel_ring_reserved_space_use(ringbuf
);
2595 request_start
= intel_ring_get_tail(ringbuf
);
2597 * Emit any outstanding flushes - execbuf can fail to emit the flush
2598 * after having emitted the batchbuffer command. Hence we need to fix
2599 * things up similar to emitting the lazy request. The difference here
2600 * is that the flush _must_ happen before the next request, no matter
2604 if (i915
.enable_execlists
)
2605 ret
= logical_ring_flush_all_caches(request
);
2607 ret
= intel_ring_flush_all_caches(request
);
2608 /* Not allowed to fail! */
2609 WARN(ret
, "*_ring_flush_all_caches failed: %d!\n", ret
);
2612 trace_i915_gem_request_add(request
);
2614 request
->head
= request_start
;
2616 /* Whilst this request exists, batch_obj will be on the
2617 * active_list, and so will hold the active reference. Only when this
2618 * request is retired will the the batch_obj be moved onto the
2619 * inactive_list and lose its active reference. Hence we do not need
2620 * to explicitly hold another reference here.
2622 request
->batch_obj
= obj
;
2624 /* Seal the request and mark it as pending execution. Note that
2625 * we may inspect this state, without holding any locks, during
2626 * hangcheck. Hence we apply the barrier to ensure that we do not
2627 * see a more recent value in the hws than we are tracking.
2629 request
->emitted_jiffies
= jiffies
;
2630 request
->previous_seqno
= engine
->last_submitted_seqno
;
2631 smp_store_mb(engine
->last_submitted_seqno
, request
->seqno
);
2632 list_add_tail(&request
->list
, &engine
->request_list
);
2634 /* Record the position of the start of the request so that
2635 * should we detect the updated seqno part-way through the
2636 * GPU processing the request, we never over-estimate the
2637 * position of the head.
2639 request
->postfix
= intel_ring_get_tail(ringbuf
);
2641 if (i915
.enable_execlists
)
2642 ret
= engine
->emit_request(request
);
2644 ret
= engine
->add_request(request
);
2646 request
->tail
= intel_ring_get_tail(ringbuf
);
2648 /* Not allowed to fail! */
2649 WARN(ret
, "emit|add_request failed: %d!\n", ret
);
2651 i915_queue_hangcheck(engine
->dev
);
2653 queue_delayed_work(dev_priv
->wq
,
2654 &dev_priv
->mm
.retire_work
,
2655 round_jiffies_up_relative(HZ
));
2656 intel_mark_busy(dev_priv
->dev
);
2658 /* Sanity check that the reserved size was large enough. */
2659 intel_ring_reserved_space_end(ringbuf
);
2662 static bool i915_context_is_banned(struct drm_i915_private
*dev_priv
,
2663 const struct intel_context
*ctx
)
2665 unsigned long elapsed
;
2667 elapsed
= get_seconds() - ctx
->hang_stats
.guilty_ts
;
2669 if (ctx
->hang_stats
.banned
)
2672 if (ctx
->hang_stats
.ban_period_seconds
&&
2673 elapsed
<= ctx
->hang_stats
.ban_period_seconds
) {
2674 if (!i915_gem_context_is_default(ctx
)) {
2675 DRM_DEBUG("context hanging too fast, banning!\n");
2677 } else if (i915_stop_ring_allow_ban(dev_priv
)) {
2678 if (i915_stop_ring_allow_warn(dev_priv
))
2679 DRM_ERROR("gpu hanging too fast, banning!\n");
2687 static void i915_set_reset_status(struct drm_i915_private
*dev_priv
,
2688 struct intel_context
*ctx
,
2691 struct i915_ctx_hang_stats
*hs
;
2696 hs
= &ctx
->hang_stats
;
2699 hs
->banned
= i915_context_is_banned(dev_priv
, ctx
);
2701 hs
->guilty_ts
= get_seconds();
2703 hs
->batch_pending
++;
2707 void i915_gem_request_free(struct kref
*req_ref
)
2709 struct drm_i915_gem_request
*req
= container_of(req_ref
,
2711 struct intel_context
*ctx
= req
->ctx
;
2714 i915_gem_request_remove_from_client(req
);
2717 if (i915
.enable_execlists
&& ctx
!= req
->i915
->kernel_context
)
2718 intel_lr_context_unpin(ctx
, req
->engine
);
2720 i915_gem_context_unreference(ctx
);
2723 kmem_cache_free(req
->i915
->requests
, req
);
2727 __i915_gem_request_alloc(struct intel_engine_cs
*engine
,
2728 struct intel_context
*ctx
,
2729 struct drm_i915_gem_request
**req_out
)
2731 struct drm_i915_private
*dev_priv
= to_i915(engine
->dev
);
2732 unsigned reset_counter
= i915_reset_counter(&dev_priv
->gpu_error
);
2733 struct drm_i915_gem_request
*req
;
2741 /* ABI: Before userspace accesses the GPU (e.g. execbuffer), report
2742 * EIO if the GPU is already wedged, or EAGAIN to drop the struct_mutex
2745 ret
= i915_gem_check_wedge(reset_counter
, dev_priv
->mm
.interruptible
);
2749 req
= kmem_cache_zalloc(dev_priv
->requests
, GFP_KERNEL
);
2753 ret
= i915_gem_get_seqno(engine
->dev
, &req
->seqno
);
2757 kref_init(&req
->ref
);
2758 req
->i915
= dev_priv
;
2759 req
->engine
= engine
;
2760 req
->reset_counter
= reset_counter
;
2762 i915_gem_context_reference(req
->ctx
);
2764 if (i915
.enable_execlists
)
2765 ret
= intel_logical_ring_alloc_request_extras(req
);
2767 ret
= intel_ring_alloc_request_extras(req
);
2769 i915_gem_context_unreference(req
->ctx
);
2774 * Reserve space in the ring buffer for all the commands required to
2775 * eventually emit this request. This is to guarantee that the
2776 * i915_add_request() call can't fail. Note that the reserve may need
2777 * to be redone if the request is not actually submitted straight
2778 * away, e.g. because a GPU scheduler has deferred it.
2780 if (i915
.enable_execlists
)
2781 ret
= intel_logical_ring_reserve_space(req
);
2783 ret
= intel_ring_reserve_space(req
);
2786 * At this point, the request is fully allocated even if not
2787 * fully prepared. Thus it can be cleaned up using the proper
2790 intel_ring_reserved_space_cancel(req
->ringbuf
);
2791 i915_gem_request_unreference(req
);
2799 kmem_cache_free(dev_priv
->requests
, req
);
2804 * i915_gem_request_alloc - allocate a request structure
2806 * @engine: engine that we wish to issue the request on.
2807 * @ctx: context that the request will be associated with.
2808 * This can be NULL if the request is not directly related to
2809 * any specific user context, in which case this function will
2810 * choose an appropriate context to use.
2812 * Returns a pointer to the allocated request if successful,
2813 * or an error code if not.
2815 struct drm_i915_gem_request
*
2816 i915_gem_request_alloc(struct intel_engine_cs
*engine
,
2817 struct intel_context
*ctx
)
2819 struct drm_i915_gem_request
*req
;
2823 ctx
= to_i915(engine
->dev
)->kernel_context
;
2824 err
= __i915_gem_request_alloc(engine
, ctx
, &req
);
2825 return err
? ERR_PTR(err
) : req
;
2828 struct drm_i915_gem_request
*
2829 i915_gem_find_active_request(struct intel_engine_cs
*engine
)
2831 struct drm_i915_gem_request
*request
;
2833 list_for_each_entry(request
, &engine
->request_list
, list
) {
2834 if (i915_gem_request_completed(request
, false))
2843 static void i915_gem_reset_engine_status(struct drm_i915_private
*dev_priv
,
2844 struct intel_engine_cs
*engine
)
2846 struct drm_i915_gem_request
*request
;
2849 request
= i915_gem_find_active_request(engine
);
2851 if (request
== NULL
)
2854 ring_hung
= engine
->hangcheck
.score
>= HANGCHECK_SCORE_RING_HUNG
;
2856 i915_set_reset_status(dev_priv
, request
->ctx
, ring_hung
);
2858 list_for_each_entry_continue(request
, &engine
->request_list
, list
)
2859 i915_set_reset_status(dev_priv
, request
->ctx
, false);
2862 static void i915_gem_reset_engine_cleanup(struct drm_i915_private
*dev_priv
,
2863 struct intel_engine_cs
*engine
)
2865 struct intel_ringbuffer
*buffer
;
2867 while (!list_empty(&engine
->active_list
)) {
2868 struct drm_i915_gem_object
*obj
;
2870 obj
= list_first_entry(&engine
->active_list
,
2871 struct drm_i915_gem_object
,
2872 engine_list
[engine
->id
]);
2874 i915_gem_object_retire__read(obj
, engine
->id
);
2878 * Clear the execlists queue up before freeing the requests, as those
2879 * are the ones that keep the context and ringbuffer backing objects
2883 if (i915
.enable_execlists
) {
2884 /* Ensure irq handler finishes or is cancelled. */
2885 tasklet_kill(&engine
->irq_tasklet
);
2887 spin_lock_bh(&engine
->execlist_lock
);
2888 /* list_splice_tail_init checks for empty lists */
2889 list_splice_tail_init(&engine
->execlist_queue
,
2890 &engine
->execlist_retired_req_list
);
2891 spin_unlock_bh(&engine
->execlist_lock
);
2893 intel_execlists_retire_requests(engine
);
2897 * We must free the requests after all the corresponding objects have
2898 * been moved off active lists. Which is the same order as the normal
2899 * retire_requests function does. This is important if object hold
2900 * implicit references on things like e.g. ppgtt address spaces through
2903 while (!list_empty(&engine
->request_list
)) {
2904 struct drm_i915_gem_request
*request
;
2906 request
= list_first_entry(&engine
->request_list
,
2907 struct drm_i915_gem_request
,
2910 i915_gem_request_retire(request
);
2913 /* Having flushed all requests from all queues, we know that all
2914 * ringbuffers must now be empty. However, since we do not reclaim
2915 * all space when retiring the request (to prevent HEADs colliding
2916 * with rapid ringbuffer wraparound) the amount of available space
2917 * upon reset is less than when we start. Do one more pass over
2918 * all the ringbuffers to reset last_retired_head.
2920 list_for_each_entry(buffer
, &engine
->buffers
, link
) {
2921 buffer
->last_retired_head
= buffer
->tail
;
2922 intel_ring_update_space(buffer
);
2925 intel_ring_init_seqno(engine
, engine
->last_submitted_seqno
);
2928 void i915_gem_reset(struct drm_device
*dev
)
2930 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2931 struct intel_engine_cs
*engine
;
2934 * Before we free the objects from the requests, we need to inspect
2935 * them for finding the guilty party. As the requests only borrow
2936 * their reference to the objects, the inspection must be done first.
2938 for_each_engine(engine
, dev_priv
)
2939 i915_gem_reset_engine_status(dev_priv
, engine
);
2941 for_each_engine(engine
, dev_priv
)
2942 i915_gem_reset_engine_cleanup(dev_priv
, engine
);
2944 i915_gem_context_reset(dev
);
2946 i915_gem_restore_fences(dev
);
2948 WARN_ON(i915_verify_lists(dev
));
2952 * This function clears the request list as sequence numbers are passed.
2955 i915_gem_retire_requests_ring(struct intel_engine_cs
*engine
)
2957 WARN_ON(i915_verify_lists(engine
->dev
));
2959 /* Retire requests first as we use it above for the early return.
2960 * If we retire requests last, we may use a later seqno and so clear
2961 * the requests lists without clearing the active list, leading to
2964 while (!list_empty(&engine
->request_list
)) {
2965 struct drm_i915_gem_request
*request
;
2967 request
= list_first_entry(&engine
->request_list
,
2968 struct drm_i915_gem_request
,
2971 if (!i915_gem_request_completed(request
, true))
2974 i915_gem_request_retire(request
);
2977 /* Move any buffers on the active list that are no longer referenced
2978 * by the ringbuffer to the flushing/inactive lists as appropriate,
2979 * before we free the context associated with the requests.
2981 while (!list_empty(&engine
->active_list
)) {
2982 struct drm_i915_gem_object
*obj
;
2984 obj
= list_first_entry(&engine
->active_list
,
2985 struct drm_i915_gem_object
,
2986 engine_list
[engine
->id
]);
2988 if (!list_empty(&obj
->last_read_req
[engine
->id
]->list
))
2991 i915_gem_object_retire__read(obj
, engine
->id
);
2994 if (unlikely(engine
->trace_irq_req
&&
2995 i915_gem_request_completed(engine
->trace_irq_req
, true))) {
2996 engine
->irq_put(engine
);
2997 i915_gem_request_assign(&engine
->trace_irq_req
, NULL
);
3000 WARN_ON(i915_verify_lists(engine
->dev
));
3004 i915_gem_retire_requests(struct drm_device
*dev
)
3006 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3007 struct intel_engine_cs
*engine
;
3010 for_each_engine(engine
, dev_priv
) {
3011 i915_gem_retire_requests_ring(engine
);
3012 idle
&= list_empty(&engine
->request_list
);
3013 if (i915
.enable_execlists
) {
3014 spin_lock_bh(&engine
->execlist_lock
);
3015 idle
&= list_empty(&engine
->execlist_queue
);
3016 spin_unlock_bh(&engine
->execlist_lock
);
3018 intel_execlists_retire_requests(engine
);
3023 mod_delayed_work(dev_priv
->wq
,
3024 &dev_priv
->mm
.idle_work
,
3025 msecs_to_jiffies(100));
3031 i915_gem_retire_work_handler(struct work_struct
*work
)
3033 struct drm_i915_private
*dev_priv
=
3034 container_of(work
, typeof(*dev_priv
), mm
.retire_work
.work
);
3035 struct drm_device
*dev
= dev_priv
->dev
;
3038 /* Come back later if the device is busy... */
3040 if (mutex_trylock(&dev
->struct_mutex
)) {
3041 idle
= i915_gem_retire_requests(dev
);
3042 mutex_unlock(&dev
->struct_mutex
);
3045 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
,
3046 round_jiffies_up_relative(HZ
));
3050 i915_gem_idle_work_handler(struct work_struct
*work
)
3052 struct drm_i915_private
*dev_priv
=
3053 container_of(work
, typeof(*dev_priv
), mm
.idle_work
.work
);
3054 struct drm_device
*dev
= dev_priv
->dev
;
3055 struct intel_engine_cs
*engine
;
3057 for_each_engine(engine
, dev_priv
)
3058 if (!list_empty(&engine
->request_list
))
3061 /* we probably should sync with hangcheck here, using cancel_work_sync.
3062 * Also locking seems to be fubar here, engine->request_list is protected
3063 * by dev->struct_mutex. */
3065 intel_mark_idle(dev
);
3067 if (mutex_trylock(&dev
->struct_mutex
)) {
3068 for_each_engine(engine
, dev_priv
)
3069 i915_gem_batch_pool_fini(&engine
->batch_pool
);
3071 mutex_unlock(&dev
->struct_mutex
);
3076 * Ensures that an object will eventually get non-busy by flushing any required
3077 * write domains, emitting any outstanding lazy request and retiring and
3078 * completed requests.
3081 i915_gem_object_flush_active(struct drm_i915_gem_object
*obj
)
3088 for (i
= 0; i
< I915_NUM_ENGINES
; i
++) {
3089 struct drm_i915_gem_request
*req
;
3091 req
= obj
->last_read_req
[i
];
3095 if (list_empty(&req
->list
))
3098 if (i915_gem_request_completed(req
, true)) {
3099 __i915_gem_request_retire__upto(req
);
3101 i915_gem_object_retire__read(obj
, i
);
3109 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
3110 * @DRM_IOCTL_ARGS: standard ioctl arguments
3112 * Returns 0 if successful, else an error is returned with the remaining time in
3113 * the timeout parameter.
3114 * -ETIME: object is still busy after timeout
3115 * -ERESTARTSYS: signal interrupted the wait
3116 * -ENONENT: object doesn't exist
3117 * Also possible, but rare:
3118 * -EAGAIN: GPU wedged
3120 * -ENODEV: Internal IRQ fail
3121 * -E?: The add request failed
3123 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
3124 * non-zero timeout parameter the wait ioctl will wait for the given number of
3125 * nanoseconds on an object becoming unbusy. Since the wait itself does so
3126 * without holding struct_mutex the object may become re-busied before this
3127 * function completes. A similar but shorter * race condition exists in the busy
3131 i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
, struct drm_file
*file
)
3133 struct drm_i915_gem_wait
*args
= data
;
3134 struct drm_i915_gem_object
*obj
;
3135 struct drm_i915_gem_request
*req
[I915_NUM_ENGINES
];
3139 if (args
->flags
!= 0)
3142 ret
= i915_mutex_lock_interruptible(dev
);
3146 obj
= to_intel_bo(drm_gem_object_lookup(file
, args
->bo_handle
));
3147 if (&obj
->base
== NULL
) {
3148 mutex_unlock(&dev
->struct_mutex
);
3152 /* Need to make sure the object gets inactive eventually. */
3153 ret
= i915_gem_object_flush_active(obj
);
3160 /* Do this after OLR check to make sure we make forward progress polling
3161 * on this IOCTL with a timeout == 0 (like busy ioctl)
3163 if (args
->timeout_ns
== 0) {
3168 drm_gem_object_unreference(&obj
->base
);
3170 for (i
= 0; i
< I915_NUM_ENGINES
; i
++) {
3171 if (obj
->last_read_req
[i
] == NULL
)
3174 req
[n
++] = i915_gem_request_reference(obj
->last_read_req
[i
]);
3177 mutex_unlock(&dev
->struct_mutex
);
3179 for (i
= 0; i
< n
; i
++) {
3181 ret
= __i915_wait_request(req
[i
], true,
3182 args
->timeout_ns
> 0 ? &args
->timeout_ns
: NULL
,
3183 to_rps_client(file
));
3184 i915_gem_request_unreference__unlocked(req
[i
]);
3189 drm_gem_object_unreference(&obj
->base
);
3190 mutex_unlock(&dev
->struct_mutex
);
3195 __i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
3196 struct intel_engine_cs
*to
,
3197 struct drm_i915_gem_request
*from_req
,
3198 struct drm_i915_gem_request
**to_req
)
3200 struct intel_engine_cs
*from
;
3203 from
= i915_gem_request_get_engine(from_req
);
3207 if (i915_gem_request_completed(from_req
, true))
3210 if (!i915_semaphore_is_enabled(obj
->base
.dev
)) {
3211 struct drm_i915_private
*i915
= to_i915(obj
->base
.dev
);
3212 ret
= __i915_wait_request(from_req
,
3213 i915
->mm
.interruptible
,
3215 &i915
->rps
.semaphores
);
3219 i915_gem_object_retire_request(obj
, from_req
);
3221 int idx
= intel_ring_sync_index(from
, to
);
3222 u32 seqno
= i915_gem_request_get_seqno(from_req
);
3226 if (seqno
<= from
->semaphore
.sync_seqno
[idx
])
3229 if (*to_req
== NULL
) {
3230 struct drm_i915_gem_request
*req
;
3232 req
= i915_gem_request_alloc(to
, NULL
);
3234 return PTR_ERR(req
);
3239 trace_i915_gem_ring_sync_to(*to_req
, from
, from_req
);
3240 ret
= to
->semaphore
.sync_to(*to_req
, from
, seqno
);
3244 /* We use last_read_req because sync_to()
3245 * might have just caused seqno wrap under
3248 from
->semaphore
.sync_seqno
[idx
] =
3249 i915_gem_request_get_seqno(obj
->last_read_req
[from
->id
]);
3256 * i915_gem_object_sync - sync an object to a ring.
3258 * @obj: object which may be in use on another ring.
3259 * @to: ring we wish to use the object on. May be NULL.
3260 * @to_req: request we wish to use the object for. See below.
3261 * This will be allocated and returned if a request is
3262 * required but not passed in.
3264 * This code is meant to abstract object synchronization with the GPU.
3265 * Calling with NULL implies synchronizing the object with the CPU
3266 * rather than a particular GPU ring. Conceptually we serialise writes
3267 * between engines inside the GPU. We only allow one engine to write
3268 * into a buffer at any time, but multiple readers. To ensure each has
3269 * a coherent view of memory, we must:
3271 * - If there is an outstanding write request to the object, the new
3272 * request must wait for it to complete (either CPU or in hw, requests
3273 * on the same ring will be naturally ordered).
3275 * - If we are a write request (pending_write_domain is set), the new
3276 * request must wait for outstanding read requests to complete.
3278 * For CPU synchronisation (NULL to) no request is required. For syncing with
3279 * rings to_req must be non-NULL. However, a request does not have to be
3280 * pre-allocated. If *to_req is NULL and sync commands will be emitted then a
3281 * request will be allocated automatically and returned through *to_req. Note
3282 * that it is not guaranteed that commands will be emitted (because the system
3283 * might already be idle). Hence there is no need to create a request that
3284 * might never have any work submitted. Note further that if a request is
3285 * returned in *to_req, it is the responsibility of the caller to submit
3286 * that request (after potentially adding more work to it).
3288 * Returns 0 if successful, else propagates up the lower layer error.
3291 i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
3292 struct intel_engine_cs
*to
,
3293 struct drm_i915_gem_request
**to_req
)
3295 const bool readonly
= obj
->base
.pending_write_domain
== 0;
3296 struct drm_i915_gem_request
*req
[I915_NUM_ENGINES
];
3303 return i915_gem_object_wait_rendering(obj
, readonly
);
3307 if (obj
->last_write_req
)
3308 req
[n
++] = obj
->last_write_req
;
3310 for (i
= 0; i
< I915_NUM_ENGINES
; i
++)
3311 if (obj
->last_read_req
[i
])
3312 req
[n
++] = obj
->last_read_req
[i
];
3314 for (i
= 0; i
< n
; i
++) {
3315 ret
= __i915_gem_object_sync(obj
, to
, req
[i
], to_req
);
3323 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object
*obj
)
3325 u32 old_write_domain
, old_read_domains
;
3327 /* Force a pagefault for domain tracking on next user access */
3328 i915_gem_release_mmap(obj
);
3330 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
) == 0)
3333 old_read_domains
= obj
->base
.read_domains
;
3334 old_write_domain
= obj
->base
.write_domain
;
3336 obj
->base
.read_domains
&= ~I915_GEM_DOMAIN_GTT
;
3337 obj
->base
.write_domain
&= ~I915_GEM_DOMAIN_GTT
;
3339 trace_i915_gem_object_change_domain(obj
,
3344 static int __i915_vma_unbind(struct i915_vma
*vma
, bool wait
)
3346 struct drm_i915_gem_object
*obj
= vma
->obj
;
3347 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
3350 if (list_empty(&vma
->obj_link
))
3353 if (!drm_mm_node_allocated(&vma
->node
)) {
3354 i915_gem_vma_destroy(vma
);
3361 BUG_ON(obj
->pages
== NULL
);
3364 ret
= i915_gem_object_wait_rendering(obj
, false);
3369 if (vma
->is_ggtt
&& vma
->ggtt_view
.type
== I915_GGTT_VIEW_NORMAL
) {
3370 i915_gem_object_finish_gtt(obj
);
3372 /* release the fence reg _after_ flushing */
3373 ret
= i915_gem_object_put_fence(obj
);
3378 trace_i915_vma_unbind(vma
);
3380 vma
->vm
->unbind_vma(vma
);
3383 list_del_init(&vma
->vm_link
);
3385 if (vma
->ggtt_view
.type
== I915_GGTT_VIEW_NORMAL
) {
3386 obj
->map_and_fenceable
= false;
3387 } else if (vma
->ggtt_view
.pages
) {
3388 sg_free_table(vma
->ggtt_view
.pages
);
3389 kfree(vma
->ggtt_view
.pages
);
3391 vma
->ggtt_view
.pages
= NULL
;
3394 drm_mm_remove_node(&vma
->node
);
3395 i915_gem_vma_destroy(vma
);
3397 /* Since the unbound list is global, only move to that list if
3398 * no more VMAs exist. */
3399 if (list_empty(&obj
->vma_list
))
3400 list_move_tail(&obj
->global_list
, &dev_priv
->mm
.unbound_list
);
3402 /* And finally now the object is completely decoupled from this vma,
3403 * we can drop its hold on the backing storage and allow it to be
3404 * reaped by the shrinker.
3406 i915_gem_object_unpin_pages(obj
);
3411 int i915_vma_unbind(struct i915_vma
*vma
)
3413 return __i915_vma_unbind(vma
, true);
3416 int __i915_vma_unbind_no_wait(struct i915_vma
*vma
)
3418 return __i915_vma_unbind(vma
, false);
3421 int i915_gpu_idle(struct drm_device
*dev
)
3423 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3424 struct intel_engine_cs
*engine
;
3427 /* Flush everything onto the inactive list. */
3428 for_each_engine(engine
, dev_priv
) {
3429 if (!i915
.enable_execlists
) {
3430 struct drm_i915_gem_request
*req
;
3432 req
= i915_gem_request_alloc(engine
, NULL
);
3434 return PTR_ERR(req
);
3436 ret
= i915_switch_context(req
);
3437 i915_add_request_no_flush(req
);
3442 ret
= intel_engine_idle(engine
);
3447 WARN_ON(i915_verify_lists(dev
));
3451 static bool i915_gem_valid_gtt_space(struct i915_vma
*vma
,
3452 unsigned long cache_level
)
3454 struct drm_mm_node
*gtt_space
= &vma
->node
;
3455 struct drm_mm_node
*other
;
3458 * On some machines we have to be careful when putting differing types
3459 * of snoopable memory together to avoid the prefetcher crossing memory
3460 * domains and dying. During vm initialisation, we decide whether or not
3461 * these constraints apply and set the drm_mm.color_adjust
3464 if (vma
->vm
->mm
.color_adjust
== NULL
)
3467 if (!drm_mm_node_allocated(gtt_space
))
3470 if (list_empty(>t_space
->node_list
))
3473 other
= list_entry(gtt_space
->node_list
.prev
, struct drm_mm_node
, node_list
);
3474 if (other
->allocated
&& !other
->hole_follows
&& other
->color
!= cache_level
)
3477 other
= list_entry(gtt_space
->node_list
.next
, struct drm_mm_node
, node_list
);
3478 if (other
->allocated
&& !gtt_space
->hole_follows
&& other
->color
!= cache_level
)
3485 * Finds free space in the GTT aperture and binds the object or a view of it
3488 static struct i915_vma
*
3489 i915_gem_object_bind_to_vm(struct drm_i915_gem_object
*obj
,
3490 struct i915_address_space
*vm
,
3491 const struct i915_ggtt_view
*ggtt_view
,
3495 struct drm_device
*dev
= obj
->base
.dev
;
3496 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3497 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
3498 u32 fence_alignment
, unfenced_alignment
;
3499 u32 search_flag
, alloc_flag
;
3501 u64 size
, fence_size
;
3502 struct i915_vma
*vma
;
3505 if (i915_is_ggtt(vm
)) {
3508 if (WARN_ON(!ggtt_view
))
3509 return ERR_PTR(-EINVAL
);
3511 view_size
= i915_ggtt_view_size(obj
, ggtt_view
);
3513 fence_size
= i915_gem_get_gtt_size(dev
,
3516 fence_alignment
= i915_gem_get_gtt_alignment(dev
,
3520 unfenced_alignment
= i915_gem_get_gtt_alignment(dev
,
3524 size
= flags
& PIN_MAPPABLE
? fence_size
: view_size
;
3526 fence_size
= i915_gem_get_gtt_size(dev
,
3529 fence_alignment
= i915_gem_get_gtt_alignment(dev
,
3533 unfenced_alignment
=
3534 i915_gem_get_gtt_alignment(dev
,
3538 size
= flags
& PIN_MAPPABLE
? fence_size
: obj
->base
.size
;
3541 start
= flags
& PIN_OFFSET_BIAS
? flags
& PIN_OFFSET_MASK
: 0;
3543 if (flags
& PIN_MAPPABLE
)
3544 end
= min_t(u64
, end
, ggtt
->mappable_end
);
3545 if (flags
& PIN_ZONE_4G
)
3546 end
= min_t(u64
, end
, (1ULL << 32) - PAGE_SIZE
);
3549 alignment
= flags
& PIN_MAPPABLE
? fence_alignment
:
3551 if (flags
& PIN_MAPPABLE
&& alignment
& (fence_alignment
- 1)) {
3552 DRM_DEBUG("Invalid object (view type=%u) alignment requested %u\n",
3553 ggtt_view
? ggtt_view
->type
: 0,
3555 return ERR_PTR(-EINVAL
);
3558 /* If binding the object/GGTT view requires more space than the entire
3559 * aperture has, reject it early before evicting everything in a vain
3560 * attempt to find space.
3563 DRM_DEBUG("Attempting to bind an object (view type=%u) larger than the aperture: size=%llu > %s aperture=%llu\n",
3564 ggtt_view
? ggtt_view
->type
: 0,
3566 flags
& PIN_MAPPABLE
? "mappable" : "total",
3568 return ERR_PTR(-E2BIG
);
3571 ret
= i915_gem_object_get_pages(obj
);
3573 return ERR_PTR(ret
);
3575 i915_gem_object_pin_pages(obj
);
3577 vma
= ggtt_view
? i915_gem_obj_lookup_or_create_ggtt_vma(obj
, ggtt_view
) :
3578 i915_gem_obj_lookup_or_create_vma(obj
, vm
);
3583 if (flags
& PIN_OFFSET_FIXED
) {
3584 uint64_t offset
= flags
& PIN_OFFSET_MASK
;
3586 if (offset
& (alignment
- 1) || offset
+ size
> end
) {
3590 vma
->node
.start
= offset
;
3591 vma
->node
.size
= size
;
3592 vma
->node
.color
= obj
->cache_level
;
3593 ret
= drm_mm_reserve_node(&vm
->mm
, &vma
->node
);
3595 ret
= i915_gem_evict_for_vma(vma
);
3597 ret
= drm_mm_reserve_node(&vm
->mm
, &vma
->node
);
3602 if (flags
& PIN_HIGH
) {
3603 search_flag
= DRM_MM_SEARCH_BELOW
;
3604 alloc_flag
= DRM_MM_CREATE_TOP
;
3606 search_flag
= DRM_MM_SEARCH_DEFAULT
;
3607 alloc_flag
= DRM_MM_CREATE_DEFAULT
;
3611 ret
= drm_mm_insert_node_in_range_generic(&vm
->mm
, &vma
->node
,
3618 ret
= i915_gem_evict_something(dev
, vm
, size
, alignment
,
3628 if (WARN_ON(!i915_gem_valid_gtt_space(vma
, obj
->cache_level
))) {
3630 goto err_remove_node
;
3633 trace_i915_vma_bind(vma
, flags
);
3634 ret
= i915_vma_bind(vma
, obj
->cache_level
, flags
);
3636 goto err_remove_node
;
3638 list_move_tail(&obj
->global_list
, &dev_priv
->mm
.bound_list
);
3639 list_add_tail(&vma
->vm_link
, &vm
->inactive_list
);
3644 drm_mm_remove_node(&vma
->node
);
3646 i915_gem_vma_destroy(vma
);
3649 i915_gem_object_unpin_pages(obj
);
3654 i915_gem_clflush_object(struct drm_i915_gem_object
*obj
,
3657 /* If we don't have a page list set up, then we're not pinned
3658 * to GPU, and we can ignore the cache flush because it'll happen
3659 * again at bind time.
3661 if (obj
->pages
== NULL
)
3665 * Stolen memory is always coherent with the GPU as it is explicitly
3666 * marked as wc by the system, or the system is cache-coherent.
3668 if (obj
->stolen
|| obj
->phys_handle
)
3671 /* If the GPU is snooping the contents of the CPU cache,
3672 * we do not need to manually clear the CPU cache lines. However,
3673 * the caches are only snooped when the render cache is
3674 * flushed/invalidated. As we always have to emit invalidations
3675 * and flushes when moving into and out of the RENDER domain, correct
3676 * snooping behaviour occurs naturally as the result of our domain
3679 if (!force
&& cpu_cache_is_coherent(obj
->base
.dev
, obj
->cache_level
)) {
3680 obj
->cache_dirty
= true;
3684 trace_i915_gem_object_clflush(obj
);
3685 drm_clflush_sg(obj
->pages
);
3686 obj
->cache_dirty
= false;
3691 /** Flushes the GTT write domain for the object if it's dirty. */
3693 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
)
3695 uint32_t old_write_domain
;
3697 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_GTT
)
3700 /* No actual flushing is required for the GTT write domain. Writes
3701 * to it immediately go to main memory as far as we know, so there's
3702 * no chipset flush. It also doesn't land in render cache.
3704 * However, we do have to enforce the order so that all writes through
3705 * the GTT land before any writes to the device, such as updates to
3710 old_write_domain
= obj
->base
.write_domain
;
3711 obj
->base
.write_domain
= 0;
3713 intel_fb_obj_flush(obj
, false, ORIGIN_GTT
);
3715 trace_i915_gem_object_change_domain(obj
,
3716 obj
->base
.read_domains
,
3720 /** Flushes the CPU write domain for the object if it's dirty. */
3722 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
)
3724 uint32_t old_write_domain
;
3726 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
)
3729 if (i915_gem_clflush_object(obj
, obj
->pin_display
))
3730 i915_gem_chipset_flush(obj
->base
.dev
);
3732 old_write_domain
= obj
->base
.write_domain
;
3733 obj
->base
.write_domain
= 0;
3735 intel_fb_obj_flush(obj
, false, ORIGIN_CPU
);
3737 trace_i915_gem_object_change_domain(obj
,
3738 obj
->base
.read_domains
,
3743 * Moves a single object to the GTT read, and possibly write domain.
3745 * This function returns when the move is complete, including waiting on
3749 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
, bool write
)
3751 struct drm_device
*dev
= obj
->base
.dev
;
3752 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3753 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
3754 uint32_t old_write_domain
, old_read_domains
;
3755 struct i915_vma
*vma
;
3758 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_GTT
)
3761 ret
= i915_gem_object_wait_rendering(obj
, !write
);
3765 /* Flush and acquire obj->pages so that we are coherent through
3766 * direct access in memory with previous cached writes through
3767 * shmemfs and that our cache domain tracking remains valid.
3768 * For example, if the obj->filp was moved to swap without us
3769 * being notified and releasing the pages, we would mistakenly
3770 * continue to assume that the obj remained out of the CPU cached
3773 ret
= i915_gem_object_get_pages(obj
);
3777 i915_gem_object_flush_cpu_write_domain(obj
);
3779 /* Serialise direct access to this object with the barriers for
3780 * coherent writes from the GPU, by effectively invalidating the
3781 * GTT domain upon first access.
3783 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
) == 0)
3786 old_write_domain
= obj
->base
.write_domain
;
3787 old_read_domains
= obj
->base
.read_domains
;
3789 /* It should now be out of any other write domains, and we can update
3790 * the domain values for our changes.
3792 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
3793 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
3795 obj
->base
.read_domains
= I915_GEM_DOMAIN_GTT
;
3796 obj
->base
.write_domain
= I915_GEM_DOMAIN_GTT
;
3800 trace_i915_gem_object_change_domain(obj
,
3804 /* And bump the LRU for this access */
3805 vma
= i915_gem_obj_to_ggtt(obj
);
3806 if (vma
&& drm_mm_node_allocated(&vma
->node
) && !obj
->active
)
3807 list_move_tail(&vma
->vm_link
,
3808 &ggtt
->base
.inactive_list
);
3814 * Changes the cache-level of an object across all VMA.
3816 * After this function returns, the object will be in the new cache-level
3817 * across all GTT and the contents of the backing storage will be coherent,
3818 * with respect to the new cache-level. In order to keep the backing storage
3819 * coherent for all users, we only allow a single cache level to be set
3820 * globally on the object and prevent it from being changed whilst the
3821 * hardware is reading from the object. That is if the object is currently
3822 * on the scanout it will be set to uncached (or equivalent display
3823 * cache coherency) and all non-MOCS GPU access will also be uncached so
3824 * that all direct access to the scanout remains coherent.
3826 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
3827 enum i915_cache_level cache_level
)
3829 struct drm_device
*dev
= obj
->base
.dev
;
3830 struct i915_vma
*vma
, *next
;
3834 if (obj
->cache_level
== cache_level
)
3837 /* Inspect the list of currently bound VMA and unbind any that would
3838 * be invalid given the new cache-level. This is principally to
3839 * catch the issue of the CS prefetch crossing page boundaries and
3840 * reading an invalid PTE on older architectures.
3842 list_for_each_entry_safe(vma
, next
, &obj
->vma_list
, obj_link
) {
3843 if (!drm_mm_node_allocated(&vma
->node
))
3846 if (vma
->pin_count
) {
3847 DRM_DEBUG("can not change the cache level of pinned objects\n");
3851 if (!i915_gem_valid_gtt_space(vma
, cache_level
)) {
3852 ret
= i915_vma_unbind(vma
);
3859 /* We can reuse the existing drm_mm nodes but need to change the
3860 * cache-level on the PTE. We could simply unbind them all and
3861 * rebind with the correct cache-level on next use. However since
3862 * we already have a valid slot, dma mapping, pages etc, we may as
3863 * rewrite the PTE in the belief that doing so tramples upon less
3864 * state and so involves less work.
3867 /* Before we change the PTE, the GPU must not be accessing it.
3868 * If we wait upon the object, we know that all the bound
3869 * VMA are no longer active.
3871 ret
= i915_gem_object_wait_rendering(obj
, false);
3875 if (!HAS_LLC(dev
) && cache_level
!= I915_CACHE_NONE
) {
3876 /* Access to snoopable pages through the GTT is
3877 * incoherent and on some machines causes a hard
3878 * lockup. Relinquish the CPU mmaping to force
3879 * userspace to refault in the pages and we can
3880 * then double check if the GTT mapping is still
3881 * valid for that pointer access.
3883 i915_gem_release_mmap(obj
);
3885 /* As we no longer need a fence for GTT access,
3886 * we can relinquish it now (and so prevent having
3887 * to steal a fence from someone else on the next
3888 * fence request). Note GPU activity would have
3889 * dropped the fence as all snoopable access is
3890 * supposed to be linear.
3892 ret
= i915_gem_object_put_fence(obj
);
3896 /* We either have incoherent backing store and
3897 * so no GTT access or the architecture is fully
3898 * coherent. In such cases, existing GTT mmaps
3899 * ignore the cache bit in the PTE and we can
3900 * rewrite it without confusing the GPU or having
3901 * to force userspace to fault back in its mmaps.
3905 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
) {
3906 if (!drm_mm_node_allocated(&vma
->node
))
3909 ret
= i915_vma_bind(vma
, cache_level
, PIN_UPDATE
);
3915 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
)
3916 vma
->node
.color
= cache_level
;
3917 obj
->cache_level
= cache_level
;
3920 /* Flush the dirty CPU caches to the backing storage so that the
3921 * object is now coherent at its new cache level (with respect
3922 * to the access domain).
3924 if (obj
->cache_dirty
&&
3925 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
&&
3926 cpu_write_needs_clflush(obj
)) {
3927 if (i915_gem_clflush_object(obj
, true))
3928 i915_gem_chipset_flush(obj
->base
.dev
);
3934 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
3935 struct drm_file
*file
)
3937 struct drm_i915_gem_caching
*args
= data
;
3938 struct drm_i915_gem_object
*obj
;
3940 obj
= to_intel_bo(drm_gem_object_lookup(file
, args
->handle
));
3941 if (&obj
->base
== NULL
)
3944 switch (obj
->cache_level
) {
3945 case I915_CACHE_LLC
:
3946 case I915_CACHE_L3_LLC
:
3947 args
->caching
= I915_CACHING_CACHED
;
3951 args
->caching
= I915_CACHING_DISPLAY
;
3955 args
->caching
= I915_CACHING_NONE
;
3959 drm_gem_object_unreference_unlocked(&obj
->base
);
3963 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
3964 struct drm_file
*file
)
3966 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3967 struct drm_i915_gem_caching
*args
= data
;
3968 struct drm_i915_gem_object
*obj
;
3969 enum i915_cache_level level
;
3972 switch (args
->caching
) {
3973 case I915_CACHING_NONE
:
3974 level
= I915_CACHE_NONE
;
3976 case I915_CACHING_CACHED
:
3978 * Due to a HW issue on BXT A stepping, GPU stores via a
3979 * snooped mapping may leave stale data in a corresponding CPU
3980 * cacheline, whereas normally such cachelines would get
3983 if (!HAS_LLC(dev
) && !HAS_SNOOP(dev
))
3986 level
= I915_CACHE_LLC
;
3988 case I915_CACHING_DISPLAY
:
3989 level
= HAS_WT(dev
) ? I915_CACHE_WT
: I915_CACHE_NONE
;
3995 intel_runtime_pm_get(dev_priv
);
3997 ret
= i915_mutex_lock_interruptible(dev
);
4001 obj
= to_intel_bo(drm_gem_object_lookup(file
, args
->handle
));
4002 if (&obj
->base
== NULL
) {
4007 ret
= i915_gem_object_set_cache_level(obj
, level
);
4009 drm_gem_object_unreference(&obj
->base
);
4011 mutex_unlock(&dev
->struct_mutex
);
4013 intel_runtime_pm_put(dev_priv
);
4019 * Prepare buffer for display plane (scanout, cursors, etc).
4020 * Can be called from an uninterruptible phase (modesetting) and allows
4021 * any flushes to be pipelined (for pageflips).
4024 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
4026 const struct i915_ggtt_view
*view
)
4028 u32 old_read_domains
, old_write_domain
;
4031 /* Mark the pin_display early so that we account for the
4032 * display coherency whilst setting up the cache domains.
4036 /* The display engine is not coherent with the LLC cache on gen6. As
4037 * a result, we make sure that the pinning that is about to occur is
4038 * done with uncached PTEs. This is lowest common denominator for all
4041 * However for gen6+, we could do better by using the GFDT bit instead
4042 * of uncaching, which would allow us to flush all the LLC-cached data
4043 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
4045 ret
= i915_gem_object_set_cache_level(obj
,
4046 HAS_WT(obj
->base
.dev
) ? I915_CACHE_WT
: I915_CACHE_NONE
);
4048 goto err_unpin_display
;
4050 /* As the user may map the buffer once pinned in the display plane
4051 * (e.g. libkms for the bootup splash), we have to ensure that we
4052 * always use map_and_fenceable for all scanout buffers.
4054 ret
= i915_gem_object_ggtt_pin(obj
, view
, alignment
,
4055 view
->type
== I915_GGTT_VIEW_NORMAL
?
4058 goto err_unpin_display
;
4060 i915_gem_object_flush_cpu_write_domain(obj
);
4062 old_write_domain
= obj
->base
.write_domain
;
4063 old_read_domains
= obj
->base
.read_domains
;
4065 /* It should now be out of any other write domains, and we can update
4066 * the domain values for our changes.
4068 obj
->base
.write_domain
= 0;
4069 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
4071 trace_i915_gem_object_change_domain(obj
,
4083 i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object
*obj
,
4084 const struct i915_ggtt_view
*view
)
4086 if (WARN_ON(obj
->pin_display
== 0))
4089 i915_gem_object_ggtt_unpin_view(obj
, view
);
4095 * Moves a single object to the CPU read, and possibly write domain.
4097 * This function returns when the move is complete, including waiting on
4101 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
)
4103 uint32_t old_write_domain
, old_read_domains
;
4106 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_CPU
)
4109 ret
= i915_gem_object_wait_rendering(obj
, !write
);
4113 i915_gem_object_flush_gtt_write_domain(obj
);
4115 old_write_domain
= obj
->base
.write_domain
;
4116 old_read_domains
= obj
->base
.read_domains
;
4118 /* Flush the CPU cache if it's still invalid. */
4119 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) == 0) {
4120 i915_gem_clflush_object(obj
, false);
4122 obj
->base
.read_domains
|= I915_GEM_DOMAIN_CPU
;
4125 /* It should now be out of any other write domains, and we can update
4126 * the domain values for our changes.
4128 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
4130 /* If we're writing through the CPU, then the GPU read domains will
4131 * need to be invalidated at next use.
4134 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
4135 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
4138 trace_i915_gem_object_change_domain(obj
,
4145 /* Throttle our rendering by waiting until the ring has completed our requests
4146 * emitted over 20 msec ago.
4148 * Note that if we were to use the current jiffies each time around the loop,
4149 * we wouldn't escape the function with any frames outstanding if the time to
4150 * render a frame was over 20ms.
4152 * This should get us reasonable parallelism between CPU and GPU but also
4153 * relatively low latency when blocking on a particular request to finish.
4156 i915_gem_ring_throttle(struct drm_device
*dev
, struct drm_file
*file
)
4158 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4159 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
4160 unsigned long recent_enough
= jiffies
- DRM_I915_THROTTLE_JIFFIES
;
4161 struct drm_i915_gem_request
*request
, *target
= NULL
;
4164 ret
= i915_gem_wait_for_error(&dev_priv
->gpu_error
);
4168 /* ABI: return -EIO if already wedged */
4169 if (i915_terminally_wedged(&dev_priv
->gpu_error
))
4172 spin_lock(&file_priv
->mm
.lock
);
4173 list_for_each_entry(request
, &file_priv
->mm
.request_list
, client_list
) {
4174 if (time_after_eq(request
->emitted_jiffies
, recent_enough
))
4178 * Note that the request might not have been submitted yet.
4179 * In which case emitted_jiffies will be zero.
4181 if (!request
->emitted_jiffies
)
4187 i915_gem_request_reference(target
);
4188 spin_unlock(&file_priv
->mm
.lock
);
4193 ret
= __i915_wait_request(target
, true, NULL
, NULL
);
4195 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, 0);
4197 i915_gem_request_unreference__unlocked(target
);
4203 i915_vma_misplaced(struct i915_vma
*vma
, uint32_t alignment
, uint64_t flags
)
4205 struct drm_i915_gem_object
*obj
= vma
->obj
;
4208 vma
->node
.start
& (alignment
- 1))
4211 if (flags
& PIN_MAPPABLE
&& !obj
->map_and_fenceable
)
4214 if (flags
& PIN_OFFSET_BIAS
&&
4215 vma
->node
.start
< (flags
& PIN_OFFSET_MASK
))
4218 if (flags
& PIN_OFFSET_FIXED
&&
4219 vma
->node
.start
!= (flags
& PIN_OFFSET_MASK
))
4225 void __i915_vma_set_map_and_fenceable(struct i915_vma
*vma
)
4227 struct drm_i915_gem_object
*obj
= vma
->obj
;
4228 bool mappable
, fenceable
;
4229 u32 fence_size
, fence_alignment
;
4231 fence_size
= i915_gem_get_gtt_size(obj
->base
.dev
,
4234 fence_alignment
= i915_gem_get_gtt_alignment(obj
->base
.dev
,
4239 fenceable
= (vma
->node
.size
== fence_size
&&
4240 (vma
->node
.start
& (fence_alignment
- 1)) == 0);
4242 mappable
= (vma
->node
.start
+ fence_size
<=
4243 to_i915(obj
->base
.dev
)->ggtt
.mappable_end
);
4245 obj
->map_and_fenceable
= mappable
&& fenceable
;
4249 i915_gem_object_do_pin(struct drm_i915_gem_object
*obj
,
4250 struct i915_address_space
*vm
,
4251 const struct i915_ggtt_view
*ggtt_view
,
4255 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
4256 struct i915_vma
*vma
;
4260 if (WARN_ON(vm
== &dev_priv
->mm
.aliasing_ppgtt
->base
))
4263 if (WARN_ON(flags
& (PIN_GLOBAL
| PIN_MAPPABLE
) && !i915_is_ggtt(vm
)))
4266 if (WARN_ON((flags
& (PIN_MAPPABLE
| PIN_GLOBAL
)) == PIN_MAPPABLE
))
4269 if (WARN_ON(i915_is_ggtt(vm
) != !!ggtt_view
))
4272 vma
= ggtt_view
? i915_gem_obj_to_ggtt_view(obj
, ggtt_view
) :
4273 i915_gem_obj_to_vma(obj
, vm
);
4276 if (WARN_ON(vma
->pin_count
== DRM_I915_GEM_OBJECT_MAX_PIN_COUNT
))
4279 if (i915_vma_misplaced(vma
, alignment
, flags
)) {
4280 WARN(vma
->pin_count
,
4281 "bo is already pinned in %s with incorrect alignment:"
4282 " offset=%08x %08x, req.alignment=%x, req.map_and_fenceable=%d,"
4283 " obj->map_and_fenceable=%d\n",
4284 ggtt_view
? "ggtt" : "ppgtt",
4285 upper_32_bits(vma
->node
.start
),
4286 lower_32_bits(vma
->node
.start
),
4288 !!(flags
& PIN_MAPPABLE
),
4289 obj
->map_and_fenceable
);
4290 ret
= i915_vma_unbind(vma
);
4298 bound
= vma
? vma
->bound
: 0;
4299 if (vma
== NULL
|| !drm_mm_node_allocated(&vma
->node
)) {
4300 vma
= i915_gem_object_bind_to_vm(obj
, vm
, ggtt_view
, alignment
,
4303 return PTR_ERR(vma
);
4305 ret
= i915_vma_bind(vma
, obj
->cache_level
, flags
);
4310 if (ggtt_view
&& ggtt_view
->type
== I915_GGTT_VIEW_NORMAL
&&
4311 (bound
^ vma
->bound
) & GLOBAL_BIND
) {
4312 __i915_vma_set_map_and_fenceable(vma
);
4313 WARN_ON(flags
& PIN_MAPPABLE
&& !obj
->map_and_fenceable
);
4321 i915_gem_object_pin(struct drm_i915_gem_object
*obj
,
4322 struct i915_address_space
*vm
,
4326 return i915_gem_object_do_pin(obj
, vm
,
4327 i915_is_ggtt(vm
) ? &i915_ggtt_view_normal
: NULL
,
4332 i915_gem_object_ggtt_pin(struct drm_i915_gem_object
*obj
,
4333 const struct i915_ggtt_view
*view
,
4337 struct drm_device
*dev
= obj
->base
.dev
;
4338 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4339 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
4343 return i915_gem_object_do_pin(obj
, &ggtt
->base
, view
,
4344 alignment
, flags
| PIN_GLOBAL
);
4348 i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object
*obj
,
4349 const struct i915_ggtt_view
*view
)
4351 struct i915_vma
*vma
= i915_gem_obj_to_ggtt_view(obj
, view
);
4353 WARN_ON(vma
->pin_count
== 0);
4354 WARN_ON(!i915_gem_obj_ggtt_bound_view(obj
, view
));
4360 i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
4361 struct drm_file
*file
)
4363 struct drm_i915_gem_busy
*args
= data
;
4364 struct drm_i915_gem_object
*obj
;
4367 ret
= i915_mutex_lock_interruptible(dev
);
4371 obj
= to_intel_bo(drm_gem_object_lookup(file
, args
->handle
));
4372 if (&obj
->base
== NULL
) {
4377 /* Count all active objects as busy, even if they are currently not used
4378 * by the gpu. Users of this interface expect objects to eventually
4379 * become non-busy without any further actions, therefore emit any
4380 * necessary flushes here.
4382 ret
= i915_gem_object_flush_active(obj
);
4390 for (i
= 0; i
< I915_NUM_ENGINES
; i
++) {
4391 struct drm_i915_gem_request
*req
;
4393 req
= obj
->last_read_req
[i
];
4395 args
->busy
|= 1 << (16 + req
->engine
->exec_id
);
4397 if (obj
->last_write_req
)
4398 args
->busy
|= obj
->last_write_req
->engine
->exec_id
;
4402 drm_gem_object_unreference(&obj
->base
);
4404 mutex_unlock(&dev
->struct_mutex
);
4409 i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
4410 struct drm_file
*file_priv
)
4412 return i915_gem_ring_throttle(dev
, file_priv
);
4416 i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
4417 struct drm_file
*file_priv
)
4419 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4420 struct drm_i915_gem_madvise
*args
= data
;
4421 struct drm_i915_gem_object
*obj
;
4424 switch (args
->madv
) {
4425 case I915_MADV_DONTNEED
:
4426 case I915_MADV_WILLNEED
:
4432 ret
= i915_mutex_lock_interruptible(dev
);
4436 obj
= to_intel_bo(drm_gem_object_lookup(file_priv
, args
->handle
));
4437 if (&obj
->base
== NULL
) {
4442 if (i915_gem_obj_is_pinned(obj
)) {
4448 obj
->tiling_mode
!= I915_TILING_NONE
&&
4449 dev_priv
->quirks
& QUIRK_PIN_SWIZZLED_PAGES
) {
4450 if (obj
->madv
== I915_MADV_WILLNEED
)
4451 i915_gem_object_unpin_pages(obj
);
4452 if (args
->madv
== I915_MADV_WILLNEED
)
4453 i915_gem_object_pin_pages(obj
);
4456 if (obj
->madv
!= __I915_MADV_PURGED
)
4457 obj
->madv
= args
->madv
;
4459 /* if the object is no longer attached, discard its backing storage */
4460 if (obj
->madv
== I915_MADV_DONTNEED
&& obj
->pages
== NULL
)
4461 i915_gem_object_truncate(obj
);
4463 args
->retained
= obj
->madv
!= __I915_MADV_PURGED
;
4466 drm_gem_object_unreference(&obj
->base
);
4468 mutex_unlock(&dev
->struct_mutex
);
4472 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
4473 const struct drm_i915_gem_object_ops
*ops
)
4477 INIT_LIST_HEAD(&obj
->global_list
);
4478 for (i
= 0; i
< I915_NUM_ENGINES
; i
++)
4479 INIT_LIST_HEAD(&obj
->engine_list
[i
]);
4480 INIT_LIST_HEAD(&obj
->obj_exec_link
);
4481 INIT_LIST_HEAD(&obj
->vma_list
);
4482 INIT_LIST_HEAD(&obj
->batch_pool_link
);
4486 obj
->fence_reg
= I915_FENCE_REG_NONE
;
4487 obj
->madv
= I915_MADV_WILLNEED
;
4489 i915_gem_info_add_obj(obj
->base
.dev
->dev_private
, obj
->base
.size
);
4492 static const struct drm_i915_gem_object_ops i915_gem_object_ops
= {
4493 .flags
= I915_GEM_OBJECT_HAS_STRUCT_PAGE
,
4494 .get_pages
= i915_gem_object_get_pages_gtt
,
4495 .put_pages
= i915_gem_object_put_pages_gtt
,
4498 struct drm_i915_gem_object
*i915_gem_alloc_object(struct drm_device
*dev
,
4501 struct drm_i915_gem_object
*obj
;
4502 struct address_space
*mapping
;
4505 obj
= i915_gem_object_alloc(dev
);
4509 if (drm_gem_object_init(dev
, &obj
->base
, size
) != 0) {
4510 i915_gem_object_free(obj
);
4514 mask
= GFP_HIGHUSER
| __GFP_RECLAIMABLE
;
4515 if (IS_CRESTLINE(dev
) || IS_BROADWATER(dev
)) {
4516 /* 965gm cannot relocate objects above 4GiB. */
4517 mask
&= ~__GFP_HIGHMEM
;
4518 mask
|= __GFP_DMA32
;
4521 mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
4522 mapping_set_gfp_mask(mapping
, mask
);
4524 i915_gem_object_init(obj
, &i915_gem_object_ops
);
4526 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
4527 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
4530 /* On some devices, we can have the GPU use the LLC (the CPU
4531 * cache) for about a 10% performance improvement
4532 * compared to uncached. Graphics requests other than
4533 * display scanout are coherent with the CPU in
4534 * accessing this cache. This means in this mode we
4535 * don't need to clflush on the CPU side, and on the
4536 * GPU side we only need to flush internal caches to
4537 * get data visible to the CPU.
4539 * However, we maintain the display planes as UC, and so
4540 * need to rebind when first used as such.
4542 obj
->cache_level
= I915_CACHE_LLC
;
4544 obj
->cache_level
= I915_CACHE_NONE
;
4546 trace_i915_gem_object_create(obj
);
4551 static bool discard_backing_storage(struct drm_i915_gem_object
*obj
)
4553 /* If we are the last user of the backing storage (be it shmemfs
4554 * pages or stolen etc), we know that the pages are going to be
4555 * immediately released. In this case, we can then skip copying
4556 * back the contents from the GPU.
4559 if (obj
->madv
!= I915_MADV_WILLNEED
)
4562 if (obj
->base
.filp
== NULL
)
4565 /* At first glance, this looks racy, but then again so would be
4566 * userspace racing mmap against close. However, the first external
4567 * reference to the filp can only be obtained through the
4568 * i915_gem_mmap_ioctl() which safeguards us against the user
4569 * acquiring such a reference whilst we are in the middle of
4570 * freeing the object.
4572 return atomic_long_read(&obj
->base
.filp
->f_count
) == 1;
4575 void i915_gem_free_object(struct drm_gem_object
*gem_obj
)
4577 struct drm_i915_gem_object
*obj
= to_intel_bo(gem_obj
);
4578 struct drm_device
*dev
= obj
->base
.dev
;
4579 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4580 struct i915_vma
*vma
, *next
;
4582 intel_runtime_pm_get(dev_priv
);
4584 trace_i915_gem_object_destroy(obj
);
4586 list_for_each_entry_safe(vma
, next
, &obj
->vma_list
, obj_link
) {
4590 ret
= i915_vma_unbind(vma
);
4591 if (WARN_ON(ret
== -ERESTARTSYS
)) {
4592 bool was_interruptible
;
4594 was_interruptible
= dev_priv
->mm
.interruptible
;
4595 dev_priv
->mm
.interruptible
= false;
4597 WARN_ON(i915_vma_unbind(vma
));
4599 dev_priv
->mm
.interruptible
= was_interruptible
;
4603 /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
4604 * before progressing. */
4606 i915_gem_object_unpin_pages(obj
);
4608 WARN_ON(obj
->frontbuffer_bits
);
4610 if (obj
->pages
&& obj
->madv
== I915_MADV_WILLNEED
&&
4611 dev_priv
->quirks
& QUIRK_PIN_SWIZZLED_PAGES
&&
4612 obj
->tiling_mode
!= I915_TILING_NONE
)
4613 i915_gem_object_unpin_pages(obj
);
4615 if (WARN_ON(obj
->pages_pin_count
))
4616 obj
->pages_pin_count
= 0;
4617 if (discard_backing_storage(obj
))
4618 obj
->madv
= I915_MADV_DONTNEED
;
4619 i915_gem_object_put_pages(obj
);
4620 i915_gem_object_free_mmap_offset(obj
);
4624 if (obj
->base
.import_attach
)
4625 drm_prime_gem_destroy(&obj
->base
, NULL
);
4627 if (obj
->ops
->release
)
4628 obj
->ops
->release(obj
);
4630 drm_gem_object_release(&obj
->base
);
4631 i915_gem_info_remove_obj(dev_priv
, obj
->base
.size
);
4634 i915_gem_object_free(obj
);
4636 intel_runtime_pm_put(dev_priv
);
4639 struct i915_vma
*i915_gem_obj_to_vma(struct drm_i915_gem_object
*obj
,
4640 struct i915_address_space
*vm
)
4642 struct i915_vma
*vma
;
4643 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
) {
4644 if (vma
->ggtt_view
.type
== I915_GGTT_VIEW_NORMAL
&&
4651 struct i915_vma
*i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object
*obj
,
4652 const struct i915_ggtt_view
*view
)
4654 struct drm_device
*dev
= obj
->base
.dev
;
4655 struct drm_i915_private
*dev_priv
= to_i915(dev
);
4656 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
4657 struct i915_vma
*vma
;
4661 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
)
4662 if (vma
->vm
== &ggtt
->base
&&
4663 i915_ggtt_view_equal(&vma
->ggtt_view
, view
))
4668 void i915_gem_vma_destroy(struct i915_vma
*vma
)
4670 WARN_ON(vma
->node
.allocated
);
4672 /* Keep the vma as a placeholder in the execbuffer reservation lists */
4673 if (!list_empty(&vma
->exec_list
))
4677 i915_ppgtt_put(i915_vm_to_ppgtt(vma
->vm
));
4679 list_del(&vma
->obj_link
);
4681 kmem_cache_free(to_i915(vma
->obj
->base
.dev
)->vmas
, vma
);
4685 i915_gem_stop_engines(struct drm_device
*dev
)
4687 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4688 struct intel_engine_cs
*engine
;
4690 for_each_engine(engine
, dev_priv
)
4691 dev_priv
->gt
.stop_engine(engine
);
4695 i915_gem_suspend(struct drm_device
*dev
)
4697 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4700 mutex_lock(&dev
->struct_mutex
);
4701 ret
= i915_gpu_idle(dev
);
4705 i915_gem_retire_requests(dev
);
4707 i915_gem_stop_engines(dev
);
4708 mutex_unlock(&dev
->struct_mutex
);
4710 cancel_delayed_work_sync(&dev_priv
->gpu_error
.hangcheck_work
);
4711 cancel_delayed_work_sync(&dev_priv
->mm
.retire_work
);
4712 flush_delayed_work(&dev_priv
->mm
.idle_work
);
4714 /* Assert that we sucessfully flushed all the work and
4715 * reset the GPU back to its idle, low power state.
4717 WARN_ON(dev_priv
->mm
.busy
);
4722 mutex_unlock(&dev
->struct_mutex
);
4726 int i915_gem_l3_remap(struct drm_i915_gem_request
*req
, int slice
)
4728 struct intel_engine_cs
*engine
= req
->engine
;
4729 struct drm_device
*dev
= engine
->dev
;
4730 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4731 u32
*remap_info
= dev_priv
->l3_parity
.remap_info
[slice
];
4734 if (!HAS_L3_DPF(dev
) || !remap_info
)
4737 ret
= intel_ring_begin(req
, GEN7_L3LOG_SIZE
/ 4 * 3);
4742 * Note: We do not worry about the concurrent register cacheline hang
4743 * here because no other code should access these registers other than
4744 * at initialization time.
4746 for (i
= 0; i
< GEN7_L3LOG_SIZE
/ 4; i
++) {
4747 intel_ring_emit(engine
, MI_LOAD_REGISTER_IMM(1));
4748 intel_ring_emit_reg(engine
, GEN7_L3LOG(slice
, i
));
4749 intel_ring_emit(engine
, remap_info
[i
]);
4752 intel_ring_advance(engine
);
4757 void i915_gem_init_swizzling(struct drm_device
*dev
)
4759 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4761 if (INTEL_INFO(dev
)->gen
< 5 ||
4762 dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_NONE
)
4765 I915_WRITE(DISP_ARB_CTL
, I915_READ(DISP_ARB_CTL
) |
4766 DISP_TILE_SURFACE_SWIZZLING
);
4771 I915_WRITE(TILECTL
, I915_READ(TILECTL
) | TILECTL_SWZCTL
);
4773 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB
));
4774 else if (IS_GEN7(dev
))
4775 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB
));
4776 else if (IS_GEN8(dev
))
4777 I915_WRITE(GAMTARBMODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW
));
4782 static void init_unused_ring(struct drm_device
*dev
, u32 base
)
4784 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4786 I915_WRITE(RING_CTL(base
), 0);
4787 I915_WRITE(RING_HEAD(base
), 0);
4788 I915_WRITE(RING_TAIL(base
), 0);
4789 I915_WRITE(RING_START(base
), 0);
4792 static void init_unused_rings(struct drm_device
*dev
)
4795 init_unused_ring(dev
, PRB1_BASE
);
4796 init_unused_ring(dev
, SRB0_BASE
);
4797 init_unused_ring(dev
, SRB1_BASE
);
4798 init_unused_ring(dev
, SRB2_BASE
);
4799 init_unused_ring(dev
, SRB3_BASE
);
4800 } else if (IS_GEN2(dev
)) {
4801 init_unused_ring(dev
, SRB0_BASE
);
4802 init_unused_ring(dev
, SRB1_BASE
);
4803 } else if (IS_GEN3(dev
)) {
4804 init_unused_ring(dev
, PRB1_BASE
);
4805 init_unused_ring(dev
, PRB2_BASE
);
4809 int i915_gem_init_engines(struct drm_device
*dev
)
4811 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4814 ret
= intel_init_render_ring_buffer(dev
);
4819 ret
= intel_init_bsd_ring_buffer(dev
);
4821 goto cleanup_render_ring
;
4825 ret
= intel_init_blt_ring_buffer(dev
);
4827 goto cleanup_bsd_ring
;
4830 if (HAS_VEBOX(dev
)) {
4831 ret
= intel_init_vebox_ring_buffer(dev
);
4833 goto cleanup_blt_ring
;
4836 if (HAS_BSD2(dev
)) {
4837 ret
= intel_init_bsd2_ring_buffer(dev
);
4839 goto cleanup_vebox_ring
;
4845 intel_cleanup_engine(&dev_priv
->engine
[VECS
]);
4847 intel_cleanup_engine(&dev_priv
->engine
[BCS
]);
4849 intel_cleanup_engine(&dev_priv
->engine
[VCS
]);
4850 cleanup_render_ring
:
4851 intel_cleanup_engine(&dev_priv
->engine
[RCS
]);
4857 i915_gem_init_hw(struct drm_device
*dev
)
4859 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4860 struct intel_engine_cs
*engine
;
4863 if (INTEL_INFO(dev
)->gen
< 6 && !intel_enable_gtt())
4866 /* Double layer security blanket, see i915_gem_init() */
4867 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
4869 if (HAS_EDRAM(dev
) && INTEL_GEN(dev_priv
) < 9)
4870 I915_WRITE(HSW_IDICR
, I915_READ(HSW_IDICR
) | IDIHASHMSK(0xf));
4872 if (IS_HASWELL(dev
))
4873 I915_WRITE(MI_PREDICATE_RESULT_2
, IS_HSW_GT3(dev
) ?
4874 LOWER_SLICE_ENABLED
: LOWER_SLICE_DISABLED
);
4876 if (HAS_PCH_NOP(dev
)) {
4877 if (IS_IVYBRIDGE(dev
)) {
4878 u32 temp
= I915_READ(GEN7_MSG_CTL
);
4879 temp
&= ~(WAIT_FOR_PCH_FLR_ACK
| WAIT_FOR_PCH_RESET_ACK
);
4880 I915_WRITE(GEN7_MSG_CTL
, temp
);
4881 } else if (INTEL_INFO(dev
)->gen
>= 7) {
4882 u32 temp
= I915_READ(HSW_NDE_RSTWRN_OPT
);
4883 temp
&= ~RESET_PCH_HANDSHAKE_ENABLE
;
4884 I915_WRITE(HSW_NDE_RSTWRN_OPT
, temp
);
4888 i915_gem_init_swizzling(dev
);
4891 * At least 830 can leave some of the unused rings
4892 * "active" (ie. head != tail) after resume which
4893 * will prevent c3 entry. Makes sure all unused rings
4896 init_unused_rings(dev
);
4898 BUG_ON(!dev_priv
->kernel_context
);
4900 ret
= i915_ppgtt_init_hw(dev
);
4902 DRM_ERROR("PPGTT enable HW failed %d\n", ret
);
4906 /* Need to do basic initialisation of all rings first: */
4907 for_each_engine(engine
, dev_priv
) {
4908 ret
= engine
->init_hw(engine
);
4913 intel_mocs_init_l3cc_table(dev
);
4915 /* We can't enable contexts until all firmware is loaded */
4916 if (HAS_GUC_UCODE(dev
)) {
4917 ret
= intel_guc_ucode_load(dev
);
4919 DRM_ERROR("Failed to initialize GuC, error %d\n", ret
);
4926 * Increment the next seqno by 0x100 so we have a visible break
4927 * on re-initialisation
4929 ret
= i915_gem_set_seqno(dev
, dev_priv
->next_seqno
+0x100);
4933 /* Now it is safe to go back round and do everything else: */
4934 for_each_engine(engine
, dev_priv
) {
4935 struct drm_i915_gem_request
*req
;
4937 req
= i915_gem_request_alloc(engine
, NULL
);
4943 if (engine
->id
== RCS
) {
4944 for (j
= 0; j
< NUM_L3_SLICES(dev
); j
++) {
4945 ret
= i915_gem_l3_remap(req
, j
);
4951 ret
= i915_ppgtt_init_ring(req
);
4955 ret
= i915_gem_context_enable(req
);
4960 i915_add_request_no_flush(req
);
4962 DRM_ERROR("Failed to enable %s, error=%d\n",
4964 i915_gem_cleanup_engines(dev
);
4970 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
4974 int i915_gem_init(struct drm_device
*dev
)
4976 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4979 i915
.enable_execlists
= intel_sanitize_enable_execlists(dev
,
4980 i915
.enable_execlists
);
4982 mutex_lock(&dev
->struct_mutex
);
4984 if (!i915
.enable_execlists
) {
4985 dev_priv
->gt
.execbuf_submit
= i915_gem_ringbuffer_submission
;
4986 dev_priv
->gt
.init_engines
= i915_gem_init_engines
;
4987 dev_priv
->gt
.cleanup_engine
= intel_cleanup_engine
;
4988 dev_priv
->gt
.stop_engine
= intel_stop_engine
;
4990 dev_priv
->gt
.execbuf_submit
= intel_execlists_submission
;
4991 dev_priv
->gt
.init_engines
= intel_logical_rings_init
;
4992 dev_priv
->gt
.cleanup_engine
= intel_logical_ring_cleanup
;
4993 dev_priv
->gt
.stop_engine
= intel_logical_ring_stop
;
4996 /* This is just a security blanket to placate dragons.
4997 * On some systems, we very sporadically observe that the first TLBs
4998 * used by the CS may be stale, despite us poking the TLB reset. If
4999 * we hold the forcewake during initialisation these problems
5000 * just magically go away.
5002 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
5004 ret
= i915_gem_init_userptr(dev
);
5008 i915_gem_init_ggtt(dev
);
5010 ret
= i915_gem_context_init(dev
);
5014 ret
= dev_priv
->gt
.init_engines(dev
);
5018 ret
= i915_gem_init_hw(dev
);
5020 /* Allow ring initialisation to fail by marking the GPU as
5021 * wedged. But we only want to do this where the GPU is angry,
5022 * for all other failure, such as an allocation failure, bail.
5024 DRM_ERROR("Failed to initialize GPU, declaring it wedged\n");
5025 atomic_or(I915_WEDGED
, &dev_priv
->gpu_error
.reset_counter
);
5030 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
5031 mutex_unlock(&dev
->struct_mutex
);
5037 i915_gem_cleanup_engines(struct drm_device
*dev
)
5039 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5040 struct intel_engine_cs
*engine
;
5042 for_each_engine(engine
, dev_priv
)
5043 dev_priv
->gt
.cleanup_engine(engine
);
5045 if (i915
.enable_execlists
)
5047 * Neither the BIOS, ourselves or any other kernel
5048 * expects the system to be in execlists mode on startup,
5049 * so we need to reset the GPU back to legacy mode.
5051 intel_gpu_reset(dev
, ALL_ENGINES
);
5055 init_engine_lists(struct intel_engine_cs
*engine
)
5057 INIT_LIST_HEAD(&engine
->active_list
);
5058 INIT_LIST_HEAD(&engine
->request_list
);
5062 i915_gem_load_init_fences(struct drm_i915_private
*dev_priv
)
5064 struct drm_device
*dev
= dev_priv
->dev
;
5066 if (INTEL_INFO(dev_priv
)->gen
>= 7 && !IS_VALLEYVIEW(dev_priv
) &&
5067 !IS_CHERRYVIEW(dev_priv
))
5068 dev_priv
->num_fence_regs
= 32;
5069 else if (INTEL_INFO(dev_priv
)->gen
>= 4 || IS_I945G(dev_priv
) ||
5070 IS_I945GM(dev_priv
) || IS_G33(dev_priv
))
5071 dev_priv
->num_fence_regs
= 16;
5073 dev_priv
->num_fence_regs
= 8;
5075 if (intel_vgpu_active(dev
))
5076 dev_priv
->num_fence_regs
=
5077 I915_READ(vgtif_reg(avail_rs
.fence_num
));
5079 /* Initialize fence registers to zero */
5080 i915_gem_restore_fences(dev
);
5082 i915_gem_detect_bit_6_swizzle(dev
);
5086 i915_gem_load_init(struct drm_device
*dev
)
5088 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5092 kmem_cache_create("i915_gem_object",
5093 sizeof(struct drm_i915_gem_object
), 0,
5097 kmem_cache_create("i915_gem_vma",
5098 sizeof(struct i915_vma
), 0,
5101 dev_priv
->requests
=
5102 kmem_cache_create("i915_gem_request",
5103 sizeof(struct drm_i915_gem_request
), 0,
5107 INIT_LIST_HEAD(&dev_priv
->vm_list
);
5108 INIT_LIST_HEAD(&dev_priv
->context_list
);
5109 INIT_LIST_HEAD(&dev_priv
->mm
.unbound_list
);
5110 INIT_LIST_HEAD(&dev_priv
->mm
.bound_list
);
5111 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
5112 for (i
= 0; i
< I915_NUM_ENGINES
; i
++)
5113 init_engine_lists(&dev_priv
->engine
[i
]);
5114 for (i
= 0; i
< I915_MAX_NUM_FENCES
; i
++)
5115 INIT_LIST_HEAD(&dev_priv
->fence_regs
[i
].lru_list
);
5116 INIT_DELAYED_WORK(&dev_priv
->mm
.retire_work
,
5117 i915_gem_retire_work_handler
);
5118 INIT_DELAYED_WORK(&dev_priv
->mm
.idle_work
,
5119 i915_gem_idle_work_handler
);
5120 init_waitqueue_head(&dev_priv
->gpu_error
.reset_queue
);
5122 dev_priv
->relative_constants_mode
= I915_EXEC_CONSTANTS_REL_GENERAL
;
5125 * Set initial sequence number for requests.
5126 * Using this number allows the wraparound to happen early,
5127 * catching any obvious problems.
5129 dev_priv
->next_seqno
= ((u32
)~0 - 0x1100);
5130 dev_priv
->last_seqno
= ((u32
)~0 - 0x1101);
5132 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
5134 init_waitqueue_head(&dev_priv
->pending_flip_queue
);
5136 dev_priv
->mm
.interruptible
= true;
5138 mutex_init(&dev_priv
->fb_tracking
.lock
);
5141 void i915_gem_load_cleanup(struct drm_device
*dev
)
5143 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5145 kmem_cache_destroy(dev_priv
->requests
);
5146 kmem_cache_destroy(dev_priv
->vmas
);
5147 kmem_cache_destroy(dev_priv
->objects
);
5150 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
)
5152 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
5154 /* Clean up our request list when the client is going away, so that
5155 * later retire_requests won't dereference our soon-to-be-gone
5158 spin_lock(&file_priv
->mm
.lock
);
5159 while (!list_empty(&file_priv
->mm
.request_list
)) {
5160 struct drm_i915_gem_request
*request
;
5162 request
= list_first_entry(&file_priv
->mm
.request_list
,
5163 struct drm_i915_gem_request
,
5165 list_del(&request
->client_list
);
5166 request
->file_priv
= NULL
;
5168 spin_unlock(&file_priv
->mm
.lock
);
5170 if (!list_empty(&file_priv
->rps
.link
)) {
5171 spin_lock(&to_i915(dev
)->rps
.client_lock
);
5172 list_del(&file_priv
->rps
.link
);
5173 spin_unlock(&to_i915(dev
)->rps
.client_lock
);
5177 int i915_gem_open(struct drm_device
*dev
, struct drm_file
*file
)
5179 struct drm_i915_file_private
*file_priv
;
5182 DRM_DEBUG_DRIVER("\n");
5184 file_priv
= kzalloc(sizeof(*file_priv
), GFP_KERNEL
);
5188 file
->driver_priv
= file_priv
;
5189 file_priv
->dev_priv
= dev
->dev_private
;
5190 file_priv
->file
= file
;
5191 INIT_LIST_HEAD(&file_priv
->rps
.link
);
5193 spin_lock_init(&file_priv
->mm
.lock
);
5194 INIT_LIST_HEAD(&file_priv
->mm
.request_list
);
5196 file_priv
->bsd_ring
= -1;
5198 ret
= i915_gem_context_open(dev
, file
);
5206 * i915_gem_track_fb - update frontbuffer tracking
5207 * @old: current GEM buffer for the frontbuffer slots
5208 * @new: new GEM buffer for the frontbuffer slots
5209 * @frontbuffer_bits: bitmask of frontbuffer slots
5211 * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them
5212 * from @old and setting them in @new. Both @old and @new can be NULL.
5214 void i915_gem_track_fb(struct drm_i915_gem_object
*old
,
5215 struct drm_i915_gem_object
*new,
5216 unsigned frontbuffer_bits
)
5219 WARN_ON(!mutex_is_locked(&old
->base
.dev
->struct_mutex
));
5220 WARN_ON(!(old
->frontbuffer_bits
& frontbuffer_bits
));
5221 old
->frontbuffer_bits
&= ~frontbuffer_bits
;
5225 WARN_ON(!mutex_is_locked(&new->base
.dev
->struct_mutex
));
5226 WARN_ON(new->frontbuffer_bits
& frontbuffer_bits
);
5227 new->frontbuffer_bits
|= frontbuffer_bits
;
5231 /* All the new VM stuff */
5232 u64
i915_gem_obj_offset(struct drm_i915_gem_object
*o
,
5233 struct i915_address_space
*vm
)
5235 struct drm_i915_private
*dev_priv
= o
->base
.dev
->dev_private
;
5236 struct i915_vma
*vma
;
5238 WARN_ON(vm
== &dev_priv
->mm
.aliasing_ppgtt
->base
);
5240 list_for_each_entry(vma
, &o
->vma_list
, obj_link
) {
5242 vma
->ggtt_view
.type
!= I915_GGTT_VIEW_NORMAL
)
5245 return vma
->node
.start
;
5248 WARN(1, "%s vma for this object not found.\n",
5249 i915_is_ggtt(vm
) ? "global" : "ppgtt");
5253 u64
i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object
*o
,
5254 const struct i915_ggtt_view
*view
)
5256 struct drm_i915_private
*dev_priv
= to_i915(o
->base
.dev
);
5257 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
5258 struct i915_vma
*vma
;
5260 list_for_each_entry(vma
, &o
->vma_list
, obj_link
)
5261 if (vma
->vm
== &ggtt
->base
&&
5262 i915_ggtt_view_equal(&vma
->ggtt_view
, view
))
5263 return vma
->node
.start
;
5265 WARN(1, "global vma for this object not found. (view=%u)\n", view
->type
);
5269 bool i915_gem_obj_bound(struct drm_i915_gem_object
*o
,
5270 struct i915_address_space
*vm
)
5272 struct i915_vma
*vma
;
5274 list_for_each_entry(vma
, &o
->vma_list
, obj_link
) {
5276 vma
->ggtt_view
.type
!= I915_GGTT_VIEW_NORMAL
)
5278 if (vma
->vm
== vm
&& drm_mm_node_allocated(&vma
->node
))
5285 bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object
*o
,
5286 const struct i915_ggtt_view
*view
)
5288 struct drm_i915_private
*dev_priv
= to_i915(o
->base
.dev
);
5289 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
5290 struct i915_vma
*vma
;
5292 list_for_each_entry(vma
, &o
->vma_list
, obj_link
)
5293 if (vma
->vm
== &ggtt
->base
&&
5294 i915_ggtt_view_equal(&vma
->ggtt_view
, view
) &&
5295 drm_mm_node_allocated(&vma
->node
))
5301 bool i915_gem_obj_bound_any(struct drm_i915_gem_object
*o
)
5303 struct i915_vma
*vma
;
5305 list_for_each_entry(vma
, &o
->vma_list
, obj_link
)
5306 if (drm_mm_node_allocated(&vma
->node
))
5312 unsigned long i915_gem_obj_size(struct drm_i915_gem_object
*o
,
5313 struct i915_address_space
*vm
)
5315 struct drm_i915_private
*dev_priv
= o
->base
.dev
->dev_private
;
5316 struct i915_vma
*vma
;
5318 WARN_ON(vm
== &dev_priv
->mm
.aliasing_ppgtt
->base
);
5320 BUG_ON(list_empty(&o
->vma_list
));
5322 list_for_each_entry(vma
, &o
->vma_list
, obj_link
) {
5324 vma
->ggtt_view
.type
!= I915_GGTT_VIEW_NORMAL
)
5327 return vma
->node
.size
;
5332 bool i915_gem_obj_is_pinned(struct drm_i915_gem_object
*obj
)
5334 struct i915_vma
*vma
;
5335 list_for_each_entry(vma
, &obj
->vma_list
, obj_link
)
5336 if (vma
->pin_count
> 0)
5342 /* Like i915_gem_object_get_page(), but mark the returned page dirty */
5344 i915_gem_object_get_dirty_page(struct drm_i915_gem_object
*obj
, int n
)
5348 /* Only default objects have per-page dirty tracking */
5349 if (WARN_ON((obj
->ops
->flags
& I915_GEM_OBJECT_HAS_STRUCT_PAGE
) == 0))
5352 page
= i915_gem_object_get_page(obj
, n
);
5353 set_page_dirty(page
);
5357 /* Allocate a new GEM object and fill it with the supplied data */
5358 struct drm_i915_gem_object
*
5359 i915_gem_object_create_from_data(struct drm_device
*dev
,
5360 const void *data
, size_t size
)
5362 struct drm_i915_gem_object
*obj
;
5363 struct sg_table
*sg
;
5367 obj
= i915_gem_alloc_object(dev
, round_up(size
, PAGE_SIZE
));
5368 if (IS_ERR_OR_NULL(obj
))
5371 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
5375 ret
= i915_gem_object_get_pages(obj
);
5379 i915_gem_object_pin_pages(obj
);
5381 bytes
= sg_copy_from_buffer(sg
->sgl
, sg
->nents
, (void *)data
, size
);
5382 obj
->dirty
= 1; /* Backing store is now out of date */
5383 i915_gem_object_unpin_pages(obj
);
5385 if (WARN_ON(bytes
!= size
)) {
5386 DRM_ERROR("Incomplete copy, wrote %zu of %zu", bytes
, size
);
5394 drm_gem_object_unreference(&obj
->base
);
5395 return ERR_PTR(ret
);