2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/slab.h>
35 #include <linux/swap.h>
36 #include <linux/pci.h>
38 struct change_domains
{
39 uint32_t invalidate_domains
;
40 uint32_t flush_domains
;
44 static uint32_t i915_gem_get_gtt_alignment(struct drm_i915_gem_object
*obj_priv
);
45 static uint32_t i915_gem_get_gtt_size(struct drm_i915_gem_object
*obj_priv
);
47 static int i915_gem_object_flush_gpu_write_domain(struct drm_gem_object
*obj
,
49 static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object
*obj
);
50 static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object
*obj
);
51 static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object
*obj
,
53 static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object
*obj
,
56 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object
*obj
);
57 static int i915_gem_object_wait_rendering(struct drm_gem_object
*obj
,
59 static int i915_gem_object_bind_to_gtt(struct drm_gem_object
*obj
,
61 bool map_and_fenceable
);
62 static void i915_gem_clear_fence_reg(struct drm_gem_object
*obj
);
63 static int i915_gem_phys_pwrite(struct drm_device
*dev
, struct drm_gem_object
*obj
,
64 struct drm_i915_gem_pwrite
*args
,
65 struct drm_file
*file_priv
);
66 static void i915_gem_free_object_tail(struct drm_gem_object
*obj
);
68 static int i915_gem_inactive_shrink(struct shrinker
*shrinker
,
73 /* some bookkeeping */
74 static void i915_gem_info_add_obj(struct drm_i915_private
*dev_priv
,
77 dev_priv
->mm
.object_count
++;
78 dev_priv
->mm
.object_memory
+= size
;
81 static void i915_gem_info_remove_obj(struct drm_i915_private
*dev_priv
,
84 dev_priv
->mm
.object_count
--;
85 dev_priv
->mm
.object_memory
-= size
;
88 static void i915_gem_info_add_gtt(struct drm_i915_private
*dev_priv
,
89 struct drm_i915_gem_object
*obj
)
91 dev_priv
->mm
.gtt_count
++;
92 dev_priv
->mm
.gtt_memory
+= obj
->gtt_space
->size
;
93 if (obj
->gtt_offset
< dev_priv
->mm
.gtt_mappable_end
) {
94 dev_priv
->mm
.mappable_gtt_used
+=
95 min_t(size_t, obj
->gtt_space
->size
,
96 dev_priv
->mm
.gtt_mappable_end
- obj
->gtt_offset
);
100 static void i915_gem_info_remove_gtt(struct drm_i915_private
*dev_priv
,
101 struct drm_i915_gem_object
*obj
)
103 dev_priv
->mm
.gtt_count
--;
104 dev_priv
->mm
.gtt_memory
-= obj
->gtt_space
->size
;
105 if (obj
->gtt_offset
< dev_priv
->mm
.gtt_mappable_end
) {
106 dev_priv
->mm
.mappable_gtt_used
-=
107 min_t(size_t, obj
->gtt_space
->size
,
108 dev_priv
->mm
.gtt_mappable_end
- obj
->gtt_offset
);
113 * Update the mappable working set counters. Call _only_ when there is a change
114 * in one of (pin|fault)_mappable and update *_mappable _before_ calling.
115 * @mappable: new state the changed mappable flag (either pin_ or fault_).
118 i915_gem_info_update_mappable(struct drm_i915_private
*dev_priv
,
119 struct drm_i915_gem_object
*obj
,
123 if (obj
->pin_mappable
&& obj
->fault_mappable
)
124 /* Combined state was already mappable. */
126 dev_priv
->mm
.gtt_mappable_count
++;
127 dev_priv
->mm
.gtt_mappable_memory
+= obj
->gtt_space
->size
;
129 if (obj
->pin_mappable
|| obj
->fault_mappable
)
130 /* Combined state still mappable. */
132 dev_priv
->mm
.gtt_mappable_count
--;
133 dev_priv
->mm
.gtt_mappable_memory
-= obj
->gtt_space
->size
;
137 static void i915_gem_info_add_pin(struct drm_i915_private
*dev_priv
,
138 struct drm_i915_gem_object
*obj
,
141 dev_priv
->mm
.pin_count
++;
142 dev_priv
->mm
.pin_memory
+= obj
->gtt_space
->size
;
144 obj
->pin_mappable
= true;
145 i915_gem_info_update_mappable(dev_priv
, obj
, true);
149 static void i915_gem_info_remove_pin(struct drm_i915_private
*dev_priv
,
150 struct drm_i915_gem_object
*obj
)
152 dev_priv
->mm
.pin_count
--;
153 dev_priv
->mm
.pin_memory
-= obj
->gtt_space
->size
;
154 if (obj
->pin_mappable
) {
155 obj
->pin_mappable
= false;
156 i915_gem_info_update_mappable(dev_priv
, obj
, false);
161 i915_gem_check_is_wedged(struct drm_device
*dev
)
163 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
164 struct completion
*x
= &dev_priv
->error_completion
;
168 if (!atomic_read(&dev_priv
->mm
.wedged
))
171 ret
= wait_for_completion_interruptible(x
);
175 /* Success, we reset the GPU! */
176 if (!atomic_read(&dev_priv
->mm
.wedged
))
179 /* GPU is hung, bump the completion count to account for
180 * the token we just consumed so that we never hit zero and
181 * end up waiting upon a subsequent completion event that
184 spin_lock_irqsave(&x
->wait
.lock
, flags
);
186 spin_unlock_irqrestore(&x
->wait
.lock
, flags
);
190 static int i915_mutex_lock_interruptible(struct drm_device
*dev
)
192 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
195 ret
= i915_gem_check_is_wedged(dev
);
199 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
203 if (atomic_read(&dev_priv
->mm
.wedged
)) {
204 mutex_unlock(&dev
->struct_mutex
);
208 WARN_ON(i915_verify_lists(dev
));
213 i915_gem_object_is_inactive(struct drm_i915_gem_object
*obj_priv
)
215 return obj_priv
->gtt_space
&&
217 obj_priv
->pin_count
== 0;
220 int i915_gem_do_init(struct drm_device
*dev
,
222 unsigned long mappable_end
,
225 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
228 (start
& (PAGE_SIZE
- 1)) != 0 ||
229 (end
& (PAGE_SIZE
- 1)) != 0) {
233 drm_mm_init(&dev_priv
->mm
.gtt_space
, start
,
236 dev_priv
->mm
.gtt_total
= end
- start
;
237 dev_priv
->mm
.mappable_gtt_total
= min(end
, mappable_end
) - start
;
238 dev_priv
->mm
.gtt_mappable_end
= mappable_end
;
244 i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
245 struct drm_file
*file_priv
)
247 struct drm_i915_gem_init
*args
= data
;
250 mutex_lock(&dev
->struct_mutex
);
251 ret
= i915_gem_do_init(dev
, args
->gtt_start
, args
->gtt_end
, args
->gtt_end
);
252 mutex_unlock(&dev
->struct_mutex
);
258 i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
259 struct drm_file
*file_priv
)
261 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
262 struct drm_i915_gem_get_aperture
*args
= data
;
264 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
267 mutex_lock(&dev
->struct_mutex
);
268 args
->aper_size
= dev_priv
->mm
.gtt_total
;
269 args
->aper_available_size
= args
->aper_size
- dev_priv
->mm
.pin_memory
;
270 mutex_unlock(&dev
->struct_mutex
);
277 * Creates a new mm object and returns a handle to it.
280 i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
281 struct drm_file
*file_priv
)
283 struct drm_i915_gem_create
*args
= data
;
284 struct drm_gem_object
*obj
;
288 args
->size
= roundup(args
->size
, PAGE_SIZE
);
290 /* Allocate the new object */
291 obj
= i915_gem_alloc_object(dev
, args
->size
);
295 ret
= drm_gem_handle_create(file_priv
, obj
, &handle
);
297 drm_gem_object_release(obj
);
298 i915_gem_info_remove_obj(dev
->dev_private
, obj
->size
);
303 /* drop reference from allocate - handle holds it now */
304 drm_gem_object_unreference(obj
);
305 trace_i915_gem_object_create(obj
);
307 args
->handle
= handle
;
311 static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object
*obj
)
313 drm_i915_private_t
*dev_priv
= obj
->dev
->dev_private
;
314 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
316 return dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_9_10_17
&&
317 obj_priv
->tiling_mode
!= I915_TILING_NONE
;
321 slow_shmem_copy(struct page
*dst_page
,
323 struct page
*src_page
,
327 char *dst_vaddr
, *src_vaddr
;
329 dst_vaddr
= kmap(dst_page
);
330 src_vaddr
= kmap(src_page
);
332 memcpy(dst_vaddr
+ dst_offset
, src_vaddr
+ src_offset
, length
);
339 slow_shmem_bit17_copy(struct page
*gpu_page
,
341 struct page
*cpu_page
,
346 char *gpu_vaddr
, *cpu_vaddr
;
348 /* Use the unswizzled path if this page isn't affected. */
349 if ((page_to_phys(gpu_page
) & (1 << 17)) == 0) {
351 return slow_shmem_copy(cpu_page
, cpu_offset
,
352 gpu_page
, gpu_offset
, length
);
354 return slow_shmem_copy(gpu_page
, gpu_offset
,
355 cpu_page
, cpu_offset
, length
);
358 gpu_vaddr
= kmap(gpu_page
);
359 cpu_vaddr
= kmap(cpu_page
);
361 /* Copy the data, XORing A6 with A17 (1). The user already knows he's
362 * XORing with the other bits (A9 for Y, A9 and A10 for X)
365 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
366 int this_length
= min(cacheline_end
- gpu_offset
, length
);
367 int swizzled_gpu_offset
= gpu_offset
^ 64;
370 memcpy(cpu_vaddr
+ cpu_offset
,
371 gpu_vaddr
+ swizzled_gpu_offset
,
374 memcpy(gpu_vaddr
+ swizzled_gpu_offset
,
375 cpu_vaddr
+ cpu_offset
,
378 cpu_offset
+= this_length
;
379 gpu_offset
+= this_length
;
380 length
-= this_length
;
388 * This is the fast shmem pread path, which attempts to copy_from_user directly
389 * from the backing pages of the object to the user's address space. On a
390 * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
393 i915_gem_shmem_pread_fast(struct drm_device
*dev
, struct drm_gem_object
*obj
,
394 struct drm_i915_gem_pread
*args
,
395 struct drm_file
*file_priv
)
397 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
398 struct address_space
*mapping
= obj
->filp
->f_path
.dentry
->d_inode
->i_mapping
;
401 char __user
*user_data
;
402 int page_offset
, page_length
;
404 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
407 obj_priv
= to_intel_bo(obj
);
408 offset
= args
->offset
;
415 /* Operation in this page
417 * page_offset = offset within page
418 * page_length = bytes to copy for this page
420 page_offset
= offset
& (PAGE_SIZE
-1);
421 page_length
= remain
;
422 if ((page_offset
+ remain
) > PAGE_SIZE
)
423 page_length
= PAGE_SIZE
- page_offset
;
425 page
= read_cache_page_gfp(mapping
, offset
>> PAGE_SHIFT
,
426 GFP_HIGHUSER
| __GFP_RECLAIMABLE
);
428 return PTR_ERR(page
);
430 vaddr
= kmap_atomic(page
);
431 ret
= __copy_to_user_inatomic(user_data
,
434 kunmap_atomic(vaddr
);
436 mark_page_accessed(page
);
437 page_cache_release(page
);
441 remain
-= page_length
;
442 user_data
+= page_length
;
443 offset
+= page_length
;
450 * This is the fallback shmem pread path, which allocates temporary storage
451 * in kernel space to copy_to_user into outside of the struct_mutex, so we
452 * can copy out of the object's backing pages while holding the struct mutex
453 * and not take page faults.
456 i915_gem_shmem_pread_slow(struct drm_device
*dev
, struct drm_gem_object
*obj
,
457 struct drm_i915_gem_pread
*args
,
458 struct drm_file
*file_priv
)
460 struct address_space
*mapping
= obj
->filp
->f_path
.dentry
->d_inode
->i_mapping
;
461 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
462 struct mm_struct
*mm
= current
->mm
;
463 struct page
**user_pages
;
465 loff_t offset
, pinned_pages
, i
;
466 loff_t first_data_page
, last_data_page
, num_pages
;
467 int shmem_page_offset
;
468 int data_page_index
, data_page_offset
;
471 uint64_t data_ptr
= args
->data_ptr
;
472 int do_bit17_swizzling
;
476 /* Pin the user pages containing the data. We can't fault while
477 * holding the struct mutex, yet we want to hold it while
478 * dereferencing the user data.
480 first_data_page
= data_ptr
/ PAGE_SIZE
;
481 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
482 num_pages
= last_data_page
- first_data_page
+ 1;
484 user_pages
= drm_malloc_ab(num_pages
, sizeof(struct page
*));
485 if (user_pages
== NULL
)
488 mutex_unlock(&dev
->struct_mutex
);
489 down_read(&mm
->mmap_sem
);
490 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
491 num_pages
, 1, 0, user_pages
, NULL
);
492 up_read(&mm
->mmap_sem
);
493 mutex_lock(&dev
->struct_mutex
);
494 if (pinned_pages
< num_pages
) {
499 ret
= i915_gem_object_set_cpu_read_domain_range(obj
,
505 do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
507 obj_priv
= to_intel_bo(obj
);
508 offset
= args
->offset
;
513 /* Operation in this page
515 * shmem_page_offset = offset within page in shmem file
516 * data_page_index = page number in get_user_pages return
517 * data_page_offset = offset with data_page_index page.
518 * page_length = bytes to copy for this page
520 shmem_page_offset
= offset
& ~PAGE_MASK
;
521 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
522 data_page_offset
= data_ptr
& ~PAGE_MASK
;
524 page_length
= remain
;
525 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
526 page_length
= PAGE_SIZE
- shmem_page_offset
;
527 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
528 page_length
= PAGE_SIZE
- data_page_offset
;
530 page
= read_cache_page_gfp(mapping
, offset
>> PAGE_SHIFT
,
531 GFP_HIGHUSER
| __GFP_RECLAIMABLE
);
533 return PTR_ERR(page
);
535 if (do_bit17_swizzling
) {
536 slow_shmem_bit17_copy(page
,
538 user_pages
[data_page_index
],
543 slow_shmem_copy(user_pages
[data_page_index
],
550 mark_page_accessed(page
);
551 page_cache_release(page
);
553 remain
-= page_length
;
554 data_ptr
+= page_length
;
555 offset
+= page_length
;
559 for (i
= 0; i
< pinned_pages
; i
++) {
560 SetPageDirty(user_pages
[i
]);
561 mark_page_accessed(user_pages
[i
]);
562 page_cache_release(user_pages
[i
]);
564 drm_free_large(user_pages
);
570 * Reads data from the object referenced by handle.
572 * On error, the contents of *data are undefined.
575 i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
576 struct drm_file
*file_priv
)
578 struct drm_i915_gem_pread
*args
= data
;
579 struct drm_gem_object
*obj
;
580 struct drm_i915_gem_object
*obj_priv
;
586 if (!access_ok(VERIFY_WRITE
,
587 (char __user
*)(uintptr_t)args
->data_ptr
,
591 ret
= fault_in_pages_writeable((char __user
*)(uintptr_t)args
->data_ptr
,
596 ret
= i915_mutex_lock_interruptible(dev
);
600 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
605 obj_priv
= to_intel_bo(obj
);
607 /* Bounds check source. */
608 if (args
->offset
> obj
->size
|| args
->size
> obj
->size
- args
->offset
) {
613 ret
= i915_gem_object_set_cpu_read_domain_range(obj
,
620 if (!i915_gem_object_needs_bit17_swizzle(obj
))
621 ret
= i915_gem_shmem_pread_fast(dev
, obj
, args
, file_priv
);
623 ret
= i915_gem_shmem_pread_slow(dev
, obj
, args
, file_priv
);
626 drm_gem_object_unreference(obj
);
628 mutex_unlock(&dev
->struct_mutex
);
632 /* This is the fast write path which cannot handle
633 * page faults in the source data
637 fast_user_write(struct io_mapping
*mapping
,
638 loff_t page_base
, int page_offset
,
639 char __user
*user_data
,
643 unsigned long unwritten
;
645 vaddr_atomic
= io_mapping_map_atomic_wc(mapping
, page_base
);
646 unwritten
= __copy_from_user_inatomic_nocache(vaddr_atomic
+ page_offset
,
648 io_mapping_unmap_atomic(vaddr_atomic
);
652 /* Here's the write path which can sleep for
657 slow_kernel_write(struct io_mapping
*mapping
,
658 loff_t gtt_base
, int gtt_offset
,
659 struct page
*user_page
, int user_offset
,
662 char __iomem
*dst_vaddr
;
665 dst_vaddr
= io_mapping_map_wc(mapping
, gtt_base
);
666 src_vaddr
= kmap(user_page
);
668 memcpy_toio(dst_vaddr
+ gtt_offset
,
669 src_vaddr
+ user_offset
,
673 io_mapping_unmap(dst_vaddr
);
677 * This is the fast pwrite path, where we copy the data directly from the
678 * user into the GTT, uncached.
681 i915_gem_gtt_pwrite_fast(struct drm_device
*dev
, struct drm_gem_object
*obj
,
682 struct drm_i915_gem_pwrite
*args
,
683 struct drm_file
*file_priv
)
685 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
686 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
688 loff_t offset
, page_base
;
689 char __user
*user_data
;
690 int page_offset
, page_length
;
692 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
695 obj_priv
= to_intel_bo(obj
);
696 offset
= obj_priv
->gtt_offset
+ args
->offset
;
699 /* Operation in this page
701 * page_base = page offset within aperture
702 * page_offset = offset within page
703 * page_length = bytes to copy for this page
705 page_base
= (offset
& ~(PAGE_SIZE
-1));
706 page_offset
= offset
& (PAGE_SIZE
-1);
707 page_length
= remain
;
708 if ((page_offset
+ remain
) > PAGE_SIZE
)
709 page_length
= PAGE_SIZE
- page_offset
;
711 /* If we get a fault while copying data, then (presumably) our
712 * source page isn't available. Return the error and we'll
713 * retry in the slow path.
715 if (fast_user_write(dev_priv
->mm
.gtt_mapping
, page_base
,
716 page_offset
, user_data
, page_length
))
720 remain
-= page_length
;
721 user_data
+= page_length
;
722 offset
+= page_length
;
729 * This is the fallback GTT pwrite path, which uses get_user_pages to pin
730 * the memory and maps it using kmap_atomic for copying.
732 * This code resulted in x11perf -rgb10text consuming about 10% more CPU
733 * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
736 i915_gem_gtt_pwrite_slow(struct drm_device
*dev
, struct drm_gem_object
*obj
,
737 struct drm_i915_gem_pwrite
*args
,
738 struct drm_file
*file_priv
)
740 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
741 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
743 loff_t gtt_page_base
, offset
;
744 loff_t first_data_page
, last_data_page
, num_pages
;
745 loff_t pinned_pages
, i
;
746 struct page
**user_pages
;
747 struct mm_struct
*mm
= current
->mm
;
748 int gtt_page_offset
, data_page_offset
, data_page_index
, page_length
;
750 uint64_t data_ptr
= args
->data_ptr
;
754 /* Pin the user pages containing the data. We can't fault while
755 * holding the struct mutex, and all of the pwrite implementations
756 * want to hold it while dereferencing the user data.
758 first_data_page
= data_ptr
/ PAGE_SIZE
;
759 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
760 num_pages
= last_data_page
- first_data_page
+ 1;
762 user_pages
= drm_malloc_ab(num_pages
, sizeof(struct page
*));
763 if (user_pages
== NULL
)
766 mutex_unlock(&dev
->struct_mutex
);
767 down_read(&mm
->mmap_sem
);
768 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
769 num_pages
, 0, 0, user_pages
, NULL
);
770 up_read(&mm
->mmap_sem
);
771 mutex_lock(&dev
->struct_mutex
);
772 if (pinned_pages
< num_pages
) {
774 goto out_unpin_pages
;
777 ret
= i915_gem_object_set_to_gtt_domain(obj
, 1);
779 goto out_unpin_pages
;
781 obj_priv
= to_intel_bo(obj
);
782 offset
= obj_priv
->gtt_offset
+ args
->offset
;
785 /* Operation in this page
787 * gtt_page_base = page offset within aperture
788 * gtt_page_offset = offset within page in aperture
789 * data_page_index = page number in get_user_pages return
790 * data_page_offset = offset with data_page_index page.
791 * page_length = bytes to copy for this page
793 gtt_page_base
= offset
& PAGE_MASK
;
794 gtt_page_offset
= offset
& ~PAGE_MASK
;
795 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
796 data_page_offset
= data_ptr
& ~PAGE_MASK
;
798 page_length
= remain
;
799 if ((gtt_page_offset
+ page_length
) > PAGE_SIZE
)
800 page_length
= PAGE_SIZE
- gtt_page_offset
;
801 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
802 page_length
= PAGE_SIZE
- data_page_offset
;
804 slow_kernel_write(dev_priv
->mm
.gtt_mapping
,
805 gtt_page_base
, gtt_page_offset
,
806 user_pages
[data_page_index
],
810 remain
-= page_length
;
811 offset
+= page_length
;
812 data_ptr
+= page_length
;
816 for (i
= 0; i
< pinned_pages
; i
++)
817 page_cache_release(user_pages
[i
]);
818 drm_free_large(user_pages
);
824 * This is the fast shmem pwrite path, which attempts to directly
825 * copy_from_user into the kmapped pages backing the object.
828 i915_gem_shmem_pwrite_fast(struct drm_device
*dev
, struct drm_gem_object
*obj
,
829 struct drm_i915_gem_pwrite
*args
,
830 struct drm_file
*file_priv
)
832 struct address_space
*mapping
= obj
->filp
->f_path
.dentry
->d_inode
->i_mapping
;
833 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
836 char __user
*user_data
;
837 int page_offset
, page_length
;
839 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
842 obj_priv
= to_intel_bo(obj
);
843 offset
= args
->offset
;
851 /* Operation in this page
853 * page_offset = offset within page
854 * page_length = bytes to copy for this page
856 page_offset
= offset
& (PAGE_SIZE
-1);
857 page_length
= remain
;
858 if ((page_offset
+ remain
) > PAGE_SIZE
)
859 page_length
= PAGE_SIZE
- page_offset
;
861 page
= read_cache_page_gfp(mapping
, offset
>> PAGE_SHIFT
,
862 GFP_HIGHUSER
| __GFP_RECLAIMABLE
);
864 return PTR_ERR(page
);
866 vaddr
= kmap_atomic(page
, KM_USER0
);
867 ret
= __copy_from_user_inatomic(vaddr
+ page_offset
,
870 kunmap_atomic(vaddr
, KM_USER0
);
872 set_page_dirty(page
);
873 mark_page_accessed(page
);
874 page_cache_release(page
);
876 /* If we get a fault while copying data, then (presumably) our
877 * source page isn't available. Return the error and we'll
878 * retry in the slow path.
883 remain
-= page_length
;
884 user_data
+= page_length
;
885 offset
+= page_length
;
892 * This is the fallback shmem pwrite path, which uses get_user_pages to pin
893 * the memory and maps it using kmap_atomic for copying.
895 * This avoids taking mmap_sem for faulting on the user's address while the
896 * struct_mutex is held.
899 i915_gem_shmem_pwrite_slow(struct drm_device
*dev
, struct drm_gem_object
*obj
,
900 struct drm_i915_gem_pwrite
*args
,
901 struct drm_file
*file_priv
)
903 struct address_space
*mapping
= obj
->filp
->f_path
.dentry
->d_inode
->i_mapping
;
904 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
905 struct mm_struct
*mm
= current
->mm
;
906 struct page
**user_pages
;
908 loff_t offset
, pinned_pages
, i
;
909 loff_t first_data_page
, last_data_page
, num_pages
;
910 int shmem_page_offset
;
911 int data_page_index
, data_page_offset
;
914 uint64_t data_ptr
= args
->data_ptr
;
915 int do_bit17_swizzling
;
919 /* Pin the user pages containing the data. We can't fault while
920 * holding the struct mutex, and all of the pwrite implementations
921 * want to hold it while dereferencing the user data.
923 first_data_page
= data_ptr
/ PAGE_SIZE
;
924 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
925 num_pages
= last_data_page
- first_data_page
+ 1;
927 user_pages
= drm_malloc_ab(num_pages
, sizeof(struct page
*));
928 if (user_pages
== NULL
)
931 mutex_unlock(&dev
->struct_mutex
);
932 down_read(&mm
->mmap_sem
);
933 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
934 num_pages
, 0, 0, user_pages
, NULL
);
935 up_read(&mm
->mmap_sem
);
936 mutex_lock(&dev
->struct_mutex
);
937 if (pinned_pages
< num_pages
) {
942 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
946 do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
948 obj_priv
= to_intel_bo(obj
);
949 offset
= args
->offset
;
955 /* Operation in this page
957 * shmem_page_offset = offset within page in shmem file
958 * data_page_index = page number in get_user_pages return
959 * data_page_offset = offset with data_page_index page.
960 * page_length = bytes to copy for this page
962 shmem_page_offset
= offset
& ~PAGE_MASK
;
963 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
964 data_page_offset
= data_ptr
& ~PAGE_MASK
;
966 page_length
= remain
;
967 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
968 page_length
= PAGE_SIZE
- shmem_page_offset
;
969 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
970 page_length
= PAGE_SIZE
- data_page_offset
;
972 page
= read_cache_page_gfp(mapping
, offset
>> PAGE_SHIFT
,
973 GFP_HIGHUSER
| __GFP_RECLAIMABLE
);
979 if (do_bit17_swizzling
) {
980 slow_shmem_bit17_copy(page
,
982 user_pages
[data_page_index
],
987 slow_shmem_copy(page
,
989 user_pages
[data_page_index
],
994 set_page_dirty(page
);
995 mark_page_accessed(page
);
996 page_cache_release(page
);
998 remain
-= page_length
;
999 data_ptr
+= page_length
;
1000 offset
+= page_length
;
1004 for (i
= 0; i
< pinned_pages
; i
++)
1005 page_cache_release(user_pages
[i
]);
1006 drm_free_large(user_pages
);
1012 * Writes data to the object referenced by handle.
1014 * On error, the contents of the buffer that were to be modified are undefined.
1017 i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
1018 struct drm_file
*file
)
1020 struct drm_i915_gem_pwrite
*args
= data
;
1021 struct drm_gem_object
*obj
;
1022 struct drm_i915_gem_object
*obj_priv
;
1025 if (args
->size
== 0)
1028 if (!access_ok(VERIFY_READ
,
1029 (char __user
*)(uintptr_t)args
->data_ptr
,
1033 ret
= fault_in_pages_readable((char __user
*)(uintptr_t)args
->data_ptr
,
1038 ret
= i915_mutex_lock_interruptible(dev
);
1042 obj
= drm_gem_object_lookup(dev
, file
, args
->handle
);
1047 obj_priv
= to_intel_bo(obj
);
1049 /* Bounds check destination. */
1050 if (args
->offset
> obj
->size
|| args
->size
> obj
->size
- args
->offset
) {
1055 /* We can only do the GTT pwrite on untiled buffers, as otherwise
1056 * it would end up going through the fenced access, and we'll get
1057 * different detiling behavior between reading and writing.
1058 * pread/pwrite currently are reading and writing from the CPU
1059 * perspective, requiring manual detiling by the client.
1061 if (obj_priv
->phys_obj
)
1062 ret
= i915_gem_phys_pwrite(dev
, obj
, args
, file
);
1063 else if (obj_priv
->tiling_mode
== I915_TILING_NONE
&&
1064 obj_priv
->gtt_space
&&
1065 obj
->write_domain
!= I915_GEM_DOMAIN_CPU
) {
1066 ret
= i915_gem_object_pin(obj
, 0, true);
1070 ret
= i915_gem_object_set_to_gtt_domain(obj
, 1);
1074 ret
= i915_gem_gtt_pwrite_fast(dev
, obj
, args
, file
);
1076 ret
= i915_gem_gtt_pwrite_slow(dev
, obj
, args
, file
);
1079 i915_gem_object_unpin(obj
);
1081 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
1086 if (!i915_gem_object_needs_bit17_swizzle(obj
))
1087 ret
= i915_gem_shmem_pwrite_fast(dev
, obj
, args
, file
);
1089 ret
= i915_gem_shmem_pwrite_slow(dev
, obj
, args
, file
);
1093 drm_gem_object_unreference(obj
);
1095 mutex_unlock(&dev
->struct_mutex
);
1100 * Called when user space prepares to use an object with the CPU, either
1101 * through the mmap ioctl's mapping or a GTT mapping.
1104 i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
1105 struct drm_file
*file_priv
)
1107 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1108 struct drm_i915_gem_set_domain
*args
= data
;
1109 struct drm_gem_object
*obj
;
1110 struct drm_i915_gem_object
*obj_priv
;
1111 uint32_t read_domains
= args
->read_domains
;
1112 uint32_t write_domain
= args
->write_domain
;
1115 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1118 /* Only handle setting domains to types used by the CPU. */
1119 if (write_domain
& I915_GEM_GPU_DOMAINS
)
1122 if (read_domains
& I915_GEM_GPU_DOMAINS
)
1125 /* Having something in the write domain implies it's in the read
1126 * domain, and only that read domain. Enforce that in the request.
1128 if (write_domain
!= 0 && read_domains
!= write_domain
)
1131 ret
= i915_mutex_lock_interruptible(dev
);
1135 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1140 obj_priv
= to_intel_bo(obj
);
1142 intel_mark_busy(dev
, obj
);
1144 if (read_domains
& I915_GEM_DOMAIN_GTT
) {
1145 ret
= i915_gem_object_set_to_gtt_domain(obj
, write_domain
!= 0);
1147 /* Update the LRU on the fence for the CPU access that's
1150 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
) {
1151 struct drm_i915_fence_reg
*reg
=
1152 &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
1153 list_move_tail(®
->lru_list
,
1154 &dev_priv
->mm
.fence_list
);
1157 /* Silently promote "you're not bound, there was nothing to do"
1158 * to success, since the client was just asking us to
1159 * make sure everything was done.
1164 ret
= i915_gem_object_set_to_cpu_domain(obj
, write_domain
!= 0);
1167 /* Maintain LRU order of "inactive" objects */
1168 if (ret
== 0 && i915_gem_object_is_inactive(obj_priv
))
1169 list_move_tail(&obj_priv
->mm_list
, &dev_priv
->mm
.inactive_list
);
1171 drm_gem_object_unreference(obj
);
1173 mutex_unlock(&dev
->struct_mutex
);
1178 * Called when user space has done writes to this buffer
1181 i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1182 struct drm_file
*file_priv
)
1184 struct drm_i915_gem_sw_finish
*args
= data
;
1185 struct drm_gem_object
*obj
;
1188 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1191 ret
= i915_mutex_lock_interruptible(dev
);
1195 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1201 /* Pinned buffers may be scanout, so flush the cache */
1202 if (to_intel_bo(obj
)->pin_count
)
1203 i915_gem_object_flush_cpu_write_domain(obj
);
1205 drm_gem_object_unreference(obj
);
1207 mutex_unlock(&dev
->struct_mutex
);
1212 * Maps the contents of an object, returning the address it is mapped
1215 * While the mapping holds a reference on the contents of the object, it doesn't
1216 * imply a ref on the object itself.
1219 i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1220 struct drm_file
*file_priv
)
1222 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1223 struct drm_i915_gem_mmap
*args
= data
;
1224 struct drm_gem_object
*obj
;
1228 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1231 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1235 if (obj
->size
> dev_priv
->mm
.gtt_mappable_end
) {
1236 drm_gem_object_unreference_unlocked(obj
);
1240 offset
= args
->offset
;
1242 down_write(¤t
->mm
->mmap_sem
);
1243 addr
= do_mmap(obj
->filp
, 0, args
->size
,
1244 PROT_READ
| PROT_WRITE
, MAP_SHARED
,
1246 up_write(¤t
->mm
->mmap_sem
);
1247 drm_gem_object_unreference_unlocked(obj
);
1248 if (IS_ERR((void *)addr
))
1251 args
->addr_ptr
= (uint64_t) addr
;
1257 * i915_gem_fault - fault a page into the GTT
1258 * vma: VMA in question
1261 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1262 * from userspace. The fault handler takes care of binding the object to
1263 * the GTT (if needed), allocating and programming a fence register (again,
1264 * only if needed based on whether the old reg is still valid or the object
1265 * is tiled) and inserting a new PTE into the faulting process.
1267 * Note that the faulting process may involve evicting existing objects
1268 * from the GTT and/or fence registers to make room. So performance may
1269 * suffer if the GTT working set is large or there are few fence registers
1272 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
)
1274 struct drm_gem_object
*obj
= vma
->vm_private_data
;
1275 struct drm_device
*dev
= obj
->dev
;
1276 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1277 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1278 pgoff_t page_offset
;
1281 bool write
= !!(vmf
->flags
& FAULT_FLAG_WRITE
);
1283 /* We don't use vmf->pgoff since that has the fake offset */
1284 page_offset
= ((unsigned long)vmf
->virtual_address
- vma
->vm_start
) >>
1287 /* Now bind it into the GTT if needed */
1288 mutex_lock(&dev
->struct_mutex
);
1289 BUG_ON(obj_priv
->pin_count
&& !obj_priv
->pin_mappable
);
1291 if (obj_priv
->gtt_space
) {
1292 if (!obj_priv
->map_and_fenceable
) {
1293 ret
= i915_gem_object_unbind(obj
);
1299 if (!obj_priv
->gtt_space
) {
1300 ret
= i915_gem_object_bind_to_gtt(obj
, 0, true);
1305 ret
= i915_gem_object_set_to_gtt_domain(obj
, write
);
1309 if (!obj_priv
->fault_mappable
) {
1310 obj_priv
->fault_mappable
= true;
1311 i915_gem_info_update_mappable(dev_priv
, obj_priv
, true);
1314 /* Need a new fence register? */
1315 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
) {
1316 ret
= i915_gem_object_get_fence_reg(obj
, true);
1321 if (i915_gem_object_is_inactive(obj_priv
))
1322 list_move_tail(&obj_priv
->mm_list
, &dev_priv
->mm
.inactive_list
);
1324 pfn
= ((dev
->agp
->base
+ obj_priv
->gtt_offset
) >> PAGE_SHIFT
) +
1327 /* Finally, remap it using the new GTT offset */
1328 ret
= vm_insert_pfn(vma
, (unsigned long)vmf
->virtual_address
, pfn
);
1330 mutex_unlock(&dev
->struct_mutex
);
1337 return VM_FAULT_NOPAGE
;
1339 return VM_FAULT_OOM
;
1341 return VM_FAULT_SIGBUS
;
1346 * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1347 * @obj: obj in question
1349 * GEM memory mapping works by handing back to userspace a fake mmap offset
1350 * it can use in a subsequent mmap(2) call. The DRM core code then looks
1351 * up the object based on the offset and sets up the various memory mapping
1354 * This routine allocates and attaches a fake offset for @obj.
1357 i915_gem_create_mmap_offset(struct drm_gem_object
*obj
)
1359 struct drm_device
*dev
= obj
->dev
;
1360 struct drm_gem_mm
*mm
= dev
->mm_private
;
1361 struct drm_map_list
*list
;
1362 struct drm_local_map
*map
;
1365 /* Set the object up for mmap'ing */
1366 list
= &obj
->map_list
;
1367 list
->map
= kzalloc(sizeof(struct drm_map_list
), GFP_KERNEL
);
1372 map
->type
= _DRM_GEM
;
1373 map
->size
= obj
->size
;
1376 /* Get a DRM GEM mmap offset allocated... */
1377 list
->file_offset_node
= drm_mm_search_free(&mm
->offset_manager
,
1378 obj
->size
/ PAGE_SIZE
, 0, 0);
1379 if (!list
->file_offset_node
) {
1380 DRM_ERROR("failed to allocate offset for bo %d\n", obj
->name
);
1385 list
->file_offset_node
= drm_mm_get_block(list
->file_offset_node
,
1386 obj
->size
/ PAGE_SIZE
, 0);
1387 if (!list
->file_offset_node
) {
1392 list
->hash
.key
= list
->file_offset_node
->start
;
1393 ret
= drm_ht_insert_item(&mm
->offset_hash
, &list
->hash
);
1395 DRM_ERROR("failed to add to map hash\n");
1402 drm_mm_put_block(list
->file_offset_node
);
1411 * i915_gem_release_mmap - remove physical page mappings
1412 * @obj: obj in question
1414 * Preserve the reservation of the mmapping with the DRM core code, but
1415 * relinquish ownership of the pages back to the system.
1417 * It is vital that we remove the page mapping if we have mapped a tiled
1418 * object through the GTT and then lose the fence register due to
1419 * resource pressure. Similarly if the object has been moved out of the
1420 * aperture, than pages mapped into userspace must be revoked. Removing the
1421 * mapping will then trigger a page fault on the next user access, allowing
1422 * fixup by i915_gem_fault().
1425 i915_gem_release_mmap(struct drm_gem_object
*obj
)
1427 struct drm_device
*dev
= obj
->dev
;
1428 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1429 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1431 if (unlikely(obj
->map_list
.map
&& dev
->dev_mapping
))
1432 unmap_mapping_range(dev
->dev_mapping
,
1433 (loff_t
)obj
->map_list
.hash
.key
<<PAGE_SHIFT
,
1436 if (obj_priv
->fault_mappable
) {
1437 obj_priv
->fault_mappable
= false;
1438 i915_gem_info_update_mappable(dev_priv
, obj_priv
, false);
1443 i915_gem_free_mmap_offset(struct drm_gem_object
*obj
)
1445 struct drm_device
*dev
= obj
->dev
;
1446 struct drm_gem_mm
*mm
= dev
->mm_private
;
1447 struct drm_map_list
*list
= &obj
->map_list
;
1449 drm_ht_remove_item(&mm
->offset_hash
, &list
->hash
);
1450 drm_mm_put_block(list
->file_offset_node
);
1456 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1457 * @obj: object to check
1459 * Return the required GTT alignment for an object, taking into account
1460 * potential fence register mapping.
1463 i915_gem_get_gtt_alignment(struct drm_i915_gem_object
*obj_priv
)
1465 struct drm_device
*dev
= obj_priv
->base
.dev
;
1468 * Minimum alignment is 4k (GTT page size), but might be greater
1469 * if a fence register is needed for the object.
1471 if (INTEL_INFO(dev
)->gen
>= 4 ||
1472 obj_priv
->tiling_mode
== I915_TILING_NONE
)
1476 * Previous chips need to be aligned to the size of the smallest
1477 * fence register that can contain the object.
1479 return i915_gem_get_gtt_size(obj_priv
);
1483 * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an
1485 * @obj: object to check
1487 * Return the required GTT alignment for an object, only taking into account
1488 * unfenced tiled surface requirements.
1491 i915_gem_get_unfenced_gtt_alignment(struct drm_i915_gem_object
*obj_priv
)
1493 struct drm_device
*dev
= obj_priv
->base
.dev
;
1497 * Minimum alignment is 4k (GTT page size) for sane hw.
1499 if (INTEL_INFO(dev
)->gen
>= 4 || IS_G33(dev
) ||
1500 obj_priv
->tiling_mode
== I915_TILING_NONE
)
1504 * Older chips need unfenced tiled buffers to be aligned to the left
1505 * edge of an even tile row (where tile rows are counted as if the bo is
1506 * placed in a fenced gtt region).
1509 (obj_priv
->tiling_mode
== I915_TILING_Y
&& HAS_128_BYTE_Y_TILING(dev
)))
1514 return tile_height
* obj_priv
->stride
* 2;
1518 i915_gem_get_gtt_size(struct drm_i915_gem_object
*obj_priv
)
1520 struct drm_device
*dev
= obj_priv
->base
.dev
;
1524 * Minimum alignment is 4k (GTT page size), but might be greater
1525 * if a fence register is needed for the object.
1527 if (INTEL_INFO(dev
)->gen
>= 4)
1528 return obj_priv
->base
.size
;
1531 * Previous chips need to be aligned to the size of the smallest
1532 * fence register that can contain the object.
1534 if (INTEL_INFO(dev
)->gen
== 3)
1539 while (size
< obj_priv
->base
.size
)
1546 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1548 * @data: GTT mapping ioctl data
1549 * @file_priv: GEM object info
1551 * Simply returns the fake offset to userspace so it can mmap it.
1552 * The mmap call will end up in drm_gem_mmap(), which will set things
1553 * up so we can get faults in the handler above.
1555 * The fault handler will take care of binding the object into the GTT
1556 * (since it may have been evicted to make room for something), allocating
1557 * a fence register, and mapping the appropriate aperture address into
1561 i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
1562 struct drm_file
*file_priv
)
1564 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1565 struct drm_i915_gem_mmap_gtt
*args
= data
;
1566 struct drm_gem_object
*obj
;
1567 struct drm_i915_gem_object
*obj_priv
;
1570 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1573 ret
= i915_mutex_lock_interruptible(dev
);
1577 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1582 obj_priv
= to_intel_bo(obj
);
1584 if (obj
->size
> dev_priv
->mm
.gtt_mappable_end
) {
1589 if (obj_priv
->madv
!= I915_MADV_WILLNEED
) {
1590 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1595 if (!obj
->map_list
.map
) {
1596 ret
= i915_gem_create_mmap_offset(obj
);
1601 args
->offset
= (u64
)obj
->map_list
.hash
.key
<< PAGE_SHIFT
;
1604 drm_gem_object_unreference(obj
);
1606 mutex_unlock(&dev
->struct_mutex
);
1611 i915_gem_object_get_pages_gtt(struct drm_gem_object
*obj
,
1614 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1616 struct address_space
*mapping
;
1617 struct inode
*inode
;
1620 /* Get the list of pages out of our struct file. They'll be pinned
1621 * at this point until we release them.
1623 page_count
= obj
->size
/ PAGE_SIZE
;
1624 BUG_ON(obj_priv
->pages
!= NULL
);
1625 obj_priv
->pages
= drm_malloc_ab(page_count
, sizeof(struct page
*));
1626 if (obj_priv
->pages
== NULL
)
1629 inode
= obj
->filp
->f_path
.dentry
->d_inode
;
1630 mapping
= inode
->i_mapping
;
1631 for (i
= 0; i
< page_count
; i
++) {
1632 page
= read_cache_page_gfp(mapping
, i
,
1640 obj_priv
->pages
[i
] = page
;
1643 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
)
1644 i915_gem_object_do_bit_17_swizzle(obj
);
1650 page_cache_release(obj_priv
->pages
[i
]);
1652 drm_free_large(obj_priv
->pages
);
1653 obj_priv
->pages
= NULL
;
1654 return PTR_ERR(page
);
1658 i915_gem_object_put_pages_gtt(struct drm_gem_object
*obj
)
1660 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1661 int page_count
= obj
->size
/ PAGE_SIZE
;
1664 BUG_ON(obj_priv
->madv
== __I915_MADV_PURGED
);
1666 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
)
1667 i915_gem_object_save_bit_17_swizzle(obj
);
1669 if (obj_priv
->madv
== I915_MADV_DONTNEED
)
1670 obj_priv
->dirty
= 0;
1672 for (i
= 0; i
< page_count
; i
++) {
1673 if (obj_priv
->dirty
)
1674 set_page_dirty(obj_priv
->pages
[i
]);
1676 if (obj_priv
->madv
== I915_MADV_WILLNEED
)
1677 mark_page_accessed(obj_priv
->pages
[i
]);
1679 page_cache_release(obj_priv
->pages
[i
]);
1681 obj_priv
->dirty
= 0;
1683 drm_free_large(obj_priv
->pages
);
1684 obj_priv
->pages
= NULL
;
1688 i915_gem_next_request_seqno(struct drm_device
*dev
,
1689 struct intel_ring_buffer
*ring
)
1691 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1692 return ring
->outstanding_lazy_request
= dev_priv
->next_seqno
;
1696 i915_gem_object_move_to_active(struct drm_gem_object
*obj
,
1697 struct intel_ring_buffer
*ring
)
1699 struct drm_device
*dev
= obj
->dev
;
1700 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1701 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1702 uint32_t seqno
= i915_gem_next_request_seqno(dev
, ring
);
1704 BUG_ON(ring
== NULL
);
1705 obj_priv
->ring
= ring
;
1707 /* Add a reference if we're newly entering the active list. */
1708 if (!obj_priv
->active
) {
1709 drm_gem_object_reference(obj
);
1710 obj_priv
->active
= 1;
1713 /* Move from whatever list we were on to the tail of execution. */
1714 list_move_tail(&obj_priv
->mm_list
, &dev_priv
->mm
.active_list
);
1715 list_move_tail(&obj_priv
->ring_list
, &ring
->active_list
);
1716 obj_priv
->last_rendering_seqno
= seqno
;
1720 i915_gem_object_move_to_flushing(struct drm_gem_object
*obj
)
1722 struct drm_device
*dev
= obj
->dev
;
1723 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1724 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1726 BUG_ON(!obj_priv
->active
);
1727 list_move_tail(&obj_priv
->mm_list
, &dev_priv
->mm
.flushing_list
);
1728 list_del_init(&obj_priv
->ring_list
);
1729 obj_priv
->last_rendering_seqno
= 0;
1732 /* Immediately discard the backing storage */
1734 i915_gem_object_truncate(struct drm_gem_object
*obj
)
1736 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1737 struct inode
*inode
;
1739 /* Our goal here is to return as much of the memory as
1740 * is possible back to the system as we are called from OOM.
1741 * To do this we must instruct the shmfs to drop all of its
1742 * backing pages, *now*. Here we mirror the actions taken
1743 * when by shmem_delete_inode() to release the backing store.
1745 inode
= obj
->filp
->f_path
.dentry
->d_inode
;
1746 truncate_inode_pages(inode
->i_mapping
, 0);
1747 if (inode
->i_op
->truncate_range
)
1748 inode
->i_op
->truncate_range(inode
, 0, (loff_t
)-1);
1750 obj_priv
->madv
= __I915_MADV_PURGED
;
1754 i915_gem_object_is_purgeable(struct drm_i915_gem_object
*obj_priv
)
1756 return obj_priv
->madv
== I915_MADV_DONTNEED
;
1760 i915_gem_object_move_to_inactive(struct drm_gem_object
*obj
)
1762 struct drm_device
*dev
= obj
->dev
;
1763 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1764 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1766 if (obj_priv
->pin_count
!= 0)
1767 list_move_tail(&obj_priv
->mm_list
, &dev_priv
->mm
.pinned_list
);
1769 list_move_tail(&obj_priv
->mm_list
, &dev_priv
->mm
.inactive_list
);
1770 list_del_init(&obj_priv
->ring_list
);
1772 BUG_ON(!list_empty(&obj_priv
->gpu_write_list
));
1774 obj_priv
->last_rendering_seqno
= 0;
1775 obj_priv
->ring
= NULL
;
1776 if (obj_priv
->active
) {
1777 obj_priv
->active
= 0;
1778 drm_gem_object_unreference(obj
);
1780 WARN_ON(i915_verify_lists(dev
));
1784 i915_gem_process_flushing_list(struct drm_device
*dev
,
1785 uint32_t flush_domains
,
1786 struct intel_ring_buffer
*ring
)
1788 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1789 struct drm_i915_gem_object
*obj_priv
, *next
;
1791 list_for_each_entry_safe(obj_priv
, next
,
1792 &ring
->gpu_write_list
,
1794 struct drm_gem_object
*obj
= &obj_priv
->base
;
1796 if (obj
->write_domain
& flush_domains
) {
1797 uint32_t old_write_domain
= obj
->write_domain
;
1799 obj
->write_domain
= 0;
1800 list_del_init(&obj_priv
->gpu_write_list
);
1801 i915_gem_object_move_to_active(obj
, ring
);
1803 /* update the fence lru list */
1804 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
) {
1805 struct drm_i915_fence_reg
*reg
=
1806 &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
1807 list_move_tail(®
->lru_list
,
1808 &dev_priv
->mm
.fence_list
);
1811 trace_i915_gem_object_change_domain(obj
,
1819 i915_add_request(struct drm_device
*dev
,
1820 struct drm_file
*file
,
1821 struct drm_i915_gem_request
*request
,
1822 struct intel_ring_buffer
*ring
)
1824 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1825 struct drm_i915_file_private
*file_priv
= NULL
;
1830 BUG_ON(request
== NULL
);
1833 file_priv
= file
->driver_priv
;
1835 ret
= ring
->add_request(ring
, &seqno
);
1839 ring
->outstanding_lazy_request
= false;
1841 request
->seqno
= seqno
;
1842 request
->ring
= ring
;
1843 request
->emitted_jiffies
= jiffies
;
1844 was_empty
= list_empty(&ring
->request_list
);
1845 list_add_tail(&request
->list
, &ring
->request_list
);
1848 spin_lock(&file_priv
->mm
.lock
);
1849 request
->file_priv
= file_priv
;
1850 list_add_tail(&request
->client_list
,
1851 &file_priv
->mm
.request_list
);
1852 spin_unlock(&file_priv
->mm
.lock
);
1855 if (!dev_priv
->mm
.suspended
) {
1856 mod_timer(&dev_priv
->hangcheck_timer
,
1857 jiffies
+ msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD
));
1859 queue_delayed_work(dev_priv
->wq
,
1860 &dev_priv
->mm
.retire_work
, HZ
);
1866 * Command execution barrier
1868 * Ensures that all commands in the ring are finished
1869 * before signalling the CPU
1872 i915_retire_commands(struct drm_device
*dev
, struct intel_ring_buffer
*ring
)
1874 uint32_t flush_domains
= 0;
1876 /* The sampler always gets flushed on i965 (sigh) */
1877 if (INTEL_INFO(dev
)->gen
>= 4)
1878 flush_domains
|= I915_GEM_DOMAIN_SAMPLER
;
1880 ring
->flush(ring
, I915_GEM_DOMAIN_COMMAND
, flush_domains
);
1884 i915_gem_request_remove_from_client(struct drm_i915_gem_request
*request
)
1886 struct drm_i915_file_private
*file_priv
= request
->file_priv
;
1891 spin_lock(&file_priv
->mm
.lock
);
1892 list_del(&request
->client_list
);
1893 request
->file_priv
= NULL
;
1894 spin_unlock(&file_priv
->mm
.lock
);
1897 static void i915_gem_reset_ring_lists(struct drm_i915_private
*dev_priv
,
1898 struct intel_ring_buffer
*ring
)
1900 while (!list_empty(&ring
->request_list
)) {
1901 struct drm_i915_gem_request
*request
;
1903 request
= list_first_entry(&ring
->request_list
,
1904 struct drm_i915_gem_request
,
1907 list_del(&request
->list
);
1908 i915_gem_request_remove_from_client(request
);
1912 while (!list_empty(&ring
->active_list
)) {
1913 struct drm_i915_gem_object
*obj_priv
;
1915 obj_priv
= list_first_entry(&ring
->active_list
,
1916 struct drm_i915_gem_object
,
1919 obj_priv
->base
.write_domain
= 0;
1920 list_del_init(&obj_priv
->gpu_write_list
);
1921 i915_gem_object_move_to_inactive(&obj_priv
->base
);
1925 void i915_gem_reset(struct drm_device
*dev
)
1927 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1928 struct drm_i915_gem_object
*obj_priv
;
1931 i915_gem_reset_ring_lists(dev_priv
, &dev_priv
->render_ring
);
1932 i915_gem_reset_ring_lists(dev_priv
, &dev_priv
->bsd_ring
);
1933 i915_gem_reset_ring_lists(dev_priv
, &dev_priv
->blt_ring
);
1935 /* Remove anything from the flushing lists. The GPU cache is likely
1936 * to be lost on reset along with the data, so simply move the
1937 * lost bo to the inactive list.
1939 while (!list_empty(&dev_priv
->mm
.flushing_list
)) {
1940 obj_priv
= list_first_entry(&dev_priv
->mm
.flushing_list
,
1941 struct drm_i915_gem_object
,
1944 obj_priv
->base
.write_domain
= 0;
1945 list_del_init(&obj_priv
->gpu_write_list
);
1946 i915_gem_object_move_to_inactive(&obj_priv
->base
);
1949 /* Move everything out of the GPU domains to ensure we do any
1950 * necessary invalidation upon reuse.
1952 list_for_each_entry(obj_priv
,
1953 &dev_priv
->mm
.inactive_list
,
1956 obj_priv
->base
.read_domains
&= ~I915_GEM_GPU_DOMAINS
;
1959 /* The fence registers are invalidated so clear them out */
1960 for (i
= 0; i
< 16; i
++) {
1961 struct drm_i915_fence_reg
*reg
;
1963 reg
= &dev_priv
->fence_regs
[i
];
1967 i915_gem_clear_fence_reg(reg
->obj
);
1972 * This function clears the request list as sequence numbers are passed.
1975 i915_gem_retire_requests_ring(struct drm_device
*dev
,
1976 struct intel_ring_buffer
*ring
)
1978 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1981 if (!ring
->status_page
.page_addr
||
1982 list_empty(&ring
->request_list
))
1985 WARN_ON(i915_verify_lists(dev
));
1987 seqno
= ring
->get_seqno(ring
);
1988 while (!list_empty(&ring
->request_list
)) {
1989 struct drm_i915_gem_request
*request
;
1991 request
= list_first_entry(&ring
->request_list
,
1992 struct drm_i915_gem_request
,
1995 if (!i915_seqno_passed(seqno
, request
->seqno
))
1998 trace_i915_gem_request_retire(dev
, request
->seqno
);
2000 list_del(&request
->list
);
2001 i915_gem_request_remove_from_client(request
);
2005 /* Move any buffers on the active list that are no longer referenced
2006 * by the ringbuffer to the flushing/inactive lists as appropriate.
2008 while (!list_empty(&ring
->active_list
)) {
2009 struct drm_gem_object
*obj
;
2010 struct drm_i915_gem_object
*obj_priv
;
2012 obj_priv
= list_first_entry(&ring
->active_list
,
2013 struct drm_i915_gem_object
,
2016 if (!i915_seqno_passed(seqno
, obj_priv
->last_rendering_seqno
))
2019 obj
= &obj_priv
->base
;
2020 if (obj
->write_domain
!= 0)
2021 i915_gem_object_move_to_flushing(obj
);
2023 i915_gem_object_move_to_inactive(obj
);
2026 if (unlikely (dev_priv
->trace_irq_seqno
&&
2027 i915_seqno_passed(dev_priv
->trace_irq_seqno
, seqno
))) {
2028 ring
->user_irq_put(ring
);
2029 dev_priv
->trace_irq_seqno
= 0;
2032 WARN_ON(i915_verify_lists(dev
));
2036 i915_gem_retire_requests(struct drm_device
*dev
)
2038 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2040 if (!list_empty(&dev_priv
->mm
.deferred_free_list
)) {
2041 struct drm_i915_gem_object
*obj_priv
, *tmp
;
2043 /* We must be careful that during unbind() we do not
2044 * accidentally infinitely recurse into retire requests.
2046 * retire -> free -> unbind -> wait -> retire_ring
2048 list_for_each_entry_safe(obj_priv
, tmp
,
2049 &dev_priv
->mm
.deferred_free_list
,
2051 i915_gem_free_object_tail(&obj_priv
->base
);
2054 i915_gem_retire_requests_ring(dev
, &dev_priv
->render_ring
);
2055 i915_gem_retire_requests_ring(dev
, &dev_priv
->bsd_ring
);
2056 i915_gem_retire_requests_ring(dev
, &dev_priv
->blt_ring
);
2060 i915_gem_retire_work_handler(struct work_struct
*work
)
2062 drm_i915_private_t
*dev_priv
;
2063 struct drm_device
*dev
;
2065 dev_priv
= container_of(work
, drm_i915_private_t
,
2066 mm
.retire_work
.work
);
2067 dev
= dev_priv
->dev
;
2069 /* Come back later if the device is busy... */
2070 if (!mutex_trylock(&dev
->struct_mutex
)) {
2071 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, HZ
);
2075 i915_gem_retire_requests(dev
);
2077 if (!dev_priv
->mm
.suspended
&&
2078 (!list_empty(&dev_priv
->render_ring
.request_list
) ||
2079 !list_empty(&dev_priv
->bsd_ring
.request_list
) ||
2080 !list_empty(&dev_priv
->blt_ring
.request_list
)))
2081 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, HZ
);
2082 mutex_unlock(&dev
->struct_mutex
);
2086 i915_do_wait_request(struct drm_device
*dev
, uint32_t seqno
,
2087 bool interruptible
, struct intel_ring_buffer
*ring
)
2089 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2095 if (atomic_read(&dev_priv
->mm
.wedged
))
2098 if (seqno
== ring
->outstanding_lazy_request
) {
2099 struct drm_i915_gem_request
*request
;
2101 request
= kzalloc(sizeof(*request
), GFP_KERNEL
);
2102 if (request
== NULL
)
2105 ret
= i915_add_request(dev
, NULL
, request
, ring
);
2111 seqno
= request
->seqno
;
2114 if (!i915_seqno_passed(ring
->get_seqno(ring
), seqno
)) {
2115 if (HAS_PCH_SPLIT(dev
))
2116 ier
= I915_READ(DEIER
) | I915_READ(GTIER
);
2118 ier
= I915_READ(IER
);
2120 DRM_ERROR("something (likely vbetool) disabled "
2121 "interrupts, re-enabling\n");
2122 i915_driver_irq_preinstall(dev
);
2123 i915_driver_irq_postinstall(dev
);
2126 trace_i915_gem_request_wait_begin(dev
, seqno
);
2128 ring
->waiting_seqno
= seqno
;
2129 ring
->user_irq_get(ring
);
2131 ret
= wait_event_interruptible(ring
->irq_queue
,
2132 i915_seqno_passed(ring
->get_seqno(ring
), seqno
)
2133 || atomic_read(&dev_priv
->mm
.wedged
));
2135 wait_event(ring
->irq_queue
,
2136 i915_seqno_passed(ring
->get_seqno(ring
), seqno
)
2137 || atomic_read(&dev_priv
->mm
.wedged
));
2139 ring
->user_irq_put(ring
);
2140 ring
->waiting_seqno
= 0;
2142 trace_i915_gem_request_wait_end(dev
, seqno
);
2144 if (atomic_read(&dev_priv
->mm
.wedged
))
2147 if (ret
&& ret
!= -ERESTARTSYS
)
2148 DRM_ERROR("%s returns %d (awaiting %d at %d, next %d)\n",
2149 __func__
, ret
, seqno
, ring
->get_seqno(ring
),
2150 dev_priv
->next_seqno
);
2152 /* Directly dispatch request retiring. While we have the work queue
2153 * to handle this, the waiter on a request often wants an associated
2154 * buffer to have made it to the inactive list, and we would need
2155 * a separate wait queue to handle that.
2158 i915_gem_retire_requests_ring(dev
, ring
);
2164 * Waits for a sequence number to be signaled, and cleans up the
2165 * request and object lists appropriately for that event.
2168 i915_wait_request(struct drm_device
*dev
, uint32_t seqno
,
2169 struct intel_ring_buffer
*ring
)
2171 return i915_do_wait_request(dev
, seqno
, 1, ring
);
2175 i915_gem_flush_ring(struct drm_device
*dev
,
2176 struct drm_file
*file_priv
,
2177 struct intel_ring_buffer
*ring
,
2178 uint32_t invalidate_domains
,
2179 uint32_t flush_domains
)
2181 ring
->flush(ring
, invalidate_domains
, flush_domains
);
2182 i915_gem_process_flushing_list(dev
, flush_domains
, ring
);
2186 i915_gem_flush(struct drm_device
*dev
,
2187 struct drm_file
*file_priv
,
2188 uint32_t invalidate_domains
,
2189 uint32_t flush_domains
,
2190 uint32_t flush_rings
)
2192 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2194 if (flush_domains
& I915_GEM_DOMAIN_CPU
)
2195 intel_gtt_chipset_flush();
2197 if ((flush_domains
| invalidate_domains
) & I915_GEM_GPU_DOMAINS
) {
2198 if (flush_rings
& RING_RENDER
)
2199 i915_gem_flush_ring(dev
, file_priv
,
2200 &dev_priv
->render_ring
,
2201 invalidate_domains
, flush_domains
);
2202 if (flush_rings
& RING_BSD
)
2203 i915_gem_flush_ring(dev
, file_priv
,
2204 &dev_priv
->bsd_ring
,
2205 invalidate_domains
, flush_domains
);
2206 if (flush_rings
& RING_BLT
)
2207 i915_gem_flush_ring(dev
, file_priv
,
2208 &dev_priv
->blt_ring
,
2209 invalidate_domains
, flush_domains
);
2214 * Ensures that all rendering to the object has completed and the object is
2215 * safe to unbind from the GTT or access from the CPU.
2218 i915_gem_object_wait_rendering(struct drm_gem_object
*obj
,
2221 struct drm_device
*dev
= obj
->dev
;
2222 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2225 /* This function only exists to support waiting for existing rendering,
2226 * not for emitting required flushes.
2228 BUG_ON((obj
->write_domain
& I915_GEM_GPU_DOMAINS
) != 0);
2230 /* If there is rendering queued on the buffer being evicted, wait for
2233 if (obj_priv
->active
) {
2234 ret
= i915_do_wait_request(dev
,
2235 obj_priv
->last_rendering_seqno
,
2246 * Unbinds an object from the GTT aperture.
2249 i915_gem_object_unbind(struct drm_gem_object
*obj
)
2251 struct drm_device
*dev
= obj
->dev
;
2252 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2253 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2256 if (obj_priv
->gtt_space
== NULL
)
2259 if (obj_priv
->pin_count
!= 0) {
2260 DRM_ERROR("Attempting to unbind pinned buffer\n");
2264 /* blow away mappings if mapped through GTT */
2265 i915_gem_release_mmap(obj
);
2267 /* Move the object to the CPU domain to ensure that
2268 * any possible CPU writes while it's not in the GTT
2269 * are flushed when we go to remap it. This will
2270 * also ensure that all pending GPU writes are finished
2273 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
2274 if (ret
== -ERESTARTSYS
)
2276 /* Continue on if we fail due to EIO, the GPU is hung so we
2277 * should be safe and we need to cleanup or else we might
2278 * cause memory corruption through use-after-free.
2281 i915_gem_clflush_object(obj
);
2282 obj
->read_domains
= obj
->write_domain
= I915_GEM_DOMAIN_CPU
;
2285 /* release the fence reg _after_ flushing */
2286 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
)
2287 i915_gem_clear_fence_reg(obj
);
2289 drm_unbind_agp(obj_priv
->agp_mem
);
2290 drm_free_agp(obj_priv
->agp_mem
, obj
->size
/ PAGE_SIZE
);
2292 i915_gem_object_put_pages_gtt(obj
);
2294 i915_gem_info_remove_gtt(dev_priv
, obj_priv
);
2295 list_del_init(&obj_priv
->mm_list
);
2296 /* Avoid an unnecessary call to unbind on rebind. */
2297 obj_priv
->map_and_fenceable
= true;
2299 drm_mm_put_block(obj_priv
->gtt_space
);
2300 obj_priv
->gtt_space
= NULL
;
2301 obj_priv
->gtt_offset
= 0;
2303 if (i915_gem_object_is_purgeable(obj_priv
))
2304 i915_gem_object_truncate(obj
);
2306 trace_i915_gem_object_unbind(obj
);
2311 static int i915_ring_idle(struct drm_device
*dev
,
2312 struct intel_ring_buffer
*ring
)
2314 if (list_empty(&ring
->gpu_write_list
) && list_empty(&ring
->active_list
))
2317 i915_gem_flush_ring(dev
, NULL
, ring
,
2318 I915_GEM_GPU_DOMAINS
, I915_GEM_GPU_DOMAINS
);
2319 return i915_wait_request(dev
,
2320 i915_gem_next_request_seqno(dev
, ring
),
2325 i915_gpu_idle(struct drm_device
*dev
)
2327 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2331 lists_empty
= (list_empty(&dev_priv
->mm
.flushing_list
) &&
2332 list_empty(&dev_priv
->mm
.active_list
));
2336 /* Flush everything onto the inactive list. */
2337 ret
= i915_ring_idle(dev
, &dev_priv
->render_ring
);
2341 ret
= i915_ring_idle(dev
, &dev_priv
->bsd_ring
);
2345 ret
= i915_ring_idle(dev
, &dev_priv
->blt_ring
);
2352 static void sandybridge_write_fence_reg(struct drm_gem_object
*obj
)
2354 struct drm_device
*dev
= obj
->dev
;
2355 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2356 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2357 u32 size
= i915_gem_get_gtt_size(obj_priv
);
2358 int regnum
= obj_priv
->fence_reg
;
2361 val
= (uint64_t)((obj_priv
->gtt_offset
+ size
- 4096) &
2363 val
|= obj_priv
->gtt_offset
& 0xfffff000;
2364 val
|= (uint64_t)((obj_priv
->stride
/ 128) - 1) <<
2365 SANDYBRIDGE_FENCE_PITCH_SHIFT
;
2367 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2368 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
2369 val
|= I965_FENCE_REG_VALID
;
2371 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0
+ (regnum
* 8), val
);
2374 static void i965_write_fence_reg(struct drm_gem_object
*obj
)
2376 struct drm_device
*dev
= obj
->dev
;
2377 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2378 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2379 u32 size
= i915_gem_get_gtt_size(obj_priv
);
2380 int regnum
= obj_priv
->fence_reg
;
2383 val
= (uint64_t)((obj_priv
->gtt_offset
+ size
- 4096) &
2385 val
|= obj_priv
->gtt_offset
& 0xfffff000;
2386 val
|= ((obj_priv
->stride
/ 128) - 1) << I965_FENCE_PITCH_SHIFT
;
2387 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2388 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
2389 val
|= I965_FENCE_REG_VALID
;
2391 I915_WRITE64(FENCE_REG_965_0
+ (regnum
* 8), val
);
2394 static void i915_write_fence_reg(struct drm_gem_object
*obj
)
2396 struct drm_device
*dev
= obj
->dev
;
2397 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2398 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2399 u32 size
= i915_gem_get_gtt_size(obj_priv
);
2400 uint32_t fence_reg
, val
, pitch_val
;
2403 if ((obj_priv
->gtt_offset
& ~I915_FENCE_START_MASK
) ||
2404 (obj_priv
->gtt_offset
& (size
- 1))) {
2405 WARN(1, "%s: object 0x%08x [fenceable? %d] not 1M or size (0x%08x) aligned [gtt_space offset=%lx, size=%lx]\n",
2406 __func__
, obj_priv
->gtt_offset
, obj_priv
->map_and_fenceable
, size
,
2407 obj_priv
->gtt_space
->start
, obj_priv
->gtt_space
->size
);
2411 if (obj_priv
->tiling_mode
== I915_TILING_Y
&&
2412 HAS_128_BYTE_Y_TILING(dev
))
2417 /* Note: pitch better be a power of two tile widths */
2418 pitch_val
= obj_priv
->stride
/ tile_width
;
2419 pitch_val
= ffs(pitch_val
) - 1;
2421 if (obj_priv
->tiling_mode
== I915_TILING_Y
&&
2422 HAS_128_BYTE_Y_TILING(dev
))
2423 WARN_ON(pitch_val
> I830_FENCE_MAX_PITCH_VAL
);
2425 WARN_ON(pitch_val
> I915_FENCE_MAX_PITCH_VAL
);
2427 val
= obj_priv
->gtt_offset
;
2428 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2429 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2430 val
|= I915_FENCE_SIZE_BITS(size
);
2431 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2432 val
|= I830_FENCE_REG_VALID
;
2434 fence_reg
= obj_priv
->fence_reg
;
2436 fence_reg
= FENCE_REG_830_0
+ fence_reg
* 4;
2438 fence_reg
= FENCE_REG_945_8
+ (fence_reg
- 8) * 4;
2439 I915_WRITE(fence_reg
, val
);
2442 static void i830_write_fence_reg(struct drm_gem_object
*obj
)
2444 struct drm_device
*dev
= obj
->dev
;
2445 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2446 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2447 u32 size
= i915_gem_get_gtt_size(obj_priv
);
2448 int regnum
= obj_priv
->fence_reg
;
2451 uint32_t fence_size_bits
;
2453 if ((obj_priv
->gtt_offset
& ~I830_FENCE_START_MASK
) ||
2454 (obj_priv
->gtt_offset
& (obj
->size
- 1))) {
2455 WARN(1, "%s: object 0x%08x not 512K or size aligned\n",
2456 __func__
, obj_priv
->gtt_offset
);
2460 pitch_val
= obj_priv
->stride
/ 128;
2461 pitch_val
= ffs(pitch_val
) - 1;
2462 WARN_ON(pitch_val
> I830_FENCE_MAX_PITCH_VAL
);
2464 val
= obj_priv
->gtt_offset
;
2465 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2466 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2467 fence_size_bits
= I830_FENCE_SIZE_BITS(size
);
2468 WARN_ON(fence_size_bits
& ~0x00000f00);
2469 val
|= fence_size_bits
;
2470 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2471 val
|= I830_FENCE_REG_VALID
;
2473 I915_WRITE(FENCE_REG_830_0
+ (regnum
* 4), val
);
2476 static int i915_find_fence_reg(struct drm_device
*dev
,
2479 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2480 struct drm_i915_fence_reg
*reg
;
2481 struct drm_i915_gem_object
*obj_priv
= NULL
;
2484 /* First try to find a free reg */
2486 for (i
= dev_priv
->fence_reg_start
; i
< dev_priv
->num_fence_regs
; i
++) {
2487 reg
= &dev_priv
->fence_regs
[i
];
2491 obj_priv
= to_intel_bo(reg
->obj
);
2492 if (!obj_priv
->pin_count
)
2499 /* None available, try to steal one or wait for a user to finish */
2500 avail
= I915_FENCE_REG_NONE
;
2501 list_for_each_entry(reg
, &dev_priv
->mm
.fence_list
,
2503 obj_priv
= to_intel_bo(reg
->obj
);
2504 if (obj_priv
->pin_count
)
2508 avail
= obj_priv
->fence_reg
;
2512 BUG_ON(avail
== I915_FENCE_REG_NONE
);
2514 /* We only have a reference on obj from the active list. put_fence_reg
2515 * might drop that one, causing a use-after-free in it. So hold a
2516 * private reference to obj like the other callers of put_fence_reg
2517 * (set_tiling ioctl) do. */
2518 drm_gem_object_reference(&obj_priv
->base
);
2519 ret
= i915_gem_object_put_fence_reg(&obj_priv
->base
, interruptible
);
2520 drm_gem_object_unreference(&obj_priv
->base
);
2528 * i915_gem_object_get_fence_reg - set up a fence reg for an object
2529 * @obj: object to map through a fence reg
2531 * When mapping objects through the GTT, userspace wants to be able to write
2532 * to them without having to worry about swizzling if the object is tiled.
2534 * This function walks the fence regs looking for a free one for @obj,
2535 * stealing one if it can't find any.
2537 * It then sets up the reg based on the object's properties: address, pitch
2538 * and tiling format.
2541 i915_gem_object_get_fence_reg(struct drm_gem_object
*obj
,
2544 struct drm_device
*dev
= obj
->dev
;
2545 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2546 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2547 struct drm_i915_fence_reg
*reg
= NULL
;
2550 /* Just update our place in the LRU if our fence is getting used. */
2551 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
) {
2552 reg
= &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
2553 list_move_tail(®
->lru_list
, &dev_priv
->mm
.fence_list
);
2557 switch (obj_priv
->tiling_mode
) {
2558 case I915_TILING_NONE
:
2559 WARN(1, "allocating a fence for non-tiled object?\n");
2562 if (!obj_priv
->stride
)
2564 WARN((obj_priv
->stride
& (512 - 1)),
2565 "object 0x%08x is X tiled but has non-512B pitch\n",
2566 obj_priv
->gtt_offset
);
2569 if (!obj_priv
->stride
)
2571 WARN((obj_priv
->stride
& (128 - 1)),
2572 "object 0x%08x is Y tiled but has non-128B pitch\n",
2573 obj_priv
->gtt_offset
);
2577 ret
= i915_find_fence_reg(dev
, interruptible
);
2581 obj_priv
->fence_reg
= ret
;
2582 reg
= &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
2583 list_add_tail(®
->lru_list
, &dev_priv
->mm
.fence_list
);
2587 switch (INTEL_INFO(dev
)->gen
) {
2589 sandybridge_write_fence_reg(obj
);
2593 i965_write_fence_reg(obj
);
2596 i915_write_fence_reg(obj
);
2599 i830_write_fence_reg(obj
);
2603 trace_i915_gem_object_get_fence(obj
,
2604 obj_priv
->fence_reg
,
2605 obj_priv
->tiling_mode
);
2611 * i915_gem_clear_fence_reg - clear out fence register info
2612 * @obj: object to clear
2614 * Zeroes out the fence register itself and clears out the associated
2615 * data structures in dev_priv and obj_priv.
2618 i915_gem_clear_fence_reg(struct drm_gem_object
*obj
)
2620 struct drm_device
*dev
= obj
->dev
;
2621 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2622 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2623 struct drm_i915_fence_reg
*reg
=
2624 &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
2627 switch (INTEL_INFO(dev
)->gen
) {
2629 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0
+
2630 (obj_priv
->fence_reg
* 8), 0);
2634 I915_WRITE64(FENCE_REG_965_0
+ (obj_priv
->fence_reg
* 8), 0);
2637 if (obj_priv
->fence_reg
>= 8)
2638 fence_reg
= FENCE_REG_945_8
+ (obj_priv
->fence_reg
- 8) * 4;
2641 fence_reg
= FENCE_REG_830_0
+ obj_priv
->fence_reg
* 4;
2643 I915_WRITE(fence_reg
, 0);
2648 obj_priv
->fence_reg
= I915_FENCE_REG_NONE
;
2649 list_del_init(®
->lru_list
);
2653 * i915_gem_object_put_fence_reg - waits on outstanding fenced access
2654 * to the buffer to finish, and then resets the fence register.
2655 * @obj: tiled object holding a fence register.
2656 * @bool: whether the wait upon the fence is interruptible
2658 * Zeroes out the fence register itself and clears out the associated
2659 * data structures in dev_priv and obj_priv.
2662 i915_gem_object_put_fence_reg(struct drm_gem_object
*obj
,
2665 struct drm_device
*dev
= obj
->dev
;
2666 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2667 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2668 struct drm_i915_fence_reg
*reg
;
2670 if (obj_priv
->fence_reg
== I915_FENCE_REG_NONE
)
2673 /* If we've changed tiling, GTT-mappings of the object
2674 * need to re-fault to ensure that the correct fence register
2675 * setup is in place.
2677 i915_gem_release_mmap(obj
);
2679 /* On the i915, GPU access to tiled buffers is via a fence,
2680 * therefore we must wait for any outstanding access to complete
2681 * before clearing the fence.
2683 reg
= &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
2687 ret
= i915_gem_object_flush_gpu_write_domain(obj
, true);
2691 ret
= i915_gem_object_wait_rendering(obj
, interruptible
);
2698 i915_gem_object_flush_gtt_write_domain(obj
);
2699 i915_gem_clear_fence_reg(obj
);
2705 * Finds free space in the GTT aperture and binds the object there.
2708 i915_gem_object_bind_to_gtt(struct drm_gem_object
*obj
,
2710 bool map_and_fenceable
)
2712 struct drm_device
*dev
= obj
->dev
;
2713 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2714 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2715 struct drm_mm_node
*free_space
;
2716 gfp_t gfpmask
= __GFP_NORETRY
| __GFP_NOWARN
;
2717 u32 size
, fence_size
, fence_alignment
, unfenced_alignment
;
2718 bool mappable
, fenceable
;
2721 if (obj_priv
->madv
!= I915_MADV_WILLNEED
) {
2722 DRM_ERROR("Attempting to bind a purgeable object\n");
2726 fence_size
= i915_gem_get_gtt_size(obj_priv
);
2727 fence_alignment
= i915_gem_get_gtt_alignment(obj_priv
);
2728 unfenced_alignment
= i915_gem_get_unfenced_gtt_alignment(obj_priv
);
2731 alignment
= map_and_fenceable
? fence_alignment
:
2733 if (map_and_fenceable
&& alignment
& (fence_alignment
- 1)) {
2734 DRM_ERROR("Invalid object alignment requested %u\n", alignment
);
2738 size
= map_and_fenceable
? fence_size
: obj
->size
;
2740 /* If the object is bigger than the entire aperture, reject it early
2741 * before evicting everything in a vain attempt to find space.
2744 (map_and_fenceable
? dev_priv
->mm
.gtt_mappable_end
: dev_priv
->mm
.gtt_total
)) {
2745 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2750 if (map_and_fenceable
)
2752 drm_mm_search_free_in_range(&dev_priv
->mm
.gtt_space
,
2754 dev_priv
->mm
.gtt_mappable_end
,
2757 free_space
= drm_mm_search_free(&dev_priv
->mm
.gtt_space
,
2758 size
, alignment
, 0);
2760 if (free_space
!= NULL
) {
2761 if (map_and_fenceable
)
2762 obj_priv
->gtt_space
=
2763 drm_mm_get_block_range_generic(free_space
,
2765 dev_priv
->mm
.gtt_mappable_end
,
2768 obj_priv
->gtt_space
=
2769 drm_mm_get_block(free_space
, size
, alignment
);
2771 if (obj_priv
->gtt_space
== NULL
) {
2772 /* If the gtt is empty and we're still having trouble
2773 * fitting our object in, we're out of memory.
2775 ret
= i915_gem_evict_something(dev
, size
, alignment
,
2783 ret
= i915_gem_object_get_pages_gtt(obj
, gfpmask
);
2785 drm_mm_put_block(obj_priv
->gtt_space
);
2786 obj_priv
->gtt_space
= NULL
;
2788 if (ret
== -ENOMEM
) {
2789 /* first try to clear up some space from the GTT */
2790 ret
= i915_gem_evict_something(dev
, size
,
2794 /* now try to shrink everyone else */
2809 /* Create an AGP memory structure pointing at our pages, and bind it
2812 obj_priv
->agp_mem
= drm_agp_bind_pages(dev
,
2814 obj
->size
>> PAGE_SHIFT
,
2815 obj_priv
->gtt_space
->start
,
2816 obj_priv
->agp_type
);
2817 if (obj_priv
->agp_mem
== NULL
) {
2818 i915_gem_object_put_pages_gtt(obj
);
2819 drm_mm_put_block(obj_priv
->gtt_space
);
2820 obj_priv
->gtt_space
= NULL
;
2822 ret
= i915_gem_evict_something(dev
, size
,
2823 alignment
, map_and_fenceable
);
2830 obj_priv
->gtt_offset
= obj_priv
->gtt_space
->start
;
2832 /* keep track of bounds object by adding it to the inactive list */
2833 list_add_tail(&obj_priv
->mm_list
, &dev_priv
->mm
.inactive_list
);
2834 i915_gem_info_add_gtt(dev_priv
, obj_priv
);
2836 /* Assert that the object is not currently in any GPU domain. As it
2837 * wasn't in the GTT, there shouldn't be any way it could have been in
2840 BUG_ON(obj
->read_domains
& I915_GEM_GPU_DOMAINS
);
2841 BUG_ON(obj
->write_domain
& I915_GEM_GPU_DOMAINS
);
2843 trace_i915_gem_object_bind(obj
, obj_priv
->gtt_offset
, map_and_fenceable
);
2846 obj_priv
->gtt_space
->size
== fence_size
&&
2847 (obj_priv
->gtt_space
->start
& (fence_alignment
-1)) == 0;
2850 obj_priv
->gtt_offset
+ obj
->size
<= dev_priv
->mm
.gtt_mappable_end
;
2852 obj_priv
->map_and_fenceable
= mappable
&& fenceable
;
2858 i915_gem_clflush_object(struct drm_gem_object
*obj
)
2860 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2862 /* If we don't have a page list set up, then we're not pinned
2863 * to GPU, and we can ignore the cache flush because it'll happen
2864 * again at bind time.
2866 if (obj_priv
->pages
== NULL
)
2869 trace_i915_gem_object_clflush(obj
);
2871 drm_clflush_pages(obj_priv
->pages
, obj
->size
/ PAGE_SIZE
);
2874 /** Flushes any GPU write domain for the object if it's dirty. */
2876 i915_gem_object_flush_gpu_write_domain(struct drm_gem_object
*obj
,
2879 struct drm_device
*dev
= obj
->dev
;
2881 if ((obj
->write_domain
& I915_GEM_GPU_DOMAINS
) == 0)
2884 /* Queue the GPU write cache flushing we need. */
2885 i915_gem_flush_ring(dev
, NULL
,
2886 to_intel_bo(obj
)->ring
,
2887 0, obj
->write_domain
);
2888 BUG_ON(obj
->write_domain
);
2893 return i915_gem_object_wait_rendering(obj
, true);
2896 /** Flushes the GTT write domain for the object if it's dirty. */
2898 i915_gem_object_flush_gtt_write_domain(struct drm_gem_object
*obj
)
2900 uint32_t old_write_domain
;
2902 if (obj
->write_domain
!= I915_GEM_DOMAIN_GTT
)
2905 /* No actual flushing is required for the GTT write domain. Writes
2906 * to it immediately go to main memory as far as we know, so there's
2907 * no chipset flush. It also doesn't land in render cache.
2909 i915_gem_release_mmap(obj
);
2911 old_write_domain
= obj
->write_domain
;
2912 obj
->write_domain
= 0;
2914 trace_i915_gem_object_change_domain(obj
,
2919 /** Flushes the CPU write domain for the object if it's dirty. */
2921 i915_gem_object_flush_cpu_write_domain(struct drm_gem_object
*obj
)
2923 uint32_t old_write_domain
;
2925 if (obj
->write_domain
!= I915_GEM_DOMAIN_CPU
)
2928 i915_gem_clflush_object(obj
);
2929 intel_gtt_chipset_flush();
2930 old_write_domain
= obj
->write_domain
;
2931 obj
->write_domain
= 0;
2933 trace_i915_gem_object_change_domain(obj
,
2939 * Moves a single object to the GTT read, and possibly write domain.
2941 * This function returns when the move is complete, including waiting on
2945 i915_gem_object_set_to_gtt_domain(struct drm_gem_object
*obj
, int write
)
2947 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2948 uint32_t old_write_domain
, old_read_domains
;
2951 /* Not valid to be called on unbound objects. */
2952 if (obj_priv
->gtt_space
== NULL
)
2955 ret
= i915_gem_object_flush_gpu_write_domain(obj
, false);
2959 i915_gem_object_flush_cpu_write_domain(obj
);
2962 ret
= i915_gem_object_wait_rendering(obj
, true);
2967 old_write_domain
= obj
->write_domain
;
2968 old_read_domains
= obj
->read_domains
;
2970 /* It should now be out of any other write domains, and we can update
2971 * the domain values for our changes.
2973 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
2974 obj
->read_domains
|= I915_GEM_DOMAIN_GTT
;
2976 obj
->read_domains
= I915_GEM_DOMAIN_GTT
;
2977 obj
->write_domain
= I915_GEM_DOMAIN_GTT
;
2978 obj_priv
->dirty
= 1;
2981 trace_i915_gem_object_change_domain(obj
,
2989 * Prepare buffer for display plane. Use uninterruptible for possible flush
2990 * wait, as in modesetting process we're not supposed to be interrupted.
2993 i915_gem_object_set_to_display_plane(struct drm_gem_object
*obj
,
2996 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2997 uint32_t old_read_domains
;
3000 /* Not valid to be called on unbound objects. */
3001 if (obj_priv
->gtt_space
== NULL
)
3004 ret
= i915_gem_object_flush_gpu_write_domain(obj
, true);
3008 /* Currently, we are always called from an non-interruptible context. */
3010 ret
= i915_gem_object_wait_rendering(obj
, false);
3015 i915_gem_object_flush_cpu_write_domain(obj
);
3017 old_read_domains
= obj
->read_domains
;
3018 obj
->read_domains
|= I915_GEM_DOMAIN_GTT
;
3020 trace_i915_gem_object_change_domain(obj
,
3028 i915_gem_object_flush_gpu(struct drm_i915_gem_object
*obj
,
3034 if (obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
)
3035 i915_gem_flush_ring(obj
->base
.dev
, NULL
, obj
->ring
,
3036 0, obj
->base
.write_domain
);
3038 return i915_gem_object_wait_rendering(&obj
->base
, interruptible
);
3042 * Moves a single object to the CPU read, and possibly write domain.
3044 * This function returns when the move is complete, including waiting on
3048 i915_gem_object_set_to_cpu_domain(struct drm_gem_object
*obj
, int write
)
3050 uint32_t old_write_domain
, old_read_domains
;
3053 ret
= i915_gem_object_flush_gpu_write_domain(obj
, false);
3057 i915_gem_object_flush_gtt_write_domain(obj
);
3059 /* If we have a partially-valid cache of the object in the CPU,
3060 * finish invalidating it and free the per-page flags.
3062 i915_gem_object_set_to_full_cpu_read_domain(obj
);
3065 ret
= i915_gem_object_wait_rendering(obj
, true);
3070 old_write_domain
= obj
->write_domain
;
3071 old_read_domains
= obj
->read_domains
;
3073 /* Flush the CPU cache if it's still invalid. */
3074 if ((obj
->read_domains
& I915_GEM_DOMAIN_CPU
) == 0) {
3075 i915_gem_clflush_object(obj
);
3077 obj
->read_domains
|= I915_GEM_DOMAIN_CPU
;
3080 /* It should now be out of any other write domains, and we can update
3081 * the domain values for our changes.
3083 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
3085 /* If we're writing through the CPU, then the GPU read domains will
3086 * need to be invalidated at next use.
3089 obj
->read_domains
= I915_GEM_DOMAIN_CPU
;
3090 obj
->write_domain
= I915_GEM_DOMAIN_CPU
;
3093 trace_i915_gem_object_change_domain(obj
,
3101 * Set the next domain for the specified object. This
3102 * may not actually perform the necessary flushing/invaliding though,
3103 * as that may want to be batched with other set_domain operations
3105 * This is (we hope) the only really tricky part of gem. The goal
3106 * is fairly simple -- track which caches hold bits of the object
3107 * and make sure they remain coherent. A few concrete examples may
3108 * help to explain how it works. For shorthand, we use the notation
3109 * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
3110 * a pair of read and write domain masks.
3112 * Case 1: the batch buffer
3118 * 5. Unmapped from GTT
3121 * Let's take these a step at a time
3124 * Pages allocated from the kernel may still have
3125 * cache contents, so we set them to (CPU, CPU) always.
3126 * 2. Written by CPU (using pwrite)
3127 * The pwrite function calls set_domain (CPU, CPU) and
3128 * this function does nothing (as nothing changes)
3130 * This function asserts that the object is not
3131 * currently in any GPU-based read or write domains
3133 * i915_gem_execbuffer calls set_domain (COMMAND, 0).
3134 * As write_domain is zero, this function adds in the
3135 * current read domains (CPU+COMMAND, 0).
3136 * flush_domains is set to CPU.
3137 * invalidate_domains is set to COMMAND
3138 * clflush is run to get data out of the CPU caches
3139 * then i915_dev_set_domain calls i915_gem_flush to
3140 * emit an MI_FLUSH and drm_agp_chipset_flush
3141 * 5. Unmapped from GTT
3142 * i915_gem_object_unbind calls set_domain (CPU, CPU)
3143 * flush_domains and invalidate_domains end up both zero
3144 * so no flushing/invalidating happens
3148 * Case 2: The shared render buffer
3152 * 3. Read/written by GPU
3153 * 4. set_domain to (CPU,CPU)
3154 * 5. Read/written by CPU
3155 * 6. Read/written by GPU
3158 * Same as last example, (CPU, CPU)
3160 * Nothing changes (assertions find that it is not in the GPU)
3161 * 3. Read/written by GPU
3162 * execbuffer calls set_domain (RENDER, RENDER)
3163 * flush_domains gets CPU
3164 * invalidate_domains gets GPU
3166 * MI_FLUSH and drm_agp_chipset_flush
3167 * 4. set_domain (CPU, CPU)
3168 * flush_domains gets GPU
3169 * invalidate_domains gets CPU
3170 * wait_rendering (obj) to make sure all drawing is complete.
3171 * This will include an MI_FLUSH to get the data from GPU
3173 * clflush (obj) to invalidate the CPU cache
3174 * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
3175 * 5. Read/written by CPU
3176 * cache lines are loaded and dirtied
3177 * 6. Read written by GPU
3178 * Same as last GPU access
3180 * Case 3: The constant buffer
3185 * 4. Updated (written) by CPU again
3194 * flush_domains = CPU
3195 * invalidate_domains = RENDER
3198 * drm_agp_chipset_flush
3199 * 4. Updated (written) by CPU again
3201 * flush_domains = 0 (no previous write domain)
3202 * invalidate_domains = 0 (no new read domains)
3205 * flush_domains = CPU
3206 * invalidate_domains = RENDER
3209 * drm_agp_chipset_flush
3212 i915_gem_object_set_to_gpu_domain(struct drm_gem_object
*obj
,
3213 struct intel_ring_buffer
*ring
,
3214 struct change_domains
*cd
)
3216 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
3217 uint32_t invalidate_domains
= 0;
3218 uint32_t flush_domains
= 0;
3221 * If the object isn't moving to a new write domain,
3222 * let the object stay in multiple read domains
3224 if (obj
->pending_write_domain
== 0)
3225 obj
->pending_read_domains
|= obj
->read_domains
;
3228 * Flush the current write domain if
3229 * the new read domains don't match. Invalidate
3230 * any read domains which differ from the old
3233 if (obj
->write_domain
&&
3234 (obj
->write_domain
!= obj
->pending_read_domains
||
3235 obj_priv
->ring
!= ring
)) {
3236 flush_domains
|= obj
->write_domain
;
3237 invalidate_domains
|=
3238 obj
->pending_read_domains
& ~obj
->write_domain
;
3241 * Invalidate any read caches which may have
3242 * stale data. That is, any new read domains.
3244 invalidate_domains
|= obj
->pending_read_domains
& ~obj
->read_domains
;
3245 if ((flush_domains
| invalidate_domains
) & I915_GEM_DOMAIN_CPU
)
3246 i915_gem_clflush_object(obj
);
3248 /* blow away mappings if mapped through GTT */
3249 if ((flush_domains
| invalidate_domains
) & I915_GEM_DOMAIN_GTT
)
3250 i915_gem_release_mmap(obj
);
3252 /* The actual obj->write_domain will be updated with
3253 * pending_write_domain after we emit the accumulated flush for all
3254 * of our domain changes in execbuffers (which clears objects'
3255 * write_domains). So if we have a current write domain that we
3256 * aren't changing, set pending_write_domain to that.
3258 if (flush_domains
== 0 && obj
->pending_write_domain
== 0)
3259 obj
->pending_write_domain
= obj
->write_domain
;
3261 cd
->invalidate_domains
|= invalidate_domains
;
3262 cd
->flush_domains
|= flush_domains
;
3263 if (flush_domains
& I915_GEM_GPU_DOMAINS
)
3264 cd
->flush_rings
|= obj_priv
->ring
->id
;
3265 if (invalidate_domains
& I915_GEM_GPU_DOMAINS
)
3266 cd
->flush_rings
|= ring
->id
;
3270 * Moves the object from a partially CPU read to a full one.
3272 * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3273 * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
3276 i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object
*obj
)
3278 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
3280 if (!obj_priv
->page_cpu_valid
)
3283 /* If we're partially in the CPU read domain, finish moving it in.
3285 if (obj
->read_domains
& I915_GEM_DOMAIN_CPU
) {
3288 for (i
= 0; i
<= (obj
->size
- 1) / PAGE_SIZE
; i
++) {
3289 if (obj_priv
->page_cpu_valid
[i
])
3291 drm_clflush_pages(obj_priv
->pages
+ i
, 1);
3295 /* Free the page_cpu_valid mappings which are now stale, whether
3296 * or not we've got I915_GEM_DOMAIN_CPU.
3298 kfree(obj_priv
->page_cpu_valid
);
3299 obj_priv
->page_cpu_valid
= NULL
;
3303 * Set the CPU read domain on a range of the object.
3305 * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3306 * not entirely valid. The page_cpu_valid member of the object flags which
3307 * pages have been flushed, and will be respected by
3308 * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3309 * of the whole object.
3311 * This function returns when the move is complete, including waiting on
3315 i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object
*obj
,
3316 uint64_t offset
, uint64_t size
)
3318 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
3319 uint32_t old_read_domains
;
3322 if (offset
== 0 && size
== obj
->size
)
3323 return i915_gem_object_set_to_cpu_domain(obj
, 0);
3325 ret
= i915_gem_object_flush_gpu_write_domain(obj
, false);
3328 i915_gem_object_flush_gtt_write_domain(obj
);
3330 /* If we're already fully in the CPU read domain, we're done. */
3331 if (obj_priv
->page_cpu_valid
== NULL
&&
3332 (obj
->read_domains
& I915_GEM_DOMAIN_CPU
) != 0)
3335 /* Otherwise, create/clear the per-page CPU read domain flag if we're
3336 * newly adding I915_GEM_DOMAIN_CPU
3338 if (obj_priv
->page_cpu_valid
== NULL
) {
3339 obj_priv
->page_cpu_valid
= kzalloc(obj
->size
/ PAGE_SIZE
,
3341 if (obj_priv
->page_cpu_valid
== NULL
)
3343 } else if ((obj
->read_domains
& I915_GEM_DOMAIN_CPU
) == 0)
3344 memset(obj_priv
->page_cpu_valid
, 0, obj
->size
/ PAGE_SIZE
);
3346 /* Flush the cache on any pages that are still invalid from the CPU's
3349 for (i
= offset
/ PAGE_SIZE
; i
<= (offset
+ size
- 1) / PAGE_SIZE
;
3351 if (obj_priv
->page_cpu_valid
[i
])
3354 drm_clflush_pages(obj_priv
->pages
+ i
, 1);
3356 obj_priv
->page_cpu_valid
[i
] = 1;
3359 /* It should now be out of any other write domains, and we can update
3360 * the domain values for our changes.
3362 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
3364 old_read_domains
= obj
->read_domains
;
3365 obj
->read_domains
|= I915_GEM_DOMAIN_CPU
;
3367 trace_i915_gem_object_change_domain(obj
,
3375 i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object
*obj
,
3376 struct drm_file
*file_priv
,
3377 struct drm_i915_gem_exec_object2
*entry
,
3378 struct drm_i915_gem_relocation_entry
*reloc
)
3380 struct drm_device
*dev
= obj
->base
.dev
;
3381 struct drm_gem_object
*target_obj
;
3382 uint32_t target_offset
;
3385 target_obj
= drm_gem_object_lookup(dev
, file_priv
,
3386 reloc
->target_handle
);
3387 if (target_obj
== NULL
)
3390 target_offset
= to_intel_bo(target_obj
)->gtt_offset
;
3393 DRM_INFO("%s: obj %p offset %08x target %d "
3394 "read %08x write %08x gtt %08x "
3395 "presumed %08x delta %08x\n",
3398 (int) reloc
->offset
,
3399 (int) reloc
->target_handle
,
3400 (int) reloc
->read_domains
,
3401 (int) reloc
->write_domain
,
3402 (int) target_offset
,
3403 (int) reloc
->presumed_offset
,
3407 /* The target buffer should have appeared before us in the
3408 * exec_object list, so it should have a GTT space bound by now.
3410 if (target_offset
== 0) {
3411 DRM_ERROR("No GTT space found for object %d\n",
3412 reloc
->target_handle
);
3416 /* Validate that the target is in a valid r/w GPU domain */
3417 if (reloc
->write_domain
& (reloc
->write_domain
- 1)) {
3418 DRM_ERROR("reloc with multiple write domains: "
3419 "obj %p target %d offset %d "
3420 "read %08x write %08x",
3421 obj
, reloc
->target_handle
,
3422 (int) reloc
->offset
,
3423 reloc
->read_domains
,
3424 reloc
->write_domain
);
3427 if (reloc
->write_domain
& I915_GEM_DOMAIN_CPU
||
3428 reloc
->read_domains
& I915_GEM_DOMAIN_CPU
) {
3429 DRM_ERROR("reloc with read/write CPU domains: "
3430 "obj %p target %d offset %d "
3431 "read %08x write %08x",
3432 obj
, reloc
->target_handle
,
3433 (int) reloc
->offset
,
3434 reloc
->read_domains
,
3435 reloc
->write_domain
);
3438 if (reloc
->write_domain
&& target_obj
->pending_write_domain
&&
3439 reloc
->write_domain
!= target_obj
->pending_write_domain
) {
3440 DRM_ERROR("Write domain conflict: "
3441 "obj %p target %d offset %d "
3442 "new %08x old %08x\n",
3443 obj
, reloc
->target_handle
,
3444 (int) reloc
->offset
,
3445 reloc
->write_domain
,
3446 target_obj
->pending_write_domain
);
3450 target_obj
->pending_read_domains
|= reloc
->read_domains
;
3451 target_obj
->pending_write_domain
|= reloc
->write_domain
;
3453 /* If the relocation already has the right value in it, no
3454 * more work needs to be done.
3456 if (target_offset
== reloc
->presumed_offset
)
3459 /* Check that the relocation address is valid... */
3460 if (reloc
->offset
> obj
->base
.size
- 4) {
3461 DRM_ERROR("Relocation beyond object bounds: "
3462 "obj %p target %d offset %d size %d.\n",
3463 obj
, reloc
->target_handle
,
3464 (int) reloc
->offset
,
3465 (int) obj
->base
.size
);
3468 if (reloc
->offset
& 3) {
3469 DRM_ERROR("Relocation not 4-byte aligned: "
3470 "obj %p target %d offset %d.\n",
3471 obj
, reloc
->target_handle
,
3472 (int) reloc
->offset
);
3476 /* and points to somewhere within the target object. */
3477 if (reloc
->delta
>= target_obj
->size
) {
3478 DRM_ERROR("Relocation beyond target object bounds: "
3479 "obj %p target %d delta %d size %d.\n",
3480 obj
, reloc
->target_handle
,
3482 (int) target_obj
->size
);
3486 reloc
->delta
+= target_offset
;
3487 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_CPU
) {
3488 uint32_t page_offset
= reloc
->offset
& ~PAGE_MASK
;
3491 vaddr
= kmap_atomic(obj
->pages
[reloc
->offset
>> PAGE_SHIFT
]);
3492 *(uint32_t *)(vaddr
+ page_offset
) = reloc
->delta
;
3493 kunmap_atomic(vaddr
);
3495 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3496 uint32_t __iomem
*reloc_entry
;
3497 void __iomem
*reloc_page
;
3499 ret
= i915_gem_object_set_to_gtt_domain(&obj
->base
, 1);
3503 /* Map the page containing the relocation we're going to perform. */
3504 reloc
->offset
+= obj
->gtt_offset
;
3505 reloc_page
= io_mapping_map_atomic_wc(dev_priv
->mm
.gtt_mapping
,
3506 reloc
->offset
& PAGE_MASK
);
3507 reloc_entry
= (uint32_t __iomem
*)
3508 (reloc_page
+ (reloc
->offset
& ~PAGE_MASK
));
3509 iowrite32(reloc
->delta
, reloc_entry
);
3510 io_mapping_unmap_atomic(reloc_page
);
3513 /* and update the user's relocation entry */
3514 reloc
->presumed_offset
= target_offset
;
3519 drm_gem_object_unreference(target_obj
);
3524 i915_gem_execbuffer_relocate_object(struct drm_i915_gem_object
*obj
,
3525 struct drm_file
*file_priv
,
3526 struct drm_i915_gem_exec_object2
*entry
)
3528 struct drm_i915_gem_relocation_entry __user
*user_relocs
;
3531 user_relocs
= (void __user
*)(uintptr_t)entry
->relocs_ptr
;
3532 for (i
= 0; i
< entry
->relocation_count
; i
++) {
3533 struct drm_i915_gem_relocation_entry reloc
;
3535 if (__copy_from_user_inatomic(&reloc
,
3540 ret
= i915_gem_execbuffer_relocate_entry(obj
, file_priv
, entry
, &reloc
);
3544 if (__copy_to_user_inatomic(&user_relocs
[i
].presumed_offset
,
3545 &reloc
.presumed_offset
,
3546 sizeof(reloc
.presumed_offset
)))
3554 i915_gem_execbuffer_relocate_object_slow(struct drm_i915_gem_object
*obj
,
3555 struct drm_file
*file_priv
,
3556 struct drm_i915_gem_exec_object2
*entry
,
3557 struct drm_i915_gem_relocation_entry
*relocs
)
3561 for (i
= 0; i
< entry
->relocation_count
; i
++) {
3562 ret
= i915_gem_execbuffer_relocate_entry(obj
, file_priv
, entry
, &relocs
[i
]);
3571 i915_gem_execbuffer_relocate(struct drm_device
*dev
,
3572 struct drm_file
*file
,
3573 struct drm_gem_object
**object_list
,
3574 struct drm_i915_gem_exec_object2
*exec_list
,
3579 for (i
= 0; i
< count
; i
++) {
3580 struct drm_i915_gem_object
*obj
= to_intel_bo(object_list
[i
]);
3581 obj
->base
.pending_read_domains
= 0;
3582 obj
->base
.pending_write_domain
= 0;
3583 ret
= i915_gem_execbuffer_relocate_object(obj
, file
,
3593 i915_gem_execbuffer_reserve(struct drm_device
*dev
,
3594 struct drm_file
*file
,
3595 struct drm_gem_object
**object_list
,
3596 struct drm_i915_gem_exec_object2
*exec_list
,
3599 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3602 /* attempt to pin all of the buffers into the GTT */
3606 for (i
= 0; i
< count
; i
++) {
3607 struct drm_i915_gem_exec_object2
*entry
= &exec_list
[i
];
3608 struct drm_i915_gem_object
*obj
= to_intel_bo(object_list
[i
]);
3610 entry
->flags
& EXEC_OBJECT_NEEDS_FENCE
&&
3611 obj
->tiling_mode
!= I915_TILING_NONE
;
3613 /* g33/pnv can't fence buffers in the unmappable part */
3614 bool need_mappable
=
3615 entry
->relocation_count
? true : need_fence
;
3617 /* Check fence reg constraints and rebind if necessary */
3618 if (need_mappable
&& !obj
->map_and_fenceable
) {
3619 ret
= i915_gem_object_unbind(&obj
->base
);
3624 ret
= i915_gem_object_pin(&obj
->base
,
3631 * Pre-965 chips need a fence register set up in order
3632 * to properly handle blits to/from tiled surfaces.
3635 ret
= i915_gem_object_get_fence_reg(&obj
->base
, true);
3637 i915_gem_object_unpin(&obj
->base
);
3641 dev_priv
->fence_regs
[obj
->fence_reg
].gpu
= true;
3644 entry
->offset
= obj
->gtt_offset
;
3648 i915_gem_object_unpin(object_list
[i
]);
3650 if (ret
!= -ENOSPC
|| retry
> 1)
3653 /* First attempt, just clear anything that is purgeable.
3654 * Second attempt, clear the entire GTT.
3656 ret
= i915_gem_evict_everything(dev
, retry
== 0);
3665 i915_gem_execbuffer_relocate_slow(struct drm_device
*dev
,
3666 struct drm_file
*file
,
3667 struct drm_gem_object
**object_list
,
3668 struct drm_i915_gem_exec_object2
*exec_list
,
3671 struct drm_i915_gem_relocation_entry
*reloc
;
3674 for (i
= 0; i
< count
; i
++) {
3675 struct drm_i915_gem_object
*obj
= to_intel_bo(object_list
[i
]);
3676 obj
->in_execbuffer
= false;
3679 mutex_unlock(&dev
->struct_mutex
);
3682 for (i
= 0; i
< count
; i
++)
3683 total
+= exec_list
[i
].relocation_count
;
3685 reloc
= drm_malloc_ab(total
, sizeof(*reloc
));
3686 if (reloc
== NULL
) {
3687 mutex_lock(&dev
->struct_mutex
);
3692 for (i
= 0; i
< count
; i
++) {
3693 struct drm_i915_gem_relocation_entry __user
*user_relocs
;
3695 user_relocs
= (void __user
*)(uintptr_t)exec_list
[i
].relocs_ptr
;
3697 if (copy_from_user(reloc
+total
, user_relocs
,
3698 exec_list
[i
].relocation_count
*
3701 mutex_lock(&dev
->struct_mutex
);
3705 total
+= exec_list
[i
].relocation_count
;
3708 ret
= i915_mutex_lock_interruptible(dev
);
3710 mutex_lock(&dev
->struct_mutex
);
3714 ret
= i915_gem_execbuffer_reserve(dev
, file
,
3715 object_list
, exec_list
,
3721 for (i
= 0; i
< count
; i
++) {
3722 struct drm_i915_gem_object
*obj
= to_intel_bo(object_list
[i
]);
3723 obj
->base
.pending_read_domains
= 0;
3724 obj
->base
.pending_write_domain
= 0;
3725 ret
= i915_gem_execbuffer_relocate_object_slow(obj
, file
,
3731 total
+= exec_list
[i
].relocation_count
;
3734 /* Leave the user relocations as are, this is the painfully slow path,
3735 * and we want to avoid the complication of dropping the lock whilst
3736 * having buffers reserved in the aperture and so causing spurious
3737 * ENOSPC for random operations.
3741 drm_free_large(reloc
);
3746 i915_gem_execbuffer_move_to_gpu(struct drm_device
*dev
,
3747 struct drm_file
*file
,
3748 struct intel_ring_buffer
*ring
,
3749 struct drm_gem_object
**objects
,
3752 struct change_domains cd
;
3755 cd
.invalidate_domains
= 0;
3756 cd
.flush_domains
= 0;
3758 for (i
= 0; i
< count
; i
++)
3759 i915_gem_object_set_to_gpu_domain(objects
[i
], ring
, &cd
);
3761 if (cd
.invalidate_domains
| cd
.flush_domains
) {
3763 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
3765 cd
.invalidate_domains
,
3768 i915_gem_flush(dev
, file
,
3769 cd
.invalidate_domains
,
3774 for (i
= 0; i
< count
; i
++) {
3775 struct drm_i915_gem_object
*obj
= to_intel_bo(objects
[i
]);
3776 /* XXX replace with semaphores */
3777 if (obj
->ring
&& ring
!= obj
->ring
) {
3778 ret
= i915_gem_object_wait_rendering(&obj
->base
, true);
3787 /* Throttle our rendering by waiting until the ring has completed our requests
3788 * emitted over 20 msec ago.
3790 * Note that if we were to use the current jiffies each time around the loop,
3791 * we wouldn't escape the function with any frames outstanding if the time to
3792 * render a frame was over 20ms.
3794 * This should get us reasonable parallelism between CPU and GPU but also
3795 * relatively low latency when blocking on a particular request to finish.
3798 i915_gem_ring_throttle(struct drm_device
*dev
, struct drm_file
*file
)
3800 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3801 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
3802 unsigned long recent_enough
= jiffies
- msecs_to_jiffies(20);
3803 struct drm_i915_gem_request
*request
;
3804 struct intel_ring_buffer
*ring
= NULL
;
3808 spin_lock(&file_priv
->mm
.lock
);
3809 list_for_each_entry(request
, &file_priv
->mm
.request_list
, client_list
) {
3810 if (time_after_eq(request
->emitted_jiffies
, recent_enough
))
3813 ring
= request
->ring
;
3814 seqno
= request
->seqno
;
3816 spin_unlock(&file_priv
->mm
.lock
);
3822 if (!i915_seqno_passed(ring
->get_seqno(ring
), seqno
)) {
3823 /* And wait for the seqno passing without holding any locks and
3824 * causing extra latency for others. This is safe as the irq
3825 * generation is designed to be run atomically and so is
3828 ring
->user_irq_get(ring
);
3829 ret
= wait_event_interruptible(ring
->irq_queue
,
3830 i915_seqno_passed(ring
->get_seqno(ring
), seqno
)
3831 || atomic_read(&dev_priv
->mm
.wedged
));
3832 ring
->user_irq_put(ring
);
3834 if (ret
== 0 && atomic_read(&dev_priv
->mm
.wedged
))
3839 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, 0);
3845 i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2
*exec
,
3846 uint64_t exec_offset
)
3848 uint32_t exec_start
, exec_len
;
3850 exec_start
= (uint32_t) exec_offset
+ exec
->batch_start_offset
;
3851 exec_len
= (uint32_t) exec
->batch_len
;
3853 if ((exec_start
| exec_len
) & 0x7)
3863 validate_exec_list(struct drm_i915_gem_exec_object2
*exec
,
3868 for (i
= 0; i
< count
; i
++) {
3869 char __user
*ptr
= (char __user
*)(uintptr_t)exec
[i
].relocs_ptr
;
3870 int length
; /* limited by fault_in_pages_readable() */
3872 /* First check for malicious input causing overflow */
3873 if (exec
[i
].relocation_count
>
3874 INT_MAX
/ sizeof(struct drm_i915_gem_relocation_entry
))
3877 length
= exec
[i
].relocation_count
*
3878 sizeof(struct drm_i915_gem_relocation_entry
);
3879 if (!access_ok(VERIFY_READ
, ptr
, length
))
3882 /* we may also need to update the presumed offsets */
3883 if (!access_ok(VERIFY_WRITE
, ptr
, length
))
3886 if (fault_in_pages_readable(ptr
, length
))
3894 i915_gem_do_execbuffer(struct drm_device
*dev
, void *data
,
3895 struct drm_file
*file
,
3896 struct drm_i915_gem_execbuffer2
*args
,
3897 struct drm_i915_gem_exec_object2
*exec_list
)
3899 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3900 struct drm_gem_object
**object_list
= NULL
;
3901 struct drm_gem_object
*batch_obj
;
3902 struct drm_clip_rect
*cliprects
= NULL
;
3903 struct drm_i915_gem_request
*request
= NULL
;
3905 uint64_t exec_offset
;
3907 struct intel_ring_buffer
*ring
= NULL
;
3909 ret
= i915_gem_check_is_wedged(dev
);
3913 ret
= validate_exec_list(exec_list
, args
->buffer_count
);
3918 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3919 (int) args
->buffers_ptr
, args
->buffer_count
, args
->batch_len
);
3921 switch (args
->flags
& I915_EXEC_RING_MASK
) {
3922 case I915_EXEC_DEFAULT
:
3923 case I915_EXEC_RENDER
:
3924 ring
= &dev_priv
->render_ring
;
3927 if (!HAS_BSD(dev
)) {
3928 DRM_ERROR("execbuf with invalid ring (BSD)\n");
3931 ring
= &dev_priv
->bsd_ring
;
3934 if (!HAS_BLT(dev
)) {
3935 DRM_ERROR("execbuf with invalid ring (BLT)\n");
3938 ring
= &dev_priv
->blt_ring
;
3941 DRM_ERROR("execbuf with unknown ring: %d\n",
3942 (int)(args
->flags
& I915_EXEC_RING_MASK
));
3946 if (args
->buffer_count
< 1) {
3947 DRM_ERROR("execbuf with %d buffers\n", args
->buffer_count
);
3950 object_list
= drm_malloc_ab(sizeof(*object_list
), args
->buffer_count
);
3951 if (object_list
== NULL
) {
3952 DRM_ERROR("Failed to allocate object list for %d buffers\n",
3953 args
->buffer_count
);
3958 if (args
->num_cliprects
!= 0) {
3959 cliprects
= kcalloc(args
->num_cliprects
, sizeof(*cliprects
),
3961 if (cliprects
== NULL
) {
3966 ret
= copy_from_user(cliprects
,
3967 (struct drm_clip_rect __user
*)
3968 (uintptr_t) args
->cliprects_ptr
,
3969 sizeof(*cliprects
) * args
->num_cliprects
);
3971 DRM_ERROR("copy %d cliprects failed: %d\n",
3972 args
->num_cliprects
, ret
);
3978 request
= kzalloc(sizeof(*request
), GFP_KERNEL
);
3979 if (request
== NULL
) {
3984 ret
= i915_mutex_lock_interruptible(dev
);
3988 if (dev_priv
->mm
.suspended
) {
3989 mutex_unlock(&dev
->struct_mutex
);
3994 /* Look up object handles */
3995 for (i
= 0; i
< args
->buffer_count
; i
++) {
3996 struct drm_i915_gem_object
*obj_priv
;
3998 object_list
[i
] = drm_gem_object_lookup(dev
, file
,
3999 exec_list
[i
].handle
);
4000 if (object_list
[i
] == NULL
) {
4001 DRM_ERROR("Invalid object handle %d at index %d\n",
4002 exec_list
[i
].handle
, i
);
4003 /* prevent error path from reading uninitialized data */
4004 args
->buffer_count
= i
+ 1;
4009 obj_priv
= to_intel_bo(object_list
[i
]);
4010 if (obj_priv
->in_execbuffer
) {
4011 DRM_ERROR("Object %p appears more than once in object list\n",
4013 /* prevent error path from reading uninitialized data */
4014 args
->buffer_count
= i
+ 1;
4018 obj_priv
->in_execbuffer
= true;
4021 /* Move the objects en-masse into the GTT, evicting if necessary. */
4022 ret
= i915_gem_execbuffer_reserve(dev
, file
,
4023 object_list
, exec_list
,
4024 args
->buffer_count
);
4028 /* The objects are in their final locations, apply the relocations. */
4029 ret
= i915_gem_execbuffer_relocate(dev
, file
,
4030 object_list
, exec_list
,
4031 args
->buffer_count
);
4033 if (ret
== -EFAULT
) {
4034 ret
= i915_gem_execbuffer_relocate_slow(dev
, file
,
4037 args
->buffer_count
);
4038 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
4044 /* Set the pending read domains for the batch buffer to COMMAND */
4045 batch_obj
= object_list
[args
->buffer_count
-1];
4046 if (batch_obj
->pending_write_domain
) {
4047 DRM_ERROR("Attempting to use self-modifying batch buffer\n");
4051 batch_obj
->pending_read_domains
|= I915_GEM_DOMAIN_COMMAND
;
4053 /* Sanity check the batch buffer */
4054 exec_offset
= to_intel_bo(batch_obj
)->gtt_offset
;
4055 ret
= i915_gem_check_execbuffer(args
, exec_offset
);
4057 DRM_ERROR("execbuf with invalid offset/length\n");
4061 ret
= i915_gem_execbuffer_move_to_gpu(dev
, file
, ring
,
4062 object_list
, args
->buffer_count
);
4067 for (i
= 0; i
< args
->buffer_count
; i
++) {
4068 i915_gem_object_check_coherency(object_list
[i
],
4069 exec_list
[i
].handle
);
4074 i915_gem_dump_object(batch_obj
,
4080 /* Check for any pending flips. As we only maintain a flip queue depth
4081 * of 1, we can simply insert a WAIT for the next display flip prior
4082 * to executing the batch and avoid stalling the CPU.
4085 for (i
= 0; i
< args
->buffer_count
; i
++) {
4086 if (object_list
[i
]->write_domain
)
4087 flips
|= atomic_read(&to_intel_bo(object_list
[i
])->pending_flip
);
4090 int plane
, flip_mask
;
4092 for (plane
= 0; flips
>> plane
; plane
++) {
4093 if (((flips
>> plane
) & 1) == 0)
4097 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
4099 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
4101 ret
= intel_ring_begin(ring
, 2);
4105 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
4106 intel_ring_emit(ring
, MI_NOOP
);
4107 intel_ring_advance(ring
);
4111 /* Exec the batchbuffer */
4112 ret
= ring
->dispatch_execbuffer(ring
, args
, cliprects
, exec_offset
);
4114 DRM_ERROR("dispatch failed %d\n", ret
);
4118 for (i
= 0; i
< args
->buffer_count
; i
++) {
4119 struct drm_gem_object
*obj
= object_list
[i
];
4121 obj
->read_domains
= obj
->pending_read_domains
;
4122 obj
->write_domain
= obj
->pending_write_domain
;
4124 i915_gem_object_move_to_active(obj
, ring
);
4125 if (obj
->write_domain
) {
4126 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
4127 obj_priv
->dirty
= 1;
4128 list_move_tail(&obj_priv
->gpu_write_list
,
4129 &ring
->gpu_write_list
);
4130 intel_mark_busy(dev
, obj
);
4133 trace_i915_gem_object_change_domain(obj
,
4139 * Ensure that the commands in the batch buffer are
4140 * finished before the interrupt fires
4142 i915_retire_commands(dev
, ring
);
4144 if (i915_add_request(dev
, file
, request
, ring
))
4145 i915_gem_next_request_seqno(dev
, ring
);
4150 for (i
= 0; i
< args
->buffer_count
; i
++) {
4151 if (object_list
[i
] == NULL
)
4154 to_intel_bo(object_list
[i
])->in_execbuffer
= false;
4155 drm_gem_object_unreference(object_list
[i
]);
4158 mutex_unlock(&dev
->struct_mutex
);
4161 drm_free_large(object_list
);
4169 * Legacy execbuffer just creates an exec2 list from the original exec object
4170 * list array and passes it to the real function.
4173 i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
4174 struct drm_file
*file_priv
)
4176 struct drm_i915_gem_execbuffer
*args
= data
;
4177 struct drm_i915_gem_execbuffer2 exec2
;
4178 struct drm_i915_gem_exec_object
*exec_list
= NULL
;
4179 struct drm_i915_gem_exec_object2
*exec2_list
= NULL
;
4183 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
4184 (int) args
->buffers_ptr
, args
->buffer_count
, args
->batch_len
);
4187 if (args
->buffer_count
< 1) {
4188 DRM_ERROR("execbuf with %d buffers\n", args
->buffer_count
);
4192 /* Copy in the exec list from userland */
4193 exec_list
= drm_malloc_ab(sizeof(*exec_list
), args
->buffer_count
);
4194 exec2_list
= drm_malloc_ab(sizeof(*exec2_list
), args
->buffer_count
);
4195 if (exec_list
== NULL
|| exec2_list
== NULL
) {
4196 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
4197 args
->buffer_count
);
4198 drm_free_large(exec_list
);
4199 drm_free_large(exec2_list
);
4202 ret
= copy_from_user(exec_list
,
4203 (struct drm_i915_relocation_entry __user
*)
4204 (uintptr_t) args
->buffers_ptr
,
4205 sizeof(*exec_list
) * args
->buffer_count
);
4207 DRM_ERROR("copy %d exec entries failed %d\n",
4208 args
->buffer_count
, ret
);
4209 drm_free_large(exec_list
);
4210 drm_free_large(exec2_list
);
4214 for (i
= 0; i
< args
->buffer_count
; i
++) {
4215 exec2_list
[i
].handle
= exec_list
[i
].handle
;
4216 exec2_list
[i
].relocation_count
= exec_list
[i
].relocation_count
;
4217 exec2_list
[i
].relocs_ptr
= exec_list
[i
].relocs_ptr
;
4218 exec2_list
[i
].alignment
= exec_list
[i
].alignment
;
4219 exec2_list
[i
].offset
= exec_list
[i
].offset
;
4220 if (INTEL_INFO(dev
)->gen
< 4)
4221 exec2_list
[i
].flags
= EXEC_OBJECT_NEEDS_FENCE
;
4223 exec2_list
[i
].flags
= 0;
4226 exec2
.buffers_ptr
= args
->buffers_ptr
;
4227 exec2
.buffer_count
= args
->buffer_count
;
4228 exec2
.batch_start_offset
= args
->batch_start_offset
;
4229 exec2
.batch_len
= args
->batch_len
;
4230 exec2
.DR1
= args
->DR1
;
4231 exec2
.DR4
= args
->DR4
;
4232 exec2
.num_cliprects
= args
->num_cliprects
;
4233 exec2
.cliprects_ptr
= args
->cliprects_ptr
;
4234 exec2
.flags
= I915_EXEC_RENDER
;
4236 ret
= i915_gem_do_execbuffer(dev
, data
, file_priv
, &exec2
, exec2_list
);
4238 /* Copy the new buffer offsets back to the user's exec list. */
4239 for (i
= 0; i
< args
->buffer_count
; i
++)
4240 exec_list
[i
].offset
= exec2_list
[i
].offset
;
4241 /* ... and back out to userspace */
4242 ret
= copy_to_user((struct drm_i915_relocation_entry __user
*)
4243 (uintptr_t) args
->buffers_ptr
,
4245 sizeof(*exec_list
) * args
->buffer_count
);
4248 DRM_ERROR("failed to copy %d exec entries "
4249 "back to user (%d)\n",
4250 args
->buffer_count
, ret
);
4254 drm_free_large(exec_list
);
4255 drm_free_large(exec2_list
);
4260 i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
4261 struct drm_file
*file_priv
)
4263 struct drm_i915_gem_execbuffer2
*args
= data
;
4264 struct drm_i915_gem_exec_object2
*exec2_list
= NULL
;
4268 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
4269 (int) args
->buffers_ptr
, args
->buffer_count
, args
->batch_len
);
4272 if (args
->buffer_count
< 1) {
4273 DRM_ERROR("execbuf2 with %d buffers\n", args
->buffer_count
);
4277 exec2_list
= drm_malloc_ab(sizeof(*exec2_list
), args
->buffer_count
);
4278 if (exec2_list
== NULL
) {
4279 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
4280 args
->buffer_count
);
4283 ret
= copy_from_user(exec2_list
,
4284 (struct drm_i915_relocation_entry __user
*)
4285 (uintptr_t) args
->buffers_ptr
,
4286 sizeof(*exec2_list
) * args
->buffer_count
);
4288 DRM_ERROR("copy %d exec entries failed %d\n",
4289 args
->buffer_count
, ret
);
4290 drm_free_large(exec2_list
);
4294 ret
= i915_gem_do_execbuffer(dev
, data
, file_priv
, args
, exec2_list
);
4296 /* Copy the new buffer offsets back to the user's exec list. */
4297 ret
= copy_to_user((struct drm_i915_relocation_entry __user
*)
4298 (uintptr_t) args
->buffers_ptr
,
4300 sizeof(*exec2_list
) * args
->buffer_count
);
4303 DRM_ERROR("failed to copy %d exec entries "
4304 "back to user (%d)\n",
4305 args
->buffer_count
, ret
);
4309 drm_free_large(exec2_list
);
4314 i915_gem_object_pin(struct drm_gem_object
*obj
, uint32_t alignment
,
4315 bool map_and_fenceable
)
4317 struct drm_device
*dev
= obj
->dev
;
4318 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4319 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
4322 BUG_ON(obj_priv
->pin_count
== DRM_I915_GEM_OBJECT_MAX_PIN_COUNT
);
4323 BUG_ON(map_and_fenceable
&& !map_and_fenceable
);
4324 WARN_ON(i915_verify_lists(dev
));
4326 if (obj_priv
->gtt_space
!= NULL
) {
4327 if ((alignment
&& obj_priv
->gtt_offset
& (alignment
- 1)) ||
4328 (map_and_fenceable
&& !obj_priv
->map_and_fenceable
)) {
4329 WARN(obj_priv
->pin_count
,
4330 "bo is already pinned with incorrect alignment:"
4331 " offset=%x, req.alignment=%x, req.map_and_fenceable=%d,"
4332 " obj->map_and_fenceable=%d\n",
4333 obj_priv
->gtt_offset
, alignment
,
4335 obj_priv
->map_and_fenceable
);
4336 ret
= i915_gem_object_unbind(obj
);
4342 if (obj_priv
->gtt_space
== NULL
) {
4343 ret
= i915_gem_object_bind_to_gtt(obj
, alignment
,
4349 if (obj_priv
->pin_count
++ == 0) {
4350 i915_gem_info_add_pin(dev_priv
, obj_priv
, map_and_fenceable
);
4351 if (!obj_priv
->active
)
4352 list_move_tail(&obj_priv
->mm_list
,
4353 &dev_priv
->mm
.pinned_list
);
4355 BUG_ON(!obj_priv
->pin_mappable
&& map_and_fenceable
);
4357 WARN_ON(i915_verify_lists(dev
));
4362 i915_gem_object_unpin(struct drm_gem_object
*obj
)
4364 struct drm_device
*dev
= obj
->dev
;
4365 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4366 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
4368 WARN_ON(i915_verify_lists(dev
));
4369 BUG_ON(obj_priv
->pin_count
== 0);
4370 BUG_ON(obj_priv
->gtt_space
== NULL
);
4372 if (--obj_priv
->pin_count
== 0) {
4373 if (!obj_priv
->active
)
4374 list_move_tail(&obj_priv
->mm_list
,
4375 &dev_priv
->mm
.inactive_list
);
4376 i915_gem_info_remove_pin(dev_priv
, obj_priv
);
4378 WARN_ON(i915_verify_lists(dev
));
4382 i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
4383 struct drm_file
*file_priv
)
4385 struct drm_i915_gem_pin
*args
= data
;
4386 struct drm_gem_object
*obj
;
4387 struct drm_i915_gem_object
*obj_priv
;
4390 ret
= i915_mutex_lock_interruptible(dev
);
4394 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4399 obj_priv
= to_intel_bo(obj
);
4401 if (obj_priv
->madv
!= I915_MADV_WILLNEED
) {
4402 DRM_ERROR("Attempting to pin a purgeable buffer\n");
4407 if (obj_priv
->pin_filp
!= NULL
&& obj_priv
->pin_filp
!= file_priv
) {
4408 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
4414 obj_priv
->user_pin_count
++;
4415 obj_priv
->pin_filp
= file_priv
;
4416 if (obj_priv
->user_pin_count
== 1) {
4417 ret
= i915_gem_object_pin(obj
, args
->alignment
, true);
4422 /* XXX - flush the CPU caches for pinned objects
4423 * as the X server doesn't manage domains yet
4425 i915_gem_object_flush_cpu_write_domain(obj
);
4426 args
->offset
= obj_priv
->gtt_offset
;
4428 drm_gem_object_unreference(obj
);
4430 mutex_unlock(&dev
->struct_mutex
);
4435 i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
4436 struct drm_file
*file_priv
)
4438 struct drm_i915_gem_pin
*args
= data
;
4439 struct drm_gem_object
*obj
;
4440 struct drm_i915_gem_object
*obj_priv
;
4443 ret
= i915_mutex_lock_interruptible(dev
);
4447 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4452 obj_priv
= to_intel_bo(obj
);
4454 if (obj_priv
->pin_filp
!= file_priv
) {
4455 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4460 obj_priv
->user_pin_count
--;
4461 if (obj_priv
->user_pin_count
== 0) {
4462 obj_priv
->pin_filp
= NULL
;
4463 i915_gem_object_unpin(obj
);
4467 drm_gem_object_unreference(obj
);
4469 mutex_unlock(&dev
->struct_mutex
);
4474 i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
4475 struct drm_file
*file_priv
)
4477 struct drm_i915_gem_busy
*args
= data
;
4478 struct drm_gem_object
*obj
;
4479 struct drm_i915_gem_object
*obj_priv
;
4482 ret
= i915_mutex_lock_interruptible(dev
);
4486 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4491 obj_priv
= to_intel_bo(obj
);
4493 /* Count all active objects as busy, even if they are currently not used
4494 * by the gpu. Users of this interface expect objects to eventually
4495 * become non-busy without any further actions, therefore emit any
4496 * necessary flushes here.
4498 args
->busy
= obj_priv
->active
;
4500 /* Unconditionally flush objects, even when the gpu still uses this
4501 * object. Userspace calling this function indicates that it wants to
4502 * use this buffer rather sooner than later, so issuing the required
4503 * flush earlier is beneficial.
4505 if (obj
->write_domain
& I915_GEM_GPU_DOMAINS
)
4506 i915_gem_flush_ring(dev
, file_priv
,
4508 0, obj
->write_domain
);
4510 /* Update the active list for the hardware's current position.
4511 * Otherwise this only updates on a delayed timer or when irqs
4512 * are actually unmasked, and our working set ends up being
4513 * larger than required.
4515 i915_gem_retire_requests_ring(dev
, obj_priv
->ring
);
4517 args
->busy
= obj_priv
->active
;
4520 drm_gem_object_unreference(obj
);
4522 mutex_unlock(&dev
->struct_mutex
);
4527 i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
4528 struct drm_file
*file_priv
)
4530 return i915_gem_ring_throttle(dev
, file_priv
);
4534 i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
4535 struct drm_file
*file_priv
)
4537 struct drm_i915_gem_madvise
*args
= data
;
4538 struct drm_gem_object
*obj
;
4539 struct drm_i915_gem_object
*obj_priv
;
4542 switch (args
->madv
) {
4543 case I915_MADV_DONTNEED
:
4544 case I915_MADV_WILLNEED
:
4550 ret
= i915_mutex_lock_interruptible(dev
);
4554 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4559 obj_priv
= to_intel_bo(obj
);
4561 if (obj_priv
->pin_count
) {
4566 if (obj_priv
->madv
!= __I915_MADV_PURGED
)
4567 obj_priv
->madv
= args
->madv
;
4569 /* if the object is no longer bound, discard its backing storage */
4570 if (i915_gem_object_is_purgeable(obj_priv
) &&
4571 obj_priv
->gtt_space
== NULL
)
4572 i915_gem_object_truncate(obj
);
4574 args
->retained
= obj_priv
->madv
!= __I915_MADV_PURGED
;
4577 drm_gem_object_unreference(obj
);
4579 mutex_unlock(&dev
->struct_mutex
);
4583 struct drm_gem_object
* i915_gem_alloc_object(struct drm_device
*dev
,
4586 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4587 struct drm_i915_gem_object
*obj
;
4589 obj
= kzalloc(sizeof(*obj
), GFP_KERNEL
);
4593 if (drm_gem_object_init(dev
, &obj
->base
, size
) != 0) {
4598 i915_gem_info_add_obj(dev_priv
, size
);
4600 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
4601 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
4603 obj
->agp_type
= AGP_USER_MEMORY
;
4604 obj
->base
.driver_private
= NULL
;
4605 obj
->fence_reg
= I915_FENCE_REG_NONE
;
4606 INIT_LIST_HEAD(&obj
->mm_list
);
4607 INIT_LIST_HEAD(&obj
->ring_list
);
4608 INIT_LIST_HEAD(&obj
->gpu_write_list
);
4609 obj
->madv
= I915_MADV_WILLNEED
;
4610 /* Avoid an unnecessary call to unbind on the first bind. */
4611 obj
->map_and_fenceable
= true;
4616 int i915_gem_init_object(struct drm_gem_object
*obj
)
4623 static void i915_gem_free_object_tail(struct drm_gem_object
*obj
)
4625 struct drm_device
*dev
= obj
->dev
;
4626 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4627 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
4630 ret
= i915_gem_object_unbind(obj
);
4631 if (ret
== -ERESTARTSYS
) {
4632 list_move(&obj_priv
->mm_list
,
4633 &dev_priv
->mm
.deferred_free_list
);
4637 if (obj
->map_list
.map
)
4638 i915_gem_free_mmap_offset(obj
);
4640 drm_gem_object_release(obj
);
4641 i915_gem_info_remove_obj(dev_priv
, obj
->size
);
4643 kfree(obj_priv
->page_cpu_valid
);
4644 kfree(obj_priv
->bit_17
);
4648 void i915_gem_free_object(struct drm_gem_object
*obj
)
4650 struct drm_device
*dev
= obj
->dev
;
4651 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
4653 trace_i915_gem_object_destroy(obj
);
4655 while (obj_priv
->pin_count
> 0)
4656 i915_gem_object_unpin(obj
);
4658 if (obj_priv
->phys_obj
)
4659 i915_gem_detach_phys_object(dev
, obj
);
4661 i915_gem_free_object_tail(obj
);
4665 i915_gem_idle(struct drm_device
*dev
)
4667 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4670 mutex_lock(&dev
->struct_mutex
);
4672 if (dev_priv
->mm
.suspended
) {
4673 mutex_unlock(&dev
->struct_mutex
);
4677 ret
= i915_gpu_idle(dev
);
4679 mutex_unlock(&dev
->struct_mutex
);
4683 /* Under UMS, be paranoid and evict. */
4684 if (!drm_core_check_feature(dev
, DRIVER_MODESET
)) {
4685 ret
= i915_gem_evict_inactive(dev
, false);
4687 mutex_unlock(&dev
->struct_mutex
);
4692 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4693 * We need to replace this with a semaphore, or something.
4694 * And not confound mm.suspended!
4696 dev_priv
->mm
.suspended
= 1;
4697 del_timer_sync(&dev_priv
->hangcheck_timer
);
4699 i915_kernel_lost_context(dev
);
4700 i915_gem_cleanup_ringbuffer(dev
);
4702 mutex_unlock(&dev
->struct_mutex
);
4704 /* Cancel the retire work handler, which should be idle now. */
4705 cancel_delayed_work_sync(&dev_priv
->mm
.retire_work
);
4711 * 965+ support PIPE_CONTROL commands, which provide finer grained control
4712 * over cache flushing.
4715 i915_gem_init_pipe_control(struct drm_device
*dev
)
4717 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4718 struct drm_gem_object
*obj
;
4719 struct drm_i915_gem_object
*obj_priv
;
4722 obj
= i915_gem_alloc_object(dev
, 4096);
4724 DRM_ERROR("Failed to allocate seqno page\n");
4728 obj_priv
= to_intel_bo(obj
);
4729 obj_priv
->agp_type
= AGP_USER_CACHED_MEMORY
;
4731 ret
= i915_gem_object_pin(obj
, 4096, true);
4735 dev_priv
->seqno_gfx_addr
= obj_priv
->gtt_offset
;
4736 dev_priv
->seqno_page
= kmap(obj_priv
->pages
[0]);
4737 if (dev_priv
->seqno_page
== NULL
)
4740 dev_priv
->seqno_obj
= obj
;
4741 memset(dev_priv
->seqno_page
, 0, PAGE_SIZE
);
4746 i915_gem_object_unpin(obj
);
4748 drm_gem_object_unreference(obj
);
4755 i915_gem_cleanup_pipe_control(struct drm_device
*dev
)
4757 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4758 struct drm_gem_object
*obj
;
4759 struct drm_i915_gem_object
*obj_priv
;
4761 obj
= dev_priv
->seqno_obj
;
4762 obj_priv
= to_intel_bo(obj
);
4763 kunmap(obj_priv
->pages
[0]);
4764 i915_gem_object_unpin(obj
);
4765 drm_gem_object_unreference(obj
);
4766 dev_priv
->seqno_obj
= NULL
;
4768 dev_priv
->seqno_page
= NULL
;
4772 i915_gem_init_ringbuffer(struct drm_device
*dev
)
4774 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4777 if (HAS_PIPE_CONTROL(dev
)) {
4778 ret
= i915_gem_init_pipe_control(dev
);
4783 ret
= intel_init_render_ring_buffer(dev
);
4785 goto cleanup_pipe_control
;
4788 ret
= intel_init_bsd_ring_buffer(dev
);
4790 goto cleanup_render_ring
;
4794 ret
= intel_init_blt_ring_buffer(dev
);
4796 goto cleanup_bsd_ring
;
4799 dev_priv
->next_seqno
= 1;
4804 intel_cleanup_ring_buffer(&dev_priv
->bsd_ring
);
4805 cleanup_render_ring
:
4806 intel_cleanup_ring_buffer(&dev_priv
->render_ring
);
4807 cleanup_pipe_control
:
4808 if (HAS_PIPE_CONTROL(dev
))
4809 i915_gem_cleanup_pipe_control(dev
);
4814 i915_gem_cleanup_ringbuffer(struct drm_device
*dev
)
4816 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4818 intel_cleanup_ring_buffer(&dev_priv
->render_ring
);
4819 intel_cleanup_ring_buffer(&dev_priv
->bsd_ring
);
4820 intel_cleanup_ring_buffer(&dev_priv
->blt_ring
);
4821 if (HAS_PIPE_CONTROL(dev
))
4822 i915_gem_cleanup_pipe_control(dev
);
4826 i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
4827 struct drm_file
*file_priv
)
4829 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4832 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4835 if (atomic_read(&dev_priv
->mm
.wedged
)) {
4836 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4837 atomic_set(&dev_priv
->mm
.wedged
, 0);
4840 mutex_lock(&dev
->struct_mutex
);
4841 dev_priv
->mm
.suspended
= 0;
4843 ret
= i915_gem_init_ringbuffer(dev
);
4845 mutex_unlock(&dev
->struct_mutex
);
4849 BUG_ON(!list_empty(&dev_priv
->mm
.active_list
));
4850 BUG_ON(!list_empty(&dev_priv
->render_ring
.active_list
));
4851 BUG_ON(!list_empty(&dev_priv
->bsd_ring
.active_list
));
4852 BUG_ON(!list_empty(&dev_priv
->blt_ring
.active_list
));
4853 BUG_ON(!list_empty(&dev_priv
->mm
.flushing_list
));
4854 BUG_ON(!list_empty(&dev_priv
->mm
.inactive_list
));
4855 BUG_ON(!list_empty(&dev_priv
->render_ring
.request_list
));
4856 BUG_ON(!list_empty(&dev_priv
->bsd_ring
.request_list
));
4857 BUG_ON(!list_empty(&dev_priv
->blt_ring
.request_list
));
4858 mutex_unlock(&dev
->struct_mutex
);
4860 ret
= drm_irq_install(dev
);
4862 goto cleanup_ringbuffer
;
4867 mutex_lock(&dev
->struct_mutex
);
4868 i915_gem_cleanup_ringbuffer(dev
);
4869 dev_priv
->mm
.suspended
= 1;
4870 mutex_unlock(&dev
->struct_mutex
);
4876 i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
4877 struct drm_file
*file_priv
)
4879 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4882 drm_irq_uninstall(dev
);
4883 return i915_gem_idle(dev
);
4887 i915_gem_lastclose(struct drm_device
*dev
)
4891 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4894 ret
= i915_gem_idle(dev
);
4896 DRM_ERROR("failed to idle hardware: %d\n", ret
);
4900 init_ring_lists(struct intel_ring_buffer
*ring
)
4902 INIT_LIST_HEAD(&ring
->active_list
);
4903 INIT_LIST_HEAD(&ring
->request_list
);
4904 INIT_LIST_HEAD(&ring
->gpu_write_list
);
4908 i915_gem_load(struct drm_device
*dev
)
4911 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4913 INIT_LIST_HEAD(&dev_priv
->mm
.active_list
);
4914 INIT_LIST_HEAD(&dev_priv
->mm
.flushing_list
);
4915 INIT_LIST_HEAD(&dev_priv
->mm
.inactive_list
);
4916 INIT_LIST_HEAD(&dev_priv
->mm
.pinned_list
);
4917 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
4918 INIT_LIST_HEAD(&dev_priv
->mm
.deferred_free_list
);
4919 init_ring_lists(&dev_priv
->render_ring
);
4920 init_ring_lists(&dev_priv
->bsd_ring
);
4921 init_ring_lists(&dev_priv
->blt_ring
);
4922 for (i
= 0; i
< 16; i
++)
4923 INIT_LIST_HEAD(&dev_priv
->fence_regs
[i
].lru_list
);
4924 INIT_DELAYED_WORK(&dev_priv
->mm
.retire_work
,
4925 i915_gem_retire_work_handler
);
4926 init_completion(&dev_priv
->error_completion
);
4928 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4930 u32 tmp
= I915_READ(MI_ARB_STATE
);
4931 if (!(tmp
& MI_ARB_C3_LP_WRITE_ENABLE
)) {
4932 /* arb state is a masked write, so set bit + bit in mask */
4933 tmp
= MI_ARB_C3_LP_WRITE_ENABLE
| (MI_ARB_C3_LP_WRITE_ENABLE
<< MI_ARB_MASK_SHIFT
);
4934 I915_WRITE(MI_ARB_STATE
, tmp
);
4938 /* Old X drivers will take 0-2 for front, back, depth buffers */
4939 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
4940 dev_priv
->fence_reg_start
= 3;
4942 if (INTEL_INFO(dev
)->gen
>= 4 || IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
4943 dev_priv
->num_fence_regs
= 16;
4945 dev_priv
->num_fence_regs
= 8;
4947 /* Initialize fence registers to zero */
4948 switch (INTEL_INFO(dev
)->gen
) {
4950 for (i
= 0; i
< 16; i
++)
4951 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0
+ (i
* 8), 0);
4955 for (i
= 0; i
< 16; i
++)
4956 I915_WRITE64(FENCE_REG_965_0
+ (i
* 8), 0);
4959 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
4960 for (i
= 0; i
< 8; i
++)
4961 I915_WRITE(FENCE_REG_945_8
+ (i
* 4), 0);
4963 for (i
= 0; i
< 8; i
++)
4964 I915_WRITE(FENCE_REG_830_0
+ (i
* 4), 0);
4967 i915_gem_detect_bit_6_swizzle(dev
);
4968 init_waitqueue_head(&dev_priv
->pending_flip_queue
);
4970 dev_priv
->mm
.inactive_shrinker
.shrink
= i915_gem_inactive_shrink
;
4971 dev_priv
->mm
.inactive_shrinker
.seeks
= DEFAULT_SEEKS
;
4972 register_shrinker(&dev_priv
->mm
.inactive_shrinker
);
4976 * Create a physically contiguous memory object for this object
4977 * e.g. for cursor + overlay regs
4979 static int i915_gem_init_phys_object(struct drm_device
*dev
,
4980 int id
, int size
, int align
)
4982 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4983 struct drm_i915_gem_phys_object
*phys_obj
;
4986 if (dev_priv
->mm
.phys_objs
[id
- 1] || !size
)
4989 phys_obj
= kzalloc(sizeof(struct drm_i915_gem_phys_object
), GFP_KERNEL
);
4995 phys_obj
->handle
= drm_pci_alloc(dev
, size
, align
);
4996 if (!phys_obj
->handle
) {
5001 set_memory_wc((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
5004 dev_priv
->mm
.phys_objs
[id
- 1] = phys_obj
;
5012 static void i915_gem_free_phys_object(struct drm_device
*dev
, int id
)
5014 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
5015 struct drm_i915_gem_phys_object
*phys_obj
;
5017 if (!dev_priv
->mm
.phys_objs
[id
- 1])
5020 phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
5021 if (phys_obj
->cur_obj
) {
5022 i915_gem_detach_phys_object(dev
, phys_obj
->cur_obj
);
5026 set_memory_wb((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
5028 drm_pci_free(dev
, phys_obj
->handle
);
5030 dev_priv
->mm
.phys_objs
[id
- 1] = NULL
;
5033 void i915_gem_free_all_phys_object(struct drm_device
*dev
)
5037 for (i
= I915_GEM_PHYS_CURSOR_0
; i
<= I915_MAX_PHYS_OBJECT
; i
++)
5038 i915_gem_free_phys_object(dev
, i
);
5041 void i915_gem_detach_phys_object(struct drm_device
*dev
,
5042 struct drm_gem_object
*obj
)
5044 struct address_space
*mapping
= obj
->filp
->f_path
.dentry
->d_inode
->i_mapping
;
5045 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
5050 if (!obj_priv
->phys_obj
)
5052 vaddr
= obj_priv
->phys_obj
->handle
->vaddr
;
5054 page_count
= obj
->size
/ PAGE_SIZE
;
5056 for (i
= 0; i
< page_count
; i
++) {
5057 struct page
*page
= read_cache_page_gfp(mapping
, i
,
5058 GFP_HIGHUSER
| __GFP_RECLAIMABLE
);
5059 if (!IS_ERR(page
)) {
5060 char *dst
= kmap_atomic(page
);
5061 memcpy(dst
, vaddr
+ i
*PAGE_SIZE
, PAGE_SIZE
);
5064 drm_clflush_pages(&page
, 1);
5066 set_page_dirty(page
);
5067 mark_page_accessed(page
);
5068 page_cache_release(page
);
5071 intel_gtt_chipset_flush();
5073 obj_priv
->phys_obj
->cur_obj
= NULL
;
5074 obj_priv
->phys_obj
= NULL
;
5078 i915_gem_attach_phys_object(struct drm_device
*dev
,
5079 struct drm_gem_object
*obj
,
5083 struct address_space
*mapping
= obj
->filp
->f_path
.dentry
->d_inode
->i_mapping
;
5084 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
5085 struct drm_i915_gem_object
*obj_priv
;
5090 if (id
> I915_MAX_PHYS_OBJECT
)
5093 obj_priv
= to_intel_bo(obj
);
5095 if (obj_priv
->phys_obj
) {
5096 if (obj_priv
->phys_obj
->id
== id
)
5098 i915_gem_detach_phys_object(dev
, obj
);
5101 /* create a new object */
5102 if (!dev_priv
->mm
.phys_objs
[id
- 1]) {
5103 ret
= i915_gem_init_phys_object(dev
, id
,
5106 DRM_ERROR("failed to init phys object %d size: %zu\n", id
, obj
->size
);
5111 /* bind to the object */
5112 obj_priv
->phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
5113 obj_priv
->phys_obj
->cur_obj
= obj
;
5115 page_count
= obj
->size
/ PAGE_SIZE
;
5117 for (i
= 0; i
< page_count
; i
++) {
5121 page
= read_cache_page_gfp(mapping
, i
,
5122 GFP_HIGHUSER
| __GFP_RECLAIMABLE
);
5124 return PTR_ERR(page
);
5126 src
= kmap_atomic(page
);
5127 dst
= obj_priv
->phys_obj
->handle
->vaddr
+ (i
* PAGE_SIZE
);
5128 memcpy(dst
, src
, PAGE_SIZE
);
5131 mark_page_accessed(page
);
5132 page_cache_release(page
);
5139 i915_gem_phys_pwrite(struct drm_device
*dev
, struct drm_gem_object
*obj
,
5140 struct drm_i915_gem_pwrite
*args
,
5141 struct drm_file
*file_priv
)
5143 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
5144 void *vaddr
= obj_priv
->phys_obj
->handle
->vaddr
+ args
->offset
;
5145 char __user
*user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
5147 DRM_DEBUG_DRIVER("vaddr %p, %lld\n", vaddr
, args
->size
);
5149 if (__copy_from_user_inatomic_nocache(vaddr
, user_data
, args
->size
)) {
5150 unsigned long unwritten
;
5152 /* The physical object once assigned is fixed for the lifetime
5153 * of the obj, so we can safely drop the lock and continue
5156 mutex_unlock(&dev
->struct_mutex
);
5157 unwritten
= copy_from_user(vaddr
, user_data
, args
->size
);
5158 mutex_lock(&dev
->struct_mutex
);
5163 intel_gtt_chipset_flush();
5167 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
)
5169 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
5171 /* Clean up our request list when the client is going away, so that
5172 * later retire_requests won't dereference our soon-to-be-gone
5175 spin_lock(&file_priv
->mm
.lock
);
5176 while (!list_empty(&file_priv
->mm
.request_list
)) {
5177 struct drm_i915_gem_request
*request
;
5179 request
= list_first_entry(&file_priv
->mm
.request_list
,
5180 struct drm_i915_gem_request
,
5182 list_del(&request
->client_list
);
5183 request
->file_priv
= NULL
;
5185 spin_unlock(&file_priv
->mm
.lock
);
5189 i915_gpu_is_active(struct drm_device
*dev
)
5191 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
5194 lists_empty
= list_empty(&dev_priv
->mm
.flushing_list
) &&
5195 list_empty(&dev_priv
->mm
.active_list
);
5197 return !lists_empty
;
5201 i915_gem_inactive_shrink(struct shrinker
*shrinker
,
5205 struct drm_i915_private
*dev_priv
=
5206 container_of(shrinker
,
5207 struct drm_i915_private
,
5208 mm
.inactive_shrinker
);
5209 struct drm_device
*dev
= dev_priv
->dev
;
5210 struct drm_i915_gem_object
*obj
, *next
;
5213 if (!mutex_trylock(&dev
->struct_mutex
))
5216 /* "fast-path" to count number of available objects */
5217 if (nr_to_scan
== 0) {
5219 list_for_each_entry(obj
,
5220 &dev_priv
->mm
.inactive_list
,
5223 mutex_unlock(&dev
->struct_mutex
);
5224 return cnt
/ 100 * sysctl_vfs_cache_pressure
;
5228 /* first scan for clean buffers */
5229 i915_gem_retire_requests(dev
);
5231 list_for_each_entry_safe(obj
, next
,
5232 &dev_priv
->mm
.inactive_list
,
5234 if (i915_gem_object_is_purgeable(obj
)) {
5235 i915_gem_object_unbind(&obj
->base
);
5236 if (--nr_to_scan
== 0)
5241 /* second pass, evict/count anything still on the inactive list */
5243 list_for_each_entry_safe(obj
, next
,
5244 &dev_priv
->mm
.inactive_list
,
5247 i915_gem_object_unbind(&obj
->base
);
5253 if (nr_to_scan
&& i915_gpu_is_active(dev
)) {
5255 * We are desperate for pages, so as a last resort, wait
5256 * for the GPU to finish and discard whatever we can.
5257 * This has a dramatic impact to reduce the number of
5258 * OOM-killer events whilst running the GPU aggressively.
5260 if (i915_gpu_idle(dev
) == 0)
5263 mutex_unlock(&dev
->struct_mutex
);
5264 return cnt
/ 100 * sysctl_vfs_cache_pressure
;