2 * Copyright © 2008-2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/drm_vma_manager.h>
30 #include <drm/i915_drm.h>
32 #include "i915_vgpu.h"
33 #include "i915_trace.h"
34 #include "intel_drv.h"
35 #include <linux/shmem_fs.h>
36 #include <linux/slab.h>
37 #include <linux/swap.h>
38 #include <linux/pci.h>
39 #include <linux/dma-buf.h>
41 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
);
42 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
);
43 static __must_check
int
44 i915_gem_object_wait_rendering(struct drm_i915_gem_object
*obj
,
47 i915_gem_object_retire(struct drm_i915_gem_object
*obj
);
49 static void i915_gem_write_fence(struct drm_device
*dev
, int reg
,
50 struct drm_i915_gem_object
*obj
);
51 static void i915_gem_object_update_fence(struct drm_i915_gem_object
*obj
,
52 struct drm_i915_fence_reg
*fence
,
55 static bool cpu_cache_is_coherent(struct drm_device
*dev
,
56 enum i915_cache_level level
)
58 return HAS_LLC(dev
) || level
!= I915_CACHE_NONE
;
61 static bool cpu_write_needs_clflush(struct drm_i915_gem_object
*obj
)
63 if (!cpu_cache_is_coherent(obj
->base
.dev
, obj
->cache_level
))
66 return obj
->pin_display
;
69 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object
*obj
)
72 i915_gem_release_mmap(obj
);
74 /* As we do not have an associated fence register, we will force
75 * a tiling change if we ever need to acquire one.
77 obj
->fence_dirty
= false;
78 obj
->fence_reg
= I915_FENCE_REG_NONE
;
81 /* some bookkeeping */
82 static void i915_gem_info_add_obj(struct drm_i915_private
*dev_priv
,
85 spin_lock(&dev_priv
->mm
.object_stat_lock
);
86 dev_priv
->mm
.object_count
++;
87 dev_priv
->mm
.object_memory
+= size
;
88 spin_unlock(&dev_priv
->mm
.object_stat_lock
);
91 static void i915_gem_info_remove_obj(struct drm_i915_private
*dev_priv
,
94 spin_lock(&dev_priv
->mm
.object_stat_lock
);
95 dev_priv
->mm
.object_count
--;
96 dev_priv
->mm
.object_memory
-= size
;
97 spin_unlock(&dev_priv
->mm
.object_stat_lock
);
101 i915_gem_wait_for_error(struct i915_gpu_error
*error
)
105 #define EXIT_COND (!i915_reset_in_progress(error) || \
106 i915_terminally_wedged(error))
111 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
112 * userspace. If it takes that long something really bad is going on and
113 * we should simply try to bail out and fail as gracefully as possible.
115 ret
= wait_event_interruptible_timeout(error
->reset_queue
,
119 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
121 } else if (ret
< 0) {
129 int i915_mutex_lock_interruptible(struct drm_device
*dev
)
131 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
134 ret
= i915_gem_wait_for_error(&dev_priv
->gpu_error
);
138 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
142 WARN_ON(i915_verify_lists(dev
));
147 i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
148 struct drm_file
*file
)
150 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
151 struct drm_i915_gem_get_aperture
*args
= data
;
152 struct drm_i915_gem_object
*obj
;
156 mutex_lock(&dev
->struct_mutex
);
157 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
)
158 if (i915_gem_obj_is_pinned(obj
))
159 pinned
+= i915_gem_obj_ggtt_size(obj
);
160 mutex_unlock(&dev
->struct_mutex
);
162 args
->aper_size
= dev_priv
->gtt
.base
.total
;
163 args
->aper_available_size
= args
->aper_size
- pinned
;
169 i915_gem_object_get_pages_phys(struct drm_i915_gem_object
*obj
)
171 struct address_space
*mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
172 char *vaddr
= obj
->phys_handle
->vaddr
;
174 struct scatterlist
*sg
;
177 if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj
)))
180 for (i
= 0; i
< obj
->base
.size
/ PAGE_SIZE
; i
++) {
184 page
= shmem_read_mapping_page(mapping
, i
);
186 return PTR_ERR(page
);
188 src
= kmap_atomic(page
);
189 memcpy(vaddr
, src
, PAGE_SIZE
);
190 drm_clflush_virt_range(vaddr
, PAGE_SIZE
);
193 page_cache_release(page
);
197 i915_gem_chipset_flush(obj
->base
.dev
);
199 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
203 if (sg_alloc_table(st
, 1, GFP_KERNEL
)) {
210 sg
->length
= obj
->base
.size
;
212 sg_dma_address(sg
) = obj
->phys_handle
->busaddr
;
213 sg_dma_len(sg
) = obj
->base
.size
;
216 obj
->has_dma_mapping
= true;
221 i915_gem_object_put_pages_phys(struct drm_i915_gem_object
*obj
)
225 BUG_ON(obj
->madv
== __I915_MADV_PURGED
);
227 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
229 /* In the event of a disaster, abandon all caches and
232 WARN_ON(ret
!= -EIO
);
233 obj
->base
.read_domains
= obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
236 if (obj
->madv
== I915_MADV_DONTNEED
)
240 struct address_space
*mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
241 char *vaddr
= obj
->phys_handle
->vaddr
;
244 for (i
= 0; i
< obj
->base
.size
/ PAGE_SIZE
; i
++) {
248 page
= shmem_read_mapping_page(mapping
, i
);
252 dst
= kmap_atomic(page
);
253 drm_clflush_virt_range(vaddr
, PAGE_SIZE
);
254 memcpy(dst
, vaddr
, PAGE_SIZE
);
257 set_page_dirty(page
);
258 if (obj
->madv
== I915_MADV_WILLNEED
)
259 mark_page_accessed(page
);
260 page_cache_release(page
);
266 sg_free_table(obj
->pages
);
269 obj
->has_dma_mapping
= false;
273 i915_gem_object_release_phys(struct drm_i915_gem_object
*obj
)
275 drm_pci_free(obj
->base
.dev
, obj
->phys_handle
);
278 static const struct drm_i915_gem_object_ops i915_gem_phys_ops
= {
279 .get_pages
= i915_gem_object_get_pages_phys
,
280 .put_pages
= i915_gem_object_put_pages_phys
,
281 .release
= i915_gem_object_release_phys
,
285 drop_pages(struct drm_i915_gem_object
*obj
)
287 struct i915_vma
*vma
, *next
;
290 drm_gem_object_reference(&obj
->base
);
291 list_for_each_entry_safe(vma
, next
, &obj
->vma_list
, vma_link
)
292 if (i915_vma_unbind(vma
))
295 ret
= i915_gem_object_put_pages(obj
);
296 drm_gem_object_unreference(&obj
->base
);
302 i915_gem_object_attach_phys(struct drm_i915_gem_object
*obj
,
305 drm_dma_handle_t
*phys
;
308 if (obj
->phys_handle
) {
309 if ((unsigned long)obj
->phys_handle
->vaddr
& (align
-1))
315 if (obj
->madv
!= I915_MADV_WILLNEED
)
318 if (obj
->base
.filp
== NULL
)
321 ret
= drop_pages(obj
);
325 /* create a new object */
326 phys
= drm_pci_alloc(obj
->base
.dev
, obj
->base
.size
, align
);
330 obj
->phys_handle
= phys
;
331 obj
->ops
= &i915_gem_phys_ops
;
333 return i915_gem_object_get_pages(obj
);
337 i915_gem_phys_pwrite(struct drm_i915_gem_object
*obj
,
338 struct drm_i915_gem_pwrite
*args
,
339 struct drm_file
*file_priv
)
341 struct drm_device
*dev
= obj
->base
.dev
;
342 void *vaddr
= obj
->phys_handle
->vaddr
+ args
->offset
;
343 char __user
*user_data
= to_user_ptr(args
->data_ptr
);
346 /* We manually control the domain here and pretend that it
347 * remains coherent i.e. in the GTT domain, like shmem_pwrite.
349 ret
= i915_gem_object_wait_rendering(obj
, false);
353 intel_fb_obj_invalidate(obj
, NULL
, ORIGIN_CPU
);
354 if (__copy_from_user_inatomic_nocache(vaddr
, user_data
, args
->size
)) {
355 unsigned long unwritten
;
357 /* The physical object once assigned is fixed for the lifetime
358 * of the obj, so we can safely drop the lock and continue
361 mutex_unlock(&dev
->struct_mutex
);
362 unwritten
= copy_from_user(vaddr
, user_data
, args
->size
);
363 mutex_lock(&dev
->struct_mutex
);
370 drm_clflush_virt_range(vaddr
, args
->size
);
371 i915_gem_chipset_flush(dev
);
374 intel_fb_obj_flush(obj
, false);
378 void *i915_gem_object_alloc(struct drm_device
*dev
)
380 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
381 return kmem_cache_zalloc(dev_priv
->objects
, GFP_KERNEL
);
384 void i915_gem_object_free(struct drm_i915_gem_object
*obj
)
386 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
387 kmem_cache_free(dev_priv
->objects
, obj
);
391 i915_gem_create(struct drm_file
*file
,
392 struct drm_device
*dev
,
396 struct drm_i915_gem_object
*obj
;
400 size
= roundup(size
, PAGE_SIZE
);
404 /* Allocate the new object */
405 obj
= i915_gem_alloc_object(dev
, size
);
409 ret
= drm_gem_handle_create(file
, &obj
->base
, &handle
);
410 /* drop reference from allocate - handle holds it now */
411 drm_gem_object_unreference_unlocked(&obj
->base
);
420 i915_gem_dumb_create(struct drm_file
*file
,
421 struct drm_device
*dev
,
422 struct drm_mode_create_dumb
*args
)
424 /* have to work out size/pitch and return them */
425 args
->pitch
= ALIGN(args
->width
* DIV_ROUND_UP(args
->bpp
, 8), 64);
426 args
->size
= args
->pitch
* args
->height
;
427 return i915_gem_create(file
, dev
,
428 args
->size
, &args
->handle
);
432 * Creates a new mm object and returns a handle to it.
435 i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
436 struct drm_file
*file
)
438 struct drm_i915_gem_create
*args
= data
;
440 return i915_gem_create(file
, dev
,
441 args
->size
, &args
->handle
);
445 __copy_to_user_swizzled(char __user
*cpu_vaddr
,
446 const char *gpu_vaddr
, int gpu_offset
,
449 int ret
, cpu_offset
= 0;
452 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
453 int this_length
= min(cacheline_end
- gpu_offset
, length
);
454 int swizzled_gpu_offset
= gpu_offset
^ 64;
456 ret
= __copy_to_user(cpu_vaddr
+ cpu_offset
,
457 gpu_vaddr
+ swizzled_gpu_offset
,
462 cpu_offset
+= this_length
;
463 gpu_offset
+= this_length
;
464 length
-= this_length
;
471 __copy_from_user_swizzled(char *gpu_vaddr
, int gpu_offset
,
472 const char __user
*cpu_vaddr
,
475 int ret
, cpu_offset
= 0;
478 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
479 int this_length
= min(cacheline_end
- gpu_offset
, length
);
480 int swizzled_gpu_offset
= gpu_offset
^ 64;
482 ret
= __copy_from_user(gpu_vaddr
+ swizzled_gpu_offset
,
483 cpu_vaddr
+ cpu_offset
,
488 cpu_offset
+= this_length
;
489 gpu_offset
+= this_length
;
490 length
-= this_length
;
497 * Pins the specified object's pages and synchronizes the object with
498 * GPU accesses. Sets needs_clflush to non-zero if the caller should
499 * flush the object from the CPU cache.
501 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object
*obj
,
511 if (!(obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
)) {
512 /* If we're not in the cpu read domain, set ourself into the gtt
513 * read domain and manually flush cachelines (if required). This
514 * optimizes for the case when the gpu will dirty the data
515 * anyway again before the next pread happens. */
516 *needs_clflush
= !cpu_cache_is_coherent(obj
->base
.dev
,
518 ret
= i915_gem_object_wait_rendering(obj
, true);
522 i915_gem_object_retire(obj
);
525 ret
= i915_gem_object_get_pages(obj
);
529 i915_gem_object_pin_pages(obj
);
534 /* Per-page copy function for the shmem pread fastpath.
535 * Flushes invalid cachelines before reading the target if
536 * needs_clflush is set. */
538 shmem_pread_fast(struct page
*page
, int shmem_page_offset
, int page_length
,
539 char __user
*user_data
,
540 bool page_do_bit17_swizzling
, bool needs_clflush
)
545 if (unlikely(page_do_bit17_swizzling
))
548 vaddr
= kmap_atomic(page
);
550 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
552 ret
= __copy_to_user_inatomic(user_data
,
553 vaddr
+ shmem_page_offset
,
555 kunmap_atomic(vaddr
);
557 return ret
? -EFAULT
: 0;
561 shmem_clflush_swizzled_range(char *addr
, unsigned long length
,
564 if (unlikely(swizzled
)) {
565 unsigned long start
= (unsigned long) addr
;
566 unsigned long end
= (unsigned long) addr
+ length
;
568 /* For swizzling simply ensure that we always flush both
569 * channels. Lame, but simple and it works. Swizzled
570 * pwrite/pread is far from a hotpath - current userspace
571 * doesn't use it at all. */
572 start
= round_down(start
, 128);
573 end
= round_up(end
, 128);
575 drm_clflush_virt_range((void *)start
, end
- start
);
577 drm_clflush_virt_range(addr
, length
);
582 /* Only difference to the fast-path function is that this can handle bit17
583 * and uses non-atomic copy and kmap functions. */
585 shmem_pread_slow(struct page
*page
, int shmem_page_offset
, int page_length
,
586 char __user
*user_data
,
587 bool page_do_bit17_swizzling
, bool needs_clflush
)
594 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
596 page_do_bit17_swizzling
);
598 if (page_do_bit17_swizzling
)
599 ret
= __copy_to_user_swizzled(user_data
,
600 vaddr
, shmem_page_offset
,
603 ret
= __copy_to_user(user_data
,
604 vaddr
+ shmem_page_offset
,
608 return ret
? - EFAULT
: 0;
612 i915_gem_shmem_pread(struct drm_device
*dev
,
613 struct drm_i915_gem_object
*obj
,
614 struct drm_i915_gem_pread
*args
,
615 struct drm_file
*file
)
617 char __user
*user_data
;
620 int shmem_page_offset
, page_length
, ret
= 0;
621 int obj_do_bit17_swizzling
, page_do_bit17_swizzling
;
623 int needs_clflush
= 0;
624 struct sg_page_iter sg_iter
;
626 user_data
= to_user_ptr(args
->data_ptr
);
629 obj_do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
631 ret
= i915_gem_obj_prepare_shmem_read(obj
, &needs_clflush
);
635 offset
= args
->offset
;
637 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
,
638 offset
>> PAGE_SHIFT
) {
639 struct page
*page
= sg_page_iter_page(&sg_iter
);
644 /* Operation in this page
646 * shmem_page_offset = offset within page in shmem file
647 * page_length = bytes to copy for this page
649 shmem_page_offset
= offset_in_page(offset
);
650 page_length
= remain
;
651 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
652 page_length
= PAGE_SIZE
- shmem_page_offset
;
654 page_do_bit17_swizzling
= obj_do_bit17_swizzling
&&
655 (page_to_phys(page
) & (1 << 17)) != 0;
657 ret
= shmem_pread_fast(page
, shmem_page_offset
, page_length
,
658 user_data
, page_do_bit17_swizzling
,
663 mutex_unlock(&dev
->struct_mutex
);
665 if (likely(!i915
.prefault_disable
) && !prefaulted
) {
666 ret
= fault_in_multipages_writeable(user_data
, remain
);
667 /* Userspace is tricking us, but we've already clobbered
668 * its pages with the prefault and promised to write the
669 * data up to the first fault. Hence ignore any errors
670 * and just continue. */
675 ret
= shmem_pread_slow(page
, shmem_page_offset
, page_length
,
676 user_data
, page_do_bit17_swizzling
,
679 mutex_lock(&dev
->struct_mutex
);
685 remain
-= page_length
;
686 user_data
+= page_length
;
687 offset
+= page_length
;
691 i915_gem_object_unpin_pages(obj
);
697 * Reads data from the object referenced by handle.
699 * On error, the contents of *data are undefined.
702 i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
703 struct drm_file
*file
)
705 struct drm_i915_gem_pread
*args
= data
;
706 struct drm_i915_gem_object
*obj
;
712 if (!access_ok(VERIFY_WRITE
,
713 to_user_ptr(args
->data_ptr
),
717 ret
= i915_mutex_lock_interruptible(dev
);
721 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
722 if (&obj
->base
== NULL
) {
727 /* Bounds check source. */
728 if (args
->offset
> obj
->base
.size
||
729 args
->size
> obj
->base
.size
- args
->offset
) {
734 /* prime objects have no backing filp to GEM pread/pwrite
737 if (!obj
->base
.filp
) {
742 trace_i915_gem_object_pread(obj
, args
->offset
, args
->size
);
744 ret
= i915_gem_shmem_pread(dev
, obj
, args
, file
);
747 drm_gem_object_unreference(&obj
->base
);
749 mutex_unlock(&dev
->struct_mutex
);
753 /* This is the fast write path which cannot handle
754 * page faults in the source data
758 fast_user_write(struct io_mapping
*mapping
,
759 loff_t page_base
, int page_offset
,
760 char __user
*user_data
,
763 void __iomem
*vaddr_atomic
;
765 unsigned long unwritten
;
767 vaddr_atomic
= io_mapping_map_atomic_wc(mapping
, page_base
);
768 /* We can use the cpu mem copy function because this is X86. */
769 vaddr
= (void __force
*)vaddr_atomic
+ page_offset
;
770 unwritten
= __copy_from_user_inatomic_nocache(vaddr
,
772 io_mapping_unmap_atomic(vaddr_atomic
);
777 * This is the fast pwrite path, where we copy the data directly from the
778 * user into the GTT, uncached.
781 i915_gem_gtt_pwrite_fast(struct drm_device
*dev
,
782 struct drm_i915_gem_object
*obj
,
783 struct drm_i915_gem_pwrite
*args
,
784 struct drm_file
*file
)
786 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
788 loff_t offset
, page_base
;
789 char __user
*user_data
;
790 int page_offset
, page_length
, ret
;
792 ret
= i915_gem_obj_ggtt_pin(obj
, 0, PIN_MAPPABLE
| PIN_NONBLOCK
);
796 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
800 ret
= i915_gem_object_put_fence(obj
);
804 user_data
= to_user_ptr(args
->data_ptr
);
807 offset
= i915_gem_obj_ggtt_offset(obj
) + args
->offset
;
809 intel_fb_obj_invalidate(obj
, NULL
, ORIGIN_GTT
);
812 /* Operation in this page
814 * page_base = page offset within aperture
815 * page_offset = offset within page
816 * page_length = bytes to copy for this page
818 page_base
= offset
& PAGE_MASK
;
819 page_offset
= offset_in_page(offset
);
820 page_length
= remain
;
821 if ((page_offset
+ remain
) > PAGE_SIZE
)
822 page_length
= PAGE_SIZE
- page_offset
;
824 /* If we get a fault while copying data, then (presumably) our
825 * source page isn't available. Return the error and we'll
826 * retry in the slow path.
828 if (fast_user_write(dev_priv
->gtt
.mappable
, page_base
,
829 page_offset
, user_data
, page_length
)) {
834 remain
-= page_length
;
835 user_data
+= page_length
;
836 offset
+= page_length
;
840 intel_fb_obj_flush(obj
, false);
842 i915_gem_object_ggtt_unpin(obj
);
847 /* Per-page copy function for the shmem pwrite fastpath.
848 * Flushes invalid cachelines before writing to the target if
849 * needs_clflush_before is set and flushes out any written cachelines after
850 * writing if needs_clflush is set. */
852 shmem_pwrite_fast(struct page
*page
, int shmem_page_offset
, int page_length
,
853 char __user
*user_data
,
854 bool page_do_bit17_swizzling
,
855 bool needs_clflush_before
,
856 bool needs_clflush_after
)
861 if (unlikely(page_do_bit17_swizzling
))
864 vaddr
= kmap_atomic(page
);
865 if (needs_clflush_before
)
866 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
868 ret
= __copy_from_user_inatomic(vaddr
+ shmem_page_offset
,
869 user_data
, page_length
);
870 if (needs_clflush_after
)
871 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
873 kunmap_atomic(vaddr
);
875 return ret
? -EFAULT
: 0;
878 /* Only difference to the fast-path function is that this can handle bit17
879 * and uses non-atomic copy and kmap functions. */
881 shmem_pwrite_slow(struct page
*page
, int shmem_page_offset
, int page_length
,
882 char __user
*user_data
,
883 bool page_do_bit17_swizzling
,
884 bool needs_clflush_before
,
885 bool needs_clflush_after
)
891 if (unlikely(needs_clflush_before
|| page_do_bit17_swizzling
))
892 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
894 page_do_bit17_swizzling
);
895 if (page_do_bit17_swizzling
)
896 ret
= __copy_from_user_swizzled(vaddr
, shmem_page_offset
,
900 ret
= __copy_from_user(vaddr
+ shmem_page_offset
,
903 if (needs_clflush_after
)
904 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
906 page_do_bit17_swizzling
);
909 return ret
? -EFAULT
: 0;
913 i915_gem_shmem_pwrite(struct drm_device
*dev
,
914 struct drm_i915_gem_object
*obj
,
915 struct drm_i915_gem_pwrite
*args
,
916 struct drm_file
*file
)
920 char __user
*user_data
;
921 int shmem_page_offset
, page_length
, ret
= 0;
922 int obj_do_bit17_swizzling
, page_do_bit17_swizzling
;
923 int hit_slowpath
= 0;
924 int needs_clflush_after
= 0;
925 int needs_clflush_before
= 0;
926 struct sg_page_iter sg_iter
;
928 user_data
= to_user_ptr(args
->data_ptr
);
931 obj_do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
933 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
934 /* If we're not in the cpu write domain, set ourself into the gtt
935 * write domain and manually flush cachelines (if required). This
936 * optimizes for the case when the gpu will use the data
937 * right away and we therefore have to clflush anyway. */
938 needs_clflush_after
= cpu_write_needs_clflush(obj
);
939 ret
= i915_gem_object_wait_rendering(obj
, false);
943 i915_gem_object_retire(obj
);
945 /* Same trick applies to invalidate partially written cachelines read
947 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) == 0)
948 needs_clflush_before
=
949 !cpu_cache_is_coherent(dev
, obj
->cache_level
);
951 ret
= i915_gem_object_get_pages(obj
);
955 intel_fb_obj_invalidate(obj
, NULL
, ORIGIN_CPU
);
957 i915_gem_object_pin_pages(obj
);
959 offset
= args
->offset
;
962 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
,
963 offset
>> PAGE_SHIFT
) {
964 struct page
*page
= sg_page_iter_page(&sg_iter
);
965 int partial_cacheline_write
;
970 /* Operation in this page
972 * shmem_page_offset = offset within page in shmem file
973 * page_length = bytes to copy for this page
975 shmem_page_offset
= offset_in_page(offset
);
977 page_length
= remain
;
978 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
979 page_length
= PAGE_SIZE
- shmem_page_offset
;
981 /* If we don't overwrite a cacheline completely we need to be
982 * careful to have up-to-date data by first clflushing. Don't
983 * overcomplicate things and flush the entire patch. */
984 partial_cacheline_write
= needs_clflush_before
&&
985 ((shmem_page_offset
| page_length
)
986 & (boot_cpu_data
.x86_clflush_size
- 1));
988 page_do_bit17_swizzling
= obj_do_bit17_swizzling
&&
989 (page_to_phys(page
) & (1 << 17)) != 0;
991 ret
= shmem_pwrite_fast(page
, shmem_page_offset
, page_length
,
992 user_data
, page_do_bit17_swizzling
,
993 partial_cacheline_write
,
994 needs_clflush_after
);
999 mutex_unlock(&dev
->struct_mutex
);
1000 ret
= shmem_pwrite_slow(page
, shmem_page_offset
, page_length
,
1001 user_data
, page_do_bit17_swizzling
,
1002 partial_cacheline_write
,
1003 needs_clflush_after
);
1005 mutex_lock(&dev
->struct_mutex
);
1011 remain
-= page_length
;
1012 user_data
+= page_length
;
1013 offset
+= page_length
;
1017 i915_gem_object_unpin_pages(obj
);
1021 * Fixup: Flush cpu caches in case we didn't flush the dirty
1022 * cachelines in-line while writing and the object moved
1023 * out of the cpu write domain while we've dropped the lock.
1025 if (!needs_clflush_after
&&
1026 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
1027 if (i915_gem_clflush_object(obj
, obj
->pin_display
))
1028 i915_gem_chipset_flush(dev
);
1032 if (needs_clflush_after
)
1033 i915_gem_chipset_flush(dev
);
1035 intel_fb_obj_flush(obj
, false);
1040 * Writes data to the object referenced by handle.
1042 * On error, the contents of the buffer that were to be modified are undefined.
1045 i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
1046 struct drm_file
*file
)
1048 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1049 struct drm_i915_gem_pwrite
*args
= data
;
1050 struct drm_i915_gem_object
*obj
;
1053 if (args
->size
== 0)
1056 if (!access_ok(VERIFY_READ
,
1057 to_user_ptr(args
->data_ptr
),
1061 if (likely(!i915
.prefault_disable
)) {
1062 ret
= fault_in_multipages_readable(to_user_ptr(args
->data_ptr
),
1068 intel_runtime_pm_get(dev_priv
);
1070 ret
= i915_mutex_lock_interruptible(dev
);
1074 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1075 if (&obj
->base
== NULL
) {
1080 /* Bounds check destination. */
1081 if (args
->offset
> obj
->base
.size
||
1082 args
->size
> obj
->base
.size
- args
->offset
) {
1087 /* prime objects have no backing filp to GEM pread/pwrite
1090 if (!obj
->base
.filp
) {
1095 trace_i915_gem_object_pwrite(obj
, args
->offset
, args
->size
);
1098 /* We can only do the GTT pwrite on untiled buffers, as otherwise
1099 * it would end up going through the fenced access, and we'll get
1100 * different detiling behavior between reading and writing.
1101 * pread/pwrite currently are reading and writing from the CPU
1102 * perspective, requiring manual detiling by the client.
1104 if (obj
->tiling_mode
== I915_TILING_NONE
&&
1105 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
&&
1106 cpu_write_needs_clflush(obj
)) {
1107 ret
= i915_gem_gtt_pwrite_fast(dev
, obj
, args
, file
);
1108 /* Note that the gtt paths might fail with non-page-backed user
1109 * pointers (e.g. gtt mappings when moving data between
1110 * textures). Fallback to the shmem path in that case. */
1113 if (ret
== -EFAULT
|| ret
== -ENOSPC
) {
1114 if (obj
->phys_handle
)
1115 ret
= i915_gem_phys_pwrite(obj
, args
, file
);
1117 ret
= i915_gem_shmem_pwrite(dev
, obj
, args
, file
);
1121 drm_gem_object_unreference(&obj
->base
);
1123 mutex_unlock(&dev
->struct_mutex
);
1125 intel_runtime_pm_put(dev_priv
);
1131 i915_gem_check_wedge(struct i915_gpu_error
*error
,
1134 if (i915_reset_in_progress(error
)) {
1135 /* Non-interruptible callers can't handle -EAGAIN, hence return
1136 * -EIO unconditionally for these. */
1140 /* Recovery complete, but the reset failed ... */
1141 if (i915_terminally_wedged(error
))
1145 * Check if GPU Reset is in progress - we need intel_ring_begin
1146 * to work properly to reinit the hw state while the gpu is
1147 * still marked as reset-in-progress. Handle this with a flag.
1149 if (!error
->reload_in_reset
)
1157 * Compare arbitrary request against outstanding lazy request. Emit on match.
1160 i915_gem_check_olr(struct drm_i915_gem_request
*req
)
1164 WARN_ON(!mutex_is_locked(&req
->ring
->dev
->struct_mutex
));
1167 if (req
== req
->ring
->outstanding_lazy_request
)
1168 ret
= i915_add_request(req
->ring
);
1173 static void fake_irq(unsigned long data
)
1175 wake_up_process((struct task_struct
*)data
);
1178 static bool missed_irq(struct drm_i915_private
*dev_priv
,
1179 struct intel_engine_cs
*ring
)
1181 return test_bit(ring
->id
, &dev_priv
->gpu_error
.missed_irq_rings
);
1185 * __i915_wait_request - wait until execution of request has finished
1187 * @reset_counter: reset sequence associated with the given request
1188 * @interruptible: do an interruptible wait (normally yes)
1189 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
1191 * Note: It is of utmost importance that the passed in seqno and reset_counter
1192 * values have been read by the caller in an smp safe manner. Where read-side
1193 * locks are involved, it is sufficient to read the reset_counter before
1194 * unlocking the lock that protects the seqno. For lockless tricks, the
1195 * reset_counter _must_ be read before, and an appropriate smp_rmb must be
1198 * Returns 0 if the request was found within the alloted time. Else returns the
1199 * errno with remaining time filled in timeout argument.
1201 int __i915_wait_request(struct drm_i915_gem_request
*req
,
1202 unsigned reset_counter
,
1205 struct drm_i915_file_private
*file_priv
)
1207 struct intel_engine_cs
*ring
= i915_gem_request_get_ring(req
);
1208 struct drm_device
*dev
= ring
->dev
;
1209 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1210 const bool irq_test_in_progress
=
1211 ACCESS_ONCE(dev_priv
->gpu_error
.test_irq_rings
) & intel_ring_flag(ring
);
1213 unsigned long timeout_expire
;
1217 WARN(!intel_irqs_enabled(dev_priv
), "IRQs disabled");
1219 if (i915_gem_request_completed(req
, true))
1222 timeout_expire
= timeout
?
1223 jiffies
+ nsecs_to_jiffies_timeout((u64
)*timeout
) : 0;
1225 if (INTEL_INFO(dev
)->gen
>= 6)
1226 gen6_rps_boost(dev_priv
, file_priv
);
1228 if (!irq_test_in_progress
&& WARN_ON(!ring
->irq_get(ring
)))
1231 /* Record current time in case interrupted by signal, or wedged */
1232 trace_i915_gem_request_wait_begin(req
);
1233 before
= ktime_get_raw_ns();
1235 struct timer_list timer
;
1237 prepare_to_wait(&ring
->irq_queue
, &wait
,
1238 interruptible
? TASK_INTERRUPTIBLE
: TASK_UNINTERRUPTIBLE
);
1240 /* We need to check whether any gpu reset happened in between
1241 * the caller grabbing the seqno and now ... */
1242 if (reset_counter
!= atomic_read(&dev_priv
->gpu_error
.reset_counter
)) {
1243 /* ... but upgrade the -EAGAIN to an -EIO if the gpu
1244 * is truely gone. */
1245 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, interruptible
);
1251 if (i915_gem_request_completed(req
, false)) {
1256 if (interruptible
&& signal_pending(current
)) {
1261 if (timeout
&& time_after_eq(jiffies
, timeout_expire
)) {
1266 timer
.function
= NULL
;
1267 if (timeout
|| missed_irq(dev_priv
, ring
)) {
1268 unsigned long expire
;
1270 setup_timer_on_stack(&timer
, fake_irq
, (unsigned long)current
);
1271 expire
= missed_irq(dev_priv
, ring
) ? jiffies
+ 1 : timeout_expire
;
1272 mod_timer(&timer
, expire
);
1277 if (timer
.function
) {
1278 del_singleshot_timer_sync(&timer
);
1279 destroy_timer_on_stack(&timer
);
1282 now
= ktime_get_raw_ns();
1283 trace_i915_gem_request_wait_end(req
);
1285 if (!irq_test_in_progress
)
1286 ring
->irq_put(ring
);
1288 finish_wait(&ring
->irq_queue
, &wait
);
1291 s64 tres
= *timeout
- (now
- before
);
1293 *timeout
= tres
< 0 ? 0 : tres
;
1296 * Apparently ktime isn't accurate enough and occasionally has a
1297 * bit of mismatch in the jiffies<->nsecs<->ktime loop. So patch
1298 * things up to make the test happy. We allow up to 1 jiffy.
1300 * This is a regrssion from the timespec->ktime conversion.
1302 if (ret
== -ETIME
&& *timeout
< jiffies_to_usecs(1)*1000)
1310 * Waits for a request to be signaled, and cleans up the
1311 * request and object lists appropriately for that event.
1314 i915_wait_request(struct drm_i915_gem_request
*req
)
1316 struct drm_device
*dev
;
1317 struct drm_i915_private
*dev_priv
;
1319 unsigned reset_counter
;
1322 BUG_ON(req
== NULL
);
1324 dev
= req
->ring
->dev
;
1325 dev_priv
= dev
->dev_private
;
1326 interruptible
= dev_priv
->mm
.interruptible
;
1328 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
1330 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, interruptible
);
1334 ret
= i915_gem_check_olr(req
);
1338 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
1339 i915_gem_request_reference(req
);
1340 ret
= __i915_wait_request(req
, reset_counter
,
1341 interruptible
, NULL
, NULL
);
1342 i915_gem_request_unreference(req
);
1347 i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object
*obj
)
1352 /* Manually manage the write flush as we may have not yet
1353 * retired the buffer.
1355 * Note that the last_write_req is always the earlier of
1356 * the two (read/write) requests, so if we haved successfully waited,
1357 * we know we have passed the last write.
1359 i915_gem_request_assign(&obj
->last_write_req
, NULL
);
1365 * Ensures that all rendering to the object has completed and the object is
1366 * safe to unbind from the GTT or access from the CPU.
1368 static __must_check
int
1369 i915_gem_object_wait_rendering(struct drm_i915_gem_object
*obj
,
1372 struct drm_i915_gem_request
*req
;
1375 req
= readonly
? obj
->last_write_req
: obj
->last_read_req
;
1379 ret
= i915_wait_request(req
);
1383 return i915_gem_object_wait_rendering__tail(obj
);
1386 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1387 * as the object state may change during this call.
1389 static __must_check
int
1390 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object
*obj
,
1391 struct drm_i915_file_private
*file_priv
,
1394 struct drm_i915_gem_request
*req
;
1395 struct drm_device
*dev
= obj
->base
.dev
;
1396 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1397 unsigned reset_counter
;
1400 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
1401 BUG_ON(!dev_priv
->mm
.interruptible
);
1403 req
= readonly
? obj
->last_write_req
: obj
->last_read_req
;
1407 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, true);
1411 ret
= i915_gem_check_olr(req
);
1415 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
1416 i915_gem_request_reference(req
);
1417 mutex_unlock(&dev
->struct_mutex
);
1418 ret
= __i915_wait_request(req
, reset_counter
, true, NULL
, file_priv
);
1419 mutex_lock(&dev
->struct_mutex
);
1420 i915_gem_request_unreference(req
);
1424 return i915_gem_object_wait_rendering__tail(obj
);
1428 * Called when user space prepares to use an object with the CPU, either
1429 * through the mmap ioctl's mapping or a GTT mapping.
1432 i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
1433 struct drm_file
*file
)
1435 struct drm_i915_gem_set_domain
*args
= data
;
1436 struct drm_i915_gem_object
*obj
;
1437 uint32_t read_domains
= args
->read_domains
;
1438 uint32_t write_domain
= args
->write_domain
;
1441 /* Only handle setting domains to types used by the CPU. */
1442 if (write_domain
& I915_GEM_GPU_DOMAINS
)
1445 if (read_domains
& I915_GEM_GPU_DOMAINS
)
1448 /* Having something in the write domain implies it's in the read
1449 * domain, and only that read domain. Enforce that in the request.
1451 if (write_domain
!= 0 && read_domains
!= write_domain
)
1454 ret
= i915_mutex_lock_interruptible(dev
);
1458 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1459 if (&obj
->base
== NULL
) {
1464 /* Try to flush the object off the GPU without holding the lock.
1465 * We will repeat the flush holding the lock in the normal manner
1466 * to catch cases where we are gazumped.
1468 ret
= i915_gem_object_wait_rendering__nonblocking(obj
,
1474 if (read_domains
& I915_GEM_DOMAIN_GTT
)
1475 ret
= i915_gem_object_set_to_gtt_domain(obj
, write_domain
!= 0);
1477 ret
= i915_gem_object_set_to_cpu_domain(obj
, write_domain
!= 0);
1480 drm_gem_object_unreference(&obj
->base
);
1482 mutex_unlock(&dev
->struct_mutex
);
1487 * Called when user space has done writes to this buffer
1490 i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1491 struct drm_file
*file
)
1493 struct drm_i915_gem_sw_finish
*args
= data
;
1494 struct drm_i915_gem_object
*obj
;
1497 ret
= i915_mutex_lock_interruptible(dev
);
1501 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1502 if (&obj
->base
== NULL
) {
1507 /* Pinned buffers may be scanout, so flush the cache */
1508 if (obj
->pin_display
)
1509 i915_gem_object_flush_cpu_write_domain(obj
);
1511 drm_gem_object_unreference(&obj
->base
);
1513 mutex_unlock(&dev
->struct_mutex
);
1518 * Maps the contents of an object, returning the address it is mapped
1521 * While the mapping holds a reference on the contents of the object, it doesn't
1522 * imply a ref on the object itself.
1526 * DRM driver writers who look a this function as an example for how to do GEM
1527 * mmap support, please don't implement mmap support like here. The modern way
1528 * to implement DRM mmap support is with an mmap offset ioctl (like
1529 * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly.
1530 * That way debug tooling like valgrind will understand what's going on, hiding
1531 * the mmap call in a driver private ioctl will break that. The i915 driver only
1532 * does cpu mmaps this way because we didn't know better.
1535 i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1536 struct drm_file
*file
)
1538 struct drm_i915_gem_mmap
*args
= data
;
1539 struct drm_gem_object
*obj
;
1542 if (args
->flags
& ~(I915_MMAP_WC
))
1545 if (args
->flags
& I915_MMAP_WC
&& !cpu_has_pat
)
1548 obj
= drm_gem_object_lookup(dev
, file
, args
->handle
);
1552 /* prime objects have no backing filp to GEM mmap
1556 drm_gem_object_unreference_unlocked(obj
);
1560 addr
= vm_mmap(obj
->filp
, 0, args
->size
,
1561 PROT_READ
| PROT_WRITE
, MAP_SHARED
,
1563 if (args
->flags
& I915_MMAP_WC
) {
1564 struct mm_struct
*mm
= current
->mm
;
1565 struct vm_area_struct
*vma
;
1567 down_write(&mm
->mmap_sem
);
1568 vma
= find_vma(mm
, addr
);
1571 pgprot_writecombine(vm_get_page_prot(vma
->vm_flags
));
1574 up_write(&mm
->mmap_sem
);
1576 drm_gem_object_unreference_unlocked(obj
);
1577 if (IS_ERR((void *)addr
))
1580 args
->addr_ptr
= (uint64_t) addr
;
1586 * i915_gem_fault - fault a page into the GTT
1587 * vma: VMA in question
1590 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1591 * from userspace. The fault handler takes care of binding the object to
1592 * the GTT (if needed), allocating and programming a fence register (again,
1593 * only if needed based on whether the old reg is still valid or the object
1594 * is tiled) and inserting a new PTE into the faulting process.
1596 * Note that the faulting process may involve evicting existing objects
1597 * from the GTT and/or fence registers to make room. So performance may
1598 * suffer if the GTT working set is large or there are few fence registers
1601 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
)
1603 struct drm_i915_gem_object
*obj
= to_intel_bo(vma
->vm_private_data
);
1604 struct drm_device
*dev
= obj
->base
.dev
;
1605 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1606 pgoff_t page_offset
;
1609 bool write
= !!(vmf
->flags
& FAULT_FLAG_WRITE
);
1611 intel_runtime_pm_get(dev_priv
);
1613 /* We don't use vmf->pgoff since that has the fake offset */
1614 page_offset
= ((unsigned long)vmf
->virtual_address
- vma
->vm_start
) >>
1617 ret
= i915_mutex_lock_interruptible(dev
);
1621 trace_i915_gem_object_fault(obj
, page_offset
, true, write
);
1623 /* Try to flush the object off the GPU first without holding the lock.
1624 * Upon reacquiring the lock, we will perform our sanity checks and then
1625 * repeat the flush holding the lock in the normal manner to catch cases
1626 * where we are gazumped.
1628 ret
= i915_gem_object_wait_rendering__nonblocking(obj
, NULL
, !write
);
1632 /* Access to snoopable pages through the GTT is incoherent. */
1633 if (obj
->cache_level
!= I915_CACHE_NONE
&& !HAS_LLC(dev
)) {
1638 /* Now bind it into the GTT if needed */
1639 ret
= i915_gem_obj_ggtt_pin(obj
, 0, PIN_MAPPABLE
);
1643 ret
= i915_gem_object_set_to_gtt_domain(obj
, write
);
1647 ret
= i915_gem_object_get_fence(obj
);
1651 /* Finally, remap it using the new GTT offset */
1652 pfn
= dev_priv
->gtt
.mappable_base
+ i915_gem_obj_ggtt_offset(obj
);
1655 if (!obj
->fault_mappable
) {
1656 unsigned long size
= min_t(unsigned long,
1657 vma
->vm_end
- vma
->vm_start
,
1661 for (i
= 0; i
< size
>> PAGE_SHIFT
; i
++) {
1662 ret
= vm_insert_pfn(vma
,
1663 (unsigned long)vma
->vm_start
+ i
* PAGE_SIZE
,
1669 obj
->fault_mappable
= true;
1671 ret
= vm_insert_pfn(vma
,
1672 (unsigned long)vmf
->virtual_address
,
1675 i915_gem_object_ggtt_unpin(obj
);
1677 mutex_unlock(&dev
->struct_mutex
);
1682 * We eat errors when the gpu is terminally wedged to avoid
1683 * userspace unduly crashing (gl has no provisions for mmaps to
1684 * fail). But any other -EIO isn't ours (e.g. swap in failure)
1685 * and so needs to be reported.
1687 if (!i915_terminally_wedged(&dev_priv
->gpu_error
)) {
1688 ret
= VM_FAULT_SIGBUS
;
1693 * EAGAIN means the gpu is hung and we'll wait for the error
1694 * handler to reset everything when re-faulting in
1695 * i915_mutex_lock_interruptible.
1702 * EBUSY is ok: this just means that another thread
1703 * already did the job.
1705 ret
= VM_FAULT_NOPAGE
;
1712 ret
= VM_FAULT_SIGBUS
;
1715 WARN_ONCE(ret
, "unhandled error in i915_gem_fault: %i\n", ret
);
1716 ret
= VM_FAULT_SIGBUS
;
1720 intel_runtime_pm_put(dev_priv
);
1725 * i915_gem_release_mmap - remove physical page mappings
1726 * @obj: obj in question
1728 * Preserve the reservation of the mmapping with the DRM core code, but
1729 * relinquish ownership of the pages back to the system.
1731 * It is vital that we remove the page mapping if we have mapped a tiled
1732 * object through the GTT and then lose the fence register due to
1733 * resource pressure. Similarly if the object has been moved out of the
1734 * aperture, than pages mapped into userspace must be revoked. Removing the
1735 * mapping will then trigger a page fault on the next user access, allowing
1736 * fixup by i915_gem_fault().
1739 i915_gem_release_mmap(struct drm_i915_gem_object
*obj
)
1741 if (!obj
->fault_mappable
)
1744 drm_vma_node_unmap(&obj
->base
.vma_node
,
1745 obj
->base
.dev
->anon_inode
->i_mapping
);
1746 obj
->fault_mappable
= false;
1750 i915_gem_release_all_mmaps(struct drm_i915_private
*dev_priv
)
1752 struct drm_i915_gem_object
*obj
;
1754 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
)
1755 i915_gem_release_mmap(obj
);
1759 i915_gem_get_gtt_size(struct drm_device
*dev
, uint32_t size
, int tiling_mode
)
1763 if (INTEL_INFO(dev
)->gen
>= 4 ||
1764 tiling_mode
== I915_TILING_NONE
)
1767 /* Previous chips need a power-of-two fence region when tiling */
1768 if (INTEL_INFO(dev
)->gen
== 3)
1769 gtt_size
= 1024*1024;
1771 gtt_size
= 512*1024;
1773 while (gtt_size
< size
)
1780 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1781 * @obj: object to check
1783 * Return the required GTT alignment for an object, taking into account
1784 * potential fence register mapping.
1787 i915_gem_get_gtt_alignment(struct drm_device
*dev
, uint32_t size
,
1788 int tiling_mode
, bool fenced
)
1791 * Minimum alignment is 4k (GTT page size), but might be greater
1792 * if a fence register is needed for the object.
1794 if (INTEL_INFO(dev
)->gen
>= 4 || (!fenced
&& IS_G33(dev
)) ||
1795 tiling_mode
== I915_TILING_NONE
)
1799 * Previous chips need to be aligned to the size of the smallest
1800 * fence register that can contain the object.
1802 return i915_gem_get_gtt_size(dev
, size
, tiling_mode
);
1805 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object
*obj
)
1807 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
1810 if (drm_vma_node_has_offset(&obj
->base
.vma_node
))
1813 dev_priv
->mm
.shrinker_no_lock_stealing
= true;
1815 ret
= drm_gem_create_mmap_offset(&obj
->base
);
1819 /* Badly fragmented mmap space? The only way we can recover
1820 * space is by destroying unwanted objects. We can't randomly release
1821 * mmap_offsets as userspace expects them to be persistent for the
1822 * lifetime of the objects. The closest we can is to release the
1823 * offsets on purgeable objects by truncating it and marking it purged,
1824 * which prevents userspace from ever using that object again.
1826 i915_gem_shrink(dev_priv
,
1827 obj
->base
.size
>> PAGE_SHIFT
,
1829 I915_SHRINK_UNBOUND
|
1830 I915_SHRINK_PURGEABLE
);
1831 ret
= drm_gem_create_mmap_offset(&obj
->base
);
1835 i915_gem_shrink_all(dev_priv
);
1836 ret
= drm_gem_create_mmap_offset(&obj
->base
);
1838 dev_priv
->mm
.shrinker_no_lock_stealing
= false;
1843 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object
*obj
)
1845 drm_gem_free_mmap_offset(&obj
->base
);
1849 i915_gem_mmap_gtt(struct drm_file
*file
,
1850 struct drm_device
*dev
,
1854 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1855 struct drm_i915_gem_object
*obj
;
1858 ret
= i915_mutex_lock_interruptible(dev
);
1862 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, handle
));
1863 if (&obj
->base
== NULL
) {
1868 if (obj
->base
.size
> dev_priv
->gtt
.mappable_end
) {
1873 if (obj
->madv
!= I915_MADV_WILLNEED
) {
1874 DRM_DEBUG("Attempting to mmap a purgeable buffer\n");
1879 ret
= i915_gem_object_create_mmap_offset(obj
);
1883 *offset
= drm_vma_node_offset_addr(&obj
->base
.vma_node
);
1886 drm_gem_object_unreference(&obj
->base
);
1888 mutex_unlock(&dev
->struct_mutex
);
1893 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1895 * @data: GTT mapping ioctl data
1896 * @file: GEM object info
1898 * Simply returns the fake offset to userspace so it can mmap it.
1899 * The mmap call will end up in drm_gem_mmap(), which will set things
1900 * up so we can get faults in the handler above.
1902 * The fault handler will take care of binding the object into the GTT
1903 * (since it may have been evicted to make room for something), allocating
1904 * a fence register, and mapping the appropriate aperture address into
1908 i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
1909 struct drm_file
*file
)
1911 struct drm_i915_gem_mmap_gtt
*args
= data
;
1913 return i915_gem_mmap_gtt(file
, dev
, args
->handle
, &args
->offset
);
1916 /* Immediately discard the backing storage */
1918 i915_gem_object_truncate(struct drm_i915_gem_object
*obj
)
1920 i915_gem_object_free_mmap_offset(obj
);
1922 if (obj
->base
.filp
== NULL
)
1925 /* Our goal here is to return as much of the memory as
1926 * is possible back to the system as we are called from OOM.
1927 * To do this we must instruct the shmfs to drop all of its
1928 * backing pages, *now*.
1930 shmem_truncate_range(file_inode(obj
->base
.filp
), 0, (loff_t
)-1);
1931 obj
->madv
= __I915_MADV_PURGED
;
1934 /* Try to discard unwanted pages */
1936 i915_gem_object_invalidate(struct drm_i915_gem_object
*obj
)
1938 struct address_space
*mapping
;
1940 switch (obj
->madv
) {
1941 case I915_MADV_DONTNEED
:
1942 i915_gem_object_truncate(obj
);
1943 case __I915_MADV_PURGED
:
1947 if (obj
->base
.filp
== NULL
)
1950 mapping
= file_inode(obj
->base
.filp
)->i_mapping
,
1951 invalidate_mapping_pages(mapping
, 0, (loff_t
)-1);
1955 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object
*obj
)
1957 struct sg_page_iter sg_iter
;
1960 BUG_ON(obj
->madv
== __I915_MADV_PURGED
);
1962 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
1964 /* In the event of a disaster, abandon all caches and
1965 * hope for the best.
1967 WARN_ON(ret
!= -EIO
);
1968 i915_gem_clflush_object(obj
, true);
1969 obj
->base
.read_domains
= obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
1972 if (i915_gem_object_needs_bit17_swizzle(obj
))
1973 i915_gem_object_save_bit_17_swizzle(obj
);
1975 if (obj
->madv
== I915_MADV_DONTNEED
)
1978 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
, 0) {
1979 struct page
*page
= sg_page_iter_page(&sg_iter
);
1982 set_page_dirty(page
);
1984 if (obj
->madv
== I915_MADV_WILLNEED
)
1985 mark_page_accessed(page
);
1987 page_cache_release(page
);
1991 sg_free_table(obj
->pages
);
1996 i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
)
1998 const struct drm_i915_gem_object_ops
*ops
= obj
->ops
;
2000 if (obj
->pages
== NULL
)
2003 if (obj
->pages_pin_count
)
2006 BUG_ON(i915_gem_obj_bound_any(obj
));
2008 /* ->put_pages might need to allocate memory for the bit17 swizzle
2009 * array, hence protect them from being reaped by removing them from gtt
2011 list_del(&obj
->global_list
);
2013 ops
->put_pages(obj
);
2016 i915_gem_object_invalidate(obj
);
2022 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object
*obj
)
2024 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2026 struct address_space
*mapping
;
2027 struct sg_table
*st
;
2028 struct scatterlist
*sg
;
2029 struct sg_page_iter sg_iter
;
2031 unsigned long last_pfn
= 0; /* suppress gcc warning */
2034 /* Assert that the object is not currently in any GPU domain. As it
2035 * wasn't in the GTT, there shouldn't be any way it could have been in
2038 BUG_ON(obj
->base
.read_domains
& I915_GEM_GPU_DOMAINS
);
2039 BUG_ON(obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
);
2041 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
2045 page_count
= obj
->base
.size
/ PAGE_SIZE
;
2046 if (sg_alloc_table(st
, page_count
, GFP_KERNEL
)) {
2051 /* Get the list of pages out of our struct file. They'll be pinned
2052 * at this point until we release them.
2054 * Fail silently without starting the shrinker
2056 mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
2057 gfp
= mapping_gfp_mask(mapping
);
2058 gfp
|= __GFP_NORETRY
| __GFP_NOWARN
| __GFP_NO_KSWAPD
;
2059 gfp
&= ~(__GFP_IO
| __GFP_WAIT
);
2062 for (i
= 0; i
< page_count
; i
++) {
2063 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
2065 i915_gem_shrink(dev_priv
,
2068 I915_SHRINK_UNBOUND
|
2069 I915_SHRINK_PURGEABLE
);
2070 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
2073 /* We've tried hard to allocate the memory by reaping
2074 * our own buffer, now let the real VM do its job and
2075 * go down in flames if truly OOM.
2077 i915_gem_shrink_all(dev_priv
);
2078 page
= shmem_read_mapping_page(mapping
, i
);
2082 #ifdef CONFIG_SWIOTLB
2083 if (swiotlb_nr_tbl()) {
2085 sg_set_page(sg
, page
, PAGE_SIZE
, 0);
2090 if (!i
|| page_to_pfn(page
) != last_pfn
+ 1) {
2094 sg_set_page(sg
, page
, PAGE_SIZE
, 0);
2096 sg
->length
+= PAGE_SIZE
;
2098 last_pfn
= page_to_pfn(page
);
2100 /* Check that the i965g/gm workaround works. */
2101 WARN_ON((gfp
& __GFP_DMA32
) && (last_pfn
>= 0x00100000UL
));
2103 #ifdef CONFIG_SWIOTLB
2104 if (!swiotlb_nr_tbl())
2109 if (i915_gem_object_needs_bit17_swizzle(obj
))
2110 i915_gem_object_do_bit_17_swizzle(obj
);
2112 if (obj
->tiling_mode
!= I915_TILING_NONE
&&
2113 dev_priv
->quirks
& QUIRK_PIN_SWIZZLED_PAGES
)
2114 i915_gem_object_pin_pages(obj
);
2120 for_each_sg_page(st
->sgl
, &sg_iter
, st
->nents
, 0)
2121 page_cache_release(sg_page_iter_page(&sg_iter
));
2125 /* shmemfs first checks if there is enough memory to allocate the page
2126 * and reports ENOSPC should there be insufficient, along with the usual
2127 * ENOMEM for a genuine allocation failure.
2129 * We use ENOSPC in our driver to mean that we have run out of aperture
2130 * space and so want to translate the error from shmemfs back to our
2131 * usual understanding of ENOMEM.
2133 if (PTR_ERR(page
) == -ENOSPC
)
2136 return PTR_ERR(page
);
2139 /* Ensure that the associated pages are gathered from the backing storage
2140 * and pinned into our object. i915_gem_object_get_pages() may be called
2141 * multiple times before they are released by a single call to
2142 * i915_gem_object_put_pages() - once the pages are no longer referenced
2143 * either as a result of memory pressure (reaping pages under the shrinker)
2144 * or as the object is itself released.
2147 i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
)
2149 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2150 const struct drm_i915_gem_object_ops
*ops
= obj
->ops
;
2156 if (obj
->madv
!= I915_MADV_WILLNEED
) {
2157 DRM_DEBUG("Attempting to obtain a purgeable object\n");
2161 BUG_ON(obj
->pages_pin_count
);
2163 ret
= ops
->get_pages(obj
);
2167 list_add_tail(&obj
->global_list
, &dev_priv
->mm
.unbound_list
);
2169 obj
->get_page
.sg
= obj
->pages
->sgl
;
2170 obj
->get_page
.last
= 0;
2176 i915_gem_object_move_to_active(struct drm_i915_gem_object
*obj
,
2177 struct intel_engine_cs
*ring
)
2179 struct drm_i915_gem_request
*req
;
2180 struct intel_engine_cs
*old_ring
;
2182 BUG_ON(ring
== NULL
);
2184 req
= intel_ring_get_request(ring
);
2185 old_ring
= i915_gem_request_get_ring(obj
->last_read_req
);
2187 if (old_ring
!= ring
&& obj
->last_write_req
) {
2188 /* Keep the request relative to the current ring */
2189 i915_gem_request_assign(&obj
->last_write_req
, req
);
2192 /* Add a reference if we're newly entering the active list. */
2194 drm_gem_object_reference(&obj
->base
);
2198 list_move_tail(&obj
->ring_list
, &ring
->active_list
);
2200 i915_gem_request_assign(&obj
->last_read_req
, req
);
2203 void i915_vma_move_to_active(struct i915_vma
*vma
,
2204 struct intel_engine_cs
*ring
)
2206 list_move_tail(&vma
->mm_list
, &vma
->vm
->active_list
);
2207 return i915_gem_object_move_to_active(vma
->obj
, ring
);
2211 i915_gem_object_move_to_inactive(struct drm_i915_gem_object
*obj
)
2213 struct i915_vma
*vma
;
2215 BUG_ON(obj
->base
.write_domain
& ~I915_GEM_GPU_DOMAINS
);
2216 BUG_ON(!obj
->active
);
2218 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
) {
2219 if (!list_empty(&vma
->mm_list
))
2220 list_move_tail(&vma
->mm_list
, &vma
->vm
->inactive_list
);
2223 intel_fb_obj_flush(obj
, true);
2225 list_del_init(&obj
->ring_list
);
2227 i915_gem_request_assign(&obj
->last_read_req
, NULL
);
2228 i915_gem_request_assign(&obj
->last_write_req
, NULL
);
2229 obj
->base
.write_domain
= 0;
2231 i915_gem_request_assign(&obj
->last_fenced_req
, NULL
);
2234 drm_gem_object_unreference(&obj
->base
);
2236 WARN_ON(i915_verify_lists(dev
));
2240 i915_gem_object_retire(struct drm_i915_gem_object
*obj
)
2242 if (obj
->last_read_req
== NULL
)
2245 if (i915_gem_request_completed(obj
->last_read_req
, true))
2246 i915_gem_object_move_to_inactive(obj
);
2250 i915_gem_init_seqno(struct drm_device
*dev
, u32 seqno
)
2252 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2253 struct intel_engine_cs
*ring
;
2256 /* Carefully retire all requests without writing to the rings */
2257 for_each_ring(ring
, dev_priv
, i
) {
2258 ret
= intel_ring_idle(ring
);
2262 i915_gem_retire_requests(dev
);
2264 /* Finally reset hw state */
2265 for_each_ring(ring
, dev_priv
, i
) {
2266 intel_ring_init_seqno(ring
, seqno
);
2268 for (j
= 0; j
< ARRAY_SIZE(ring
->semaphore
.sync_seqno
); j
++)
2269 ring
->semaphore
.sync_seqno
[j
] = 0;
2275 int i915_gem_set_seqno(struct drm_device
*dev
, u32 seqno
)
2277 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2283 /* HWS page needs to be set less than what we
2284 * will inject to ring
2286 ret
= i915_gem_init_seqno(dev
, seqno
- 1);
2290 /* Carefully set the last_seqno value so that wrap
2291 * detection still works
2293 dev_priv
->next_seqno
= seqno
;
2294 dev_priv
->last_seqno
= seqno
- 1;
2295 if (dev_priv
->last_seqno
== 0)
2296 dev_priv
->last_seqno
--;
2302 i915_gem_get_seqno(struct drm_device
*dev
, u32
*seqno
)
2304 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2306 /* reserve 0 for non-seqno */
2307 if (dev_priv
->next_seqno
== 0) {
2308 int ret
= i915_gem_init_seqno(dev
, 0);
2312 dev_priv
->next_seqno
= 1;
2315 *seqno
= dev_priv
->last_seqno
= dev_priv
->next_seqno
++;
2319 int __i915_add_request(struct intel_engine_cs
*ring
,
2320 struct drm_file
*file
,
2321 struct drm_i915_gem_object
*obj
)
2323 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
2324 struct drm_i915_gem_request
*request
;
2325 struct intel_ringbuffer
*ringbuf
;
2329 request
= ring
->outstanding_lazy_request
;
2330 if (WARN_ON(request
== NULL
))
2333 if (i915
.enable_execlists
) {
2334 ringbuf
= request
->ctx
->engine
[ring
->id
].ringbuf
;
2336 ringbuf
= ring
->buffer
;
2338 request_start
= intel_ring_get_tail(ringbuf
);
2340 * Emit any outstanding flushes - execbuf can fail to emit the flush
2341 * after having emitted the batchbuffer command. Hence we need to fix
2342 * things up similar to emitting the lazy request. The difference here
2343 * is that the flush _must_ happen before the next request, no matter
2346 if (i915
.enable_execlists
) {
2347 ret
= logical_ring_flush_all_caches(ringbuf
, request
->ctx
);
2351 ret
= intel_ring_flush_all_caches(ring
);
2356 /* Record the position of the start of the request so that
2357 * should we detect the updated seqno part-way through the
2358 * GPU processing the request, we never over-estimate the
2359 * position of the head.
2361 request
->postfix
= intel_ring_get_tail(ringbuf
);
2363 if (i915
.enable_execlists
) {
2364 ret
= ring
->emit_request(ringbuf
, request
);
2368 ret
= ring
->add_request(ring
);
2373 request
->head
= request_start
;
2374 request
->tail
= intel_ring_get_tail(ringbuf
);
2376 /* Whilst this request exists, batch_obj will be on the
2377 * active_list, and so will hold the active reference. Only when this
2378 * request is retired will the the batch_obj be moved onto the
2379 * inactive_list and lose its active reference. Hence we do not need
2380 * to explicitly hold another reference here.
2382 request
->batch_obj
= obj
;
2384 if (!i915
.enable_execlists
) {
2385 /* Hold a reference to the current context so that we can inspect
2386 * it later in case a hangcheck error event fires.
2388 request
->ctx
= ring
->last_context
;
2390 i915_gem_context_reference(request
->ctx
);
2393 request
->emitted_jiffies
= jiffies
;
2394 list_add_tail(&request
->list
, &ring
->request_list
);
2395 request
->file_priv
= NULL
;
2398 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
2400 spin_lock(&file_priv
->mm
.lock
);
2401 request
->file_priv
= file_priv
;
2402 list_add_tail(&request
->client_list
,
2403 &file_priv
->mm
.request_list
);
2404 spin_unlock(&file_priv
->mm
.lock
);
2406 request
->pid
= get_pid(task_pid(current
));
2409 trace_i915_gem_request_add(request
);
2410 ring
->outstanding_lazy_request
= NULL
;
2412 i915_queue_hangcheck(ring
->dev
);
2414 queue_delayed_work(dev_priv
->wq
,
2415 &dev_priv
->mm
.retire_work
,
2416 round_jiffies_up_relative(HZ
));
2417 intel_mark_busy(dev_priv
->dev
);
2423 i915_gem_request_remove_from_client(struct drm_i915_gem_request
*request
)
2425 struct drm_i915_file_private
*file_priv
= request
->file_priv
;
2430 spin_lock(&file_priv
->mm
.lock
);
2431 list_del(&request
->client_list
);
2432 request
->file_priv
= NULL
;
2433 spin_unlock(&file_priv
->mm
.lock
);
2436 static bool i915_context_is_banned(struct drm_i915_private
*dev_priv
,
2437 const struct intel_context
*ctx
)
2439 unsigned long elapsed
;
2441 elapsed
= get_seconds() - ctx
->hang_stats
.guilty_ts
;
2443 if (ctx
->hang_stats
.banned
)
2446 if (ctx
->hang_stats
.ban_period_seconds
&&
2447 elapsed
<= ctx
->hang_stats
.ban_period_seconds
) {
2448 if (!i915_gem_context_is_default(ctx
)) {
2449 DRM_DEBUG("context hanging too fast, banning!\n");
2451 } else if (i915_stop_ring_allow_ban(dev_priv
)) {
2452 if (i915_stop_ring_allow_warn(dev_priv
))
2453 DRM_ERROR("gpu hanging too fast, banning!\n");
2461 static void i915_set_reset_status(struct drm_i915_private
*dev_priv
,
2462 struct intel_context
*ctx
,
2465 struct i915_ctx_hang_stats
*hs
;
2470 hs
= &ctx
->hang_stats
;
2473 hs
->banned
= i915_context_is_banned(dev_priv
, ctx
);
2475 hs
->guilty_ts
= get_seconds();
2477 hs
->batch_pending
++;
2481 static void i915_gem_free_request(struct drm_i915_gem_request
*request
)
2483 list_del(&request
->list
);
2484 i915_gem_request_remove_from_client(request
);
2486 put_pid(request
->pid
);
2488 i915_gem_request_unreference(request
);
2491 void i915_gem_request_free(struct kref
*req_ref
)
2493 struct drm_i915_gem_request
*req
= container_of(req_ref
,
2495 struct intel_context
*ctx
= req
->ctx
;
2498 if (i915
.enable_execlists
) {
2499 struct intel_engine_cs
*ring
= req
->ring
;
2501 if (ctx
!= ring
->default_context
)
2502 intel_lr_context_unpin(ring
, ctx
);
2505 i915_gem_context_unreference(ctx
);
2508 kmem_cache_free(req
->i915
->requests
, req
);
2511 int i915_gem_request_alloc(struct intel_engine_cs
*ring
,
2512 struct intel_context
*ctx
)
2514 struct drm_i915_private
*dev_priv
= to_i915(ring
->dev
);
2515 struct drm_i915_gem_request
*rq
;
2518 if (ring
->outstanding_lazy_request
)
2521 rq
= kmem_cache_zalloc(dev_priv
->requests
, GFP_KERNEL
);
2525 kref_init(&rq
->ref
);
2526 rq
->i915
= dev_priv
;
2528 ret
= i915_gem_get_seqno(ring
->dev
, &rq
->seqno
);
2535 rq
->uniq
= dev_priv
->request_uniq
++;
2537 if (i915
.enable_execlists
)
2538 ret
= intel_logical_ring_alloc_request_extras(rq
, ctx
);
2540 ret
= intel_ring_alloc_request_extras(rq
);
2546 ring
->outstanding_lazy_request
= rq
;
2550 struct drm_i915_gem_request
*
2551 i915_gem_find_active_request(struct intel_engine_cs
*ring
)
2553 struct drm_i915_gem_request
*request
;
2555 list_for_each_entry(request
, &ring
->request_list
, list
) {
2556 if (i915_gem_request_completed(request
, false))
2565 static void i915_gem_reset_ring_status(struct drm_i915_private
*dev_priv
,
2566 struct intel_engine_cs
*ring
)
2568 struct drm_i915_gem_request
*request
;
2571 request
= i915_gem_find_active_request(ring
);
2573 if (request
== NULL
)
2576 ring_hung
= ring
->hangcheck
.score
>= HANGCHECK_SCORE_RING_HUNG
;
2578 i915_set_reset_status(dev_priv
, request
->ctx
, ring_hung
);
2580 list_for_each_entry_continue(request
, &ring
->request_list
, list
)
2581 i915_set_reset_status(dev_priv
, request
->ctx
, false);
2584 static void i915_gem_reset_ring_cleanup(struct drm_i915_private
*dev_priv
,
2585 struct intel_engine_cs
*ring
)
2587 while (!list_empty(&ring
->active_list
)) {
2588 struct drm_i915_gem_object
*obj
;
2590 obj
= list_first_entry(&ring
->active_list
,
2591 struct drm_i915_gem_object
,
2594 i915_gem_object_move_to_inactive(obj
);
2598 * Clear the execlists queue up before freeing the requests, as those
2599 * are the ones that keep the context and ringbuffer backing objects
2602 while (!list_empty(&ring
->execlist_queue
)) {
2603 struct drm_i915_gem_request
*submit_req
;
2605 submit_req
= list_first_entry(&ring
->execlist_queue
,
2606 struct drm_i915_gem_request
,
2608 list_del(&submit_req
->execlist_link
);
2610 if (submit_req
->ctx
!= ring
->default_context
)
2611 intel_lr_context_unpin(ring
, submit_req
->ctx
);
2613 i915_gem_request_unreference(submit_req
);
2617 * We must free the requests after all the corresponding objects have
2618 * been moved off active lists. Which is the same order as the normal
2619 * retire_requests function does. This is important if object hold
2620 * implicit references on things like e.g. ppgtt address spaces through
2623 while (!list_empty(&ring
->request_list
)) {
2624 struct drm_i915_gem_request
*request
;
2626 request
= list_first_entry(&ring
->request_list
,
2627 struct drm_i915_gem_request
,
2630 i915_gem_free_request(request
);
2633 /* This may not have been flushed before the reset, so clean it now */
2634 i915_gem_request_assign(&ring
->outstanding_lazy_request
, NULL
);
2637 void i915_gem_restore_fences(struct drm_device
*dev
)
2639 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2642 for (i
= 0; i
< dev_priv
->num_fence_regs
; i
++) {
2643 struct drm_i915_fence_reg
*reg
= &dev_priv
->fence_regs
[i
];
2646 * Commit delayed tiling changes if we have an object still
2647 * attached to the fence, otherwise just clear the fence.
2650 i915_gem_object_update_fence(reg
->obj
, reg
,
2651 reg
->obj
->tiling_mode
);
2653 i915_gem_write_fence(dev
, i
, NULL
);
2658 void i915_gem_reset(struct drm_device
*dev
)
2660 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2661 struct intel_engine_cs
*ring
;
2665 * Before we free the objects from the requests, we need to inspect
2666 * them for finding the guilty party. As the requests only borrow
2667 * their reference to the objects, the inspection must be done first.
2669 for_each_ring(ring
, dev_priv
, i
)
2670 i915_gem_reset_ring_status(dev_priv
, ring
);
2672 for_each_ring(ring
, dev_priv
, i
)
2673 i915_gem_reset_ring_cleanup(dev_priv
, ring
);
2675 i915_gem_context_reset(dev
);
2677 i915_gem_restore_fences(dev
);
2681 * This function clears the request list as sequence numbers are passed.
2684 i915_gem_retire_requests_ring(struct intel_engine_cs
*ring
)
2686 if (list_empty(&ring
->request_list
))
2689 WARN_ON(i915_verify_lists(ring
->dev
));
2691 /* Retire requests first as we use it above for the early return.
2692 * If we retire requests last, we may use a later seqno and so clear
2693 * the requests lists without clearing the active list, leading to
2696 while (!list_empty(&ring
->request_list
)) {
2697 struct drm_i915_gem_request
*request
;
2699 request
= list_first_entry(&ring
->request_list
,
2700 struct drm_i915_gem_request
,
2703 if (!i915_gem_request_completed(request
, true))
2706 trace_i915_gem_request_retire(request
);
2708 /* We know the GPU must have read the request to have
2709 * sent us the seqno + interrupt, so use the position
2710 * of tail of the request to update the last known position
2713 request
->ringbuf
->last_retired_head
= request
->postfix
;
2715 i915_gem_free_request(request
);
2718 /* Move any buffers on the active list that are no longer referenced
2719 * by the ringbuffer to the flushing/inactive lists as appropriate,
2720 * before we free the context associated with the requests.
2722 while (!list_empty(&ring
->active_list
)) {
2723 struct drm_i915_gem_object
*obj
;
2725 obj
= list_first_entry(&ring
->active_list
,
2726 struct drm_i915_gem_object
,
2729 if (!i915_gem_request_completed(obj
->last_read_req
, true))
2732 i915_gem_object_move_to_inactive(obj
);
2735 if (unlikely(ring
->trace_irq_req
&&
2736 i915_gem_request_completed(ring
->trace_irq_req
, true))) {
2737 ring
->irq_put(ring
);
2738 i915_gem_request_assign(&ring
->trace_irq_req
, NULL
);
2741 WARN_ON(i915_verify_lists(ring
->dev
));
2745 i915_gem_retire_requests(struct drm_device
*dev
)
2747 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2748 struct intel_engine_cs
*ring
;
2752 for_each_ring(ring
, dev_priv
, i
) {
2753 i915_gem_retire_requests_ring(ring
);
2754 idle
&= list_empty(&ring
->request_list
);
2755 if (i915
.enable_execlists
) {
2756 unsigned long flags
;
2758 spin_lock_irqsave(&ring
->execlist_lock
, flags
);
2759 idle
&= list_empty(&ring
->execlist_queue
);
2760 spin_unlock_irqrestore(&ring
->execlist_lock
, flags
);
2762 intel_execlists_retire_requests(ring
);
2767 mod_delayed_work(dev_priv
->wq
,
2768 &dev_priv
->mm
.idle_work
,
2769 msecs_to_jiffies(100));
2775 i915_gem_retire_work_handler(struct work_struct
*work
)
2777 struct drm_i915_private
*dev_priv
=
2778 container_of(work
, typeof(*dev_priv
), mm
.retire_work
.work
);
2779 struct drm_device
*dev
= dev_priv
->dev
;
2782 /* Come back later if the device is busy... */
2784 if (mutex_trylock(&dev
->struct_mutex
)) {
2785 idle
= i915_gem_retire_requests(dev
);
2786 mutex_unlock(&dev
->struct_mutex
);
2789 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
,
2790 round_jiffies_up_relative(HZ
));
2794 i915_gem_idle_work_handler(struct work_struct
*work
)
2796 struct drm_i915_private
*dev_priv
=
2797 container_of(work
, typeof(*dev_priv
), mm
.idle_work
.work
);
2798 struct drm_device
*dev
= dev_priv
->dev
;
2799 struct intel_engine_cs
*ring
;
2802 for_each_ring(ring
, dev_priv
, i
)
2803 if (!list_empty(&ring
->request_list
))
2806 intel_mark_idle(dev
);
2808 if (mutex_trylock(&dev
->struct_mutex
)) {
2809 struct intel_engine_cs
*ring
;
2812 for_each_ring(ring
, dev_priv
, i
)
2813 i915_gem_batch_pool_fini(&ring
->batch_pool
);
2815 mutex_unlock(&dev
->struct_mutex
);
2820 * Ensures that an object will eventually get non-busy by flushing any required
2821 * write domains, emitting any outstanding lazy request and retiring and
2822 * completed requests.
2825 i915_gem_object_flush_active(struct drm_i915_gem_object
*obj
)
2827 struct intel_engine_cs
*ring
;
2831 ring
= i915_gem_request_get_ring(obj
->last_read_req
);
2833 ret
= i915_gem_check_olr(obj
->last_read_req
);
2837 i915_gem_retire_requests_ring(ring
);
2844 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2845 * @DRM_IOCTL_ARGS: standard ioctl arguments
2847 * Returns 0 if successful, else an error is returned with the remaining time in
2848 * the timeout parameter.
2849 * -ETIME: object is still busy after timeout
2850 * -ERESTARTSYS: signal interrupted the wait
2851 * -ENONENT: object doesn't exist
2852 * Also possible, but rare:
2853 * -EAGAIN: GPU wedged
2855 * -ENODEV: Internal IRQ fail
2856 * -E?: The add request failed
2858 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2859 * non-zero timeout parameter the wait ioctl will wait for the given number of
2860 * nanoseconds on an object becoming unbusy. Since the wait itself does so
2861 * without holding struct_mutex the object may become re-busied before this
2862 * function completes. A similar but shorter * race condition exists in the busy
2866 i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
, struct drm_file
*file
)
2868 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2869 struct drm_i915_gem_wait
*args
= data
;
2870 struct drm_i915_gem_object
*obj
;
2871 struct drm_i915_gem_request
*req
;
2872 unsigned reset_counter
;
2875 if (args
->flags
!= 0)
2878 ret
= i915_mutex_lock_interruptible(dev
);
2882 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->bo_handle
));
2883 if (&obj
->base
== NULL
) {
2884 mutex_unlock(&dev
->struct_mutex
);
2888 /* Need to make sure the object gets inactive eventually. */
2889 ret
= i915_gem_object_flush_active(obj
);
2893 if (!obj
->active
|| !obj
->last_read_req
)
2896 req
= obj
->last_read_req
;
2898 /* Do this after OLR check to make sure we make forward progress polling
2899 * on this IOCTL with a timeout == 0 (like busy ioctl)
2901 if (args
->timeout_ns
== 0) {
2906 drm_gem_object_unreference(&obj
->base
);
2907 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
2908 i915_gem_request_reference(req
);
2909 mutex_unlock(&dev
->struct_mutex
);
2911 ret
= __i915_wait_request(req
, reset_counter
, true,
2912 args
->timeout_ns
> 0 ? &args
->timeout_ns
: NULL
,
2914 i915_gem_request_unreference__unlocked(req
);
2918 drm_gem_object_unreference(&obj
->base
);
2919 mutex_unlock(&dev
->struct_mutex
);
2924 * i915_gem_object_sync - sync an object to a ring.
2926 * @obj: object which may be in use on another ring.
2927 * @to: ring we wish to use the object on. May be NULL.
2929 * This code is meant to abstract object synchronization with the GPU.
2930 * Calling with NULL implies synchronizing the object with the CPU
2931 * rather than a particular GPU ring.
2933 * Returns 0 if successful, else propagates up the lower layer error.
2936 i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
2937 struct intel_engine_cs
*to
)
2939 struct intel_engine_cs
*from
;
2943 from
= i915_gem_request_get_ring(obj
->last_read_req
);
2945 if (from
== NULL
|| to
== from
)
2948 if (to
== NULL
|| !i915_semaphore_is_enabled(obj
->base
.dev
))
2949 return i915_gem_object_wait_rendering(obj
, false);
2951 idx
= intel_ring_sync_index(from
, to
);
2953 seqno
= i915_gem_request_get_seqno(obj
->last_read_req
);
2954 /* Optimization: Avoid semaphore sync when we are sure we already
2955 * waited for an object with higher seqno */
2956 if (seqno
<= from
->semaphore
.sync_seqno
[idx
])
2959 ret
= i915_gem_check_olr(obj
->last_read_req
);
2963 trace_i915_gem_ring_sync_to(from
, to
, obj
->last_read_req
);
2964 ret
= to
->semaphore
.sync_to(to
, from
, seqno
);
2966 /* We use last_read_req because sync_to()
2967 * might have just caused seqno wrap under
2970 from
->semaphore
.sync_seqno
[idx
] =
2971 i915_gem_request_get_seqno(obj
->last_read_req
);
2976 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object
*obj
)
2978 u32 old_write_domain
, old_read_domains
;
2980 /* Force a pagefault for domain tracking on next user access */
2981 i915_gem_release_mmap(obj
);
2983 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
) == 0)
2986 /* Wait for any direct GTT access to complete */
2989 old_read_domains
= obj
->base
.read_domains
;
2990 old_write_domain
= obj
->base
.write_domain
;
2992 obj
->base
.read_domains
&= ~I915_GEM_DOMAIN_GTT
;
2993 obj
->base
.write_domain
&= ~I915_GEM_DOMAIN_GTT
;
2995 trace_i915_gem_object_change_domain(obj
,
3000 int i915_vma_unbind(struct i915_vma
*vma
)
3002 struct drm_i915_gem_object
*obj
= vma
->obj
;
3003 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
3006 if (list_empty(&vma
->vma_link
))
3009 if (!drm_mm_node_allocated(&vma
->node
)) {
3010 i915_gem_vma_destroy(vma
);
3017 BUG_ON(obj
->pages
== NULL
);
3019 ret
= i915_gem_object_finish_gpu(obj
);
3022 /* Continue on if we fail due to EIO, the GPU is hung so we
3023 * should be safe and we need to cleanup or else we might
3024 * cause memory corruption through use-after-free.
3027 if (i915_is_ggtt(vma
->vm
) &&
3028 vma
->ggtt_view
.type
== I915_GGTT_VIEW_NORMAL
) {
3029 i915_gem_object_finish_gtt(obj
);
3031 /* release the fence reg _after_ flushing */
3032 ret
= i915_gem_object_put_fence(obj
);
3037 trace_i915_vma_unbind(vma
);
3039 vma
->unbind_vma(vma
);
3041 list_del_init(&vma
->mm_list
);
3042 if (i915_is_ggtt(vma
->vm
)) {
3043 if (vma
->ggtt_view
.type
== I915_GGTT_VIEW_NORMAL
) {
3044 obj
->map_and_fenceable
= false;
3045 } else if (vma
->ggtt_view
.pages
) {
3046 sg_free_table(vma
->ggtt_view
.pages
);
3047 kfree(vma
->ggtt_view
.pages
);
3048 vma
->ggtt_view
.pages
= NULL
;
3052 drm_mm_remove_node(&vma
->node
);
3053 i915_gem_vma_destroy(vma
);
3055 /* Since the unbound list is global, only move to that list if
3056 * no more VMAs exist. */
3057 if (list_empty(&obj
->vma_list
)) {
3058 /* Throw away the active reference before
3059 * moving to the unbound list. */
3060 i915_gem_object_retire(obj
);
3062 i915_gem_gtt_finish_object(obj
);
3063 list_move_tail(&obj
->global_list
, &dev_priv
->mm
.unbound_list
);
3066 /* And finally now the object is completely decoupled from this vma,
3067 * we can drop its hold on the backing storage and allow it to be
3068 * reaped by the shrinker.
3070 i915_gem_object_unpin_pages(obj
);
3075 int i915_gpu_idle(struct drm_device
*dev
)
3077 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3078 struct intel_engine_cs
*ring
;
3081 /* Flush everything onto the inactive list. */
3082 for_each_ring(ring
, dev_priv
, i
) {
3083 if (!i915
.enable_execlists
) {
3084 ret
= i915_switch_context(ring
, ring
->default_context
);
3089 ret
= intel_ring_idle(ring
);
3097 static void i965_write_fence_reg(struct drm_device
*dev
, int reg
,
3098 struct drm_i915_gem_object
*obj
)
3100 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3102 int fence_pitch_shift
;
3104 if (INTEL_INFO(dev
)->gen
>= 6) {
3105 fence_reg
= FENCE_REG_SANDYBRIDGE_0
;
3106 fence_pitch_shift
= SANDYBRIDGE_FENCE_PITCH_SHIFT
;
3108 fence_reg
= FENCE_REG_965_0
;
3109 fence_pitch_shift
= I965_FENCE_PITCH_SHIFT
;
3112 fence_reg
+= reg
* 8;
3114 /* To w/a incoherency with non-atomic 64-bit register updates,
3115 * we split the 64-bit update into two 32-bit writes. In order
3116 * for a partial fence not to be evaluated between writes, we
3117 * precede the update with write to turn off the fence register,
3118 * and only enable the fence as the last step.
3120 * For extra levels of paranoia, we make sure each step lands
3121 * before applying the next step.
3123 I915_WRITE(fence_reg
, 0);
3124 POSTING_READ(fence_reg
);
3127 u32 size
= i915_gem_obj_ggtt_size(obj
);
3130 /* Adjust fence size to match tiled area */
3131 if (obj
->tiling_mode
!= I915_TILING_NONE
) {
3132 uint32_t row_size
= obj
->stride
*
3133 (obj
->tiling_mode
== I915_TILING_Y
? 32 : 8);
3134 size
= (size
/ row_size
) * row_size
;
3137 val
= (uint64_t)((i915_gem_obj_ggtt_offset(obj
) + size
- 4096) &
3139 val
|= i915_gem_obj_ggtt_offset(obj
) & 0xfffff000;
3140 val
|= (uint64_t)((obj
->stride
/ 128) - 1) << fence_pitch_shift
;
3141 if (obj
->tiling_mode
== I915_TILING_Y
)
3142 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
3143 val
|= I965_FENCE_REG_VALID
;
3145 I915_WRITE(fence_reg
+ 4, val
>> 32);
3146 POSTING_READ(fence_reg
+ 4);
3148 I915_WRITE(fence_reg
+ 0, val
);
3149 POSTING_READ(fence_reg
);
3151 I915_WRITE(fence_reg
+ 4, 0);
3152 POSTING_READ(fence_reg
+ 4);
3156 static void i915_write_fence_reg(struct drm_device
*dev
, int reg
,
3157 struct drm_i915_gem_object
*obj
)
3159 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3163 u32 size
= i915_gem_obj_ggtt_size(obj
);
3167 WARN((i915_gem_obj_ggtt_offset(obj
) & ~I915_FENCE_START_MASK
) ||
3168 (size
& -size
) != size
||
3169 (i915_gem_obj_ggtt_offset(obj
) & (size
- 1)),
3170 "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
3171 i915_gem_obj_ggtt_offset(obj
), obj
->map_and_fenceable
, size
);
3173 if (obj
->tiling_mode
== I915_TILING_Y
&& HAS_128_BYTE_Y_TILING(dev
))
3178 /* Note: pitch better be a power of two tile widths */
3179 pitch_val
= obj
->stride
/ tile_width
;
3180 pitch_val
= ffs(pitch_val
) - 1;
3182 val
= i915_gem_obj_ggtt_offset(obj
);
3183 if (obj
->tiling_mode
== I915_TILING_Y
)
3184 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
3185 val
|= I915_FENCE_SIZE_BITS(size
);
3186 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
3187 val
|= I830_FENCE_REG_VALID
;
3192 reg
= FENCE_REG_830_0
+ reg
* 4;
3194 reg
= FENCE_REG_945_8
+ (reg
- 8) * 4;
3196 I915_WRITE(reg
, val
);
3200 static void i830_write_fence_reg(struct drm_device
*dev
, int reg
,
3201 struct drm_i915_gem_object
*obj
)
3203 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3207 u32 size
= i915_gem_obj_ggtt_size(obj
);
3210 WARN((i915_gem_obj_ggtt_offset(obj
) & ~I830_FENCE_START_MASK
) ||
3211 (size
& -size
) != size
||
3212 (i915_gem_obj_ggtt_offset(obj
) & (size
- 1)),
3213 "object 0x%08lx not 512K or pot-size 0x%08x aligned\n",
3214 i915_gem_obj_ggtt_offset(obj
), size
);
3216 pitch_val
= obj
->stride
/ 128;
3217 pitch_val
= ffs(pitch_val
) - 1;
3219 val
= i915_gem_obj_ggtt_offset(obj
);
3220 if (obj
->tiling_mode
== I915_TILING_Y
)
3221 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
3222 val
|= I830_FENCE_SIZE_BITS(size
);
3223 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
3224 val
|= I830_FENCE_REG_VALID
;
3228 I915_WRITE(FENCE_REG_830_0
+ reg
* 4, val
);
3229 POSTING_READ(FENCE_REG_830_0
+ reg
* 4);
3232 inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object
*obj
)
3234 return obj
&& obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
;
3237 static void i915_gem_write_fence(struct drm_device
*dev
, int reg
,
3238 struct drm_i915_gem_object
*obj
)
3240 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3242 /* Ensure that all CPU reads are completed before installing a fence
3243 * and all writes before removing the fence.
3245 if (i915_gem_object_needs_mb(dev_priv
->fence_regs
[reg
].obj
))
3248 WARN(obj
&& (!obj
->stride
|| !obj
->tiling_mode
),
3249 "bogus fence setup with stride: 0x%x, tiling mode: %i\n",
3250 obj
->stride
, obj
->tiling_mode
);
3253 i830_write_fence_reg(dev
, reg
, obj
);
3254 else if (IS_GEN3(dev
))
3255 i915_write_fence_reg(dev
, reg
, obj
);
3256 else if (INTEL_INFO(dev
)->gen
>= 4)
3257 i965_write_fence_reg(dev
, reg
, obj
);
3259 /* And similarly be paranoid that no direct access to this region
3260 * is reordered to before the fence is installed.
3262 if (i915_gem_object_needs_mb(obj
))
3266 static inline int fence_number(struct drm_i915_private
*dev_priv
,
3267 struct drm_i915_fence_reg
*fence
)
3269 return fence
- dev_priv
->fence_regs
;
3272 static void i915_gem_object_update_fence(struct drm_i915_gem_object
*obj
,
3273 struct drm_i915_fence_reg
*fence
,
3276 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
3277 int reg
= fence_number(dev_priv
, fence
);
3279 i915_gem_write_fence(obj
->base
.dev
, reg
, enable
? obj
: NULL
);
3282 obj
->fence_reg
= reg
;
3284 list_move_tail(&fence
->lru_list
, &dev_priv
->mm
.fence_list
);
3286 obj
->fence_reg
= I915_FENCE_REG_NONE
;
3288 list_del_init(&fence
->lru_list
);
3290 obj
->fence_dirty
= false;
3294 i915_gem_object_wait_fence(struct drm_i915_gem_object
*obj
)
3296 if (obj
->last_fenced_req
) {
3297 int ret
= i915_wait_request(obj
->last_fenced_req
);
3301 i915_gem_request_assign(&obj
->last_fenced_req
, NULL
);
3308 i915_gem_object_put_fence(struct drm_i915_gem_object
*obj
)
3310 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
3311 struct drm_i915_fence_reg
*fence
;
3314 ret
= i915_gem_object_wait_fence(obj
);
3318 if (obj
->fence_reg
== I915_FENCE_REG_NONE
)
3321 fence
= &dev_priv
->fence_regs
[obj
->fence_reg
];
3323 if (WARN_ON(fence
->pin_count
))
3326 i915_gem_object_fence_lost(obj
);
3327 i915_gem_object_update_fence(obj
, fence
, false);
3332 static struct drm_i915_fence_reg
*
3333 i915_find_fence_reg(struct drm_device
*dev
)
3335 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3336 struct drm_i915_fence_reg
*reg
, *avail
;
3339 /* First try to find a free reg */
3341 for (i
= dev_priv
->fence_reg_start
; i
< dev_priv
->num_fence_regs
; i
++) {
3342 reg
= &dev_priv
->fence_regs
[i
];
3346 if (!reg
->pin_count
)
3353 /* None available, try to steal one or wait for a user to finish */
3354 list_for_each_entry(reg
, &dev_priv
->mm
.fence_list
, lru_list
) {
3362 /* Wait for completion of pending flips which consume fences */
3363 if (intel_has_pending_fb_unpin(dev
))
3364 return ERR_PTR(-EAGAIN
);
3366 return ERR_PTR(-EDEADLK
);
3370 * i915_gem_object_get_fence - set up fencing for an object
3371 * @obj: object to map through a fence reg
3373 * When mapping objects through the GTT, userspace wants to be able to write
3374 * to them without having to worry about swizzling if the object is tiled.
3375 * This function walks the fence regs looking for a free one for @obj,
3376 * stealing one if it can't find any.
3378 * It then sets up the reg based on the object's properties: address, pitch
3379 * and tiling format.
3381 * For an untiled surface, this removes any existing fence.
3384 i915_gem_object_get_fence(struct drm_i915_gem_object
*obj
)
3386 struct drm_device
*dev
= obj
->base
.dev
;
3387 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3388 bool enable
= obj
->tiling_mode
!= I915_TILING_NONE
;
3389 struct drm_i915_fence_reg
*reg
;
3392 /* Have we updated the tiling parameters upon the object and so
3393 * will need to serialise the write to the associated fence register?
3395 if (obj
->fence_dirty
) {
3396 ret
= i915_gem_object_wait_fence(obj
);
3401 /* Just update our place in the LRU if our fence is getting reused. */
3402 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
3403 reg
= &dev_priv
->fence_regs
[obj
->fence_reg
];
3404 if (!obj
->fence_dirty
) {
3405 list_move_tail(®
->lru_list
,
3406 &dev_priv
->mm
.fence_list
);
3409 } else if (enable
) {
3410 if (WARN_ON(!obj
->map_and_fenceable
))
3413 reg
= i915_find_fence_reg(dev
);
3415 return PTR_ERR(reg
);
3418 struct drm_i915_gem_object
*old
= reg
->obj
;
3420 ret
= i915_gem_object_wait_fence(old
);
3424 i915_gem_object_fence_lost(old
);
3429 i915_gem_object_update_fence(obj
, reg
, enable
);
3434 static bool i915_gem_valid_gtt_space(struct i915_vma
*vma
,
3435 unsigned long cache_level
)
3437 struct drm_mm_node
*gtt_space
= &vma
->node
;
3438 struct drm_mm_node
*other
;
3441 * On some machines we have to be careful when putting differing types
3442 * of snoopable memory together to avoid the prefetcher crossing memory
3443 * domains and dying. During vm initialisation, we decide whether or not
3444 * these constraints apply and set the drm_mm.color_adjust
3447 if (vma
->vm
->mm
.color_adjust
== NULL
)
3450 if (!drm_mm_node_allocated(gtt_space
))
3453 if (list_empty(>t_space
->node_list
))
3456 other
= list_entry(gtt_space
->node_list
.prev
, struct drm_mm_node
, node_list
);
3457 if (other
->allocated
&& !other
->hole_follows
&& other
->color
!= cache_level
)
3460 other
= list_entry(gtt_space
->node_list
.next
, struct drm_mm_node
, node_list
);
3461 if (other
->allocated
&& !gtt_space
->hole_follows
&& other
->color
!= cache_level
)
3468 * Finds free space in the GTT aperture and binds the object there.
3470 static struct i915_vma
*
3471 i915_gem_object_bind_to_vm(struct drm_i915_gem_object
*obj
,
3472 struct i915_address_space
*vm
,
3473 const struct i915_ggtt_view
*ggtt_view
,
3477 struct drm_device
*dev
= obj
->base
.dev
;
3478 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3479 u32 size
, fence_size
, fence_alignment
, unfenced_alignment
;
3480 unsigned long start
=
3481 flags
& PIN_OFFSET_BIAS
? flags
& PIN_OFFSET_MASK
: 0;
3483 flags
& PIN_MAPPABLE
? dev_priv
->gtt
.mappable_end
: vm
->total
;
3484 struct i915_vma
*vma
;
3487 if(WARN_ON(i915_is_ggtt(vm
) != !!ggtt_view
))
3488 return ERR_PTR(-EINVAL
);
3490 fence_size
= i915_gem_get_gtt_size(dev
,
3493 fence_alignment
= i915_gem_get_gtt_alignment(dev
,
3495 obj
->tiling_mode
, true);
3496 unfenced_alignment
=
3497 i915_gem_get_gtt_alignment(dev
,
3499 obj
->tiling_mode
, false);
3502 alignment
= flags
& PIN_MAPPABLE
? fence_alignment
:
3504 if (flags
& PIN_MAPPABLE
&& alignment
& (fence_alignment
- 1)) {
3505 DRM_DEBUG("Invalid object alignment requested %u\n", alignment
);
3506 return ERR_PTR(-EINVAL
);
3509 size
= flags
& PIN_MAPPABLE
? fence_size
: obj
->base
.size
;
3511 /* If the object is bigger than the entire aperture, reject it early
3512 * before evicting everything in a vain attempt to find space.
3514 if (obj
->base
.size
> end
) {
3515 DRM_DEBUG("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%lu\n",
3517 flags
& PIN_MAPPABLE
? "mappable" : "total",
3519 return ERR_PTR(-E2BIG
);
3522 ret
= i915_gem_object_get_pages(obj
);
3524 return ERR_PTR(ret
);
3526 i915_gem_object_pin_pages(obj
);
3528 vma
= ggtt_view
? i915_gem_obj_lookup_or_create_ggtt_vma(obj
, ggtt_view
) :
3529 i915_gem_obj_lookup_or_create_vma(obj
, vm
);
3535 ret
= drm_mm_insert_node_in_range_generic(&vm
->mm
, &vma
->node
,
3539 DRM_MM_SEARCH_DEFAULT
,
3540 DRM_MM_CREATE_DEFAULT
);
3542 ret
= i915_gem_evict_something(dev
, vm
, size
, alignment
,
3551 if (WARN_ON(!i915_gem_valid_gtt_space(vma
, obj
->cache_level
))) {
3553 goto err_remove_node
;
3556 ret
= i915_gem_gtt_prepare_object(obj
);
3558 goto err_remove_node
;
3560 /* allocate before insert / bind */
3561 if (vma
->vm
->allocate_va_range
) {
3562 trace_i915_va_alloc(vma
->vm
, vma
->node
.start
, vma
->node
.size
,
3563 VM_TO_TRACE_NAME(vma
->vm
));
3564 ret
= vma
->vm
->allocate_va_range(vma
->vm
,
3568 goto err_remove_node
;
3571 trace_i915_vma_bind(vma
, flags
);
3572 ret
= i915_vma_bind(vma
, obj
->cache_level
,
3573 flags
& PIN_GLOBAL
? GLOBAL_BIND
: 0);
3575 goto err_finish_gtt
;
3577 list_move_tail(&obj
->global_list
, &dev_priv
->mm
.bound_list
);
3578 list_add_tail(&vma
->mm_list
, &vm
->inactive_list
);
3583 i915_gem_gtt_finish_object(obj
);
3585 drm_mm_remove_node(&vma
->node
);
3587 i915_gem_vma_destroy(vma
);
3590 i915_gem_object_unpin_pages(obj
);
3595 i915_gem_clflush_object(struct drm_i915_gem_object
*obj
,
3598 /* If we don't have a page list set up, then we're not pinned
3599 * to GPU, and we can ignore the cache flush because it'll happen
3600 * again at bind time.
3602 if (obj
->pages
== NULL
)
3606 * Stolen memory is always coherent with the GPU as it is explicitly
3607 * marked as wc by the system, or the system is cache-coherent.
3609 if (obj
->stolen
|| obj
->phys_handle
)
3612 /* If the GPU is snooping the contents of the CPU cache,
3613 * we do not need to manually clear the CPU cache lines. However,
3614 * the caches are only snooped when the render cache is
3615 * flushed/invalidated. As we always have to emit invalidations
3616 * and flushes when moving into and out of the RENDER domain, correct
3617 * snooping behaviour occurs naturally as the result of our domain
3620 if (!force
&& cpu_cache_is_coherent(obj
->base
.dev
, obj
->cache_level
)) {
3621 obj
->cache_dirty
= true;
3625 trace_i915_gem_object_clflush(obj
);
3626 drm_clflush_sg(obj
->pages
);
3627 obj
->cache_dirty
= false;
3632 /** Flushes the GTT write domain for the object if it's dirty. */
3634 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
)
3636 uint32_t old_write_domain
;
3638 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_GTT
)
3641 /* No actual flushing is required for the GTT write domain. Writes
3642 * to it immediately go to main memory as far as we know, so there's
3643 * no chipset flush. It also doesn't land in render cache.
3645 * However, we do have to enforce the order so that all writes through
3646 * the GTT land before any writes to the device, such as updates to
3651 old_write_domain
= obj
->base
.write_domain
;
3652 obj
->base
.write_domain
= 0;
3654 intel_fb_obj_flush(obj
, false);
3656 trace_i915_gem_object_change_domain(obj
,
3657 obj
->base
.read_domains
,
3661 /** Flushes the CPU write domain for the object if it's dirty. */
3663 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
)
3665 uint32_t old_write_domain
;
3667 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
)
3670 if (i915_gem_clflush_object(obj
, obj
->pin_display
))
3671 i915_gem_chipset_flush(obj
->base
.dev
);
3673 old_write_domain
= obj
->base
.write_domain
;
3674 obj
->base
.write_domain
= 0;
3676 intel_fb_obj_flush(obj
, false);
3678 trace_i915_gem_object_change_domain(obj
,
3679 obj
->base
.read_domains
,
3684 * Moves a single object to the GTT read, and possibly write domain.
3686 * This function returns when the move is complete, including waiting on
3690 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
, bool write
)
3692 uint32_t old_write_domain
, old_read_domains
;
3693 struct i915_vma
*vma
;
3696 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_GTT
)
3699 ret
= i915_gem_object_wait_rendering(obj
, !write
);
3703 i915_gem_object_retire(obj
);
3705 /* Flush and acquire obj->pages so that we are coherent through
3706 * direct access in memory with previous cached writes through
3707 * shmemfs and that our cache domain tracking remains valid.
3708 * For example, if the obj->filp was moved to swap without us
3709 * being notified and releasing the pages, we would mistakenly
3710 * continue to assume that the obj remained out of the CPU cached
3713 ret
= i915_gem_object_get_pages(obj
);
3717 i915_gem_object_flush_cpu_write_domain(obj
);
3719 /* Serialise direct access to this object with the barriers for
3720 * coherent writes from the GPU, by effectively invalidating the
3721 * GTT domain upon first access.
3723 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
) == 0)
3726 old_write_domain
= obj
->base
.write_domain
;
3727 old_read_domains
= obj
->base
.read_domains
;
3729 /* It should now be out of any other write domains, and we can update
3730 * the domain values for our changes.
3732 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
3733 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
3735 obj
->base
.read_domains
= I915_GEM_DOMAIN_GTT
;
3736 obj
->base
.write_domain
= I915_GEM_DOMAIN_GTT
;
3741 intel_fb_obj_invalidate(obj
, NULL
, ORIGIN_GTT
);
3743 trace_i915_gem_object_change_domain(obj
,
3747 /* And bump the LRU for this access */
3748 vma
= i915_gem_obj_to_ggtt(obj
);
3749 if (vma
&& drm_mm_node_allocated(&vma
->node
) && !obj
->active
)
3750 list_move_tail(&vma
->mm_list
,
3751 &to_i915(obj
->base
.dev
)->gtt
.base
.inactive_list
);
3756 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
3757 enum i915_cache_level cache_level
)
3759 struct drm_device
*dev
= obj
->base
.dev
;
3760 struct i915_vma
*vma
, *next
;
3763 if (obj
->cache_level
== cache_level
)
3766 if (i915_gem_obj_is_pinned(obj
)) {
3767 DRM_DEBUG("can not change the cache level of pinned objects\n");
3771 list_for_each_entry_safe(vma
, next
, &obj
->vma_list
, vma_link
) {
3772 if (!i915_gem_valid_gtt_space(vma
, cache_level
)) {
3773 ret
= i915_vma_unbind(vma
);
3779 if (i915_gem_obj_bound_any(obj
)) {
3780 ret
= i915_gem_object_finish_gpu(obj
);
3784 i915_gem_object_finish_gtt(obj
);
3786 /* Before SandyBridge, you could not use tiling or fence
3787 * registers with snooped memory, so relinquish any fences
3788 * currently pointing to our region in the aperture.
3790 if (INTEL_INFO(dev
)->gen
< 6) {
3791 ret
= i915_gem_object_put_fence(obj
);
3796 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
3797 if (drm_mm_node_allocated(&vma
->node
)) {
3798 ret
= i915_vma_bind(vma
, cache_level
,
3799 vma
->bound
& GLOBAL_BIND
);
3805 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
3806 vma
->node
.color
= cache_level
;
3807 obj
->cache_level
= cache_level
;
3809 if (obj
->cache_dirty
&&
3810 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
&&
3811 cpu_write_needs_clflush(obj
)) {
3812 if (i915_gem_clflush_object(obj
, true))
3813 i915_gem_chipset_flush(obj
->base
.dev
);
3819 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
3820 struct drm_file
*file
)
3822 struct drm_i915_gem_caching
*args
= data
;
3823 struct drm_i915_gem_object
*obj
;
3826 ret
= i915_mutex_lock_interruptible(dev
);
3830 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3831 if (&obj
->base
== NULL
) {
3836 switch (obj
->cache_level
) {
3837 case I915_CACHE_LLC
:
3838 case I915_CACHE_L3_LLC
:
3839 args
->caching
= I915_CACHING_CACHED
;
3843 args
->caching
= I915_CACHING_DISPLAY
;
3847 args
->caching
= I915_CACHING_NONE
;
3851 drm_gem_object_unreference(&obj
->base
);
3853 mutex_unlock(&dev
->struct_mutex
);
3857 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
3858 struct drm_file
*file
)
3860 struct drm_i915_gem_caching
*args
= data
;
3861 struct drm_i915_gem_object
*obj
;
3862 enum i915_cache_level level
;
3865 switch (args
->caching
) {
3866 case I915_CACHING_NONE
:
3867 level
= I915_CACHE_NONE
;
3869 case I915_CACHING_CACHED
:
3870 level
= I915_CACHE_LLC
;
3872 case I915_CACHING_DISPLAY
:
3873 level
= HAS_WT(dev
) ? I915_CACHE_WT
: I915_CACHE_NONE
;
3879 ret
= i915_mutex_lock_interruptible(dev
);
3883 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3884 if (&obj
->base
== NULL
) {
3889 ret
= i915_gem_object_set_cache_level(obj
, level
);
3891 drm_gem_object_unreference(&obj
->base
);
3893 mutex_unlock(&dev
->struct_mutex
);
3897 static bool is_pin_display(struct drm_i915_gem_object
*obj
)
3899 struct i915_vma
*vma
;
3901 vma
= i915_gem_obj_to_ggtt(obj
);
3905 /* There are 2 sources that pin objects:
3906 * 1. The display engine (scanouts, sprites, cursors);
3907 * 2. Reservations for execbuffer;
3909 * We can ignore reservations as we hold the struct_mutex and
3910 * are only called outside of the reservation path.
3912 return vma
->pin_count
;
3916 * Prepare buffer for display plane (scanout, cursors, etc).
3917 * Can be called from an uninterruptible phase (modesetting) and allows
3918 * any flushes to be pipelined (for pageflips).
3921 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
3923 struct intel_engine_cs
*pipelined
,
3924 const struct i915_ggtt_view
*view
)
3926 u32 old_read_domains
, old_write_domain
;
3927 bool was_pin_display
;
3930 if (pipelined
!= i915_gem_request_get_ring(obj
->last_read_req
)) {
3931 ret
= i915_gem_object_sync(obj
, pipelined
);
3936 /* Mark the pin_display early so that we account for the
3937 * display coherency whilst setting up the cache domains.
3939 was_pin_display
= obj
->pin_display
;
3940 obj
->pin_display
= true;
3942 /* The display engine is not coherent with the LLC cache on gen6. As
3943 * a result, we make sure that the pinning that is about to occur is
3944 * done with uncached PTEs. This is lowest common denominator for all
3947 * However for gen6+, we could do better by using the GFDT bit instead
3948 * of uncaching, which would allow us to flush all the LLC-cached data
3949 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3951 ret
= i915_gem_object_set_cache_level(obj
,
3952 HAS_WT(obj
->base
.dev
) ? I915_CACHE_WT
: I915_CACHE_NONE
);
3954 goto err_unpin_display
;
3956 /* As the user may map the buffer once pinned in the display plane
3957 * (e.g. libkms for the bootup splash), we have to ensure that we
3958 * always use map_and_fenceable for all scanout buffers.
3960 ret
= i915_gem_object_ggtt_pin(obj
, view
, alignment
,
3961 view
->type
== I915_GGTT_VIEW_NORMAL
?
3964 goto err_unpin_display
;
3966 i915_gem_object_flush_cpu_write_domain(obj
);
3968 old_write_domain
= obj
->base
.write_domain
;
3969 old_read_domains
= obj
->base
.read_domains
;
3971 /* It should now be out of any other write domains, and we can update
3972 * the domain values for our changes.
3974 obj
->base
.write_domain
= 0;
3975 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
3977 trace_i915_gem_object_change_domain(obj
,
3984 WARN_ON(was_pin_display
!= is_pin_display(obj
));
3985 obj
->pin_display
= was_pin_display
;
3990 i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object
*obj
,
3991 const struct i915_ggtt_view
*view
)
3993 i915_gem_object_ggtt_unpin_view(obj
, view
);
3995 obj
->pin_display
= is_pin_display(obj
);
3999 i915_gem_object_finish_gpu(struct drm_i915_gem_object
*obj
)
4003 if ((obj
->base
.read_domains
& I915_GEM_GPU_DOMAINS
) == 0)
4006 ret
= i915_gem_object_wait_rendering(obj
, false);
4010 /* Ensure that we invalidate the GPU's caches and TLBs. */
4011 obj
->base
.read_domains
&= ~I915_GEM_GPU_DOMAINS
;
4016 * Moves a single object to the CPU read, and possibly write domain.
4018 * This function returns when the move is complete, including waiting on
4022 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
)
4024 uint32_t old_write_domain
, old_read_domains
;
4027 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_CPU
)
4030 ret
= i915_gem_object_wait_rendering(obj
, !write
);
4034 i915_gem_object_retire(obj
);
4035 i915_gem_object_flush_gtt_write_domain(obj
);
4037 old_write_domain
= obj
->base
.write_domain
;
4038 old_read_domains
= obj
->base
.read_domains
;
4040 /* Flush the CPU cache if it's still invalid. */
4041 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) == 0) {
4042 i915_gem_clflush_object(obj
, false);
4044 obj
->base
.read_domains
|= I915_GEM_DOMAIN_CPU
;
4047 /* It should now be out of any other write domains, and we can update
4048 * the domain values for our changes.
4050 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
4052 /* If we're writing through the CPU, then the GPU read domains will
4053 * need to be invalidated at next use.
4056 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
4057 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
4061 intel_fb_obj_invalidate(obj
, NULL
, ORIGIN_CPU
);
4063 trace_i915_gem_object_change_domain(obj
,
4070 /* Throttle our rendering by waiting until the ring has completed our requests
4071 * emitted over 20 msec ago.
4073 * Note that if we were to use the current jiffies each time around the loop,
4074 * we wouldn't escape the function with any frames outstanding if the time to
4075 * render a frame was over 20ms.
4077 * This should get us reasonable parallelism between CPU and GPU but also
4078 * relatively low latency when blocking on a particular request to finish.
4081 i915_gem_ring_throttle(struct drm_device
*dev
, struct drm_file
*file
)
4083 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4084 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
4085 unsigned long recent_enough
= jiffies
- msecs_to_jiffies(20);
4086 struct drm_i915_gem_request
*request
, *target
= NULL
;
4087 unsigned reset_counter
;
4090 ret
= i915_gem_wait_for_error(&dev_priv
->gpu_error
);
4094 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, false);
4098 spin_lock(&file_priv
->mm
.lock
);
4099 list_for_each_entry(request
, &file_priv
->mm
.request_list
, client_list
) {
4100 if (time_after_eq(request
->emitted_jiffies
, recent_enough
))
4105 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
4107 i915_gem_request_reference(target
);
4108 spin_unlock(&file_priv
->mm
.lock
);
4113 ret
= __i915_wait_request(target
, reset_counter
, true, NULL
, NULL
);
4115 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, 0);
4117 i915_gem_request_unreference__unlocked(target
);
4123 i915_vma_misplaced(struct i915_vma
*vma
, uint32_t alignment
, uint64_t flags
)
4125 struct drm_i915_gem_object
*obj
= vma
->obj
;
4128 vma
->node
.start
& (alignment
- 1))
4131 if (flags
& PIN_MAPPABLE
&& !obj
->map_and_fenceable
)
4134 if (flags
& PIN_OFFSET_BIAS
&&
4135 vma
->node
.start
< (flags
& PIN_OFFSET_MASK
))
4142 i915_gem_object_do_pin(struct drm_i915_gem_object
*obj
,
4143 struct i915_address_space
*vm
,
4144 const struct i915_ggtt_view
*ggtt_view
,
4148 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
4149 struct i915_vma
*vma
;
4153 if (WARN_ON(vm
== &dev_priv
->mm
.aliasing_ppgtt
->base
))
4156 if (WARN_ON(flags
& (PIN_GLOBAL
| PIN_MAPPABLE
) && !i915_is_ggtt(vm
)))
4159 if (WARN_ON((flags
& (PIN_MAPPABLE
| PIN_GLOBAL
)) == PIN_MAPPABLE
))
4162 if (WARN_ON(i915_is_ggtt(vm
) != !!ggtt_view
))
4165 vma
= ggtt_view
? i915_gem_obj_to_ggtt_view(obj
, ggtt_view
) :
4166 i915_gem_obj_to_vma(obj
, vm
);
4169 return PTR_ERR(vma
);
4172 if (WARN_ON(vma
->pin_count
== DRM_I915_GEM_OBJECT_MAX_PIN_COUNT
))
4175 if (i915_vma_misplaced(vma
, alignment
, flags
)) {
4176 unsigned long offset
;
4177 offset
= ggtt_view
? i915_gem_obj_ggtt_offset_view(obj
, ggtt_view
) :
4178 i915_gem_obj_offset(obj
, vm
);
4179 WARN(vma
->pin_count
,
4180 "bo is already pinned in %s with incorrect alignment:"
4181 " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d,"
4182 " obj->map_and_fenceable=%d\n",
4183 ggtt_view
? "ggtt" : "ppgtt",
4186 !!(flags
& PIN_MAPPABLE
),
4187 obj
->map_and_fenceable
);
4188 ret
= i915_vma_unbind(vma
);
4196 bound
= vma
? vma
->bound
: 0;
4197 if (vma
== NULL
|| !drm_mm_node_allocated(&vma
->node
)) {
4198 /* In true PPGTT, bind has possibly changed PDEs, which
4199 * means we must do a context switch before the GPU can
4200 * accurately read some of the VMAs.
4202 vma
= i915_gem_object_bind_to_vm(obj
, vm
, ggtt_view
, alignment
,
4205 return PTR_ERR(vma
);
4208 if (flags
& PIN_GLOBAL
&& !(vma
->bound
& GLOBAL_BIND
)) {
4209 ret
= i915_vma_bind(vma
, obj
->cache_level
, GLOBAL_BIND
);
4214 if ((bound
^ vma
->bound
) & GLOBAL_BIND
) {
4215 bool mappable
, fenceable
;
4216 u32 fence_size
, fence_alignment
;
4218 fence_size
= i915_gem_get_gtt_size(obj
->base
.dev
,
4221 fence_alignment
= i915_gem_get_gtt_alignment(obj
->base
.dev
,
4226 fenceable
= (vma
->node
.size
== fence_size
&&
4227 (vma
->node
.start
& (fence_alignment
- 1)) == 0);
4229 mappable
= (vma
->node
.start
+ fence_size
<=
4230 dev_priv
->gtt
.mappable_end
);
4232 obj
->map_and_fenceable
= mappable
&& fenceable
;
4235 WARN_ON(flags
& PIN_MAPPABLE
&& !obj
->map_and_fenceable
);
4238 if (flags
& PIN_MAPPABLE
)
4239 obj
->pin_mappable
|= true;
4245 i915_gem_object_pin(struct drm_i915_gem_object
*obj
,
4246 struct i915_address_space
*vm
,
4250 return i915_gem_object_do_pin(obj
, vm
,
4251 i915_is_ggtt(vm
) ? &i915_ggtt_view_normal
: NULL
,
4256 i915_gem_object_ggtt_pin(struct drm_i915_gem_object
*obj
,
4257 const struct i915_ggtt_view
*view
,
4261 if (WARN_ONCE(!view
, "no view specified"))
4264 return i915_gem_object_do_pin(obj
, i915_obj_to_ggtt(obj
), view
,
4265 alignment
, flags
| PIN_GLOBAL
);
4269 i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object
*obj
,
4270 const struct i915_ggtt_view
*view
)
4272 struct i915_vma
*vma
= i915_gem_obj_to_ggtt_view(obj
, view
);
4275 WARN_ON(vma
->pin_count
== 0);
4276 WARN_ON(!i915_gem_obj_ggtt_bound_view(obj
, view
));
4278 if (--vma
->pin_count
== 0 && view
->type
== I915_GGTT_VIEW_NORMAL
)
4279 obj
->pin_mappable
= false;
4283 i915_gem_object_pin_fence(struct drm_i915_gem_object
*obj
)
4285 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
4286 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
4287 struct i915_vma
*ggtt_vma
= i915_gem_obj_to_ggtt(obj
);
4289 WARN_ON(!ggtt_vma
||
4290 dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
>
4291 ggtt_vma
->pin_count
);
4292 dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
++;
4299 i915_gem_object_unpin_fence(struct drm_i915_gem_object
*obj
)
4301 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
4302 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
4303 WARN_ON(dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
<= 0);
4304 dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
--;
4309 i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
4310 struct drm_file
*file
)
4312 struct drm_i915_gem_busy
*args
= data
;
4313 struct drm_i915_gem_object
*obj
;
4316 ret
= i915_mutex_lock_interruptible(dev
);
4320 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
4321 if (&obj
->base
== NULL
) {
4326 /* Count all active objects as busy, even if they are currently not used
4327 * by the gpu. Users of this interface expect objects to eventually
4328 * become non-busy without any further actions, therefore emit any
4329 * necessary flushes here.
4331 ret
= i915_gem_object_flush_active(obj
);
4333 args
->busy
= obj
->active
;
4334 if (obj
->last_read_req
) {
4335 struct intel_engine_cs
*ring
;
4336 BUILD_BUG_ON(I915_NUM_RINGS
> 16);
4337 ring
= i915_gem_request_get_ring(obj
->last_read_req
);
4338 args
->busy
|= intel_ring_flag(ring
) << 16;
4341 drm_gem_object_unreference(&obj
->base
);
4343 mutex_unlock(&dev
->struct_mutex
);
4348 i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
4349 struct drm_file
*file_priv
)
4351 return i915_gem_ring_throttle(dev
, file_priv
);
4355 i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
4356 struct drm_file
*file_priv
)
4358 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4359 struct drm_i915_gem_madvise
*args
= data
;
4360 struct drm_i915_gem_object
*obj
;
4363 switch (args
->madv
) {
4364 case I915_MADV_DONTNEED
:
4365 case I915_MADV_WILLNEED
:
4371 ret
= i915_mutex_lock_interruptible(dev
);
4375 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file_priv
, args
->handle
));
4376 if (&obj
->base
== NULL
) {
4381 if (i915_gem_obj_is_pinned(obj
)) {
4387 obj
->tiling_mode
!= I915_TILING_NONE
&&
4388 dev_priv
->quirks
& QUIRK_PIN_SWIZZLED_PAGES
) {
4389 if (obj
->madv
== I915_MADV_WILLNEED
)
4390 i915_gem_object_unpin_pages(obj
);
4391 if (args
->madv
== I915_MADV_WILLNEED
)
4392 i915_gem_object_pin_pages(obj
);
4395 if (obj
->madv
!= __I915_MADV_PURGED
)
4396 obj
->madv
= args
->madv
;
4398 /* if the object is no longer attached, discard its backing storage */
4399 if (obj
->madv
== I915_MADV_DONTNEED
&& obj
->pages
== NULL
)
4400 i915_gem_object_truncate(obj
);
4402 args
->retained
= obj
->madv
!= __I915_MADV_PURGED
;
4405 drm_gem_object_unreference(&obj
->base
);
4407 mutex_unlock(&dev
->struct_mutex
);
4411 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
4412 const struct drm_i915_gem_object_ops
*ops
)
4414 INIT_LIST_HEAD(&obj
->global_list
);
4415 INIT_LIST_HEAD(&obj
->ring_list
);
4416 INIT_LIST_HEAD(&obj
->obj_exec_link
);
4417 INIT_LIST_HEAD(&obj
->vma_list
);
4418 INIT_LIST_HEAD(&obj
->batch_pool_link
);
4422 obj
->fence_reg
= I915_FENCE_REG_NONE
;
4423 obj
->madv
= I915_MADV_WILLNEED
;
4425 i915_gem_info_add_obj(obj
->base
.dev
->dev_private
, obj
->base
.size
);
4428 static const struct drm_i915_gem_object_ops i915_gem_object_ops
= {
4429 .get_pages
= i915_gem_object_get_pages_gtt
,
4430 .put_pages
= i915_gem_object_put_pages_gtt
,
4433 struct drm_i915_gem_object
*i915_gem_alloc_object(struct drm_device
*dev
,
4436 struct drm_i915_gem_object
*obj
;
4437 struct address_space
*mapping
;
4440 obj
= i915_gem_object_alloc(dev
);
4444 if (drm_gem_object_init(dev
, &obj
->base
, size
) != 0) {
4445 i915_gem_object_free(obj
);
4449 mask
= GFP_HIGHUSER
| __GFP_RECLAIMABLE
;
4450 if (IS_CRESTLINE(dev
) || IS_BROADWATER(dev
)) {
4451 /* 965gm cannot relocate objects above 4GiB. */
4452 mask
&= ~__GFP_HIGHMEM
;
4453 mask
|= __GFP_DMA32
;
4456 mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
4457 mapping_set_gfp_mask(mapping
, mask
);
4459 i915_gem_object_init(obj
, &i915_gem_object_ops
);
4461 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
4462 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
4465 /* On some devices, we can have the GPU use the LLC (the CPU
4466 * cache) for about a 10% performance improvement
4467 * compared to uncached. Graphics requests other than
4468 * display scanout are coherent with the CPU in
4469 * accessing this cache. This means in this mode we
4470 * don't need to clflush on the CPU side, and on the
4471 * GPU side we only need to flush internal caches to
4472 * get data visible to the CPU.
4474 * However, we maintain the display planes as UC, and so
4475 * need to rebind when first used as such.
4477 obj
->cache_level
= I915_CACHE_LLC
;
4479 obj
->cache_level
= I915_CACHE_NONE
;
4481 trace_i915_gem_object_create(obj
);
4486 static bool discard_backing_storage(struct drm_i915_gem_object
*obj
)
4488 /* If we are the last user of the backing storage (be it shmemfs
4489 * pages or stolen etc), we know that the pages are going to be
4490 * immediately released. In this case, we can then skip copying
4491 * back the contents from the GPU.
4494 if (obj
->madv
!= I915_MADV_WILLNEED
)
4497 if (obj
->base
.filp
== NULL
)
4500 /* At first glance, this looks racy, but then again so would be
4501 * userspace racing mmap against close. However, the first external
4502 * reference to the filp can only be obtained through the
4503 * i915_gem_mmap_ioctl() which safeguards us against the user
4504 * acquiring such a reference whilst we are in the middle of
4505 * freeing the object.
4507 return atomic_long_read(&obj
->base
.filp
->f_count
) == 1;
4510 void i915_gem_free_object(struct drm_gem_object
*gem_obj
)
4512 struct drm_i915_gem_object
*obj
= to_intel_bo(gem_obj
);
4513 struct drm_device
*dev
= obj
->base
.dev
;
4514 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4515 struct i915_vma
*vma
, *next
;
4517 intel_runtime_pm_get(dev_priv
);
4519 trace_i915_gem_object_destroy(obj
);
4521 list_for_each_entry_safe(vma
, next
, &obj
->vma_list
, vma_link
) {
4525 ret
= i915_vma_unbind(vma
);
4526 if (WARN_ON(ret
== -ERESTARTSYS
)) {
4527 bool was_interruptible
;
4529 was_interruptible
= dev_priv
->mm
.interruptible
;
4530 dev_priv
->mm
.interruptible
= false;
4532 WARN_ON(i915_vma_unbind(vma
));
4534 dev_priv
->mm
.interruptible
= was_interruptible
;
4538 /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
4539 * before progressing. */
4541 i915_gem_object_unpin_pages(obj
);
4543 WARN_ON(obj
->frontbuffer_bits
);
4545 if (obj
->pages
&& obj
->madv
== I915_MADV_WILLNEED
&&
4546 dev_priv
->quirks
& QUIRK_PIN_SWIZZLED_PAGES
&&
4547 obj
->tiling_mode
!= I915_TILING_NONE
)
4548 i915_gem_object_unpin_pages(obj
);
4550 if (WARN_ON(obj
->pages_pin_count
))
4551 obj
->pages_pin_count
= 0;
4552 if (discard_backing_storage(obj
))
4553 obj
->madv
= I915_MADV_DONTNEED
;
4554 i915_gem_object_put_pages(obj
);
4555 i915_gem_object_free_mmap_offset(obj
);
4559 if (obj
->base
.import_attach
)
4560 drm_prime_gem_destroy(&obj
->base
, NULL
);
4562 if (obj
->ops
->release
)
4563 obj
->ops
->release(obj
);
4565 drm_gem_object_release(&obj
->base
);
4566 i915_gem_info_remove_obj(dev_priv
, obj
->base
.size
);
4569 i915_gem_object_free(obj
);
4571 intel_runtime_pm_put(dev_priv
);
4574 struct i915_vma
*i915_gem_obj_to_vma(struct drm_i915_gem_object
*obj
,
4575 struct i915_address_space
*vm
)
4577 struct i915_vma
*vma
;
4578 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
) {
4579 if (i915_is_ggtt(vma
->vm
) &&
4580 vma
->ggtt_view
.type
!= I915_GGTT_VIEW_NORMAL
)
4588 struct i915_vma
*i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object
*obj
,
4589 const struct i915_ggtt_view
*view
)
4591 struct i915_address_space
*ggtt
= i915_obj_to_ggtt(obj
);
4592 struct i915_vma
*vma
;
4594 if (WARN_ONCE(!view
, "no view specified"))
4595 return ERR_PTR(-EINVAL
);
4597 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
4598 if (vma
->vm
== ggtt
&&
4599 i915_ggtt_view_equal(&vma
->ggtt_view
, view
))
4604 void i915_gem_vma_destroy(struct i915_vma
*vma
)
4606 struct i915_address_space
*vm
= NULL
;
4607 WARN_ON(vma
->node
.allocated
);
4609 /* Keep the vma as a placeholder in the execbuffer reservation lists */
4610 if (!list_empty(&vma
->exec_list
))
4615 if (!i915_is_ggtt(vm
))
4616 i915_ppgtt_put(i915_vm_to_ppgtt(vm
));
4618 list_del(&vma
->vma_link
);
4620 kmem_cache_free(to_i915(vma
->obj
->base
.dev
)->vmas
, vma
);
4624 i915_gem_stop_ringbuffers(struct drm_device
*dev
)
4626 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4627 struct intel_engine_cs
*ring
;
4630 for_each_ring(ring
, dev_priv
, i
)
4631 dev_priv
->gt
.stop_ring(ring
);
4635 i915_gem_suspend(struct drm_device
*dev
)
4637 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4640 mutex_lock(&dev
->struct_mutex
);
4641 ret
= i915_gpu_idle(dev
);
4645 i915_gem_retire_requests(dev
);
4647 i915_gem_stop_ringbuffers(dev
);
4648 mutex_unlock(&dev
->struct_mutex
);
4650 cancel_delayed_work_sync(&dev_priv
->gpu_error
.hangcheck_work
);
4651 cancel_delayed_work_sync(&dev_priv
->mm
.retire_work
);
4652 flush_delayed_work(&dev_priv
->mm
.idle_work
);
4654 /* Assert that we sucessfully flushed all the work and
4655 * reset the GPU back to its idle, low power state.
4657 WARN_ON(dev_priv
->mm
.busy
);
4662 mutex_unlock(&dev
->struct_mutex
);
4666 int i915_gem_l3_remap(struct intel_engine_cs
*ring
, int slice
)
4668 struct drm_device
*dev
= ring
->dev
;
4669 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4670 u32 reg_base
= GEN7_L3LOG_BASE
+ (slice
* 0x200);
4671 u32
*remap_info
= dev_priv
->l3_parity
.remap_info
[slice
];
4674 if (!HAS_L3_DPF(dev
) || !remap_info
)
4677 ret
= intel_ring_begin(ring
, GEN7_L3LOG_SIZE
/ 4 * 3);
4682 * Note: We do not worry about the concurrent register cacheline hang
4683 * here because no other code should access these registers other than
4684 * at initialization time.
4686 for (i
= 0; i
< GEN7_L3LOG_SIZE
; i
+= 4) {
4687 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
4688 intel_ring_emit(ring
, reg_base
+ i
);
4689 intel_ring_emit(ring
, remap_info
[i
/4]);
4692 intel_ring_advance(ring
);
4697 void i915_gem_init_swizzling(struct drm_device
*dev
)
4699 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4701 if (INTEL_INFO(dev
)->gen
< 5 ||
4702 dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_NONE
)
4705 I915_WRITE(DISP_ARB_CTL
, I915_READ(DISP_ARB_CTL
) |
4706 DISP_TILE_SURFACE_SWIZZLING
);
4711 I915_WRITE(TILECTL
, I915_READ(TILECTL
) | TILECTL_SWZCTL
);
4713 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB
));
4714 else if (IS_GEN7(dev
))
4715 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB
));
4716 else if (IS_GEN8(dev
))
4717 I915_WRITE(GAMTARBMODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW
));
4723 intel_enable_blt(struct drm_device
*dev
)
4728 /* The blitter was dysfunctional on early prototypes */
4729 if (IS_GEN6(dev
) && dev
->pdev
->revision
< 8) {
4730 DRM_INFO("BLT not supported on this pre-production hardware;"
4731 " graphics performance will be degraded.\n");
4738 static void init_unused_ring(struct drm_device
*dev
, u32 base
)
4740 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4742 I915_WRITE(RING_CTL(base
), 0);
4743 I915_WRITE(RING_HEAD(base
), 0);
4744 I915_WRITE(RING_TAIL(base
), 0);
4745 I915_WRITE(RING_START(base
), 0);
4748 static void init_unused_rings(struct drm_device
*dev
)
4751 init_unused_ring(dev
, PRB1_BASE
);
4752 init_unused_ring(dev
, SRB0_BASE
);
4753 init_unused_ring(dev
, SRB1_BASE
);
4754 init_unused_ring(dev
, SRB2_BASE
);
4755 init_unused_ring(dev
, SRB3_BASE
);
4756 } else if (IS_GEN2(dev
)) {
4757 init_unused_ring(dev
, SRB0_BASE
);
4758 init_unused_ring(dev
, SRB1_BASE
);
4759 } else if (IS_GEN3(dev
)) {
4760 init_unused_ring(dev
, PRB1_BASE
);
4761 init_unused_ring(dev
, PRB2_BASE
);
4765 int i915_gem_init_rings(struct drm_device
*dev
)
4767 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4770 ret
= intel_init_render_ring_buffer(dev
);
4775 ret
= intel_init_bsd_ring_buffer(dev
);
4777 goto cleanup_render_ring
;
4780 if (intel_enable_blt(dev
)) {
4781 ret
= intel_init_blt_ring_buffer(dev
);
4783 goto cleanup_bsd_ring
;
4786 if (HAS_VEBOX(dev
)) {
4787 ret
= intel_init_vebox_ring_buffer(dev
);
4789 goto cleanup_blt_ring
;
4792 if (HAS_BSD2(dev
)) {
4793 ret
= intel_init_bsd2_ring_buffer(dev
);
4795 goto cleanup_vebox_ring
;
4798 ret
= i915_gem_set_seqno(dev
, ((u32
)~0 - 0x1000));
4800 goto cleanup_bsd2_ring
;
4805 intel_cleanup_ring_buffer(&dev_priv
->ring
[VCS2
]);
4807 intel_cleanup_ring_buffer(&dev_priv
->ring
[VECS
]);
4809 intel_cleanup_ring_buffer(&dev_priv
->ring
[BCS
]);
4811 intel_cleanup_ring_buffer(&dev_priv
->ring
[VCS
]);
4812 cleanup_render_ring
:
4813 intel_cleanup_ring_buffer(&dev_priv
->ring
[RCS
]);
4819 i915_gem_init_hw(struct drm_device
*dev
)
4821 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4822 struct intel_engine_cs
*ring
;
4825 if (INTEL_INFO(dev
)->gen
< 6 && !intel_enable_gtt())
4828 /* Double layer security blanket, see i915_gem_init() */
4829 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
4831 if (dev_priv
->ellc_size
)
4832 I915_WRITE(HSW_IDICR
, I915_READ(HSW_IDICR
) | IDIHASHMSK(0xf));
4834 if (IS_HASWELL(dev
))
4835 I915_WRITE(MI_PREDICATE_RESULT_2
, IS_HSW_GT3(dev
) ?
4836 LOWER_SLICE_ENABLED
: LOWER_SLICE_DISABLED
);
4838 if (HAS_PCH_NOP(dev
)) {
4839 if (IS_IVYBRIDGE(dev
)) {
4840 u32 temp
= I915_READ(GEN7_MSG_CTL
);
4841 temp
&= ~(WAIT_FOR_PCH_FLR_ACK
| WAIT_FOR_PCH_RESET_ACK
);
4842 I915_WRITE(GEN7_MSG_CTL
, temp
);
4843 } else if (INTEL_INFO(dev
)->gen
>= 7) {
4844 u32 temp
= I915_READ(HSW_NDE_RSTWRN_OPT
);
4845 temp
&= ~RESET_PCH_HANDSHAKE_ENABLE
;
4846 I915_WRITE(HSW_NDE_RSTWRN_OPT
, temp
);
4850 i915_gem_init_swizzling(dev
);
4853 * At least 830 can leave some of the unused rings
4854 * "active" (ie. head != tail) after resume which
4855 * will prevent c3 entry. Makes sure all unused rings
4858 init_unused_rings(dev
);
4860 for_each_ring(ring
, dev_priv
, i
) {
4861 ret
= ring
->init_hw(ring
);
4866 for (i
= 0; i
< NUM_L3_SLICES(dev
); i
++)
4867 i915_gem_l3_remap(&dev_priv
->ring
[RCS
], i
);
4869 ret
= i915_ppgtt_init_hw(dev
);
4870 if (ret
&& ret
!= -EIO
) {
4871 DRM_ERROR("PPGTT enable failed %d\n", ret
);
4872 i915_gem_cleanup_ringbuffer(dev
);
4875 ret
= i915_gem_context_enable(dev_priv
);
4876 if (ret
&& ret
!= -EIO
) {
4877 DRM_ERROR("Context enable failed %d\n", ret
);
4878 i915_gem_cleanup_ringbuffer(dev
);
4884 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
4888 int i915_gem_init(struct drm_device
*dev
)
4890 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4893 i915
.enable_execlists
= intel_sanitize_enable_execlists(dev
,
4894 i915
.enable_execlists
);
4896 mutex_lock(&dev
->struct_mutex
);
4898 if (IS_VALLEYVIEW(dev
)) {
4899 /* VLVA0 (potential hack), BIOS isn't actually waking us */
4900 I915_WRITE(VLV_GTLC_WAKE_CTRL
, VLV_GTLC_ALLOWWAKEREQ
);
4901 if (wait_for((I915_READ(VLV_GTLC_PW_STATUS
) &
4902 VLV_GTLC_ALLOWWAKEACK
), 10))
4903 DRM_DEBUG_DRIVER("allow wake ack timed out\n");
4906 if (!i915
.enable_execlists
) {
4907 dev_priv
->gt
.execbuf_submit
= i915_gem_ringbuffer_submission
;
4908 dev_priv
->gt
.init_rings
= i915_gem_init_rings
;
4909 dev_priv
->gt
.cleanup_ring
= intel_cleanup_ring_buffer
;
4910 dev_priv
->gt
.stop_ring
= intel_stop_ring_buffer
;
4912 dev_priv
->gt
.execbuf_submit
= intel_execlists_submission
;
4913 dev_priv
->gt
.init_rings
= intel_logical_rings_init
;
4914 dev_priv
->gt
.cleanup_ring
= intel_logical_ring_cleanup
;
4915 dev_priv
->gt
.stop_ring
= intel_logical_ring_stop
;
4918 /* This is just a security blanket to placate dragons.
4919 * On some systems, we very sporadically observe that the first TLBs
4920 * used by the CS may be stale, despite us poking the TLB reset. If
4921 * we hold the forcewake during initialisation these problems
4922 * just magically go away.
4924 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
4926 ret
= i915_gem_init_userptr(dev
);
4930 i915_gem_init_global_gtt(dev
);
4932 ret
= i915_gem_context_init(dev
);
4936 ret
= dev_priv
->gt
.init_rings(dev
);
4940 ret
= i915_gem_init_hw(dev
);
4942 /* Allow ring initialisation to fail by marking the GPU as
4943 * wedged. But we only want to do this where the GPU is angry,
4944 * for all other failure, such as an allocation failure, bail.
4946 DRM_ERROR("Failed to initialize GPU, declaring it wedged\n");
4947 atomic_set_mask(I915_WEDGED
, &dev_priv
->gpu_error
.reset_counter
);
4952 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
4953 mutex_unlock(&dev
->struct_mutex
);
4959 i915_gem_cleanup_ringbuffer(struct drm_device
*dev
)
4961 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4962 struct intel_engine_cs
*ring
;
4965 for_each_ring(ring
, dev_priv
, i
)
4966 dev_priv
->gt
.cleanup_ring(ring
);
4970 init_ring_lists(struct intel_engine_cs
*ring
)
4972 INIT_LIST_HEAD(&ring
->active_list
);
4973 INIT_LIST_HEAD(&ring
->request_list
);
4976 void i915_init_vm(struct drm_i915_private
*dev_priv
,
4977 struct i915_address_space
*vm
)
4979 if (!i915_is_ggtt(vm
))
4980 drm_mm_init(&vm
->mm
, vm
->start
, vm
->total
);
4981 vm
->dev
= dev_priv
->dev
;
4982 INIT_LIST_HEAD(&vm
->active_list
);
4983 INIT_LIST_HEAD(&vm
->inactive_list
);
4984 INIT_LIST_HEAD(&vm
->global_link
);
4985 list_add_tail(&vm
->global_link
, &dev_priv
->vm_list
);
4989 i915_gem_load(struct drm_device
*dev
)
4991 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4995 kmem_cache_create("i915_gem_object",
4996 sizeof(struct drm_i915_gem_object
), 0,
5000 kmem_cache_create("i915_gem_vma",
5001 sizeof(struct i915_vma
), 0,
5004 dev_priv
->requests
=
5005 kmem_cache_create("i915_gem_request",
5006 sizeof(struct drm_i915_gem_request
), 0,
5010 INIT_LIST_HEAD(&dev_priv
->vm_list
);
5011 i915_init_vm(dev_priv
, &dev_priv
->gtt
.base
);
5013 INIT_LIST_HEAD(&dev_priv
->context_list
);
5014 INIT_LIST_HEAD(&dev_priv
->mm
.unbound_list
);
5015 INIT_LIST_HEAD(&dev_priv
->mm
.bound_list
);
5016 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
5017 for (i
= 0; i
< I915_NUM_RINGS
; i
++)
5018 init_ring_lists(&dev_priv
->ring
[i
]);
5019 for (i
= 0; i
< I915_MAX_NUM_FENCES
; i
++)
5020 INIT_LIST_HEAD(&dev_priv
->fence_regs
[i
].lru_list
);
5021 INIT_DELAYED_WORK(&dev_priv
->mm
.retire_work
,
5022 i915_gem_retire_work_handler
);
5023 INIT_DELAYED_WORK(&dev_priv
->mm
.idle_work
,
5024 i915_gem_idle_work_handler
);
5025 init_waitqueue_head(&dev_priv
->gpu_error
.reset_queue
);
5027 dev_priv
->relative_constants_mode
= I915_EXEC_CONSTANTS_REL_GENERAL
;
5029 if (INTEL_INFO(dev
)->gen
>= 7 && !IS_VALLEYVIEW(dev
))
5030 dev_priv
->num_fence_regs
= 32;
5031 else if (INTEL_INFO(dev
)->gen
>= 4 || IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
5032 dev_priv
->num_fence_regs
= 16;
5034 dev_priv
->num_fence_regs
= 8;
5036 if (intel_vgpu_active(dev
))
5037 dev_priv
->num_fence_regs
=
5038 I915_READ(vgtif_reg(avail_rs
.fence_num
));
5040 /* Initialize fence registers to zero */
5041 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
5042 i915_gem_restore_fences(dev
);
5044 i915_gem_detect_bit_6_swizzle(dev
);
5045 init_waitqueue_head(&dev_priv
->pending_flip_queue
);
5047 dev_priv
->mm
.interruptible
= true;
5049 i915_gem_shrinker_init(dev_priv
);
5051 mutex_init(&dev_priv
->fb_tracking
.lock
);
5054 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
)
5056 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
5058 /* Clean up our request list when the client is going away, so that
5059 * later retire_requests won't dereference our soon-to-be-gone
5062 spin_lock(&file_priv
->mm
.lock
);
5063 while (!list_empty(&file_priv
->mm
.request_list
)) {
5064 struct drm_i915_gem_request
*request
;
5066 request
= list_first_entry(&file_priv
->mm
.request_list
,
5067 struct drm_i915_gem_request
,
5069 list_del(&request
->client_list
);
5070 request
->file_priv
= NULL
;
5072 spin_unlock(&file_priv
->mm
.lock
);
5074 if (!list_empty(&file_priv
->rps_boost
)) {
5075 mutex_lock(&to_i915(dev
)->rps
.hw_lock
);
5076 list_del(&file_priv
->rps_boost
);
5077 mutex_unlock(&to_i915(dev
)->rps
.hw_lock
);
5081 int i915_gem_open(struct drm_device
*dev
, struct drm_file
*file
)
5083 struct drm_i915_file_private
*file_priv
;
5086 DRM_DEBUG_DRIVER("\n");
5088 file_priv
= kzalloc(sizeof(*file_priv
), GFP_KERNEL
);
5092 file
->driver_priv
= file_priv
;
5093 file_priv
->dev_priv
= dev
->dev_private
;
5094 file_priv
->file
= file
;
5095 INIT_LIST_HEAD(&file_priv
->rps_boost
);
5097 spin_lock_init(&file_priv
->mm
.lock
);
5098 INIT_LIST_HEAD(&file_priv
->mm
.request_list
);
5100 ret
= i915_gem_context_open(dev
, file
);
5108 * i915_gem_track_fb - update frontbuffer tracking
5109 * old: current GEM buffer for the frontbuffer slots
5110 * new: new GEM buffer for the frontbuffer slots
5111 * frontbuffer_bits: bitmask of frontbuffer slots
5113 * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them
5114 * from @old and setting them in @new. Both @old and @new can be NULL.
5116 void i915_gem_track_fb(struct drm_i915_gem_object
*old
,
5117 struct drm_i915_gem_object
*new,
5118 unsigned frontbuffer_bits
)
5121 WARN_ON(!mutex_is_locked(&old
->base
.dev
->struct_mutex
));
5122 WARN_ON(!(old
->frontbuffer_bits
& frontbuffer_bits
));
5123 old
->frontbuffer_bits
&= ~frontbuffer_bits
;
5127 WARN_ON(!mutex_is_locked(&new->base
.dev
->struct_mutex
));
5128 WARN_ON(new->frontbuffer_bits
& frontbuffer_bits
);
5129 new->frontbuffer_bits
|= frontbuffer_bits
;
5133 /* All the new VM stuff */
5135 i915_gem_obj_offset(struct drm_i915_gem_object
*o
,
5136 struct i915_address_space
*vm
)
5138 struct drm_i915_private
*dev_priv
= o
->base
.dev
->dev_private
;
5139 struct i915_vma
*vma
;
5141 WARN_ON(vm
== &dev_priv
->mm
.aliasing_ppgtt
->base
);
5143 list_for_each_entry(vma
, &o
->vma_list
, vma_link
) {
5144 if (i915_is_ggtt(vma
->vm
) &&
5145 vma
->ggtt_view
.type
!= I915_GGTT_VIEW_NORMAL
)
5148 return vma
->node
.start
;
5151 WARN(1, "%s vma for this object not found.\n",
5152 i915_is_ggtt(vm
) ? "global" : "ppgtt");
5157 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object
*o
,
5158 const struct i915_ggtt_view
*view
)
5160 struct i915_address_space
*ggtt
= i915_obj_to_ggtt(o
);
5161 struct i915_vma
*vma
;
5163 list_for_each_entry(vma
, &o
->vma_list
, vma_link
)
5164 if (vma
->vm
== ggtt
&&
5165 i915_ggtt_view_equal(&vma
->ggtt_view
, view
))
5166 return vma
->node
.start
;
5168 WARN(1, "global vma for this object not found.\n");
5172 bool i915_gem_obj_bound(struct drm_i915_gem_object
*o
,
5173 struct i915_address_space
*vm
)
5175 struct i915_vma
*vma
;
5177 list_for_each_entry(vma
, &o
->vma_list
, vma_link
) {
5178 if (i915_is_ggtt(vma
->vm
) &&
5179 vma
->ggtt_view
.type
!= I915_GGTT_VIEW_NORMAL
)
5181 if (vma
->vm
== vm
&& drm_mm_node_allocated(&vma
->node
))
5188 bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object
*o
,
5189 const struct i915_ggtt_view
*view
)
5191 struct i915_address_space
*ggtt
= i915_obj_to_ggtt(o
);
5192 struct i915_vma
*vma
;
5194 list_for_each_entry(vma
, &o
->vma_list
, vma_link
)
5195 if (vma
->vm
== ggtt
&&
5196 i915_ggtt_view_equal(&vma
->ggtt_view
, view
) &&
5197 drm_mm_node_allocated(&vma
->node
))
5203 bool i915_gem_obj_bound_any(struct drm_i915_gem_object
*o
)
5205 struct i915_vma
*vma
;
5207 list_for_each_entry(vma
, &o
->vma_list
, vma_link
)
5208 if (drm_mm_node_allocated(&vma
->node
))
5214 unsigned long i915_gem_obj_size(struct drm_i915_gem_object
*o
,
5215 struct i915_address_space
*vm
)
5217 struct drm_i915_private
*dev_priv
= o
->base
.dev
->dev_private
;
5218 struct i915_vma
*vma
;
5220 WARN_ON(vm
== &dev_priv
->mm
.aliasing_ppgtt
->base
);
5222 BUG_ON(list_empty(&o
->vma_list
));
5224 list_for_each_entry(vma
, &o
->vma_list
, vma_link
) {
5225 if (i915_is_ggtt(vma
->vm
) &&
5226 vma
->ggtt_view
.type
!= I915_GGTT_VIEW_NORMAL
)
5229 return vma
->node
.size
;
5234 bool i915_gem_obj_is_pinned(struct drm_i915_gem_object
*obj
)
5236 struct i915_vma
*vma
;
5237 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
) {
5238 if (i915_is_ggtt(vma
->vm
) &&
5239 vma
->ggtt_view
.type
!= I915_GGTT_VIEW_NORMAL
)
5241 if (vma
->pin_count
> 0)