2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/slab.h>
35 #include <linux/swap.h>
36 #include <linux/pci.h>
37 #include <linux/intel-gtt.h>
39 struct change_domains
{
40 uint32_t invalidate_domains
;
41 uint32_t flush_domains
;
45 static uint32_t i915_gem_get_gtt_alignment(struct drm_i915_gem_object
*obj_priv
);
46 static uint32_t i915_gem_get_gtt_size(struct drm_i915_gem_object
*obj_priv
);
48 static int i915_gem_object_flush_gpu_write_domain(struct drm_gem_object
*obj
,
50 static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object
*obj
);
51 static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object
*obj
);
52 static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object
*obj
,
54 static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object
*obj
,
57 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object
*obj
);
58 static int i915_gem_object_wait_rendering(struct drm_gem_object
*obj
,
60 static int i915_gem_object_bind_to_gtt(struct drm_gem_object
*obj
,
64 static void i915_gem_clear_fence_reg(struct drm_gem_object
*obj
);
65 static int i915_gem_phys_pwrite(struct drm_device
*dev
, struct drm_gem_object
*obj
,
66 struct drm_i915_gem_pwrite
*args
,
67 struct drm_file
*file_priv
);
68 static void i915_gem_free_object_tail(struct drm_gem_object
*obj
);
70 static int i915_gem_inactive_shrink(struct shrinker
*shrinker
,
75 /* some bookkeeping */
76 static void i915_gem_info_add_obj(struct drm_i915_private
*dev_priv
,
79 dev_priv
->mm
.object_count
++;
80 dev_priv
->mm
.object_memory
+= size
;
83 static void i915_gem_info_remove_obj(struct drm_i915_private
*dev_priv
,
86 dev_priv
->mm
.object_count
--;
87 dev_priv
->mm
.object_memory
-= size
;
90 static void i915_gem_info_add_gtt(struct drm_i915_private
*dev_priv
,
91 struct drm_i915_gem_object
*obj
)
93 dev_priv
->mm
.gtt_count
++;
94 dev_priv
->mm
.gtt_memory
+= obj
->gtt_space
->size
;
95 if (obj
->gtt_offset
< dev_priv
->mm
.gtt_mappable_end
) {
96 dev_priv
->mm
.mappable_gtt_used
+=
97 min_t(size_t, obj
->gtt_space
->size
,
98 dev_priv
->mm
.gtt_mappable_end
- obj
->gtt_offset
);
102 static void i915_gem_info_remove_gtt(struct drm_i915_private
*dev_priv
,
103 struct drm_i915_gem_object
*obj
)
105 dev_priv
->mm
.gtt_count
--;
106 dev_priv
->mm
.gtt_memory
-= obj
->gtt_space
->size
;
107 if (obj
->gtt_offset
< dev_priv
->mm
.gtt_mappable_end
) {
108 dev_priv
->mm
.mappable_gtt_used
-=
109 min_t(size_t, obj
->gtt_space
->size
,
110 dev_priv
->mm
.gtt_mappable_end
- obj
->gtt_offset
);
115 * Update the mappable working set counters. Call _only_ when there is a change
116 * in one of (pin|fault)_mappable and update *_mappable _before_ calling.
117 * @mappable: new state the changed mappable flag (either pin_ or fault_).
120 i915_gem_info_update_mappable(struct drm_i915_private
*dev_priv
,
121 struct drm_i915_gem_object
*obj
,
125 if (obj
->pin_mappable
&& obj
->fault_mappable
)
126 /* Combined state was already mappable. */
128 dev_priv
->mm
.gtt_mappable_count
++;
129 dev_priv
->mm
.gtt_mappable_memory
+= obj
->gtt_space
->size
;
131 if (obj
->pin_mappable
|| obj
->fault_mappable
)
132 /* Combined state still mappable. */
134 dev_priv
->mm
.gtt_mappable_count
--;
135 dev_priv
->mm
.gtt_mappable_memory
-= obj
->gtt_space
->size
;
139 static void i915_gem_info_add_pin(struct drm_i915_private
*dev_priv
,
140 struct drm_i915_gem_object
*obj
,
143 dev_priv
->mm
.pin_count
++;
144 dev_priv
->mm
.pin_memory
+= obj
->gtt_space
->size
;
146 obj
->pin_mappable
= true;
147 i915_gem_info_update_mappable(dev_priv
, obj
, true);
151 static void i915_gem_info_remove_pin(struct drm_i915_private
*dev_priv
,
152 struct drm_i915_gem_object
*obj
)
154 dev_priv
->mm
.pin_count
--;
155 dev_priv
->mm
.pin_memory
-= obj
->gtt_space
->size
;
156 if (obj
->pin_mappable
) {
157 obj
->pin_mappable
= false;
158 i915_gem_info_update_mappable(dev_priv
, obj
, false);
163 i915_gem_check_is_wedged(struct drm_device
*dev
)
165 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
166 struct completion
*x
= &dev_priv
->error_completion
;
170 if (!atomic_read(&dev_priv
->mm
.wedged
))
173 ret
= wait_for_completion_interruptible(x
);
177 /* Success, we reset the GPU! */
178 if (!atomic_read(&dev_priv
->mm
.wedged
))
181 /* GPU is hung, bump the completion count to account for
182 * the token we just consumed so that we never hit zero and
183 * end up waiting upon a subsequent completion event that
186 spin_lock_irqsave(&x
->wait
.lock
, flags
);
188 spin_unlock_irqrestore(&x
->wait
.lock
, flags
);
192 static int i915_mutex_lock_interruptible(struct drm_device
*dev
)
194 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
197 ret
= i915_gem_check_is_wedged(dev
);
201 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
205 if (atomic_read(&dev_priv
->mm
.wedged
)) {
206 mutex_unlock(&dev
->struct_mutex
);
210 WARN_ON(i915_verify_lists(dev
));
215 i915_gem_object_is_inactive(struct drm_i915_gem_object
*obj_priv
)
217 return obj_priv
->gtt_space
&&
219 obj_priv
->pin_count
== 0;
222 int i915_gem_do_init(struct drm_device
*dev
,
224 unsigned long mappable_end
,
227 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
230 (start
& (PAGE_SIZE
- 1)) != 0 ||
231 (end
& (PAGE_SIZE
- 1)) != 0) {
235 drm_mm_init(&dev_priv
->mm
.gtt_space
, start
,
238 dev_priv
->mm
.gtt_total
= end
- start
;
239 dev_priv
->mm
.mappable_gtt_total
= min(end
, mappable_end
) - start
;
240 dev_priv
->mm
.gtt_mappable_end
= mappable_end
;
246 i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
247 struct drm_file
*file_priv
)
249 struct drm_i915_gem_init
*args
= data
;
252 mutex_lock(&dev
->struct_mutex
);
253 ret
= i915_gem_do_init(dev
, args
->gtt_start
, args
->gtt_end
, args
->gtt_end
);
254 mutex_unlock(&dev
->struct_mutex
);
260 i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
261 struct drm_file
*file_priv
)
263 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
264 struct drm_i915_gem_get_aperture
*args
= data
;
266 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
269 mutex_lock(&dev
->struct_mutex
);
270 args
->aper_size
= dev_priv
->mm
.gtt_total
;
271 args
->aper_available_size
= args
->aper_size
- dev_priv
->mm
.pin_memory
;
272 mutex_unlock(&dev
->struct_mutex
);
279 * Creates a new mm object and returns a handle to it.
282 i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
283 struct drm_file
*file_priv
)
285 struct drm_i915_gem_create
*args
= data
;
286 struct drm_gem_object
*obj
;
290 args
->size
= roundup(args
->size
, PAGE_SIZE
);
292 /* Allocate the new object */
293 obj
= i915_gem_alloc_object(dev
, args
->size
);
297 ret
= drm_gem_handle_create(file_priv
, obj
, &handle
);
299 drm_gem_object_release(obj
);
300 i915_gem_info_remove_obj(dev
->dev_private
, obj
->size
);
305 /* drop reference from allocate - handle holds it now */
306 drm_gem_object_unreference(obj
);
307 trace_i915_gem_object_create(obj
);
309 args
->handle
= handle
;
313 static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object
*obj
)
315 drm_i915_private_t
*dev_priv
= obj
->dev
->dev_private
;
316 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
318 return dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_9_10_17
&&
319 obj_priv
->tiling_mode
!= I915_TILING_NONE
;
323 slow_shmem_copy(struct page
*dst_page
,
325 struct page
*src_page
,
329 char *dst_vaddr
, *src_vaddr
;
331 dst_vaddr
= kmap(dst_page
);
332 src_vaddr
= kmap(src_page
);
334 memcpy(dst_vaddr
+ dst_offset
, src_vaddr
+ src_offset
, length
);
341 slow_shmem_bit17_copy(struct page
*gpu_page
,
343 struct page
*cpu_page
,
348 char *gpu_vaddr
, *cpu_vaddr
;
350 /* Use the unswizzled path if this page isn't affected. */
351 if ((page_to_phys(gpu_page
) & (1 << 17)) == 0) {
353 return slow_shmem_copy(cpu_page
, cpu_offset
,
354 gpu_page
, gpu_offset
, length
);
356 return slow_shmem_copy(gpu_page
, gpu_offset
,
357 cpu_page
, cpu_offset
, length
);
360 gpu_vaddr
= kmap(gpu_page
);
361 cpu_vaddr
= kmap(cpu_page
);
363 /* Copy the data, XORing A6 with A17 (1). The user already knows he's
364 * XORing with the other bits (A9 for Y, A9 and A10 for X)
367 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
368 int this_length
= min(cacheline_end
- gpu_offset
, length
);
369 int swizzled_gpu_offset
= gpu_offset
^ 64;
372 memcpy(cpu_vaddr
+ cpu_offset
,
373 gpu_vaddr
+ swizzled_gpu_offset
,
376 memcpy(gpu_vaddr
+ swizzled_gpu_offset
,
377 cpu_vaddr
+ cpu_offset
,
380 cpu_offset
+= this_length
;
381 gpu_offset
+= this_length
;
382 length
-= this_length
;
390 * This is the fast shmem pread path, which attempts to copy_from_user directly
391 * from the backing pages of the object to the user's address space. On a
392 * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
395 i915_gem_shmem_pread_fast(struct drm_device
*dev
, struct drm_gem_object
*obj
,
396 struct drm_i915_gem_pread
*args
,
397 struct drm_file
*file_priv
)
399 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
400 struct address_space
*mapping
= obj
->filp
->f_path
.dentry
->d_inode
->i_mapping
;
403 char __user
*user_data
;
404 int page_offset
, page_length
;
406 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
409 obj_priv
= to_intel_bo(obj
);
410 offset
= args
->offset
;
417 /* Operation in this page
419 * page_offset = offset within page
420 * page_length = bytes to copy for this page
422 page_offset
= offset
& (PAGE_SIZE
-1);
423 page_length
= remain
;
424 if ((page_offset
+ remain
) > PAGE_SIZE
)
425 page_length
= PAGE_SIZE
- page_offset
;
427 page
= read_cache_page_gfp(mapping
, offset
>> PAGE_SHIFT
,
428 GFP_HIGHUSER
| __GFP_RECLAIMABLE
);
430 return PTR_ERR(page
);
432 vaddr
= kmap_atomic(page
);
433 ret
= __copy_to_user_inatomic(user_data
,
436 kunmap_atomic(vaddr
);
438 mark_page_accessed(page
);
439 page_cache_release(page
);
443 remain
-= page_length
;
444 user_data
+= page_length
;
445 offset
+= page_length
;
452 * This is the fallback shmem pread path, which allocates temporary storage
453 * in kernel space to copy_to_user into outside of the struct_mutex, so we
454 * can copy out of the object's backing pages while holding the struct mutex
455 * and not take page faults.
458 i915_gem_shmem_pread_slow(struct drm_device
*dev
, struct drm_gem_object
*obj
,
459 struct drm_i915_gem_pread
*args
,
460 struct drm_file
*file_priv
)
462 struct address_space
*mapping
= obj
->filp
->f_path
.dentry
->d_inode
->i_mapping
;
463 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
464 struct mm_struct
*mm
= current
->mm
;
465 struct page
**user_pages
;
467 loff_t offset
, pinned_pages
, i
;
468 loff_t first_data_page
, last_data_page
, num_pages
;
469 int shmem_page_offset
;
470 int data_page_index
, data_page_offset
;
473 uint64_t data_ptr
= args
->data_ptr
;
474 int do_bit17_swizzling
;
478 /* Pin the user pages containing the data. We can't fault while
479 * holding the struct mutex, yet we want to hold it while
480 * dereferencing the user data.
482 first_data_page
= data_ptr
/ PAGE_SIZE
;
483 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
484 num_pages
= last_data_page
- first_data_page
+ 1;
486 user_pages
= drm_malloc_ab(num_pages
, sizeof(struct page
*));
487 if (user_pages
== NULL
)
490 mutex_unlock(&dev
->struct_mutex
);
491 down_read(&mm
->mmap_sem
);
492 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
493 num_pages
, 1, 0, user_pages
, NULL
);
494 up_read(&mm
->mmap_sem
);
495 mutex_lock(&dev
->struct_mutex
);
496 if (pinned_pages
< num_pages
) {
501 ret
= i915_gem_object_set_cpu_read_domain_range(obj
,
507 do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
509 obj_priv
= to_intel_bo(obj
);
510 offset
= args
->offset
;
515 /* Operation in this page
517 * shmem_page_offset = offset within page in shmem file
518 * data_page_index = page number in get_user_pages return
519 * data_page_offset = offset with data_page_index page.
520 * page_length = bytes to copy for this page
522 shmem_page_offset
= offset
& ~PAGE_MASK
;
523 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
524 data_page_offset
= data_ptr
& ~PAGE_MASK
;
526 page_length
= remain
;
527 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
528 page_length
= PAGE_SIZE
- shmem_page_offset
;
529 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
530 page_length
= PAGE_SIZE
- data_page_offset
;
532 page
= read_cache_page_gfp(mapping
, offset
>> PAGE_SHIFT
,
533 GFP_HIGHUSER
| __GFP_RECLAIMABLE
);
535 return PTR_ERR(page
);
537 if (do_bit17_swizzling
) {
538 slow_shmem_bit17_copy(page
,
540 user_pages
[data_page_index
],
545 slow_shmem_copy(user_pages
[data_page_index
],
552 mark_page_accessed(page
);
553 page_cache_release(page
);
555 remain
-= page_length
;
556 data_ptr
+= page_length
;
557 offset
+= page_length
;
561 for (i
= 0; i
< pinned_pages
; i
++) {
562 SetPageDirty(user_pages
[i
]);
563 mark_page_accessed(user_pages
[i
]);
564 page_cache_release(user_pages
[i
]);
566 drm_free_large(user_pages
);
572 * Reads data from the object referenced by handle.
574 * On error, the contents of *data are undefined.
577 i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
578 struct drm_file
*file_priv
)
580 struct drm_i915_gem_pread
*args
= data
;
581 struct drm_gem_object
*obj
;
582 struct drm_i915_gem_object
*obj_priv
;
585 ret
= i915_mutex_lock_interruptible(dev
);
589 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
594 obj_priv
= to_intel_bo(obj
);
596 /* Bounds check source. */
597 if (args
->offset
> obj
->size
|| args
->size
> obj
->size
- args
->offset
) {
605 if (!access_ok(VERIFY_WRITE
,
606 (char __user
*)(uintptr_t)args
->data_ptr
,
612 ret
= fault_in_pages_writeable((char __user
*)(uintptr_t)args
->data_ptr
,
619 ret
= i915_gem_object_set_cpu_read_domain_range(obj
,
626 if (!i915_gem_object_needs_bit17_swizzle(obj
))
627 ret
= i915_gem_shmem_pread_fast(dev
, obj
, args
, file_priv
);
629 ret
= i915_gem_shmem_pread_slow(dev
, obj
, args
, file_priv
);
632 drm_gem_object_unreference(obj
);
634 mutex_unlock(&dev
->struct_mutex
);
638 /* This is the fast write path which cannot handle
639 * page faults in the source data
643 fast_user_write(struct io_mapping
*mapping
,
644 loff_t page_base
, int page_offset
,
645 char __user
*user_data
,
649 unsigned long unwritten
;
651 vaddr_atomic
= io_mapping_map_atomic_wc(mapping
, page_base
);
652 unwritten
= __copy_from_user_inatomic_nocache(vaddr_atomic
+ page_offset
,
654 io_mapping_unmap_atomic(vaddr_atomic
);
658 /* Here's the write path which can sleep for
663 slow_kernel_write(struct io_mapping
*mapping
,
664 loff_t gtt_base
, int gtt_offset
,
665 struct page
*user_page
, int user_offset
,
668 char __iomem
*dst_vaddr
;
671 dst_vaddr
= io_mapping_map_wc(mapping
, gtt_base
);
672 src_vaddr
= kmap(user_page
);
674 memcpy_toio(dst_vaddr
+ gtt_offset
,
675 src_vaddr
+ user_offset
,
679 io_mapping_unmap(dst_vaddr
);
683 * This is the fast pwrite path, where we copy the data directly from the
684 * user into the GTT, uncached.
687 i915_gem_gtt_pwrite_fast(struct drm_device
*dev
, struct drm_gem_object
*obj
,
688 struct drm_i915_gem_pwrite
*args
,
689 struct drm_file
*file_priv
)
691 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
692 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
694 loff_t offset
, page_base
;
695 char __user
*user_data
;
696 int page_offset
, page_length
;
698 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
701 obj_priv
= to_intel_bo(obj
);
702 offset
= obj_priv
->gtt_offset
+ args
->offset
;
705 /* Operation in this page
707 * page_base = page offset within aperture
708 * page_offset = offset within page
709 * page_length = bytes to copy for this page
711 page_base
= (offset
& ~(PAGE_SIZE
-1));
712 page_offset
= offset
& (PAGE_SIZE
-1);
713 page_length
= remain
;
714 if ((page_offset
+ remain
) > PAGE_SIZE
)
715 page_length
= PAGE_SIZE
- page_offset
;
717 /* If we get a fault while copying data, then (presumably) our
718 * source page isn't available. Return the error and we'll
719 * retry in the slow path.
721 if (fast_user_write(dev_priv
->mm
.gtt_mapping
, page_base
,
722 page_offset
, user_data
, page_length
))
726 remain
-= page_length
;
727 user_data
+= page_length
;
728 offset
+= page_length
;
735 * This is the fallback GTT pwrite path, which uses get_user_pages to pin
736 * the memory and maps it using kmap_atomic for copying.
738 * This code resulted in x11perf -rgb10text consuming about 10% more CPU
739 * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
742 i915_gem_gtt_pwrite_slow(struct drm_device
*dev
, struct drm_gem_object
*obj
,
743 struct drm_i915_gem_pwrite
*args
,
744 struct drm_file
*file_priv
)
746 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
747 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
749 loff_t gtt_page_base
, offset
;
750 loff_t first_data_page
, last_data_page
, num_pages
;
751 loff_t pinned_pages
, i
;
752 struct page
**user_pages
;
753 struct mm_struct
*mm
= current
->mm
;
754 int gtt_page_offset
, data_page_offset
, data_page_index
, page_length
;
756 uint64_t data_ptr
= args
->data_ptr
;
760 /* Pin the user pages containing the data. We can't fault while
761 * holding the struct mutex, and all of the pwrite implementations
762 * want to hold it while dereferencing the user data.
764 first_data_page
= data_ptr
/ PAGE_SIZE
;
765 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
766 num_pages
= last_data_page
- first_data_page
+ 1;
768 user_pages
= drm_malloc_ab(num_pages
, sizeof(struct page
*));
769 if (user_pages
== NULL
)
772 mutex_unlock(&dev
->struct_mutex
);
773 down_read(&mm
->mmap_sem
);
774 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
775 num_pages
, 0, 0, user_pages
, NULL
);
776 up_read(&mm
->mmap_sem
);
777 mutex_lock(&dev
->struct_mutex
);
778 if (pinned_pages
< num_pages
) {
780 goto out_unpin_pages
;
783 ret
= i915_gem_object_set_to_gtt_domain(obj
, 1);
785 goto out_unpin_pages
;
787 obj_priv
= to_intel_bo(obj
);
788 offset
= obj_priv
->gtt_offset
+ args
->offset
;
791 /* Operation in this page
793 * gtt_page_base = page offset within aperture
794 * gtt_page_offset = offset within page in aperture
795 * data_page_index = page number in get_user_pages return
796 * data_page_offset = offset with data_page_index page.
797 * page_length = bytes to copy for this page
799 gtt_page_base
= offset
& PAGE_MASK
;
800 gtt_page_offset
= offset
& ~PAGE_MASK
;
801 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
802 data_page_offset
= data_ptr
& ~PAGE_MASK
;
804 page_length
= remain
;
805 if ((gtt_page_offset
+ page_length
) > PAGE_SIZE
)
806 page_length
= PAGE_SIZE
- gtt_page_offset
;
807 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
808 page_length
= PAGE_SIZE
- data_page_offset
;
810 slow_kernel_write(dev_priv
->mm
.gtt_mapping
,
811 gtt_page_base
, gtt_page_offset
,
812 user_pages
[data_page_index
],
816 remain
-= page_length
;
817 offset
+= page_length
;
818 data_ptr
+= page_length
;
822 for (i
= 0; i
< pinned_pages
; i
++)
823 page_cache_release(user_pages
[i
]);
824 drm_free_large(user_pages
);
830 * This is the fast shmem pwrite path, which attempts to directly
831 * copy_from_user into the kmapped pages backing the object.
834 i915_gem_shmem_pwrite_fast(struct drm_device
*dev
, struct drm_gem_object
*obj
,
835 struct drm_i915_gem_pwrite
*args
,
836 struct drm_file
*file_priv
)
838 struct address_space
*mapping
= obj
->filp
->f_path
.dentry
->d_inode
->i_mapping
;
839 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
842 char __user
*user_data
;
843 int page_offset
, page_length
;
845 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
848 obj_priv
= to_intel_bo(obj
);
849 offset
= args
->offset
;
857 /* Operation in this page
859 * page_offset = offset within page
860 * page_length = bytes to copy for this page
862 page_offset
= offset
& (PAGE_SIZE
-1);
863 page_length
= remain
;
864 if ((page_offset
+ remain
) > PAGE_SIZE
)
865 page_length
= PAGE_SIZE
- page_offset
;
867 page
= read_cache_page_gfp(mapping
, offset
>> PAGE_SHIFT
,
868 GFP_HIGHUSER
| __GFP_RECLAIMABLE
);
870 return PTR_ERR(page
);
872 vaddr
= kmap_atomic(page
, KM_USER0
);
873 ret
= __copy_from_user_inatomic(vaddr
+ page_offset
,
876 kunmap_atomic(vaddr
, KM_USER0
);
878 set_page_dirty(page
);
879 mark_page_accessed(page
);
880 page_cache_release(page
);
882 /* If we get a fault while copying data, then (presumably) our
883 * source page isn't available. Return the error and we'll
884 * retry in the slow path.
889 remain
-= page_length
;
890 user_data
+= page_length
;
891 offset
+= page_length
;
898 * This is the fallback shmem pwrite path, which uses get_user_pages to pin
899 * the memory and maps it using kmap_atomic for copying.
901 * This avoids taking mmap_sem for faulting on the user's address while the
902 * struct_mutex is held.
905 i915_gem_shmem_pwrite_slow(struct drm_device
*dev
, struct drm_gem_object
*obj
,
906 struct drm_i915_gem_pwrite
*args
,
907 struct drm_file
*file_priv
)
909 struct address_space
*mapping
= obj
->filp
->f_path
.dentry
->d_inode
->i_mapping
;
910 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
911 struct mm_struct
*mm
= current
->mm
;
912 struct page
**user_pages
;
914 loff_t offset
, pinned_pages
, i
;
915 loff_t first_data_page
, last_data_page
, num_pages
;
916 int shmem_page_offset
;
917 int data_page_index
, data_page_offset
;
920 uint64_t data_ptr
= args
->data_ptr
;
921 int do_bit17_swizzling
;
925 /* Pin the user pages containing the data. We can't fault while
926 * holding the struct mutex, and all of the pwrite implementations
927 * want to hold it while dereferencing the user data.
929 first_data_page
= data_ptr
/ PAGE_SIZE
;
930 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
931 num_pages
= last_data_page
- first_data_page
+ 1;
933 user_pages
= drm_malloc_ab(num_pages
, sizeof(struct page
*));
934 if (user_pages
== NULL
)
937 mutex_unlock(&dev
->struct_mutex
);
938 down_read(&mm
->mmap_sem
);
939 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
940 num_pages
, 0, 0, user_pages
, NULL
);
941 up_read(&mm
->mmap_sem
);
942 mutex_lock(&dev
->struct_mutex
);
943 if (pinned_pages
< num_pages
) {
948 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
952 do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
954 obj_priv
= to_intel_bo(obj
);
955 offset
= args
->offset
;
961 /* Operation in this page
963 * shmem_page_offset = offset within page in shmem file
964 * data_page_index = page number in get_user_pages return
965 * data_page_offset = offset with data_page_index page.
966 * page_length = bytes to copy for this page
968 shmem_page_offset
= offset
& ~PAGE_MASK
;
969 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
970 data_page_offset
= data_ptr
& ~PAGE_MASK
;
972 page_length
= remain
;
973 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
974 page_length
= PAGE_SIZE
- shmem_page_offset
;
975 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
976 page_length
= PAGE_SIZE
- data_page_offset
;
978 page
= read_cache_page_gfp(mapping
, offset
>> PAGE_SHIFT
,
979 GFP_HIGHUSER
| __GFP_RECLAIMABLE
);
985 if (do_bit17_swizzling
) {
986 slow_shmem_bit17_copy(page
,
988 user_pages
[data_page_index
],
993 slow_shmem_copy(page
,
995 user_pages
[data_page_index
],
1000 set_page_dirty(page
);
1001 mark_page_accessed(page
);
1002 page_cache_release(page
);
1004 remain
-= page_length
;
1005 data_ptr
+= page_length
;
1006 offset
+= page_length
;
1010 for (i
= 0; i
< pinned_pages
; i
++)
1011 page_cache_release(user_pages
[i
]);
1012 drm_free_large(user_pages
);
1018 * Writes data to the object referenced by handle.
1020 * On error, the contents of the buffer that were to be modified are undefined.
1023 i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
1024 struct drm_file
*file
)
1026 struct drm_i915_gem_pwrite
*args
= data
;
1027 struct drm_gem_object
*obj
;
1028 struct drm_i915_gem_object
*obj_priv
;
1031 ret
= i915_mutex_lock_interruptible(dev
);
1035 obj
= drm_gem_object_lookup(dev
, file
, args
->handle
);
1040 obj_priv
= to_intel_bo(obj
);
1043 /* Bounds check destination. */
1044 if (args
->offset
> obj
->size
|| args
->size
> obj
->size
- args
->offset
) {
1049 if (args
->size
== 0)
1052 if (!access_ok(VERIFY_READ
,
1053 (char __user
*)(uintptr_t)args
->data_ptr
,
1059 ret
= fault_in_pages_readable((char __user
*)(uintptr_t)args
->data_ptr
,
1066 /* We can only do the GTT pwrite on untiled buffers, as otherwise
1067 * it would end up going through the fenced access, and we'll get
1068 * different detiling behavior between reading and writing.
1069 * pread/pwrite currently are reading and writing from the CPU
1070 * perspective, requiring manual detiling by the client.
1072 if (obj_priv
->phys_obj
)
1073 ret
= i915_gem_phys_pwrite(dev
, obj
, args
, file
);
1074 else if (obj_priv
->tiling_mode
== I915_TILING_NONE
&&
1075 obj_priv
->gtt_space
&&
1076 obj
->write_domain
!= I915_GEM_DOMAIN_CPU
) {
1077 ret
= i915_gem_object_pin(obj
, 0, true, false);
1081 ret
= i915_gem_object_set_to_gtt_domain(obj
, 1);
1085 ret
= i915_gem_gtt_pwrite_fast(dev
, obj
, args
, file
);
1087 ret
= i915_gem_gtt_pwrite_slow(dev
, obj
, args
, file
);
1090 i915_gem_object_unpin(obj
);
1092 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
1097 if (!i915_gem_object_needs_bit17_swizzle(obj
))
1098 ret
= i915_gem_shmem_pwrite_fast(dev
, obj
, args
, file
);
1100 ret
= i915_gem_shmem_pwrite_slow(dev
, obj
, args
, file
);
1104 drm_gem_object_unreference(obj
);
1106 mutex_unlock(&dev
->struct_mutex
);
1111 * Called when user space prepares to use an object with the CPU, either
1112 * through the mmap ioctl's mapping or a GTT mapping.
1115 i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
1116 struct drm_file
*file_priv
)
1118 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1119 struct drm_i915_gem_set_domain
*args
= data
;
1120 struct drm_gem_object
*obj
;
1121 struct drm_i915_gem_object
*obj_priv
;
1122 uint32_t read_domains
= args
->read_domains
;
1123 uint32_t write_domain
= args
->write_domain
;
1126 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1129 /* Only handle setting domains to types used by the CPU. */
1130 if (write_domain
& I915_GEM_GPU_DOMAINS
)
1133 if (read_domains
& I915_GEM_GPU_DOMAINS
)
1136 /* Having something in the write domain implies it's in the read
1137 * domain, and only that read domain. Enforce that in the request.
1139 if (write_domain
!= 0 && read_domains
!= write_domain
)
1142 ret
= i915_mutex_lock_interruptible(dev
);
1146 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1151 obj_priv
= to_intel_bo(obj
);
1153 intel_mark_busy(dev
, obj
);
1155 if (read_domains
& I915_GEM_DOMAIN_GTT
) {
1156 ret
= i915_gem_object_set_to_gtt_domain(obj
, write_domain
!= 0);
1158 /* Update the LRU on the fence for the CPU access that's
1161 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
) {
1162 struct drm_i915_fence_reg
*reg
=
1163 &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
1164 list_move_tail(®
->lru_list
,
1165 &dev_priv
->mm
.fence_list
);
1168 /* Silently promote "you're not bound, there was nothing to do"
1169 * to success, since the client was just asking us to
1170 * make sure everything was done.
1175 ret
= i915_gem_object_set_to_cpu_domain(obj
, write_domain
!= 0);
1178 /* Maintain LRU order of "inactive" objects */
1179 if (ret
== 0 && i915_gem_object_is_inactive(obj_priv
))
1180 list_move_tail(&obj_priv
->mm_list
, &dev_priv
->mm
.inactive_list
);
1182 drm_gem_object_unreference(obj
);
1184 mutex_unlock(&dev
->struct_mutex
);
1189 * Called when user space has done writes to this buffer
1192 i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1193 struct drm_file
*file_priv
)
1195 struct drm_i915_gem_sw_finish
*args
= data
;
1196 struct drm_gem_object
*obj
;
1199 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1202 ret
= i915_mutex_lock_interruptible(dev
);
1206 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1212 /* Pinned buffers may be scanout, so flush the cache */
1213 if (to_intel_bo(obj
)->pin_count
)
1214 i915_gem_object_flush_cpu_write_domain(obj
);
1216 drm_gem_object_unreference(obj
);
1218 mutex_unlock(&dev
->struct_mutex
);
1223 * Maps the contents of an object, returning the address it is mapped
1226 * While the mapping holds a reference on the contents of the object, it doesn't
1227 * imply a ref on the object itself.
1230 i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1231 struct drm_file
*file_priv
)
1233 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1234 struct drm_i915_gem_mmap
*args
= data
;
1235 struct drm_gem_object
*obj
;
1239 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1242 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1246 if (obj
->size
> dev_priv
->mm
.gtt_mappable_end
) {
1247 drm_gem_object_unreference_unlocked(obj
);
1251 offset
= args
->offset
;
1253 down_write(¤t
->mm
->mmap_sem
);
1254 addr
= do_mmap(obj
->filp
, 0, args
->size
,
1255 PROT_READ
| PROT_WRITE
, MAP_SHARED
,
1257 up_write(¤t
->mm
->mmap_sem
);
1258 drm_gem_object_unreference_unlocked(obj
);
1259 if (IS_ERR((void *)addr
))
1262 args
->addr_ptr
= (uint64_t) addr
;
1268 * i915_gem_fault - fault a page into the GTT
1269 * vma: VMA in question
1272 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1273 * from userspace. The fault handler takes care of binding the object to
1274 * the GTT (if needed), allocating and programming a fence register (again,
1275 * only if needed based on whether the old reg is still valid or the object
1276 * is tiled) and inserting a new PTE into the faulting process.
1278 * Note that the faulting process may involve evicting existing objects
1279 * from the GTT and/or fence registers to make room. So performance may
1280 * suffer if the GTT working set is large or there are few fence registers
1283 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
)
1285 struct drm_gem_object
*obj
= vma
->vm_private_data
;
1286 struct drm_device
*dev
= obj
->dev
;
1287 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1288 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1289 pgoff_t page_offset
;
1292 bool write
= !!(vmf
->flags
& FAULT_FLAG_WRITE
);
1294 /* We don't use vmf->pgoff since that has the fake offset */
1295 page_offset
= ((unsigned long)vmf
->virtual_address
- vma
->vm_start
) >>
1298 /* Now bind it into the GTT if needed */
1299 mutex_lock(&dev
->struct_mutex
);
1300 BUG_ON(obj_priv
->pin_count
&& !obj_priv
->pin_mappable
);
1302 if (obj_priv
->gtt_space
) {
1303 if (!obj_priv
->mappable
||
1304 (obj_priv
->tiling_mode
&& !obj_priv
->fenceable
)) {
1305 ret
= i915_gem_object_unbind(obj
);
1311 if (!obj_priv
->gtt_space
) {
1312 ret
= i915_gem_object_bind_to_gtt(obj
, 0,
1313 true, obj_priv
->tiling_mode
);
1318 ret
= i915_gem_object_set_to_gtt_domain(obj
, write
);
1322 if (!obj_priv
->fault_mappable
) {
1323 obj_priv
->fault_mappable
= true;
1324 i915_gem_info_update_mappable(dev_priv
, obj_priv
, true);
1327 /* Need a new fence register? */
1328 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
) {
1329 ret
= i915_gem_object_get_fence_reg(obj
, true);
1334 if (i915_gem_object_is_inactive(obj_priv
))
1335 list_move_tail(&obj_priv
->mm_list
, &dev_priv
->mm
.inactive_list
);
1337 pfn
= ((dev
->agp
->base
+ obj_priv
->gtt_offset
) >> PAGE_SHIFT
) +
1340 /* Finally, remap it using the new GTT offset */
1341 ret
= vm_insert_pfn(vma
, (unsigned long)vmf
->virtual_address
, pfn
);
1343 mutex_unlock(&dev
->struct_mutex
);
1348 return VM_FAULT_NOPAGE
;
1351 return VM_FAULT_OOM
;
1353 return VM_FAULT_SIGBUS
;
1358 * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1359 * @obj: obj in question
1361 * GEM memory mapping works by handing back to userspace a fake mmap offset
1362 * it can use in a subsequent mmap(2) call. The DRM core code then looks
1363 * up the object based on the offset and sets up the various memory mapping
1366 * This routine allocates and attaches a fake offset for @obj.
1369 i915_gem_create_mmap_offset(struct drm_gem_object
*obj
)
1371 struct drm_device
*dev
= obj
->dev
;
1372 struct drm_gem_mm
*mm
= dev
->mm_private
;
1373 struct drm_map_list
*list
;
1374 struct drm_local_map
*map
;
1377 /* Set the object up for mmap'ing */
1378 list
= &obj
->map_list
;
1379 list
->map
= kzalloc(sizeof(struct drm_map_list
), GFP_KERNEL
);
1384 map
->type
= _DRM_GEM
;
1385 map
->size
= obj
->size
;
1388 /* Get a DRM GEM mmap offset allocated... */
1389 list
->file_offset_node
= drm_mm_search_free(&mm
->offset_manager
,
1390 obj
->size
/ PAGE_SIZE
, 0, 0);
1391 if (!list
->file_offset_node
) {
1392 DRM_ERROR("failed to allocate offset for bo %d\n", obj
->name
);
1397 list
->file_offset_node
= drm_mm_get_block(list
->file_offset_node
,
1398 obj
->size
/ PAGE_SIZE
, 0);
1399 if (!list
->file_offset_node
) {
1404 list
->hash
.key
= list
->file_offset_node
->start
;
1405 ret
= drm_ht_insert_item(&mm
->offset_hash
, &list
->hash
);
1407 DRM_ERROR("failed to add to map hash\n");
1414 drm_mm_put_block(list
->file_offset_node
);
1423 * i915_gem_release_mmap - remove physical page mappings
1424 * @obj: obj in question
1426 * Preserve the reservation of the mmapping with the DRM core code, but
1427 * relinquish ownership of the pages back to the system.
1429 * It is vital that we remove the page mapping if we have mapped a tiled
1430 * object through the GTT and then lose the fence register due to
1431 * resource pressure. Similarly if the object has been moved out of the
1432 * aperture, than pages mapped into userspace must be revoked. Removing the
1433 * mapping will then trigger a page fault on the next user access, allowing
1434 * fixup by i915_gem_fault().
1437 i915_gem_release_mmap(struct drm_gem_object
*obj
)
1439 struct drm_device
*dev
= obj
->dev
;
1440 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1441 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1443 if (unlikely(obj
->map_list
.map
&& dev
->dev_mapping
))
1444 unmap_mapping_range(dev
->dev_mapping
,
1445 (loff_t
)obj
->map_list
.hash
.key
<<PAGE_SHIFT
,
1448 if (obj_priv
->fault_mappable
) {
1449 obj_priv
->fault_mappable
= false;
1450 i915_gem_info_update_mappable(dev_priv
, obj_priv
, false);
1455 i915_gem_free_mmap_offset(struct drm_gem_object
*obj
)
1457 struct drm_device
*dev
= obj
->dev
;
1458 struct drm_gem_mm
*mm
= dev
->mm_private
;
1459 struct drm_map_list
*list
= &obj
->map_list
;
1461 drm_ht_remove_item(&mm
->offset_hash
, &list
->hash
);
1462 drm_mm_put_block(list
->file_offset_node
);
1468 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1469 * @obj: object to check
1471 * Return the required GTT alignment for an object, taking into account
1472 * potential fence register mapping if needed.
1475 i915_gem_get_gtt_alignment(struct drm_i915_gem_object
*obj_priv
)
1477 struct drm_device
*dev
= obj_priv
->base
.dev
;
1480 * Minimum alignment is 4k (GTT page size), but might be greater
1481 * if a fence register is needed for the object.
1483 if (INTEL_INFO(dev
)->gen
>= 4 ||
1484 obj_priv
->tiling_mode
== I915_TILING_NONE
)
1488 * Previous chips need to be aligned to the size of the smallest
1489 * fence register that can contain the object.
1491 return i915_gem_get_gtt_size(obj_priv
);
1495 i915_gem_get_gtt_size(struct drm_i915_gem_object
*obj_priv
)
1497 struct drm_device
*dev
= obj_priv
->base
.dev
;
1501 * Minimum alignment is 4k (GTT page size), but might be greater
1502 * if a fence register is needed for the object.
1504 if (INTEL_INFO(dev
)->gen
>= 4)
1505 return obj_priv
->base
.size
;
1508 * Previous chips need to be aligned to the size of the smallest
1509 * fence register that can contain the object.
1511 if (INTEL_INFO(dev
)->gen
== 3)
1516 while (size
< obj_priv
->base
.size
)
1523 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1525 * @data: GTT mapping ioctl data
1526 * @file_priv: GEM object info
1528 * Simply returns the fake offset to userspace so it can mmap it.
1529 * The mmap call will end up in drm_gem_mmap(), which will set things
1530 * up so we can get faults in the handler above.
1532 * The fault handler will take care of binding the object into the GTT
1533 * (since it may have been evicted to make room for something), allocating
1534 * a fence register, and mapping the appropriate aperture address into
1538 i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
1539 struct drm_file
*file_priv
)
1541 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1542 struct drm_i915_gem_mmap_gtt
*args
= data
;
1543 struct drm_gem_object
*obj
;
1544 struct drm_i915_gem_object
*obj_priv
;
1547 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1550 ret
= i915_mutex_lock_interruptible(dev
);
1554 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1559 obj_priv
= to_intel_bo(obj
);
1561 if (obj
->size
> dev_priv
->mm
.gtt_mappable_end
) {
1566 if (obj_priv
->madv
!= I915_MADV_WILLNEED
) {
1567 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1572 if (!obj
->map_list
.map
) {
1573 ret
= i915_gem_create_mmap_offset(obj
);
1578 args
->offset
= (u64
)obj
->map_list
.hash
.key
<< PAGE_SHIFT
;
1581 drm_gem_object_unreference(obj
);
1583 mutex_unlock(&dev
->struct_mutex
);
1588 i915_gem_object_get_pages_gtt(struct drm_gem_object
*obj
,
1591 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1593 struct address_space
*mapping
;
1594 struct inode
*inode
;
1597 /* Get the list of pages out of our struct file. They'll be pinned
1598 * at this point until we release them.
1600 page_count
= obj
->size
/ PAGE_SIZE
;
1601 BUG_ON(obj_priv
->pages
!= NULL
);
1602 obj_priv
->pages
= drm_malloc_ab(page_count
, sizeof(struct page
*));
1603 if (obj_priv
->pages
== NULL
)
1606 inode
= obj
->filp
->f_path
.dentry
->d_inode
;
1607 mapping
= inode
->i_mapping
;
1608 for (i
= 0; i
< page_count
; i
++) {
1609 page
= read_cache_page_gfp(mapping
, i
,
1617 obj_priv
->pages
[i
] = page
;
1620 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
)
1621 i915_gem_object_do_bit_17_swizzle(obj
);
1627 page_cache_release(obj_priv
->pages
[i
]);
1629 drm_free_large(obj_priv
->pages
);
1630 obj_priv
->pages
= NULL
;
1631 return PTR_ERR(page
);
1635 i915_gem_object_put_pages_gtt(struct drm_gem_object
*obj
)
1637 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1638 int page_count
= obj
->size
/ PAGE_SIZE
;
1641 BUG_ON(obj_priv
->madv
== __I915_MADV_PURGED
);
1643 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
)
1644 i915_gem_object_save_bit_17_swizzle(obj
);
1646 if (obj_priv
->madv
== I915_MADV_DONTNEED
)
1647 obj_priv
->dirty
= 0;
1649 for (i
= 0; i
< page_count
; i
++) {
1650 if (obj_priv
->dirty
)
1651 set_page_dirty(obj_priv
->pages
[i
]);
1653 if (obj_priv
->madv
== I915_MADV_WILLNEED
)
1654 mark_page_accessed(obj_priv
->pages
[i
]);
1656 page_cache_release(obj_priv
->pages
[i
]);
1658 obj_priv
->dirty
= 0;
1660 drm_free_large(obj_priv
->pages
);
1661 obj_priv
->pages
= NULL
;
1665 i915_gem_next_request_seqno(struct drm_device
*dev
,
1666 struct intel_ring_buffer
*ring
)
1668 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1670 ring
->outstanding_lazy_request
= true;
1671 return dev_priv
->next_seqno
;
1675 i915_gem_object_move_to_active(struct drm_gem_object
*obj
,
1676 struct intel_ring_buffer
*ring
)
1678 struct drm_device
*dev
= obj
->dev
;
1679 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1680 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1681 uint32_t seqno
= i915_gem_next_request_seqno(dev
, ring
);
1683 BUG_ON(ring
== NULL
);
1684 obj_priv
->ring
= ring
;
1686 /* Add a reference if we're newly entering the active list. */
1687 if (!obj_priv
->active
) {
1688 drm_gem_object_reference(obj
);
1689 obj_priv
->active
= 1;
1692 /* Move from whatever list we were on to the tail of execution. */
1693 list_move_tail(&obj_priv
->mm_list
, &dev_priv
->mm
.active_list
);
1694 list_move_tail(&obj_priv
->ring_list
, &ring
->active_list
);
1695 obj_priv
->last_rendering_seqno
= seqno
;
1699 i915_gem_object_move_to_flushing(struct drm_gem_object
*obj
)
1701 struct drm_device
*dev
= obj
->dev
;
1702 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1703 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1705 BUG_ON(!obj_priv
->active
);
1706 list_move_tail(&obj_priv
->mm_list
, &dev_priv
->mm
.flushing_list
);
1707 list_del_init(&obj_priv
->ring_list
);
1708 obj_priv
->last_rendering_seqno
= 0;
1711 /* Immediately discard the backing storage */
1713 i915_gem_object_truncate(struct drm_gem_object
*obj
)
1715 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1716 struct inode
*inode
;
1718 /* Our goal here is to return as much of the memory as
1719 * is possible back to the system as we are called from OOM.
1720 * To do this we must instruct the shmfs to drop all of its
1721 * backing pages, *now*. Here we mirror the actions taken
1722 * when by shmem_delete_inode() to release the backing store.
1724 inode
= obj
->filp
->f_path
.dentry
->d_inode
;
1725 truncate_inode_pages(inode
->i_mapping
, 0);
1726 if (inode
->i_op
->truncate_range
)
1727 inode
->i_op
->truncate_range(inode
, 0, (loff_t
)-1);
1729 obj_priv
->madv
= __I915_MADV_PURGED
;
1733 i915_gem_object_is_purgeable(struct drm_i915_gem_object
*obj_priv
)
1735 return obj_priv
->madv
== I915_MADV_DONTNEED
;
1739 i915_gem_object_move_to_inactive(struct drm_gem_object
*obj
)
1741 struct drm_device
*dev
= obj
->dev
;
1742 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1743 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1745 if (obj_priv
->pin_count
!= 0)
1746 list_move_tail(&obj_priv
->mm_list
, &dev_priv
->mm
.pinned_list
);
1748 list_move_tail(&obj_priv
->mm_list
, &dev_priv
->mm
.inactive_list
);
1749 list_del_init(&obj_priv
->ring_list
);
1751 BUG_ON(!list_empty(&obj_priv
->gpu_write_list
));
1753 obj_priv
->last_rendering_seqno
= 0;
1754 obj_priv
->ring
= NULL
;
1755 if (obj_priv
->active
) {
1756 obj_priv
->active
= 0;
1757 drm_gem_object_unreference(obj
);
1759 WARN_ON(i915_verify_lists(dev
));
1763 i915_gem_process_flushing_list(struct drm_device
*dev
,
1764 uint32_t flush_domains
,
1765 struct intel_ring_buffer
*ring
)
1767 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1768 struct drm_i915_gem_object
*obj_priv
, *next
;
1770 list_for_each_entry_safe(obj_priv
, next
,
1771 &ring
->gpu_write_list
,
1773 struct drm_gem_object
*obj
= &obj_priv
->base
;
1775 if (obj
->write_domain
& flush_domains
) {
1776 uint32_t old_write_domain
= obj
->write_domain
;
1778 obj
->write_domain
= 0;
1779 list_del_init(&obj_priv
->gpu_write_list
);
1780 i915_gem_object_move_to_active(obj
, ring
);
1782 /* update the fence lru list */
1783 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
) {
1784 struct drm_i915_fence_reg
*reg
=
1785 &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
1786 list_move_tail(®
->lru_list
,
1787 &dev_priv
->mm
.fence_list
);
1790 trace_i915_gem_object_change_domain(obj
,
1798 i915_add_request(struct drm_device
*dev
,
1799 struct drm_file
*file
,
1800 struct drm_i915_gem_request
*request
,
1801 struct intel_ring_buffer
*ring
)
1803 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1804 struct drm_i915_file_private
*file_priv
= NULL
;
1809 BUG_ON(request
== NULL
);
1812 file_priv
= file
->driver_priv
;
1814 ret
= ring
->add_request(ring
, &seqno
);
1818 ring
->outstanding_lazy_request
= false;
1820 request
->seqno
= seqno
;
1821 request
->ring
= ring
;
1822 request
->emitted_jiffies
= jiffies
;
1823 was_empty
= list_empty(&ring
->request_list
);
1824 list_add_tail(&request
->list
, &ring
->request_list
);
1827 spin_lock(&file_priv
->mm
.lock
);
1828 request
->file_priv
= file_priv
;
1829 list_add_tail(&request
->client_list
,
1830 &file_priv
->mm
.request_list
);
1831 spin_unlock(&file_priv
->mm
.lock
);
1834 if (!dev_priv
->mm
.suspended
) {
1835 mod_timer(&dev_priv
->hangcheck_timer
,
1836 jiffies
+ msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD
));
1838 queue_delayed_work(dev_priv
->wq
,
1839 &dev_priv
->mm
.retire_work
, HZ
);
1845 * Command execution barrier
1847 * Ensures that all commands in the ring are finished
1848 * before signalling the CPU
1851 i915_retire_commands(struct drm_device
*dev
, struct intel_ring_buffer
*ring
)
1853 uint32_t flush_domains
= 0;
1855 /* The sampler always gets flushed on i965 (sigh) */
1856 if (INTEL_INFO(dev
)->gen
>= 4)
1857 flush_domains
|= I915_GEM_DOMAIN_SAMPLER
;
1859 ring
->flush(ring
, I915_GEM_DOMAIN_COMMAND
, flush_domains
);
1863 i915_gem_request_remove_from_client(struct drm_i915_gem_request
*request
)
1865 struct drm_i915_file_private
*file_priv
= request
->file_priv
;
1870 spin_lock(&file_priv
->mm
.lock
);
1871 list_del(&request
->client_list
);
1872 request
->file_priv
= NULL
;
1873 spin_unlock(&file_priv
->mm
.lock
);
1876 static void i915_gem_reset_ring_lists(struct drm_i915_private
*dev_priv
,
1877 struct intel_ring_buffer
*ring
)
1879 while (!list_empty(&ring
->request_list
)) {
1880 struct drm_i915_gem_request
*request
;
1882 request
= list_first_entry(&ring
->request_list
,
1883 struct drm_i915_gem_request
,
1886 list_del(&request
->list
);
1887 i915_gem_request_remove_from_client(request
);
1891 while (!list_empty(&ring
->active_list
)) {
1892 struct drm_i915_gem_object
*obj_priv
;
1894 obj_priv
= list_first_entry(&ring
->active_list
,
1895 struct drm_i915_gem_object
,
1898 obj_priv
->base
.write_domain
= 0;
1899 list_del_init(&obj_priv
->gpu_write_list
);
1900 i915_gem_object_move_to_inactive(&obj_priv
->base
);
1904 void i915_gem_reset(struct drm_device
*dev
)
1906 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1907 struct drm_i915_gem_object
*obj_priv
;
1910 i915_gem_reset_ring_lists(dev_priv
, &dev_priv
->render_ring
);
1911 i915_gem_reset_ring_lists(dev_priv
, &dev_priv
->bsd_ring
);
1912 i915_gem_reset_ring_lists(dev_priv
, &dev_priv
->blt_ring
);
1914 /* Remove anything from the flushing lists. The GPU cache is likely
1915 * to be lost on reset along with the data, so simply move the
1916 * lost bo to the inactive list.
1918 while (!list_empty(&dev_priv
->mm
.flushing_list
)) {
1919 obj_priv
= list_first_entry(&dev_priv
->mm
.flushing_list
,
1920 struct drm_i915_gem_object
,
1923 obj_priv
->base
.write_domain
= 0;
1924 list_del_init(&obj_priv
->gpu_write_list
);
1925 i915_gem_object_move_to_inactive(&obj_priv
->base
);
1928 /* Move everything out of the GPU domains to ensure we do any
1929 * necessary invalidation upon reuse.
1931 list_for_each_entry(obj_priv
,
1932 &dev_priv
->mm
.inactive_list
,
1935 obj_priv
->base
.read_domains
&= ~I915_GEM_GPU_DOMAINS
;
1938 /* The fence registers are invalidated so clear them out */
1939 for (i
= 0; i
< 16; i
++) {
1940 struct drm_i915_fence_reg
*reg
;
1942 reg
= &dev_priv
->fence_regs
[i
];
1946 i915_gem_clear_fence_reg(reg
->obj
);
1951 * This function clears the request list as sequence numbers are passed.
1954 i915_gem_retire_requests_ring(struct drm_device
*dev
,
1955 struct intel_ring_buffer
*ring
)
1957 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1960 if (!ring
->status_page
.page_addr
||
1961 list_empty(&ring
->request_list
))
1964 WARN_ON(i915_verify_lists(dev
));
1966 seqno
= ring
->get_seqno(ring
);
1967 while (!list_empty(&ring
->request_list
)) {
1968 struct drm_i915_gem_request
*request
;
1970 request
= list_first_entry(&ring
->request_list
,
1971 struct drm_i915_gem_request
,
1974 if (!i915_seqno_passed(seqno
, request
->seqno
))
1977 trace_i915_gem_request_retire(dev
, request
->seqno
);
1979 list_del(&request
->list
);
1980 i915_gem_request_remove_from_client(request
);
1984 /* Move any buffers on the active list that are no longer referenced
1985 * by the ringbuffer to the flushing/inactive lists as appropriate.
1987 while (!list_empty(&ring
->active_list
)) {
1988 struct drm_gem_object
*obj
;
1989 struct drm_i915_gem_object
*obj_priv
;
1991 obj_priv
= list_first_entry(&ring
->active_list
,
1992 struct drm_i915_gem_object
,
1995 if (!i915_seqno_passed(seqno
, obj_priv
->last_rendering_seqno
))
1998 obj
= &obj_priv
->base
;
1999 if (obj
->write_domain
!= 0)
2000 i915_gem_object_move_to_flushing(obj
);
2002 i915_gem_object_move_to_inactive(obj
);
2005 if (unlikely (dev_priv
->trace_irq_seqno
&&
2006 i915_seqno_passed(dev_priv
->trace_irq_seqno
, seqno
))) {
2007 ring
->user_irq_put(ring
);
2008 dev_priv
->trace_irq_seqno
= 0;
2011 WARN_ON(i915_verify_lists(dev
));
2015 i915_gem_retire_requests(struct drm_device
*dev
)
2017 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2019 if (!list_empty(&dev_priv
->mm
.deferred_free_list
)) {
2020 struct drm_i915_gem_object
*obj_priv
, *tmp
;
2022 /* We must be careful that during unbind() we do not
2023 * accidentally infinitely recurse into retire requests.
2025 * retire -> free -> unbind -> wait -> retire_ring
2027 list_for_each_entry_safe(obj_priv
, tmp
,
2028 &dev_priv
->mm
.deferred_free_list
,
2030 i915_gem_free_object_tail(&obj_priv
->base
);
2033 i915_gem_retire_requests_ring(dev
, &dev_priv
->render_ring
);
2034 i915_gem_retire_requests_ring(dev
, &dev_priv
->bsd_ring
);
2035 i915_gem_retire_requests_ring(dev
, &dev_priv
->blt_ring
);
2039 i915_gem_retire_work_handler(struct work_struct
*work
)
2041 drm_i915_private_t
*dev_priv
;
2042 struct drm_device
*dev
;
2044 dev_priv
= container_of(work
, drm_i915_private_t
,
2045 mm
.retire_work
.work
);
2046 dev
= dev_priv
->dev
;
2048 /* Come back later if the device is busy... */
2049 if (!mutex_trylock(&dev
->struct_mutex
)) {
2050 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, HZ
);
2054 i915_gem_retire_requests(dev
);
2056 if (!dev_priv
->mm
.suspended
&&
2057 (!list_empty(&dev_priv
->render_ring
.request_list
) ||
2058 !list_empty(&dev_priv
->bsd_ring
.request_list
) ||
2059 !list_empty(&dev_priv
->blt_ring
.request_list
)))
2060 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, HZ
);
2061 mutex_unlock(&dev
->struct_mutex
);
2065 i915_do_wait_request(struct drm_device
*dev
, uint32_t seqno
,
2066 bool interruptible
, struct intel_ring_buffer
*ring
)
2068 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2074 if (atomic_read(&dev_priv
->mm
.wedged
))
2077 if (ring
->outstanding_lazy_request
) {
2078 struct drm_i915_gem_request
*request
;
2080 request
= kzalloc(sizeof(*request
), GFP_KERNEL
);
2081 if (request
== NULL
)
2084 ret
= i915_add_request(dev
, NULL
, request
, ring
);
2090 seqno
= request
->seqno
;
2092 BUG_ON(seqno
== dev_priv
->next_seqno
);
2094 if (!i915_seqno_passed(ring
->get_seqno(ring
), seqno
)) {
2095 if (HAS_PCH_SPLIT(dev
))
2096 ier
= I915_READ(DEIER
) | I915_READ(GTIER
);
2098 ier
= I915_READ(IER
);
2100 DRM_ERROR("something (likely vbetool) disabled "
2101 "interrupts, re-enabling\n");
2102 i915_driver_irq_preinstall(dev
);
2103 i915_driver_irq_postinstall(dev
);
2106 trace_i915_gem_request_wait_begin(dev
, seqno
);
2108 ring
->waiting_seqno
= seqno
;
2109 ring
->user_irq_get(ring
);
2111 ret
= wait_event_interruptible(ring
->irq_queue
,
2112 i915_seqno_passed(ring
->get_seqno(ring
), seqno
)
2113 || atomic_read(&dev_priv
->mm
.wedged
));
2115 wait_event(ring
->irq_queue
,
2116 i915_seqno_passed(ring
->get_seqno(ring
), seqno
)
2117 || atomic_read(&dev_priv
->mm
.wedged
));
2119 ring
->user_irq_put(ring
);
2120 ring
->waiting_seqno
= 0;
2122 trace_i915_gem_request_wait_end(dev
, seqno
);
2124 if (atomic_read(&dev_priv
->mm
.wedged
))
2127 if (ret
&& ret
!= -ERESTARTSYS
)
2128 DRM_ERROR("%s returns %d (awaiting %d at %d, next %d)\n",
2129 __func__
, ret
, seqno
, ring
->get_seqno(ring
),
2130 dev_priv
->next_seqno
);
2132 /* Directly dispatch request retiring. While we have the work queue
2133 * to handle this, the waiter on a request often wants an associated
2134 * buffer to have made it to the inactive list, and we would need
2135 * a separate wait queue to handle that.
2138 i915_gem_retire_requests_ring(dev
, ring
);
2144 * Waits for a sequence number to be signaled, and cleans up the
2145 * request and object lists appropriately for that event.
2148 i915_wait_request(struct drm_device
*dev
, uint32_t seqno
,
2149 struct intel_ring_buffer
*ring
)
2151 return i915_do_wait_request(dev
, seqno
, 1, ring
);
2155 i915_gem_flush_ring(struct drm_device
*dev
,
2156 struct drm_file
*file_priv
,
2157 struct intel_ring_buffer
*ring
,
2158 uint32_t invalidate_domains
,
2159 uint32_t flush_domains
)
2161 ring
->flush(ring
, invalidate_domains
, flush_domains
);
2162 i915_gem_process_flushing_list(dev
, flush_domains
, ring
);
2166 i915_gem_flush(struct drm_device
*dev
,
2167 struct drm_file
*file_priv
,
2168 uint32_t invalidate_domains
,
2169 uint32_t flush_domains
,
2170 uint32_t flush_rings
)
2172 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2174 if (flush_domains
& I915_GEM_DOMAIN_CPU
)
2175 drm_agp_chipset_flush(dev
);
2177 if ((flush_domains
| invalidate_domains
) & I915_GEM_GPU_DOMAINS
) {
2178 if (flush_rings
& RING_RENDER
)
2179 i915_gem_flush_ring(dev
, file_priv
,
2180 &dev_priv
->render_ring
,
2181 invalidate_domains
, flush_domains
);
2182 if (flush_rings
& RING_BSD
)
2183 i915_gem_flush_ring(dev
, file_priv
,
2184 &dev_priv
->bsd_ring
,
2185 invalidate_domains
, flush_domains
);
2186 if (flush_rings
& RING_BLT
)
2187 i915_gem_flush_ring(dev
, file_priv
,
2188 &dev_priv
->blt_ring
,
2189 invalidate_domains
, flush_domains
);
2194 * Ensures that all rendering to the object has completed and the object is
2195 * safe to unbind from the GTT or access from the CPU.
2198 i915_gem_object_wait_rendering(struct drm_gem_object
*obj
,
2201 struct drm_device
*dev
= obj
->dev
;
2202 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2205 /* This function only exists to support waiting for existing rendering,
2206 * not for emitting required flushes.
2208 BUG_ON((obj
->write_domain
& I915_GEM_GPU_DOMAINS
) != 0);
2210 /* If there is rendering queued on the buffer being evicted, wait for
2213 if (obj_priv
->active
) {
2214 ret
= i915_do_wait_request(dev
,
2215 obj_priv
->last_rendering_seqno
,
2226 * Unbinds an object from the GTT aperture.
2229 i915_gem_object_unbind(struct drm_gem_object
*obj
)
2231 struct drm_device
*dev
= obj
->dev
;
2232 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2233 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2236 if (obj_priv
->gtt_space
== NULL
)
2239 if (obj_priv
->pin_count
!= 0) {
2240 DRM_ERROR("Attempting to unbind pinned buffer\n");
2244 /* blow away mappings if mapped through GTT */
2245 i915_gem_release_mmap(obj
);
2247 /* Move the object to the CPU domain to ensure that
2248 * any possible CPU writes while it's not in the GTT
2249 * are flushed when we go to remap it. This will
2250 * also ensure that all pending GPU writes are finished
2253 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
2254 if (ret
== -ERESTARTSYS
)
2256 /* Continue on if we fail due to EIO, the GPU is hung so we
2257 * should be safe and we need to cleanup or else we might
2258 * cause memory corruption through use-after-free.
2261 i915_gem_clflush_object(obj
);
2262 obj
->read_domains
= obj
->write_domain
= I915_GEM_DOMAIN_CPU
;
2265 /* release the fence reg _after_ flushing */
2266 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
)
2267 i915_gem_clear_fence_reg(obj
);
2269 drm_unbind_agp(obj_priv
->agp_mem
);
2270 drm_free_agp(obj_priv
->agp_mem
, obj
->size
/ PAGE_SIZE
);
2272 i915_gem_object_put_pages_gtt(obj
);
2274 i915_gem_info_remove_gtt(dev_priv
, obj_priv
);
2275 list_del_init(&obj_priv
->mm_list
);
2276 obj_priv
->fenceable
= true;
2277 obj_priv
->mappable
= true;
2279 drm_mm_put_block(obj_priv
->gtt_space
);
2280 obj_priv
->gtt_space
= NULL
;
2281 obj_priv
->gtt_offset
= 0;
2283 if (i915_gem_object_is_purgeable(obj_priv
))
2284 i915_gem_object_truncate(obj
);
2286 trace_i915_gem_object_unbind(obj
);
2291 static int i915_ring_idle(struct drm_device
*dev
,
2292 struct intel_ring_buffer
*ring
)
2294 if (list_empty(&ring
->gpu_write_list
) && list_empty(&ring
->active_list
))
2297 i915_gem_flush_ring(dev
, NULL
, ring
,
2298 I915_GEM_GPU_DOMAINS
, I915_GEM_GPU_DOMAINS
);
2299 return i915_wait_request(dev
,
2300 i915_gem_next_request_seqno(dev
, ring
),
2305 i915_gpu_idle(struct drm_device
*dev
)
2307 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2311 lists_empty
= (list_empty(&dev_priv
->mm
.flushing_list
) &&
2312 list_empty(&dev_priv
->mm
.active_list
));
2316 /* Flush everything onto the inactive list. */
2317 ret
= i915_ring_idle(dev
, &dev_priv
->render_ring
);
2321 ret
= i915_ring_idle(dev
, &dev_priv
->bsd_ring
);
2325 ret
= i915_ring_idle(dev
, &dev_priv
->blt_ring
);
2332 static void sandybridge_write_fence_reg(struct drm_gem_object
*obj
)
2334 struct drm_device
*dev
= obj
->dev
;
2335 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2336 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2337 u32 size
= i915_gem_get_gtt_size(obj_priv
);
2338 int regnum
= obj_priv
->fence_reg
;
2341 val
= (uint64_t)((obj_priv
->gtt_offset
+ size
- 4096) &
2343 val
|= obj_priv
->gtt_offset
& 0xfffff000;
2344 val
|= (uint64_t)((obj_priv
->stride
/ 128) - 1) <<
2345 SANDYBRIDGE_FENCE_PITCH_SHIFT
;
2347 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2348 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
2349 val
|= I965_FENCE_REG_VALID
;
2351 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0
+ (regnum
* 8), val
);
2354 static void i965_write_fence_reg(struct drm_gem_object
*obj
)
2356 struct drm_device
*dev
= obj
->dev
;
2357 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2358 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2359 u32 size
= i915_gem_get_gtt_size(obj_priv
);
2360 int regnum
= obj_priv
->fence_reg
;
2363 val
= (uint64_t)((obj_priv
->gtt_offset
+ size
- 4096) &
2365 val
|= obj_priv
->gtt_offset
& 0xfffff000;
2366 val
|= ((obj_priv
->stride
/ 128) - 1) << I965_FENCE_PITCH_SHIFT
;
2367 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2368 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
2369 val
|= I965_FENCE_REG_VALID
;
2371 I915_WRITE64(FENCE_REG_965_0
+ (regnum
* 8), val
);
2374 static void i915_write_fence_reg(struct drm_gem_object
*obj
)
2376 struct drm_device
*dev
= obj
->dev
;
2377 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2378 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2379 u32 size
= i915_gem_get_gtt_size(obj_priv
);
2380 uint32_t fence_reg
, val
, pitch_val
;
2383 if ((obj_priv
->gtt_offset
& ~I915_FENCE_START_MASK
) ||
2384 (obj_priv
->gtt_offset
& (size
- 1))) {
2385 WARN(1, "%s: object 0x%08x [fenceable? %d] not 1M or size (0x%08x) aligned [gtt_space offset=%lx, size=%lx]\n",
2386 __func__
, obj_priv
->gtt_offset
, obj_priv
->fenceable
, size
,
2387 obj_priv
->gtt_space
->start
, obj_priv
->gtt_space
->size
);
2391 if (obj_priv
->tiling_mode
== I915_TILING_Y
&&
2392 HAS_128_BYTE_Y_TILING(dev
))
2397 /* Note: pitch better be a power of two tile widths */
2398 pitch_val
= obj_priv
->stride
/ tile_width
;
2399 pitch_val
= ffs(pitch_val
) - 1;
2401 if (obj_priv
->tiling_mode
== I915_TILING_Y
&&
2402 HAS_128_BYTE_Y_TILING(dev
))
2403 WARN_ON(pitch_val
> I830_FENCE_MAX_PITCH_VAL
);
2405 WARN_ON(pitch_val
> I915_FENCE_MAX_PITCH_VAL
);
2407 val
= obj_priv
->gtt_offset
;
2408 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2409 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2410 val
|= I915_FENCE_SIZE_BITS(size
);
2411 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2412 val
|= I830_FENCE_REG_VALID
;
2414 fence_reg
= obj_priv
->fence_reg
;
2416 fence_reg
= FENCE_REG_830_0
+ fence_reg
* 4;
2418 fence_reg
= FENCE_REG_945_8
+ (fence_reg
- 8) * 4;
2419 I915_WRITE(fence_reg
, val
);
2422 static void i830_write_fence_reg(struct drm_gem_object
*obj
)
2424 struct drm_device
*dev
= obj
->dev
;
2425 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2426 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2427 u32 size
= i915_gem_get_gtt_size(obj_priv
);
2428 int regnum
= obj_priv
->fence_reg
;
2431 uint32_t fence_size_bits
;
2433 if ((obj_priv
->gtt_offset
& ~I830_FENCE_START_MASK
) ||
2434 (obj_priv
->gtt_offset
& (obj
->size
- 1))) {
2435 WARN(1, "%s: object 0x%08x not 512K or size aligned\n",
2436 __func__
, obj_priv
->gtt_offset
);
2440 pitch_val
= obj_priv
->stride
/ 128;
2441 pitch_val
= ffs(pitch_val
) - 1;
2442 WARN_ON(pitch_val
> I830_FENCE_MAX_PITCH_VAL
);
2444 val
= obj_priv
->gtt_offset
;
2445 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2446 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2447 fence_size_bits
= I830_FENCE_SIZE_BITS(size
);
2448 WARN_ON(fence_size_bits
& ~0x00000f00);
2449 val
|= fence_size_bits
;
2450 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2451 val
|= I830_FENCE_REG_VALID
;
2453 I915_WRITE(FENCE_REG_830_0
+ (regnum
* 4), val
);
2456 static int i915_find_fence_reg(struct drm_device
*dev
,
2459 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2460 struct drm_i915_fence_reg
*reg
;
2461 struct drm_i915_gem_object
*obj_priv
= NULL
;
2464 /* First try to find a free reg */
2466 for (i
= dev_priv
->fence_reg_start
; i
< dev_priv
->num_fence_regs
; i
++) {
2467 reg
= &dev_priv
->fence_regs
[i
];
2471 obj_priv
= to_intel_bo(reg
->obj
);
2472 if (!obj_priv
->pin_count
)
2479 /* None available, try to steal one or wait for a user to finish */
2480 avail
= I915_FENCE_REG_NONE
;
2481 list_for_each_entry(reg
, &dev_priv
->mm
.fence_list
,
2483 obj_priv
= to_intel_bo(reg
->obj
);
2484 if (obj_priv
->pin_count
)
2488 avail
= obj_priv
->fence_reg
;
2492 BUG_ON(avail
== I915_FENCE_REG_NONE
);
2494 /* We only have a reference on obj from the active list. put_fence_reg
2495 * might drop that one, causing a use-after-free in it. So hold a
2496 * private reference to obj like the other callers of put_fence_reg
2497 * (set_tiling ioctl) do. */
2498 drm_gem_object_reference(&obj_priv
->base
);
2499 ret
= i915_gem_object_put_fence_reg(&obj_priv
->base
, interruptible
);
2500 drm_gem_object_unreference(&obj_priv
->base
);
2508 * i915_gem_object_get_fence_reg - set up a fence reg for an object
2509 * @obj: object to map through a fence reg
2511 * When mapping objects through the GTT, userspace wants to be able to write
2512 * to them without having to worry about swizzling if the object is tiled.
2514 * This function walks the fence regs looking for a free one for @obj,
2515 * stealing one if it can't find any.
2517 * It then sets up the reg based on the object's properties: address, pitch
2518 * and tiling format.
2521 i915_gem_object_get_fence_reg(struct drm_gem_object
*obj
,
2524 struct drm_device
*dev
= obj
->dev
;
2525 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2526 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2527 struct drm_i915_fence_reg
*reg
= NULL
;
2530 /* Just update our place in the LRU if our fence is getting used. */
2531 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
) {
2532 reg
= &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
2533 list_move_tail(®
->lru_list
, &dev_priv
->mm
.fence_list
);
2537 switch (obj_priv
->tiling_mode
) {
2538 case I915_TILING_NONE
:
2539 WARN(1, "allocating a fence for non-tiled object?\n");
2542 if (!obj_priv
->stride
)
2544 WARN((obj_priv
->stride
& (512 - 1)),
2545 "object 0x%08x is X tiled but has non-512B pitch\n",
2546 obj_priv
->gtt_offset
);
2549 if (!obj_priv
->stride
)
2551 WARN((obj_priv
->stride
& (128 - 1)),
2552 "object 0x%08x is Y tiled but has non-128B pitch\n",
2553 obj_priv
->gtt_offset
);
2557 ret
= i915_find_fence_reg(dev
, interruptible
);
2561 obj_priv
->fence_reg
= ret
;
2562 reg
= &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
2563 list_add_tail(®
->lru_list
, &dev_priv
->mm
.fence_list
);
2567 switch (INTEL_INFO(dev
)->gen
) {
2569 sandybridge_write_fence_reg(obj
);
2573 i965_write_fence_reg(obj
);
2576 i915_write_fence_reg(obj
);
2579 i830_write_fence_reg(obj
);
2583 trace_i915_gem_object_get_fence(obj
,
2584 obj_priv
->fence_reg
,
2585 obj_priv
->tiling_mode
);
2591 * i915_gem_clear_fence_reg - clear out fence register info
2592 * @obj: object to clear
2594 * Zeroes out the fence register itself and clears out the associated
2595 * data structures in dev_priv and obj_priv.
2598 i915_gem_clear_fence_reg(struct drm_gem_object
*obj
)
2600 struct drm_device
*dev
= obj
->dev
;
2601 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2602 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2603 struct drm_i915_fence_reg
*reg
=
2604 &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
2607 switch (INTEL_INFO(dev
)->gen
) {
2609 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0
+
2610 (obj_priv
->fence_reg
* 8), 0);
2614 I915_WRITE64(FENCE_REG_965_0
+ (obj_priv
->fence_reg
* 8), 0);
2617 if (obj_priv
->fence_reg
>= 8)
2618 fence_reg
= FENCE_REG_945_8
+ (obj_priv
->fence_reg
- 8) * 4;
2621 fence_reg
= FENCE_REG_830_0
+ obj_priv
->fence_reg
* 4;
2623 I915_WRITE(fence_reg
, 0);
2628 obj_priv
->fence_reg
= I915_FENCE_REG_NONE
;
2629 list_del_init(®
->lru_list
);
2633 * i915_gem_object_put_fence_reg - waits on outstanding fenced access
2634 * to the buffer to finish, and then resets the fence register.
2635 * @obj: tiled object holding a fence register.
2636 * @bool: whether the wait upon the fence is interruptible
2638 * Zeroes out the fence register itself and clears out the associated
2639 * data structures in dev_priv and obj_priv.
2642 i915_gem_object_put_fence_reg(struct drm_gem_object
*obj
,
2645 struct drm_device
*dev
= obj
->dev
;
2646 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2647 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2648 struct drm_i915_fence_reg
*reg
;
2650 if (obj_priv
->fence_reg
== I915_FENCE_REG_NONE
)
2653 /* If we've changed tiling, GTT-mappings of the object
2654 * need to re-fault to ensure that the correct fence register
2655 * setup is in place.
2657 i915_gem_release_mmap(obj
);
2659 /* On the i915, GPU access to tiled buffers is via a fence,
2660 * therefore we must wait for any outstanding access to complete
2661 * before clearing the fence.
2663 reg
= &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
2667 ret
= i915_gem_object_flush_gpu_write_domain(obj
, true);
2671 ret
= i915_gem_object_wait_rendering(obj
, interruptible
);
2678 i915_gem_object_flush_gtt_write_domain(obj
);
2679 i915_gem_clear_fence_reg(obj
);
2685 * Finds free space in the GTT aperture and binds the object there.
2688 i915_gem_object_bind_to_gtt(struct drm_gem_object
*obj
,
2693 struct drm_device
*dev
= obj
->dev
;
2694 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2695 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2696 struct drm_mm_node
*free_space
;
2697 gfp_t gfpmask
= __GFP_NORETRY
| __GFP_NOWARN
;
2698 u32 size
, fence_size
, fence_alignment
;
2701 if (obj_priv
->madv
!= I915_MADV_WILLNEED
) {
2702 DRM_ERROR("Attempting to bind a purgeable object\n");
2706 fence_size
= i915_gem_get_gtt_size(obj_priv
);
2707 fence_alignment
= i915_gem_get_gtt_alignment(obj_priv
);
2710 alignment
= need_fence
? fence_alignment
: 4096;
2711 if (need_fence
&& alignment
& (fence_alignment
- 1)) {
2712 DRM_ERROR("Invalid object alignment requested %u\n", alignment
);
2716 size
= need_fence
? fence_size
: obj
->size
;
2718 /* If the object is bigger than the entire aperture, reject it early
2719 * before evicting everything in a vain attempt to find space.
2722 (mappable
? dev_priv
->mm
.gtt_mappable_end
: dev_priv
->mm
.gtt_total
)) {
2723 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2730 drm_mm_search_free_in_range(&dev_priv
->mm
.gtt_space
,
2732 dev_priv
->mm
.gtt_mappable_end
,
2735 free_space
= drm_mm_search_free(&dev_priv
->mm
.gtt_space
,
2736 size
, alignment
, 0);
2738 if (free_space
!= NULL
) {
2740 obj_priv
->gtt_space
=
2741 drm_mm_get_block_range_generic(free_space
,
2743 dev_priv
->mm
.gtt_mappable_end
,
2746 obj_priv
->gtt_space
=
2747 drm_mm_get_block(free_space
, size
, alignment
);
2749 if (obj_priv
->gtt_space
== NULL
) {
2750 /* If the gtt is empty and we're still having trouble
2751 * fitting our object in, we're out of memory.
2753 ret
= i915_gem_evict_something(dev
, size
, alignment
, mappable
);
2760 ret
= i915_gem_object_get_pages_gtt(obj
, gfpmask
);
2762 drm_mm_put_block(obj_priv
->gtt_space
);
2763 obj_priv
->gtt_space
= NULL
;
2765 if (ret
== -ENOMEM
) {
2766 /* first try to clear up some space from the GTT */
2767 ret
= i915_gem_evict_something(dev
, size
,
2768 alignment
, mappable
);
2770 /* now try to shrink everyone else */
2785 /* Create an AGP memory structure pointing at our pages, and bind it
2788 obj_priv
->agp_mem
= drm_agp_bind_pages(dev
,
2790 obj
->size
>> PAGE_SHIFT
,
2791 obj_priv
->gtt_space
->start
,
2792 obj_priv
->agp_type
);
2793 if (obj_priv
->agp_mem
== NULL
) {
2794 i915_gem_object_put_pages_gtt(obj
);
2795 drm_mm_put_block(obj_priv
->gtt_space
);
2796 obj_priv
->gtt_space
= NULL
;
2798 ret
= i915_gem_evict_something(dev
, size
,
2799 alignment
, mappable
);
2806 obj_priv
->gtt_offset
= obj_priv
->gtt_space
->start
;
2808 /* keep track of bounds object by adding it to the inactive list */
2809 list_add_tail(&obj_priv
->mm_list
, &dev_priv
->mm
.inactive_list
);
2810 i915_gem_info_add_gtt(dev_priv
, obj_priv
);
2812 /* Assert that the object is not currently in any GPU domain. As it
2813 * wasn't in the GTT, there shouldn't be any way it could have been in
2816 BUG_ON(obj
->read_domains
& I915_GEM_GPU_DOMAINS
);
2817 BUG_ON(obj
->write_domain
& I915_GEM_GPU_DOMAINS
);
2819 trace_i915_gem_object_bind(obj
, obj_priv
->gtt_offset
, mappable
);
2821 obj_priv
->fenceable
=
2822 obj_priv
->gtt_space
->size
== fence_size
&&
2823 (obj_priv
->gtt_space
->start
& (fence_alignment
-1)) == 0;
2825 obj_priv
->mappable
=
2826 obj_priv
->gtt_offset
+ obj
->size
<= dev_priv
->mm
.gtt_mappable_end
;
2832 i915_gem_clflush_object(struct drm_gem_object
*obj
)
2834 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2836 /* If we don't have a page list set up, then we're not pinned
2837 * to GPU, and we can ignore the cache flush because it'll happen
2838 * again at bind time.
2840 if (obj_priv
->pages
== NULL
)
2843 trace_i915_gem_object_clflush(obj
);
2845 drm_clflush_pages(obj_priv
->pages
, obj
->size
/ PAGE_SIZE
);
2848 /** Flushes any GPU write domain for the object if it's dirty. */
2850 i915_gem_object_flush_gpu_write_domain(struct drm_gem_object
*obj
,
2853 struct drm_device
*dev
= obj
->dev
;
2855 if ((obj
->write_domain
& I915_GEM_GPU_DOMAINS
) == 0)
2858 /* Queue the GPU write cache flushing we need. */
2859 i915_gem_flush_ring(dev
, NULL
,
2860 to_intel_bo(obj
)->ring
,
2861 0, obj
->write_domain
);
2862 BUG_ON(obj
->write_domain
);
2867 return i915_gem_object_wait_rendering(obj
, true);
2870 /** Flushes the GTT write domain for the object if it's dirty. */
2872 i915_gem_object_flush_gtt_write_domain(struct drm_gem_object
*obj
)
2874 uint32_t old_write_domain
;
2876 if (obj
->write_domain
!= I915_GEM_DOMAIN_GTT
)
2879 /* No actual flushing is required for the GTT write domain. Writes
2880 * to it immediately go to main memory as far as we know, so there's
2881 * no chipset flush. It also doesn't land in render cache.
2883 i915_gem_release_mmap(obj
);
2885 old_write_domain
= obj
->write_domain
;
2886 obj
->write_domain
= 0;
2888 trace_i915_gem_object_change_domain(obj
,
2893 /** Flushes the CPU write domain for the object if it's dirty. */
2895 i915_gem_object_flush_cpu_write_domain(struct drm_gem_object
*obj
)
2897 struct drm_device
*dev
= obj
->dev
;
2898 uint32_t old_write_domain
;
2900 if (obj
->write_domain
!= I915_GEM_DOMAIN_CPU
)
2903 i915_gem_clflush_object(obj
);
2904 drm_agp_chipset_flush(dev
);
2905 old_write_domain
= obj
->write_domain
;
2906 obj
->write_domain
= 0;
2908 trace_i915_gem_object_change_domain(obj
,
2914 * Moves a single object to the GTT read, and possibly write domain.
2916 * This function returns when the move is complete, including waiting on
2920 i915_gem_object_set_to_gtt_domain(struct drm_gem_object
*obj
, int write
)
2922 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2923 uint32_t old_write_domain
, old_read_domains
;
2926 /* Not valid to be called on unbound objects. */
2927 if (obj_priv
->gtt_space
== NULL
)
2930 ret
= i915_gem_object_flush_gpu_write_domain(obj
, false);
2934 i915_gem_object_flush_cpu_write_domain(obj
);
2937 ret
= i915_gem_object_wait_rendering(obj
, true);
2942 old_write_domain
= obj
->write_domain
;
2943 old_read_domains
= obj
->read_domains
;
2945 /* It should now be out of any other write domains, and we can update
2946 * the domain values for our changes.
2948 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
2949 obj
->read_domains
|= I915_GEM_DOMAIN_GTT
;
2951 obj
->read_domains
= I915_GEM_DOMAIN_GTT
;
2952 obj
->write_domain
= I915_GEM_DOMAIN_GTT
;
2953 obj_priv
->dirty
= 1;
2956 trace_i915_gem_object_change_domain(obj
,
2964 * Prepare buffer for display plane. Use uninterruptible for possible flush
2965 * wait, as in modesetting process we're not supposed to be interrupted.
2968 i915_gem_object_set_to_display_plane(struct drm_gem_object
*obj
,
2971 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2972 uint32_t old_read_domains
;
2975 /* Not valid to be called on unbound objects. */
2976 if (obj_priv
->gtt_space
== NULL
)
2979 ret
= i915_gem_object_flush_gpu_write_domain(obj
, true);
2983 /* Currently, we are always called from an non-interruptible context. */
2985 ret
= i915_gem_object_wait_rendering(obj
, false);
2990 i915_gem_object_flush_cpu_write_domain(obj
);
2992 old_read_domains
= obj
->read_domains
;
2993 obj
->read_domains
|= I915_GEM_DOMAIN_GTT
;
2995 trace_i915_gem_object_change_domain(obj
,
3003 * Moves a single object to the CPU read, and possibly write domain.
3005 * This function returns when the move is complete, including waiting on
3009 i915_gem_object_set_to_cpu_domain(struct drm_gem_object
*obj
, int write
)
3011 uint32_t old_write_domain
, old_read_domains
;
3014 ret
= i915_gem_object_flush_gpu_write_domain(obj
, false);
3018 i915_gem_object_flush_gtt_write_domain(obj
);
3020 /* If we have a partially-valid cache of the object in the CPU,
3021 * finish invalidating it and free the per-page flags.
3023 i915_gem_object_set_to_full_cpu_read_domain(obj
);
3026 ret
= i915_gem_object_wait_rendering(obj
, true);
3031 old_write_domain
= obj
->write_domain
;
3032 old_read_domains
= obj
->read_domains
;
3034 /* Flush the CPU cache if it's still invalid. */
3035 if ((obj
->read_domains
& I915_GEM_DOMAIN_CPU
) == 0) {
3036 i915_gem_clflush_object(obj
);
3038 obj
->read_domains
|= I915_GEM_DOMAIN_CPU
;
3041 /* It should now be out of any other write domains, and we can update
3042 * the domain values for our changes.
3044 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
3046 /* If we're writing through the CPU, then the GPU read domains will
3047 * need to be invalidated at next use.
3050 obj
->read_domains
= I915_GEM_DOMAIN_CPU
;
3051 obj
->write_domain
= I915_GEM_DOMAIN_CPU
;
3054 trace_i915_gem_object_change_domain(obj
,
3062 * Set the next domain for the specified object. This
3063 * may not actually perform the necessary flushing/invaliding though,
3064 * as that may want to be batched with other set_domain operations
3066 * This is (we hope) the only really tricky part of gem. The goal
3067 * is fairly simple -- track which caches hold bits of the object
3068 * and make sure they remain coherent. A few concrete examples may
3069 * help to explain how it works. For shorthand, we use the notation
3070 * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
3071 * a pair of read and write domain masks.
3073 * Case 1: the batch buffer
3079 * 5. Unmapped from GTT
3082 * Let's take these a step at a time
3085 * Pages allocated from the kernel may still have
3086 * cache contents, so we set them to (CPU, CPU) always.
3087 * 2. Written by CPU (using pwrite)
3088 * The pwrite function calls set_domain (CPU, CPU) and
3089 * this function does nothing (as nothing changes)
3091 * This function asserts that the object is not
3092 * currently in any GPU-based read or write domains
3094 * i915_gem_execbuffer calls set_domain (COMMAND, 0).
3095 * As write_domain is zero, this function adds in the
3096 * current read domains (CPU+COMMAND, 0).
3097 * flush_domains is set to CPU.
3098 * invalidate_domains is set to COMMAND
3099 * clflush is run to get data out of the CPU caches
3100 * then i915_dev_set_domain calls i915_gem_flush to
3101 * emit an MI_FLUSH and drm_agp_chipset_flush
3102 * 5. Unmapped from GTT
3103 * i915_gem_object_unbind calls set_domain (CPU, CPU)
3104 * flush_domains and invalidate_domains end up both zero
3105 * so no flushing/invalidating happens
3109 * Case 2: The shared render buffer
3113 * 3. Read/written by GPU
3114 * 4. set_domain to (CPU,CPU)
3115 * 5. Read/written by CPU
3116 * 6. Read/written by GPU
3119 * Same as last example, (CPU, CPU)
3121 * Nothing changes (assertions find that it is not in the GPU)
3122 * 3. Read/written by GPU
3123 * execbuffer calls set_domain (RENDER, RENDER)
3124 * flush_domains gets CPU
3125 * invalidate_domains gets GPU
3127 * MI_FLUSH and drm_agp_chipset_flush
3128 * 4. set_domain (CPU, CPU)
3129 * flush_domains gets GPU
3130 * invalidate_domains gets CPU
3131 * wait_rendering (obj) to make sure all drawing is complete.
3132 * This will include an MI_FLUSH to get the data from GPU
3134 * clflush (obj) to invalidate the CPU cache
3135 * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
3136 * 5. Read/written by CPU
3137 * cache lines are loaded and dirtied
3138 * 6. Read written by GPU
3139 * Same as last GPU access
3141 * Case 3: The constant buffer
3146 * 4. Updated (written) by CPU again
3155 * flush_domains = CPU
3156 * invalidate_domains = RENDER
3159 * drm_agp_chipset_flush
3160 * 4. Updated (written) by CPU again
3162 * flush_domains = 0 (no previous write domain)
3163 * invalidate_domains = 0 (no new read domains)
3166 * flush_domains = CPU
3167 * invalidate_domains = RENDER
3170 * drm_agp_chipset_flush
3173 i915_gem_object_set_to_gpu_domain(struct drm_gem_object
*obj
,
3174 struct intel_ring_buffer
*ring
,
3175 struct change_domains
*cd
)
3177 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
3178 uint32_t invalidate_domains
= 0;
3179 uint32_t flush_domains
= 0;
3182 * If the object isn't moving to a new write domain,
3183 * let the object stay in multiple read domains
3185 if (obj
->pending_write_domain
== 0)
3186 obj
->pending_read_domains
|= obj
->read_domains
;
3189 * Flush the current write domain if
3190 * the new read domains don't match. Invalidate
3191 * any read domains which differ from the old
3194 if (obj
->write_domain
&&
3195 (obj
->write_domain
!= obj
->pending_read_domains
||
3196 obj_priv
->ring
!= ring
)) {
3197 flush_domains
|= obj
->write_domain
;
3198 invalidate_domains
|=
3199 obj
->pending_read_domains
& ~obj
->write_domain
;
3202 * Invalidate any read caches which may have
3203 * stale data. That is, any new read domains.
3205 invalidate_domains
|= obj
->pending_read_domains
& ~obj
->read_domains
;
3206 if ((flush_domains
| invalidate_domains
) & I915_GEM_DOMAIN_CPU
)
3207 i915_gem_clflush_object(obj
);
3209 /* blow away mappings if mapped through GTT */
3210 if ((flush_domains
| invalidate_domains
) & I915_GEM_DOMAIN_GTT
)
3211 i915_gem_release_mmap(obj
);
3213 /* The actual obj->write_domain will be updated with
3214 * pending_write_domain after we emit the accumulated flush for all
3215 * of our domain changes in execbuffers (which clears objects'
3216 * write_domains). So if we have a current write domain that we
3217 * aren't changing, set pending_write_domain to that.
3219 if (flush_domains
== 0 && obj
->pending_write_domain
== 0)
3220 obj
->pending_write_domain
= obj
->write_domain
;
3222 cd
->invalidate_domains
|= invalidate_domains
;
3223 cd
->flush_domains
|= flush_domains
;
3224 if (flush_domains
& I915_GEM_GPU_DOMAINS
)
3225 cd
->flush_rings
|= obj_priv
->ring
->id
;
3226 if (invalidate_domains
& I915_GEM_GPU_DOMAINS
)
3227 cd
->flush_rings
|= ring
->id
;
3231 * Moves the object from a partially CPU read to a full one.
3233 * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3234 * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
3237 i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object
*obj
)
3239 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
3241 if (!obj_priv
->page_cpu_valid
)
3244 /* If we're partially in the CPU read domain, finish moving it in.
3246 if (obj
->read_domains
& I915_GEM_DOMAIN_CPU
) {
3249 for (i
= 0; i
<= (obj
->size
- 1) / PAGE_SIZE
; i
++) {
3250 if (obj_priv
->page_cpu_valid
[i
])
3252 drm_clflush_pages(obj_priv
->pages
+ i
, 1);
3256 /* Free the page_cpu_valid mappings which are now stale, whether
3257 * or not we've got I915_GEM_DOMAIN_CPU.
3259 kfree(obj_priv
->page_cpu_valid
);
3260 obj_priv
->page_cpu_valid
= NULL
;
3264 * Set the CPU read domain on a range of the object.
3266 * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3267 * not entirely valid. The page_cpu_valid member of the object flags which
3268 * pages have been flushed, and will be respected by
3269 * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3270 * of the whole object.
3272 * This function returns when the move is complete, including waiting on
3276 i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object
*obj
,
3277 uint64_t offset
, uint64_t size
)
3279 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
3280 uint32_t old_read_domains
;
3283 if (offset
== 0 && size
== obj
->size
)
3284 return i915_gem_object_set_to_cpu_domain(obj
, 0);
3286 ret
= i915_gem_object_flush_gpu_write_domain(obj
, false);
3289 i915_gem_object_flush_gtt_write_domain(obj
);
3291 /* If we're already fully in the CPU read domain, we're done. */
3292 if (obj_priv
->page_cpu_valid
== NULL
&&
3293 (obj
->read_domains
& I915_GEM_DOMAIN_CPU
) != 0)
3296 /* Otherwise, create/clear the per-page CPU read domain flag if we're
3297 * newly adding I915_GEM_DOMAIN_CPU
3299 if (obj_priv
->page_cpu_valid
== NULL
) {
3300 obj_priv
->page_cpu_valid
= kzalloc(obj
->size
/ PAGE_SIZE
,
3302 if (obj_priv
->page_cpu_valid
== NULL
)
3304 } else if ((obj
->read_domains
& I915_GEM_DOMAIN_CPU
) == 0)
3305 memset(obj_priv
->page_cpu_valid
, 0, obj
->size
/ PAGE_SIZE
);
3307 /* Flush the cache on any pages that are still invalid from the CPU's
3310 for (i
= offset
/ PAGE_SIZE
; i
<= (offset
+ size
- 1) / PAGE_SIZE
;
3312 if (obj_priv
->page_cpu_valid
[i
])
3315 drm_clflush_pages(obj_priv
->pages
+ i
, 1);
3317 obj_priv
->page_cpu_valid
[i
] = 1;
3320 /* It should now be out of any other write domains, and we can update
3321 * the domain values for our changes.
3323 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
3325 old_read_domains
= obj
->read_domains
;
3326 obj
->read_domains
|= I915_GEM_DOMAIN_CPU
;
3328 trace_i915_gem_object_change_domain(obj
,
3336 * Pin an object to the GTT and evaluate the relocations landing in it.
3339 i915_gem_execbuffer_relocate(struct drm_i915_gem_object
*obj
,
3340 struct drm_file
*file_priv
,
3341 struct drm_i915_gem_exec_object2
*entry
)
3343 struct drm_device
*dev
= obj
->base
.dev
;
3344 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3345 struct drm_i915_gem_relocation_entry __user
*user_relocs
;
3346 struct drm_gem_object
*target_obj
= NULL
;
3347 uint32_t target_handle
= 0;
3350 user_relocs
= (void __user
*)(uintptr_t)entry
->relocs_ptr
;
3351 for (i
= 0; i
< entry
->relocation_count
; i
++) {
3352 struct drm_i915_gem_relocation_entry reloc
;
3353 uint32_t target_offset
;
3355 if (__copy_from_user_inatomic(&reloc
,
3362 if (reloc
.target_handle
!= target_handle
) {
3363 drm_gem_object_unreference(target_obj
);
3365 target_obj
= drm_gem_object_lookup(dev
, file_priv
,
3366 reloc
.target_handle
);
3367 if (target_obj
== NULL
) {
3372 target_handle
= reloc
.target_handle
;
3374 target_offset
= to_intel_bo(target_obj
)->gtt_offset
;
3377 DRM_INFO("%s: obj %p offset %08x target %d "
3378 "read %08x write %08x gtt %08x "
3379 "presumed %08x delta %08x\n",
3383 (int) reloc
.target_handle
,
3384 (int) reloc
.read_domains
,
3385 (int) reloc
.write_domain
,
3386 (int) target_offset
,
3387 (int) reloc
.presumed_offset
,
3391 /* The target buffer should have appeared before us in the
3392 * exec_object list, so it should have a GTT space bound by now.
3394 if (target_offset
== 0) {
3395 DRM_ERROR("No GTT space found for object %d\n",
3396 reloc
.target_handle
);
3401 /* Validate that the target is in a valid r/w GPU domain */
3402 if (reloc
.write_domain
& (reloc
.write_domain
- 1)) {
3403 DRM_ERROR("reloc with multiple write domains: "
3404 "obj %p target %d offset %d "
3405 "read %08x write %08x",
3406 obj
, reloc
.target_handle
,
3409 reloc
.write_domain
);
3413 if (reloc
.write_domain
& I915_GEM_DOMAIN_CPU
||
3414 reloc
.read_domains
& I915_GEM_DOMAIN_CPU
) {
3415 DRM_ERROR("reloc with read/write CPU domains: "
3416 "obj %p target %d offset %d "
3417 "read %08x write %08x",
3418 obj
, reloc
.target_handle
,
3421 reloc
.write_domain
);
3425 if (reloc
.write_domain
&& target_obj
->pending_write_domain
&&
3426 reloc
.write_domain
!= target_obj
->pending_write_domain
) {
3427 DRM_ERROR("Write domain conflict: "
3428 "obj %p target %d offset %d "
3429 "new %08x old %08x\n",
3430 obj
, reloc
.target_handle
,
3433 target_obj
->pending_write_domain
);
3438 target_obj
->pending_read_domains
|= reloc
.read_domains
;
3439 target_obj
->pending_write_domain
|= reloc
.write_domain
;
3441 /* If the relocation already has the right value in it, no
3442 * more work needs to be done.
3444 if (target_offset
== reloc
.presumed_offset
)
3447 /* Check that the relocation address is valid... */
3448 if (reloc
.offset
> obj
->base
.size
- 4) {
3449 DRM_ERROR("Relocation beyond object bounds: "
3450 "obj %p target %d offset %d size %d.\n",
3451 obj
, reloc
.target_handle
,
3452 (int) reloc
.offset
, (int) obj
->base
.size
);
3456 if (reloc
.offset
& 3) {
3457 DRM_ERROR("Relocation not 4-byte aligned: "
3458 "obj %p target %d offset %d.\n",
3459 obj
, reloc
.target_handle
,
3460 (int) reloc
.offset
);
3465 /* and points to somewhere within the target object. */
3466 if (reloc
.delta
>= target_obj
->size
) {
3467 DRM_ERROR("Relocation beyond target object bounds: "
3468 "obj %p target %d delta %d size %d.\n",
3469 obj
, reloc
.target_handle
,
3470 (int) reloc
.delta
, (int) target_obj
->size
);
3475 reloc
.delta
+= target_offset
;
3476 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_CPU
) {
3477 uint32_t page_offset
= reloc
.offset
& ~PAGE_MASK
;
3480 vaddr
= kmap_atomic(obj
->pages
[reloc
.offset
>> PAGE_SHIFT
]);
3481 *(uint32_t *)(vaddr
+ page_offset
) = reloc
.delta
;
3482 kunmap_atomic(vaddr
);
3484 uint32_t __iomem
*reloc_entry
;
3485 void __iomem
*reloc_page
;
3487 ret
= i915_gem_object_set_to_gtt_domain(&obj
->base
, 1);
3491 /* Map the page containing the relocation we're going to perform. */
3492 reloc
.offset
+= obj
->gtt_offset
;
3493 reloc_page
= io_mapping_map_atomic_wc(dev_priv
->mm
.gtt_mapping
,
3494 reloc
.offset
& PAGE_MASK
);
3495 reloc_entry
= (uint32_t __iomem
*)
3496 (reloc_page
+ (reloc
.offset
& ~PAGE_MASK
));
3497 iowrite32(reloc
.delta
, reloc_entry
);
3498 io_mapping_unmap_atomic(reloc_page
);
3501 /* and update the user's relocation entry */
3502 reloc
.presumed_offset
= target_offset
;
3503 if (__copy_to_user_inatomic(&user_relocs
[i
].presumed_offset
,
3504 &reloc
.presumed_offset
,
3505 sizeof(reloc
.presumed_offset
))) {
3511 drm_gem_object_unreference(target_obj
);
3516 i915_gem_execbuffer_pin(struct drm_device
*dev
,
3517 struct drm_file
*file
,
3518 struct drm_gem_object
**object_list
,
3519 struct drm_i915_gem_exec_object2
*exec_list
,
3522 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3525 /* attempt to pin all of the buffers into the GTT */
3529 for (i
= 0; i
< count
; i
++) {
3530 struct drm_i915_gem_exec_object2
*entry
= &exec_list
[i
];
3531 struct drm_i915_gem_object
*obj
= to_intel_bo(object_list
[i
]);
3533 entry
->flags
& EXEC_OBJECT_NEEDS_FENCE
&&
3534 obj
->tiling_mode
!= I915_TILING_NONE
;
3536 /* g33/pnv can't fence buffers in the unmappable part */
3537 bool need_mappable
=
3538 entry
->relocation_count
? true : need_fence
;
3540 /* Check fence reg constraints and rebind if necessary */
3541 if ((need_fence
&& !obj
->fenceable
) ||
3542 (need_mappable
&& !obj
->mappable
)) {
3543 ret
= i915_gem_object_unbind(&obj
->base
);
3548 ret
= i915_gem_object_pin(&obj
->base
,
3556 * Pre-965 chips need a fence register set up in order
3557 * to properly handle blits to/from tiled surfaces.
3560 ret
= i915_gem_object_get_fence_reg(&obj
->base
, true);
3562 i915_gem_object_unpin(&obj
->base
);
3566 dev_priv
->fence_regs
[obj
->fence_reg
].gpu
= true;
3569 entry
->offset
= obj
->gtt_offset
;
3573 i915_gem_object_unpin(object_list
[i
]);
3575 if (ret
!= -ENOSPC
|| retry
> 1)
3578 /* First attempt, just clear anything that is purgeable.
3579 * Second attempt, clear the entire GTT.
3581 ret
= i915_gem_evict_everything(dev
, retry
== 0);
3590 i915_gem_execbuffer_move_to_gpu(struct drm_device
*dev
,
3591 struct drm_file
*file
,
3592 struct intel_ring_buffer
*ring
,
3593 struct drm_gem_object
**objects
,
3596 struct change_domains cd
;
3599 cd
.invalidate_domains
= 0;
3600 cd
.flush_domains
= 0;
3602 for (i
= 0; i
< count
; i
++)
3603 i915_gem_object_set_to_gpu_domain(objects
[i
], ring
, &cd
);
3605 if (cd
.invalidate_domains
| cd
.flush_domains
) {
3607 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
3609 cd
.invalidate_domains
,
3612 i915_gem_flush(dev
, file
,
3613 cd
.invalidate_domains
,
3618 for (i
= 0; i
< count
; i
++) {
3619 struct drm_i915_gem_object
*obj
= to_intel_bo(objects
[i
]);
3620 /* XXX replace with semaphores */
3621 if (obj
->ring
&& ring
!= obj
->ring
) {
3622 ret
= i915_gem_object_wait_rendering(&obj
->base
, true);
3631 /* Throttle our rendering by waiting until the ring has completed our requests
3632 * emitted over 20 msec ago.
3634 * Note that if we were to use the current jiffies each time around the loop,
3635 * we wouldn't escape the function with any frames outstanding if the time to
3636 * render a frame was over 20ms.
3638 * This should get us reasonable parallelism between CPU and GPU but also
3639 * relatively low latency when blocking on a particular request to finish.
3642 i915_gem_ring_throttle(struct drm_device
*dev
, struct drm_file
*file
)
3644 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3645 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
3646 unsigned long recent_enough
= jiffies
- msecs_to_jiffies(20);
3647 struct drm_i915_gem_request
*request
;
3648 struct intel_ring_buffer
*ring
= NULL
;
3652 spin_lock(&file_priv
->mm
.lock
);
3653 list_for_each_entry(request
, &file_priv
->mm
.request_list
, client_list
) {
3654 if (time_after_eq(request
->emitted_jiffies
, recent_enough
))
3657 ring
= request
->ring
;
3658 seqno
= request
->seqno
;
3660 spin_unlock(&file_priv
->mm
.lock
);
3666 if (!i915_seqno_passed(ring
->get_seqno(ring
), seqno
)) {
3667 /* And wait for the seqno passing without holding any locks and
3668 * causing extra latency for others. This is safe as the irq
3669 * generation is designed to be run atomically and so is
3672 ring
->user_irq_get(ring
);
3673 ret
= wait_event_interruptible(ring
->irq_queue
,
3674 i915_seqno_passed(ring
->get_seqno(ring
), seqno
)
3675 || atomic_read(&dev_priv
->mm
.wedged
));
3676 ring
->user_irq_put(ring
);
3678 if (ret
== 0 && atomic_read(&dev_priv
->mm
.wedged
))
3683 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, 0);
3689 i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2
*exec
,
3690 uint64_t exec_offset
)
3692 uint32_t exec_start
, exec_len
;
3694 exec_start
= (uint32_t) exec_offset
+ exec
->batch_start_offset
;
3695 exec_len
= (uint32_t) exec
->batch_len
;
3697 if ((exec_start
| exec_len
) & 0x7)
3707 validate_exec_list(struct drm_i915_gem_exec_object2
*exec
,
3712 for (i
= 0; i
< count
; i
++) {
3713 char __user
*ptr
= (char __user
*)(uintptr_t)exec
[i
].relocs_ptr
;
3714 size_t length
= exec
[i
].relocation_count
* sizeof(struct drm_i915_gem_relocation_entry
);
3716 if (!access_ok(VERIFY_READ
, ptr
, length
))
3719 /* we may also need to update the presumed offsets */
3720 if (!access_ok(VERIFY_WRITE
, ptr
, length
))
3723 if (fault_in_pages_readable(ptr
, length
))
3731 i915_gem_do_execbuffer(struct drm_device
*dev
, void *data
,
3732 struct drm_file
*file
,
3733 struct drm_i915_gem_execbuffer2
*args
,
3734 struct drm_i915_gem_exec_object2
*exec_list
)
3736 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3737 struct drm_gem_object
**object_list
= NULL
;
3738 struct drm_gem_object
*batch_obj
;
3739 struct drm_clip_rect
*cliprects
= NULL
;
3740 struct drm_i915_gem_request
*request
= NULL
;
3742 uint64_t exec_offset
;
3744 struct intel_ring_buffer
*ring
= NULL
;
3746 ret
= i915_gem_check_is_wedged(dev
);
3750 ret
= validate_exec_list(exec_list
, args
->buffer_count
);
3755 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3756 (int) args
->buffers_ptr
, args
->buffer_count
, args
->batch_len
);
3758 switch (args
->flags
& I915_EXEC_RING_MASK
) {
3759 case I915_EXEC_DEFAULT
:
3760 case I915_EXEC_RENDER
:
3761 ring
= &dev_priv
->render_ring
;
3764 if (!HAS_BSD(dev
)) {
3765 DRM_ERROR("execbuf with invalid ring (BSD)\n");
3768 ring
= &dev_priv
->bsd_ring
;
3771 if (!HAS_BLT(dev
)) {
3772 DRM_ERROR("execbuf with invalid ring (BLT)\n");
3775 ring
= &dev_priv
->blt_ring
;
3778 DRM_ERROR("execbuf with unknown ring: %d\n",
3779 (int)(args
->flags
& I915_EXEC_RING_MASK
));
3783 if (args
->buffer_count
< 1) {
3784 DRM_ERROR("execbuf with %d buffers\n", args
->buffer_count
);
3787 object_list
= drm_malloc_ab(sizeof(*object_list
), args
->buffer_count
);
3788 if (object_list
== NULL
) {
3789 DRM_ERROR("Failed to allocate object list for %d buffers\n",
3790 args
->buffer_count
);
3795 if (args
->num_cliprects
!= 0) {
3796 cliprects
= kcalloc(args
->num_cliprects
, sizeof(*cliprects
),
3798 if (cliprects
== NULL
) {
3803 ret
= copy_from_user(cliprects
,
3804 (struct drm_clip_rect __user
*)
3805 (uintptr_t) args
->cliprects_ptr
,
3806 sizeof(*cliprects
) * args
->num_cliprects
);
3808 DRM_ERROR("copy %d cliprects failed: %d\n",
3809 args
->num_cliprects
, ret
);
3815 request
= kzalloc(sizeof(*request
), GFP_KERNEL
);
3816 if (request
== NULL
) {
3821 ret
= i915_mutex_lock_interruptible(dev
);
3825 if (dev_priv
->mm
.suspended
) {
3826 mutex_unlock(&dev
->struct_mutex
);
3831 /* Look up object handles */
3832 for (i
= 0; i
< args
->buffer_count
; i
++) {
3833 struct drm_i915_gem_object
*obj_priv
;
3835 object_list
[i
] = drm_gem_object_lookup(dev
, file
,
3836 exec_list
[i
].handle
);
3837 if (object_list
[i
] == NULL
) {
3838 DRM_ERROR("Invalid object handle %d at index %d\n",
3839 exec_list
[i
].handle
, i
);
3840 /* prevent error path from reading uninitialized data */
3841 args
->buffer_count
= i
+ 1;
3846 obj_priv
= to_intel_bo(object_list
[i
]);
3847 if (obj_priv
->in_execbuffer
) {
3848 DRM_ERROR("Object %p appears more than once in object list\n",
3850 /* prevent error path from reading uninitialized data */
3851 args
->buffer_count
= i
+ 1;
3855 obj_priv
->in_execbuffer
= true;
3858 /* Move the objects en-masse into the GTT, evicting if necessary. */
3859 ret
= i915_gem_execbuffer_pin(dev
, file
,
3860 object_list
, exec_list
,
3861 args
->buffer_count
);
3865 /* The objects are in their final locations, apply the relocations. */
3866 for (i
= 0; i
< args
->buffer_count
; i
++) {
3867 struct drm_i915_gem_object
*obj
= to_intel_bo(object_list
[i
]);
3868 obj
->base
.pending_read_domains
= 0;
3869 obj
->base
.pending_write_domain
= 0;
3870 ret
= i915_gem_execbuffer_relocate(obj
, file
, &exec_list
[i
]);
3875 /* Set the pending read domains for the batch buffer to COMMAND */
3876 batch_obj
= object_list
[args
->buffer_count
-1];
3877 if (batch_obj
->pending_write_domain
) {
3878 DRM_ERROR("Attempting to use self-modifying batch buffer\n");
3882 batch_obj
->pending_read_domains
|= I915_GEM_DOMAIN_COMMAND
;
3884 /* Sanity check the batch buffer */
3885 exec_offset
= to_intel_bo(batch_obj
)->gtt_offset
;
3886 ret
= i915_gem_check_execbuffer(args
, exec_offset
);
3888 DRM_ERROR("execbuf with invalid offset/length\n");
3892 ret
= i915_gem_execbuffer_move_to_gpu(dev
, file
, ring
,
3893 object_list
, args
->buffer_count
);
3898 for (i
= 0; i
< args
->buffer_count
; i
++) {
3899 i915_gem_object_check_coherency(object_list
[i
],
3900 exec_list
[i
].handle
);
3905 i915_gem_dump_object(batch_obj
,
3911 /* Check for any pending flips. As we only maintain a flip queue depth
3912 * of 1, we can simply insert a WAIT for the next display flip prior
3913 * to executing the batch and avoid stalling the CPU.
3916 for (i
= 0; i
< args
->buffer_count
; i
++) {
3917 if (object_list
[i
]->write_domain
)
3918 flips
|= atomic_read(&to_intel_bo(object_list
[i
])->pending_flip
);
3921 int plane
, flip_mask
;
3923 for (plane
= 0; flips
>> plane
; plane
++) {
3924 if (((flips
>> plane
) & 1) == 0)
3928 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
3930 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
3932 ret
= intel_ring_begin(ring
, 2);
3936 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
3937 intel_ring_emit(ring
, MI_NOOP
);
3938 intel_ring_advance(ring
);
3942 /* Exec the batchbuffer */
3943 ret
= ring
->dispatch_execbuffer(ring
, args
, cliprects
, exec_offset
);
3945 DRM_ERROR("dispatch failed %d\n", ret
);
3949 for (i
= 0; i
< args
->buffer_count
; i
++) {
3950 struct drm_gem_object
*obj
= object_list
[i
];
3952 obj
->read_domains
= obj
->pending_read_domains
;
3953 obj
->write_domain
= obj
->pending_write_domain
;
3955 i915_gem_object_move_to_active(obj
, ring
);
3956 if (obj
->write_domain
) {
3957 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
3958 obj_priv
->dirty
= 1;
3959 list_move_tail(&obj_priv
->gpu_write_list
,
3960 &ring
->gpu_write_list
);
3961 intel_mark_busy(dev
, obj
);
3964 trace_i915_gem_object_change_domain(obj
,
3970 * Ensure that the commands in the batch buffer are
3971 * finished before the interrupt fires
3973 i915_retire_commands(dev
, ring
);
3975 if (i915_add_request(dev
, file
, request
, ring
))
3976 ring
->outstanding_lazy_request
= true;
3981 for (i
= 0; i
< args
->buffer_count
; i
++) {
3982 if (object_list
[i
] == NULL
)
3985 to_intel_bo(object_list
[i
])->in_execbuffer
= false;
3986 drm_gem_object_unreference(object_list
[i
]);
3989 mutex_unlock(&dev
->struct_mutex
);
3992 drm_free_large(object_list
);
4000 * Legacy execbuffer just creates an exec2 list from the original exec object
4001 * list array and passes it to the real function.
4004 i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
4005 struct drm_file
*file_priv
)
4007 struct drm_i915_gem_execbuffer
*args
= data
;
4008 struct drm_i915_gem_execbuffer2 exec2
;
4009 struct drm_i915_gem_exec_object
*exec_list
= NULL
;
4010 struct drm_i915_gem_exec_object2
*exec2_list
= NULL
;
4014 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
4015 (int) args
->buffers_ptr
, args
->buffer_count
, args
->batch_len
);
4018 if (args
->buffer_count
< 1) {
4019 DRM_ERROR("execbuf with %d buffers\n", args
->buffer_count
);
4023 /* Copy in the exec list from userland */
4024 exec_list
= drm_malloc_ab(sizeof(*exec_list
), args
->buffer_count
);
4025 exec2_list
= drm_malloc_ab(sizeof(*exec2_list
), args
->buffer_count
);
4026 if (exec_list
== NULL
|| exec2_list
== NULL
) {
4027 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
4028 args
->buffer_count
);
4029 drm_free_large(exec_list
);
4030 drm_free_large(exec2_list
);
4033 ret
= copy_from_user(exec_list
,
4034 (struct drm_i915_relocation_entry __user
*)
4035 (uintptr_t) args
->buffers_ptr
,
4036 sizeof(*exec_list
) * args
->buffer_count
);
4038 DRM_ERROR("copy %d exec entries failed %d\n",
4039 args
->buffer_count
, ret
);
4040 drm_free_large(exec_list
);
4041 drm_free_large(exec2_list
);
4045 for (i
= 0; i
< args
->buffer_count
; i
++) {
4046 exec2_list
[i
].handle
= exec_list
[i
].handle
;
4047 exec2_list
[i
].relocation_count
= exec_list
[i
].relocation_count
;
4048 exec2_list
[i
].relocs_ptr
= exec_list
[i
].relocs_ptr
;
4049 exec2_list
[i
].alignment
= exec_list
[i
].alignment
;
4050 exec2_list
[i
].offset
= exec_list
[i
].offset
;
4051 if (INTEL_INFO(dev
)->gen
< 4)
4052 exec2_list
[i
].flags
= EXEC_OBJECT_NEEDS_FENCE
;
4054 exec2_list
[i
].flags
= 0;
4057 exec2
.buffers_ptr
= args
->buffers_ptr
;
4058 exec2
.buffer_count
= args
->buffer_count
;
4059 exec2
.batch_start_offset
= args
->batch_start_offset
;
4060 exec2
.batch_len
= args
->batch_len
;
4061 exec2
.DR1
= args
->DR1
;
4062 exec2
.DR4
= args
->DR4
;
4063 exec2
.num_cliprects
= args
->num_cliprects
;
4064 exec2
.cliprects_ptr
= args
->cliprects_ptr
;
4065 exec2
.flags
= I915_EXEC_RENDER
;
4067 ret
= i915_gem_do_execbuffer(dev
, data
, file_priv
, &exec2
, exec2_list
);
4069 /* Copy the new buffer offsets back to the user's exec list. */
4070 for (i
= 0; i
< args
->buffer_count
; i
++)
4071 exec_list
[i
].offset
= exec2_list
[i
].offset
;
4072 /* ... and back out to userspace */
4073 ret
= copy_to_user((struct drm_i915_relocation_entry __user
*)
4074 (uintptr_t) args
->buffers_ptr
,
4076 sizeof(*exec_list
) * args
->buffer_count
);
4079 DRM_ERROR("failed to copy %d exec entries "
4080 "back to user (%d)\n",
4081 args
->buffer_count
, ret
);
4085 drm_free_large(exec_list
);
4086 drm_free_large(exec2_list
);
4091 i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
4092 struct drm_file
*file_priv
)
4094 struct drm_i915_gem_execbuffer2
*args
= data
;
4095 struct drm_i915_gem_exec_object2
*exec2_list
= NULL
;
4099 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
4100 (int) args
->buffers_ptr
, args
->buffer_count
, args
->batch_len
);
4103 if (args
->buffer_count
< 1) {
4104 DRM_ERROR("execbuf2 with %d buffers\n", args
->buffer_count
);
4108 exec2_list
= drm_malloc_ab(sizeof(*exec2_list
), args
->buffer_count
);
4109 if (exec2_list
== NULL
) {
4110 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
4111 args
->buffer_count
);
4114 ret
= copy_from_user(exec2_list
,
4115 (struct drm_i915_relocation_entry __user
*)
4116 (uintptr_t) args
->buffers_ptr
,
4117 sizeof(*exec2_list
) * args
->buffer_count
);
4119 DRM_ERROR("copy %d exec entries failed %d\n",
4120 args
->buffer_count
, ret
);
4121 drm_free_large(exec2_list
);
4125 ret
= i915_gem_do_execbuffer(dev
, data
, file_priv
, args
, exec2_list
);
4127 /* Copy the new buffer offsets back to the user's exec list. */
4128 ret
= copy_to_user((struct drm_i915_relocation_entry __user
*)
4129 (uintptr_t) args
->buffers_ptr
,
4131 sizeof(*exec2_list
) * args
->buffer_count
);
4134 DRM_ERROR("failed to copy %d exec entries "
4135 "back to user (%d)\n",
4136 args
->buffer_count
, ret
);
4140 drm_free_large(exec2_list
);
4145 i915_gem_object_pin(struct drm_gem_object
*obj
, uint32_t alignment
,
4146 bool mappable
, bool need_fence
)
4148 struct drm_device
*dev
= obj
->dev
;
4149 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4150 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
4153 BUG_ON(obj_priv
->pin_count
== DRM_I915_GEM_OBJECT_MAX_PIN_COUNT
);
4154 BUG_ON(need_fence
&& !mappable
);
4155 WARN_ON(i915_verify_lists(dev
));
4157 if (obj_priv
->gtt_space
!= NULL
) {
4158 if ((alignment
&& obj_priv
->gtt_offset
& (alignment
- 1)) ||
4159 (need_fence
&& !obj_priv
->fenceable
) ||
4160 (mappable
&& !obj_priv
->mappable
)) {
4161 WARN(obj_priv
->pin_count
,
4162 "bo is already pinned with incorrect alignment:"
4163 " offset=%x, req.alignment=%x, need_fence=%d, fenceable=%d, mappable=%d, cpu_accessible=%d\n",
4164 obj_priv
->gtt_offset
, alignment
,
4165 need_fence
, obj_priv
->fenceable
,
4166 mappable
, obj_priv
->mappable
);
4167 ret
= i915_gem_object_unbind(obj
);
4173 if (obj_priv
->gtt_space
== NULL
) {
4174 ret
= i915_gem_object_bind_to_gtt(obj
, alignment
,
4175 mappable
, need_fence
);
4180 if (obj_priv
->pin_count
++ == 0) {
4181 i915_gem_info_add_pin(dev_priv
, obj_priv
, mappable
);
4182 if (!obj_priv
->active
)
4183 list_move_tail(&obj_priv
->mm_list
,
4184 &dev_priv
->mm
.pinned_list
);
4186 BUG_ON(!obj_priv
->pin_mappable
&& mappable
);
4188 WARN_ON(i915_verify_lists(dev
));
4193 i915_gem_object_unpin(struct drm_gem_object
*obj
)
4195 struct drm_device
*dev
= obj
->dev
;
4196 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4197 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
4199 WARN_ON(i915_verify_lists(dev
));
4200 BUG_ON(obj_priv
->pin_count
== 0);
4201 BUG_ON(obj_priv
->gtt_space
== NULL
);
4203 if (--obj_priv
->pin_count
== 0) {
4204 if (!obj_priv
->active
)
4205 list_move_tail(&obj_priv
->mm_list
,
4206 &dev_priv
->mm
.inactive_list
);
4207 i915_gem_info_remove_pin(dev_priv
, obj_priv
);
4209 WARN_ON(i915_verify_lists(dev
));
4213 i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
4214 struct drm_file
*file_priv
)
4216 struct drm_i915_gem_pin
*args
= data
;
4217 struct drm_gem_object
*obj
;
4218 struct drm_i915_gem_object
*obj_priv
;
4221 ret
= i915_mutex_lock_interruptible(dev
);
4225 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4230 obj_priv
= to_intel_bo(obj
);
4232 if (obj_priv
->madv
!= I915_MADV_WILLNEED
) {
4233 DRM_ERROR("Attempting to pin a purgeable buffer\n");
4238 if (obj_priv
->pin_filp
!= NULL
&& obj_priv
->pin_filp
!= file_priv
) {
4239 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
4245 obj_priv
->user_pin_count
++;
4246 obj_priv
->pin_filp
= file_priv
;
4247 if (obj_priv
->user_pin_count
== 1) {
4248 ret
= i915_gem_object_pin(obj
, args
->alignment
,
4249 true, obj_priv
->tiling_mode
);
4254 /* XXX - flush the CPU caches for pinned objects
4255 * as the X server doesn't manage domains yet
4257 i915_gem_object_flush_cpu_write_domain(obj
);
4258 args
->offset
= obj_priv
->gtt_offset
;
4260 drm_gem_object_unreference(obj
);
4262 mutex_unlock(&dev
->struct_mutex
);
4267 i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
4268 struct drm_file
*file_priv
)
4270 struct drm_i915_gem_pin
*args
= data
;
4271 struct drm_gem_object
*obj
;
4272 struct drm_i915_gem_object
*obj_priv
;
4275 ret
= i915_mutex_lock_interruptible(dev
);
4279 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4284 obj_priv
= to_intel_bo(obj
);
4286 if (obj_priv
->pin_filp
!= file_priv
) {
4287 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4292 obj_priv
->user_pin_count
--;
4293 if (obj_priv
->user_pin_count
== 0) {
4294 obj_priv
->pin_filp
= NULL
;
4295 i915_gem_object_unpin(obj
);
4299 drm_gem_object_unreference(obj
);
4301 mutex_unlock(&dev
->struct_mutex
);
4306 i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
4307 struct drm_file
*file_priv
)
4309 struct drm_i915_gem_busy
*args
= data
;
4310 struct drm_gem_object
*obj
;
4311 struct drm_i915_gem_object
*obj_priv
;
4314 ret
= i915_mutex_lock_interruptible(dev
);
4318 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4323 obj_priv
= to_intel_bo(obj
);
4325 /* Count all active objects as busy, even if they are currently not used
4326 * by the gpu. Users of this interface expect objects to eventually
4327 * become non-busy without any further actions, therefore emit any
4328 * necessary flushes here.
4330 args
->busy
= obj_priv
->active
;
4332 /* Unconditionally flush objects, even when the gpu still uses this
4333 * object. Userspace calling this function indicates that it wants to
4334 * use this buffer rather sooner than later, so issuing the required
4335 * flush earlier is beneficial.
4337 if (obj
->write_domain
& I915_GEM_GPU_DOMAINS
)
4338 i915_gem_flush_ring(dev
, file_priv
,
4340 0, obj
->write_domain
);
4342 /* Update the active list for the hardware's current position.
4343 * Otherwise this only updates on a delayed timer or when irqs
4344 * are actually unmasked, and our working set ends up being
4345 * larger than required.
4347 i915_gem_retire_requests_ring(dev
, obj_priv
->ring
);
4349 args
->busy
= obj_priv
->active
;
4352 drm_gem_object_unreference(obj
);
4354 mutex_unlock(&dev
->struct_mutex
);
4359 i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
4360 struct drm_file
*file_priv
)
4362 return i915_gem_ring_throttle(dev
, file_priv
);
4366 i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
4367 struct drm_file
*file_priv
)
4369 struct drm_i915_gem_madvise
*args
= data
;
4370 struct drm_gem_object
*obj
;
4371 struct drm_i915_gem_object
*obj_priv
;
4374 switch (args
->madv
) {
4375 case I915_MADV_DONTNEED
:
4376 case I915_MADV_WILLNEED
:
4382 ret
= i915_mutex_lock_interruptible(dev
);
4386 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4391 obj_priv
= to_intel_bo(obj
);
4393 if (obj_priv
->pin_count
) {
4398 if (obj_priv
->madv
!= __I915_MADV_PURGED
)
4399 obj_priv
->madv
= args
->madv
;
4401 /* if the object is no longer bound, discard its backing storage */
4402 if (i915_gem_object_is_purgeable(obj_priv
) &&
4403 obj_priv
->gtt_space
== NULL
)
4404 i915_gem_object_truncate(obj
);
4406 args
->retained
= obj_priv
->madv
!= __I915_MADV_PURGED
;
4409 drm_gem_object_unreference(obj
);
4411 mutex_unlock(&dev
->struct_mutex
);
4415 struct drm_gem_object
* i915_gem_alloc_object(struct drm_device
*dev
,
4418 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4419 struct drm_i915_gem_object
*obj
;
4421 obj
= kzalloc(sizeof(*obj
), GFP_KERNEL
);
4425 if (drm_gem_object_init(dev
, &obj
->base
, size
) != 0) {
4430 i915_gem_info_add_obj(dev_priv
, size
);
4432 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
4433 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
4435 obj
->agp_type
= AGP_USER_MEMORY
;
4436 obj
->base
.driver_private
= NULL
;
4437 obj
->fence_reg
= I915_FENCE_REG_NONE
;
4438 INIT_LIST_HEAD(&obj
->mm_list
);
4439 INIT_LIST_HEAD(&obj
->ring_list
);
4440 INIT_LIST_HEAD(&obj
->gpu_write_list
);
4441 obj
->madv
= I915_MADV_WILLNEED
;
4442 obj
->fenceable
= true;
4443 obj
->mappable
= true;
4448 int i915_gem_init_object(struct drm_gem_object
*obj
)
4455 static void i915_gem_free_object_tail(struct drm_gem_object
*obj
)
4457 struct drm_device
*dev
= obj
->dev
;
4458 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4459 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
4462 ret
= i915_gem_object_unbind(obj
);
4463 if (ret
== -ERESTARTSYS
) {
4464 list_move(&obj_priv
->mm_list
,
4465 &dev_priv
->mm
.deferred_free_list
);
4469 if (obj
->map_list
.map
)
4470 i915_gem_free_mmap_offset(obj
);
4472 drm_gem_object_release(obj
);
4473 i915_gem_info_remove_obj(dev_priv
, obj
->size
);
4475 kfree(obj_priv
->page_cpu_valid
);
4476 kfree(obj_priv
->bit_17
);
4480 void i915_gem_free_object(struct drm_gem_object
*obj
)
4482 struct drm_device
*dev
= obj
->dev
;
4483 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
4485 trace_i915_gem_object_destroy(obj
);
4487 while (obj_priv
->pin_count
> 0)
4488 i915_gem_object_unpin(obj
);
4490 if (obj_priv
->phys_obj
)
4491 i915_gem_detach_phys_object(dev
, obj
);
4493 i915_gem_free_object_tail(obj
);
4497 i915_gem_idle(struct drm_device
*dev
)
4499 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4502 mutex_lock(&dev
->struct_mutex
);
4504 if (dev_priv
->mm
.suspended
) {
4505 mutex_unlock(&dev
->struct_mutex
);
4509 ret
= i915_gpu_idle(dev
);
4511 mutex_unlock(&dev
->struct_mutex
);
4515 /* Under UMS, be paranoid and evict. */
4516 if (!drm_core_check_feature(dev
, DRIVER_MODESET
)) {
4517 ret
= i915_gem_evict_inactive(dev
, false);
4519 mutex_unlock(&dev
->struct_mutex
);
4524 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4525 * We need to replace this with a semaphore, or something.
4526 * And not confound mm.suspended!
4528 dev_priv
->mm
.suspended
= 1;
4529 del_timer_sync(&dev_priv
->hangcheck_timer
);
4531 i915_kernel_lost_context(dev
);
4532 i915_gem_cleanup_ringbuffer(dev
);
4534 mutex_unlock(&dev
->struct_mutex
);
4536 /* Cancel the retire work handler, which should be idle now. */
4537 cancel_delayed_work_sync(&dev_priv
->mm
.retire_work
);
4543 * 965+ support PIPE_CONTROL commands, which provide finer grained control
4544 * over cache flushing.
4547 i915_gem_init_pipe_control(struct drm_device
*dev
)
4549 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4550 struct drm_gem_object
*obj
;
4551 struct drm_i915_gem_object
*obj_priv
;
4554 obj
= i915_gem_alloc_object(dev
, 4096);
4556 DRM_ERROR("Failed to allocate seqno page\n");
4560 obj_priv
= to_intel_bo(obj
);
4561 obj_priv
->agp_type
= AGP_USER_CACHED_MEMORY
;
4563 ret
= i915_gem_object_pin(obj
, 4096, true, false);
4567 dev_priv
->seqno_gfx_addr
= obj_priv
->gtt_offset
;
4568 dev_priv
->seqno_page
= kmap(obj_priv
->pages
[0]);
4569 if (dev_priv
->seqno_page
== NULL
)
4572 dev_priv
->seqno_obj
= obj
;
4573 memset(dev_priv
->seqno_page
, 0, PAGE_SIZE
);
4578 i915_gem_object_unpin(obj
);
4580 drm_gem_object_unreference(obj
);
4587 i915_gem_cleanup_pipe_control(struct drm_device
*dev
)
4589 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4590 struct drm_gem_object
*obj
;
4591 struct drm_i915_gem_object
*obj_priv
;
4593 obj
= dev_priv
->seqno_obj
;
4594 obj_priv
= to_intel_bo(obj
);
4595 kunmap(obj_priv
->pages
[0]);
4596 i915_gem_object_unpin(obj
);
4597 drm_gem_object_unreference(obj
);
4598 dev_priv
->seqno_obj
= NULL
;
4600 dev_priv
->seqno_page
= NULL
;
4604 i915_gem_init_ringbuffer(struct drm_device
*dev
)
4606 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4609 if (HAS_PIPE_CONTROL(dev
)) {
4610 ret
= i915_gem_init_pipe_control(dev
);
4615 ret
= intel_init_render_ring_buffer(dev
);
4617 goto cleanup_pipe_control
;
4620 ret
= intel_init_bsd_ring_buffer(dev
);
4622 goto cleanup_render_ring
;
4626 ret
= intel_init_blt_ring_buffer(dev
);
4628 goto cleanup_bsd_ring
;
4631 dev_priv
->next_seqno
= 1;
4636 intel_cleanup_ring_buffer(&dev_priv
->bsd_ring
);
4637 cleanup_render_ring
:
4638 intel_cleanup_ring_buffer(&dev_priv
->render_ring
);
4639 cleanup_pipe_control
:
4640 if (HAS_PIPE_CONTROL(dev
))
4641 i915_gem_cleanup_pipe_control(dev
);
4646 i915_gem_cleanup_ringbuffer(struct drm_device
*dev
)
4648 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4650 intel_cleanup_ring_buffer(&dev_priv
->render_ring
);
4651 intel_cleanup_ring_buffer(&dev_priv
->bsd_ring
);
4652 intel_cleanup_ring_buffer(&dev_priv
->blt_ring
);
4653 if (HAS_PIPE_CONTROL(dev
))
4654 i915_gem_cleanup_pipe_control(dev
);
4658 i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
4659 struct drm_file
*file_priv
)
4661 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4664 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4667 if (atomic_read(&dev_priv
->mm
.wedged
)) {
4668 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4669 atomic_set(&dev_priv
->mm
.wedged
, 0);
4672 mutex_lock(&dev
->struct_mutex
);
4673 dev_priv
->mm
.suspended
= 0;
4675 ret
= i915_gem_init_ringbuffer(dev
);
4677 mutex_unlock(&dev
->struct_mutex
);
4681 BUG_ON(!list_empty(&dev_priv
->mm
.active_list
));
4682 BUG_ON(!list_empty(&dev_priv
->render_ring
.active_list
));
4683 BUG_ON(!list_empty(&dev_priv
->bsd_ring
.active_list
));
4684 BUG_ON(!list_empty(&dev_priv
->blt_ring
.active_list
));
4685 BUG_ON(!list_empty(&dev_priv
->mm
.flushing_list
));
4686 BUG_ON(!list_empty(&dev_priv
->mm
.inactive_list
));
4687 BUG_ON(!list_empty(&dev_priv
->render_ring
.request_list
));
4688 BUG_ON(!list_empty(&dev_priv
->bsd_ring
.request_list
));
4689 BUG_ON(!list_empty(&dev_priv
->blt_ring
.request_list
));
4690 mutex_unlock(&dev
->struct_mutex
);
4692 ret
= drm_irq_install(dev
);
4694 goto cleanup_ringbuffer
;
4699 mutex_lock(&dev
->struct_mutex
);
4700 i915_gem_cleanup_ringbuffer(dev
);
4701 dev_priv
->mm
.suspended
= 1;
4702 mutex_unlock(&dev
->struct_mutex
);
4708 i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
4709 struct drm_file
*file_priv
)
4711 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4714 drm_irq_uninstall(dev
);
4715 return i915_gem_idle(dev
);
4719 i915_gem_lastclose(struct drm_device
*dev
)
4723 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4726 ret
= i915_gem_idle(dev
);
4728 DRM_ERROR("failed to idle hardware: %d\n", ret
);
4732 init_ring_lists(struct intel_ring_buffer
*ring
)
4734 INIT_LIST_HEAD(&ring
->active_list
);
4735 INIT_LIST_HEAD(&ring
->request_list
);
4736 INIT_LIST_HEAD(&ring
->gpu_write_list
);
4740 i915_gem_load(struct drm_device
*dev
)
4743 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4745 INIT_LIST_HEAD(&dev_priv
->mm
.active_list
);
4746 INIT_LIST_HEAD(&dev_priv
->mm
.flushing_list
);
4747 INIT_LIST_HEAD(&dev_priv
->mm
.inactive_list
);
4748 INIT_LIST_HEAD(&dev_priv
->mm
.pinned_list
);
4749 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
4750 INIT_LIST_HEAD(&dev_priv
->mm
.deferred_free_list
);
4751 init_ring_lists(&dev_priv
->render_ring
);
4752 init_ring_lists(&dev_priv
->bsd_ring
);
4753 init_ring_lists(&dev_priv
->blt_ring
);
4754 for (i
= 0; i
< 16; i
++)
4755 INIT_LIST_HEAD(&dev_priv
->fence_regs
[i
].lru_list
);
4756 INIT_DELAYED_WORK(&dev_priv
->mm
.retire_work
,
4757 i915_gem_retire_work_handler
);
4758 init_completion(&dev_priv
->error_completion
);
4760 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4762 u32 tmp
= I915_READ(MI_ARB_STATE
);
4763 if (!(tmp
& MI_ARB_C3_LP_WRITE_ENABLE
)) {
4764 /* arb state is a masked write, so set bit + bit in mask */
4765 tmp
= MI_ARB_C3_LP_WRITE_ENABLE
| (MI_ARB_C3_LP_WRITE_ENABLE
<< MI_ARB_MASK_SHIFT
);
4766 I915_WRITE(MI_ARB_STATE
, tmp
);
4770 /* Old X drivers will take 0-2 for front, back, depth buffers */
4771 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
4772 dev_priv
->fence_reg_start
= 3;
4774 if (INTEL_INFO(dev
)->gen
>= 4 || IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
4775 dev_priv
->num_fence_regs
= 16;
4777 dev_priv
->num_fence_regs
= 8;
4779 /* Initialize fence registers to zero */
4780 switch (INTEL_INFO(dev
)->gen
) {
4782 for (i
= 0; i
< 16; i
++)
4783 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0
+ (i
* 8), 0);
4787 for (i
= 0; i
< 16; i
++)
4788 I915_WRITE64(FENCE_REG_965_0
+ (i
* 8), 0);
4791 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
4792 for (i
= 0; i
< 8; i
++)
4793 I915_WRITE(FENCE_REG_945_8
+ (i
* 4), 0);
4795 for (i
= 0; i
< 8; i
++)
4796 I915_WRITE(FENCE_REG_830_0
+ (i
* 4), 0);
4799 i915_gem_detect_bit_6_swizzle(dev
);
4800 init_waitqueue_head(&dev_priv
->pending_flip_queue
);
4802 dev_priv
->mm
.inactive_shrinker
.shrink
= i915_gem_inactive_shrink
;
4803 dev_priv
->mm
.inactive_shrinker
.seeks
= DEFAULT_SEEKS
;
4804 register_shrinker(&dev_priv
->mm
.inactive_shrinker
);
4808 * Create a physically contiguous memory object for this object
4809 * e.g. for cursor + overlay regs
4811 static int i915_gem_init_phys_object(struct drm_device
*dev
,
4812 int id
, int size
, int align
)
4814 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4815 struct drm_i915_gem_phys_object
*phys_obj
;
4818 if (dev_priv
->mm
.phys_objs
[id
- 1] || !size
)
4821 phys_obj
= kzalloc(sizeof(struct drm_i915_gem_phys_object
), GFP_KERNEL
);
4827 phys_obj
->handle
= drm_pci_alloc(dev
, size
, align
);
4828 if (!phys_obj
->handle
) {
4833 set_memory_wc((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
4836 dev_priv
->mm
.phys_objs
[id
- 1] = phys_obj
;
4844 static void i915_gem_free_phys_object(struct drm_device
*dev
, int id
)
4846 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4847 struct drm_i915_gem_phys_object
*phys_obj
;
4849 if (!dev_priv
->mm
.phys_objs
[id
- 1])
4852 phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
4853 if (phys_obj
->cur_obj
) {
4854 i915_gem_detach_phys_object(dev
, phys_obj
->cur_obj
);
4858 set_memory_wb((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
4860 drm_pci_free(dev
, phys_obj
->handle
);
4862 dev_priv
->mm
.phys_objs
[id
- 1] = NULL
;
4865 void i915_gem_free_all_phys_object(struct drm_device
*dev
)
4869 for (i
= I915_GEM_PHYS_CURSOR_0
; i
<= I915_MAX_PHYS_OBJECT
; i
++)
4870 i915_gem_free_phys_object(dev
, i
);
4873 void i915_gem_detach_phys_object(struct drm_device
*dev
,
4874 struct drm_gem_object
*obj
)
4876 struct address_space
*mapping
= obj
->filp
->f_path
.dentry
->d_inode
->i_mapping
;
4877 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
4882 if (!obj_priv
->phys_obj
)
4884 vaddr
= obj_priv
->phys_obj
->handle
->vaddr
;
4886 page_count
= obj
->size
/ PAGE_SIZE
;
4888 for (i
= 0; i
< page_count
; i
++) {
4889 struct page
*page
= read_cache_page_gfp(mapping
, i
,
4890 GFP_HIGHUSER
| __GFP_RECLAIMABLE
);
4891 if (!IS_ERR(page
)) {
4892 char *dst
= kmap_atomic(page
);
4893 memcpy(dst
, vaddr
+ i
*PAGE_SIZE
, PAGE_SIZE
);
4896 drm_clflush_pages(&page
, 1);
4898 set_page_dirty(page
);
4899 mark_page_accessed(page
);
4900 page_cache_release(page
);
4903 drm_agp_chipset_flush(dev
);
4905 obj_priv
->phys_obj
->cur_obj
= NULL
;
4906 obj_priv
->phys_obj
= NULL
;
4910 i915_gem_attach_phys_object(struct drm_device
*dev
,
4911 struct drm_gem_object
*obj
,
4915 struct address_space
*mapping
= obj
->filp
->f_path
.dentry
->d_inode
->i_mapping
;
4916 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4917 struct drm_i915_gem_object
*obj_priv
;
4922 if (id
> I915_MAX_PHYS_OBJECT
)
4925 obj_priv
= to_intel_bo(obj
);
4927 if (obj_priv
->phys_obj
) {
4928 if (obj_priv
->phys_obj
->id
== id
)
4930 i915_gem_detach_phys_object(dev
, obj
);
4933 /* create a new object */
4934 if (!dev_priv
->mm
.phys_objs
[id
- 1]) {
4935 ret
= i915_gem_init_phys_object(dev
, id
,
4938 DRM_ERROR("failed to init phys object %d size: %zu\n", id
, obj
->size
);
4943 /* bind to the object */
4944 obj_priv
->phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
4945 obj_priv
->phys_obj
->cur_obj
= obj
;
4947 page_count
= obj
->size
/ PAGE_SIZE
;
4949 for (i
= 0; i
< page_count
; i
++) {
4953 page
= read_cache_page_gfp(mapping
, i
,
4954 GFP_HIGHUSER
| __GFP_RECLAIMABLE
);
4956 return PTR_ERR(page
);
4958 src
= kmap_atomic(page
);
4959 dst
= obj_priv
->phys_obj
->handle
->vaddr
+ (i
* PAGE_SIZE
);
4960 memcpy(dst
, src
, PAGE_SIZE
);
4963 mark_page_accessed(page
);
4964 page_cache_release(page
);
4971 i915_gem_phys_pwrite(struct drm_device
*dev
, struct drm_gem_object
*obj
,
4972 struct drm_i915_gem_pwrite
*args
,
4973 struct drm_file
*file_priv
)
4975 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
4978 char __user
*user_data
;
4980 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
4981 obj_addr
= obj_priv
->phys_obj
->handle
->vaddr
+ args
->offset
;
4983 DRM_DEBUG_DRIVER("obj_addr %p, %lld\n", obj_addr
, args
->size
);
4984 ret
= copy_from_user(obj_addr
, user_data
, args
->size
);
4988 drm_agp_chipset_flush(dev
);
4992 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
)
4994 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
4996 /* Clean up our request list when the client is going away, so that
4997 * later retire_requests won't dereference our soon-to-be-gone
5000 spin_lock(&file_priv
->mm
.lock
);
5001 while (!list_empty(&file_priv
->mm
.request_list
)) {
5002 struct drm_i915_gem_request
*request
;
5004 request
= list_first_entry(&file_priv
->mm
.request_list
,
5005 struct drm_i915_gem_request
,
5007 list_del(&request
->client_list
);
5008 request
->file_priv
= NULL
;
5010 spin_unlock(&file_priv
->mm
.lock
);
5014 i915_gpu_is_active(struct drm_device
*dev
)
5016 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
5019 lists_empty
= list_empty(&dev_priv
->mm
.flushing_list
) &&
5020 list_empty(&dev_priv
->mm
.active_list
);
5022 return !lists_empty
;
5026 i915_gem_inactive_shrink(struct shrinker
*shrinker
,
5030 struct drm_i915_private
*dev_priv
=
5031 container_of(shrinker
,
5032 struct drm_i915_private
,
5033 mm
.inactive_shrinker
);
5034 struct drm_device
*dev
= dev_priv
->dev
;
5035 struct drm_i915_gem_object
*obj
, *next
;
5038 if (!mutex_trylock(&dev
->struct_mutex
))
5041 /* "fast-path" to count number of available objects */
5042 if (nr_to_scan
== 0) {
5044 list_for_each_entry(obj
,
5045 &dev_priv
->mm
.inactive_list
,
5048 mutex_unlock(&dev
->struct_mutex
);
5049 return cnt
/ 100 * sysctl_vfs_cache_pressure
;
5053 /* first scan for clean buffers */
5054 i915_gem_retire_requests(dev
);
5056 list_for_each_entry_safe(obj
, next
,
5057 &dev_priv
->mm
.inactive_list
,
5059 if (i915_gem_object_is_purgeable(obj
)) {
5060 i915_gem_object_unbind(&obj
->base
);
5061 if (--nr_to_scan
== 0)
5066 /* second pass, evict/count anything still on the inactive list */
5068 list_for_each_entry_safe(obj
, next
,
5069 &dev_priv
->mm
.inactive_list
,
5072 i915_gem_object_unbind(&obj
->base
);
5078 if (nr_to_scan
&& i915_gpu_is_active(dev
)) {
5080 * We are desperate for pages, so as a last resort, wait
5081 * for the GPU to finish and discard whatever we can.
5082 * This has a dramatic impact to reduce the number of
5083 * OOM-killer events whilst running the GPU aggressively.
5085 if (i915_gpu_idle(dev
) == 0)
5088 mutex_unlock(&dev
->struct_mutex
);
5089 return cnt
/ 100 * sysctl_vfs_cache_pressure
;