2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/i915_drm.h>
31 #include "i915_trace.h"
32 #include "intel_drv.h"
33 #include <linux/shmem_fs.h>
34 #include <linux/slab.h>
35 #include <linux/swap.h>
36 #include <linux/pci.h>
37 #include <linux/dma-buf.h>
39 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
);
40 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
);
41 static __must_check
int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object
*obj
,
43 bool map_and_fenceable
,
45 static int i915_gem_phys_pwrite(struct drm_device
*dev
,
46 struct drm_i915_gem_object
*obj
,
47 struct drm_i915_gem_pwrite
*args
,
48 struct drm_file
*file
);
50 static void i915_gem_write_fence(struct drm_device
*dev
, int reg
,
51 struct drm_i915_gem_object
*obj
);
52 static void i915_gem_object_update_fence(struct drm_i915_gem_object
*obj
,
53 struct drm_i915_fence_reg
*fence
,
56 static int i915_gem_inactive_shrink(struct shrinker
*shrinker
,
57 struct shrink_control
*sc
);
58 static long i915_gem_purge(struct drm_i915_private
*dev_priv
, long target
);
59 static void i915_gem_shrink_all(struct drm_i915_private
*dev_priv
);
60 static void i915_gem_object_truncate(struct drm_i915_gem_object
*obj
);
62 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object
*obj
)
65 i915_gem_release_mmap(obj
);
67 /* As we do not have an associated fence register, we will force
68 * a tiling change if we ever need to acquire one.
70 obj
->fence_dirty
= false;
71 obj
->fence_reg
= I915_FENCE_REG_NONE
;
74 /* some bookkeeping */
75 static void i915_gem_info_add_obj(struct drm_i915_private
*dev_priv
,
78 dev_priv
->mm
.object_count
++;
79 dev_priv
->mm
.object_memory
+= size
;
82 static void i915_gem_info_remove_obj(struct drm_i915_private
*dev_priv
,
85 dev_priv
->mm
.object_count
--;
86 dev_priv
->mm
.object_memory
-= size
;
90 i915_gem_wait_for_error(struct i915_gpu_error
*error
)
94 #define EXIT_COND (!i915_reset_in_progress(error))
98 /* GPU is already declared terminally dead, give up. */
99 if (i915_terminally_wedged(error
))
103 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
104 * userspace. If it takes that long something really bad is going on and
105 * we should simply try to bail out and fail as gracefully as possible.
107 ret
= wait_event_interruptible_timeout(error
->reset_queue
,
111 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
113 } else if (ret
< 0) {
121 int i915_mutex_lock_interruptible(struct drm_device
*dev
)
123 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
126 ret
= i915_gem_wait_for_error(&dev_priv
->gpu_error
);
130 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
134 WARN_ON(i915_verify_lists(dev
));
139 i915_gem_object_is_inactive(struct drm_i915_gem_object
*obj
)
141 return obj
->gtt_space
&& !obj
->active
;
145 i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
146 struct drm_file
*file
)
148 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
149 struct drm_i915_gem_init
*args
= data
;
151 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
154 if (args
->gtt_start
>= args
->gtt_end
||
155 (args
->gtt_end
| args
->gtt_start
) & (PAGE_SIZE
- 1))
158 /* GEM with user mode setting was never supported on ilk and later. */
159 if (INTEL_INFO(dev
)->gen
>= 5)
162 mutex_lock(&dev
->struct_mutex
);
163 i915_gem_setup_global_gtt(dev
, args
->gtt_start
, args
->gtt_end
,
165 dev_priv
->gtt
.mappable_end
= args
->gtt_end
;
166 mutex_unlock(&dev
->struct_mutex
);
172 i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
173 struct drm_file
*file
)
175 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
176 struct drm_i915_gem_get_aperture
*args
= data
;
177 struct drm_i915_gem_object
*obj
;
181 mutex_lock(&dev
->struct_mutex
);
182 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, gtt_list
)
184 pinned
+= obj
->gtt_space
->size
;
185 mutex_unlock(&dev
->struct_mutex
);
187 args
->aper_size
= dev_priv
->gtt
.total
;
188 args
->aper_available_size
= args
->aper_size
- pinned
;
193 void *i915_gem_object_alloc(struct drm_device
*dev
)
195 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
196 return kmem_cache_alloc(dev_priv
->slab
, GFP_KERNEL
| __GFP_ZERO
);
199 void i915_gem_object_free(struct drm_i915_gem_object
*obj
)
201 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
202 kmem_cache_free(dev_priv
->slab
, obj
);
206 i915_gem_create(struct drm_file
*file
,
207 struct drm_device
*dev
,
211 struct drm_i915_gem_object
*obj
;
215 size
= roundup(size
, PAGE_SIZE
);
219 /* Allocate the new object */
220 obj
= i915_gem_alloc_object(dev
, size
);
224 ret
= drm_gem_handle_create(file
, &obj
->base
, &handle
);
226 drm_gem_object_release(&obj
->base
);
227 i915_gem_info_remove_obj(dev
->dev_private
, obj
->base
.size
);
228 i915_gem_object_free(obj
);
232 /* drop reference from allocate - handle holds it now */
233 drm_gem_object_unreference(&obj
->base
);
234 trace_i915_gem_object_create(obj
);
241 i915_gem_dumb_create(struct drm_file
*file
,
242 struct drm_device
*dev
,
243 struct drm_mode_create_dumb
*args
)
245 /* have to work out size/pitch and return them */
246 args
->pitch
= ALIGN(args
->width
* ((args
->bpp
+ 7) / 8), 64);
247 args
->size
= args
->pitch
* args
->height
;
248 return i915_gem_create(file
, dev
,
249 args
->size
, &args
->handle
);
252 int i915_gem_dumb_destroy(struct drm_file
*file
,
253 struct drm_device
*dev
,
256 return drm_gem_handle_delete(file
, handle
);
260 * Creates a new mm object and returns a handle to it.
263 i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
264 struct drm_file
*file
)
266 struct drm_i915_gem_create
*args
= data
;
268 return i915_gem_create(file
, dev
,
269 args
->size
, &args
->handle
);
273 __copy_to_user_swizzled(char __user
*cpu_vaddr
,
274 const char *gpu_vaddr
, int gpu_offset
,
277 int ret
, cpu_offset
= 0;
280 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
281 int this_length
= min(cacheline_end
- gpu_offset
, length
);
282 int swizzled_gpu_offset
= gpu_offset
^ 64;
284 ret
= __copy_to_user(cpu_vaddr
+ cpu_offset
,
285 gpu_vaddr
+ swizzled_gpu_offset
,
290 cpu_offset
+= this_length
;
291 gpu_offset
+= this_length
;
292 length
-= this_length
;
299 __copy_from_user_swizzled(char *gpu_vaddr
, int gpu_offset
,
300 const char __user
*cpu_vaddr
,
303 int ret
, cpu_offset
= 0;
306 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
307 int this_length
= min(cacheline_end
- gpu_offset
, length
);
308 int swizzled_gpu_offset
= gpu_offset
^ 64;
310 ret
= __copy_from_user(gpu_vaddr
+ swizzled_gpu_offset
,
311 cpu_vaddr
+ cpu_offset
,
316 cpu_offset
+= this_length
;
317 gpu_offset
+= this_length
;
318 length
-= this_length
;
324 /* Per-page copy function for the shmem pread fastpath.
325 * Flushes invalid cachelines before reading the target if
326 * needs_clflush is set. */
328 shmem_pread_fast(struct page
*page
, int shmem_page_offset
, int page_length
,
329 char __user
*user_data
,
330 bool page_do_bit17_swizzling
, bool needs_clflush
)
335 if (unlikely(page_do_bit17_swizzling
))
338 vaddr
= kmap_atomic(page
);
340 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
342 ret
= __copy_to_user_inatomic(user_data
,
343 vaddr
+ shmem_page_offset
,
345 kunmap_atomic(vaddr
);
347 return ret
? -EFAULT
: 0;
351 shmem_clflush_swizzled_range(char *addr
, unsigned long length
,
354 if (unlikely(swizzled
)) {
355 unsigned long start
= (unsigned long) addr
;
356 unsigned long end
= (unsigned long) addr
+ length
;
358 /* For swizzling simply ensure that we always flush both
359 * channels. Lame, but simple and it works. Swizzled
360 * pwrite/pread is far from a hotpath - current userspace
361 * doesn't use it at all. */
362 start
= round_down(start
, 128);
363 end
= round_up(end
, 128);
365 drm_clflush_virt_range((void *)start
, end
- start
);
367 drm_clflush_virt_range(addr
, length
);
372 /* Only difference to the fast-path function is that this can handle bit17
373 * and uses non-atomic copy and kmap functions. */
375 shmem_pread_slow(struct page
*page
, int shmem_page_offset
, int page_length
,
376 char __user
*user_data
,
377 bool page_do_bit17_swizzling
, bool needs_clflush
)
384 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
386 page_do_bit17_swizzling
);
388 if (page_do_bit17_swizzling
)
389 ret
= __copy_to_user_swizzled(user_data
,
390 vaddr
, shmem_page_offset
,
393 ret
= __copy_to_user(user_data
,
394 vaddr
+ shmem_page_offset
,
398 return ret
? - EFAULT
: 0;
402 i915_gem_shmem_pread(struct drm_device
*dev
,
403 struct drm_i915_gem_object
*obj
,
404 struct drm_i915_gem_pread
*args
,
405 struct drm_file
*file
)
407 char __user
*user_data
;
410 int shmem_page_offset
, page_length
, ret
= 0;
411 int obj_do_bit17_swizzling
, page_do_bit17_swizzling
;
413 int needs_clflush
= 0;
414 struct scatterlist
*sg
;
417 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
420 obj_do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
422 if (!(obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
)) {
423 /* If we're not in the cpu read domain, set ourself into the gtt
424 * read domain and manually flush cachelines (if required). This
425 * optimizes for the case when the gpu will dirty the data
426 * anyway again before the next pread happens. */
427 if (obj
->cache_level
== I915_CACHE_NONE
)
429 if (obj
->gtt_space
) {
430 ret
= i915_gem_object_set_to_gtt_domain(obj
, false);
436 ret
= i915_gem_object_get_pages(obj
);
440 i915_gem_object_pin_pages(obj
);
442 offset
= args
->offset
;
444 for_each_sg(obj
->pages
->sgl
, sg
, obj
->pages
->nents
, i
) {
447 if (i
< offset
>> PAGE_SHIFT
)
453 /* Operation in this page
455 * shmem_page_offset = offset within page in shmem file
456 * page_length = bytes to copy for this page
458 shmem_page_offset
= offset_in_page(offset
);
459 page_length
= remain
;
460 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
461 page_length
= PAGE_SIZE
- shmem_page_offset
;
464 page_do_bit17_swizzling
= obj_do_bit17_swizzling
&&
465 (page_to_phys(page
) & (1 << 17)) != 0;
467 ret
= shmem_pread_fast(page
, shmem_page_offset
, page_length
,
468 user_data
, page_do_bit17_swizzling
,
473 mutex_unlock(&dev
->struct_mutex
);
476 ret
= fault_in_multipages_writeable(user_data
, remain
);
477 /* Userspace is tricking us, but we've already clobbered
478 * its pages with the prefault and promised to write the
479 * data up to the first fault. Hence ignore any errors
480 * and just continue. */
485 ret
= shmem_pread_slow(page
, shmem_page_offset
, page_length
,
486 user_data
, page_do_bit17_swizzling
,
489 mutex_lock(&dev
->struct_mutex
);
492 mark_page_accessed(page
);
497 remain
-= page_length
;
498 user_data
+= page_length
;
499 offset
+= page_length
;
503 i915_gem_object_unpin_pages(obj
);
509 * Reads data from the object referenced by handle.
511 * On error, the contents of *data are undefined.
514 i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
515 struct drm_file
*file
)
517 struct drm_i915_gem_pread
*args
= data
;
518 struct drm_i915_gem_object
*obj
;
524 if (!access_ok(VERIFY_WRITE
,
525 (char __user
*)(uintptr_t)args
->data_ptr
,
529 ret
= i915_mutex_lock_interruptible(dev
);
533 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
534 if (&obj
->base
== NULL
) {
539 /* Bounds check source. */
540 if (args
->offset
> obj
->base
.size
||
541 args
->size
> obj
->base
.size
- args
->offset
) {
546 /* prime objects have no backing filp to GEM pread/pwrite
549 if (!obj
->base
.filp
) {
554 trace_i915_gem_object_pread(obj
, args
->offset
, args
->size
);
556 ret
= i915_gem_shmem_pread(dev
, obj
, args
, file
);
559 drm_gem_object_unreference(&obj
->base
);
561 mutex_unlock(&dev
->struct_mutex
);
565 /* This is the fast write path which cannot handle
566 * page faults in the source data
570 fast_user_write(struct io_mapping
*mapping
,
571 loff_t page_base
, int page_offset
,
572 char __user
*user_data
,
575 void __iomem
*vaddr_atomic
;
577 unsigned long unwritten
;
579 vaddr_atomic
= io_mapping_map_atomic_wc(mapping
, page_base
);
580 /* We can use the cpu mem copy function because this is X86. */
581 vaddr
= (void __force
*)vaddr_atomic
+ page_offset
;
582 unwritten
= __copy_from_user_inatomic_nocache(vaddr
,
584 io_mapping_unmap_atomic(vaddr_atomic
);
589 * This is the fast pwrite path, where we copy the data directly from the
590 * user into the GTT, uncached.
593 i915_gem_gtt_pwrite_fast(struct drm_device
*dev
,
594 struct drm_i915_gem_object
*obj
,
595 struct drm_i915_gem_pwrite
*args
,
596 struct drm_file
*file
)
598 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
600 loff_t offset
, page_base
;
601 char __user
*user_data
;
602 int page_offset
, page_length
, ret
;
604 ret
= i915_gem_object_pin(obj
, 0, true, true);
608 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
612 ret
= i915_gem_object_put_fence(obj
);
616 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
619 offset
= obj
->gtt_offset
+ args
->offset
;
622 /* Operation in this page
624 * page_base = page offset within aperture
625 * page_offset = offset within page
626 * page_length = bytes to copy for this page
628 page_base
= offset
& PAGE_MASK
;
629 page_offset
= offset_in_page(offset
);
630 page_length
= remain
;
631 if ((page_offset
+ remain
) > PAGE_SIZE
)
632 page_length
= PAGE_SIZE
- page_offset
;
634 /* If we get a fault while copying data, then (presumably) our
635 * source page isn't available. Return the error and we'll
636 * retry in the slow path.
638 if (fast_user_write(dev_priv
->gtt
.mappable
, page_base
,
639 page_offset
, user_data
, page_length
)) {
644 remain
-= page_length
;
645 user_data
+= page_length
;
646 offset
+= page_length
;
650 i915_gem_object_unpin(obj
);
655 /* Per-page copy function for the shmem pwrite fastpath.
656 * Flushes invalid cachelines before writing to the target if
657 * needs_clflush_before is set and flushes out any written cachelines after
658 * writing if needs_clflush is set. */
660 shmem_pwrite_fast(struct page
*page
, int shmem_page_offset
, int page_length
,
661 char __user
*user_data
,
662 bool page_do_bit17_swizzling
,
663 bool needs_clflush_before
,
664 bool needs_clflush_after
)
669 if (unlikely(page_do_bit17_swizzling
))
672 vaddr
= kmap_atomic(page
);
673 if (needs_clflush_before
)
674 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
676 ret
= __copy_from_user_inatomic_nocache(vaddr
+ shmem_page_offset
,
679 if (needs_clflush_after
)
680 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
682 kunmap_atomic(vaddr
);
684 return ret
? -EFAULT
: 0;
687 /* Only difference to the fast-path function is that this can handle bit17
688 * and uses non-atomic copy and kmap functions. */
690 shmem_pwrite_slow(struct page
*page
, int shmem_page_offset
, int page_length
,
691 char __user
*user_data
,
692 bool page_do_bit17_swizzling
,
693 bool needs_clflush_before
,
694 bool needs_clflush_after
)
700 if (unlikely(needs_clflush_before
|| page_do_bit17_swizzling
))
701 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
703 page_do_bit17_swizzling
);
704 if (page_do_bit17_swizzling
)
705 ret
= __copy_from_user_swizzled(vaddr
, shmem_page_offset
,
709 ret
= __copy_from_user(vaddr
+ shmem_page_offset
,
712 if (needs_clflush_after
)
713 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
715 page_do_bit17_swizzling
);
718 return ret
? -EFAULT
: 0;
722 i915_gem_shmem_pwrite(struct drm_device
*dev
,
723 struct drm_i915_gem_object
*obj
,
724 struct drm_i915_gem_pwrite
*args
,
725 struct drm_file
*file
)
729 char __user
*user_data
;
730 int shmem_page_offset
, page_length
, ret
= 0;
731 int obj_do_bit17_swizzling
, page_do_bit17_swizzling
;
732 int hit_slowpath
= 0;
733 int needs_clflush_after
= 0;
734 int needs_clflush_before
= 0;
736 struct scatterlist
*sg
;
738 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
741 obj_do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
743 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
744 /* If we're not in the cpu write domain, set ourself into the gtt
745 * write domain and manually flush cachelines (if required). This
746 * optimizes for the case when the gpu will use the data
747 * right away and we therefore have to clflush anyway. */
748 if (obj
->cache_level
== I915_CACHE_NONE
)
749 needs_clflush_after
= 1;
750 if (obj
->gtt_space
) {
751 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
756 /* Same trick applies for invalidate partially written cachelines before
758 if (!(obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
)
759 && obj
->cache_level
== I915_CACHE_NONE
)
760 needs_clflush_before
= 1;
762 ret
= i915_gem_object_get_pages(obj
);
766 i915_gem_object_pin_pages(obj
);
768 offset
= args
->offset
;
771 for_each_sg(obj
->pages
->sgl
, sg
, obj
->pages
->nents
, i
) {
773 int partial_cacheline_write
;
775 if (i
< offset
>> PAGE_SHIFT
)
781 /* Operation in this page
783 * shmem_page_offset = offset within page in shmem file
784 * page_length = bytes to copy for this page
786 shmem_page_offset
= offset_in_page(offset
);
788 page_length
= remain
;
789 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
790 page_length
= PAGE_SIZE
- shmem_page_offset
;
792 /* If we don't overwrite a cacheline completely we need to be
793 * careful to have up-to-date data by first clflushing. Don't
794 * overcomplicate things and flush the entire patch. */
795 partial_cacheline_write
= needs_clflush_before
&&
796 ((shmem_page_offset
| page_length
)
797 & (boot_cpu_data
.x86_clflush_size
- 1));
800 page_do_bit17_swizzling
= obj_do_bit17_swizzling
&&
801 (page_to_phys(page
) & (1 << 17)) != 0;
803 ret
= shmem_pwrite_fast(page
, shmem_page_offset
, page_length
,
804 user_data
, page_do_bit17_swizzling
,
805 partial_cacheline_write
,
806 needs_clflush_after
);
811 mutex_unlock(&dev
->struct_mutex
);
812 ret
= shmem_pwrite_slow(page
, shmem_page_offset
, page_length
,
813 user_data
, page_do_bit17_swizzling
,
814 partial_cacheline_write
,
815 needs_clflush_after
);
817 mutex_lock(&dev
->struct_mutex
);
820 set_page_dirty(page
);
821 mark_page_accessed(page
);
826 remain
-= page_length
;
827 user_data
+= page_length
;
828 offset
+= page_length
;
832 i915_gem_object_unpin_pages(obj
);
836 * Fixup: Flush cpu caches in case we didn't flush the dirty
837 * cachelines in-line while writing and the object moved
838 * out of the cpu write domain while we've dropped the lock.
840 if (!needs_clflush_after
&&
841 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
842 i915_gem_clflush_object(obj
);
843 i915_gem_chipset_flush(dev
);
847 if (needs_clflush_after
)
848 i915_gem_chipset_flush(dev
);
854 * Writes data to the object referenced by handle.
856 * On error, the contents of the buffer that were to be modified are undefined.
859 i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
860 struct drm_file
*file
)
862 struct drm_i915_gem_pwrite
*args
= data
;
863 struct drm_i915_gem_object
*obj
;
869 if (!access_ok(VERIFY_READ
,
870 (char __user
*)(uintptr_t)args
->data_ptr
,
874 ret
= fault_in_multipages_readable((char __user
*)(uintptr_t)args
->data_ptr
,
879 ret
= i915_mutex_lock_interruptible(dev
);
883 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
884 if (&obj
->base
== NULL
) {
889 /* Bounds check destination. */
890 if (args
->offset
> obj
->base
.size
||
891 args
->size
> obj
->base
.size
- args
->offset
) {
896 /* prime objects have no backing filp to GEM pread/pwrite
899 if (!obj
->base
.filp
) {
904 trace_i915_gem_object_pwrite(obj
, args
->offset
, args
->size
);
907 /* We can only do the GTT pwrite on untiled buffers, as otherwise
908 * it would end up going through the fenced access, and we'll get
909 * different detiling behavior between reading and writing.
910 * pread/pwrite currently are reading and writing from the CPU
911 * perspective, requiring manual detiling by the client.
914 ret
= i915_gem_phys_pwrite(dev
, obj
, args
, file
);
918 if (obj
->cache_level
== I915_CACHE_NONE
&&
919 obj
->tiling_mode
== I915_TILING_NONE
&&
920 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
921 ret
= i915_gem_gtt_pwrite_fast(dev
, obj
, args
, file
);
922 /* Note that the gtt paths might fail with non-page-backed user
923 * pointers (e.g. gtt mappings when moving data between
924 * textures). Fallback to the shmem path in that case. */
927 if (ret
== -EFAULT
|| ret
== -ENOSPC
)
928 ret
= i915_gem_shmem_pwrite(dev
, obj
, args
, file
);
931 drm_gem_object_unreference(&obj
->base
);
933 mutex_unlock(&dev
->struct_mutex
);
938 i915_gem_check_wedge(struct i915_gpu_error
*error
,
941 if (i915_reset_in_progress(error
)) {
942 /* Non-interruptible callers can't handle -EAGAIN, hence return
943 * -EIO unconditionally for these. */
947 /* Recovery complete, but the reset failed ... */
948 if (i915_terminally_wedged(error
))
958 * Compare seqno against outstanding lazy request. Emit a request if they are
962 i915_gem_check_olr(struct intel_ring_buffer
*ring
, u32 seqno
)
966 BUG_ON(!mutex_is_locked(&ring
->dev
->struct_mutex
));
969 if (seqno
== ring
->outstanding_lazy_request
)
970 ret
= i915_add_request(ring
, NULL
, NULL
);
976 * __wait_seqno - wait until execution of seqno has finished
977 * @ring: the ring expected to report seqno
979 * @reset_counter: reset sequence associated with the given seqno
980 * @interruptible: do an interruptible wait (normally yes)
981 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
983 * Note: It is of utmost importance that the passed in seqno and reset_counter
984 * values have been read by the caller in an smp safe manner. Where read-side
985 * locks are involved, it is sufficient to read the reset_counter before
986 * unlocking the lock that protects the seqno. For lockless tricks, the
987 * reset_counter _must_ be read before, and an appropriate smp_rmb must be
990 * Returns 0 if the seqno was found within the alloted time. Else returns the
991 * errno with remaining time filled in timeout argument.
993 static int __wait_seqno(struct intel_ring_buffer
*ring
, u32 seqno
,
994 unsigned reset_counter
,
995 bool interruptible
, struct timespec
*timeout
)
997 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
998 struct timespec before
, now
, wait_time
={1,0};
999 unsigned long timeout_jiffies
;
1001 bool wait_forever
= true;
1004 if (i915_seqno_passed(ring
->get_seqno(ring
, true), seqno
))
1007 trace_i915_gem_request_wait_begin(ring
, seqno
);
1009 if (timeout
!= NULL
) {
1010 wait_time
= *timeout
;
1011 wait_forever
= false;
1014 timeout_jiffies
= timespec_to_jiffies(&wait_time
);
1016 if (WARN_ON(!ring
->irq_get(ring
)))
1019 /* Record current time in case interrupted by signal, or wedged * */
1020 getrawmonotonic(&before
);
1023 (i915_seqno_passed(ring->get_seqno(ring, false), seqno) || \
1024 i915_reset_in_progress(&dev_priv->gpu_error) || \
1025 reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
1028 end
= wait_event_interruptible_timeout(ring
->irq_queue
,
1032 end
= wait_event_timeout(ring
->irq_queue
, EXIT_COND
,
1035 /* We need to check whether any gpu reset happened in between
1036 * the caller grabbing the seqno and now ... */
1037 if (reset_counter
!= atomic_read(&dev_priv
->gpu_error
.reset_counter
))
1040 /* ... but upgrade the -EGAIN to an -EIO if the gpu is truely
1042 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, interruptible
);
1045 } while (end
== 0 && wait_forever
);
1047 getrawmonotonic(&now
);
1049 ring
->irq_put(ring
);
1050 trace_i915_gem_request_wait_end(ring
, seqno
);
1054 struct timespec sleep_time
= timespec_sub(now
, before
);
1055 *timeout
= timespec_sub(*timeout
, sleep_time
);
1060 case -EAGAIN
: /* Wedged */
1061 case -ERESTARTSYS
: /* Signal */
1063 case 0: /* Timeout */
1065 set_normalized_timespec(timeout
, 0, 0);
1067 default: /* Completed */
1068 WARN_ON(end
< 0); /* We're not aware of other errors */
1074 * Waits for a sequence number to be signaled, and cleans up the
1075 * request and object lists appropriately for that event.
1078 i915_wait_seqno(struct intel_ring_buffer
*ring
, uint32_t seqno
)
1080 struct drm_device
*dev
= ring
->dev
;
1081 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1082 bool interruptible
= dev_priv
->mm
.interruptible
;
1085 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
1088 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, interruptible
);
1092 ret
= i915_gem_check_olr(ring
, seqno
);
1096 return __wait_seqno(ring
, seqno
,
1097 atomic_read(&dev_priv
->gpu_error
.reset_counter
),
1098 interruptible
, NULL
);
1102 * Ensures that all rendering to the object has completed and the object is
1103 * safe to unbind from the GTT or access from the CPU.
1105 static __must_check
int
1106 i915_gem_object_wait_rendering(struct drm_i915_gem_object
*obj
,
1109 struct intel_ring_buffer
*ring
= obj
->ring
;
1113 seqno
= readonly
? obj
->last_write_seqno
: obj
->last_read_seqno
;
1117 ret
= i915_wait_seqno(ring
, seqno
);
1121 i915_gem_retire_requests_ring(ring
);
1123 /* Manually manage the write flush as we may have not yet
1124 * retired the buffer.
1126 if (obj
->last_write_seqno
&&
1127 i915_seqno_passed(seqno
, obj
->last_write_seqno
)) {
1128 obj
->last_write_seqno
= 0;
1129 obj
->base
.write_domain
&= ~I915_GEM_GPU_DOMAINS
;
1135 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1136 * as the object state may change during this call.
1138 static __must_check
int
1139 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object
*obj
,
1142 struct drm_device
*dev
= obj
->base
.dev
;
1143 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1144 struct intel_ring_buffer
*ring
= obj
->ring
;
1145 unsigned reset_counter
;
1149 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
1150 BUG_ON(!dev_priv
->mm
.interruptible
);
1152 seqno
= readonly
? obj
->last_write_seqno
: obj
->last_read_seqno
;
1156 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, true);
1160 ret
= i915_gem_check_olr(ring
, seqno
);
1164 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
1165 mutex_unlock(&dev
->struct_mutex
);
1166 ret
= __wait_seqno(ring
, seqno
, reset_counter
, true, NULL
);
1167 mutex_lock(&dev
->struct_mutex
);
1169 i915_gem_retire_requests_ring(ring
);
1171 /* Manually manage the write flush as we may have not yet
1172 * retired the buffer.
1174 if (obj
->last_write_seqno
&&
1175 i915_seqno_passed(seqno
, obj
->last_write_seqno
)) {
1176 obj
->last_write_seqno
= 0;
1177 obj
->base
.write_domain
&= ~I915_GEM_GPU_DOMAINS
;
1184 * Called when user space prepares to use an object with the CPU, either
1185 * through the mmap ioctl's mapping or a GTT mapping.
1188 i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
1189 struct drm_file
*file
)
1191 struct drm_i915_gem_set_domain
*args
= data
;
1192 struct drm_i915_gem_object
*obj
;
1193 uint32_t read_domains
= args
->read_domains
;
1194 uint32_t write_domain
= args
->write_domain
;
1197 /* Only handle setting domains to types used by the CPU. */
1198 if (write_domain
& I915_GEM_GPU_DOMAINS
)
1201 if (read_domains
& I915_GEM_GPU_DOMAINS
)
1204 /* Having something in the write domain implies it's in the read
1205 * domain, and only that read domain. Enforce that in the request.
1207 if (write_domain
!= 0 && read_domains
!= write_domain
)
1210 ret
= i915_mutex_lock_interruptible(dev
);
1214 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1215 if (&obj
->base
== NULL
) {
1220 /* Try to flush the object off the GPU without holding the lock.
1221 * We will repeat the flush holding the lock in the normal manner
1222 * to catch cases where we are gazumped.
1224 ret
= i915_gem_object_wait_rendering__nonblocking(obj
, !write_domain
);
1228 if (read_domains
& I915_GEM_DOMAIN_GTT
) {
1229 ret
= i915_gem_object_set_to_gtt_domain(obj
, write_domain
!= 0);
1231 /* Silently promote "you're not bound, there was nothing to do"
1232 * to success, since the client was just asking us to
1233 * make sure everything was done.
1238 ret
= i915_gem_object_set_to_cpu_domain(obj
, write_domain
!= 0);
1242 drm_gem_object_unreference(&obj
->base
);
1244 mutex_unlock(&dev
->struct_mutex
);
1249 * Called when user space has done writes to this buffer
1252 i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1253 struct drm_file
*file
)
1255 struct drm_i915_gem_sw_finish
*args
= data
;
1256 struct drm_i915_gem_object
*obj
;
1259 ret
= i915_mutex_lock_interruptible(dev
);
1263 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1264 if (&obj
->base
== NULL
) {
1269 /* Pinned buffers may be scanout, so flush the cache */
1271 i915_gem_object_flush_cpu_write_domain(obj
);
1273 drm_gem_object_unreference(&obj
->base
);
1275 mutex_unlock(&dev
->struct_mutex
);
1280 * Maps the contents of an object, returning the address it is mapped
1283 * While the mapping holds a reference on the contents of the object, it doesn't
1284 * imply a ref on the object itself.
1287 i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1288 struct drm_file
*file
)
1290 struct drm_i915_gem_mmap
*args
= data
;
1291 struct drm_gem_object
*obj
;
1294 obj
= drm_gem_object_lookup(dev
, file
, args
->handle
);
1298 /* prime objects have no backing filp to GEM mmap
1302 drm_gem_object_unreference_unlocked(obj
);
1306 addr
= vm_mmap(obj
->filp
, 0, args
->size
,
1307 PROT_READ
| PROT_WRITE
, MAP_SHARED
,
1309 drm_gem_object_unreference_unlocked(obj
);
1310 if (IS_ERR((void *)addr
))
1313 args
->addr_ptr
= (uint64_t) addr
;
1319 * i915_gem_fault - fault a page into the GTT
1320 * vma: VMA in question
1323 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1324 * from userspace. The fault handler takes care of binding the object to
1325 * the GTT (if needed), allocating and programming a fence register (again,
1326 * only if needed based on whether the old reg is still valid or the object
1327 * is tiled) and inserting a new PTE into the faulting process.
1329 * Note that the faulting process may involve evicting existing objects
1330 * from the GTT and/or fence registers to make room. So performance may
1331 * suffer if the GTT working set is large or there are few fence registers
1334 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
)
1336 struct drm_i915_gem_object
*obj
= to_intel_bo(vma
->vm_private_data
);
1337 struct drm_device
*dev
= obj
->base
.dev
;
1338 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1339 pgoff_t page_offset
;
1342 bool write
= !!(vmf
->flags
& FAULT_FLAG_WRITE
);
1344 /* We don't use vmf->pgoff since that has the fake offset */
1345 page_offset
= ((unsigned long)vmf
->virtual_address
- vma
->vm_start
) >>
1348 ret
= i915_mutex_lock_interruptible(dev
);
1352 trace_i915_gem_object_fault(obj
, page_offset
, true, write
);
1354 /* Access to snoopable pages through the GTT is incoherent. */
1355 if (obj
->cache_level
!= I915_CACHE_NONE
&& !HAS_LLC(dev
)) {
1360 /* Now bind it into the GTT if needed */
1361 ret
= i915_gem_object_pin(obj
, 0, true, false);
1365 ret
= i915_gem_object_set_to_gtt_domain(obj
, write
);
1369 ret
= i915_gem_object_get_fence(obj
);
1373 obj
->fault_mappable
= true;
1375 pfn
= ((dev_priv
->gtt
.mappable_base
+ obj
->gtt_offset
) >> PAGE_SHIFT
) +
1378 /* Finally, remap it using the new GTT offset */
1379 ret
= vm_insert_pfn(vma
, (unsigned long)vmf
->virtual_address
, pfn
);
1381 i915_gem_object_unpin(obj
);
1383 mutex_unlock(&dev
->struct_mutex
);
1387 /* If this -EIO is due to a gpu hang, give the reset code a
1388 * chance to clean up the mess. Otherwise return the proper
1390 if (i915_terminally_wedged(&dev_priv
->gpu_error
))
1391 return VM_FAULT_SIGBUS
;
1393 /* Give the error handler a chance to run and move the
1394 * objects off the GPU active list. Next time we service the
1395 * fault, we should be able to transition the page into the
1396 * GTT without touching the GPU (and so avoid further
1397 * EIO/EGAIN). If the GPU is wedged, then there is no issue
1398 * with coherency, just lost writes.
1406 * EBUSY is ok: this just means that another thread
1407 * already did the job.
1409 return VM_FAULT_NOPAGE
;
1411 return VM_FAULT_OOM
;
1413 return VM_FAULT_SIGBUS
;
1415 WARN_ONCE(ret
, "unhandled error in i915_gem_fault: %i\n", ret
);
1416 return VM_FAULT_SIGBUS
;
1421 * i915_gem_release_mmap - remove physical page mappings
1422 * @obj: obj in question
1424 * Preserve the reservation of the mmapping with the DRM core code, but
1425 * relinquish ownership of the pages back to the system.
1427 * It is vital that we remove the page mapping if we have mapped a tiled
1428 * object through the GTT and then lose the fence register due to
1429 * resource pressure. Similarly if the object has been moved out of the
1430 * aperture, than pages mapped into userspace must be revoked. Removing the
1431 * mapping will then trigger a page fault on the next user access, allowing
1432 * fixup by i915_gem_fault().
1435 i915_gem_release_mmap(struct drm_i915_gem_object
*obj
)
1437 if (!obj
->fault_mappable
)
1440 if (obj
->base
.dev
->dev_mapping
)
1441 unmap_mapping_range(obj
->base
.dev
->dev_mapping
,
1442 (loff_t
)obj
->base
.map_list
.hash
.key
<<PAGE_SHIFT
,
1445 obj
->fault_mappable
= false;
1449 i915_gem_get_gtt_size(struct drm_device
*dev
, uint32_t size
, int tiling_mode
)
1453 if (INTEL_INFO(dev
)->gen
>= 4 ||
1454 tiling_mode
== I915_TILING_NONE
)
1457 /* Previous chips need a power-of-two fence region when tiling */
1458 if (INTEL_INFO(dev
)->gen
== 3)
1459 gtt_size
= 1024*1024;
1461 gtt_size
= 512*1024;
1463 while (gtt_size
< size
)
1470 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1471 * @obj: object to check
1473 * Return the required GTT alignment for an object, taking into account
1474 * potential fence register mapping.
1477 i915_gem_get_gtt_alignment(struct drm_device
*dev
, uint32_t size
,
1478 int tiling_mode
, bool fenced
)
1481 * Minimum alignment is 4k (GTT page size), but might be greater
1482 * if a fence register is needed for the object.
1484 if (INTEL_INFO(dev
)->gen
>= 4 || (!fenced
&& IS_G33(dev
)) ||
1485 tiling_mode
== I915_TILING_NONE
)
1489 * Previous chips need to be aligned to the size of the smallest
1490 * fence register that can contain the object.
1492 return i915_gem_get_gtt_size(dev
, size
, tiling_mode
);
1495 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object
*obj
)
1497 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
1500 if (obj
->base
.map_list
.map
)
1503 dev_priv
->mm
.shrinker_no_lock_stealing
= true;
1505 ret
= drm_gem_create_mmap_offset(&obj
->base
);
1509 /* Badly fragmented mmap space? The only way we can recover
1510 * space is by destroying unwanted objects. We can't randomly release
1511 * mmap_offsets as userspace expects them to be persistent for the
1512 * lifetime of the objects. The closest we can is to release the
1513 * offsets on purgeable objects by truncating it and marking it purged,
1514 * which prevents userspace from ever using that object again.
1516 i915_gem_purge(dev_priv
, obj
->base
.size
>> PAGE_SHIFT
);
1517 ret
= drm_gem_create_mmap_offset(&obj
->base
);
1521 i915_gem_shrink_all(dev_priv
);
1522 ret
= drm_gem_create_mmap_offset(&obj
->base
);
1524 dev_priv
->mm
.shrinker_no_lock_stealing
= false;
1529 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object
*obj
)
1531 if (!obj
->base
.map_list
.map
)
1534 drm_gem_free_mmap_offset(&obj
->base
);
1538 i915_gem_mmap_gtt(struct drm_file
*file
,
1539 struct drm_device
*dev
,
1543 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1544 struct drm_i915_gem_object
*obj
;
1547 ret
= i915_mutex_lock_interruptible(dev
);
1551 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, handle
));
1552 if (&obj
->base
== NULL
) {
1557 if (obj
->base
.size
> dev_priv
->gtt
.mappable_end
) {
1562 if (obj
->madv
!= I915_MADV_WILLNEED
) {
1563 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1568 ret
= i915_gem_object_create_mmap_offset(obj
);
1572 *offset
= (u64
)obj
->base
.map_list
.hash
.key
<< PAGE_SHIFT
;
1575 drm_gem_object_unreference(&obj
->base
);
1577 mutex_unlock(&dev
->struct_mutex
);
1582 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1584 * @data: GTT mapping ioctl data
1585 * @file: GEM object info
1587 * Simply returns the fake offset to userspace so it can mmap it.
1588 * The mmap call will end up in drm_gem_mmap(), which will set things
1589 * up so we can get faults in the handler above.
1591 * The fault handler will take care of binding the object into the GTT
1592 * (since it may have been evicted to make room for something), allocating
1593 * a fence register, and mapping the appropriate aperture address into
1597 i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
1598 struct drm_file
*file
)
1600 struct drm_i915_gem_mmap_gtt
*args
= data
;
1602 return i915_gem_mmap_gtt(file
, dev
, args
->handle
, &args
->offset
);
1605 /* Immediately discard the backing storage */
1607 i915_gem_object_truncate(struct drm_i915_gem_object
*obj
)
1609 struct inode
*inode
;
1611 i915_gem_object_free_mmap_offset(obj
);
1613 if (obj
->base
.filp
== NULL
)
1616 /* Our goal here is to return as much of the memory as
1617 * is possible back to the system as we are called from OOM.
1618 * To do this we must instruct the shmfs to drop all of its
1619 * backing pages, *now*.
1621 inode
= obj
->base
.filp
->f_path
.dentry
->d_inode
;
1622 shmem_truncate_range(inode
, 0, (loff_t
)-1);
1624 obj
->madv
= __I915_MADV_PURGED
;
1628 i915_gem_object_is_purgeable(struct drm_i915_gem_object
*obj
)
1630 return obj
->madv
== I915_MADV_DONTNEED
;
1634 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object
*obj
)
1636 int page_count
= obj
->base
.size
/ PAGE_SIZE
;
1637 struct scatterlist
*sg
;
1640 BUG_ON(obj
->madv
== __I915_MADV_PURGED
);
1642 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
1644 /* In the event of a disaster, abandon all caches and
1645 * hope for the best.
1647 WARN_ON(ret
!= -EIO
);
1648 i915_gem_clflush_object(obj
);
1649 obj
->base
.read_domains
= obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
1652 if (i915_gem_object_needs_bit17_swizzle(obj
))
1653 i915_gem_object_save_bit_17_swizzle(obj
);
1655 if (obj
->madv
== I915_MADV_DONTNEED
)
1658 for_each_sg(obj
->pages
->sgl
, sg
, page_count
, i
) {
1659 struct page
*page
= sg_page(sg
);
1662 set_page_dirty(page
);
1664 if (obj
->madv
== I915_MADV_WILLNEED
)
1665 mark_page_accessed(page
);
1667 page_cache_release(page
);
1671 sg_free_table(obj
->pages
);
1676 i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
)
1678 const struct drm_i915_gem_object_ops
*ops
= obj
->ops
;
1680 if (obj
->pages
== NULL
)
1683 BUG_ON(obj
->gtt_space
);
1685 if (obj
->pages_pin_count
)
1688 /* ->put_pages might need to allocate memory for the bit17 swizzle
1689 * array, hence protect them from being reaped by removing them from gtt
1691 list_del(&obj
->gtt_list
);
1693 ops
->put_pages(obj
);
1696 if (i915_gem_object_is_purgeable(obj
))
1697 i915_gem_object_truncate(obj
);
1703 __i915_gem_shrink(struct drm_i915_private
*dev_priv
, long target
,
1704 bool purgeable_only
)
1706 struct drm_i915_gem_object
*obj
, *next
;
1709 list_for_each_entry_safe(obj
, next
,
1710 &dev_priv
->mm
.unbound_list
,
1712 if ((i915_gem_object_is_purgeable(obj
) || !purgeable_only
) &&
1713 i915_gem_object_put_pages(obj
) == 0) {
1714 count
+= obj
->base
.size
>> PAGE_SHIFT
;
1715 if (count
>= target
)
1720 list_for_each_entry_safe(obj
, next
,
1721 &dev_priv
->mm
.inactive_list
,
1723 if ((i915_gem_object_is_purgeable(obj
) || !purgeable_only
) &&
1724 i915_gem_object_unbind(obj
) == 0 &&
1725 i915_gem_object_put_pages(obj
) == 0) {
1726 count
+= obj
->base
.size
>> PAGE_SHIFT
;
1727 if (count
>= target
)
1736 i915_gem_purge(struct drm_i915_private
*dev_priv
, long target
)
1738 return __i915_gem_shrink(dev_priv
, target
, true);
1742 i915_gem_shrink_all(struct drm_i915_private
*dev_priv
)
1744 struct drm_i915_gem_object
*obj
, *next
;
1746 i915_gem_evict_everything(dev_priv
->dev
);
1748 list_for_each_entry_safe(obj
, next
, &dev_priv
->mm
.unbound_list
, gtt_list
)
1749 i915_gem_object_put_pages(obj
);
1753 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object
*obj
)
1755 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
1757 struct address_space
*mapping
;
1758 struct sg_table
*st
;
1759 struct scatterlist
*sg
;
1763 /* Assert that the object is not currently in any GPU domain. As it
1764 * wasn't in the GTT, there shouldn't be any way it could have been in
1767 BUG_ON(obj
->base
.read_domains
& I915_GEM_GPU_DOMAINS
);
1768 BUG_ON(obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
);
1770 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
1774 page_count
= obj
->base
.size
/ PAGE_SIZE
;
1775 if (sg_alloc_table(st
, page_count
, GFP_KERNEL
)) {
1781 /* Get the list of pages out of our struct file. They'll be pinned
1782 * at this point until we release them.
1784 * Fail silently without starting the shrinker
1786 mapping
= obj
->base
.filp
->f_path
.dentry
->d_inode
->i_mapping
;
1787 gfp
= mapping_gfp_mask(mapping
);
1788 gfp
|= __GFP_NORETRY
| __GFP_NOWARN
| __GFP_NO_KSWAPD
;
1789 gfp
&= ~(__GFP_IO
| __GFP_WAIT
);
1790 for_each_sg(st
->sgl
, sg
, page_count
, i
) {
1791 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
1793 i915_gem_purge(dev_priv
, page_count
);
1794 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
1797 /* We've tried hard to allocate the memory by reaping
1798 * our own buffer, now let the real VM do its job and
1799 * go down in flames if truly OOM.
1801 gfp
&= ~(__GFP_NORETRY
| __GFP_NOWARN
| __GFP_NO_KSWAPD
);
1802 gfp
|= __GFP_IO
| __GFP_WAIT
;
1804 i915_gem_shrink_all(dev_priv
);
1805 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
1809 gfp
|= __GFP_NORETRY
| __GFP_NOWARN
| __GFP_NO_KSWAPD
;
1810 gfp
&= ~(__GFP_IO
| __GFP_WAIT
);
1813 sg_set_page(sg
, page
, PAGE_SIZE
, 0);
1818 if (i915_gem_object_needs_bit17_swizzle(obj
))
1819 i915_gem_object_do_bit_17_swizzle(obj
);
1824 for_each_sg(st
->sgl
, sg
, i
, page_count
)
1825 page_cache_release(sg_page(sg
));
1828 return PTR_ERR(page
);
1831 /* Ensure that the associated pages are gathered from the backing storage
1832 * and pinned into our object. i915_gem_object_get_pages() may be called
1833 * multiple times before they are released by a single call to
1834 * i915_gem_object_put_pages() - once the pages are no longer referenced
1835 * either as a result of memory pressure (reaping pages under the shrinker)
1836 * or as the object is itself released.
1839 i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
)
1841 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
1842 const struct drm_i915_gem_object_ops
*ops
= obj
->ops
;
1848 if (obj
->madv
!= I915_MADV_WILLNEED
) {
1849 DRM_ERROR("Attempting to obtain a purgeable object\n");
1853 BUG_ON(obj
->pages_pin_count
);
1855 ret
= ops
->get_pages(obj
);
1859 list_add_tail(&obj
->gtt_list
, &dev_priv
->mm
.unbound_list
);
1864 i915_gem_object_move_to_active(struct drm_i915_gem_object
*obj
,
1865 struct intel_ring_buffer
*ring
)
1867 struct drm_device
*dev
= obj
->base
.dev
;
1868 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1869 u32 seqno
= intel_ring_get_seqno(ring
);
1871 BUG_ON(ring
== NULL
);
1874 /* Add a reference if we're newly entering the active list. */
1876 drm_gem_object_reference(&obj
->base
);
1880 /* Move from whatever list we were on to the tail of execution. */
1881 list_move_tail(&obj
->mm_list
, &dev_priv
->mm
.active_list
);
1882 list_move_tail(&obj
->ring_list
, &ring
->active_list
);
1884 obj
->last_read_seqno
= seqno
;
1886 if (obj
->fenced_gpu_access
) {
1887 obj
->last_fenced_seqno
= seqno
;
1889 /* Bump MRU to take account of the delayed flush */
1890 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
1891 struct drm_i915_fence_reg
*reg
;
1893 reg
= &dev_priv
->fence_regs
[obj
->fence_reg
];
1894 list_move_tail(®
->lru_list
,
1895 &dev_priv
->mm
.fence_list
);
1901 i915_gem_object_move_to_inactive(struct drm_i915_gem_object
*obj
)
1903 struct drm_device
*dev
= obj
->base
.dev
;
1904 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1906 BUG_ON(obj
->base
.write_domain
& ~I915_GEM_GPU_DOMAINS
);
1907 BUG_ON(!obj
->active
);
1909 list_move_tail(&obj
->mm_list
, &dev_priv
->mm
.inactive_list
);
1911 list_del_init(&obj
->ring_list
);
1914 obj
->last_read_seqno
= 0;
1915 obj
->last_write_seqno
= 0;
1916 obj
->base
.write_domain
= 0;
1918 obj
->last_fenced_seqno
= 0;
1919 obj
->fenced_gpu_access
= false;
1922 drm_gem_object_unreference(&obj
->base
);
1924 WARN_ON(i915_verify_lists(dev
));
1928 i915_gem_init_seqno(struct drm_device
*dev
, u32 seqno
)
1930 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1931 struct intel_ring_buffer
*ring
;
1934 /* Carefully retire all requests without writing to the rings */
1935 for_each_ring(ring
, dev_priv
, i
) {
1936 ret
= intel_ring_idle(ring
);
1940 i915_gem_retire_requests(dev
);
1942 /* Finally reset hw state */
1943 for_each_ring(ring
, dev_priv
, i
) {
1944 intel_ring_init_seqno(ring
, seqno
);
1946 for (j
= 0; j
< ARRAY_SIZE(ring
->sync_seqno
); j
++)
1947 ring
->sync_seqno
[j
] = 0;
1953 int i915_gem_set_seqno(struct drm_device
*dev
, u32 seqno
)
1955 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1961 /* HWS page needs to be set less than what we
1962 * will inject to ring
1964 ret
= i915_gem_init_seqno(dev
, seqno
- 1);
1968 /* Carefully set the last_seqno value so that wrap
1969 * detection still works
1971 dev_priv
->next_seqno
= seqno
;
1972 dev_priv
->last_seqno
= seqno
- 1;
1973 if (dev_priv
->last_seqno
== 0)
1974 dev_priv
->last_seqno
--;
1980 i915_gem_get_seqno(struct drm_device
*dev
, u32
*seqno
)
1982 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1984 /* reserve 0 for non-seqno */
1985 if (dev_priv
->next_seqno
== 0) {
1986 int ret
= i915_gem_init_seqno(dev
, 0);
1990 dev_priv
->next_seqno
= 1;
1993 *seqno
= dev_priv
->last_seqno
= dev_priv
->next_seqno
++;
1998 i915_add_request(struct intel_ring_buffer
*ring
,
1999 struct drm_file
*file
,
2002 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
2003 struct drm_i915_gem_request
*request
;
2004 u32 request_ring_position
;
2009 * Emit any outstanding flushes - execbuf can fail to emit the flush
2010 * after having emitted the batchbuffer command. Hence we need to fix
2011 * things up similar to emitting the lazy request. The difference here
2012 * is that the flush _must_ happen before the next request, no matter
2015 ret
= intel_ring_flush_all_caches(ring
);
2019 request
= kmalloc(sizeof(*request
), GFP_KERNEL
);
2020 if (request
== NULL
)
2024 /* Record the position of the start of the request so that
2025 * should we detect the updated seqno part-way through the
2026 * GPU processing the request, we never over-estimate the
2027 * position of the head.
2029 request_ring_position
= intel_ring_get_tail(ring
);
2031 ret
= ring
->add_request(ring
);
2037 request
->seqno
= intel_ring_get_seqno(ring
);
2038 request
->ring
= ring
;
2039 request
->tail
= request_ring_position
;
2040 request
->emitted_jiffies
= jiffies
;
2041 was_empty
= list_empty(&ring
->request_list
);
2042 list_add_tail(&request
->list
, &ring
->request_list
);
2043 request
->file_priv
= NULL
;
2046 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
2048 spin_lock(&file_priv
->mm
.lock
);
2049 request
->file_priv
= file_priv
;
2050 list_add_tail(&request
->client_list
,
2051 &file_priv
->mm
.request_list
);
2052 spin_unlock(&file_priv
->mm
.lock
);
2055 trace_i915_gem_request_add(ring
, request
->seqno
);
2056 ring
->outstanding_lazy_request
= 0;
2058 if (!dev_priv
->mm
.suspended
) {
2059 if (i915_enable_hangcheck
) {
2060 mod_timer(&dev_priv
->gpu_error
.hangcheck_timer
,
2061 round_jiffies_up(jiffies
+ DRM_I915_HANGCHECK_JIFFIES
));
2064 queue_delayed_work(dev_priv
->wq
,
2065 &dev_priv
->mm
.retire_work
,
2066 round_jiffies_up_relative(HZ
));
2067 intel_mark_busy(dev_priv
->dev
);
2072 *out_seqno
= request
->seqno
;
2077 i915_gem_request_remove_from_client(struct drm_i915_gem_request
*request
)
2079 struct drm_i915_file_private
*file_priv
= request
->file_priv
;
2084 spin_lock(&file_priv
->mm
.lock
);
2085 if (request
->file_priv
) {
2086 list_del(&request
->client_list
);
2087 request
->file_priv
= NULL
;
2089 spin_unlock(&file_priv
->mm
.lock
);
2092 static void i915_gem_reset_ring_lists(struct drm_i915_private
*dev_priv
,
2093 struct intel_ring_buffer
*ring
)
2095 while (!list_empty(&ring
->request_list
)) {
2096 struct drm_i915_gem_request
*request
;
2098 request
= list_first_entry(&ring
->request_list
,
2099 struct drm_i915_gem_request
,
2102 list_del(&request
->list
);
2103 i915_gem_request_remove_from_client(request
);
2107 while (!list_empty(&ring
->active_list
)) {
2108 struct drm_i915_gem_object
*obj
;
2110 obj
= list_first_entry(&ring
->active_list
,
2111 struct drm_i915_gem_object
,
2114 i915_gem_object_move_to_inactive(obj
);
2118 static void i915_gem_reset_fences(struct drm_device
*dev
)
2120 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2123 for (i
= 0; i
< dev_priv
->num_fence_regs
; i
++) {
2124 struct drm_i915_fence_reg
*reg
= &dev_priv
->fence_regs
[i
];
2126 i915_gem_write_fence(dev
, i
, NULL
);
2129 i915_gem_object_fence_lost(reg
->obj
);
2133 INIT_LIST_HEAD(®
->lru_list
);
2136 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
2139 void i915_gem_reset(struct drm_device
*dev
)
2141 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2142 struct drm_i915_gem_object
*obj
;
2143 struct intel_ring_buffer
*ring
;
2146 for_each_ring(ring
, dev_priv
, i
)
2147 i915_gem_reset_ring_lists(dev_priv
, ring
);
2149 /* Move everything out of the GPU domains to ensure we do any
2150 * necessary invalidation upon reuse.
2152 list_for_each_entry(obj
,
2153 &dev_priv
->mm
.inactive_list
,
2156 obj
->base
.read_domains
&= ~I915_GEM_GPU_DOMAINS
;
2159 /* The fence registers are invalidated so clear them out */
2160 i915_gem_reset_fences(dev
);
2164 * This function clears the request list as sequence numbers are passed.
2167 i915_gem_retire_requests_ring(struct intel_ring_buffer
*ring
)
2171 if (list_empty(&ring
->request_list
))
2174 WARN_ON(i915_verify_lists(ring
->dev
));
2176 seqno
= ring
->get_seqno(ring
, true);
2178 while (!list_empty(&ring
->request_list
)) {
2179 struct drm_i915_gem_request
*request
;
2181 request
= list_first_entry(&ring
->request_list
,
2182 struct drm_i915_gem_request
,
2185 if (!i915_seqno_passed(seqno
, request
->seqno
))
2188 trace_i915_gem_request_retire(ring
, request
->seqno
);
2189 /* We know the GPU must have read the request to have
2190 * sent us the seqno + interrupt, so use the position
2191 * of tail of the request to update the last known position
2194 ring
->last_retired_head
= request
->tail
;
2196 list_del(&request
->list
);
2197 i915_gem_request_remove_from_client(request
);
2201 /* Move any buffers on the active list that are no longer referenced
2202 * by the ringbuffer to the flushing/inactive lists as appropriate.
2204 while (!list_empty(&ring
->active_list
)) {
2205 struct drm_i915_gem_object
*obj
;
2207 obj
= list_first_entry(&ring
->active_list
,
2208 struct drm_i915_gem_object
,
2211 if (!i915_seqno_passed(seqno
, obj
->last_read_seqno
))
2214 i915_gem_object_move_to_inactive(obj
);
2217 if (unlikely(ring
->trace_irq_seqno
&&
2218 i915_seqno_passed(seqno
, ring
->trace_irq_seqno
))) {
2219 ring
->irq_put(ring
);
2220 ring
->trace_irq_seqno
= 0;
2223 WARN_ON(i915_verify_lists(ring
->dev
));
2227 i915_gem_retire_requests(struct drm_device
*dev
)
2229 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2230 struct intel_ring_buffer
*ring
;
2233 for_each_ring(ring
, dev_priv
, i
)
2234 i915_gem_retire_requests_ring(ring
);
2238 i915_gem_retire_work_handler(struct work_struct
*work
)
2240 drm_i915_private_t
*dev_priv
;
2241 struct drm_device
*dev
;
2242 struct intel_ring_buffer
*ring
;
2246 dev_priv
= container_of(work
, drm_i915_private_t
,
2247 mm
.retire_work
.work
);
2248 dev
= dev_priv
->dev
;
2250 /* Come back later if the device is busy... */
2251 if (!mutex_trylock(&dev
->struct_mutex
)) {
2252 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
,
2253 round_jiffies_up_relative(HZ
));
2257 i915_gem_retire_requests(dev
);
2259 /* Send a periodic flush down the ring so we don't hold onto GEM
2260 * objects indefinitely.
2263 for_each_ring(ring
, dev_priv
, i
) {
2264 if (ring
->gpu_caches_dirty
)
2265 i915_add_request(ring
, NULL
, NULL
);
2267 idle
&= list_empty(&ring
->request_list
);
2270 if (!dev_priv
->mm
.suspended
&& !idle
)
2271 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
,
2272 round_jiffies_up_relative(HZ
));
2274 intel_mark_idle(dev
);
2276 mutex_unlock(&dev
->struct_mutex
);
2280 * Ensures that an object will eventually get non-busy by flushing any required
2281 * write domains, emitting any outstanding lazy request and retiring and
2282 * completed requests.
2285 i915_gem_object_flush_active(struct drm_i915_gem_object
*obj
)
2290 ret
= i915_gem_check_olr(obj
->ring
, obj
->last_read_seqno
);
2294 i915_gem_retire_requests_ring(obj
->ring
);
2301 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2302 * @DRM_IOCTL_ARGS: standard ioctl arguments
2304 * Returns 0 if successful, else an error is returned with the remaining time in
2305 * the timeout parameter.
2306 * -ETIME: object is still busy after timeout
2307 * -ERESTARTSYS: signal interrupted the wait
2308 * -ENONENT: object doesn't exist
2309 * Also possible, but rare:
2310 * -EAGAIN: GPU wedged
2312 * -ENODEV: Internal IRQ fail
2313 * -E?: The add request failed
2315 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2316 * non-zero timeout parameter the wait ioctl will wait for the given number of
2317 * nanoseconds on an object becoming unbusy. Since the wait itself does so
2318 * without holding struct_mutex the object may become re-busied before this
2319 * function completes. A similar but shorter * race condition exists in the busy
2323 i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
, struct drm_file
*file
)
2325 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2326 struct drm_i915_gem_wait
*args
= data
;
2327 struct drm_i915_gem_object
*obj
;
2328 struct intel_ring_buffer
*ring
= NULL
;
2329 struct timespec timeout_stack
, *timeout
= NULL
;
2330 unsigned reset_counter
;
2334 if (args
->timeout_ns
>= 0) {
2335 timeout_stack
= ns_to_timespec(args
->timeout_ns
);
2336 timeout
= &timeout_stack
;
2339 ret
= i915_mutex_lock_interruptible(dev
);
2343 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->bo_handle
));
2344 if (&obj
->base
== NULL
) {
2345 mutex_unlock(&dev
->struct_mutex
);
2349 /* Need to make sure the object gets inactive eventually. */
2350 ret
= i915_gem_object_flush_active(obj
);
2355 seqno
= obj
->last_read_seqno
;
2362 /* Do this after OLR check to make sure we make forward progress polling
2363 * on this IOCTL with a 0 timeout (like busy ioctl)
2365 if (!args
->timeout_ns
) {
2370 drm_gem_object_unreference(&obj
->base
);
2371 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
2372 mutex_unlock(&dev
->struct_mutex
);
2374 ret
= __wait_seqno(ring
, seqno
, reset_counter
, true, timeout
);
2376 WARN_ON(!timespec_valid(timeout
));
2377 args
->timeout_ns
= timespec_to_ns(timeout
);
2382 drm_gem_object_unreference(&obj
->base
);
2383 mutex_unlock(&dev
->struct_mutex
);
2388 * i915_gem_object_sync - sync an object to a ring.
2390 * @obj: object which may be in use on another ring.
2391 * @to: ring we wish to use the object on. May be NULL.
2393 * This code is meant to abstract object synchronization with the GPU.
2394 * Calling with NULL implies synchronizing the object with the CPU
2395 * rather than a particular GPU ring.
2397 * Returns 0 if successful, else propagates up the lower layer error.
2400 i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
2401 struct intel_ring_buffer
*to
)
2403 struct intel_ring_buffer
*from
= obj
->ring
;
2407 if (from
== NULL
|| to
== from
)
2410 if (to
== NULL
|| !i915_semaphore_is_enabled(obj
->base
.dev
))
2411 return i915_gem_object_wait_rendering(obj
, false);
2413 idx
= intel_ring_sync_index(from
, to
);
2415 seqno
= obj
->last_read_seqno
;
2416 if (seqno
<= from
->sync_seqno
[idx
])
2419 ret
= i915_gem_check_olr(obj
->ring
, seqno
);
2423 ret
= to
->sync_to(to
, from
, seqno
);
2425 /* We use last_read_seqno because sync_to()
2426 * might have just caused seqno wrap under
2429 from
->sync_seqno
[idx
] = obj
->last_read_seqno
;
2434 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object
*obj
)
2436 u32 old_write_domain
, old_read_domains
;
2438 /* Force a pagefault for domain tracking on next user access */
2439 i915_gem_release_mmap(obj
);
2441 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
) == 0)
2444 /* Wait for any direct GTT access to complete */
2447 old_read_domains
= obj
->base
.read_domains
;
2448 old_write_domain
= obj
->base
.write_domain
;
2450 obj
->base
.read_domains
&= ~I915_GEM_DOMAIN_GTT
;
2451 obj
->base
.write_domain
&= ~I915_GEM_DOMAIN_GTT
;
2453 trace_i915_gem_object_change_domain(obj
,
2459 * Unbinds an object from the GTT aperture.
2462 i915_gem_object_unbind(struct drm_i915_gem_object
*obj
)
2464 drm_i915_private_t
*dev_priv
= obj
->base
.dev
->dev_private
;
2467 if (obj
->gtt_space
== NULL
)
2473 BUG_ON(obj
->pages
== NULL
);
2475 ret
= i915_gem_object_finish_gpu(obj
);
2478 /* Continue on if we fail due to EIO, the GPU is hung so we
2479 * should be safe and we need to cleanup or else we might
2480 * cause memory corruption through use-after-free.
2483 i915_gem_object_finish_gtt(obj
);
2485 /* release the fence reg _after_ flushing */
2486 ret
= i915_gem_object_put_fence(obj
);
2490 trace_i915_gem_object_unbind(obj
);
2492 if (obj
->has_global_gtt_mapping
)
2493 i915_gem_gtt_unbind_object(obj
);
2494 if (obj
->has_aliasing_ppgtt_mapping
) {
2495 i915_ppgtt_unbind_object(dev_priv
->mm
.aliasing_ppgtt
, obj
);
2496 obj
->has_aliasing_ppgtt_mapping
= 0;
2498 i915_gem_gtt_finish_object(obj
);
2500 list_del(&obj
->mm_list
);
2501 list_move_tail(&obj
->gtt_list
, &dev_priv
->mm
.unbound_list
);
2502 /* Avoid an unnecessary call to unbind on rebind. */
2503 obj
->map_and_fenceable
= true;
2505 drm_mm_put_block(obj
->gtt_space
);
2506 obj
->gtt_space
= NULL
;
2507 obj
->gtt_offset
= 0;
2512 int i915_gpu_idle(struct drm_device
*dev
)
2514 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2515 struct intel_ring_buffer
*ring
;
2518 /* Flush everything onto the inactive list. */
2519 for_each_ring(ring
, dev_priv
, i
) {
2520 ret
= i915_switch_context(ring
, NULL
, DEFAULT_CONTEXT_ID
);
2524 ret
= intel_ring_idle(ring
);
2532 static void i965_write_fence_reg(struct drm_device
*dev
, int reg
,
2533 struct drm_i915_gem_object
*obj
)
2535 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2537 int fence_pitch_shift
;
2540 if (INTEL_INFO(dev
)->gen
>= 6) {
2541 fence_reg
= FENCE_REG_SANDYBRIDGE_0
;
2542 fence_pitch_shift
= SANDYBRIDGE_FENCE_PITCH_SHIFT
;
2544 fence_reg
= FENCE_REG_965_0
;
2545 fence_pitch_shift
= I965_FENCE_PITCH_SHIFT
;
2549 u32 size
= obj
->gtt_space
->size
;
2551 val
= (uint64_t)((obj
->gtt_offset
+ size
- 4096) &
2553 val
|= obj
->gtt_offset
& 0xfffff000;
2554 val
|= (uint64_t)((obj
->stride
/ 128) - 1) << fence_pitch_shift
;
2555 if (obj
->tiling_mode
== I915_TILING_Y
)
2556 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
2557 val
|= I965_FENCE_REG_VALID
;
2561 fence_reg
+= reg
* 8;
2562 I915_WRITE64(fence_reg
, val
);
2563 POSTING_READ(fence_reg
);
2566 static void i915_write_fence_reg(struct drm_device
*dev
, int reg
,
2567 struct drm_i915_gem_object
*obj
)
2569 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2573 u32 size
= obj
->gtt_space
->size
;
2577 WARN((obj
->gtt_offset
& ~I915_FENCE_START_MASK
) ||
2578 (size
& -size
) != size
||
2579 (obj
->gtt_offset
& (size
- 1)),
2580 "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2581 obj
->gtt_offset
, obj
->map_and_fenceable
, size
);
2583 if (obj
->tiling_mode
== I915_TILING_Y
&& HAS_128_BYTE_Y_TILING(dev
))
2588 /* Note: pitch better be a power of two tile widths */
2589 pitch_val
= obj
->stride
/ tile_width
;
2590 pitch_val
= ffs(pitch_val
) - 1;
2592 val
= obj
->gtt_offset
;
2593 if (obj
->tiling_mode
== I915_TILING_Y
)
2594 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2595 val
|= I915_FENCE_SIZE_BITS(size
);
2596 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2597 val
|= I830_FENCE_REG_VALID
;
2602 reg
= FENCE_REG_830_0
+ reg
* 4;
2604 reg
= FENCE_REG_945_8
+ (reg
- 8) * 4;
2606 I915_WRITE(reg
, val
);
2610 static void i830_write_fence_reg(struct drm_device
*dev
, int reg
,
2611 struct drm_i915_gem_object
*obj
)
2613 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2617 u32 size
= obj
->gtt_space
->size
;
2620 WARN((obj
->gtt_offset
& ~I830_FENCE_START_MASK
) ||
2621 (size
& -size
) != size
||
2622 (obj
->gtt_offset
& (size
- 1)),
2623 "object 0x%08x not 512K or pot-size 0x%08x aligned\n",
2624 obj
->gtt_offset
, size
);
2626 pitch_val
= obj
->stride
/ 128;
2627 pitch_val
= ffs(pitch_val
) - 1;
2629 val
= obj
->gtt_offset
;
2630 if (obj
->tiling_mode
== I915_TILING_Y
)
2631 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2632 val
|= I830_FENCE_SIZE_BITS(size
);
2633 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2634 val
|= I830_FENCE_REG_VALID
;
2638 I915_WRITE(FENCE_REG_830_0
+ reg
* 4, val
);
2639 POSTING_READ(FENCE_REG_830_0
+ reg
* 4);
2642 inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object
*obj
)
2644 return obj
&& obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
;
2647 static void i915_gem_write_fence(struct drm_device
*dev
, int reg
,
2648 struct drm_i915_gem_object
*obj
)
2650 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2652 /* Ensure that all CPU reads are completed before installing a fence
2653 * and all writes before removing the fence.
2655 if (i915_gem_object_needs_mb(dev_priv
->fence_regs
[reg
].obj
))
2658 switch (INTEL_INFO(dev
)->gen
) {
2662 case 4: i965_write_fence_reg(dev
, reg
, obj
); break;
2663 case 3: i915_write_fence_reg(dev
, reg
, obj
); break;
2664 case 2: i830_write_fence_reg(dev
, reg
, obj
); break;
2668 /* And similarly be paranoid that no direct access to this region
2669 * is reordered to before the fence is installed.
2671 if (i915_gem_object_needs_mb(obj
))
2675 static inline int fence_number(struct drm_i915_private
*dev_priv
,
2676 struct drm_i915_fence_reg
*fence
)
2678 return fence
- dev_priv
->fence_regs
;
2681 static void i915_gem_object_update_fence(struct drm_i915_gem_object
*obj
,
2682 struct drm_i915_fence_reg
*fence
,
2685 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2686 int reg
= fence_number(dev_priv
, fence
);
2688 i915_gem_write_fence(obj
->base
.dev
, reg
, enable
? obj
: NULL
);
2691 obj
->fence_reg
= reg
;
2693 list_move_tail(&fence
->lru_list
, &dev_priv
->mm
.fence_list
);
2695 obj
->fence_reg
= I915_FENCE_REG_NONE
;
2697 list_del_init(&fence
->lru_list
);
2702 i915_gem_object_wait_fence(struct drm_i915_gem_object
*obj
)
2704 if (obj
->last_fenced_seqno
) {
2705 int ret
= i915_wait_seqno(obj
->ring
, obj
->last_fenced_seqno
);
2709 obj
->last_fenced_seqno
= 0;
2712 obj
->fenced_gpu_access
= false;
2717 i915_gem_object_put_fence(struct drm_i915_gem_object
*obj
)
2719 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2722 ret
= i915_gem_object_wait_fence(obj
);
2726 if (obj
->fence_reg
== I915_FENCE_REG_NONE
)
2729 i915_gem_object_update_fence(obj
,
2730 &dev_priv
->fence_regs
[obj
->fence_reg
],
2732 i915_gem_object_fence_lost(obj
);
2737 static struct drm_i915_fence_reg
*
2738 i915_find_fence_reg(struct drm_device
*dev
)
2740 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2741 struct drm_i915_fence_reg
*reg
, *avail
;
2744 /* First try to find a free reg */
2746 for (i
= dev_priv
->fence_reg_start
; i
< dev_priv
->num_fence_regs
; i
++) {
2747 reg
= &dev_priv
->fence_regs
[i
];
2751 if (!reg
->pin_count
)
2758 /* None available, try to steal one or wait for a user to finish */
2759 list_for_each_entry(reg
, &dev_priv
->mm
.fence_list
, lru_list
) {
2770 * i915_gem_object_get_fence - set up fencing for an object
2771 * @obj: object to map through a fence reg
2773 * When mapping objects through the GTT, userspace wants to be able to write
2774 * to them without having to worry about swizzling if the object is tiled.
2775 * This function walks the fence regs looking for a free one for @obj,
2776 * stealing one if it can't find any.
2778 * It then sets up the reg based on the object's properties: address, pitch
2779 * and tiling format.
2781 * For an untiled surface, this removes any existing fence.
2784 i915_gem_object_get_fence(struct drm_i915_gem_object
*obj
)
2786 struct drm_device
*dev
= obj
->base
.dev
;
2787 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2788 bool enable
= obj
->tiling_mode
!= I915_TILING_NONE
;
2789 struct drm_i915_fence_reg
*reg
;
2792 /* Have we updated the tiling parameters upon the object and so
2793 * will need to serialise the write to the associated fence register?
2795 if (obj
->fence_dirty
) {
2796 ret
= i915_gem_object_wait_fence(obj
);
2801 /* Just update our place in the LRU if our fence is getting reused. */
2802 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
2803 reg
= &dev_priv
->fence_regs
[obj
->fence_reg
];
2804 if (!obj
->fence_dirty
) {
2805 list_move_tail(®
->lru_list
,
2806 &dev_priv
->mm
.fence_list
);
2809 } else if (enable
) {
2810 reg
= i915_find_fence_reg(dev
);
2815 struct drm_i915_gem_object
*old
= reg
->obj
;
2817 ret
= i915_gem_object_wait_fence(old
);
2821 i915_gem_object_fence_lost(old
);
2826 i915_gem_object_update_fence(obj
, reg
, enable
);
2827 obj
->fence_dirty
= false;
2832 static bool i915_gem_valid_gtt_space(struct drm_device
*dev
,
2833 struct drm_mm_node
*gtt_space
,
2834 unsigned long cache_level
)
2836 struct drm_mm_node
*other
;
2838 /* On non-LLC machines we have to be careful when putting differing
2839 * types of snoopable memory together to avoid the prefetcher
2840 * crossing memory domains and dying.
2845 if (gtt_space
== NULL
)
2848 if (list_empty(>t_space
->node_list
))
2851 other
= list_entry(gtt_space
->node_list
.prev
, struct drm_mm_node
, node_list
);
2852 if (other
->allocated
&& !other
->hole_follows
&& other
->color
!= cache_level
)
2855 other
= list_entry(gtt_space
->node_list
.next
, struct drm_mm_node
, node_list
);
2856 if (other
->allocated
&& !gtt_space
->hole_follows
&& other
->color
!= cache_level
)
2862 static void i915_gem_verify_gtt(struct drm_device
*dev
)
2865 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2866 struct drm_i915_gem_object
*obj
;
2869 list_for_each_entry(obj
, &dev_priv
->mm
.gtt_list
, gtt_list
) {
2870 if (obj
->gtt_space
== NULL
) {
2871 printk(KERN_ERR
"object found on GTT list with no space reserved\n");
2876 if (obj
->cache_level
!= obj
->gtt_space
->color
) {
2877 printk(KERN_ERR
"object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n",
2878 obj
->gtt_space
->start
,
2879 obj
->gtt_space
->start
+ obj
->gtt_space
->size
,
2881 obj
->gtt_space
->color
);
2886 if (!i915_gem_valid_gtt_space(dev
,
2888 obj
->cache_level
)) {
2889 printk(KERN_ERR
"invalid GTT space found at [%08lx, %08lx] - color=%x\n",
2890 obj
->gtt_space
->start
,
2891 obj
->gtt_space
->start
+ obj
->gtt_space
->size
,
2903 * Finds free space in the GTT aperture and binds the object there.
2906 i915_gem_object_bind_to_gtt(struct drm_i915_gem_object
*obj
,
2908 bool map_and_fenceable
,
2911 struct drm_device
*dev
= obj
->base
.dev
;
2912 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2913 struct drm_mm_node
*node
;
2914 u32 size
, fence_size
, fence_alignment
, unfenced_alignment
;
2915 bool mappable
, fenceable
;
2918 fence_size
= i915_gem_get_gtt_size(dev
,
2921 fence_alignment
= i915_gem_get_gtt_alignment(dev
,
2923 obj
->tiling_mode
, true);
2924 unfenced_alignment
=
2925 i915_gem_get_gtt_alignment(dev
,
2927 obj
->tiling_mode
, false);
2930 alignment
= map_and_fenceable
? fence_alignment
:
2932 if (map_and_fenceable
&& alignment
& (fence_alignment
- 1)) {
2933 DRM_ERROR("Invalid object alignment requested %u\n", alignment
);
2937 size
= map_and_fenceable
? fence_size
: obj
->base
.size
;
2939 /* If the object is bigger than the entire aperture, reject it early
2940 * before evicting everything in a vain attempt to find space.
2942 if (obj
->base
.size
>
2943 (map_and_fenceable
? dev_priv
->gtt
.mappable_end
: dev_priv
->gtt
.total
)) {
2944 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2948 ret
= i915_gem_object_get_pages(obj
);
2952 i915_gem_object_pin_pages(obj
);
2954 node
= kzalloc(sizeof(*node
), GFP_KERNEL
);
2956 i915_gem_object_unpin_pages(obj
);
2961 if (map_and_fenceable
)
2962 ret
= drm_mm_insert_node_in_range_generic(&dev_priv
->mm
.gtt_space
, node
,
2963 size
, alignment
, obj
->cache_level
,
2964 0, dev_priv
->gtt
.mappable_end
);
2966 ret
= drm_mm_insert_node_generic(&dev_priv
->mm
.gtt_space
, node
,
2967 size
, alignment
, obj
->cache_level
);
2969 ret
= i915_gem_evict_something(dev
, size
, alignment
,
2976 i915_gem_object_unpin_pages(obj
);
2980 if (WARN_ON(!i915_gem_valid_gtt_space(dev
, node
, obj
->cache_level
))) {
2981 i915_gem_object_unpin_pages(obj
);
2982 drm_mm_put_block(node
);
2986 ret
= i915_gem_gtt_prepare_object(obj
);
2988 i915_gem_object_unpin_pages(obj
);
2989 drm_mm_put_block(node
);
2993 list_move_tail(&obj
->gtt_list
, &dev_priv
->mm
.bound_list
);
2994 list_add_tail(&obj
->mm_list
, &dev_priv
->mm
.inactive_list
);
2996 obj
->gtt_space
= node
;
2997 obj
->gtt_offset
= node
->start
;
3000 node
->size
== fence_size
&&
3001 (node
->start
& (fence_alignment
- 1)) == 0;
3004 obj
->gtt_offset
+ obj
->base
.size
<= dev_priv
->gtt
.mappable_end
;
3006 obj
->map_and_fenceable
= mappable
&& fenceable
;
3008 i915_gem_object_unpin_pages(obj
);
3009 trace_i915_gem_object_bind(obj
, map_and_fenceable
);
3010 i915_gem_verify_gtt(dev
);
3015 i915_gem_clflush_object(struct drm_i915_gem_object
*obj
)
3017 /* If we don't have a page list set up, then we're not pinned
3018 * to GPU, and we can ignore the cache flush because it'll happen
3019 * again at bind time.
3021 if (obj
->pages
== NULL
)
3024 /* If the GPU is snooping the contents of the CPU cache,
3025 * we do not need to manually clear the CPU cache lines. However,
3026 * the caches are only snooped when the render cache is
3027 * flushed/invalidated. As we always have to emit invalidations
3028 * and flushes when moving into and out of the RENDER domain, correct
3029 * snooping behaviour occurs naturally as the result of our domain
3032 if (obj
->cache_level
!= I915_CACHE_NONE
)
3035 trace_i915_gem_object_clflush(obj
);
3037 drm_clflush_sg(obj
->pages
);
3040 /** Flushes the GTT write domain for the object if it's dirty. */
3042 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
)
3044 uint32_t old_write_domain
;
3046 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_GTT
)
3049 /* No actual flushing is required for the GTT write domain. Writes
3050 * to it immediately go to main memory as far as we know, so there's
3051 * no chipset flush. It also doesn't land in render cache.
3053 * However, we do have to enforce the order so that all writes through
3054 * the GTT land before any writes to the device, such as updates to
3059 old_write_domain
= obj
->base
.write_domain
;
3060 obj
->base
.write_domain
= 0;
3062 trace_i915_gem_object_change_domain(obj
,
3063 obj
->base
.read_domains
,
3067 /** Flushes the CPU write domain for the object if it's dirty. */
3069 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
)
3071 uint32_t old_write_domain
;
3073 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
)
3076 i915_gem_clflush_object(obj
);
3077 i915_gem_chipset_flush(obj
->base
.dev
);
3078 old_write_domain
= obj
->base
.write_domain
;
3079 obj
->base
.write_domain
= 0;
3081 trace_i915_gem_object_change_domain(obj
,
3082 obj
->base
.read_domains
,
3087 * Moves a single object to the GTT read, and possibly write domain.
3089 * This function returns when the move is complete, including waiting on
3093 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
, bool write
)
3095 drm_i915_private_t
*dev_priv
= obj
->base
.dev
->dev_private
;
3096 uint32_t old_write_domain
, old_read_domains
;
3099 /* Not valid to be called on unbound objects. */
3100 if (obj
->gtt_space
== NULL
)
3103 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_GTT
)
3106 ret
= i915_gem_object_wait_rendering(obj
, !write
);
3110 i915_gem_object_flush_cpu_write_domain(obj
);
3112 /* Serialise direct access to this object with the barriers for
3113 * coherent writes from the GPU, by effectively invalidating the
3114 * GTT domain upon first access.
3116 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
) == 0)
3119 old_write_domain
= obj
->base
.write_domain
;
3120 old_read_domains
= obj
->base
.read_domains
;
3122 /* It should now be out of any other write domains, and we can update
3123 * the domain values for our changes.
3125 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
3126 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
3128 obj
->base
.read_domains
= I915_GEM_DOMAIN_GTT
;
3129 obj
->base
.write_domain
= I915_GEM_DOMAIN_GTT
;
3133 trace_i915_gem_object_change_domain(obj
,
3137 /* And bump the LRU for this access */
3138 if (i915_gem_object_is_inactive(obj
))
3139 list_move_tail(&obj
->mm_list
, &dev_priv
->mm
.inactive_list
);
3144 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
3145 enum i915_cache_level cache_level
)
3147 struct drm_device
*dev
= obj
->base
.dev
;
3148 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3151 if (obj
->cache_level
== cache_level
)
3154 if (obj
->pin_count
) {
3155 DRM_DEBUG("can not change the cache level of pinned objects\n");
3159 if (!i915_gem_valid_gtt_space(dev
, obj
->gtt_space
, cache_level
)) {
3160 ret
= i915_gem_object_unbind(obj
);
3165 if (obj
->gtt_space
) {
3166 ret
= i915_gem_object_finish_gpu(obj
);
3170 i915_gem_object_finish_gtt(obj
);
3172 /* Before SandyBridge, you could not use tiling or fence
3173 * registers with snooped memory, so relinquish any fences
3174 * currently pointing to our region in the aperture.
3176 if (INTEL_INFO(dev
)->gen
< 6) {
3177 ret
= i915_gem_object_put_fence(obj
);
3182 if (obj
->has_global_gtt_mapping
)
3183 i915_gem_gtt_bind_object(obj
, cache_level
);
3184 if (obj
->has_aliasing_ppgtt_mapping
)
3185 i915_ppgtt_bind_object(dev_priv
->mm
.aliasing_ppgtt
,
3188 obj
->gtt_space
->color
= cache_level
;
3191 if (cache_level
== I915_CACHE_NONE
) {
3192 u32 old_read_domains
, old_write_domain
;
3194 /* If we're coming from LLC cached, then we haven't
3195 * actually been tracking whether the data is in the
3196 * CPU cache or not, since we only allow one bit set
3197 * in obj->write_domain and have been skipping the clflushes.
3198 * Just set it to the CPU cache for now.
3200 WARN_ON(obj
->base
.write_domain
& ~I915_GEM_DOMAIN_CPU
);
3201 WARN_ON(obj
->base
.read_domains
& ~I915_GEM_DOMAIN_CPU
);
3203 old_read_domains
= obj
->base
.read_domains
;
3204 old_write_domain
= obj
->base
.write_domain
;
3206 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
3207 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
3209 trace_i915_gem_object_change_domain(obj
,
3214 obj
->cache_level
= cache_level
;
3215 i915_gem_verify_gtt(dev
);
3219 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
3220 struct drm_file
*file
)
3222 struct drm_i915_gem_caching
*args
= data
;
3223 struct drm_i915_gem_object
*obj
;
3226 ret
= i915_mutex_lock_interruptible(dev
);
3230 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3231 if (&obj
->base
== NULL
) {
3236 args
->caching
= obj
->cache_level
!= I915_CACHE_NONE
;
3238 drm_gem_object_unreference(&obj
->base
);
3240 mutex_unlock(&dev
->struct_mutex
);
3244 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
3245 struct drm_file
*file
)
3247 struct drm_i915_gem_caching
*args
= data
;
3248 struct drm_i915_gem_object
*obj
;
3249 enum i915_cache_level level
;
3252 switch (args
->caching
) {
3253 case I915_CACHING_NONE
:
3254 level
= I915_CACHE_NONE
;
3256 case I915_CACHING_CACHED
:
3257 level
= I915_CACHE_LLC
;
3263 ret
= i915_mutex_lock_interruptible(dev
);
3267 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3268 if (&obj
->base
== NULL
) {
3273 ret
= i915_gem_object_set_cache_level(obj
, level
);
3275 drm_gem_object_unreference(&obj
->base
);
3277 mutex_unlock(&dev
->struct_mutex
);
3282 * Prepare buffer for display plane (scanout, cursors, etc).
3283 * Can be called from an uninterruptible phase (modesetting) and allows
3284 * any flushes to be pipelined (for pageflips).
3287 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
3289 struct intel_ring_buffer
*pipelined
)
3291 u32 old_read_domains
, old_write_domain
;
3294 if (pipelined
!= obj
->ring
) {
3295 ret
= i915_gem_object_sync(obj
, pipelined
);
3300 /* The display engine is not coherent with the LLC cache on gen6. As
3301 * a result, we make sure that the pinning that is about to occur is
3302 * done with uncached PTEs. This is lowest common denominator for all
3305 * However for gen6+, we could do better by using the GFDT bit instead
3306 * of uncaching, which would allow us to flush all the LLC-cached data
3307 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3309 ret
= i915_gem_object_set_cache_level(obj
, I915_CACHE_NONE
);
3313 /* As the user may map the buffer once pinned in the display plane
3314 * (e.g. libkms for the bootup splash), we have to ensure that we
3315 * always use map_and_fenceable for all scanout buffers.
3317 ret
= i915_gem_object_pin(obj
, alignment
, true, false);
3321 i915_gem_object_flush_cpu_write_domain(obj
);
3323 old_write_domain
= obj
->base
.write_domain
;
3324 old_read_domains
= obj
->base
.read_domains
;
3326 /* It should now be out of any other write domains, and we can update
3327 * the domain values for our changes.
3329 obj
->base
.write_domain
= 0;
3330 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
3332 trace_i915_gem_object_change_domain(obj
,
3340 i915_gem_object_finish_gpu(struct drm_i915_gem_object
*obj
)
3344 if ((obj
->base
.read_domains
& I915_GEM_GPU_DOMAINS
) == 0)
3347 ret
= i915_gem_object_wait_rendering(obj
, false);
3351 /* Ensure that we invalidate the GPU's caches and TLBs. */
3352 obj
->base
.read_domains
&= ~I915_GEM_GPU_DOMAINS
;
3357 * Moves a single object to the CPU read, and possibly write domain.
3359 * This function returns when the move is complete, including waiting on
3363 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
)
3365 uint32_t old_write_domain
, old_read_domains
;
3368 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_CPU
)
3371 ret
= i915_gem_object_wait_rendering(obj
, !write
);
3375 i915_gem_object_flush_gtt_write_domain(obj
);
3377 old_write_domain
= obj
->base
.write_domain
;
3378 old_read_domains
= obj
->base
.read_domains
;
3380 /* Flush the CPU cache if it's still invalid. */
3381 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) == 0) {
3382 i915_gem_clflush_object(obj
);
3384 obj
->base
.read_domains
|= I915_GEM_DOMAIN_CPU
;
3387 /* It should now be out of any other write domains, and we can update
3388 * the domain values for our changes.
3390 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
3392 /* If we're writing through the CPU, then the GPU read domains will
3393 * need to be invalidated at next use.
3396 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
3397 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
3400 trace_i915_gem_object_change_domain(obj
,
3407 /* Throttle our rendering by waiting until the ring has completed our requests
3408 * emitted over 20 msec ago.
3410 * Note that if we were to use the current jiffies each time around the loop,
3411 * we wouldn't escape the function with any frames outstanding if the time to
3412 * render a frame was over 20ms.
3414 * This should get us reasonable parallelism between CPU and GPU but also
3415 * relatively low latency when blocking on a particular request to finish.
3418 i915_gem_ring_throttle(struct drm_device
*dev
, struct drm_file
*file
)
3420 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3421 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
3422 unsigned long recent_enough
= jiffies
- msecs_to_jiffies(20);
3423 struct drm_i915_gem_request
*request
;
3424 struct intel_ring_buffer
*ring
= NULL
;
3425 unsigned reset_counter
;
3429 ret
= i915_gem_wait_for_error(&dev_priv
->gpu_error
);
3433 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, false);
3437 spin_lock(&file_priv
->mm
.lock
);
3438 list_for_each_entry(request
, &file_priv
->mm
.request_list
, client_list
) {
3439 if (time_after_eq(request
->emitted_jiffies
, recent_enough
))
3442 ring
= request
->ring
;
3443 seqno
= request
->seqno
;
3445 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
3446 spin_unlock(&file_priv
->mm
.lock
);
3451 ret
= __wait_seqno(ring
, seqno
, reset_counter
, true, NULL
);
3453 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, 0);
3459 i915_gem_object_pin(struct drm_i915_gem_object
*obj
,
3461 bool map_and_fenceable
,
3466 if (WARN_ON(obj
->pin_count
== DRM_I915_GEM_OBJECT_MAX_PIN_COUNT
))
3469 if (obj
->gtt_space
!= NULL
) {
3470 if ((alignment
&& obj
->gtt_offset
& (alignment
- 1)) ||
3471 (map_and_fenceable
&& !obj
->map_and_fenceable
)) {
3472 WARN(obj
->pin_count
,
3473 "bo is already pinned with incorrect alignment:"
3474 " offset=%x, req.alignment=%x, req.map_and_fenceable=%d,"
3475 " obj->map_and_fenceable=%d\n",
3476 obj
->gtt_offset
, alignment
,
3478 obj
->map_and_fenceable
);
3479 ret
= i915_gem_object_unbind(obj
);
3485 if (obj
->gtt_space
== NULL
) {
3486 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
3488 ret
= i915_gem_object_bind_to_gtt(obj
, alignment
,
3494 if (!dev_priv
->mm
.aliasing_ppgtt
)
3495 i915_gem_gtt_bind_object(obj
, obj
->cache_level
);
3498 if (!obj
->has_global_gtt_mapping
&& map_and_fenceable
)
3499 i915_gem_gtt_bind_object(obj
, obj
->cache_level
);
3502 obj
->pin_mappable
|= map_and_fenceable
;
3508 i915_gem_object_unpin(struct drm_i915_gem_object
*obj
)
3510 BUG_ON(obj
->pin_count
== 0);
3511 BUG_ON(obj
->gtt_space
== NULL
);
3513 if (--obj
->pin_count
== 0)
3514 obj
->pin_mappable
= false;
3518 i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
3519 struct drm_file
*file
)
3521 struct drm_i915_gem_pin
*args
= data
;
3522 struct drm_i915_gem_object
*obj
;
3525 ret
= i915_mutex_lock_interruptible(dev
);
3529 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3530 if (&obj
->base
== NULL
) {
3535 if (obj
->madv
!= I915_MADV_WILLNEED
) {
3536 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3541 if (obj
->pin_filp
!= NULL
&& obj
->pin_filp
!= file
) {
3542 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3548 if (obj
->user_pin_count
== 0) {
3549 ret
= i915_gem_object_pin(obj
, args
->alignment
, true, false);
3554 obj
->user_pin_count
++;
3555 obj
->pin_filp
= file
;
3557 /* XXX - flush the CPU caches for pinned objects
3558 * as the X server doesn't manage domains yet
3560 i915_gem_object_flush_cpu_write_domain(obj
);
3561 args
->offset
= obj
->gtt_offset
;
3563 drm_gem_object_unreference(&obj
->base
);
3565 mutex_unlock(&dev
->struct_mutex
);
3570 i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
3571 struct drm_file
*file
)
3573 struct drm_i915_gem_pin
*args
= data
;
3574 struct drm_i915_gem_object
*obj
;
3577 ret
= i915_mutex_lock_interruptible(dev
);
3581 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3582 if (&obj
->base
== NULL
) {
3587 if (obj
->pin_filp
!= file
) {
3588 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3593 obj
->user_pin_count
--;
3594 if (obj
->user_pin_count
== 0) {
3595 obj
->pin_filp
= NULL
;
3596 i915_gem_object_unpin(obj
);
3600 drm_gem_object_unreference(&obj
->base
);
3602 mutex_unlock(&dev
->struct_mutex
);
3607 i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
3608 struct drm_file
*file
)
3610 struct drm_i915_gem_busy
*args
= data
;
3611 struct drm_i915_gem_object
*obj
;
3614 ret
= i915_mutex_lock_interruptible(dev
);
3618 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3619 if (&obj
->base
== NULL
) {
3624 /* Count all active objects as busy, even if they are currently not used
3625 * by the gpu. Users of this interface expect objects to eventually
3626 * become non-busy without any further actions, therefore emit any
3627 * necessary flushes here.
3629 ret
= i915_gem_object_flush_active(obj
);
3631 args
->busy
= obj
->active
;
3633 BUILD_BUG_ON(I915_NUM_RINGS
> 16);
3634 args
->busy
|= intel_ring_flag(obj
->ring
) << 16;
3637 drm_gem_object_unreference(&obj
->base
);
3639 mutex_unlock(&dev
->struct_mutex
);
3644 i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
3645 struct drm_file
*file_priv
)
3647 return i915_gem_ring_throttle(dev
, file_priv
);
3651 i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
3652 struct drm_file
*file_priv
)
3654 struct drm_i915_gem_madvise
*args
= data
;
3655 struct drm_i915_gem_object
*obj
;
3658 switch (args
->madv
) {
3659 case I915_MADV_DONTNEED
:
3660 case I915_MADV_WILLNEED
:
3666 ret
= i915_mutex_lock_interruptible(dev
);
3670 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file_priv
, args
->handle
));
3671 if (&obj
->base
== NULL
) {
3676 if (obj
->pin_count
) {
3681 if (obj
->madv
!= __I915_MADV_PURGED
)
3682 obj
->madv
= args
->madv
;
3684 /* if the object is no longer attached, discard its backing storage */
3685 if (i915_gem_object_is_purgeable(obj
) && obj
->pages
== NULL
)
3686 i915_gem_object_truncate(obj
);
3688 args
->retained
= obj
->madv
!= __I915_MADV_PURGED
;
3691 drm_gem_object_unreference(&obj
->base
);
3693 mutex_unlock(&dev
->struct_mutex
);
3697 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
3698 const struct drm_i915_gem_object_ops
*ops
)
3700 INIT_LIST_HEAD(&obj
->mm_list
);
3701 INIT_LIST_HEAD(&obj
->gtt_list
);
3702 INIT_LIST_HEAD(&obj
->ring_list
);
3703 INIT_LIST_HEAD(&obj
->exec_list
);
3707 obj
->fence_reg
= I915_FENCE_REG_NONE
;
3708 obj
->madv
= I915_MADV_WILLNEED
;
3709 /* Avoid an unnecessary call to unbind on the first bind. */
3710 obj
->map_and_fenceable
= true;
3712 i915_gem_info_add_obj(obj
->base
.dev
->dev_private
, obj
->base
.size
);
3715 static const struct drm_i915_gem_object_ops i915_gem_object_ops
= {
3716 .get_pages
= i915_gem_object_get_pages_gtt
,
3717 .put_pages
= i915_gem_object_put_pages_gtt
,
3720 struct drm_i915_gem_object
*i915_gem_alloc_object(struct drm_device
*dev
,
3723 struct drm_i915_gem_object
*obj
;
3724 struct address_space
*mapping
;
3727 obj
= i915_gem_object_alloc(dev
);
3731 if (drm_gem_object_init(dev
, &obj
->base
, size
) != 0) {
3732 i915_gem_object_free(obj
);
3736 mask
= GFP_HIGHUSER
| __GFP_RECLAIMABLE
;
3737 if (IS_CRESTLINE(dev
) || IS_BROADWATER(dev
)) {
3738 /* 965gm cannot relocate objects above 4GiB. */
3739 mask
&= ~__GFP_HIGHMEM
;
3740 mask
|= __GFP_DMA32
;
3743 mapping
= obj
->base
.filp
->f_path
.dentry
->d_inode
->i_mapping
;
3744 mapping_set_gfp_mask(mapping
, mask
);
3746 i915_gem_object_init(obj
, &i915_gem_object_ops
);
3748 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
3749 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
3752 /* On some devices, we can have the GPU use the LLC (the CPU
3753 * cache) for about a 10% performance improvement
3754 * compared to uncached. Graphics requests other than
3755 * display scanout are coherent with the CPU in
3756 * accessing this cache. This means in this mode we
3757 * don't need to clflush on the CPU side, and on the
3758 * GPU side we only need to flush internal caches to
3759 * get data visible to the CPU.
3761 * However, we maintain the display planes as UC, and so
3762 * need to rebind when first used as such.
3764 obj
->cache_level
= I915_CACHE_LLC
;
3766 obj
->cache_level
= I915_CACHE_NONE
;
3771 int i915_gem_init_object(struct drm_gem_object
*obj
)
3778 void i915_gem_free_object(struct drm_gem_object
*gem_obj
)
3780 struct drm_i915_gem_object
*obj
= to_intel_bo(gem_obj
);
3781 struct drm_device
*dev
= obj
->base
.dev
;
3782 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3784 trace_i915_gem_object_destroy(obj
);
3787 i915_gem_detach_phys_object(dev
, obj
);
3790 if (WARN_ON(i915_gem_object_unbind(obj
) == -ERESTARTSYS
)) {
3791 bool was_interruptible
;
3793 was_interruptible
= dev_priv
->mm
.interruptible
;
3794 dev_priv
->mm
.interruptible
= false;
3796 WARN_ON(i915_gem_object_unbind(obj
));
3798 dev_priv
->mm
.interruptible
= was_interruptible
;
3801 obj
->pages_pin_count
= 0;
3802 i915_gem_object_put_pages(obj
);
3803 i915_gem_object_free_mmap_offset(obj
);
3804 i915_gem_object_release_stolen(obj
);
3808 if (obj
->base
.import_attach
)
3809 drm_prime_gem_destroy(&obj
->base
, NULL
);
3811 drm_gem_object_release(&obj
->base
);
3812 i915_gem_info_remove_obj(dev_priv
, obj
->base
.size
);
3815 i915_gem_object_free(obj
);
3819 i915_gem_idle(struct drm_device
*dev
)
3821 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3824 mutex_lock(&dev
->struct_mutex
);
3826 if (dev_priv
->mm
.suspended
) {
3827 mutex_unlock(&dev
->struct_mutex
);
3831 ret
= i915_gpu_idle(dev
);
3833 mutex_unlock(&dev
->struct_mutex
);
3836 i915_gem_retire_requests(dev
);
3838 /* Under UMS, be paranoid and evict. */
3839 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
3840 i915_gem_evict_everything(dev
);
3842 i915_gem_reset_fences(dev
);
3844 /* Hack! Don't let anybody do execbuf while we don't control the chip.
3845 * We need to replace this with a semaphore, or something.
3846 * And not confound mm.suspended!
3848 dev_priv
->mm
.suspended
= 1;
3849 del_timer_sync(&dev_priv
->gpu_error
.hangcheck_timer
);
3851 i915_kernel_lost_context(dev
);
3852 i915_gem_cleanup_ringbuffer(dev
);
3854 mutex_unlock(&dev
->struct_mutex
);
3856 /* Cancel the retire work handler, which should be idle now. */
3857 cancel_delayed_work_sync(&dev_priv
->mm
.retire_work
);
3862 void i915_gem_l3_remap(struct drm_device
*dev
)
3864 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3868 if (!IS_IVYBRIDGE(dev
))
3871 if (!dev_priv
->l3_parity
.remap_info
)
3874 misccpctl
= I915_READ(GEN7_MISCCPCTL
);
3875 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
& ~GEN7_DOP_CLOCK_GATE_ENABLE
);
3876 POSTING_READ(GEN7_MISCCPCTL
);
3878 for (i
= 0; i
< GEN7_L3LOG_SIZE
; i
+= 4) {
3879 u32 remap
= I915_READ(GEN7_L3LOG_BASE
+ i
);
3880 if (remap
&& remap
!= dev_priv
->l3_parity
.remap_info
[i
/4])
3881 DRM_DEBUG("0x%x was already programmed to %x\n",
3882 GEN7_L3LOG_BASE
+ i
, remap
);
3883 if (remap
&& !dev_priv
->l3_parity
.remap_info
[i
/4])
3884 DRM_DEBUG_DRIVER("Clearing remapped register\n");
3885 I915_WRITE(GEN7_L3LOG_BASE
+ i
, dev_priv
->l3_parity
.remap_info
[i
/4]);
3888 /* Make sure all the writes land before disabling dop clock gating */
3889 POSTING_READ(GEN7_L3LOG_BASE
);
3891 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
);
3894 void i915_gem_init_swizzling(struct drm_device
*dev
)
3896 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3898 if (INTEL_INFO(dev
)->gen
< 5 ||
3899 dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_NONE
)
3902 I915_WRITE(DISP_ARB_CTL
, I915_READ(DISP_ARB_CTL
) |
3903 DISP_TILE_SURFACE_SWIZZLING
);
3908 I915_WRITE(TILECTL
, I915_READ(TILECTL
) | TILECTL_SWZCTL
);
3910 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB
));
3911 else if (IS_GEN7(dev
))
3912 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB
));
3918 intel_enable_blt(struct drm_device
*dev
)
3923 /* The blitter was dysfunctional on early prototypes */
3924 if (IS_GEN6(dev
) && dev
->pdev
->revision
< 8) {
3925 DRM_INFO("BLT not supported on this pre-production hardware;"
3926 " graphics performance will be degraded.\n");
3933 static int i915_gem_init_rings(struct drm_device
*dev
)
3935 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3938 ret
= intel_init_render_ring_buffer(dev
);
3943 ret
= intel_init_bsd_ring_buffer(dev
);
3945 goto cleanup_render_ring
;
3948 if (intel_enable_blt(dev
)) {
3949 ret
= intel_init_blt_ring_buffer(dev
);
3951 goto cleanup_bsd_ring
;
3954 ret
= i915_gem_set_seqno(dev
, ((u32
)~0 - 0x1000));
3956 goto cleanup_blt_ring
;
3961 intel_cleanup_ring_buffer(&dev_priv
->ring
[BCS
]);
3963 intel_cleanup_ring_buffer(&dev_priv
->ring
[VCS
]);
3964 cleanup_render_ring
:
3965 intel_cleanup_ring_buffer(&dev_priv
->ring
[RCS
]);
3971 i915_gem_init_hw(struct drm_device
*dev
)
3973 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3976 if (INTEL_INFO(dev
)->gen
< 6 && !intel_enable_gtt())
3979 if (IS_HASWELL(dev
) && (I915_READ(0x120010) == 1))
3980 I915_WRITE(0x9008, I915_READ(0x9008) | 0xf0000);
3982 i915_gem_l3_remap(dev
);
3984 i915_gem_init_swizzling(dev
);
3986 ret
= i915_gem_init_rings(dev
);
3991 * XXX: There was some w/a described somewhere suggesting loading
3992 * contexts before PPGTT.
3994 i915_gem_context_init(dev
);
3995 i915_gem_init_ppgtt(dev
);
4000 int i915_gem_init(struct drm_device
*dev
)
4002 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4005 mutex_lock(&dev
->struct_mutex
);
4006 i915_gem_init_global_gtt(dev
);
4007 ret
= i915_gem_init_hw(dev
);
4008 mutex_unlock(&dev
->struct_mutex
);
4010 i915_gem_cleanup_aliasing_ppgtt(dev
);
4014 /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */
4015 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
4016 dev_priv
->dri1
.allow_batchbuffer
= 1;
4021 i915_gem_cleanup_ringbuffer(struct drm_device
*dev
)
4023 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4024 struct intel_ring_buffer
*ring
;
4027 for_each_ring(ring
, dev_priv
, i
)
4028 intel_cleanup_ring_buffer(ring
);
4032 i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
4033 struct drm_file
*file_priv
)
4035 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4038 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4041 if (i915_reset_in_progress(&dev_priv
->gpu_error
)) {
4042 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4043 atomic_set(&dev_priv
->gpu_error
.reset_counter
, 0);
4046 mutex_lock(&dev
->struct_mutex
);
4047 dev_priv
->mm
.suspended
= 0;
4049 ret
= i915_gem_init_hw(dev
);
4051 mutex_unlock(&dev
->struct_mutex
);
4055 BUG_ON(!list_empty(&dev_priv
->mm
.active_list
));
4056 mutex_unlock(&dev
->struct_mutex
);
4058 ret
= drm_irq_install(dev
);
4060 goto cleanup_ringbuffer
;
4065 mutex_lock(&dev
->struct_mutex
);
4066 i915_gem_cleanup_ringbuffer(dev
);
4067 dev_priv
->mm
.suspended
= 1;
4068 mutex_unlock(&dev
->struct_mutex
);
4074 i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
4075 struct drm_file
*file_priv
)
4077 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4080 drm_irq_uninstall(dev
);
4081 return i915_gem_idle(dev
);
4085 i915_gem_lastclose(struct drm_device
*dev
)
4089 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4092 ret
= i915_gem_idle(dev
);
4094 DRM_ERROR("failed to idle hardware: %d\n", ret
);
4098 init_ring_lists(struct intel_ring_buffer
*ring
)
4100 INIT_LIST_HEAD(&ring
->active_list
);
4101 INIT_LIST_HEAD(&ring
->request_list
);
4105 i915_gem_load(struct drm_device
*dev
)
4107 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4111 kmem_cache_create("i915_gem_object",
4112 sizeof(struct drm_i915_gem_object
), 0,
4116 INIT_LIST_HEAD(&dev_priv
->mm
.active_list
);
4117 INIT_LIST_HEAD(&dev_priv
->mm
.inactive_list
);
4118 INIT_LIST_HEAD(&dev_priv
->mm
.unbound_list
);
4119 INIT_LIST_HEAD(&dev_priv
->mm
.bound_list
);
4120 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
4121 for (i
= 0; i
< I915_NUM_RINGS
; i
++)
4122 init_ring_lists(&dev_priv
->ring
[i
]);
4123 for (i
= 0; i
< I915_MAX_NUM_FENCES
; i
++)
4124 INIT_LIST_HEAD(&dev_priv
->fence_regs
[i
].lru_list
);
4125 INIT_DELAYED_WORK(&dev_priv
->mm
.retire_work
,
4126 i915_gem_retire_work_handler
);
4127 init_waitqueue_head(&dev_priv
->gpu_error
.reset_queue
);
4129 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4131 I915_WRITE(MI_ARB_STATE
,
4132 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE
));
4135 dev_priv
->relative_constants_mode
= I915_EXEC_CONSTANTS_REL_GENERAL
;
4137 /* Old X drivers will take 0-2 for front, back, depth buffers */
4138 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
4139 dev_priv
->fence_reg_start
= 3;
4141 if (INTEL_INFO(dev
)->gen
>= 4 || IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
4142 dev_priv
->num_fence_regs
= 16;
4144 dev_priv
->num_fence_regs
= 8;
4146 /* Initialize fence registers to zero */
4147 i915_gem_reset_fences(dev
);
4149 i915_gem_detect_bit_6_swizzle(dev
);
4150 init_waitqueue_head(&dev_priv
->pending_flip_queue
);
4152 dev_priv
->mm
.interruptible
= true;
4154 dev_priv
->mm
.inactive_shrinker
.shrink
= i915_gem_inactive_shrink
;
4155 dev_priv
->mm
.inactive_shrinker
.seeks
= DEFAULT_SEEKS
;
4156 register_shrinker(&dev_priv
->mm
.inactive_shrinker
);
4160 * Create a physically contiguous memory object for this object
4161 * e.g. for cursor + overlay regs
4163 static int i915_gem_init_phys_object(struct drm_device
*dev
,
4164 int id
, int size
, int align
)
4166 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4167 struct drm_i915_gem_phys_object
*phys_obj
;
4170 if (dev_priv
->mm
.phys_objs
[id
- 1] || !size
)
4173 phys_obj
= kzalloc(sizeof(struct drm_i915_gem_phys_object
), GFP_KERNEL
);
4179 phys_obj
->handle
= drm_pci_alloc(dev
, size
, align
);
4180 if (!phys_obj
->handle
) {
4185 set_memory_wc((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
4188 dev_priv
->mm
.phys_objs
[id
- 1] = phys_obj
;
4196 static void i915_gem_free_phys_object(struct drm_device
*dev
, int id
)
4198 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4199 struct drm_i915_gem_phys_object
*phys_obj
;
4201 if (!dev_priv
->mm
.phys_objs
[id
- 1])
4204 phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
4205 if (phys_obj
->cur_obj
) {
4206 i915_gem_detach_phys_object(dev
, phys_obj
->cur_obj
);
4210 set_memory_wb((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
4212 drm_pci_free(dev
, phys_obj
->handle
);
4214 dev_priv
->mm
.phys_objs
[id
- 1] = NULL
;
4217 void i915_gem_free_all_phys_object(struct drm_device
*dev
)
4221 for (i
= I915_GEM_PHYS_CURSOR_0
; i
<= I915_MAX_PHYS_OBJECT
; i
++)
4222 i915_gem_free_phys_object(dev
, i
);
4225 void i915_gem_detach_phys_object(struct drm_device
*dev
,
4226 struct drm_i915_gem_object
*obj
)
4228 struct address_space
*mapping
= obj
->base
.filp
->f_path
.dentry
->d_inode
->i_mapping
;
4235 vaddr
= obj
->phys_obj
->handle
->vaddr
;
4237 page_count
= obj
->base
.size
/ PAGE_SIZE
;
4238 for (i
= 0; i
< page_count
; i
++) {
4239 struct page
*page
= shmem_read_mapping_page(mapping
, i
);
4240 if (!IS_ERR(page
)) {
4241 char *dst
= kmap_atomic(page
);
4242 memcpy(dst
, vaddr
+ i
*PAGE_SIZE
, PAGE_SIZE
);
4245 drm_clflush_pages(&page
, 1);
4247 set_page_dirty(page
);
4248 mark_page_accessed(page
);
4249 page_cache_release(page
);
4252 i915_gem_chipset_flush(dev
);
4254 obj
->phys_obj
->cur_obj
= NULL
;
4255 obj
->phys_obj
= NULL
;
4259 i915_gem_attach_phys_object(struct drm_device
*dev
,
4260 struct drm_i915_gem_object
*obj
,
4264 struct address_space
*mapping
= obj
->base
.filp
->f_path
.dentry
->d_inode
->i_mapping
;
4265 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4270 if (id
> I915_MAX_PHYS_OBJECT
)
4273 if (obj
->phys_obj
) {
4274 if (obj
->phys_obj
->id
== id
)
4276 i915_gem_detach_phys_object(dev
, obj
);
4279 /* create a new object */
4280 if (!dev_priv
->mm
.phys_objs
[id
- 1]) {
4281 ret
= i915_gem_init_phys_object(dev
, id
,
4282 obj
->base
.size
, align
);
4284 DRM_ERROR("failed to init phys object %d size: %zu\n",
4285 id
, obj
->base
.size
);
4290 /* bind to the object */
4291 obj
->phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
4292 obj
->phys_obj
->cur_obj
= obj
;
4294 page_count
= obj
->base
.size
/ PAGE_SIZE
;
4296 for (i
= 0; i
< page_count
; i
++) {
4300 page
= shmem_read_mapping_page(mapping
, i
);
4302 return PTR_ERR(page
);
4304 src
= kmap_atomic(page
);
4305 dst
= obj
->phys_obj
->handle
->vaddr
+ (i
* PAGE_SIZE
);
4306 memcpy(dst
, src
, PAGE_SIZE
);
4309 mark_page_accessed(page
);
4310 page_cache_release(page
);
4317 i915_gem_phys_pwrite(struct drm_device
*dev
,
4318 struct drm_i915_gem_object
*obj
,
4319 struct drm_i915_gem_pwrite
*args
,
4320 struct drm_file
*file_priv
)
4322 void *vaddr
= obj
->phys_obj
->handle
->vaddr
+ args
->offset
;
4323 char __user
*user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
4325 if (__copy_from_user_inatomic_nocache(vaddr
, user_data
, args
->size
)) {
4326 unsigned long unwritten
;
4328 /* The physical object once assigned is fixed for the lifetime
4329 * of the obj, so we can safely drop the lock and continue
4332 mutex_unlock(&dev
->struct_mutex
);
4333 unwritten
= copy_from_user(vaddr
, user_data
, args
->size
);
4334 mutex_lock(&dev
->struct_mutex
);
4339 i915_gem_chipset_flush(dev
);
4343 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
)
4345 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
4347 /* Clean up our request list when the client is going away, so that
4348 * later retire_requests won't dereference our soon-to-be-gone
4351 spin_lock(&file_priv
->mm
.lock
);
4352 while (!list_empty(&file_priv
->mm
.request_list
)) {
4353 struct drm_i915_gem_request
*request
;
4355 request
= list_first_entry(&file_priv
->mm
.request_list
,
4356 struct drm_i915_gem_request
,
4358 list_del(&request
->client_list
);
4359 request
->file_priv
= NULL
;
4361 spin_unlock(&file_priv
->mm
.lock
);
4364 static bool mutex_is_locked_by(struct mutex
*mutex
, struct task_struct
*task
)
4366 if (!mutex_is_locked(mutex
))
4369 #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES)
4370 return mutex
->owner
== task
;
4372 /* Since UP may be pre-empted, we cannot assume that we own the lock */
4378 i915_gem_inactive_shrink(struct shrinker
*shrinker
, struct shrink_control
*sc
)
4380 struct drm_i915_private
*dev_priv
=
4381 container_of(shrinker
,
4382 struct drm_i915_private
,
4383 mm
.inactive_shrinker
);
4384 struct drm_device
*dev
= dev_priv
->dev
;
4385 struct drm_i915_gem_object
*obj
;
4386 int nr_to_scan
= sc
->nr_to_scan
;
4390 if (!mutex_trylock(&dev
->struct_mutex
)) {
4391 if (!mutex_is_locked_by(&dev
->struct_mutex
, current
))
4394 if (dev_priv
->mm
.shrinker_no_lock_stealing
)
4401 nr_to_scan
-= i915_gem_purge(dev_priv
, nr_to_scan
);
4403 nr_to_scan
-= __i915_gem_shrink(dev_priv
, nr_to_scan
,
4406 i915_gem_shrink_all(dev_priv
);
4410 list_for_each_entry(obj
, &dev_priv
->mm
.unbound_list
, gtt_list
)
4411 if (obj
->pages_pin_count
== 0)
4412 cnt
+= obj
->base
.size
>> PAGE_SHIFT
;
4413 list_for_each_entry(obj
, &dev_priv
->mm
.inactive_list
, gtt_list
)
4414 if (obj
->pin_count
== 0 && obj
->pages_pin_count
== 0)
4415 cnt
+= obj
->base
.size
>> PAGE_SHIFT
;
4418 mutex_unlock(&dev
->struct_mutex
);