2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/i915_drm.h>
31 #include "i915_trace.h"
32 #include "intel_drv.h"
33 #include <linux/shmem_fs.h>
34 #include <linux/slab.h>
35 #include <linux/swap.h>
36 #include <linux/pci.h>
37 #include <linux/dma-buf.h>
39 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
);
40 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
);
41 static __must_check
int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object
*obj
,
43 bool map_and_fenceable
,
45 static int i915_gem_phys_pwrite(struct drm_device
*dev
,
46 struct drm_i915_gem_object
*obj
,
47 struct drm_i915_gem_pwrite
*args
,
48 struct drm_file
*file
);
50 static void i915_gem_write_fence(struct drm_device
*dev
, int reg
,
51 struct drm_i915_gem_object
*obj
);
52 static void i915_gem_object_update_fence(struct drm_i915_gem_object
*obj
,
53 struct drm_i915_fence_reg
*fence
,
56 static int i915_gem_inactive_shrink(struct shrinker
*shrinker
,
57 struct shrink_control
*sc
);
58 static long i915_gem_purge(struct drm_i915_private
*dev_priv
, long target
);
59 static void i915_gem_shrink_all(struct drm_i915_private
*dev_priv
);
60 static void i915_gem_object_truncate(struct drm_i915_gem_object
*obj
);
62 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object
*obj
)
65 i915_gem_release_mmap(obj
);
67 /* As we do not have an associated fence register, we will force
68 * a tiling change if we ever need to acquire one.
70 obj
->fence_dirty
= false;
71 obj
->fence_reg
= I915_FENCE_REG_NONE
;
74 /* some bookkeeping */
75 static void i915_gem_info_add_obj(struct drm_i915_private
*dev_priv
,
78 dev_priv
->mm
.object_count
++;
79 dev_priv
->mm
.object_memory
+= size
;
82 static void i915_gem_info_remove_obj(struct drm_i915_private
*dev_priv
,
85 dev_priv
->mm
.object_count
--;
86 dev_priv
->mm
.object_memory
-= size
;
90 i915_gem_wait_for_error(struct i915_gpu_error
*error
)
94 #define EXIT_COND (!i915_reset_in_progress(error) || \
95 i915_terminally_wedged(error))
100 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
101 * userspace. If it takes that long something really bad is going on and
102 * we should simply try to bail out and fail as gracefully as possible.
104 ret
= wait_event_interruptible_timeout(error
->reset_queue
,
108 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
110 } else if (ret
< 0) {
118 int i915_mutex_lock_interruptible(struct drm_device
*dev
)
120 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
123 ret
= i915_gem_wait_for_error(&dev_priv
->gpu_error
);
127 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
131 WARN_ON(i915_verify_lists(dev
));
136 i915_gem_object_is_inactive(struct drm_i915_gem_object
*obj
)
138 return obj
->gtt_space
&& !obj
->active
;
142 i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
143 struct drm_file
*file
)
145 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
146 struct drm_i915_gem_init
*args
= data
;
148 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
151 if (args
->gtt_start
>= args
->gtt_end
||
152 (args
->gtt_end
| args
->gtt_start
) & (PAGE_SIZE
- 1))
155 /* GEM with user mode setting was never supported on ilk and later. */
156 if (INTEL_INFO(dev
)->gen
>= 5)
159 mutex_lock(&dev
->struct_mutex
);
160 i915_gem_setup_global_gtt(dev
, args
->gtt_start
, args
->gtt_end
,
162 dev_priv
->gtt
.mappable_end
= args
->gtt_end
;
163 mutex_unlock(&dev
->struct_mutex
);
169 i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
170 struct drm_file
*file
)
172 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
173 struct drm_i915_gem_get_aperture
*args
= data
;
174 struct drm_i915_gem_object
*obj
;
178 mutex_lock(&dev
->struct_mutex
);
179 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, gtt_list
)
181 pinned
+= obj
->gtt_space
->size
;
182 mutex_unlock(&dev
->struct_mutex
);
184 args
->aper_size
= dev_priv
->gtt
.total
;
185 args
->aper_available_size
= args
->aper_size
- pinned
;
190 void *i915_gem_object_alloc(struct drm_device
*dev
)
192 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
193 return kmem_cache_alloc(dev_priv
->slab
, GFP_KERNEL
| __GFP_ZERO
);
196 void i915_gem_object_free(struct drm_i915_gem_object
*obj
)
198 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
199 kmem_cache_free(dev_priv
->slab
, obj
);
203 i915_gem_create(struct drm_file
*file
,
204 struct drm_device
*dev
,
208 struct drm_i915_gem_object
*obj
;
212 size
= roundup(size
, PAGE_SIZE
);
216 /* Allocate the new object */
217 obj
= i915_gem_alloc_object(dev
, size
);
221 ret
= drm_gem_handle_create(file
, &obj
->base
, &handle
);
223 drm_gem_object_release(&obj
->base
);
224 i915_gem_info_remove_obj(dev
->dev_private
, obj
->base
.size
);
225 i915_gem_object_free(obj
);
229 /* drop reference from allocate - handle holds it now */
230 drm_gem_object_unreference(&obj
->base
);
231 trace_i915_gem_object_create(obj
);
238 i915_gem_dumb_create(struct drm_file
*file
,
239 struct drm_device
*dev
,
240 struct drm_mode_create_dumb
*args
)
242 /* have to work out size/pitch and return them */
243 args
->pitch
= ALIGN(args
->width
* ((args
->bpp
+ 7) / 8), 64);
244 args
->size
= args
->pitch
* args
->height
;
245 return i915_gem_create(file
, dev
,
246 args
->size
, &args
->handle
);
249 int i915_gem_dumb_destroy(struct drm_file
*file
,
250 struct drm_device
*dev
,
253 return drm_gem_handle_delete(file
, handle
);
257 * Creates a new mm object and returns a handle to it.
260 i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
261 struct drm_file
*file
)
263 struct drm_i915_gem_create
*args
= data
;
265 return i915_gem_create(file
, dev
,
266 args
->size
, &args
->handle
);
270 __copy_to_user_swizzled(char __user
*cpu_vaddr
,
271 const char *gpu_vaddr
, int gpu_offset
,
274 int ret
, cpu_offset
= 0;
277 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
278 int this_length
= min(cacheline_end
- gpu_offset
, length
);
279 int swizzled_gpu_offset
= gpu_offset
^ 64;
281 ret
= __copy_to_user(cpu_vaddr
+ cpu_offset
,
282 gpu_vaddr
+ swizzled_gpu_offset
,
287 cpu_offset
+= this_length
;
288 gpu_offset
+= this_length
;
289 length
-= this_length
;
296 __copy_from_user_swizzled(char *gpu_vaddr
, int gpu_offset
,
297 const char __user
*cpu_vaddr
,
300 int ret
, cpu_offset
= 0;
303 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
304 int this_length
= min(cacheline_end
- gpu_offset
, length
);
305 int swizzled_gpu_offset
= gpu_offset
^ 64;
307 ret
= __copy_from_user(gpu_vaddr
+ swizzled_gpu_offset
,
308 cpu_vaddr
+ cpu_offset
,
313 cpu_offset
+= this_length
;
314 gpu_offset
+= this_length
;
315 length
-= this_length
;
321 /* Per-page copy function for the shmem pread fastpath.
322 * Flushes invalid cachelines before reading the target if
323 * needs_clflush is set. */
325 shmem_pread_fast(struct page
*page
, int shmem_page_offset
, int page_length
,
326 char __user
*user_data
,
327 bool page_do_bit17_swizzling
, bool needs_clflush
)
332 if (unlikely(page_do_bit17_swizzling
))
335 vaddr
= kmap_atomic(page
);
337 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
339 ret
= __copy_to_user_inatomic(user_data
,
340 vaddr
+ shmem_page_offset
,
342 kunmap_atomic(vaddr
);
344 return ret
? -EFAULT
: 0;
348 shmem_clflush_swizzled_range(char *addr
, unsigned long length
,
351 if (unlikely(swizzled
)) {
352 unsigned long start
= (unsigned long) addr
;
353 unsigned long end
= (unsigned long) addr
+ length
;
355 /* For swizzling simply ensure that we always flush both
356 * channels. Lame, but simple and it works. Swizzled
357 * pwrite/pread is far from a hotpath - current userspace
358 * doesn't use it at all. */
359 start
= round_down(start
, 128);
360 end
= round_up(end
, 128);
362 drm_clflush_virt_range((void *)start
, end
- start
);
364 drm_clflush_virt_range(addr
, length
);
369 /* Only difference to the fast-path function is that this can handle bit17
370 * and uses non-atomic copy and kmap functions. */
372 shmem_pread_slow(struct page
*page
, int shmem_page_offset
, int page_length
,
373 char __user
*user_data
,
374 bool page_do_bit17_swizzling
, bool needs_clflush
)
381 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
383 page_do_bit17_swizzling
);
385 if (page_do_bit17_swizzling
)
386 ret
= __copy_to_user_swizzled(user_data
,
387 vaddr
, shmem_page_offset
,
390 ret
= __copy_to_user(user_data
,
391 vaddr
+ shmem_page_offset
,
395 return ret
? - EFAULT
: 0;
399 i915_gem_shmem_pread(struct drm_device
*dev
,
400 struct drm_i915_gem_object
*obj
,
401 struct drm_i915_gem_pread
*args
,
402 struct drm_file
*file
)
404 char __user
*user_data
;
407 int shmem_page_offset
, page_length
, ret
= 0;
408 int obj_do_bit17_swizzling
, page_do_bit17_swizzling
;
410 int needs_clflush
= 0;
411 struct sg_page_iter sg_iter
;
413 user_data
= to_user_ptr(args
->data_ptr
);
416 obj_do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
418 if (!(obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
)) {
419 /* If we're not in the cpu read domain, set ourself into the gtt
420 * read domain and manually flush cachelines (if required). This
421 * optimizes for the case when the gpu will dirty the data
422 * anyway again before the next pread happens. */
423 if (obj
->cache_level
== I915_CACHE_NONE
)
425 if (obj
->gtt_space
) {
426 ret
= i915_gem_object_set_to_gtt_domain(obj
, false);
432 ret
= i915_gem_object_get_pages(obj
);
436 i915_gem_object_pin_pages(obj
);
438 offset
= args
->offset
;
440 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
,
441 offset
>> PAGE_SHIFT
) {
442 struct page
*page
= sg_page_iter_page(&sg_iter
);
447 /* Operation in this page
449 * shmem_page_offset = offset within page in shmem file
450 * page_length = bytes to copy for this page
452 shmem_page_offset
= offset_in_page(offset
);
453 page_length
= remain
;
454 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
455 page_length
= PAGE_SIZE
- shmem_page_offset
;
457 page_do_bit17_swizzling
= obj_do_bit17_swizzling
&&
458 (page_to_phys(page
) & (1 << 17)) != 0;
460 ret
= shmem_pread_fast(page
, shmem_page_offset
, page_length
,
461 user_data
, page_do_bit17_swizzling
,
466 mutex_unlock(&dev
->struct_mutex
);
469 ret
= fault_in_multipages_writeable(user_data
, remain
);
470 /* Userspace is tricking us, but we've already clobbered
471 * its pages with the prefault and promised to write the
472 * data up to the first fault. Hence ignore any errors
473 * and just continue. */
478 ret
= shmem_pread_slow(page
, shmem_page_offset
, page_length
,
479 user_data
, page_do_bit17_swizzling
,
482 mutex_lock(&dev
->struct_mutex
);
485 mark_page_accessed(page
);
490 remain
-= page_length
;
491 user_data
+= page_length
;
492 offset
+= page_length
;
496 i915_gem_object_unpin_pages(obj
);
502 * Reads data from the object referenced by handle.
504 * On error, the contents of *data are undefined.
507 i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
508 struct drm_file
*file
)
510 struct drm_i915_gem_pread
*args
= data
;
511 struct drm_i915_gem_object
*obj
;
517 if (!access_ok(VERIFY_WRITE
,
518 to_user_ptr(args
->data_ptr
),
522 ret
= i915_mutex_lock_interruptible(dev
);
526 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
527 if (&obj
->base
== NULL
) {
532 /* Bounds check source. */
533 if (args
->offset
> obj
->base
.size
||
534 args
->size
> obj
->base
.size
- args
->offset
) {
539 /* prime objects have no backing filp to GEM pread/pwrite
542 if (!obj
->base
.filp
) {
547 trace_i915_gem_object_pread(obj
, args
->offset
, args
->size
);
549 ret
= i915_gem_shmem_pread(dev
, obj
, args
, file
);
552 drm_gem_object_unreference(&obj
->base
);
554 mutex_unlock(&dev
->struct_mutex
);
558 /* This is the fast write path which cannot handle
559 * page faults in the source data
563 fast_user_write(struct io_mapping
*mapping
,
564 loff_t page_base
, int page_offset
,
565 char __user
*user_data
,
568 void __iomem
*vaddr_atomic
;
570 unsigned long unwritten
;
572 vaddr_atomic
= io_mapping_map_atomic_wc(mapping
, page_base
);
573 /* We can use the cpu mem copy function because this is X86. */
574 vaddr
= (void __force
*)vaddr_atomic
+ page_offset
;
575 unwritten
= __copy_from_user_inatomic_nocache(vaddr
,
577 io_mapping_unmap_atomic(vaddr_atomic
);
582 * This is the fast pwrite path, where we copy the data directly from the
583 * user into the GTT, uncached.
586 i915_gem_gtt_pwrite_fast(struct drm_device
*dev
,
587 struct drm_i915_gem_object
*obj
,
588 struct drm_i915_gem_pwrite
*args
,
589 struct drm_file
*file
)
591 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
593 loff_t offset
, page_base
;
594 char __user
*user_data
;
595 int page_offset
, page_length
, ret
;
597 ret
= i915_gem_object_pin(obj
, 0, true, true);
601 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
605 ret
= i915_gem_object_put_fence(obj
);
609 user_data
= to_user_ptr(args
->data_ptr
);
612 offset
= obj
->gtt_offset
+ args
->offset
;
615 /* Operation in this page
617 * page_base = page offset within aperture
618 * page_offset = offset within page
619 * page_length = bytes to copy for this page
621 page_base
= offset
& PAGE_MASK
;
622 page_offset
= offset_in_page(offset
);
623 page_length
= remain
;
624 if ((page_offset
+ remain
) > PAGE_SIZE
)
625 page_length
= PAGE_SIZE
- page_offset
;
627 /* If we get a fault while copying data, then (presumably) our
628 * source page isn't available. Return the error and we'll
629 * retry in the slow path.
631 if (fast_user_write(dev_priv
->gtt
.mappable
, page_base
,
632 page_offset
, user_data
, page_length
)) {
637 remain
-= page_length
;
638 user_data
+= page_length
;
639 offset
+= page_length
;
643 i915_gem_object_unpin(obj
);
648 /* Per-page copy function for the shmem pwrite fastpath.
649 * Flushes invalid cachelines before writing to the target if
650 * needs_clflush_before is set and flushes out any written cachelines after
651 * writing if needs_clflush is set. */
653 shmem_pwrite_fast(struct page
*page
, int shmem_page_offset
, int page_length
,
654 char __user
*user_data
,
655 bool page_do_bit17_swizzling
,
656 bool needs_clflush_before
,
657 bool needs_clflush_after
)
662 if (unlikely(page_do_bit17_swizzling
))
665 vaddr
= kmap_atomic(page
);
666 if (needs_clflush_before
)
667 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
669 ret
= __copy_from_user_inatomic_nocache(vaddr
+ shmem_page_offset
,
672 if (needs_clflush_after
)
673 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
675 kunmap_atomic(vaddr
);
677 return ret
? -EFAULT
: 0;
680 /* Only difference to the fast-path function is that this can handle bit17
681 * and uses non-atomic copy and kmap functions. */
683 shmem_pwrite_slow(struct page
*page
, int shmem_page_offset
, int page_length
,
684 char __user
*user_data
,
685 bool page_do_bit17_swizzling
,
686 bool needs_clflush_before
,
687 bool needs_clflush_after
)
693 if (unlikely(needs_clflush_before
|| page_do_bit17_swizzling
))
694 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
696 page_do_bit17_swizzling
);
697 if (page_do_bit17_swizzling
)
698 ret
= __copy_from_user_swizzled(vaddr
, shmem_page_offset
,
702 ret
= __copy_from_user(vaddr
+ shmem_page_offset
,
705 if (needs_clflush_after
)
706 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
708 page_do_bit17_swizzling
);
711 return ret
? -EFAULT
: 0;
715 i915_gem_shmem_pwrite(struct drm_device
*dev
,
716 struct drm_i915_gem_object
*obj
,
717 struct drm_i915_gem_pwrite
*args
,
718 struct drm_file
*file
)
722 char __user
*user_data
;
723 int shmem_page_offset
, page_length
, ret
= 0;
724 int obj_do_bit17_swizzling
, page_do_bit17_swizzling
;
725 int hit_slowpath
= 0;
726 int needs_clflush_after
= 0;
727 int needs_clflush_before
= 0;
728 struct sg_page_iter sg_iter
;
730 user_data
= to_user_ptr(args
->data_ptr
);
733 obj_do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
735 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
736 /* If we're not in the cpu write domain, set ourself into the gtt
737 * write domain and manually flush cachelines (if required). This
738 * optimizes for the case when the gpu will use the data
739 * right away and we therefore have to clflush anyway. */
740 if (obj
->cache_level
== I915_CACHE_NONE
)
741 needs_clflush_after
= 1;
742 if (obj
->gtt_space
) {
743 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
748 /* Same trick applies for invalidate partially written cachelines before
750 if (!(obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
)
751 && obj
->cache_level
== I915_CACHE_NONE
)
752 needs_clflush_before
= 1;
754 ret
= i915_gem_object_get_pages(obj
);
758 i915_gem_object_pin_pages(obj
);
760 offset
= args
->offset
;
763 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
,
764 offset
>> PAGE_SHIFT
) {
765 struct page
*page
= sg_page_iter_page(&sg_iter
);
766 int partial_cacheline_write
;
771 /* Operation in this page
773 * shmem_page_offset = offset within page in shmem file
774 * page_length = bytes to copy for this page
776 shmem_page_offset
= offset_in_page(offset
);
778 page_length
= remain
;
779 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
780 page_length
= PAGE_SIZE
- shmem_page_offset
;
782 /* If we don't overwrite a cacheline completely we need to be
783 * careful to have up-to-date data by first clflushing. Don't
784 * overcomplicate things and flush the entire patch. */
785 partial_cacheline_write
= needs_clflush_before
&&
786 ((shmem_page_offset
| page_length
)
787 & (boot_cpu_data
.x86_clflush_size
- 1));
789 page_do_bit17_swizzling
= obj_do_bit17_swizzling
&&
790 (page_to_phys(page
) & (1 << 17)) != 0;
792 ret
= shmem_pwrite_fast(page
, shmem_page_offset
, page_length
,
793 user_data
, page_do_bit17_swizzling
,
794 partial_cacheline_write
,
795 needs_clflush_after
);
800 mutex_unlock(&dev
->struct_mutex
);
801 ret
= shmem_pwrite_slow(page
, shmem_page_offset
, page_length
,
802 user_data
, page_do_bit17_swizzling
,
803 partial_cacheline_write
,
804 needs_clflush_after
);
806 mutex_lock(&dev
->struct_mutex
);
809 set_page_dirty(page
);
810 mark_page_accessed(page
);
815 remain
-= page_length
;
816 user_data
+= page_length
;
817 offset
+= page_length
;
821 i915_gem_object_unpin_pages(obj
);
825 * Fixup: Flush cpu caches in case we didn't flush the dirty
826 * cachelines in-line while writing and the object moved
827 * out of the cpu write domain while we've dropped the lock.
829 if (!needs_clflush_after
&&
830 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
831 i915_gem_clflush_object(obj
);
832 i915_gem_chipset_flush(dev
);
836 if (needs_clflush_after
)
837 i915_gem_chipset_flush(dev
);
843 * Writes data to the object referenced by handle.
845 * On error, the contents of the buffer that were to be modified are undefined.
848 i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
849 struct drm_file
*file
)
851 struct drm_i915_gem_pwrite
*args
= data
;
852 struct drm_i915_gem_object
*obj
;
858 if (!access_ok(VERIFY_READ
,
859 to_user_ptr(args
->data_ptr
),
863 ret
= fault_in_multipages_readable(to_user_ptr(args
->data_ptr
),
868 ret
= i915_mutex_lock_interruptible(dev
);
872 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
873 if (&obj
->base
== NULL
) {
878 /* Bounds check destination. */
879 if (args
->offset
> obj
->base
.size
||
880 args
->size
> obj
->base
.size
- args
->offset
) {
885 /* prime objects have no backing filp to GEM pread/pwrite
888 if (!obj
->base
.filp
) {
893 trace_i915_gem_object_pwrite(obj
, args
->offset
, args
->size
);
896 /* We can only do the GTT pwrite on untiled buffers, as otherwise
897 * it would end up going through the fenced access, and we'll get
898 * different detiling behavior between reading and writing.
899 * pread/pwrite currently are reading and writing from the CPU
900 * perspective, requiring manual detiling by the client.
903 ret
= i915_gem_phys_pwrite(dev
, obj
, args
, file
);
907 if (obj
->cache_level
== I915_CACHE_NONE
&&
908 obj
->tiling_mode
== I915_TILING_NONE
&&
909 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
910 ret
= i915_gem_gtt_pwrite_fast(dev
, obj
, args
, file
);
911 /* Note that the gtt paths might fail with non-page-backed user
912 * pointers (e.g. gtt mappings when moving data between
913 * textures). Fallback to the shmem path in that case. */
916 if (ret
== -EFAULT
|| ret
== -ENOSPC
)
917 ret
= i915_gem_shmem_pwrite(dev
, obj
, args
, file
);
920 drm_gem_object_unreference(&obj
->base
);
922 mutex_unlock(&dev
->struct_mutex
);
927 i915_gem_check_wedge(struct i915_gpu_error
*error
,
930 if (i915_reset_in_progress(error
)) {
931 /* Non-interruptible callers can't handle -EAGAIN, hence return
932 * -EIO unconditionally for these. */
936 /* Recovery complete, but the reset failed ... */
937 if (i915_terminally_wedged(error
))
947 * Compare seqno against outstanding lazy request. Emit a request if they are
951 i915_gem_check_olr(struct intel_ring_buffer
*ring
, u32 seqno
)
955 BUG_ON(!mutex_is_locked(&ring
->dev
->struct_mutex
));
958 if (seqno
== ring
->outstanding_lazy_request
)
959 ret
= i915_add_request(ring
, NULL
, NULL
);
965 * __wait_seqno - wait until execution of seqno has finished
966 * @ring: the ring expected to report seqno
968 * @reset_counter: reset sequence associated with the given seqno
969 * @interruptible: do an interruptible wait (normally yes)
970 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
972 * Note: It is of utmost importance that the passed in seqno and reset_counter
973 * values have been read by the caller in an smp safe manner. Where read-side
974 * locks are involved, it is sufficient to read the reset_counter before
975 * unlocking the lock that protects the seqno. For lockless tricks, the
976 * reset_counter _must_ be read before, and an appropriate smp_rmb must be
979 * Returns 0 if the seqno was found within the alloted time. Else returns the
980 * errno with remaining time filled in timeout argument.
982 static int __wait_seqno(struct intel_ring_buffer
*ring
, u32 seqno
,
983 unsigned reset_counter
,
984 bool interruptible
, struct timespec
*timeout
)
986 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
987 struct timespec before
, now
, wait_time
={1,0};
988 unsigned long timeout_jiffies
;
990 bool wait_forever
= true;
993 if (i915_seqno_passed(ring
->get_seqno(ring
, true), seqno
))
996 trace_i915_gem_request_wait_begin(ring
, seqno
);
998 if (timeout
!= NULL
) {
999 wait_time
= *timeout
;
1000 wait_forever
= false;
1003 timeout_jiffies
= timespec_to_jiffies_timeout(&wait_time
);
1005 if (WARN_ON(!ring
->irq_get(ring
)))
1008 /* Record current time in case interrupted by signal, or wedged * */
1009 getrawmonotonic(&before
);
1012 (i915_seqno_passed(ring->get_seqno(ring, false), seqno) || \
1013 i915_reset_in_progress(&dev_priv->gpu_error) || \
1014 reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
1017 end
= wait_event_interruptible_timeout(ring
->irq_queue
,
1021 end
= wait_event_timeout(ring
->irq_queue
, EXIT_COND
,
1024 /* We need to check whether any gpu reset happened in between
1025 * the caller grabbing the seqno and now ... */
1026 if (reset_counter
!= atomic_read(&dev_priv
->gpu_error
.reset_counter
))
1029 /* ... but upgrade the -EGAIN to an -EIO if the gpu is truely
1031 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, interruptible
);
1034 } while (end
== 0 && wait_forever
);
1036 getrawmonotonic(&now
);
1038 ring
->irq_put(ring
);
1039 trace_i915_gem_request_wait_end(ring
, seqno
);
1043 struct timespec sleep_time
= timespec_sub(now
, before
);
1044 *timeout
= timespec_sub(*timeout
, sleep_time
);
1045 if (!timespec_valid(timeout
)) /* i.e. negative time remains */
1046 set_normalized_timespec(timeout
, 0, 0);
1051 case -EAGAIN
: /* Wedged */
1052 case -ERESTARTSYS
: /* Signal */
1054 case 0: /* Timeout */
1056 default: /* Completed */
1057 WARN_ON(end
< 0); /* We're not aware of other errors */
1063 * Waits for a sequence number to be signaled, and cleans up the
1064 * request and object lists appropriately for that event.
1067 i915_wait_seqno(struct intel_ring_buffer
*ring
, uint32_t seqno
)
1069 struct drm_device
*dev
= ring
->dev
;
1070 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1071 bool interruptible
= dev_priv
->mm
.interruptible
;
1074 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
1077 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, interruptible
);
1081 ret
= i915_gem_check_olr(ring
, seqno
);
1085 return __wait_seqno(ring
, seqno
,
1086 atomic_read(&dev_priv
->gpu_error
.reset_counter
),
1087 interruptible
, NULL
);
1091 * Ensures that all rendering to the object has completed and the object is
1092 * safe to unbind from the GTT or access from the CPU.
1094 static __must_check
int
1095 i915_gem_object_wait_rendering(struct drm_i915_gem_object
*obj
,
1098 struct intel_ring_buffer
*ring
= obj
->ring
;
1102 seqno
= readonly
? obj
->last_write_seqno
: obj
->last_read_seqno
;
1106 ret
= i915_wait_seqno(ring
, seqno
);
1110 i915_gem_retire_requests_ring(ring
);
1112 /* Manually manage the write flush as we may have not yet
1113 * retired the buffer.
1115 if (obj
->last_write_seqno
&&
1116 i915_seqno_passed(seqno
, obj
->last_write_seqno
)) {
1117 obj
->last_write_seqno
= 0;
1118 obj
->base
.write_domain
&= ~I915_GEM_GPU_DOMAINS
;
1124 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1125 * as the object state may change during this call.
1127 static __must_check
int
1128 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object
*obj
,
1131 struct drm_device
*dev
= obj
->base
.dev
;
1132 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1133 struct intel_ring_buffer
*ring
= obj
->ring
;
1134 unsigned reset_counter
;
1138 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
1139 BUG_ON(!dev_priv
->mm
.interruptible
);
1141 seqno
= readonly
? obj
->last_write_seqno
: obj
->last_read_seqno
;
1145 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, true);
1149 ret
= i915_gem_check_olr(ring
, seqno
);
1153 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
1154 mutex_unlock(&dev
->struct_mutex
);
1155 ret
= __wait_seqno(ring
, seqno
, reset_counter
, true, NULL
);
1156 mutex_lock(&dev
->struct_mutex
);
1158 i915_gem_retire_requests_ring(ring
);
1160 /* Manually manage the write flush as we may have not yet
1161 * retired the buffer.
1163 if (obj
->last_write_seqno
&&
1164 i915_seqno_passed(seqno
, obj
->last_write_seqno
)) {
1165 obj
->last_write_seqno
= 0;
1166 obj
->base
.write_domain
&= ~I915_GEM_GPU_DOMAINS
;
1173 * Called when user space prepares to use an object with the CPU, either
1174 * through the mmap ioctl's mapping or a GTT mapping.
1177 i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
1178 struct drm_file
*file
)
1180 struct drm_i915_gem_set_domain
*args
= data
;
1181 struct drm_i915_gem_object
*obj
;
1182 uint32_t read_domains
= args
->read_domains
;
1183 uint32_t write_domain
= args
->write_domain
;
1186 /* Only handle setting domains to types used by the CPU. */
1187 if (write_domain
& I915_GEM_GPU_DOMAINS
)
1190 if (read_domains
& I915_GEM_GPU_DOMAINS
)
1193 /* Having something in the write domain implies it's in the read
1194 * domain, and only that read domain. Enforce that in the request.
1196 if (write_domain
!= 0 && read_domains
!= write_domain
)
1199 ret
= i915_mutex_lock_interruptible(dev
);
1203 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1204 if (&obj
->base
== NULL
) {
1209 /* Try to flush the object off the GPU without holding the lock.
1210 * We will repeat the flush holding the lock in the normal manner
1211 * to catch cases where we are gazumped.
1213 ret
= i915_gem_object_wait_rendering__nonblocking(obj
, !write_domain
);
1217 if (read_domains
& I915_GEM_DOMAIN_GTT
) {
1218 ret
= i915_gem_object_set_to_gtt_domain(obj
, write_domain
!= 0);
1220 /* Silently promote "you're not bound, there was nothing to do"
1221 * to success, since the client was just asking us to
1222 * make sure everything was done.
1227 ret
= i915_gem_object_set_to_cpu_domain(obj
, write_domain
!= 0);
1231 drm_gem_object_unreference(&obj
->base
);
1233 mutex_unlock(&dev
->struct_mutex
);
1238 * Called when user space has done writes to this buffer
1241 i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1242 struct drm_file
*file
)
1244 struct drm_i915_gem_sw_finish
*args
= data
;
1245 struct drm_i915_gem_object
*obj
;
1248 ret
= i915_mutex_lock_interruptible(dev
);
1252 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1253 if (&obj
->base
== NULL
) {
1258 /* Pinned buffers may be scanout, so flush the cache */
1260 i915_gem_object_flush_cpu_write_domain(obj
);
1262 drm_gem_object_unreference(&obj
->base
);
1264 mutex_unlock(&dev
->struct_mutex
);
1269 * Maps the contents of an object, returning the address it is mapped
1272 * While the mapping holds a reference on the contents of the object, it doesn't
1273 * imply a ref on the object itself.
1276 i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1277 struct drm_file
*file
)
1279 struct drm_i915_gem_mmap
*args
= data
;
1280 struct drm_gem_object
*obj
;
1283 obj
= drm_gem_object_lookup(dev
, file
, args
->handle
);
1287 /* prime objects have no backing filp to GEM mmap
1291 drm_gem_object_unreference_unlocked(obj
);
1295 addr
= vm_mmap(obj
->filp
, 0, args
->size
,
1296 PROT_READ
| PROT_WRITE
, MAP_SHARED
,
1298 drm_gem_object_unreference_unlocked(obj
);
1299 if (IS_ERR((void *)addr
))
1302 args
->addr_ptr
= (uint64_t) addr
;
1308 * i915_gem_fault - fault a page into the GTT
1309 * vma: VMA in question
1312 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1313 * from userspace. The fault handler takes care of binding the object to
1314 * the GTT (if needed), allocating and programming a fence register (again,
1315 * only if needed based on whether the old reg is still valid or the object
1316 * is tiled) and inserting a new PTE into the faulting process.
1318 * Note that the faulting process may involve evicting existing objects
1319 * from the GTT and/or fence registers to make room. So performance may
1320 * suffer if the GTT working set is large or there are few fence registers
1323 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
)
1325 struct drm_i915_gem_object
*obj
= to_intel_bo(vma
->vm_private_data
);
1326 struct drm_device
*dev
= obj
->base
.dev
;
1327 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1328 pgoff_t page_offset
;
1331 bool write
= !!(vmf
->flags
& FAULT_FLAG_WRITE
);
1333 /* We don't use vmf->pgoff since that has the fake offset */
1334 page_offset
= ((unsigned long)vmf
->virtual_address
- vma
->vm_start
) >>
1337 ret
= i915_mutex_lock_interruptible(dev
);
1341 trace_i915_gem_object_fault(obj
, page_offset
, true, write
);
1343 /* Access to snoopable pages through the GTT is incoherent. */
1344 if (obj
->cache_level
!= I915_CACHE_NONE
&& !HAS_LLC(dev
)) {
1349 /* Now bind it into the GTT if needed */
1350 ret
= i915_gem_object_pin(obj
, 0, true, false);
1354 ret
= i915_gem_object_set_to_gtt_domain(obj
, write
);
1358 ret
= i915_gem_object_get_fence(obj
);
1362 obj
->fault_mappable
= true;
1364 pfn
= ((dev_priv
->gtt
.mappable_base
+ obj
->gtt_offset
) >> PAGE_SHIFT
) +
1367 /* Finally, remap it using the new GTT offset */
1368 ret
= vm_insert_pfn(vma
, (unsigned long)vmf
->virtual_address
, pfn
);
1370 i915_gem_object_unpin(obj
);
1372 mutex_unlock(&dev
->struct_mutex
);
1376 /* If this -EIO is due to a gpu hang, give the reset code a
1377 * chance to clean up the mess. Otherwise return the proper
1379 if (i915_terminally_wedged(&dev_priv
->gpu_error
))
1380 return VM_FAULT_SIGBUS
;
1382 /* Give the error handler a chance to run and move the
1383 * objects off the GPU active list. Next time we service the
1384 * fault, we should be able to transition the page into the
1385 * GTT without touching the GPU (and so avoid further
1386 * EIO/EGAIN). If the GPU is wedged, then there is no issue
1387 * with coherency, just lost writes.
1395 * EBUSY is ok: this just means that another thread
1396 * already did the job.
1398 return VM_FAULT_NOPAGE
;
1400 return VM_FAULT_OOM
;
1402 return VM_FAULT_SIGBUS
;
1404 WARN_ONCE(ret
, "unhandled error in i915_gem_fault: %i\n", ret
);
1405 return VM_FAULT_SIGBUS
;
1410 * i915_gem_release_mmap - remove physical page mappings
1411 * @obj: obj in question
1413 * Preserve the reservation of the mmapping with the DRM core code, but
1414 * relinquish ownership of the pages back to the system.
1416 * It is vital that we remove the page mapping if we have mapped a tiled
1417 * object through the GTT and then lose the fence register due to
1418 * resource pressure. Similarly if the object has been moved out of the
1419 * aperture, than pages mapped into userspace must be revoked. Removing the
1420 * mapping will then trigger a page fault on the next user access, allowing
1421 * fixup by i915_gem_fault().
1424 i915_gem_release_mmap(struct drm_i915_gem_object
*obj
)
1426 if (!obj
->fault_mappable
)
1429 if (obj
->base
.dev
->dev_mapping
)
1430 unmap_mapping_range(obj
->base
.dev
->dev_mapping
,
1431 (loff_t
)obj
->base
.map_list
.hash
.key
<<PAGE_SHIFT
,
1434 obj
->fault_mappable
= false;
1438 i915_gem_get_gtt_size(struct drm_device
*dev
, uint32_t size
, int tiling_mode
)
1442 if (INTEL_INFO(dev
)->gen
>= 4 ||
1443 tiling_mode
== I915_TILING_NONE
)
1446 /* Previous chips need a power-of-two fence region when tiling */
1447 if (INTEL_INFO(dev
)->gen
== 3)
1448 gtt_size
= 1024*1024;
1450 gtt_size
= 512*1024;
1452 while (gtt_size
< size
)
1459 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1460 * @obj: object to check
1462 * Return the required GTT alignment for an object, taking into account
1463 * potential fence register mapping.
1466 i915_gem_get_gtt_alignment(struct drm_device
*dev
, uint32_t size
,
1467 int tiling_mode
, bool fenced
)
1470 * Minimum alignment is 4k (GTT page size), but might be greater
1471 * if a fence register is needed for the object.
1473 if (INTEL_INFO(dev
)->gen
>= 4 || (!fenced
&& IS_G33(dev
)) ||
1474 tiling_mode
== I915_TILING_NONE
)
1478 * Previous chips need to be aligned to the size of the smallest
1479 * fence register that can contain the object.
1481 return i915_gem_get_gtt_size(dev
, size
, tiling_mode
);
1484 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object
*obj
)
1486 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
1489 if (obj
->base
.map_list
.map
)
1492 dev_priv
->mm
.shrinker_no_lock_stealing
= true;
1494 ret
= drm_gem_create_mmap_offset(&obj
->base
);
1498 /* Badly fragmented mmap space? The only way we can recover
1499 * space is by destroying unwanted objects. We can't randomly release
1500 * mmap_offsets as userspace expects them to be persistent for the
1501 * lifetime of the objects. The closest we can is to release the
1502 * offsets on purgeable objects by truncating it and marking it purged,
1503 * which prevents userspace from ever using that object again.
1505 i915_gem_purge(dev_priv
, obj
->base
.size
>> PAGE_SHIFT
);
1506 ret
= drm_gem_create_mmap_offset(&obj
->base
);
1510 i915_gem_shrink_all(dev_priv
);
1511 ret
= drm_gem_create_mmap_offset(&obj
->base
);
1513 dev_priv
->mm
.shrinker_no_lock_stealing
= false;
1518 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object
*obj
)
1520 if (!obj
->base
.map_list
.map
)
1523 drm_gem_free_mmap_offset(&obj
->base
);
1527 i915_gem_mmap_gtt(struct drm_file
*file
,
1528 struct drm_device
*dev
,
1532 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1533 struct drm_i915_gem_object
*obj
;
1536 ret
= i915_mutex_lock_interruptible(dev
);
1540 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, handle
));
1541 if (&obj
->base
== NULL
) {
1546 if (obj
->base
.size
> dev_priv
->gtt
.mappable_end
) {
1551 if (obj
->madv
!= I915_MADV_WILLNEED
) {
1552 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1557 ret
= i915_gem_object_create_mmap_offset(obj
);
1561 *offset
= (u64
)obj
->base
.map_list
.hash
.key
<< PAGE_SHIFT
;
1564 drm_gem_object_unreference(&obj
->base
);
1566 mutex_unlock(&dev
->struct_mutex
);
1571 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1573 * @data: GTT mapping ioctl data
1574 * @file: GEM object info
1576 * Simply returns the fake offset to userspace so it can mmap it.
1577 * The mmap call will end up in drm_gem_mmap(), which will set things
1578 * up so we can get faults in the handler above.
1580 * The fault handler will take care of binding the object into the GTT
1581 * (since it may have been evicted to make room for something), allocating
1582 * a fence register, and mapping the appropriate aperture address into
1586 i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
1587 struct drm_file
*file
)
1589 struct drm_i915_gem_mmap_gtt
*args
= data
;
1591 return i915_gem_mmap_gtt(file
, dev
, args
->handle
, &args
->offset
);
1594 /* Immediately discard the backing storage */
1596 i915_gem_object_truncate(struct drm_i915_gem_object
*obj
)
1598 struct inode
*inode
;
1600 i915_gem_object_free_mmap_offset(obj
);
1602 if (obj
->base
.filp
== NULL
)
1605 /* Our goal here is to return as much of the memory as
1606 * is possible back to the system as we are called from OOM.
1607 * To do this we must instruct the shmfs to drop all of its
1608 * backing pages, *now*.
1610 inode
= file_inode(obj
->base
.filp
);
1611 shmem_truncate_range(inode
, 0, (loff_t
)-1);
1613 obj
->madv
= __I915_MADV_PURGED
;
1617 i915_gem_object_is_purgeable(struct drm_i915_gem_object
*obj
)
1619 return obj
->madv
== I915_MADV_DONTNEED
;
1623 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object
*obj
)
1625 struct sg_page_iter sg_iter
;
1628 BUG_ON(obj
->madv
== __I915_MADV_PURGED
);
1630 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
1632 /* In the event of a disaster, abandon all caches and
1633 * hope for the best.
1635 WARN_ON(ret
!= -EIO
);
1636 i915_gem_clflush_object(obj
);
1637 obj
->base
.read_domains
= obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
1640 if (i915_gem_object_needs_bit17_swizzle(obj
))
1641 i915_gem_object_save_bit_17_swizzle(obj
);
1643 if (obj
->madv
== I915_MADV_DONTNEED
)
1646 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
, 0) {
1647 struct page
*page
= sg_page_iter_page(&sg_iter
);
1650 set_page_dirty(page
);
1652 if (obj
->madv
== I915_MADV_WILLNEED
)
1653 mark_page_accessed(page
);
1655 page_cache_release(page
);
1659 sg_free_table(obj
->pages
);
1664 i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
)
1666 const struct drm_i915_gem_object_ops
*ops
= obj
->ops
;
1668 if (obj
->pages
== NULL
)
1671 BUG_ON(obj
->gtt_space
);
1673 if (obj
->pages_pin_count
)
1676 /* ->put_pages might need to allocate memory for the bit17 swizzle
1677 * array, hence protect them from being reaped by removing them from gtt
1679 list_del(&obj
->gtt_list
);
1681 ops
->put_pages(obj
);
1684 if (i915_gem_object_is_purgeable(obj
))
1685 i915_gem_object_truncate(obj
);
1691 __i915_gem_shrink(struct drm_i915_private
*dev_priv
, long target
,
1692 bool purgeable_only
)
1694 struct drm_i915_gem_object
*obj
, *next
;
1697 list_for_each_entry_safe(obj
, next
,
1698 &dev_priv
->mm
.unbound_list
,
1700 if ((i915_gem_object_is_purgeable(obj
) || !purgeable_only
) &&
1701 i915_gem_object_put_pages(obj
) == 0) {
1702 count
+= obj
->base
.size
>> PAGE_SHIFT
;
1703 if (count
>= target
)
1708 list_for_each_entry_safe(obj
, next
,
1709 &dev_priv
->mm
.inactive_list
,
1711 if ((i915_gem_object_is_purgeable(obj
) || !purgeable_only
) &&
1712 i915_gem_object_unbind(obj
) == 0 &&
1713 i915_gem_object_put_pages(obj
) == 0) {
1714 count
+= obj
->base
.size
>> PAGE_SHIFT
;
1715 if (count
>= target
)
1724 i915_gem_purge(struct drm_i915_private
*dev_priv
, long target
)
1726 return __i915_gem_shrink(dev_priv
, target
, true);
1730 i915_gem_shrink_all(struct drm_i915_private
*dev_priv
)
1732 struct drm_i915_gem_object
*obj
, *next
;
1734 i915_gem_evict_everything(dev_priv
->dev
);
1736 list_for_each_entry_safe(obj
, next
, &dev_priv
->mm
.unbound_list
, gtt_list
)
1737 i915_gem_object_put_pages(obj
);
1741 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object
*obj
)
1743 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
1745 struct address_space
*mapping
;
1746 struct sg_table
*st
;
1747 struct scatterlist
*sg
;
1748 struct sg_page_iter sg_iter
;
1750 unsigned long last_pfn
= 0; /* suppress gcc warning */
1753 /* Assert that the object is not currently in any GPU domain. As it
1754 * wasn't in the GTT, there shouldn't be any way it could have been in
1757 BUG_ON(obj
->base
.read_domains
& I915_GEM_GPU_DOMAINS
);
1758 BUG_ON(obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
);
1760 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
1764 page_count
= obj
->base
.size
/ PAGE_SIZE
;
1765 if (sg_alloc_table(st
, page_count
, GFP_KERNEL
)) {
1771 /* Get the list of pages out of our struct file. They'll be pinned
1772 * at this point until we release them.
1774 * Fail silently without starting the shrinker
1776 mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
1777 gfp
= mapping_gfp_mask(mapping
);
1778 gfp
|= __GFP_NORETRY
| __GFP_NOWARN
| __GFP_NO_KSWAPD
;
1779 gfp
&= ~(__GFP_IO
| __GFP_WAIT
);
1782 for (i
= 0; i
< page_count
; i
++) {
1783 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
1785 i915_gem_purge(dev_priv
, page_count
);
1786 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
1789 /* We've tried hard to allocate the memory by reaping
1790 * our own buffer, now let the real VM do its job and
1791 * go down in flames if truly OOM.
1793 gfp
&= ~(__GFP_NORETRY
| __GFP_NOWARN
| __GFP_NO_KSWAPD
);
1794 gfp
|= __GFP_IO
| __GFP_WAIT
;
1796 i915_gem_shrink_all(dev_priv
);
1797 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
1801 gfp
|= __GFP_NORETRY
| __GFP_NOWARN
| __GFP_NO_KSWAPD
;
1802 gfp
&= ~(__GFP_IO
| __GFP_WAIT
);
1805 if (!i
|| page_to_pfn(page
) != last_pfn
+ 1) {
1809 sg_set_page(sg
, page
, PAGE_SIZE
, 0);
1811 sg
->length
+= PAGE_SIZE
;
1813 last_pfn
= page_to_pfn(page
);
1819 if (i915_gem_object_needs_bit17_swizzle(obj
))
1820 i915_gem_object_do_bit_17_swizzle(obj
);
1826 for_each_sg_page(st
->sgl
, &sg_iter
, st
->nents
, 0)
1827 page_cache_release(sg_page_iter_page(&sg_iter
));
1830 return PTR_ERR(page
);
1833 /* Ensure that the associated pages are gathered from the backing storage
1834 * and pinned into our object. i915_gem_object_get_pages() may be called
1835 * multiple times before they are released by a single call to
1836 * i915_gem_object_put_pages() - once the pages are no longer referenced
1837 * either as a result of memory pressure (reaping pages under the shrinker)
1838 * or as the object is itself released.
1841 i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
)
1843 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
1844 const struct drm_i915_gem_object_ops
*ops
= obj
->ops
;
1850 if (obj
->madv
!= I915_MADV_WILLNEED
) {
1851 DRM_ERROR("Attempting to obtain a purgeable object\n");
1855 BUG_ON(obj
->pages_pin_count
);
1857 ret
= ops
->get_pages(obj
);
1861 list_add_tail(&obj
->gtt_list
, &dev_priv
->mm
.unbound_list
);
1866 i915_gem_object_move_to_active(struct drm_i915_gem_object
*obj
,
1867 struct intel_ring_buffer
*ring
)
1869 struct drm_device
*dev
= obj
->base
.dev
;
1870 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1871 u32 seqno
= intel_ring_get_seqno(ring
);
1873 BUG_ON(ring
== NULL
);
1876 /* Add a reference if we're newly entering the active list. */
1878 drm_gem_object_reference(&obj
->base
);
1882 /* Move from whatever list we were on to the tail of execution. */
1883 list_move_tail(&obj
->mm_list
, &dev_priv
->mm
.active_list
);
1884 list_move_tail(&obj
->ring_list
, &ring
->active_list
);
1886 obj
->last_read_seqno
= seqno
;
1888 if (obj
->fenced_gpu_access
) {
1889 obj
->last_fenced_seqno
= seqno
;
1891 /* Bump MRU to take account of the delayed flush */
1892 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
1893 struct drm_i915_fence_reg
*reg
;
1895 reg
= &dev_priv
->fence_regs
[obj
->fence_reg
];
1896 list_move_tail(®
->lru_list
,
1897 &dev_priv
->mm
.fence_list
);
1903 i915_gem_object_move_to_inactive(struct drm_i915_gem_object
*obj
)
1905 struct drm_device
*dev
= obj
->base
.dev
;
1906 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1908 BUG_ON(obj
->base
.write_domain
& ~I915_GEM_GPU_DOMAINS
);
1909 BUG_ON(!obj
->active
);
1911 list_move_tail(&obj
->mm_list
, &dev_priv
->mm
.inactive_list
);
1913 list_del_init(&obj
->ring_list
);
1916 obj
->last_read_seqno
= 0;
1917 obj
->last_write_seqno
= 0;
1918 obj
->base
.write_domain
= 0;
1920 obj
->last_fenced_seqno
= 0;
1921 obj
->fenced_gpu_access
= false;
1924 drm_gem_object_unreference(&obj
->base
);
1926 WARN_ON(i915_verify_lists(dev
));
1930 i915_gem_init_seqno(struct drm_device
*dev
, u32 seqno
)
1932 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1933 struct intel_ring_buffer
*ring
;
1936 /* Carefully retire all requests without writing to the rings */
1937 for_each_ring(ring
, dev_priv
, i
) {
1938 ret
= intel_ring_idle(ring
);
1942 i915_gem_retire_requests(dev
);
1944 /* Finally reset hw state */
1945 for_each_ring(ring
, dev_priv
, i
) {
1946 intel_ring_init_seqno(ring
, seqno
);
1948 for (j
= 0; j
< ARRAY_SIZE(ring
->sync_seqno
); j
++)
1949 ring
->sync_seqno
[j
] = 0;
1955 int i915_gem_set_seqno(struct drm_device
*dev
, u32 seqno
)
1957 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1963 /* HWS page needs to be set less than what we
1964 * will inject to ring
1966 ret
= i915_gem_init_seqno(dev
, seqno
- 1);
1970 /* Carefully set the last_seqno value so that wrap
1971 * detection still works
1973 dev_priv
->next_seqno
= seqno
;
1974 dev_priv
->last_seqno
= seqno
- 1;
1975 if (dev_priv
->last_seqno
== 0)
1976 dev_priv
->last_seqno
--;
1982 i915_gem_get_seqno(struct drm_device
*dev
, u32
*seqno
)
1984 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1986 /* reserve 0 for non-seqno */
1987 if (dev_priv
->next_seqno
== 0) {
1988 int ret
= i915_gem_init_seqno(dev
, 0);
1992 dev_priv
->next_seqno
= 1;
1995 *seqno
= dev_priv
->last_seqno
= dev_priv
->next_seqno
++;
2000 i915_add_request(struct intel_ring_buffer
*ring
,
2001 struct drm_file
*file
,
2004 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
2005 struct drm_i915_gem_request
*request
;
2006 u32 request_ring_position
;
2011 * Emit any outstanding flushes - execbuf can fail to emit the flush
2012 * after having emitted the batchbuffer command. Hence we need to fix
2013 * things up similar to emitting the lazy request. The difference here
2014 * is that the flush _must_ happen before the next request, no matter
2017 ret
= intel_ring_flush_all_caches(ring
);
2021 request
= kmalloc(sizeof(*request
), GFP_KERNEL
);
2022 if (request
== NULL
)
2026 /* Record the position of the start of the request so that
2027 * should we detect the updated seqno part-way through the
2028 * GPU processing the request, we never over-estimate the
2029 * position of the head.
2031 request_ring_position
= intel_ring_get_tail(ring
);
2033 ret
= ring
->add_request(ring
);
2039 request
->seqno
= intel_ring_get_seqno(ring
);
2040 request
->ring
= ring
;
2041 request
->tail
= request_ring_position
;
2042 request
->emitted_jiffies
= jiffies
;
2043 was_empty
= list_empty(&ring
->request_list
);
2044 list_add_tail(&request
->list
, &ring
->request_list
);
2045 request
->file_priv
= NULL
;
2048 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
2050 spin_lock(&file_priv
->mm
.lock
);
2051 request
->file_priv
= file_priv
;
2052 list_add_tail(&request
->client_list
,
2053 &file_priv
->mm
.request_list
);
2054 spin_unlock(&file_priv
->mm
.lock
);
2057 trace_i915_gem_request_add(ring
, request
->seqno
);
2058 ring
->outstanding_lazy_request
= 0;
2060 if (!dev_priv
->mm
.suspended
) {
2061 if (i915_enable_hangcheck
) {
2062 mod_timer(&dev_priv
->gpu_error
.hangcheck_timer
,
2063 round_jiffies_up(jiffies
+ DRM_I915_HANGCHECK_JIFFIES
));
2066 queue_delayed_work(dev_priv
->wq
,
2067 &dev_priv
->mm
.retire_work
,
2068 round_jiffies_up_relative(HZ
));
2069 intel_mark_busy(dev_priv
->dev
);
2074 *out_seqno
= request
->seqno
;
2079 i915_gem_request_remove_from_client(struct drm_i915_gem_request
*request
)
2081 struct drm_i915_file_private
*file_priv
= request
->file_priv
;
2086 spin_lock(&file_priv
->mm
.lock
);
2087 if (request
->file_priv
) {
2088 list_del(&request
->client_list
);
2089 request
->file_priv
= NULL
;
2091 spin_unlock(&file_priv
->mm
.lock
);
2094 static void i915_gem_reset_ring_lists(struct drm_i915_private
*dev_priv
,
2095 struct intel_ring_buffer
*ring
)
2097 while (!list_empty(&ring
->request_list
)) {
2098 struct drm_i915_gem_request
*request
;
2100 request
= list_first_entry(&ring
->request_list
,
2101 struct drm_i915_gem_request
,
2104 list_del(&request
->list
);
2105 i915_gem_request_remove_from_client(request
);
2109 while (!list_empty(&ring
->active_list
)) {
2110 struct drm_i915_gem_object
*obj
;
2112 obj
= list_first_entry(&ring
->active_list
,
2113 struct drm_i915_gem_object
,
2116 i915_gem_object_move_to_inactive(obj
);
2120 static void i915_gem_reset_fences(struct drm_device
*dev
)
2122 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2125 for (i
= 0; i
< dev_priv
->num_fence_regs
; i
++) {
2126 struct drm_i915_fence_reg
*reg
= &dev_priv
->fence_regs
[i
];
2129 i915_gem_object_fence_lost(reg
->obj
);
2131 i915_gem_write_fence(dev
, i
, NULL
);
2135 INIT_LIST_HEAD(®
->lru_list
);
2138 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
2141 void i915_gem_reset(struct drm_device
*dev
)
2143 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2144 struct drm_i915_gem_object
*obj
;
2145 struct intel_ring_buffer
*ring
;
2148 for_each_ring(ring
, dev_priv
, i
)
2149 i915_gem_reset_ring_lists(dev_priv
, ring
);
2151 /* Move everything out of the GPU domains to ensure we do any
2152 * necessary invalidation upon reuse.
2154 list_for_each_entry(obj
,
2155 &dev_priv
->mm
.inactive_list
,
2158 obj
->base
.read_domains
&= ~I915_GEM_GPU_DOMAINS
;
2161 /* The fence registers are invalidated so clear them out */
2162 i915_gem_reset_fences(dev
);
2166 * This function clears the request list as sequence numbers are passed.
2169 i915_gem_retire_requests_ring(struct intel_ring_buffer
*ring
)
2173 if (list_empty(&ring
->request_list
))
2176 WARN_ON(i915_verify_lists(ring
->dev
));
2178 seqno
= ring
->get_seqno(ring
, true);
2180 while (!list_empty(&ring
->request_list
)) {
2181 struct drm_i915_gem_request
*request
;
2183 request
= list_first_entry(&ring
->request_list
,
2184 struct drm_i915_gem_request
,
2187 if (!i915_seqno_passed(seqno
, request
->seqno
))
2190 trace_i915_gem_request_retire(ring
, request
->seqno
);
2191 /* We know the GPU must have read the request to have
2192 * sent us the seqno + interrupt, so use the position
2193 * of tail of the request to update the last known position
2196 ring
->last_retired_head
= request
->tail
;
2198 list_del(&request
->list
);
2199 i915_gem_request_remove_from_client(request
);
2203 /* Move any buffers on the active list that are no longer referenced
2204 * by the ringbuffer to the flushing/inactive lists as appropriate.
2206 while (!list_empty(&ring
->active_list
)) {
2207 struct drm_i915_gem_object
*obj
;
2209 obj
= list_first_entry(&ring
->active_list
,
2210 struct drm_i915_gem_object
,
2213 if (!i915_seqno_passed(seqno
, obj
->last_read_seqno
))
2216 i915_gem_object_move_to_inactive(obj
);
2219 if (unlikely(ring
->trace_irq_seqno
&&
2220 i915_seqno_passed(seqno
, ring
->trace_irq_seqno
))) {
2221 ring
->irq_put(ring
);
2222 ring
->trace_irq_seqno
= 0;
2225 WARN_ON(i915_verify_lists(ring
->dev
));
2229 i915_gem_retire_requests(struct drm_device
*dev
)
2231 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2232 struct intel_ring_buffer
*ring
;
2235 for_each_ring(ring
, dev_priv
, i
)
2236 i915_gem_retire_requests_ring(ring
);
2240 i915_gem_retire_work_handler(struct work_struct
*work
)
2242 drm_i915_private_t
*dev_priv
;
2243 struct drm_device
*dev
;
2244 struct intel_ring_buffer
*ring
;
2248 dev_priv
= container_of(work
, drm_i915_private_t
,
2249 mm
.retire_work
.work
);
2250 dev
= dev_priv
->dev
;
2252 /* Come back later if the device is busy... */
2253 if (!mutex_trylock(&dev
->struct_mutex
)) {
2254 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
,
2255 round_jiffies_up_relative(HZ
));
2259 i915_gem_retire_requests(dev
);
2261 /* Send a periodic flush down the ring so we don't hold onto GEM
2262 * objects indefinitely.
2265 for_each_ring(ring
, dev_priv
, i
) {
2266 if (ring
->gpu_caches_dirty
)
2267 i915_add_request(ring
, NULL
, NULL
);
2269 idle
&= list_empty(&ring
->request_list
);
2272 if (!dev_priv
->mm
.suspended
&& !idle
)
2273 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
,
2274 round_jiffies_up_relative(HZ
));
2276 intel_mark_idle(dev
);
2278 mutex_unlock(&dev
->struct_mutex
);
2282 * Ensures that an object will eventually get non-busy by flushing any required
2283 * write domains, emitting any outstanding lazy request and retiring and
2284 * completed requests.
2287 i915_gem_object_flush_active(struct drm_i915_gem_object
*obj
)
2292 ret
= i915_gem_check_olr(obj
->ring
, obj
->last_read_seqno
);
2296 i915_gem_retire_requests_ring(obj
->ring
);
2303 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2304 * @DRM_IOCTL_ARGS: standard ioctl arguments
2306 * Returns 0 if successful, else an error is returned with the remaining time in
2307 * the timeout parameter.
2308 * -ETIME: object is still busy after timeout
2309 * -ERESTARTSYS: signal interrupted the wait
2310 * -ENONENT: object doesn't exist
2311 * Also possible, but rare:
2312 * -EAGAIN: GPU wedged
2314 * -ENODEV: Internal IRQ fail
2315 * -E?: The add request failed
2317 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2318 * non-zero timeout parameter the wait ioctl will wait for the given number of
2319 * nanoseconds on an object becoming unbusy. Since the wait itself does so
2320 * without holding struct_mutex the object may become re-busied before this
2321 * function completes. A similar but shorter * race condition exists in the busy
2325 i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
, struct drm_file
*file
)
2327 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2328 struct drm_i915_gem_wait
*args
= data
;
2329 struct drm_i915_gem_object
*obj
;
2330 struct intel_ring_buffer
*ring
= NULL
;
2331 struct timespec timeout_stack
, *timeout
= NULL
;
2332 unsigned reset_counter
;
2336 if (args
->timeout_ns
>= 0) {
2337 timeout_stack
= ns_to_timespec(args
->timeout_ns
);
2338 timeout
= &timeout_stack
;
2341 ret
= i915_mutex_lock_interruptible(dev
);
2345 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->bo_handle
));
2346 if (&obj
->base
== NULL
) {
2347 mutex_unlock(&dev
->struct_mutex
);
2351 /* Need to make sure the object gets inactive eventually. */
2352 ret
= i915_gem_object_flush_active(obj
);
2357 seqno
= obj
->last_read_seqno
;
2364 /* Do this after OLR check to make sure we make forward progress polling
2365 * on this IOCTL with a 0 timeout (like busy ioctl)
2367 if (!args
->timeout_ns
) {
2372 drm_gem_object_unreference(&obj
->base
);
2373 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
2374 mutex_unlock(&dev
->struct_mutex
);
2376 ret
= __wait_seqno(ring
, seqno
, reset_counter
, true, timeout
);
2378 args
->timeout_ns
= timespec_to_ns(timeout
);
2382 drm_gem_object_unreference(&obj
->base
);
2383 mutex_unlock(&dev
->struct_mutex
);
2388 * i915_gem_object_sync - sync an object to a ring.
2390 * @obj: object which may be in use on another ring.
2391 * @to: ring we wish to use the object on. May be NULL.
2393 * This code is meant to abstract object synchronization with the GPU.
2394 * Calling with NULL implies synchronizing the object with the CPU
2395 * rather than a particular GPU ring.
2397 * Returns 0 if successful, else propagates up the lower layer error.
2400 i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
2401 struct intel_ring_buffer
*to
)
2403 struct intel_ring_buffer
*from
= obj
->ring
;
2407 if (from
== NULL
|| to
== from
)
2410 if (to
== NULL
|| !i915_semaphore_is_enabled(obj
->base
.dev
))
2411 return i915_gem_object_wait_rendering(obj
, false);
2413 idx
= intel_ring_sync_index(from
, to
);
2415 seqno
= obj
->last_read_seqno
;
2416 if (seqno
<= from
->sync_seqno
[idx
])
2419 ret
= i915_gem_check_olr(obj
->ring
, seqno
);
2423 ret
= to
->sync_to(to
, from
, seqno
);
2425 /* We use last_read_seqno because sync_to()
2426 * might have just caused seqno wrap under
2429 from
->sync_seqno
[idx
] = obj
->last_read_seqno
;
2434 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object
*obj
)
2436 u32 old_write_domain
, old_read_domains
;
2438 /* Force a pagefault for domain tracking on next user access */
2439 i915_gem_release_mmap(obj
);
2441 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
) == 0)
2444 /* Wait for any direct GTT access to complete */
2447 old_read_domains
= obj
->base
.read_domains
;
2448 old_write_domain
= obj
->base
.write_domain
;
2450 obj
->base
.read_domains
&= ~I915_GEM_DOMAIN_GTT
;
2451 obj
->base
.write_domain
&= ~I915_GEM_DOMAIN_GTT
;
2453 trace_i915_gem_object_change_domain(obj
,
2459 * Unbinds an object from the GTT aperture.
2462 i915_gem_object_unbind(struct drm_i915_gem_object
*obj
)
2464 drm_i915_private_t
*dev_priv
= obj
->base
.dev
->dev_private
;
2467 if (obj
->gtt_space
== NULL
)
2473 BUG_ON(obj
->pages
== NULL
);
2475 ret
= i915_gem_object_finish_gpu(obj
);
2478 /* Continue on if we fail due to EIO, the GPU is hung so we
2479 * should be safe and we need to cleanup or else we might
2480 * cause memory corruption through use-after-free.
2483 i915_gem_object_finish_gtt(obj
);
2485 /* release the fence reg _after_ flushing */
2486 ret
= i915_gem_object_put_fence(obj
);
2490 trace_i915_gem_object_unbind(obj
);
2492 if (obj
->has_global_gtt_mapping
)
2493 i915_gem_gtt_unbind_object(obj
);
2494 if (obj
->has_aliasing_ppgtt_mapping
) {
2495 i915_ppgtt_unbind_object(dev_priv
->mm
.aliasing_ppgtt
, obj
);
2496 obj
->has_aliasing_ppgtt_mapping
= 0;
2498 i915_gem_gtt_finish_object(obj
);
2500 list_del(&obj
->mm_list
);
2501 list_move_tail(&obj
->gtt_list
, &dev_priv
->mm
.unbound_list
);
2502 /* Avoid an unnecessary call to unbind on rebind. */
2503 obj
->map_and_fenceable
= true;
2505 drm_mm_put_block(obj
->gtt_space
);
2506 obj
->gtt_space
= NULL
;
2507 obj
->gtt_offset
= 0;
2512 int i915_gpu_idle(struct drm_device
*dev
)
2514 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2515 struct intel_ring_buffer
*ring
;
2518 /* Flush everything onto the inactive list. */
2519 for_each_ring(ring
, dev_priv
, i
) {
2520 ret
= i915_switch_context(ring
, NULL
, DEFAULT_CONTEXT_ID
);
2524 ret
= intel_ring_idle(ring
);
2532 static void i965_write_fence_reg(struct drm_device
*dev
, int reg
,
2533 struct drm_i915_gem_object
*obj
)
2535 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2537 int fence_pitch_shift
;
2540 if (INTEL_INFO(dev
)->gen
>= 6) {
2541 fence_reg
= FENCE_REG_SANDYBRIDGE_0
;
2542 fence_pitch_shift
= SANDYBRIDGE_FENCE_PITCH_SHIFT
;
2544 fence_reg
= FENCE_REG_965_0
;
2545 fence_pitch_shift
= I965_FENCE_PITCH_SHIFT
;
2549 u32 size
= obj
->gtt_space
->size
;
2551 val
= (uint64_t)((obj
->gtt_offset
+ size
- 4096) &
2553 val
|= obj
->gtt_offset
& 0xfffff000;
2554 val
|= (uint64_t)((obj
->stride
/ 128) - 1) << fence_pitch_shift
;
2555 if (obj
->tiling_mode
== I915_TILING_Y
)
2556 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
2557 val
|= I965_FENCE_REG_VALID
;
2561 fence_reg
+= reg
* 8;
2562 I915_WRITE64(fence_reg
, val
);
2563 POSTING_READ(fence_reg
);
2566 static void i915_write_fence_reg(struct drm_device
*dev
, int reg
,
2567 struct drm_i915_gem_object
*obj
)
2569 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2573 u32 size
= obj
->gtt_space
->size
;
2577 WARN((obj
->gtt_offset
& ~I915_FENCE_START_MASK
) ||
2578 (size
& -size
) != size
||
2579 (obj
->gtt_offset
& (size
- 1)),
2580 "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2581 obj
->gtt_offset
, obj
->map_and_fenceable
, size
);
2583 if (obj
->tiling_mode
== I915_TILING_Y
&& HAS_128_BYTE_Y_TILING(dev
))
2588 /* Note: pitch better be a power of two tile widths */
2589 pitch_val
= obj
->stride
/ tile_width
;
2590 pitch_val
= ffs(pitch_val
) - 1;
2592 val
= obj
->gtt_offset
;
2593 if (obj
->tiling_mode
== I915_TILING_Y
)
2594 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2595 val
|= I915_FENCE_SIZE_BITS(size
);
2596 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2597 val
|= I830_FENCE_REG_VALID
;
2602 reg
= FENCE_REG_830_0
+ reg
* 4;
2604 reg
= FENCE_REG_945_8
+ (reg
- 8) * 4;
2606 I915_WRITE(reg
, val
);
2610 static void i830_write_fence_reg(struct drm_device
*dev
, int reg
,
2611 struct drm_i915_gem_object
*obj
)
2613 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2617 u32 size
= obj
->gtt_space
->size
;
2620 WARN((obj
->gtt_offset
& ~I830_FENCE_START_MASK
) ||
2621 (size
& -size
) != size
||
2622 (obj
->gtt_offset
& (size
- 1)),
2623 "object 0x%08x not 512K or pot-size 0x%08x aligned\n",
2624 obj
->gtt_offset
, size
);
2626 pitch_val
= obj
->stride
/ 128;
2627 pitch_val
= ffs(pitch_val
) - 1;
2629 val
= obj
->gtt_offset
;
2630 if (obj
->tiling_mode
== I915_TILING_Y
)
2631 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2632 val
|= I830_FENCE_SIZE_BITS(size
);
2633 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2634 val
|= I830_FENCE_REG_VALID
;
2638 I915_WRITE(FENCE_REG_830_0
+ reg
* 4, val
);
2639 POSTING_READ(FENCE_REG_830_0
+ reg
* 4);
2642 inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object
*obj
)
2644 return obj
&& obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
;
2647 static void i915_gem_write_fence(struct drm_device
*dev
, int reg
,
2648 struct drm_i915_gem_object
*obj
)
2650 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2652 /* Ensure that all CPU reads are completed before installing a fence
2653 * and all writes before removing the fence.
2655 if (i915_gem_object_needs_mb(dev_priv
->fence_regs
[reg
].obj
))
2658 switch (INTEL_INFO(dev
)->gen
) {
2662 case 4: i965_write_fence_reg(dev
, reg
, obj
); break;
2663 case 3: i915_write_fence_reg(dev
, reg
, obj
); break;
2664 case 2: i830_write_fence_reg(dev
, reg
, obj
); break;
2668 /* And similarly be paranoid that no direct access to this region
2669 * is reordered to before the fence is installed.
2671 if (i915_gem_object_needs_mb(obj
))
2675 static inline int fence_number(struct drm_i915_private
*dev_priv
,
2676 struct drm_i915_fence_reg
*fence
)
2678 return fence
- dev_priv
->fence_regs
;
2681 static void i915_gem_write_fence__ipi(void *data
)
2686 static void i915_gem_object_update_fence(struct drm_i915_gem_object
*obj
,
2687 struct drm_i915_fence_reg
*fence
,
2690 struct drm_device
*dev
= obj
->base
.dev
;
2691 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2692 int fence_reg
= fence_number(dev_priv
, fence
);
2694 /* In order to fully serialize access to the fenced region and
2695 * the update to the fence register we need to take extreme
2696 * measures on SNB+. In theory, the write to the fence register
2697 * flushes all memory transactions before, and coupled with the
2698 * mb() placed around the register write we serialise all memory
2699 * operations with respect to the changes in the tiler. Yet, on
2700 * SNB+ we need to take a step further and emit an explicit wbinvd()
2701 * on each processor in order to manually flush all memory
2702 * transactions before updating the fence register.
2704 if (HAS_LLC(obj
->base
.dev
))
2705 on_each_cpu(i915_gem_write_fence__ipi
, NULL
, 1);
2706 i915_gem_write_fence(dev
, fence_reg
, enable
? obj
: NULL
);
2709 obj
->fence_reg
= fence_reg
;
2711 list_move_tail(&fence
->lru_list
, &dev_priv
->mm
.fence_list
);
2713 obj
->fence_reg
= I915_FENCE_REG_NONE
;
2715 list_del_init(&fence
->lru_list
);
2720 i915_gem_object_wait_fence(struct drm_i915_gem_object
*obj
)
2722 if (obj
->last_fenced_seqno
) {
2723 int ret
= i915_wait_seqno(obj
->ring
, obj
->last_fenced_seqno
);
2727 obj
->last_fenced_seqno
= 0;
2730 obj
->fenced_gpu_access
= false;
2735 i915_gem_object_put_fence(struct drm_i915_gem_object
*obj
)
2737 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2738 struct drm_i915_fence_reg
*fence
;
2741 ret
= i915_gem_object_wait_fence(obj
);
2745 if (obj
->fence_reg
== I915_FENCE_REG_NONE
)
2748 fence
= &dev_priv
->fence_regs
[obj
->fence_reg
];
2750 i915_gem_object_fence_lost(obj
);
2751 i915_gem_object_update_fence(obj
, fence
, false);
2756 static struct drm_i915_fence_reg
*
2757 i915_find_fence_reg(struct drm_device
*dev
)
2759 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2760 struct drm_i915_fence_reg
*reg
, *avail
;
2763 /* First try to find a free reg */
2765 for (i
= dev_priv
->fence_reg_start
; i
< dev_priv
->num_fence_regs
; i
++) {
2766 reg
= &dev_priv
->fence_regs
[i
];
2770 if (!reg
->pin_count
)
2777 /* None available, try to steal one or wait for a user to finish */
2778 list_for_each_entry(reg
, &dev_priv
->mm
.fence_list
, lru_list
) {
2789 * i915_gem_object_get_fence - set up fencing for an object
2790 * @obj: object to map through a fence reg
2792 * When mapping objects through the GTT, userspace wants to be able to write
2793 * to them without having to worry about swizzling if the object is tiled.
2794 * This function walks the fence regs looking for a free one for @obj,
2795 * stealing one if it can't find any.
2797 * It then sets up the reg based on the object's properties: address, pitch
2798 * and tiling format.
2800 * For an untiled surface, this removes any existing fence.
2803 i915_gem_object_get_fence(struct drm_i915_gem_object
*obj
)
2805 struct drm_device
*dev
= obj
->base
.dev
;
2806 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2807 bool enable
= obj
->tiling_mode
!= I915_TILING_NONE
;
2808 struct drm_i915_fence_reg
*reg
;
2811 /* Have we updated the tiling parameters upon the object and so
2812 * will need to serialise the write to the associated fence register?
2814 if (obj
->fence_dirty
) {
2815 ret
= i915_gem_object_wait_fence(obj
);
2820 /* Just update our place in the LRU if our fence is getting reused. */
2821 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
2822 reg
= &dev_priv
->fence_regs
[obj
->fence_reg
];
2823 if (!obj
->fence_dirty
) {
2824 list_move_tail(®
->lru_list
,
2825 &dev_priv
->mm
.fence_list
);
2828 } else if (enable
) {
2829 reg
= i915_find_fence_reg(dev
);
2834 struct drm_i915_gem_object
*old
= reg
->obj
;
2836 ret
= i915_gem_object_wait_fence(old
);
2840 i915_gem_object_fence_lost(old
);
2845 i915_gem_object_update_fence(obj
, reg
, enable
);
2846 obj
->fence_dirty
= false;
2851 static bool i915_gem_valid_gtt_space(struct drm_device
*dev
,
2852 struct drm_mm_node
*gtt_space
,
2853 unsigned long cache_level
)
2855 struct drm_mm_node
*other
;
2857 /* On non-LLC machines we have to be careful when putting differing
2858 * types of snoopable memory together to avoid the prefetcher
2859 * crossing memory domains and dying.
2864 if (gtt_space
== NULL
)
2867 if (list_empty(>t_space
->node_list
))
2870 other
= list_entry(gtt_space
->node_list
.prev
, struct drm_mm_node
, node_list
);
2871 if (other
->allocated
&& !other
->hole_follows
&& other
->color
!= cache_level
)
2874 other
= list_entry(gtt_space
->node_list
.next
, struct drm_mm_node
, node_list
);
2875 if (other
->allocated
&& !gtt_space
->hole_follows
&& other
->color
!= cache_level
)
2881 static void i915_gem_verify_gtt(struct drm_device
*dev
)
2884 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2885 struct drm_i915_gem_object
*obj
;
2888 list_for_each_entry(obj
, &dev_priv
->mm
.gtt_list
, gtt_list
) {
2889 if (obj
->gtt_space
== NULL
) {
2890 printk(KERN_ERR
"object found on GTT list with no space reserved\n");
2895 if (obj
->cache_level
!= obj
->gtt_space
->color
) {
2896 printk(KERN_ERR
"object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n",
2897 obj
->gtt_space
->start
,
2898 obj
->gtt_space
->start
+ obj
->gtt_space
->size
,
2900 obj
->gtt_space
->color
);
2905 if (!i915_gem_valid_gtt_space(dev
,
2907 obj
->cache_level
)) {
2908 printk(KERN_ERR
"invalid GTT space found at [%08lx, %08lx] - color=%x\n",
2909 obj
->gtt_space
->start
,
2910 obj
->gtt_space
->start
+ obj
->gtt_space
->size
,
2922 * Finds free space in the GTT aperture and binds the object there.
2925 i915_gem_object_bind_to_gtt(struct drm_i915_gem_object
*obj
,
2927 bool map_and_fenceable
,
2930 struct drm_device
*dev
= obj
->base
.dev
;
2931 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2932 struct drm_mm_node
*node
;
2933 u32 size
, fence_size
, fence_alignment
, unfenced_alignment
;
2934 bool mappable
, fenceable
;
2937 fence_size
= i915_gem_get_gtt_size(dev
,
2940 fence_alignment
= i915_gem_get_gtt_alignment(dev
,
2942 obj
->tiling_mode
, true);
2943 unfenced_alignment
=
2944 i915_gem_get_gtt_alignment(dev
,
2946 obj
->tiling_mode
, false);
2949 alignment
= map_and_fenceable
? fence_alignment
:
2951 if (map_and_fenceable
&& alignment
& (fence_alignment
- 1)) {
2952 DRM_ERROR("Invalid object alignment requested %u\n", alignment
);
2956 size
= map_and_fenceable
? fence_size
: obj
->base
.size
;
2958 /* If the object is bigger than the entire aperture, reject it early
2959 * before evicting everything in a vain attempt to find space.
2961 if (obj
->base
.size
>
2962 (map_and_fenceable
? dev_priv
->gtt
.mappable_end
: dev_priv
->gtt
.total
)) {
2963 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2967 ret
= i915_gem_object_get_pages(obj
);
2971 i915_gem_object_pin_pages(obj
);
2973 node
= kzalloc(sizeof(*node
), GFP_KERNEL
);
2975 i915_gem_object_unpin_pages(obj
);
2980 if (map_and_fenceable
)
2981 ret
= drm_mm_insert_node_in_range_generic(&dev_priv
->mm
.gtt_space
, node
,
2982 size
, alignment
, obj
->cache_level
,
2983 0, dev_priv
->gtt
.mappable_end
);
2985 ret
= drm_mm_insert_node_generic(&dev_priv
->mm
.gtt_space
, node
,
2986 size
, alignment
, obj
->cache_level
);
2988 ret
= i915_gem_evict_something(dev
, size
, alignment
,
2995 i915_gem_object_unpin_pages(obj
);
2999 if (WARN_ON(!i915_gem_valid_gtt_space(dev
, node
, obj
->cache_level
))) {
3000 i915_gem_object_unpin_pages(obj
);
3001 drm_mm_put_block(node
);
3005 ret
= i915_gem_gtt_prepare_object(obj
);
3007 i915_gem_object_unpin_pages(obj
);
3008 drm_mm_put_block(node
);
3012 list_move_tail(&obj
->gtt_list
, &dev_priv
->mm
.bound_list
);
3013 list_add_tail(&obj
->mm_list
, &dev_priv
->mm
.inactive_list
);
3015 obj
->gtt_space
= node
;
3016 obj
->gtt_offset
= node
->start
;
3019 node
->size
== fence_size
&&
3020 (node
->start
& (fence_alignment
- 1)) == 0;
3023 obj
->gtt_offset
+ obj
->base
.size
<= dev_priv
->gtt
.mappable_end
;
3025 obj
->map_and_fenceable
= mappable
&& fenceable
;
3027 i915_gem_object_unpin_pages(obj
);
3028 trace_i915_gem_object_bind(obj
, map_and_fenceable
);
3029 i915_gem_verify_gtt(dev
);
3034 i915_gem_clflush_object(struct drm_i915_gem_object
*obj
)
3036 /* If we don't have a page list set up, then we're not pinned
3037 * to GPU, and we can ignore the cache flush because it'll happen
3038 * again at bind time.
3040 if (obj
->pages
== NULL
)
3044 * Stolen memory is always coherent with the GPU as it is explicitly
3045 * marked as wc by the system, or the system is cache-coherent.
3050 /* If the GPU is snooping the contents of the CPU cache,
3051 * we do not need to manually clear the CPU cache lines. However,
3052 * the caches are only snooped when the render cache is
3053 * flushed/invalidated. As we always have to emit invalidations
3054 * and flushes when moving into and out of the RENDER domain, correct
3055 * snooping behaviour occurs naturally as the result of our domain
3058 if (obj
->cache_level
!= I915_CACHE_NONE
)
3061 trace_i915_gem_object_clflush(obj
);
3063 drm_clflush_sg(obj
->pages
);
3066 /** Flushes the GTT write domain for the object if it's dirty. */
3068 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
)
3070 uint32_t old_write_domain
;
3072 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_GTT
)
3075 /* No actual flushing is required for the GTT write domain. Writes
3076 * to it immediately go to main memory as far as we know, so there's
3077 * no chipset flush. It also doesn't land in render cache.
3079 * However, we do have to enforce the order so that all writes through
3080 * the GTT land before any writes to the device, such as updates to
3085 old_write_domain
= obj
->base
.write_domain
;
3086 obj
->base
.write_domain
= 0;
3088 trace_i915_gem_object_change_domain(obj
,
3089 obj
->base
.read_domains
,
3093 /** Flushes the CPU write domain for the object if it's dirty. */
3095 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
)
3097 uint32_t old_write_domain
;
3099 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
)
3102 i915_gem_clflush_object(obj
);
3103 i915_gem_chipset_flush(obj
->base
.dev
);
3104 old_write_domain
= obj
->base
.write_domain
;
3105 obj
->base
.write_domain
= 0;
3107 trace_i915_gem_object_change_domain(obj
,
3108 obj
->base
.read_domains
,
3113 * Moves a single object to the GTT read, and possibly write domain.
3115 * This function returns when the move is complete, including waiting on
3119 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
, bool write
)
3121 drm_i915_private_t
*dev_priv
= obj
->base
.dev
->dev_private
;
3122 uint32_t old_write_domain
, old_read_domains
;
3125 /* Not valid to be called on unbound objects. */
3126 if (obj
->gtt_space
== NULL
)
3129 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_GTT
)
3132 ret
= i915_gem_object_wait_rendering(obj
, !write
);
3136 i915_gem_object_flush_cpu_write_domain(obj
);
3138 /* Serialise direct access to this object with the barriers for
3139 * coherent writes from the GPU, by effectively invalidating the
3140 * GTT domain upon first access.
3142 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
) == 0)
3145 old_write_domain
= obj
->base
.write_domain
;
3146 old_read_domains
= obj
->base
.read_domains
;
3148 /* It should now be out of any other write domains, and we can update
3149 * the domain values for our changes.
3151 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
3152 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
3154 obj
->base
.read_domains
= I915_GEM_DOMAIN_GTT
;
3155 obj
->base
.write_domain
= I915_GEM_DOMAIN_GTT
;
3159 trace_i915_gem_object_change_domain(obj
,
3163 /* And bump the LRU for this access */
3164 if (i915_gem_object_is_inactive(obj
))
3165 list_move_tail(&obj
->mm_list
, &dev_priv
->mm
.inactive_list
);
3170 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
3171 enum i915_cache_level cache_level
)
3173 struct drm_device
*dev
= obj
->base
.dev
;
3174 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3177 if (obj
->cache_level
== cache_level
)
3180 if (obj
->pin_count
) {
3181 DRM_DEBUG("can not change the cache level of pinned objects\n");
3185 if (!i915_gem_valid_gtt_space(dev
, obj
->gtt_space
, cache_level
)) {
3186 ret
= i915_gem_object_unbind(obj
);
3191 if (obj
->gtt_space
) {
3192 ret
= i915_gem_object_finish_gpu(obj
);
3196 i915_gem_object_finish_gtt(obj
);
3198 /* Before SandyBridge, you could not use tiling or fence
3199 * registers with snooped memory, so relinquish any fences
3200 * currently pointing to our region in the aperture.
3202 if (INTEL_INFO(dev
)->gen
< 6) {
3203 ret
= i915_gem_object_put_fence(obj
);
3208 if (obj
->has_global_gtt_mapping
)
3209 i915_gem_gtt_bind_object(obj
, cache_level
);
3210 if (obj
->has_aliasing_ppgtt_mapping
)
3211 i915_ppgtt_bind_object(dev_priv
->mm
.aliasing_ppgtt
,
3214 obj
->gtt_space
->color
= cache_level
;
3217 if (cache_level
== I915_CACHE_NONE
) {
3218 u32 old_read_domains
, old_write_domain
;
3220 /* If we're coming from LLC cached, then we haven't
3221 * actually been tracking whether the data is in the
3222 * CPU cache or not, since we only allow one bit set
3223 * in obj->write_domain and have been skipping the clflushes.
3224 * Just set it to the CPU cache for now.
3226 WARN_ON(obj
->base
.write_domain
& ~I915_GEM_DOMAIN_CPU
);
3227 WARN_ON(obj
->base
.read_domains
& ~I915_GEM_DOMAIN_CPU
);
3229 old_read_domains
= obj
->base
.read_domains
;
3230 old_write_domain
= obj
->base
.write_domain
;
3232 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
3233 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
3235 trace_i915_gem_object_change_domain(obj
,
3240 obj
->cache_level
= cache_level
;
3241 i915_gem_verify_gtt(dev
);
3245 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
3246 struct drm_file
*file
)
3248 struct drm_i915_gem_caching
*args
= data
;
3249 struct drm_i915_gem_object
*obj
;
3252 ret
= i915_mutex_lock_interruptible(dev
);
3256 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3257 if (&obj
->base
== NULL
) {
3262 args
->caching
= obj
->cache_level
!= I915_CACHE_NONE
;
3264 drm_gem_object_unreference(&obj
->base
);
3266 mutex_unlock(&dev
->struct_mutex
);
3270 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
3271 struct drm_file
*file
)
3273 struct drm_i915_gem_caching
*args
= data
;
3274 struct drm_i915_gem_object
*obj
;
3275 enum i915_cache_level level
;
3278 switch (args
->caching
) {
3279 case I915_CACHING_NONE
:
3280 level
= I915_CACHE_NONE
;
3282 case I915_CACHING_CACHED
:
3283 level
= I915_CACHE_LLC
;
3289 ret
= i915_mutex_lock_interruptible(dev
);
3293 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3294 if (&obj
->base
== NULL
) {
3299 ret
= i915_gem_object_set_cache_level(obj
, level
);
3301 drm_gem_object_unreference(&obj
->base
);
3303 mutex_unlock(&dev
->struct_mutex
);
3308 * Prepare buffer for display plane (scanout, cursors, etc).
3309 * Can be called from an uninterruptible phase (modesetting) and allows
3310 * any flushes to be pipelined (for pageflips).
3313 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
3315 struct intel_ring_buffer
*pipelined
)
3317 u32 old_read_domains
, old_write_domain
;
3320 if (pipelined
!= obj
->ring
) {
3321 ret
= i915_gem_object_sync(obj
, pipelined
);
3326 /* The display engine is not coherent with the LLC cache on gen6. As
3327 * a result, we make sure that the pinning that is about to occur is
3328 * done with uncached PTEs. This is lowest common denominator for all
3331 * However for gen6+, we could do better by using the GFDT bit instead
3332 * of uncaching, which would allow us to flush all the LLC-cached data
3333 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3335 ret
= i915_gem_object_set_cache_level(obj
, I915_CACHE_NONE
);
3339 /* As the user may map the buffer once pinned in the display plane
3340 * (e.g. libkms for the bootup splash), we have to ensure that we
3341 * always use map_and_fenceable for all scanout buffers.
3343 ret
= i915_gem_object_pin(obj
, alignment
, true, false);
3347 i915_gem_object_flush_cpu_write_domain(obj
);
3349 old_write_domain
= obj
->base
.write_domain
;
3350 old_read_domains
= obj
->base
.read_domains
;
3352 /* It should now be out of any other write domains, and we can update
3353 * the domain values for our changes.
3355 obj
->base
.write_domain
= 0;
3356 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
3358 trace_i915_gem_object_change_domain(obj
,
3366 i915_gem_object_finish_gpu(struct drm_i915_gem_object
*obj
)
3370 if ((obj
->base
.read_domains
& I915_GEM_GPU_DOMAINS
) == 0)
3373 ret
= i915_gem_object_wait_rendering(obj
, false);
3377 /* Ensure that we invalidate the GPU's caches and TLBs. */
3378 obj
->base
.read_domains
&= ~I915_GEM_GPU_DOMAINS
;
3383 * Moves a single object to the CPU read, and possibly write domain.
3385 * This function returns when the move is complete, including waiting on
3389 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
)
3391 uint32_t old_write_domain
, old_read_domains
;
3394 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_CPU
)
3397 ret
= i915_gem_object_wait_rendering(obj
, !write
);
3401 i915_gem_object_flush_gtt_write_domain(obj
);
3403 old_write_domain
= obj
->base
.write_domain
;
3404 old_read_domains
= obj
->base
.read_domains
;
3406 /* Flush the CPU cache if it's still invalid. */
3407 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) == 0) {
3408 i915_gem_clflush_object(obj
);
3410 obj
->base
.read_domains
|= I915_GEM_DOMAIN_CPU
;
3413 /* It should now be out of any other write domains, and we can update
3414 * the domain values for our changes.
3416 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
3418 /* If we're writing through the CPU, then the GPU read domains will
3419 * need to be invalidated at next use.
3422 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
3423 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
3426 trace_i915_gem_object_change_domain(obj
,
3433 /* Throttle our rendering by waiting until the ring has completed our requests
3434 * emitted over 20 msec ago.
3436 * Note that if we were to use the current jiffies each time around the loop,
3437 * we wouldn't escape the function with any frames outstanding if the time to
3438 * render a frame was over 20ms.
3440 * This should get us reasonable parallelism between CPU and GPU but also
3441 * relatively low latency when blocking on a particular request to finish.
3444 i915_gem_ring_throttle(struct drm_device
*dev
, struct drm_file
*file
)
3446 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3447 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
3448 unsigned long recent_enough
= jiffies
- msecs_to_jiffies(20);
3449 struct drm_i915_gem_request
*request
;
3450 struct intel_ring_buffer
*ring
= NULL
;
3451 unsigned reset_counter
;
3455 ret
= i915_gem_wait_for_error(&dev_priv
->gpu_error
);
3459 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, false);
3463 spin_lock(&file_priv
->mm
.lock
);
3464 list_for_each_entry(request
, &file_priv
->mm
.request_list
, client_list
) {
3465 if (time_after_eq(request
->emitted_jiffies
, recent_enough
))
3468 ring
= request
->ring
;
3469 seqno
= request
->seqno
;
3471 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
3472 spin_unlock(&file_priv
->mm
.lock
);
3477 ret
= __wait_seqno(ring
, seqno
, reset_counter
, true, NULL
);
3479 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, 0);
3485 i915_gem_object_pin(struct drm_i915_gem_object
*obj
,
3487 bool map_and_fenceable
,
3492 if (WARN_ON(obj
->pin_count
== DRM_I915_GEM_OBJECT_MAX_PIN_COUNT
))
3495 if (obj
->gtt_space
!= NULL
) {
3496 if ((alignment
&& obj
->gtt_offset
& (alignment
- 1)) ||
3497 (map_and_fenceable
&& !obj
->map_and_fenceable
)) {
3498 WARN(obj
->pin_count
,
3499 "bo is already pinned with incorrect alignment:"
3500 " offset=%x, req.alignment=%x, req.map_and_fenceable=%d,"
3501 " obj->map_and_fenceable=%d\n",
3502 obj
->gtt_offset
, alignment
,
3504 obj
->map_and_fenceable
);
3505 ret
= i915_gem_object_unbind(obj
);
3511 if (obj
->gtt_space
== NULL
) {
3512 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
3514 ret
= i915_gem_object_bind_to_gtt(obj
, alignment
,
3520 if (!dev_priv
->mm
.aliasing_ppgtt
)
3521 i915_gem_gtt_bind_object(obj
, obj
->cache_level
);
3524 if (!obj
->has_global_gtt_mapping
&& map_and_fenceable
)
3525 i915_gem_gtt_bind_object(obj
, obj
->cache_level
);
3528 obj
->pin_mappable
|= map_and_fenceable
;
3534 i915_gem_object_unpin(struct drm_i915_gem_object
*obj
)
3536 BUG_ON(obj
->pin_count
== 0);
3537 BUG_ON(obj
->gtt_space
== NULL
);
3539 if (--obj
->pin_count
== 0)
3540 obj
->pin_mappable
= false;
3544 i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
3545 struct drm_file
*file
)
3547 struct drm_i915_gem_pin
*args
= data
;
3548 struct drm_i915_gem_object
*obj
;
3551 ret
= i915_mutex_lock_interruptible(dev
);
3555 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3556 if (&obj
->base
== NULL
) {
3561 if (obj
->madv
!= I915_MADV_WILLNEED
) {
3562 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3567 if (obj
->pin_filp
!= NULL
&& obj
->pin_filp
!= file
) {
3568 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3574 if (obj
->user_pin_count
== 0) {
3575 ret
= i915_gem_object_pin(obj
, args
->alignment
, true, false);
3580 obj
->user_pin_count
++;
3581 obj
->pin_filp
= file
;
3583 /* XXX - flush the CPU caches for pinned objects
3584 * as the X server doesn't manage domains yet
3586 i915_gem_object_flush_cpu_write_domain(obj
);
3587 args
->offset
= obj
->gtt_offset
;
3589 drm_gem_object_unreference(&obj
->base
);
3591 mutex_unlock(&dev
->struct_mutex
);
3596 i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
3597 struct drm_file
*file
)
3599 struct drm_i915_gem_pin
*args
= data
;
3600 struct drm_i915_gem_object
*obj
;
3603 ret
= i915_mutex_lock_interruptible(dev
);
3607 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3608 if (&obj
->base
== NULL
) {
3613 if (obj
->pin_filp
!= file
) {
3614 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3619 obj
->user_pin_count
--;
3620 if (obj
->user_pin_count
== 0) {
3621 obj
->pin_filp
= NULL
;
3622 i915_gem_object_unpin(obj
);
3626 drm_gem_object_unreference(&obj
->base
);
3628 mutex_unlock(&dev
->struct_mutex
);
3633 i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
3634 struct drm_file
*file
)
3636 struct drm_i915_gem_busy
*args
= data
;
3637 struct drm_i915_gem_object
*obj
;
3640 ret
= i915_mutex_lock_interruptible(dev
);
3644 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3645 if (&obj
->base
== NULL
) {
3650 /* Count all active objects as busy, even if they are currently not used
3651 * by the gpu. Users of this interface expect objects to eventually
3652 * become non-busy without any further actions, therefore emit any
3653 * necessary flushes here.
3655 ret
= i915_gem_object_flush_active(obj
);
3657 args
->busy
= obj
->active
;
3659 BUILD_BUG_ON(I915_NUM_RINGS
> 16);
3660 args
->busy
|= intel_ring_flag(obj
->ring
) << 16;
3663 drm_gem_object_unreference(&obj
->base
);
3665 mutex_unlock(&dev
->struct_mutex
);
3670 i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
3671 struct drm_file
*file_priv
)
3673 return i915_gem_ring_throttle(dev
, file_priv
);
3677 i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
3678 struct drm_file
*file_priv
)
3680 struct drm_i915_gem_madvise
*args
= data
;
3681 struct drm_i915_gem_object
*obj
;
3684 switch (args
->madv
) {
3685 case I915_MADV_DONTNEED
:
3686 case I915_MADV_WILLNEED
:
3692 ret
= i915_mutex_lock_interruptible(dev
);
3696 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file_priv
, args
->handle
));
3697 if (&obj
->base
== NULL
) {
3702 if (obj
->pin_count
) {
3707 if (obj
->madv
!= __I915_MADV_PURGED
)
3708 obj
->madv
= args
->madv
;
3710 /* if the object is no longer attached, discard its backing storage */
3711 if (i915_gem_object_is_purgeable(obj
) && obj
->pages
== NULL
)
3712 i915_gem_object_truncate(obj
);
3714 args
->retained
= obj
->madv
!= __I915_MADV_PURGED
;
3717 drm_gem_object_unreference(&obj
->base
);
3719 mutex_unlock(&dev
->struct_mutex
);
3723 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
3724 const struct drm_i915_gem_object_ops
*ops
)
3726 INIT_LIST_HEAD(&obj
->mm_list
);
3727 INIT_LIST_HEAD(&obj
->gtt_list
);
3728 INIT_LIST_HEAD(&obj
->ring_list
);
3729 INIT_LIST_HEAD(&obj
->exec_list
);
3733 obj
->fence_reg
= I915_FENCE_REG_NONE
;
3734 obj
->madv
= I915_MADV_WILLNEED
;
3735 /* Avoid an unnecessary call to unbind on the first bind. */
3736 obj
->map_and_fenceable
= true;
3738 i915_gem_info_add_obj(obj
->base
.dev
->dev_private
, obj
->base
.size
);
3741 static const struct drm_i915_gem_object_ops i915_gem_object_ops
= {
3742 .get_pages
= i915_gem_object_get_pages_gtt
,
3743 .put_pages
= i915_gem_object_put_pages_gtt
,
3746 struct drm_i915_gem_object
*i915_gem_alloc_object(struct drm_device
*dev
,
3749 struct drm_i915_gem_object
*obj
;
3750 struct address_space
*mapping
;
3753 obj
= i915_gem_object_alloc(dev
);
3757 if (drm_gem_object_init(dev
, &obj
->base
, size
) != 0) {
3758 i915_gem_object_free(obj
);
3762 mask
= GFP_HIGHUSER
| __GFP_RECLAIMABLE
;
3763 if (IS_CRESTLINE(dev
) || IS_BROADWATER(dev
)) {
3764 /* 965gm cannot relocate objects above 4GiB. */
3765 mask
&= ~__GFP_HIGHMEM
;
3766 mask
|= __GFP_DMA32
;
3769 mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
3770 mapping_set_gfp_mask(mapping
, mask
);
3772 i915_gem_object_init(obj
, &i915_gem_object_ops
);
3774 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
3775 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
3778 /* On some devices, we can have the GPU use the LLC (the CPU
3779 * cache) for about a 10% performance improvement
3780 * compared to uncached. Graphics requests other than
3781 * display scanout are coherent with the CPU in
3782 * accessing this cache. This means in this mode we
3783 * don't need to clflush on the CPU side, and on the
3784 * GPU side we only need to flush internal caches to
3785 * get data visible to the CPU.
3787 * However, we maintain the display planes as UC, and so
3788 * need to rebind when first used as such.
3790 obj
->cache_level
= I915_CACHE_LLC
;
3792 obj
->cache_level
= I915_CACHE_NONE
;
3797 int i915_gem_init_object(struct drm_gem_object
*obj
)
3804 void i915_gem_free_object(struct drm_gem_object
*gem_obj
)
3806 struct drm_i915_gem_object
*obj
= to_intel_bo(gem_obj
);
3807 struct drm_device
*dev
= obj
->base
.dev
;
3808 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3810 trace_i915_gem_object_destroy(obj
);
3813 i915_gem_detach_phys_object(dev
, obj
);
3816 if (WARN_ON(i915_gem_object_unbind(obj
) == -ERESTARTSYS
)) {
3817 bool was_interruptible
;
3819 was_interruptible
= dev_priv
->mm
.interruptible
;
3820 dev_priv
->mm
.interruptible
= false;
3822 WARN_ON(i915_gem_object_unbind(obj
));
3824 dev_priv
->mm
.interruptible
= was_interruptible
;
3827 obj
->pages_pin_count
= 0;
3828 i915_gem_object_put_pages(obj
);
3829 i915_gem_object_free_mmap_offset(obj
);
3830 i915_gem_object_release_stolen(obj
);
3834 if (obj
->base
.import_attach
)
3835 drm_prime_gem_destroy(&obj
->base
, NULL
);
3837 drm_gem_object_release(&obj
->base
);
3838 i915_gem_info_remove_obj(dev_priv
, obj
->base
.size
);
3841 i915_gem_object_free(obj
);
3845 i915_gem_idle(struct drm_device
*dev
)
3847 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3850 mutex_lock(&dev
->struct_mutex
);
3852 if (dev_priv
->mm
.suspended
) {
3853 mutex_unlock(&dev
->struct_mutex
);
3857 ret
= i915_gpu_idle(dev
);
3859 mutex_unlock(&dev
->struct_mutex
);
3862 i915_gem_retire_requests(dev
);
3864 /* Under UMS, be paranoid and evict. */
3865 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
3866 i915_gem_evict_everything(dev
);
3868 i915_gem_reset_fences(dev
);
3870 /* Hack! Don't let anybody do execbuf while we don't control the chip.
3871 * We need to replace this with a semaphore, or something.
3872 * And not confound mm.suspended!
3874 dev_priv
->mm
.suspended
= 1;
3875 del_timer_sync(&dev_priv
->gpu_error
.hangcheck_timer
);
3877 i915_kernel_lost_context(dev
);
3878 i915_gem_cleanup_ringbuffer(dev
);
3880 mutex_unlock(&dev
->struct_mutex
);
3882 /* Cancel the retire work handler, which should be idle now. */
3883 cancel_delayed_work_sync(&dev_priv
->mm
.retire_work
);
3888 void i915_gem_l3_remap(struct drm_device
*dev
)
3890 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3894 if (!HAS_L3_GPU_CACHE(dev
))
3897 if (!dev_priv
->l3_parity
.remap_info
)
3900 misccpctl
= I915_READ(GEN7_MISCCPCTL
);
3901 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
& ~GEN7_DOP_CLOCK_GATE_ENABLE
);
3902 POSTING_READ(GEN7_MISCCPCTL
);
3904 for (i
= 0; i
< GEN7_L3LOG_SIZE
; i
+= 4) {
3905 u32 remap
= I915_READ(GEN7_L3LOG_BASE
+ i
);
3906 if (remap
&& remap
!= dev_priv
->l3_parity
.remap_info
[i
/4])
3907 DRM_DEBUG("0x%x was already programmed to %x\n",
3908 GEN7_L3LOG_BASE
+ i
, remap
);
3909 if (remap
&& !dev_priv
->l3_parity
.remap_info
[i
/4])
3910 DRM_DEBUG_DRIVER("Clearing remapped register\n");
3911 I915_WRITE(GEN7_L3LOG_BASE
+ i
, dev_priv
->l3_parity
.remap_info
[i
/4]);
3914 /* Make sure all the writes land before disabling dop clock gating */
3915 POSTING_READ(GEN7_L3LOG_BASE
);
3917 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
);
3920 void i915_gem_init_swizzling(struct drm_device
*dev
)
3922 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3924 if (INTEL_INFO(dev
)->gen
< 5 ||
3925 dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_NONE
)
3928 I915_WRITE(DISP_ARB_CTL
, I915_READ(DISP_ARB_CTL
) |
3929 DISP_TILE_SURFACE_SWIZZLING
);
3934 I915_WRITE(TILECTL
, I915_READ(TILECTL
) | TILECTL_SWZCTL
);
3936 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB
));
3937 else if (IS_GEN7(dev
))
3938 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB
));
3944 intel_enable_blt(struct drm_device
*dev
)
3949 /* The blitter was dysfunctional on early prototypes */
3950 if (IS_GEN6(dev
) && dev
->pdev
->revision
< 8) {
3951 DRM_INFO("BLT not supported on this pre-production hardware;"
3952 " graphics performance will be degraded.\n");
3959 static int i915_gem_init_rings(struct drm_device
*dev
)
3961 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3964 ret
= intel_init_render_ring_buffer(dev
);
3969 ret
= intel_init_bsd_ring_buffer(dev
);
3971 goto cleanup_render_ring
;
3974 if (intel_enable_blt(dev
)) {
3975 ret
= intel_init_blt_ring_buffer(dev
);
3977 goto cleanup_bsd_ring
;
3980 ret
= i915_gem_set_seqno(dev
, ((u32
)~0 - 0x1000));
3982 goto cleanup_blt_ring
;
3987 intel_cleanup_ring_buffer(&dev_priv
->ring
[BCS
]);
3989 intel_cleanup_ring_buffer(&dev_priv
->ring
[VCS
]);
3990 cleanup_render_ring
:
3991 intel_cleanup_ring_buffer(&dev_priv
->ring
[RCS
]);
3997 i915_gem_init_hw(struct drm_device
*dev
)
3999 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4002 if (INTEL_INFO(dev
)->gen
< 6 && !intel_enable_gtt())
4005 if (IS_HASWELL(dev
) && (I915_READ(0x120010) == 1))
4006 I915_WRITE(0x9008, I915_READ(0x9008) | 0xf0000);
4008 if (HAS_PCH_NOP(dev
)) {
4009 u32 temp
= I915_READ(GEN7_MSG_CTL
);
4010 temp
&= ~(WAIT_FOR_PCH_FLR_ACK
| WAIT_FOR_PCH_RESET_ACK
);
4011 I915_WRITE(GEN7_MSG_CTL
, temp
);
4014 i915_gem_l3_remap(dev
);
4016 i915_gem_init_swizzling(dev
);
4018 ret
= i915_gem_init_rings(dev
);
4023 * XXX: There was some w/a described somewhere suggesting loading
4024 * contexts before PPGTT.
4026 i915_gem_context_init(dev
);
4027 if (dev_priv
->mm
.aliasing_ppgtt
) {
4028 ret
= dev_priv
->mm
.aliasing_ppgtt
->enable(dev
);
4030 i915_gem_cleanup_aliasing_ppgtt(dev
);
4031 DRM_INFO("PPGTT enable failed. This is not fatal, but unexpected\n");
4038 int i915_gem_init(struct drm_device
*dev
)
4040 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4043 mutex_lock(&dev
->struct_mutex
);
4045 if (IS_VALLEYVIEW(dev
)) {
4046 /* VLVA0 (potential hack), BIOS isn't actually waking us */
4047 I915_WRITE(VLV_GTLC_WAKE_CTRL
, 1);
4048 if (wait_for((I915_READ(VLV_GTLC_PW_STATUS
) & 1) == 1, 10))
4049 DRM_DEBUG_DRIVER("allow wake ack timed out\n");
4052 i915_gem_init_global_gtt(dev
);
4054 ret
= i915_gem_init_hw(dev
);
4055 mutex_unlock(&dev
->struct_mutex
);
4057 i915_gem_cleanup_aliasing_ppgtt(dev
);
4061 /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */
4062 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
4063 dev_priv
->dri1
.allow_batchbuffer
= 1;
4068 i915_gem_cleanup_ringbuffer(struct drm_device
*dev
)
4070 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4071 struct intel_ring_buffer
*ring
;
4074 for_each_ring(ring
, dev_priv
, i
)
4075 intel_cleanup_ring_buffer(ring
);
4079 i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
4080 struct drm_file
*file_priv
)
4082 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4085 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4088 if (i915_reset_in_progress(&dev_priv
->gpu_error
)) {
4089 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4090 atomic_set(&dev_priv
->gpu_error
.reset_counter
, 0);
4093 mutex_lock(&dev
->struct_mutex
);
4094 dev_priv
->mm
.suspended
= 0;
4096 ret
= i915_gem_init_hw(dev
);
4098 mutex_unlock(&dev
->struct_mutex
);
4102 BUG_ON(!list_empty(&dev_priv
->mm
.active_list
));
4103 mutex_unlock(&dev
->struct_mutex
);
4105 ret
= drm_irq_install(dev
);
4107 goto cleanup_ringbuffer
;
4112 mutex_lock(&dev
->struct_mutex
);
4113 i915_gem_cleanup_ringbuffer(dev
);
4114 dev_priv
->mm
.suspended
= 1;
4115 mutex_unlock(&dev
->struct_mutex
);
4121 i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
4122 struct drm_file
*file_priv
)
4124 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4127 drm_irq_uninstall(dev
);
4128 return i915_gem_idle(dev
);
4132 i915_gem_lastclose(struct drm_device
*dev
)
4136 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4139 ret
= i915_gem_idle(dev
);
4141 DRM_ERROR("failed to idle hardware: %d\n", ret
);
4145 init_ring_lists(struct intel_ring_buffer
*ring
)
4147 INIT_LIST_HEAD(&ring
->active_list
);
4148 INIT_LIST_HEAD(&ring
->request_list
);
4152 i915_gem_load(struct drm_device
*dev
)
4154 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4158 kmem_cache_create("i915_gem_object",
4159 sizeof(struct drm_i915_gem_object
), 0,
4163 INIT_LIST_HEAD(&dev_priv
->mm
.active_list
);
4164 INIT_LIST_HEAD(&dev_priv
->mm
.inactive_list
);
4165 INIT_LIST_HEAD(&dev_priv
->mm
.unbound_list
);
4166 INIT_LIST_HEAD(&dev_priv
->mm
.bound_list
);
4167 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
4168 for (i
= 0; i
< I915_NUM_RINGS
; i
++)
4169 init_ring_lists(&dev_priv
->ring
[i
]);
4170 for (i
= 0; i
< I915_MAX_NUM_FENCES
; i
++)
4171 INIT_LIST_HEAD(&dev_priv
->fence_regs
[i
].lru_list
);
4172 INIT_DELAYED_WORK(&dev_priv
->mm
.retire_work
,
4173 i915_gem_retire_work_handler
);
4174 init_waitqueue_head(&dev_priv
->gpu_error
.reset_queue
);
4176 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4178 I915_WRITE(MI_ARB_STATE
,
4179 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE
));
4182 dev_priv
->relative_constants_mode
= I915_EXEC_CONSTANTS_REL_GENERAL
;
4184 /* Old X drivers will take 0-2 for front, back, depth buffers */
4185 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
4186 dev_priv
->fence_reg_start
= 3;
4188 if (INTEL_INFO(dev
)->gen
>= 7 && !IS_VALLEYVIEW(dev
))
4189 dev_priv
->num_fence_regs
= 32;
4190 else if (INTEL_INFO(dev
)->gen
>= 4 || IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
4191 dev_priv
->num_fence_regs
= 16;
4193 dev_priv
->num_fence_regs
= 8;
4195 /* Initialize fence registers to zero */
4196 i915_gem_reset_fences(dev
);
4198 i915_gem_detect_bit_6_swizzle(dev
);
4199 init_waitqueue_head(&dev_priv
->pending_flip_queue
);
4201 dev_priv
->mm
.interruptible
= true;
4203 dev_priv
->mm
.inactive_shrinker
.shrink
= i915_gem_inactive_shrink
;
4204 dev_priv
->mm
.inactive_shrinker
.seeks
= DEFAULT_SEEKS
;
4205 register_shrinker(&dev_priv
->mm
.inactive_shrinker
);
4209 * Create a physically contiguous memory object for this object
4210 * e.g. for cursor + overlay regs
4212 static int i915_gem_init_phys_object(struct drm_device
*dev
,
4213 int id
, int size
, int align
)
4215 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4216 struct drm_i915_gem_phys_object
*phys_obj
;
4219 if (dev_priv
->mm
.phys_objs
[id
- 1] || !size
)
4222 phys_obj
= kzalloc(sizeof(struct drm_i915_gem_phys_object
), GFP_KERNEL
);
4228 phys_obj
->handle
= drm_pci_alloc(dev
, size
, align
);
4229 if (!phys_obj
->handle
) {
4234 set_memory_wc((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
4237 dev_priv
->mm
.phys_objs
[id
- 1] = phys_obj
;
4245 static void i915_gem_free_phys_object(struct drm_device
*dev
, int id
)
4247 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4248 struct drm_i915_gem_phys_object
*phys_obj
;
4250 if (!dev_priv
->mm
.phys_objs
[id
- 1])
4253 phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
4254 if (phys_obj
->cur_obj
) {
4255 i915_gem_detach_phys_object(dev
, phys_obj
->cur_obj
);
4259 set_memory_wb((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
4261 drm_pci_free(dev
, phys_obj
->handle
);
4263 dev_priv
->mm
.phys_objs
[id
- 1] = NULL
;
4266 void i915_gem_free_all_phys_object(struct drm_device
*dev
)
4270 for (i
= I915_GEM_PHYS_CURSOR_0
; i
<= I915_MAX_PHYS_OBJECT
; i
++)
4271 i915_gem_free_phys_object(dev
, i
);
4274 void i915_gem_detach_phys_object(struct drm_device
*dev
,
4275 struct drm_i915_gem_object
*obj
)
4277 struct address_space
*mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
4284 vaddr
= obj
->phys_obj
->handle
->vaddr
;
4286 page_count
= obj
->base
.size
/ PAGE_SIZE
;
4287 for (i
= 0; i
< page_count
; i
++) {
4288 struct page
*page
= shmem_read_mapping_page(mapping
, i
);
4289 if (!IS_ERR(page
)) {
4290 char *dst
= kmap_atomic(page
);
4291 memcpy(dst
, vaddr
+ i
*PAGE_SIZE
, PAGE_SIZE
);
4294 drm_clflush_pages(&page
, 1);
4296 set_page_dirty(page
);
4297 mark_page_accessed(page
);
4298 page_cache_release(page
);
4301 i915_gem_chipset_flush(dev
);
4303 obj
->phys_obj
->cur_obj
= NULL
;
4304 obj
->phys_obj
= NULL
;
4308 i915_gem_attach_phys_object(struct drm_device
*dev
,
4309 struct drm_i915_gem_object
*obj
,
4313 struct address_space
*mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
4314 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4319 if (id
> I915_MAX_PHYS_OBJECT
)
4322 if (obj
->phys_obj
) {
4323 if (obj
->phys_obj
->id
== id
)
4325 i915_gem_detach_phys_object(dev
, obj
);
4328 /* create a new object */
4329 if (!dev_priv
->mm
.phys_objs
[id
- 1]) {
4330 ret
= i915_gem_init_phys_object(dev
, id
,
4331 obj
->base
.size
, align
);
4333 DRM_ERROR("failed to init phys object %d size: %zu\n",
4334 id
, obj
->base
.size
);
4339 /* bind to the object */
4340 obj
->phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
4341 obj
->phys_obj
->cur_obj
= obj
;
4343 page_count
= obj
->base
.size
/ PAGE_SIZE
;
4345 for (i
= 0; i
< page_count
; i
++) {
4349 page
= shmem_read_mapping_page(mapping
, i
);
4351 return PTR_ERR(page
);
4353 src
= kmap_atomic(page
);
4354 dst
= obj
->phys_obj
->handle
->vaddr
+ (i
* PAGE_SIZE
);
4355 memcpy(dst
, src
, PAGE_SIZE
);
4358 mark_page_accessed(page
);
4359 page_cache_release(page
);
4366 i915_gem_phys_pwrite(struct drm_device
*dev
,
4367 struct drm_i915_gem_object
*obj
,
4368 struct drm_i915_gem_pwrite
*args
,
4369 struct drm_file
*file_priv
)
4371 void *vaddr
= obj
->phys_obj
->handle
->vaddr
+ args
->offset
;
4372 char __user
*user_data
= to_user_ptr(args
->data_ptr
);
4374 if (__copy_from_user_inatomic_nocache(vaddr
, user_data
, args
->size
)) {
4375 unsigned long unwritten
;
4377 /* The physical object once assigned is fixed for the lifetime
4378 * of the obj, so we can safely drop the lock and continue
4381 mutex_unlock(&dev
->struct_mutex
);
4382 unwritten
= copy_from_user(vaddr
, user_data
, args
->size
);
4383 mutex_lock(&dev
->struct_mutex
);
4388 i915_gem_chipset_flush(dev
);
4392 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
)
4394 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
4396 /* Clean up our request list when the client is going away, so that
4397 * later retire_requests won't dereference our soon-to-be-gone
4400 spin_lock(&file_priv
->mm
.lock
);
4401 while (!list_empty(&file_priv
->mm
.request_list
)) {
4402 struct drm_i915_gem_request
*request
;
4404 request
= list_first_entry(&file_priv
->mm
.request_list
,
4405 struct drm_i915_gem_request
,
4407 list_del(&request
->client_list
);
4408 request
->file_priv
= NULL
;
4410 spin_unlock(&file_priv
->mm
.lock
);
4413 static bool mutex_is_locked_by(struct mutex
*mutex
, struct task_struct
*task
)
4415 if (!mutex_is_locked(mutex
))
4418 #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES)
4419 return mutex
->owner
== task
;
4421 /* Since UP may be pre-empted, we cannot assume that we own the lock */
4427 i915_gem_inactive_shrink(struct shrinker
*shrinker
, struct shrink_control
*sc
)
4429 struct drm_i915_private
*dev_priv
=
4430 container_of(shrinker
,
4431 struct drm_i915_private
,
4432 mm
.inactive_shrinker
);
4433 struct drm_device
*dev
= dev_priv
->dev
;
4434 struct drm_i915_gem_object
*obj
;
4435 int nr_to_scan
= sc
->nr_to_scan
;
4439 if (!mutex_trylock(&dev
->struct_mutex
)) {
4440 if (!mutex_is_locked_by(&dev
->struct_mutex
, current
))
4443 if (dev_priv
->mm
.shrinker_no_lock_stealing
)
4450 nr_to_scan
-= i915_gem_purge(dev_priv
, nr_to_scan
);
4452 nr_to_scan
-= __i915_gem_shrink(dev_priv
, nr_to_scan
,
4455 i915_gem_shrink_all(dev_priv
);
4459 list_for_each_entry(obj
, &dev_priv
->mm
.unbound_list
, gtt_list
)
4460 if (obj
->pages_pin_count
== 0)
4461 cnt
+= obj
->base
.size
>> PAGE_SHIFT
;
4462 list_for_each_entry(obj
, &dev_priv
->mm
.inactive_list
, gtt_list
)
4463 if (obj
->pin_count
== 0 && obj
->pages_pin_count
== 0)
4464 cnt
+= obj
->base
.size
>> PAGE_SHIFT
;
4467 mutex_unlock(&dev
->struct_mutex
);