2 * Copyright © 2008-2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/drm_vma_manager.h>
30 #include <drm/i915_drm.h>
32 #include "i915_vgpu.h"
33 #include "i915_trace.h"
34 #include "intel_drv.h"
35 #include <linux/shmem_fs.h>
36 #include <linux/slab.h>
37 #include <linux/swap.h>
38 #include <linux/pci.h>
39 #include <linux/dma-buf.h>
41 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
);
42 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
);
43 static __must_check
int
44 i915_gem_object_wait_rendering(struct drm_i915_gem_object
*obj
,
47 i915_gem_object_retire(struct drm_i915_gem_object
*obj
);
49 static void i915_gem_write_fence(struct drm_device
*dev
, int reg
,
50 struct drm_i915_gem_object
*obj
);
51 static void i915_gem_object_update_fence(struct drm_i915_gem_object
*obj
,
52 struct drm_i915_fence_reg
*fence
,
55 static bool cpu_cache_is_coherent(struct drm_device
*dev
,
56 enum i915_cache_level level
)
58 return HAS_LLC(dev
) || level
!= I915_CACHE_NONE
;
61 static bool cpu_write_needs_clflush(struct drm_i915_gem_object
*obj
)
63 if (!cpu_cache_is_coherent(obj
->base
.dev
, obj
->cache_level
))
66 return obj
->pin_display
;
69 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object
*obj
)
72 i915_gem_release_mmap(obj
);
74 /* As we do not have an associated fence register, we will force
75 * a tiling change if we ever need to acquire one.
77 obj
->fence_dirty
= false;
78 obj
->fence_reg
= I915_FENCE_REG_NONE
;
81 /* some bookkeeping */
82 static void i915_gem_info_add_obj(struct drm_i915_private
*dev_priv
,
85 spin_lock(&dev_priv
->mm
.object_stat_lock
);
86 dev_priv
->mm
.object_count
++;
87 dev_priv
->mm
.object_memory
+= size
;
88 spin_unlock(&dev_priv
->mm
.object_stat_lock
);
91 static void i915_gem_info_remove_obj(struct drm_i915_private
*dev_priv
,
94 spin_lock(&dev_priv
->mm
.object_stat_lock
);
95 dev_priv
->mm
.object_count
--;
96 dev_priv
->mm
.object_memory
-= size
;
97 spin_unlock(&dev_priv
->mm
.object_stat_lock
);
101 i915_gem_wait_for_error(struct i915_gpu_error
*error
)
105 #define EXIT_COND (!i915_reset_in_progress(error) || \
106 i915_terminally_wedged(error))
111 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
112 * userspace. If it takes that long something really bad is going on and
113 * we should simply try to bail out and fail as gracefully as possible.
115 ret
= wait_event_interruptible_timeout(error
->reset_queue
,
119 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
121 } else if (ret
< 0) {
129 int i915_mutex_lock_interruptible(struct drm_device
*dev
)
131 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
134 ret
= i915_gem_wait_for_error(&dev_priv
->gpu_error
);
138 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
142 WARN_ON(i915_verify_lists(dev
));
147 i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
148 struct drm_file
*file
)
150 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
151 struct drm_i915_gem_get_aperture
*args
= data
;
152 struct drm_i915_gem_object
*obj
;
156 mutex_lock(&dev
->struct_mutex
);
157 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
)
158 if (i915_gem_obj_is_pinned(obj
))
159 pinned
+= i915_gem_obj_ggtt_size(obj
);
160 mutex_unlock(&dev
->struct_mutex
);
162 args
->aper_size
= dev_priv
->gtt
.base
.total
;
163 args
->aper_available_size
= args
->aper_size
- pinned
;
169 i915_gem_object_get_pages_phys(struct drm_i915_gem_object
*obj
)
171 struct address_space
*mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
172 char *vaddr
= obj
->phys_handle
->vaddr
;
174 struct scatterlist
*sg
;
177 if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj
)))
180 for (i
= 0; i
< obj
->base
.size
/ PAGE_SIZE
; i
++) {
184 page
= shmem_read_mapping_page(mapping
, i
);
186 return PTR_ERR(page
);
188 src
= kmap_atomic(page
);
189 memcpy(vaddr
, src
, PAGE_SIZE
);
190 drm_clflush_virt_range(vaddr
, PAGE_SIZE
);
193 page_cache_release(page
);
197 i915_gem_chipset_flush(obj
->base
.dev
);
199 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
203 if (sg_alloc_table(st
, 1, GFP_KERNEL
)) {
210 sg
->length
= obj
->base
.size
;
212 sg_dma_address(sg
) = obj
->phys_handle
->busaddr
;
213 sg_dma_len(sg
) = obj
->base
.size
;
216 obj
->has_dma_mapping
= true;
221 i915_gem_object_put_pages_phys(struct drm_i915_gem_object
*obj
)
225 BUG_ON(obj
->madv
== __I915_MADV_PURGED
);
227 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
229 /* In the event of a disaster, abandon all caches and
232 WARN_ON(ret
!= -EIO
);
233 obj
->base
.read_domains
= obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
236 if (obj
->madv
== I915_MADV_DONTNEED
)
240 struct address_space
*mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
241 char *vaddr
= obj
->phys_handle
->vaddr
;
244 for (i
= 0; i
< obj
->base
.size
/ PAGE_SIZE
; i
++) {
248 page
= shmem_read_mapping_page(mapping
, i
);
252 dst
= kmap_atomic(page
);
253 drm_clflush_virt_range(vaddr
, PAGE_SIZE
);
254 memcpy(dst
, vaddr
, PAGE_SIZE
);
257 set_page_dirty(page
);
258 if (obj
->madv
== I915_MADV_WILLNEED
)
259 mark_page_accessed(page
);
260 page_cache_release(page
);
266 sg_free_table(obj
->pages
);
269 obj
->has_dma_mapping
= false;
273 i915_gem_object_release_phys(struct drm_i915_gem_object
*obj
)
275 drm_pci_free(obj
->base
.dev
, obj
->phys_handle
);
278 static const struct drm_i915_gem_object_ops i915_gem_phys_ops
= {
279 .get_pages
= i915_gem_object_get_pages_phys
,
280 .put_pages
= i915_gem_object_put_pages_phys
,
281 .release
= i915_gem_object_release_phys
,
285 drop_pages(struct drm_i915_gem_object
*obj
)
287 struct i915_vma
*vma
, *next
;
290 drm_gem_object_reference(&obj
->base
);
291 list_for_each_entry_safe(vma
, next
, &obj
->vma_list
, vma_link
)
292 if (i915_vma_unbind(vma
))
295 ret
= i915_gem_object_put_pages(obj
);
296 drm_gem_object_unreference(&obj
->base
);
302 i915_gem_object_attach_phys(struct drm_i915_gem_object
*obj
,
305 drm_dma_handle_t
*phys
;
308 if (obj
->phys_handle
) {
309 if ((unsigned long)obj
->phys_handle
->vaddr
& (align
-1))
315 if (obj
->madv
!= I915_MADV_WILLNEED
)
318 if (obj
->base
.filp
== NULL
)
321 ret
= drop_pages(obj
);
325 /* create a new object */
326 phys
= drm_pci_alloc(obj
->base
.dev
, obj
->base
.size
, align
);
330 obj
->phys_handle
= phys
;
331 obj
->ops
= &i915_gem_phys_ops
;
333 return i915_gem_object_get_pages(obj
);
337 i915_gem_phys_pwrite(struct drm_i915_gem_object
*obj
,
338 struct drm_i915_gem_pwrite
*args
,
339 struct drm_file
*file_priv
)
341 struct drm_device
*dev
= obj
->base
.dev
;
342 void *vaddr
= obj
->phys_handle
->vaddr
+ args
->offset
;
343 char __user
*user_data
= to_user_ptr(args
->data_ptr
);
346 /* We manually control the domain here and pretend that it
347 * remains coherent i.e. in the GTT domain, like shmem_pwrite.
349 ret
= i915_gem_object_wait_rendering(obj
, false);
353 intel_fb_obj_invalidate(obj
, NULL
, ORIGIN_CPU
);
354 if (__copy_from_user_inatomic_nocache(vaddr
, user_data
, args
->size
)) {
355 unsigned long unwritten
;
357 /* The physical object once assigned is fixed for the lifetime
358 * of the obj, so we can safely drop the lock and continue
361 mutex_unlock(&dev
->struct_mutex
);
362 unwritten
= copy_from_user(vaddr
, user_data
, args
->size
);
363 mutex_lock(&dev
->struct_mutex
);
370 drm_clflush_virt_range(vaddr
, args
->size
);
371 i915_gem_chipset_flush(dev
);
374 intel_fb_obj_flush(obj
, false);
378 void *i915_gem_object_alloc(struct drm_device
*dev
)
380 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
381 return kmem_cache_zalloc(dev_priv
->slab
, GFP_KERNEL
);
384 void i915_gem_object_free(struct drm_i915_gem_object
*obj
)
386 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
387 kmem_cache_free(dev_priv
->slab
, obj
);
391 i915_gem_create(struct drm_file
*file
,
392 struct drm_device
*dev
,
396 struct drm_i915_gem_object
*obj
;
400 size
= roundup(size
, PAGE_SIZE
);
404 /* Allocate the new object */
405 obj
= i915_gem_alloc_object(dev
, size
);
409 ret
= drm_gem_handle_create(file
, &obj
->base
, &handle
);
410 /* drop reference from allocate - handle holds it now */
411 drm_gem_object_unreference_unlocked(&obj
->base
);
420 i915_gem_dumb_create(struct drm_file
*file
,
421 struct drm_device
*dev
,
422 struct drm_mode_create_dumb
*args
)
424 /* have to work out size/pitch and return them */
425 args
->pitch
= ALIGN(args
->width
* DIV_ROUND_UP(args
->bpp
, 8), 64);
426 args
->size
= args
->pitch
* args
->height
;
427 return i915_gem_create(file
, dev
,
428 args
->size
, &args
->handle
);
432 * Creates a new mm object and returns a handle to it.
435 i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
436 struct drm_file
*file
)
438 struct drm_i915_gem_create
*args
= data
;
440 return i915_gem_create(file
, dev
,
441 args
->size
, &args
->handle
);
445 __copy_to_user_swizzled(char __user
*cpu_vaddr
,
446 const char *gpu_vaddr
, int gpu_offset
,
449 int ret
, cpu_offset
= 0;
452 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
453 int this_length
= min(cacheline_end
- gpu_offset
, length
);
454 int swizzled_gpu_offset
= gpu_offset
^ 64;
456 ret
= __copy_to_user(cpu_vaddr
+ cpu_offset
,
457 gpu_vaddr
+ swizzled_gpu_offset
,
462 cpu_offset
+= this_length
;
463 gpu_offset
+= this_length
;
464 length
-= this_length
;
471 __copy_from_user_swizzled(char *gpu_vaddr
, int gpu_offset
,
472 const char __user
*cpu_vaddr
,
475 int ret
, cpu_offset
= 0;
478 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
479 int this_length
= min(cacheline_end
- gpu_offset
, length
);
480 int swizzled_gpu_offset
= gpu_offset
^ 64;
482 ret
= __copy_from_user(gpu_vaddr
+ swizzled_gpu_offset
,
483 cpu_vaddr
+ cpu_offset
,
488 cpu_offset
+= this_length
;
489 gpu_offset
+= this_length
;
490 length
-= this_length
;
497 * Pins the specified object's pages and synchronizes the object with
498 * GPU accesses. Sets needs_clflush to non-zero if the caller should
499 * flush the object from the CPU cache.
501 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object
*obj
,
511 if (!(obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
)) {
512 /* If we're not in the cpu read domain, set ourself into the gtt
513 * read domain and manually flush cachelines (if required). This
514 * optimizes for the case when the gpu will dirty the data
515 * anyway again before the next pread happens. */
516 *needs_clflush
= !cpu_cache_is_coherent(obj
->base
.dev
,
518 ret
= i915_gem_object_wait_rendering(obj
, true);
522 i915_gem_object_retire(obj
);
525 ret
= i915_gem_object_get_pages(obj
);
529 i915_gem_object_pin_pages(obj
);
534 /* Per-page copy function for the shmem pread fastpath.
535 * Flushes invalid cachelines before reading the target if
536 * needs_clflush is set. */
538 shmem_pread_fast(struct page
*page
, int shmem_page_offset
, int page_length
,
539 char __user
*user_data
,
540 bool page_do_bit17_swizzling
, bool needs_clflush
)
545 if (unlikely(page_do_bit17_swizzling
))
548 vaddr
= kmap_atomic(page
);
550 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
552 ret
= __copy_to_user_inatomic(user_data
,
553 vaddr
+ shmem_page_offset
,
555 kunmap_atomic(vaddr
);
557 return ret
? -EFAULT
: 0;
561 shmem_clflush_swizzled_range(char *addr
, unsigned long length
,
564 if (unlikely(swizzled
)) {
565 unsigned long start
= (unsigned long) addr
;
566 unsigned long end
= (unsigned long) addr
+ length
;
568 /* For swizzling simply ensure that we always flush both
569 * channels. Lame, but simple and it works. Swizzled
570 * pwrite/pread is far from a hotpath - current userspace
571 * doesn't use it at all. */
572 start
= round_down(start
, 128);
573 end
= round_up(end
, 128);
575 drm_clflush_virt_range((void *)start
, end
- start
);
577 drm_clflush_virt_range(addr
, length
);
582 /* Only difference to the fast-path function is that this can handle bit17
583 * and uses non-atomic copy and kmap functions. */
585 shmem_pread_slow(struct page
*page
, int shmem_page_offset
, int page_length
,
586 char __user
*user_data
,
587 bool page_do_bit17_swizzling
, bool needs_clflush
)
594 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
596 page_do_bit17_swizzling
);
598 if (page_do_bit17_swizzling
)
599 ret
= __copy_to_user_swizzled(user_data
,
600 vaddr
, shmem_page_offset
,
603 ret
= __copy_to_user(user_data
,
604 vaddr
+ shmem_page_offset
,
608 return ret
? - EFAULT
: 0;
612 i915_gem_shmem_pread(struct drm_device
*dev
,
613 struct drm_i915_gem_object
*obj
,
614 struct drm_i915_gem_pread
*args
,
615 struct drm_file
*file
)
617 char __user
*user_data
;
620 int shmem_page_offset
, page_length
, ret
= 0;
621 int obj_do_bit17_swizzling
, page_do_bit17_swizzling
;
623 int needs_clflush
= 0;
624 struct sg_page_iter sg_iter
;
626 user_data
= to_user_ptr(args
->data_ptr
);
629 obj_do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
631 ret
= i915_gem_obj_prepare_shmem_read(obj
, &needs_clflush
);
635 offset
= args
->offset
;
637 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
,
638 offset
>> PAGE_SHIFT
) {
639 struct page
*page
= sg_page_iter_page(&sg_iter
);
644 /* Operation in this page
646 * shmem_page_offset = offset within page in shmem file
647 * page_length = bytes to copy for this page
649 shmem_page_offset
= offset_in_page(offset
);
650 page_length
= remain
;
651 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
652 page_length
= PAGE_SIZE
- shmem_page_offset
;
654 page_do_bit17_swizzling
= obj_do_bit17_swizzling
&&
655 (page_to_phys(page
) & (1 << 17)) != 0;
657 ret
= shmem_pread_fast(page
, shmem_page_offset
, page_length
,
658 user_data
, page_do_bit17_swizzling
,
663 mutex_unlock(&dev
->struct_mutex
);
665 if (likely(!i915
.prefault_disable
) && !prefaulted
) {
666 ret
= fault_in_multipages_writeable(user_data
, remain
);
667 /* Userspace is tricking us, but we've already clobbered
668 * its pages with the prefault and promised to write the
669 * data up to the first fault. Hence ignore any errors
670 * and just continue. */
675 ret
= shmem_pread_slow(page
, shmem_page_offset
, page_length
,
676 user_data
, page_do_bit17_swizzling
,
679 mutex_lock(&dev
->struct_mutex
);
685 remain
-= page_length
;
686 user_data
+= page_length
;
687 offset
+= page_length
;
691 i915_gem_object_unpin_pages(obj
);
697 * Reads data from the object referenced by handle.
699 * On error, the contents of *data are undefined.
702 i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
703 struct drm_file
*file
)
705 struct drm_i915_gem_pread
*args
= data
;
706 struct drm_i915_gem_object
*obj
;
712 if (!access_ok(VERIFY_WRITE
,
713 to_user_ptr(args
->data_ptr
),
717 ret
= i915_mutex_lock_interruptible(dev
);
721 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
722 if (&obj
->base
== NULL
) {
727 /* Bounds check source. */
728 if (args
->offset
> obj
->base
.size
||
729 args
->size
> obj
->base
.size
- args
->offset
) {
734 /* prime objects have no backing filp to GEM pread/pwrite
737 if (!obj
->base
.filp
) {
742 trace_i915_gem_object_pread(obj
, args
->offset
, args
->size
);
744 ret
= i915_gem_shmem_pread(dev
, obj
, args
, file
);
747 drm_gem_object_unreference(&obj
->base
);
749 mutex_unlock(&dev
->struct_mutex
);
753 /* This is the fast write path which cannot handle
754 * page faults in the source data
758 fast_user_write(struct io_mapping
*mapping
,
759 loff_t page_base
, int page_offset
,
760 char __user
*user_data
,
763 void __iomem
*vaddr_atomic
;
765 unsigned long unwritten
;
767 vaddr_atomic
= io_mapping_map_atomic_wc(mapping
, page_base
);
768 /* We can use the cpu mem copy function because this is X86. */
769 vaddr
= (void __force
*)vaddr_atomic
+ page_offset
;
770 unwritten
= __copy_from_user_inatomic_nocache(vaddr
,
772 io_mapping_unmap_atomic(vaddr_atomic
);
777 * This is the fast pwrite path, where we copy the data directly from the
778 * user into the GTT, uncached.
781 i915_gem_gtt_pwrite_fast(struct drm_device
*dev
,
782 struct drm_i915_gem_object
*obj
,
783 struct drm_i915_gem_pwrite
*args
,
784 struct drm_file
*file
)
786 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
788 loff_t offset
, page_base
;
789 char __user
*user_data
;
790 int page_offset
, page_length
, ret
;
792 ret
= i915_gem_obj_ggtt_pin(obj
, 0, PIN_MAPPABLE
| PIN_NONBLOCK
);
796 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
800 ret
= i915_gem_object_put_fence(obj
);
804 user_data
= to_user_ptr(args
->data_ptr
);
807 offset
= i915_gem_obj_ggtt_offset(obj
) + args
->offset
;
809 intel_fb_obj_invalidate(obj
, NULL
, ORIGIN_GTT
);
812 /* Operation in this page
814 * page_base = page offset within aperture
815 * page_offset = offset within page
816 * page_length = bytes to copy for this page
818 page_base
= offset
& PAGE_MASK
;
819 page_offset
= offset_in_page(offset
);
820 page_length
= remain
;
821 if ((page_offset
+ remain
) > PAGE_SIZE
)
822 page_length
= PAGE_SIZE
- page_offset
;
824 /* If we get a fault while copying data, then (presumably) our
825 * source page isn't available. Return the error and we'll
826 * retry in the slow path.
828 if (fast_user_write(dev_priv
->gtt
.mappable
, page_base
,
829 page_offset
, user_data
, page_length
)) {
834 remain
-= page_length
;
835 user_data
+= page_length
;
836 offset
+= page_length
;
840 intel_fb_obj_flush(obj
, false);
842 i915_gem_object_ggtt_unpin(obj
);
847 /* Per-page copy function for the shmem pwrite fastpath.
848 * Flushes invalid cachelines before writing to the target if
849 * needs_clflush_before is set and flushes out any written cachelines after
850 * writing if needs_clflush is set. */
852 shmem_pwrite_fast(struct page
*page
, int shmem_page_offset
, int page_length
,
853 char __user
*user_data
,
854 bool page_do_bit17_swizzling
,
855 bool needs_clflush_before
,
856 bool needs_clflush_after
)
861 if (unlikely(page_do_bit17_swizzling
))
864 vaddr
= kmap_atomic(page
);
865 if (needs_clflush_before
)
866 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
868 ret
= __copy_from_user_inatomic(vaddr
+ shmem_page_offset
,
869 user_data
, page_length
);
870 if (needs_clflush_after
)
871 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
873 kunmap_atomic(vaddr
);
875 return ret
? -EFAULT
: 0;
878 /* Only difference to the fast-path function is that this can handle bit17
879 * and uses non-atomic copy and kmap functions. */
881 shmem_pwrite_slow(struct page
*page
, int shmem_page_offset
, int page_length
,
882 char __user
*user_data
,
883 bool page_do_bit17_swizzling
,
884 bool needs_clflush_before
,
885 bool needs_clflush_after
)
891 if (unlikely(needs_clflush_before
|| page_do_bit17_swizzling
))
892 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
894 page_do_bit17_swizzling
);
895 if (page_do_bit17_swizzling
)
896 ret
= __copy_from_user_swizzled(vaddr
, shmem_page_offset
,
900 ret
= __copy_from_user(vaddr
+ shmem_page_offset
,
903 if (needs_clflush_after
)
904 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
906 page_do_bit17_swizzling
);
909 return ret
? -EFAULT
: 0;
913 i915_gem_shmem_pwrite(struct drm_device
*dev
,
914 struct drm_i915_gem_object
*obj
,
915 struct drm_i915_gem_pwrite
*args
,
916 struct drm_file
*file
)
920 char __user
*user_data
;
921 int shmem_page_offset
, page_length
, ret
= 0;
922 int obj_do_bit17_swizzling
, page_do_bit17_swizzling
;
923 int hit_slowpath
= 0;
924 int needs_clflush_after
= 0;
925 int needs_clflush_before
= 0;
926 struct sg_page_iter sg_iter
;
928 user_data
= to_user_ptr(args
->data_ptr
);
931 obj_do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
933 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
934 /* If we're not in the cpu write domain, set ourself into the gtt
935 * write domain and manually flush cachelines (if required). This
936 * optimizes for the case when the gpu will use the data
937 * right away and we therefore have to clflush anyway. */
938 needs_clflush_after
= cpu_write_needs_clflush(obj
);
939 ret
= i915_gem_object_wait_rendering(obj
, false);
943 i915_gem_object_retire(obj
);
945 /* Same trick applies to invalidate partially written cachelines read
947 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) == 0)
948 needs_clflush_before
=
949 !cpu_cache_is_coherent(dev
, obj
->cache_level
);
951 ret
= i915_gem_object_get_pages(obj
);
955 intel_fb_obj_invalidate(obj
, NULL
, ORIGIN_CPU
);
957 i915_gem_object_pin_pages(obj
);
959 offset
= args
->offset
;
962 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
,
963 offset
>> PAGE_SHIFT
) {
964 struct page
*page
= sg_page_iter_page(&sg_iter
);
965 int partial_cacheline_write
;
970 /* Operation in this page
972 * shmem_page_offset = offset within page in shmem file
973 * page_length = bytes to copy for this page
975 shmem_page_offset
= offset_in_page(offset
);
977 page_length
= remain
;
978 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
979 page_length
= PAGE_SIZE
- shmem_page_offset
;
981 /* If we don't overwrite a cacheline completely we need to be
982 * careful to have up-to-date data by first clflushing. Don't
983 * overcomplicate things and flush the entire patch. */
984 partial_cacheline_write
= needs_clflush_before
&&
985 ((shmem_page_offset
| page_length
)
986 & (boot_cpu_data
.x86_clflush_size
- 1));
988 page_do_bit17_swizzling
= obj_do_bit17_swizzling
&&
989 (page_to_phys(page
) & (1 << 17)) != 0;
991 ret
= shmem_pwrite_fast(page
, shmem_page_offset
, page_length
,
992 user_data
, page_do_bit17_swizzling
,
993 partial_cacheline_write
,
994 needs_clflush_after
);
999 mutex_unlock(&dev
->struct_mutex
);
1000 ret
= shmem_pwrite_slow(page
, shmem_page_offset
, page_length
,
1001 user_data
, page_do_bit17_swizzling
,
1002 partial_cacheline_write
,
1003 needs_clflush_after
);
1005 mutex_lock(&dev
->struct_mutex
);
1011 remain
-= page_length
;
1012 user_data
+= page_length
;
1013 offset
+= page_length
;
1017 i915_gem_object_unpin_pages(obj
);
1021 * Fixup: Flush cpu caches in case we didn't flush the dirty
1022 * cachelines in-line while writing and the object moved
1023 * out of the cpu write domain while we've dropped the lock.
1025 if (!needs_clflush_after
&&
1026 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
1027 if (i915_gem_clflush_object(obj
, obj
->pin_display
))
1028 i915_gem_chipset_flush(dev
);
1032 if (needs_clflush_after
)
1033 i915_gem_chipset_flush(dev
);
1035 intel_fb_obj_flush(obj
, false);
1040 * Writes data to the object referenced by handle.
1042 * On error, the contents of the buffer that were to be modified are undefined.
1045 i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
1046 struct drm_file
*file
)
1048 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1049 struct drm_i915_gem_pwrite
*args
= data
;
1050 struct drm_i915_gem_object
*obj
;
1053 if (args
->size
== 0)
1056 if (!access_ok(VERIFY_READ
,
1057 to_user_ptr(args
->data_ptr
),
1061 if (likely(!i915
.prefault_disable
)) {
1062 ret
= fault_in_multipages_readable(to_user_ptr(args
->data_ptr
),
1068 intel_runtime_pm_get(dev_priv
);
1070 ret
= i915_mutex_lock_interruptible(dev
);
1074 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1075 if (&obj
->base
== NULL
) {
1080 /* Bounds check destination. */
1081 if (args
->offset
> obj
->base
.size
||
1082 args
->size
> obj
->base
.size
- args
->offset
) {
1087 /* prime objects have no backing filp to GEM pread/pwrite
1090 if (!obj
->base
.filp
) {
1095 trace_i915_gem_object_pwrite(obj
, args
->offset
, args
->size
);
1098 /* We can only do the GTT pwrite on untiled buffers, as otherwise
1099 * it would end up going through the fenced access, and we'll get
1100 * different detiling behavior between reading and writing.
1101 * pread/pwrite currently are reading and writing from the CPU
1102 * perspective, requiring manual detiling by the client.
1104 if (obj
->tiling_mode
== I915_TILING_NONE
&&
1105 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
&&
1106 cpu_write_needs_clflush(obj
)) {
1107 ret
= i915_gem_gtt_pwrite_fast(dev
, obj
, args
, file
);
1108 /* Note that the gtt paths might fail with non-page-backed user
1109 * pointers (e.g. gtt mappings when moving data between
1110 * textures). Fallback to the shmem path in that case. */
1113 if (ret
== -EFAULT
|| ret
== -ENOSPC
) {
1114 if (obj
->phys_handle
)
1115 ret
= i915_gem_phys_pwrite(obj
, args
, file
);
1117 ret
= i915_gem_shmem_pwrite(dev
, obj
, args
, file
);
1121 drm_gem_object_unreference(&obj
->base
);
1123 mutex_unlock(&dev
->struct_mutex
);
1125 intel_runtime_pm_put(dev_priv
);
1131 i915_gem_check_wedge(struct i915_gpu_error
*error
,
1134 if (i915_reset_in_progress(error
)) {
1135 /* Non-interruptible callers can't handle -EAGAIN, hence return
1136 * -EIO unconditionally for these. */
1140 /* Recovery complete, but the reset failed ... */
1141 if (i915_terminally_wedged(error
))
1145 * Check if GPU Reset is in progress - we need intel_ring_begin
1146 * to work properly to reinit the hw state while the gpu is
1147 * still marked as reset-in-progress. Handle this with a flag.
1149 if (!error
->reload_in_reset
)
1157 * Compare arbitrary request against outstanding lazy request. Emit on match.
1160 i915_gem_check_olr(struct drm_i915_gem_request
*req
)
1164 WARN_ON(!mutex_is_locked(&req
->ring
->dev
->struct_mutex
));
1167 if (req
== req
->ring
->outstanding_lazy_request
)
1168 ret
= i915_add_request(req
->ring
);
1173 static void fake_irq(unsigned long data
)
1175 wake_up_process((struct task_struct
*)data
);
1178 static bool missed_irq(struct drm_i915_private
*dev_priv
,
1179 struct intel_engine_cs
*ring
)
1181 return test_bit(ring
->id
, &dev_priv
->gpu_error
.missed_irq_rings
);
1184 static bool can_wait_boost(struct drm_i915_file_private
*file_priv
)
1186 if (file_priv
== NULL
)
1189 return !atomic_xchg(&file_priv
->rps_wait_boost
, true);
1193 * __i915_wait_request - wait until execution of request has finished
1195 * @reset_counter: reset sequence associated with the given request
1196 * @interruptible: do an interruptible wait (normally yes)
1197 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
1199 * Note: It is of utmost importance that the passed in seqno and reset_counter
1200 * values have been read by the caller in an smp safe manner. Where read-side
1201 * locks are involved, it is sufficient to read the reset_counter before
1202 * unlocking the lock that protects the seqno. For lockless tricks, the
1203 * reset_counter _must_ be read before, and an appropriate smp_rmb must be
1206 * Returns 0 if the request was found within the alloted time. Else returns the
1207 * errno with remaining time filled in timeout argument.
1209 int __i915_wait_request(struct drm_i915_gem_request
*req
,
1210 unsigned reset_counter
,
1213 struct drm_i915_file_private
*file_priv
)
1215 struct intel_engine_cs
*ring
= i915_gem_request_get_ring(req
);
1216 struct drm_device
*dev
= ring
->dev
;
1217 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1218 const bool irq_test_in_progress
=
1219 ACCESS_ONCE(dev_priv
->gpu_error
.test_irq_rings
) & intel_ring_flag(ring
);
1221 unsigned long timeout_expire
;
1225 WARN(!intel_irqs_enabled(dev_priv
), "IRQs disabled");
1227 if (i915_gem_request_completed(req
, true))
1230 timeout_expire
= timeout
?
1231 jiffies
+ nsecs_to_jiffies_timeout((u64
)*timeout
) : 0;
1233 if (INTEL_INFO(dev
)->gen
>= 6 && ring
->id
== RCS
&& can_wait_boost(file_priv
)) {
1234 gen6_rps_boost(dev_priv
);
1236 mod_delayed_work(dev_priv
->wq
,
1237 &file_priv
->mm
.idle_work
,
1238 msecs_to_jiffies(100));
1241 if (!irq_test_in_progress
&& WARN_ON(!ring
->irq_get(ring
)))
1244 /* Record current time in case interrupted by signal, or wedged */
1245 trace_i915_gem_request_wait_begin(req
);
1246 before
= ktime_get_raw_ns();
1248 struct timer_list timer
;
1250 prepare_to_wait(&ring
->irq_queue
, &wait
,
1251 interruptible
? TASK_INTERRUPTIBLE
: TASK_UNINTERRUPTIBLE
);
1253 /* We need to check whether any gpu reset happened in between
1254 * the caller grabbing the seqno and now ... */
1255 if (reset_counter
!= atomic_read(&dev_priv
->gpu_error
.reset_counter
)) {
1256 /* ... but upgrade the -EAGAIN to an -EIO if the gpu
1257 * is truely gone. */
1258 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, interruptible
);
1264 if (i915_gem_request_completed(req
, false)) {
1269 if (interruptible
&& signal_pending(current
)) {
1274 if (timeout
&& time_after_eq(jiffies
, timeout_expire
)) {
1279 timer
.function
= NULL
;
1280 if (timeout
|| missed_irq(dev_priv
, ring
)) {
1281 unsigned long expire
;
1283 setup_timer_on_stack(&timer
, fake_irq
, (unsigned long)current
);
1284 expire
= missed_irq(dev_priv
, ring
) ? jiffies
+ 1 : timeout_expire
;
1285 mod_timer(&timer
, expire
);
1290 if (timer
.function
) {
1291 del_singleshot_timer_sync(&timer
);
1292 destroy_timer_on_stack(&timer
);
1295 now
= ktime_get_raw_ns();
1296 trace_i915_gem_request_wait_end(req
);
1298 if (!irq_test_in_progress
)
1299 ring
->irq_put(ring
);
1301 finish_wait(&ring
->irq_queue
, &wait
);
1304 s64 tres
= *timeout
- (now
- before
);
1306 *timeout
= tres
< 0 ? 0 : tres
;
1309 * Apparently ktime isn't accurate enough and occasionally has a
1310 * bit of mismatch in the jiffies<->nsecs<->ktime loop. So patch
1311 * things up to make the test happy. We allow up to 1 jiffy.
1313 * This is a regrssion from the timespec->ktime conversion.
1315 if (ret
== -ETIME
&& *timeout
< jiffies_to_usecs(1)*1000)
1323 * Waits for a request to be signaled, and cleans up the
1324 * request and object lists appropriately for that event.
1327 i915_wait_request(struct drm_i915_gem_request
*req
)
1329 struct drm_device
*dev
;
1330 struct drm_i915_private
*dev_priv
;
1332 unsigned reset_counter
;
1335 BUG_ON(req
== NULL
);
1337 dev
= req
->ring
->dev
;
1338 dev_priv
= dev
->dev_private
;
1339 interruptible
= dev_priv
->mm
.interruptible
;
1341 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
1343 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, interruptible
);
1347 ret
= i915_gem_check_olr(req
);
1351 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
1352 i915_gem_request_reference(req
);
1353 ret
= __i915_wait_request(req
, reset_counter
,
1354 interruptible
, NULL
, NULL
);
1355 i915_gem_request_unreference(req
);
1360 i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object
*obj
)
1365 /* Manually manage the write flush as we may have not yet
1366 * retired the buffer.
1368 * Note that the last_write_req is always the earlier of
1369 * the two (read/write) requests, so if we haved successfully waited,
1370 * we know we have passed the last write.
1372 i915_gem_request_assign(&obj
->last_write_req
, NULL
);
1378 * Ensures that all rendering to the object has completed and the object is
1379 * safe to unbind from the GTT or access from the CPU.
1381 static __must_check
int
1382 i915_gem_object_wait_rendering(struct drm_i915_gem_object
*obj
,
1385 struct drm_i915_gem_request
*req
;
1388 req
= readonly
? obj
->last_write_req
: obj
->last_read_req
;
1392 ret
= i915_wait_request(req
);
1396 return i915_gem_object_wait_rendering__tail(obj
);
1399 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1400 * as the object state may change during this call.
1402 static __must_check
int
1403 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object
*obj
,
1404 struct drm_i915_file_private
*file_priv
,
1407 struct drm_i915_gem_request
*req
;
1408 struct drm_device
*dev
= obj
->base
.dev
;
1409 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1410 unsigned reset_counter
;
1413 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
1414 BUG_ON(!dev_priv
->mm
.interruptible
);
1416 req
= readonly
? obj
->last_write_req
: obj
->last_read_req
;
1420 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, true);
1424 ret
= i915_gem_check_olr(req
);
1428 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
1429 i915_gem_request_reference(req
);
1430 mutex_unlock(&dev
->struct_mutex
);
1431 ret
= __i915_wait_request(req
, reset_counter
, true, NULL
, file_priv
);
1432 mutex_lock(&dev
->struct_mutex
);
1433 i915_gem_request_unreference(req
);
1437 return i915_gem_object_wait_rendering__tail(obj
);
1441 * Called when user space prepares to use an object with the CPU, either
1442 * through the mmap ioctl's mapping or a GTT mapping.
1445 i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
1446 struct drm_file
*file
)
1448 struct drm_i915_gem_set_domain
*args
= data
;
1449 struct drm_i915_gem_object
*obj
;
1450 uint32_t read_domains
= args
->read_domains
;
1451 uint32_t write_domain
= args
->write_domain
;
1454 /* Only handle setting domains to types used by the CPU. */
1455 if (write_domain
& I915_GEM_GPU_DOMAINS
)
1458 if (read_domains
& I915_GEM_GPU_DOMAINS
)
1461 /* Having something in the write domain implies it's in the read
1462 * domain, and only that read domain. Enforce that in the request.
1464 if (write_domain
!= 0 && read_domains
!= write_domain
)
1467 ret
= i915_mutex_lock_interruptible(dev
);
1471 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1472 if (&obj
->base
== NULL
) {
1477 /* Try to flush the object off the GPU without holding the lock.
1478 * We will repeat the flush holding the lock in the normal manner
1479 * to catch cases where we are gazumped.
1481 ret
= i915_gem_object_wait_rendering__nonblocking(obj
,
1487 if (read_domains
& I915_GEM_DOMAIN_GTT
)
1488 ret
= i915_gem_object_set_to_gtt_domain(obj
, write_domain
!= 0);
1490 ret
= i915_gem_object_set_to_cpu_domain(obj
, write_domain
!= 0);
1493 drm_gem_object_unreference(&obj
->base
);
1495 mutex_unlock(&dev
->struct_mutex
);
1500 * Called when user space has done writes to this buffer
1503 i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1504 struct drm_file
*file
)
1506 struct drm_i915_gem_sw_finish
*args
= data
;
1507 struct drm_i915_gem_object
*obj
;
1510 ret
= i915_mutex_lock_interruptible(dev
);
1514 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1515 if (&obj
->base
== NULL
) {
1520 /* Pinned buffers may be scanout, so flush the cache */
1521 if (obj
->pin_display
)
1522 i915_gem_object_flush_cpu_write_domain(obj
);
1524 drm_gem_object_unreference(&obj
->base
);
1526 mutex_unlock(&dev
->struct_mutex
);
1531 * Maps the contents of an object, returning the address it is mapped
1534 * While the mapping holds a reference on the contents of the object, it doesn't
1535 * imply a ref on the object itself.
1539 * DRM driver writers who look a this function as an example for how to do GEM
1540 * mmap support, please don't implement mmap support like here. The modern way
1541 * to implement DRM mmap support is with an mmap offset ioctl (like
1542 * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly.
1543 * That way debug tooling like valgrind will understand what's going on, hiding
1544 * the mmap call in a driver private ioctl will break that. The i915 driver only
1545 * does cpu mmaps this way because we didn't know better.
1548 i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1549 struct drm_file
*file
)
1551 struct drm_i915_gem_mmap
*args
= data
;
1552 struct drm_gem_object
*obj
;
1555 if (args
->flags
& ~(I915_MMAP_WC
))
1558 if (args
->flags
& I915_MMAP_WC
&& !cpu_has_pat
)
1561 obj
= drm_gem_object_lookup(dev
, file
, args
->handle
);
1565 /* prime objects have no backing filp to GEM mmap
1569 drm_gem_object_unreference_unlocked(obj
);
1573 addr
= vm_mmap(obj
->filp
, 0, args
->size
,
1574 PROT_READ
| PROT_WRITE
, MAP_SHARED
,
1576 if (args
->flags
& I915_MMAP_WC
) {
1577 struct mm_struct
*mm
= current
->mm
;
1578 struct vm_area_struct
*vma
;
1580 down_write(&mm
->mmap_sem
);
1581 vma
= find_vma(mm
, addr
);
1584 pgprot_writecombine(vm_get_page_prot(vma
->vm_flags
));
1587 up_write(&mm
->mmap_sem
);
1589 drm_gem_object_unreference_unlocked(obj
);
1590 if (IS_ERR((void *)addr
))
1593 args
->addr_ptr
= (uint64_t) addr
;
1599 * i915_gem_fault - fault a page into the GTT
1600 * vma: VMA in question
1603 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1604 * from userspace. The fault handler takes care of binding the object to
1605 * the GTT (if needed), allocating and programming a fence register (again,
1606 * only if needed based on whether the old reg is still valid or the object
1607 * is tiled) and inserting a new PTE into the faulting process.
1609 * Note that the faulting process may involve evicting existing objects
1610 * from the GTT and/or fence registers to make room. So performance may
1611 * suffer if the GTT working set is large or there are few fence registers
1614 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
)
1616 struct drm_i915_gem_object
*obj
= to_intel_bo(vma
->vm_private_data
);
1617 struct drm_device
*dev
= obj
->base
.dev
;
1618 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1619 pgoff_t page_offset
;
1622 bool write
= !!(vmf
->flags
& FAULT_FLAG_WRITE
);
1624 intel_runtime_pm_get(dev_priv
);
1626 /* We don't use vmf->pgoff since that has the fake offset */
1627 page_offset
= ((unsigned long)vmf
->virtual_address
- vma
->vm_start
) >>
1630 ret
= i915_mutex_lock_interruptible(dev
);
1634 trace_i915_gem_object_fault(obj
, page_offset
, true, write
);
1636 /* Try to flush the object off the GPU first without holding the lock.
1637 * Upon reacquiring the lock, we will perform our sanity checks and then
1638 * repeat the flush holding the lock in the normal manner to catch cases
1639 * where we are gazumped.
1641 ret
= i915_gem_object_wait_rendering__nonblocking(obj
, NULL
, !write
);
1645 /* Access to snoopable pages through the GTT is incoherent. */
1646 if (obj
->cache_level
!= I915_CACHE_NONE
&& !HAS_LLC(dev
)) {
1651 /* Now bind it into the GTT if needed */
1652 ret
= i915_gem_obj_ggtt_pin(obj
, 0, PIN_MAPPABLE
);
1656 ret
= i915_gem_object_set_to_gtt_domain(obj
, write
);
1660 ret
= i915_gem_object_get_fence(obj
);
1664 /* Finally, remap it using the new GTT offset */
1665 pfn
= dev_priv
->gtt
.mappable_base
+ i915_gem_obj_ggtt_offset(obj
);
1668 if (!obj
->fault_mappable
) {
1669 unsigned long size
= min_t(unsigned long,
1670 vma
->vm_end
- vma
->vm_start
,
1674 for (i
= 0; i
< size
>> PAGE_SHIFT
; i
++) {
1675 ret
= vm_insert_pfn(vma
,
1676 (unsigned long)vma
->vm_start
+ i
* PAGE_SIZE
,
1682 obj
->fault_mappable
= true;
1684 ret
= vm_insert_pfn(vma
,
1685 (unsigned long)vmf
->virtual_address
,
1688 i915_gem_object_ggtt_unpin(obj
);
1690 mutex_unlock(&dev
->struct_mutex
);
1695 * We eat errors when the gpu is terminally wedged to avoid
1696 * userspace unduly crashing (gl has no provisions for mmaps to
1697 * fail). But any other -EIO isn't ours (e.g. swap in failure)
1698 * and so needs to be reported.
1700 if (!i915_terminally_wedged(&dev_priv
->gpu_error
)) {
1701 ret
= VM_FAULT_SIGBUS
;
1706 * EAGAIN means the gpu is hung and we'll wait for the error
1707 * handler to reset everything when re-faulting in
1708 * i915_mutex_lock_interruptible.
1715 * EBUSY is ok: this just means that another thread
1716 * already did the job.
1718 ret
= VM_FAULT_NOPAGE
;
1725 ret
= VM_FAULT_SIGBUS
;
1728 WARN_ONCE(ret
, "unhandled error in i915_gem_fault: %i\n", ret
);
1729 ret
= VM_FAULT_SIGBUS
;
1733 intel_runtime_pm_put(dev_priv
);
1738 * i915_gem_release_mmap - remove physical page mappings
1739 * @obj: obj in question
1741 * Preserve the reservation of the mmapping with the DRM core code, but
1742 * relinquish ownership of the pages back to the system.
1744 * It is vital that we remove the page mapping if we have mapped a tiled
1745 * object through the GTT and then lose the fence register due to
1746 * resource pressure. Similarly if the object has been moved out of the
1747 * aperture, than pages mapped into userspace must be revoked. Removing the
1748 * mapping will then trigger a page fault on the next user access, allowing
1749 * fixup by i915_gem_fault().
1752 i915_gem_release_mmap(struct drm_i915_gem_object
*obj
)
1754 if (!obj
->fault_mappable
)
1757 drm_vma_node_unmap(&obj
->base
.vma_node
,
1758 obj
->base
.dev
->anon_inode
->i_mapping
);
1759 obj
->fault_mappable
= false;
1763 i915_gem_release_all_mmaps(struct drm_i915_private
*dev_priv
)
1765 struct drm_i915_gem_object
*obj
;
1767 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
)
1768 i915_gem_release_mmap(obj
);
1772 i915_gem_get_gtt_size(struct drm_device
*dev
, uint32_t size
, int tiling_mode
)
1776 if (INTEL_INFO(dev
)->gen
>= 4 ||
1777 tiling_mode
== I915_TILING_NONE
)
1780 /* Previous chips need a power-of-two fence region when tiling */
1781 if (INTEL_INFO(dev
)->gen
== 3)
1782 gtt_size
= 1024*1024;
1784 gtt_size
= 512*1024;
1786 while (gtt_size
< size
)
1793 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1794 * @obj: object to check
1796 * Return the required GTT alignment for an object, taking into account
1797 * potential fence register mapping.
1800 i915_gem_get_gtt_alignment(struct drm_device
*dev
, uint32_t size
,
1801 int tiling_mode
, bool fenced
)
1804 * Minimum alignment is 4k (GTT page size), but might be greater
1805 * if a fence register is needed for the object.
1807 if (INTEL_INFO(dev
)->gen
>= 4 || (!fenced
&& IS_G33(dev
)) ||
1808 tiling_mode
== I915_TILING_NONE
)
1812 * Previous chips need to be aligned to the size of the smallest
1813 * fence register that can contain the object.
1815 return i915_gem_get_gtt_size(dev
, size
, tiling_mode
);
1818 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object
*obj
)
1820 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
1823 if (drm_vma_node_has_offset(&obj
->base
.vma_node
))
1826 dev_priv
->mm
.shrinker_no_lock_stealing
= true;
1828 ret
= drm_gem_create_mmap_offset(&obj
->base
);
1832 /* Badly fragmented mmap space? The only way we can recover
1833 * space is by destroying unwanted objects. We can't randomly release
1834 * mmap_offsets as userspace expects them to be persistent for the
1835 * lifetime of the objects. The closest we can is to release the
1836 * offsets on purgeable objects by truncating it and marking it purged,
1837 * which prevents userspace from ever using that object again.
1839 i915_gem_shrink(dev_priv
,
1840 obj
->base
.size
>> PAGE_SHIFT
,
1842 I915_SHRINK_UNBOUND
|
1843 I915_SHRINK_PURGEABLE
);
1844 ret
= drm_gem_create_mmap_offset(&obj
->base
);
1848 i915_gem_shrink_all(dev_priv
);
1849 ret
= drm_gem_create_mmap_offset(&obj
->base
);
1851 dev_priv
->mm
.shrinker_no_lock_stealing
= false;
1856 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object
*obj
)
1858 drm_gem_free_mmap_offset(&obj
->base
);
1862 i915_gem_mmap_gtt(struct drm_file
*file
,
1863 struct drm_device
*dev
,
1867 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1868 struct drm_i915_gem_object
*obj
;
1871 ret
= i915_mutex_lock_interruptible(dev
);
1875 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, handle
));
1876 if (&obj
->base
== NULL
) {
1881 if (obj
->base
.size
> dev_priv
->gtt
.mappable_end
) {
1886 if (obj
->madv
!= I915_MADV_WILLNEED
) {
1887 DRM_DEBUG("Attempting to mmap a purgeable buffer\n");
1892 ret
= i915_gem_object_create_mmap_offset(obj
);
1896 *offset
= drm_vma_node_offset_addr(&obj
->base
.vma_node
);
1899 drm_gem_object_unreference(&obj
->base
);
1901 mutex_unlock(&dev
->struct_mutex
);
1906 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1908 * @data: GTT mapping ioctl data
1909 * @file: GEM object info
1911 * Simply returns the fake offset to userspace so it can mmap it.
1912 * The mmap call will end up in drm_gem_mmap(), which will set things
1913 * up so we can get faults in the handler above.
1915 * The fault handler will take care of binding the object into the GTT
1916 * (since it may have been evicted to make room for something), allocating
1917 * a fence register, and mapping the appropriate aperture address into
1921 i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
1922 struct drm_file
*file
)
1924 struct drm_i915_gem_mmap_gtt
*args
= data
;
1926 return i915_gem_mmap_gtt(file
, dev
, args
->handle
, &args
->offset
);
1929 /* Immediately discard the backing storage */
1931 i915_gem_object_truncate(struct drm_i915_gem_object
*obj
)
1933 i915_gem_object_free_mmap_offset(obj
);
1935 if (obj
->base
.filp
== NULL
)
1938 /* Our goal here is to return as much of the memory as
1939 * is possible back to the system as we are called from OOM.
1940 * To do this we must instruct the shmfs to drop all of its
1941 * backing pages, *now*.
1943 shmem_truncate_range(file_inode(obj
->base
.filp
), 0, (loff_t
)-1);
1944 obj
->madv
= __I915_MADV_PURGED
;
1947 /* Try to discard unwanted pages */
1949 i915_gem_object_invalidate(struct drm_i915_gem_object
*obj
)
1951 struct address_space
*mapping
;
1953 switch (obj
->madv
) {
1954 case I915_MADV_DONTNEED
:
1955 i915_gem_object_truncate(obj
);
1956 case __I915_MADV_PURGED
:
1960 if (obj
->base
.filp
== NULL
)
1963 mapping
= file_inode(obj
->base
.filp
)->i_mapping
,
1964 invalidate_mapping_pages(mapping
, 0, (loff_t
)-1);
1968 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object
*obj
)
1970 struct sg_page_iter sg_iter
;
1973 BUG_ON(obj
->madv
== __I915_MADV_PURGED
);
1975 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
1977 /* In the event of a disaster, abandon all caches and
1978 * hope for the best.
1980 WARN_ON(ret
!= -EIO
);
1981 i915_gem_clflush_object(obj
, true);
1982 obj
->base
.read_domains
= obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
1985 if (i915_gem_object_needs_bit17_swizzle(obj
))
1986 i915_gem_object_save_bit_17_swizzle(obj
);
1988 if (obj
->madv
== I915_MADV_DONTNEED
)
1991 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
, 0) {
1992 struct page
*page
= sg_page_iter_page(&sg_iter
);
1995 set_page_dirty(page
);
1997 if (obj
->madv
== I915_MADV_WILLNEED
)
1998 mark_page_accessed(page
);
2000 page_cache_release(page
);
2004 sg_free_table(obj
->pages
);
2009 i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
)
2011 const struct drm_i915_gem_object_ops
*ops
= obj
->ops
;
2013 if (obj
->pages
== NULL
)
2016 if (obj
->pages_pin_count
)
2019 BUG_ON(i915_gem_obj_bound_any(obj
));
2021 /* ->put_pages might need to allocate memory for the bit17 swizzle
2022 * array, hence protect them from being reaped by removing them from gtt
2024 list_del(&obj
->global_list
);
2026 ops
->put_pages(obj
);
2029 i915_gem_object_invalidate(obj
);
2035 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object
*obj
)
2037 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2039 struct address_space
*mapping
;
2040 struct sg_table
*st
;
2041 struct scatterlist
*sg
;
2042 struct sg_page_iter sg_iter
;
2044 unsigned long last_pfn
= 0; /* suppress gcc warning */
2047 /* Assert that the object is not currently in any GPU domain. As it
2048 * wasn't in the GTT, there shouldn't be any way it could have been in
2051 BUG_ON(obj
->base
.read_domains
& I915_GEM_GPU_DOMAINS
);
2052 BUG_ON(obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
);
2054 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
2058 page_count
= obj
->base
.size
/ PAGE_SIZE
;
2059 if (sg_alloc_table(st
, page_count
, GFP_KERNEL
)) {
2064 /* Get the list of pages out of our struct file. They'll be pinned
2065 * at this point until we release them.
2067 * Fail silently without starting the shrinker
2069 mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
2070 gfp
= mapping_gfp_mask(mapping
);
2071 gfp
|= __GFP_NORETRY
| __GFP_NOWARN
| __GFP_NO_KSWAPD
;
2072 gfp
&= ~(__GFP_IO
| __GFP_WAIT
);
2075 for (i
= 0; i
< page_count
; i
++) {
2076 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
2078 i915_gem_shrink(dev_priv
,
2081 I915_SHRINK_UNBOUND
|
2082 I915_SHRINK_PURGEABLE
);
2083 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
2086 /* We've tried hard to allocate the memory by reaping
2087 * our own buffer, now let the real VM do its job and
2088 * go down in flames if truly OOM.
2090 i915_gem_shrink_all(dev_priv
);
2091 page
= shmem_read_mapping_page(mapping
, i
);
2095 #ifdef CONFIG_SWIOTLB
2096 if (swiotlb_nr_tbl()) {
2098 sg_set_page(sg
, page
, PAGE_SIZE
, 0);
2103 if (!i
|| page_to_pfn(page
) != last_pfn
+ 1) {
2107 sg_set_page(sg
, page
, PAGE_SIZE
, 0);
2109 sg
->length
+= PAGE_SIZE
;
2111 last_pfn
= page_to_pfn(page
);
2113 /* Check that the i965g/gm workaround works. */
2114 WARN_ON((gfp
& __GFP_DMA32
) && (last_pfn
>= 0x00100000UL
));
2116 #ifdef CONFIG_SWIOTLB
2117 if (!swiotlb_nr_tbl())
2122 if (i915_gem_object_needs_bit17_swizzle(obj
))
2123 i915_gem_object_do_bit_17_swizzle(obj
);
2125 if (obj
->tiling_mode
!= I915_TILING_NONE
&&
2126 dev_priv
->quirks
& QUIRK_PIN_SWIZZLED_PAGES
)
2127 i915_gem_object_pin_pages(obj
);
2133 for_each_sg_page(st
->sgl
, &sg_iter
, st
->nents
, 0)
2134 page_cache_release(sg_page_iter_page(&sg_iter
));
2138 /* shmemfs first checks if there is enough memory to allocate the page
2139 * and reports ENOSPC should there be insufficient, along with the usual
2140 * ENOMEM for a genuine allocation failure.
2142 * We use ENOSPC in our driver to mean that we have run out of aperture
2143 * space and so want to translate the error from shmemfs back to our
2144 * usual understanding of ENOMEM.
2146 if (PTR_ERR(page
) == -ENOSPC
)
2149 return PTR_ERR(page
);
2152 /* Ensure that the associated pages are gathered from the backing storage
2153 * and pinned into our object. i915_gem_object_get_pages() may be called
2154 * multiple times before they are released by a single call to
2155 * i915_gem_object_put_pages() - once the pages are no longer referenced
2156 * either as a result of memory pressure (reaping pages under the shrinker)
2157 * or as the object is itself released.
2160 i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
)
2162 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2163 const struct drm_i915_gem_object_ops
*ops
= obj
->ops
;
2169 if (obj
->madv
!= I915_MADV_WILLNEED
) {
2170 DRM_DEBUG("Attempting to obtain a purgeable object\n");
2174 BUG_ON(obj
->pages_pin_count
);
2176 ret
= ops
->get_pages(obj
);
2180 list_add_tail(&obj
->global_list
, &dev_priv
->mm
.unbound_list
);
2185 i915_gem_object_move_to_active(struct drm_i915_gem_object
*obj
,
2186 struct intel_engine_cs
*ring
)
2188 struct drm_i915_gem_request
*req
;
2189 struct intel_engine_cs
*old_ring
;
2191 BUG_ON(ring
== NULL
);
2193 req
= intel_ring_get_request(ring
);
2194 old_ring
= i915_gem_request_get_ring(obj
->last_read_req
);
2196 if (old_ring
!= ring
&& obj
->last_write_req
) {
2197 /* Keep the request relative to the current ring */
2198 i915_gem_request_assign(&obj
->last_write_req
, req
);
2201 /* Add a reference if we're newly entering the active list. */
2203 drm_gem_object_reference(&obj
->base
);
2207 list_move_tail(&obj
->ring_list
, &ring
->active_list
);
2209 i915_gem_request_assign(&obj
->last_read_req
, req
);
2212 void i915_vma_move_to_active(struct i915_vma
*vma
,
2213 struct intel_engine_cs
*ring
)
2215 list_move_tail(&vma
->mm_list
, &vma
->vm
->active_list
);
2216 return i915_gem_object_move_to_active(vma
->obj
, ring
);
2220 i915_gem_object_move_to_inactive(struct drm_i915_gem_object
*obj
)
2222 struct i915_vma
*vma
;
2224 BUG_ON(obj
->base
.write_domain
& ~I915_GEM_GPU_DOMAINS
);
2225 BUG_ON(!obj
->active
);
2227 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
) {
2228 if (!list_empty(&vma
->mm_list
))
2229 list_move_tail(&vma
->mm_list
, &vma
->vm
->inactive_list
);
2232 intel_fb_obj_flush(obj
, true);
2234 list_del_init(&obj
->ring_list
);
2236 i915_gem_request_assign(&obj
->last_read_req
, NULL
);
2237 i915_gem_request_assign(&obj
->last_write_req
, NULL
);
2238 obj
->base
.write_domain
= 0;
2240 i915_gem_request_assign(&obj
->last_fenced_req
, NULL
);
2243 drm_gem_object_unreference(&obj
->base
);
2245 WARN_ON(i915_verify_lists(dev
));
2249 i915_gem_object_retire(struct drm_i915_gem_object
*obj
)
2251 if (obj
->last_read_req
== NULL
)
2254 if (i915_gem_request_completed(obj
->last_read_req
, true))
2255 i915_gem_object_move_to_inactive(obj
);
2259 i915_gem_init_seqno(struct drm_device
*dev
, u32 seqno
)
2261 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2262 struct intel_engine_cs
*ring
;
2265 /* Carefully retire all requests without writing to the rings */
2266 for_each_ring(ring
, dev_priv
, i
) {
2267 ret
= intel_ring_idle(ring
);
2271 i915_gem_retire_requests(dev
);
2273 /* Finally reset hw state */
2274 for_each_ring(ring
, dev_priv
, i
) {
2275 intel_ring_init_seqno(ring
, seqno
);
2277 for (j
= 0; j
< ARRAY_SIZE(ring
->semaphore
.sync_seqno
); j
++)
2278 ring
->semaphore
.sync_seqno
[j
] = 0;
2284 int i915_gem_set_seqno(struct drm_device
*dev
, u32 seqno
)
2286 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2292 /* HWS page needs to be set less than what we
2293 * will inject to ring
2295 ret
= i915_gem_init_seqno(dev
, seqno
- 1);
2299 /* Carefully set the last_seqno value so that wrap
2300 * detection still works
2302 dev_priv
->next_seqno
= seqno
;
2303 dev_priv
->last_seqno
= seqno
- 1;
2304 if (dev_priv
->last_seqno
== 0)
2305 dev_priv
->last_seqno
--;
2311 i915_gem_get_seqno(struct drm_device
*dev
, u32
*seqno
)
2313 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2315 /* reserve 0 for non-seqno */
2316 if (dev_priv
->next_seqno
== 0) {
2317 int ret
= i915_gem_init_seqno(dev
, 0);
2321 dev_priv
->next_seqno
= 1;
2324 *seqno
= dev_priv
->last_seqno
= dev_priv
->next_seqno
++;
2328 int __i915_add_request(struct intel_engine_cs
*ring
,
2329 struct drm_file
*file
,
2330 struct drm_i915_gem_object
*obj
)
2332 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
2333 struct drm_i915_gem_request
*request
;
2334 struct intel_ringbuffer
*ringbuf
;
2338 request
= ring
->outstanding_lazy_request
;
2339 if (WARN_ON(request
== NULL
))
2342 if (i915
.enable_execlists
) {
2343 ringbuf
= request
->ctx
->engine
[ring
->id
].ringbuf
;
2345 ringbuf
= ring
->buffer
;
2347 request_start
= intel_ring_get_tail(ringbuf
);
2349 * Emit any outstanding flushes - execbuf can fail to emit the flush
2350 * after having emitted the batchbuffer command. Hence we need to fix
2351 * things up similar to emitting the lazy request. The difference here
2352 * is that the flush _must_ happen before the next request, no matter
2355 if (i915
.enable_execlists
) {
2356 ret
= logical_ring_flush_all_caches(ringbuf
, request
->ctx
);
2360 ret
= intel_ring_flush_all_caches(ring
);
2365 /* Record the position of the start of the request so that
2366 * should we detect the updated seqno part-way through the
2367 * GPU processing the request, we never over-estimate the
2368 * position of the head.
2370 request
->postfix
= intel_ring_get_tail(ringbuf
);
2372 if (i915
.enable_execlists
) {
2373 ret
= ring
->emit_request(ringbuf
, request
);
2377 ret
= ring
->add_request(ring
);
2382 request
->head
= request_start
;
2383 request
->tail
= intel_ring_get_tail(ringbuf
);
2385 /* Whilst this request exists, batch_obj will be on the
2386 * active_list, and so will hold the active reference. Only when this
2387 * request is retired will the the batch_obj be moved onto the
2388 * inactive_list and lose its active reference. Hence we do not need
2389 * to explicitly hold another reference here.
2391 request
->batch_obj
= obj
;
2393 if (!i915
.enable_execlists
) {
2394 /* Hold a reference to the current context so that we can inspect
2395 * it later in case a hangcheck error event fires.
2397 request
->ctx
= ring
->last_context
;
2399 i915_gem_context_reference(request
->ctx
);
2402 request
->emitted_jiffies
= jiffies
;
2403 list_add_tail(&request
->list
, &ring
->request_list
);
2404 request
->file_priv
= NULL
;
2407 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
2409 spin_lock(&file_priv
->mm
.lock
);
2410 request
->file_priv
= file_priv
;
2411 list_add_tail(&request
->client_list
,
2412 &file_priv
->mm
.request_list
);
2413 spin_unlock(&file_priv
->mm
.lock
);
2415 request
->pid
= get_pid(task_pid(current
));
2418 trace_i915_gem_request_add(request
);
2419 ring
->outstanding_lazy_request
= NULL
;
2421 i915_queue_hangcheck(ring
->dev
);
2423 cancel_delayed_work_sync(&dev_priv
->mm
.idle_work
);
2424 queue_delayed_work(dev_priv
->wq
,
2425 &dev_priv
->mm
.retire_work
,
2426 round_jiffies_up_relative(HZ
));
2427 intel_mark_busy(dev_priv
->dev
);
2433 i915_gem_request_remove_from_client(struct drm_i915_gem_request
*request
)
2435 struct drm_i915_file_private
*file_priv
= request
->file_priv
;
2440 spin_lock(&file_priv
->mm
.lock
);
2441 list_del(&request
->client_list
);
2442 request
->file_priv
= NULL
;
2443 spin_unlock(&file_priv
->mm
.lock
);
2446 static bool i915_context_is_banned(struct drm_i915_private
*dev_priv
,
2447 const struct intel_context
*ctx
)
2449 unsigned long elapsed
;
2451 elapsed
= get_seconds() - ctx
->hang_stats
.guilty_ts
;
2453 if (ctx
->hang_stats
.banned
)
2456 if (ctx
->hang_stats
.ban_period_seconds
&&
2457 elapsed
<= ctx
->hang_stats
.ban_period_seconds
) {
2458 if (!i915_gem_context_is_default(ctx
)) {
2459 DRM_DEBUG("context hanging too fast, banning!\n");
2461 } else if (i915_stop_ring_allow_ban(dev_priv
)) {
2462 if (i915_stop_ring_allow_warn(dev_priv
))
2463 DRM_ERROR("gpu hanging too fast, banning!\n");
2471 static void i915_set_reset_status(struct drm_i915_private
*dev_priv
,
2472 struct intel_context
*ctx
,
2475 struct i915_ctx_hang_stats
*hs
;
2480 hs
= &ctx
->hang_stats
;
2483 hs
->banned
= i915_context_is_banned(dev_priv
, ctx
);
2485 hs
->guilty_ts
= get_seconds();
2487 hs
->batch_pending
++;
2491 static void i915_gem_free_request(struct drm_i915_gem_request
*request
)
2493 list_del(&request
->list
);
2494 i915_gem_request_remove_from_client(request
);
2496 put_pid(request
->pid
);
2498 i915_gem_request_unreference(request
);
2501 void i915_gem_request_free(struct kref
*req_ref
)
2503 struct drm_i915_gem_request
*req
= container_of(req_ref
,
2505 struct intel_context
*ctx
= req
->ctx
;
2508 if (i915
.enable_execlists
) {
2509 struct intel_engine_cs
*ring
= req
->ring
;
2511 if (ctx
!= ring
->default_context
)
2512 intel_lr_context_unpin(ring
, ctx
);
2515 i915_gem_context_unreference(ctx
);
2521 int i915_gem_request_alloc(struct intel_engine_cs
*ring
,
2522 struct intel_context
*ctx
)
2525 struct drm_i915_gem_request
*request
;
2526 struct drm_i915_private
*dev_private
= ring
->dev
->dev_private
;
2528 if (ring
->outstanding_lazy_request
)
2531 request
= kzalloc(sizeof(*request
), GFP_KERNEL
);
2532 if (request
== NULL
)
2535 ret
= i915_gem_get_seqno(ring
->dev
, &request
->seqno
);
2541 kref_init(&request
->ref
);
2542 request
->ring
= ring
;
2543 request
->uniq
= dev_private
->request_uniq
++;
2545 if (i915
.enable_execlists
)
2546 ret
= intel_logical_ring_alloc_request_extras(request
, ctx
);
2548 ret
= intel_ring_alloc_request_extras(request
);
2554 ring
->outstanding_lazy_request
= request
;
2558 struct drm_i915_gem_request
*
2559 i915_gem_find_active_request(struct intel_engine_cs
*ring
)
2561 struct drm_i915_gem_request
*request
;
2563 list_for_each_entry(request
, &ring
->request_list
, list
) {
2564 if (i915_gem_request_completed(request
, false))
2573 static void i915_gem_reset_ring_status(struct drm_i915_private
*dev_priv
,
2574 struct intel_engine_cs
*ring
)
2576 struct drm_i915_gem_request
*request
;
2579 request
= i915_gem_find_active_request(ring
);
2581 if (request
== NULL
)
2584 ring_hung
= ring
->hangcheck
.score
>= HANGCHECK_SCORE_RING_HUNG
;
2586 i915_set_reset_status(dev_priv
, request
->ctx
, ring_hung
);
2588 list_for_each_entry_continue(request
, &ring
->request_list
, list
)
2589 i915_set_reset_status(dev_priv
, request
->ctx
, false);
2592 static void i915_gem_reset_ring_cleanup(struct drm_i915_private
*dev_priv
,
2593 struct intel_engine_cs
*ring
)
2595 while (!list_empty(&ring
->active_list
)) {
2596 struct drm_i915_gem_object
*obj
;
2598 obj
= list_first_entry(&ring
->active_list
,
2599 struct drm_i915_gem_object
,
2602 i915_gem_object_move_to_inactive(obj
);
2606 * Clear the execlists queue up before freeing the requests, as those
2607 * are the ones that keep the context and ringbuffer backing objects
2610 while (!list_empty(&ring
->execlist_queue
)) {
2611 struct drm_i915_gem_request
*submit_req
;
2613 submit_req
= list_first_entry(&ring
->execlist_queue
,
2614 struct drm_i915_gem_request
,
2616 list_del(&submit_req
->execlist_link
);
2617 intel_runtime_pm_put(dev_priv
);
2619 if (submit_req
->ctx
!= ring
->default_context
)
2620 intel_lr_context_unpin(ring
, submit_req
->ctx
);
2622 i915_gem_request_unreference(submit_req
);
2626 * We must free the requests after all the corresponding objects have
2627 * been moved off active lists. Which is the same order as the normal
2628 * retire_requests function does. This is important if object hold
2629 * implicit references on things like e.g. ppgtt address spaces through
2632 while (!list_empty(&ring
->request_list
)) {
2633 struct drm_i915_gem_request
*request
;
2635 request
= list_first_entry(&ring
->request_list
,
2636 struct drm_i915_gem_request
,
2639 i915_gem_free_request(request
);
2642 /* This may not have been flushed before the reset, so clean it now */
2643 i915_gem_request_assign(&ring
->outstanding_lazy_request
, NULL
);
2646 void i915_gem_restore_fences(struct drm_device
*dev
)
2648 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2651 for (i
= 0; i
< dev_priv
->num_fence_regs
; i
++) {
2652 struct drm_i915_fence_reg
*reg
= &dev_priv
->fence_regs
[i
];
2655 * Commit delayed tiling changes if we have an object still
2656 * attached to the fence, otherwise just clear the fence.
2659 i915_gem_object_update_fence(reg
->obj
, reg
,
2660 reg
->obj
->tiling_mode
);
2662 i915_gem_write_fence(dev
, i
, NULL
);
2667 void i915_gem_reset(struct drm_device
*dev
)
2669 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2670 struct intel_engine_cs
*ring
;
2674 * Before we free the objects from the requests, we need to inspect
2675 * them for finding the guilty party. As the requests only borrow
2676 * their reference to the objects, the inspection must be done first.
2678 for_each_ring(ring
, dev_priv
, i
)
2679 i915_gem_reset_ring_status(dev_priv
, ring
);
2681 for_each_ring(ring
, dev_priv
, i
)
2682 i915_gem_reset_ring_cleanup(dev_priv
, ring
);
2684 i915_gem_context_reset(dev
);
2686 i915_gem_restore_fences(dev
);
2690 * This function clears the request list as sequence numbers are passed.
2693 i915_gem_retire_requests_ring(struct intel_engine_cs
*ring
)
2695 if (list_empty(&ring
->request_list
))
2698 WARN_ON(i915_verify_lists(ring
->dev
));
2700 /* Retire requests first as we use it above for the early return.
2701 * If we retire requests last, we may use a later seqno and so clear
2702 * the requests lists without clearing the active list, leading to
2705 while (!list_empty(&ring
->request_list
)) {
2706 struct drm_i915_gem_request
*request
;
2708 request
= list_first_entry(&ring
->request_list
,
2709 struct drm_i915_gem_request
,
2712 if (!i915_gem_request_completed(request
, true))
2715 trace_i915_gem_request_retire(request
);
2717 /* We know the GPU must have read the request to have
2718 * sent us the seqno + interrupt, so use the position
2719 * of tail of the request to update the last known position
2722 request
->ringbuf
->last_retired_head
= request
->postfix
;
2724 i915_gem_free_request(request
);
2727 /* Move any buffers on the active list that are no longer referenced
2728 * by the ringbuffer to the flushing/inactive lists as appropriate,
2729 * before we free the context associated with the requests.
2731 while (!list_empty(&ring
->active_list
)) {
2732 struct drm_i915_gem_object
*obj
;
2734 obj
= list_first_entry(&ring
->active_list
,
2735 struct drm_i915_gem_object
,
2738 if (!i915_gem_request_completed(obj
->last_read_req
, true))
2741 i915_gem_object_move_to_inactive(obj
);
2744 if (unlikely(ring
->trace_irq_req
&&
2745 i915_gem_request_completed(ring
->trace_irq_req
, true))) {
2746 ring
->irq_put(ring
);
2747 i915_gem_request_assign(&ring
->trace_irq_req
, NULL
);
2750 WARN_ON(i915_verify_lists(ring
->dev
));
2754 i915_gem_retire_requests(struct drm_device
*dev
)
2756 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2757 struct intel_engine_cs
*ring
;
2761 for_each_ring(ring
, dev_priv
, i
) {
2762 i915_gem_retire_requests_ring(ring
);
2763 idle
&= list_empty(&ring
->request_list
);
2764 if (i915
.enable_execlists
) {
2765 unsigned long flags
;
2767 spin_lock_irqsave(&ring
->execlist_lock
, flags
);
2768 idle
&= list_empty(&ring
->execlist_queue
);
2769 spin_unlock_irqrestore(&ring
->execlist_lock
, flags
);
2771 intel_execlists_retire_requests(ring
);
2776 mod_delayed_work(dev_priv
->wq
,
2777 &dev_priv
->mm
.idle_work
,
2778 msecs_to_jiffies(100));
2784 i915_gem_retire_work_handler(struct work_struct
*work
)
2786 struct drm_i915_private
*dev_priv
=
2787 container_of(work
, typeof(*dev_priv
), mm
.retire_work
.work
);
2788 struct drm_device
*dev
= dev_priv
->dev
;
2791 /* Come back later if the device is busy... */
2793 if (mutex_trylock(&dev
->struct_mutex
)) {
2794 idle
= i915_gem_retire_requests(dev
);
2795 mutex_unlock(&dev
->struct_mutex
);
2798 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
,
2799 round_jiffies_up_relative(HZ
));
2803 i915_gem_idle_work_handler(struct work_struct
*work
)
2805 struct drm_i915_private
*dev_priv
=
2806 container_of(work
, typeof(*dev_priv
), mm
.idle_work
.work
);
2808 intel_mark_idle(dev_priv
->dev
);
2812 * Ensures that an object will eventually get non-busy by flushing any required
2813 * write domains, emitting any outstanding lazy request and retiring and
2814 * completed requests.
2817 i915_gem_object_flush_active(struct drm_i915_gem_object
*obj
)
2819 struct intel_engine_cs
*ring
;
2823 ring
= i915_gem_request_get_ring(obj
->last_read_req
);
2825 ret
= i915_gem_check_olr(obj
->last_read_req
);
2829 i915_gem_retire_requests_ring(ring
);
2836 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2837 * @DRM_IOCTL_ARGS: standard ioctl arguments
2839 * Returns 0 if successful, else an error is returned with the remaining time in
2840 * the timeout parameter.
2841 * -ETIME: object is still busy after timeout
2842 * -ERESTARTSYS: signal interrupted the wait
2843 * -ENONENT: object doesn't exist
2844 * Also possible, but rare:
2845 * -EAGAIN: GPU wedged
2847 * -ENODEV: Internal IRQ fail
2848 * -E?: The add request failed
2850 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2851 * non-zero timeout parameter the wait ioctl will wait for the given number of
2852 * nanoseconds on an object becoming unbusy. Since the wait itself does so
2853 * without holding struct_mutex the object may become re-busied before this
2854 * function completes. A similar but shorter * race condition exists in the busy
2858 i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
, struct drm_file
*file
)
2860 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2861 struct drm_i915_gem_wait
*args
= data
;
2862 struct drm_i915_gem_object
*obj
;
2863 struct drm_i915_gem_request
*req
;
2864 unsigned reset_counter
;
2867 if (args
->flags
!= 0)
2870 ret
= i915_mutex_lock_interruptible(dev
);
2874 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->bo_handle
));
2875 if (&obj
->base
== NULL
) {
2876 mutex_unlock(&dev
->struct_mutex
);
2880 /* Need to make sure the object gets inactive eventually. */
2881 ret
= i915_gem_object_flush_active(obj
);
2885 if (!obj
->active
|| !obj
->last_read_req
)
2888 req
= obj
->last_read_req
;
2890 /* Do this after OLR check to make sure we make forward progress polling
2891 * on this IOCTL with a timeout == 0 (like busy ioctl)
2893 if (args
->timeout_ns
== 0) {
2898 drm_gem_object_unreference(&obj
->base
);
2899 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
2900 i915_gem_request_reference(req
);
2901 mutex_unlock(&dev
->struct_mutex
);
2903 ret
= __i915_wait_request(req
, reset_counter
, true,
2904 args
->timeout_ns
> 0 ? &args
->timeout_ns
: NULL
,
2906 i915_gem_request_unreference__unlocked(req
);
2910 drm_gem_object_unreference(&obj
->base
);
2911 mutex_unlock(&dev
->struct_mutex
);
2916 * i915_gem_object_sync - sync an object to a ring.
2918 * @obj: object which may be in use on another ring.
2919 * @to: ring we wish to use the object on. May be NULL.
2921 * This code is meant to abstract object synchronization with the GPU.
2922 * Calling with NULL implies synchronizing the object with the CPU
2923 * rather than a particular GPU ring.
2925 * Returns 0 if successful, else propagates up the lower layer error.
2928 i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
2929 struct intel_engine_cs
*to
)
2931 struct intel_engine_cs
*from
;
2935 from
= i915_gem_request_get_ring(obj
->last_read_req
);
2937 if (from
== NULL
|| to
== from
)
2940 if (to
== NULL
|| !i915_semaphore_is_enabled(obj
->base
.dev
))
2941 return i915_gem_object_wait_rendering(obj
, false);
2943 idx
= intel_ring_sync_index(from
, to
);
2945 seqno
= i915_gem_request_get_seqno(obj
->last_read_req
);
2946 /* Optimization: Avoid semaphore sync when we are sure we already
2947 * waited for an object with higher seqno */
2948 if (seqno
<= from
->semaphore
.sync_seqno
[idx
])
2951 ret
= i915_gem_check_olr(obj
->last_read_req
);
2955 trace_i915_gem_ring_sync_to(from
, to
, obj
->last_read_req
);
2956 ret
= to
->semaphore
.sync_to(to
, from
, seqno
);
2958 /* We use last_read_req because sync_to()
2959 * might have just caused seqno wrap under
2962 from
->semaphore
.sync_seqno
[idx
] =
2963 i915_gem_request_get_seqno(obj
->last_read_req
);
2968 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object
*obj
)
2970 u32 old_write_domain
, old_read_domains
;
2972 /* Force a pagefault for domain tracking on next user access */
2973 i915_gem_release_mmap(obj
);
2975 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
) == 0)
2978 /* Wait for any direct GTT access to complete */
2981 old_read_domains
= obj
->base
.read_domains
;
2982 old_write_domain
= obj
->base
.write_domain
;
2984 obj
->base
.read_domains
&= ~I915_GEM_DOMAIN_GTT
;
2985 obj
->base
.write_domain
&= ~I915_GEM_DOMAIN_GTT
;
2987 trace_i915_gem_object_change_domain(obj
,
2992 int i915_vma_unbind(struct i915_vma
*vma
)
2994 struct drm_i915_gem_object
*obj
= vma
->obj
;
2995 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2998 if (list_empty(&vma
->vma_link
))
3001 if (!drm_mm_node_allocated(&vma
->node
)) {
3002 i915_gem_vma_destroy(vma
);
3009 BUG_ON(obj
->pages
== NULL
);
3011 ret
= i915_gem_object_finish_gpu(obj
);
3014 /* Continue on if we fail due to EIO, the GPU is hung so we
3015 * should be safe and we need to cleanup or else we might
3016 * cause memory corruption through use-after-free.
3019 if (i915_is_ggtt(vma
->vm
) &&
3020 vma
->ggtt_view
.type
== I915_GGTT_VIEW_NORMAL
) {
3021 i915_gem_object_finish_gtt(obj
);
3023 /* release the fence reg _after_ flushing */
3024 ret
= i915_gem_object_put_fence(obj
);
3029 trace_i915_vma_unbind(vma
);
3031 vma
->unbind_vma(vma
);
3033 list_del_init(&vma
->mm_list
);
3034 if (i915_is_ggtt(vma
->vm
)) {
3035 if (vma
->ggtt_view
.type
== I915_GGTT_VIEW_NORMAL
) {
3036 obj
->map_and_fenceable
= false;
3037 } else if (vma
->ggtt_view
.pages
) {
3038 sg_free_table(vma
->ggtt_view
.pages
);
3039 kfree(vma
->ggtt_view
.pages
);
3040 vma
->ggtt_view
.pages
= NULL
;
3044 drm_mm_remove_node(&vma
->node
);
3045 i915_gem_vma_destroy(vma
);
3047 /* Since the unbound list is global, only move to that list if
3048 * no more VMAs exist. */
3049 if (list_empty(&obj
->vma_list
)) {
3050 /* Throw away the active reference before
3051 * moving to the unbound list. */
3052 i915_gem_object_retire(obj
);
3054 i915_gem_gtt_finish_object(obj
);
3055 list_move_tail(&obj
->global_list
, &dev_priv
->mm
.unbound_list
);
3058 /* And finally now the object is completely decoupled from this vma,
3059 * we can drop its hold on the backing storage and allow it to be
3060 * reaped by the shrinker.
3062 i915_gem_object_unpin_pages(obj
);
3067 int i915_gpu_idle(struct drm_device
*dev
)
3069 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3070 struct intel_engine_cs
*ring
;
3073 /* Flush everything onto the inactive list. */
3074 for_each_ring(ring
, dev_priv
, i
) {
3075 if (!i915
.enable_execlists
) {
3076 ret
= i915_switch_context(ring
, ring
->default_context
);
3081 ret
= intel_ring_idle(ring
);
3089 static void i965_write_fence_reg(struct drm_device
*dev
, int reg
,
3090 struct drm_i915_gem_object
*obj
)
3092 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3094 int fence_pitch_shift
;
3096 if (INTEL_INFO(dev
)->gen
>= 6) {
3097 fence_reg
= FENCE_REG_SANDYBRIDGE_0
;
3098 fence_pitch_shift
= SANDYBRIDGE_FENCE_PITCH_SHIFT
;
3100 fence_reg
= FENCE_REG_965_0
;
3101 fence_pitch_shift
= I965_FENCE_PITCH_SHIFT
;
3104 fence_reg
+= reg
* 8;
3106 /* To w/a incoherency with non-atomic 64-bit register updates,
3107 * we split the 64-bit update into two 32-bit writes. In order
3108 * for a partial fence not to be evaluated between writes, we
3109 * precede the update with write to turn off the fence register,
3110 * and only enable the fence as the last step.
3112 * For extra levels of paranoia, we make sure each step lands
3113 * before applying the next step.
3115 I915_WRITE(fence_reg
, 0);
3116 POSTING_READ(fence_reg
);
3119 u32 size
= i915_gem_obj_ggtt_size(obj
);
3122 /* Adjust fence size to match tiled area */
3123 if (obj
->tiling_mode
!= I915_TILING_NONE
) {
3124 uint32_t row_size
= obj
->stride
*
3125 (obj
->tiling_mode
== I915_TILING_Y
? 32 : 8);
3126 size
= (size
/ row_size
) * row_size
;
3129 val
= (uint64_t)((i915_gem_obj_ggtt_offset(obj
) + size
- 4096) &
3131 val
|= i915_gem_obj_ggtt_offset(obj
) & 0xfffff000;
3132 val
|= (uint64_t)((obj
->stride
/ 128) - 1) << fence_pitch_shift
;
3133 if (obj
->tiling_mode
== I915_TILING_Y
)
3134 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
3135 val
|= I965_FENCE_REG_VALID
;
3137 I915_WRITE(fence_reg
+ 4, val
>> 32);
3138 POSTING_READ(fence_reg
+ 4);
3140 I915_WRITE(fence_reg
+ 0, val
);
3141 POSTING_READ(fence_reg
);
3143 I915_WRITE(fence_reg
+ 4, 0);
3144 POSTING_READ(fence_reg
+ 4);
3148 static void i915_write_fence_reg(struct drm_device
*dev
, int reg
,
3149 struct drm_i915_gem_object
*obj
)
3151 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3155 u32 size
= i915_gem_obj_ggtt_size(obj
);
3159 WARN((i915_gem_obj_ggtt_offset(obj
) & ~I915_FENCE_START_MASK
) ||
3160 (size
& -size
) != size
||
3161 (i915_gem_obj_ggtt_offset(obj
) & (size
- 1)),
3162 "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
3163 i915_gem_obj_ggtt_offset(obj
), obj
->map_and_fenceable
, size
);
3165 if (obj
->tiling_mode
== I915_TILING_Y
&& HAS_128_BYTE_Y_TILING(dev
))
3170 /* Note: pitch better be a power of two tile widths */
3171 pitch_val
= obj
->stride
/ tile_width
;
3172 pitch_val
= ffs(pitch_val
) - 1;
3174 val
= i915_gem_obj_ggtt_offset(obj
);
3175 if (obj
->tiling_mode
== I915_TILING_Y
)
3176 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
3177 val
|= I915_FENCE_SIZE_BITS(size
);
3178 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
3179 val
|= I830_FENCE_REG_VALID
;
3184 reg
= FENCE_REG_830_0
+ reg
* 4;
3186 reg
= FENCE_REG_945_8
+ (reg
- 8) * 4;
3188 I915_WRITE(reg
, val
);
3192 static void i830_write_fence_reg(struct drm_device
*dev
, int reg
,
3193 struct drm_i915_gem_object
*obj
)
3195 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3199 u32 size
= i915_gem_obj_ggtt_size(obj
);
3202 WARN((i915_gem_obj_ggtt_offset(obj
) & ~I830_FENCE_START_MASK
) ||
3203 (size
& -size
) != size
||
3204 (i915_gem_obj_ggtt_offset(obj
) & (size
- 1)),
3205 "object 0x%08lx not 512K or pot-size 0x%08x aligned\n",
3206 i915_gem_obj_ggtt_offset(obj
), size
);
3208 pitch_val
= obj
->stride
/ 128;
3209 pitch_val
= ffs(pitch_val
) - 1;
3211 val
= i915_gem_obj_ggtt_offset(obj
);
3212 if (obj
->tiling_mode
== I915_TILING_Y
)
3213 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
3214 val
|= I830_FENCE_SIZE_BITS(size
);
3215 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
3216 val
|= I830_FENCE_REG_VALID
;
3220 I915_WRITE(FENCE_REG_830_0
+ reg
* 4, val
);
3221 POSTING_READ(FENCE_REG_830_0
+ reg
* 4);
3224 inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object
*obj
)
3226 return obj
&& obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
;
3229 static void i915_gem_write_fence(struct drm_device
*dev
, int reg
,
3230 struct drm_i915_gem_object
*obj
)
3232 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3234 /* Ensure that all CPU reads are completed before installing a fence
3235 * and all writes before removing the fence.
3237 if (i915_gem_object_needs_mb(dev_priv
->fence_regs
[reg
].obj
))
3240 WARN(obj
&& (!obj
->stride
|| !obj
->tiling_mode
),
3241 "bogus fence setup with stride: 0x%x, tiling mode: %i\n",
3242 obj
->stride
, obj
->tiling_mode
);
3245 i830_write_fence_reg(dev
, reg
, obj
);
3246 else if (IS_GEN3(dev
))
3247 i915_write_fence_reg(dev
, reg
, obj
);
3248 else if (INTEL_INFO(dev
)->gen
>= 4)
3249 i965_write_fence_reg(dev
, reg
, obj
);
3251 /* And similarly be paranoid that no direct access to this region
3252 * is reordered to before the fence is installed.
3254 if (i915_gem_object_needs_mb(obj
))
3258 static inline int fence_number(struct drm_i915_private
*dev_priv
,
3259 struct drm_i915_fence_reg
*fence
)
3261 return fence
- dev_priv
->fence_regs
;
3264 static void i915_gem_object_update_fence(struct drm_i915_gem_object
*obj
,
3265 struct drm_i915_fence_reg
*fence
,
3268 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
3269 int reg
= fence_number(dev_priv
, fence
);
3271 i915_gem_write_fence(obj
->base
.dev
, reg
, enable
? obj
: NULL
);
3274 obj
->fence_reg
= reg
;
3276 list_move_tail(&fence
->lru_list
, &dev_priv
->mm
.fence_list
);
3278 obj
->fence_reg
= I915_FENCE_REG_NONE
;
3280 list_del_init(&fence
->lru_list
);
3282 obj
->fence_dirty
= false;
3286 i915_gem_object_wait_fence(struct drm_i915_gem_object
*obj
)
3288 if (obj
->last_fenced_req
) {
3289 int ret
= i915_wait_request(obj
->last_fenced_req
);
3293 i915_gem_request_assign(&obj
->last_fenced_req
, NULL
);
3300 i915_gem_object_put_fence(struct drm_i915_gem_object
*obj
)
3302 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
3303 struct drm_i915_fence_reg
*fence
;
3306 ret
= i915_gem_object_wait_fence(obj
);
3310 if (obj
->fence_reg
== I915_FENCE_REG_NONE
)
3313 fence
= &dev_priv
->fence_regs
[obj
->fence_reg
];
3315 if (WARN_ON(fence
->pin_count
))
3318 i915_gem_object_fence_lost(obj
);
3319 i915_gem_object_update_fence(obj
, fence
, false);
3324 static struct drm_i915_fence_reg
*
3325 i915_find_fence_reg(struct drm_device
*dev
)
3327 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3328 struct drm_i915_fence_reg
*reg
, *avail
;
3331 /* First try to find a free reg */
3333 for (i
= dev_priv
->fence_reg_start
; i
< dev_priv
->num_fence_regs
; i
++) {
3334 reg
= &dev_priv
->fence_regs
[i
];
3338 if (!reg
->pin_count
)
3345 /* None available, try to steal one or wait for a user to finish */
3346 list_for_each_entry(reg
, &dev_priv
->mm
.fence_list
, lru_list
) {
3354 /* Wait for completion of pending flips which consume fences */
3355 if (intel_has_pending_fb_unpin(dev
))
3356 return ERR_PTR(-EAGAIN
);
3358 return ERR_PTR(-EDEADLK
);
3362 * i915_gem_object_get_fence - set up fencing for an object
3363 * @obj: object to map through a fence reg
3365 * When mapping objects through the GTT, userspace wants to be able to write
3366 * to them without having to worry about swizzling if the object is tiled.
3367 * This function walks the fence regs looking for a free one for @obj,
3368 * stealing one if it can't find any.
3370 * It then sets up the reg based on the object's properties: address, pitch
3371 * and tiling format.
3373 * For an untiled surface, this removes any existing fence.
3376 i915_gem_object_get_fence(struct drm_i915_gem_object
*obj
)
3378 struct drm_device
*dev
= obj
->base
.dev
;
3379 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3380 bool enable
= obj
->tiling_mode
!= I915_TILING_NONE
;
3381 struct drm_i915_fence_reg
*reg
;
3384 /* Have we updated the tiling parameters upon the object and so
3385 * will need to serialise the write to the associated fence register?
3387 if (obj
->fence_dirty
) {
3388 ret
= i915_gem_object_wait_fence(obj
);
3393 /* Just update our place in the LRU if our fence is getting reused. */
3394 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
3395 reg
= &dev_priv
->fence_regs
[obj
->fence_reg
];
3396 if (!obj
->fence_dirty
) {
3397 list_move_tail(®
->lru_list
,
3398 &dev_priv
->mm
.fence_list
);
3401 } else if (enable
) {
3402 if (WARN_ON(!obj
->map_and_fenceable
))
3405 reg
= i915_find_fence_reg(dev
);
3407 return PTR_ERR(reg
);
3410 struct drm_i915_gem_object
*old
= reg
->obj
;
3412 ret
= i915_gem_object_wait_fence(old
);
3416 i915_gem_object_fence_lost(old
);
3421 i915_gem_object_update_fence(obj
, reg
, enable
);
3426 static bool i915_gem_valid_gtt_space(struct i915_vma
*vma
,
3427 unsigned long cache_level
)
3429 struct drm_mm_node
*gtt_space
= &vma
->node
;
3430 struct drm_mm_node
*other
;
3433 * On some machines we have to be careful when putting differing types
3434 * of snoopable memory together to avoid the prefetcher crossing memory
3435 * domains and dying. During vm initialisation, we decide whether or not
3436 * these constraints apply and set the drm_mm.color_adjust
3439 if (vma
->vm
->mm
.color_adjust
== NULL
)
3442 if (!drm_mm_node_allocated(gtt_space
))
3445 if (list_empty(>t_space
->node_list
))
3448 other
= list_entry(gtt_space
->node_list
.prev
, struct drm_mm_node
, node_list
);
3449 if (other
->allocated
&& !other
->hole_follows
&& other
->color
!= cache_level
)
3452 other
= list_entry(gtt_space
->node_list
.next
, struct drm_mm_node
, node_list
);
3453 if (other
->allocated
&& !gtt_space
->hole_follows
&& other
->color
!= cache_level
)
3460 * Finds free space in the GTT aperture and binds the object there.
3462 static struct i915_vma
*
3463 i915_gem_object_bind_to_vm(struct drm_i915_gem_object
*obj
,
3464 struct i915_address_space
*vm
,
3465 const struct i915_ggtt_view
*ggtt_view
,
3469 struct drm_device
*dev
= obj
->base
.dev
;
3470 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3471 u32 size
, fence_size
, fence_alignment
, unfenced_alignment
;
3472 unsigned long start
=
3473 flags
& PIN_OFFSET_BIAS
? flags
& PIN_OFFSET_MASK
: 0;
3475 flags
& PIN_MAPPABLE
? dev_priv
->gtt
.mappable_end
: vm
->total
;
3476 struct i915_vma
*vma
;
3479 if(WARN_ON(i915_is_ggtt(vm
) != !!ggtt_view
))
3480 return ERR_PTR(-EINVAL
);
3482 fence_size
= i915_gem_get_gtt_size(dev
,
3485 fence_alignment
= i915_gem_get_gtt_alignment(dev
,
3487 obj
->tiling_mode
, true);
3488 unfenced_alignment
=
3489 i915_gem_get_gtt_alignment(dev
,
3491 obj
->tiling_mode
, false);
3494 alignment
= flags
& PIN_MAPPABLE
? fence_alignment
:
3496 if (flags
& PIN_MAPPABLE
&& alignment
& (fence_alignment
- 1)) {
3497 DRM_DEBUG("Invalid object alignment requested %u\n", alignment
);
3498 return ERR_PTR(-EINVAL
);
3501 size
= flags
& PIN_MAPPABLE
? fence_size
: obj
->base
.size
;
3503 /* If the object is bigger than the entire aperture, reject it early
3504 * before evicting everything in a vain attempt to find space.
3506 if (obj
->base
.size
> end
) {
3507 DRM_DEBUG("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%lu\n",
3509 flags
& PIN_MAPPABLE
? "mappable" : "total",
3511 return ERR_PTR(-E2BIG
);
3514 ret
= i915_gem_object_get_pages(obj
);
3516 return ERR_PTR(ret
);
3518 i915_gem_object_pin_pages(obj
);
3520 vma
= ggtt_view
? i915_gem_obj_lookup_or_create_ggtt_vma(obj
, ggtt_view
) :
3521 i915_gem_obj_lookup_or_create_vma(obj
, vm
);
3527 ret
= drm_mm_insert_node_in_range_generic(&vm
->mm
, &vma
->node
,
3531 DRM_MM_SEARCH_DEFAULT
,
3532 DRM_MM_CREATE_DEFAULT
);
3534 ret
= i915_gem_evict_something(dev
, vm
, size
, alignment
,
3543 if (WARN_ON(!i915_gem_valid_gtt_space(vma
, obj
->cache_level
))) {
3545 goto err_remove_node
;
3548 ret
= i915_gem_gtt_prepare_object(obj
);
3550 goto err_remove_node
;
3552 /* allocate before insert / bind */
3553 if (vma
->vm
->allocate_va_range
) {
3554 trace_i915_va_alloc(vma
->vm
, vma
->node
.start
, vma
->node
.size
,
3555 VM_TO_TRACE_NAME(vma
->vm
));
3556 ret
= vma
->vm
->allocate_va_range(vma
->vm
,
3560 goto err_remove_node
;
3563 trace_i915_vma_bind(vma
, flags
);
3564 ret
= i915_vma_bind(vma
, obj
->cache_level
,
3565 flags
& PIN_GLOBAL
? GLOBAL_BIND
: 0);
3567 goto err_finish_gtt
;
3569 list_move_tail(&obj
->global_list
, &dev_priv
->mm
.bound_list
);
3570 list_add_tail(&vma
->mm_list
, &vm
->inactive_list
);
3575 i915_gem_gtt_finish_object(obj
);
3577 drm_mm_remove_node(&vma
->node
);
3579 i915_gem_vma_destroy(vma
);
3582 i915_gem_object_unpin_pages(obj
);
3587 i915_gem_clflush_object(struct drm_i915_gem_object
*obj
,
3590 /* If we don't have a page list set up, then we're not pinned
3591 * to GPU, and we can ignore the cache flush because it'll happen
3592 * again at bind time.
3594 if (obj
->pages
== NULL
)
3598 * Stolen memory is always coherent with the GPU as it is explicitly
3599 * marked as wc by the system, or the system is cache-coherent.
3601 if (obj
->stolen
|| obj
->phys_handle
)
3604 /* If the GPU is snooping the contents of the CPU cache,
3605 * we do not need to manually clear the CPU cache lines. However,
3606 * the caches are only snooped when the render cache is
3607 * flushed/invalidated. As we always have to emit invalidations
3608 * and flushes when moving into and out of the RENDER domain, correct
3609 * snooping behaviour occurs naturally as the result of our domain
3612 if (!force
&& cpu_cache_is_coherent(obj
->base
.dev
, obj
->cache_level
)) {
3613 obj
->cache_dirty
= true;
3617 trace_i915_gem_object_clflush(obj
);
3618 drm_clflush_sg(obj
->pages
);
3619 obj
->cache_dirty
= false;
3624 /** Flushes the GTT write domain for the object if it's dirty. */
3626 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
)
3628 uint32_t old_write_domain
;
3630 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_GTT
)
3633 /* No actual flushing is required for the GTT write domain. Writes
3634 * to it immediately go to main memory as far as we know, so there's
3635 * no chipset flush. It also doesn't land in render cache.
3637 * However, we do have to enforce the order so that all writes through
3638 * the GTT land before any writes to the device, such as updates to
3643 old_write_domain
= obj
->base
.write_domain
;
3644 obj
->base
.write_domain
= 0;
3646 intel_fb_obj_flush(obj
, false);
3648 trace_i915_gem_object_change_domain(obj
,
3649 obj
->base
.read_domains
,
3653 /** Flushes the CPU write domain for the object if it's dirty. */
3655 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
)
3657 uint32_t old_write_domain
;
3659 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
)
3662 if (i915_gem_clflush_object(obj
, obj
->pin_display
))
3663 i915_gem_chipset_flush(obj
->base
.dev
);
3665 old_write_domain
= obj
->base
.write_domain
;
3666 obj
->base
.write_domain
= 0;
3668 intel_fb_obj_flush(obj
, false);
3670 trace_i915_gem_object_change_domain(obj
,
3671 obj
->base
.read_domains
,
3676 * Moves a single object to the GTT read, and possibly write domain.
3678 * This function returns when the move is complete, including waiting on
3682 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
, bool write
)
3684 uint32_t old_write_domain
, old_read_domains
;
3685 struct i915_vma
*vma
;
3688 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_GTT
)
3691 ret
= i915_gem_object_wait_rendering(obj
, !write
);
3695 i915_gem_object_retire(obj
);
3697 /* Flush and acquire obj->pages so that we are coherent through
3698 * direct access in memory with previous cached writes through
3699 * shmemfs and that our cache domain tracking remains valid.
3700 * For example, if the obj->filp was moved to swap without us
3701 * being notified and releasing the pages, we would mistakenly
3702 * continue to assume that the obj remained out of the CPU cached
3705 ret
= i915_gem_object_get_pages(obj
);
3709 i915_gem_object_flush_cpu_write_domain(obj
);
3711 /* Serialise direct access to this object with the barriers for
3712 * coherent writes from the GPU, by effectively invalidating the
3713 * GTT domain upon first access.
3715 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
) == 0)
3718 old_write_domain
= obj
->base
.write_domain
;
3719 old_read_domains
= obj
->base
.read_domains
;
3721 /* It should now be out of any other write domains, and we can update
3722 * the domain values for our changes.
3724 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
3725 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
3727 obj
->base
.read_domains
= I915_GEM_DOMAIN_GTT
;
3728 obj
->base
.write_domain
= I915_GEM_DOMAIN_GTT
;
3733 intel_fb_obj_invalidate(obj
, NULL
, ORIGIN_GTT
);
3735 trace_i915_gem_object_change_domain(obj
,
3739 /* And bump the LRU for this access */
3740 vma
= i915_gem_obj_to_ggtt(obj
);
3741 if (vma
&& drm_mm_node_allocated(&vma
->node
) && !obj
->active
)
3742 list_move_tail(&vma
->mm_list
,
3743 &to_i915(obj
->base
.dev
)->gtt
.base
.inactive_list
);
3748 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
3749 enum i915_cache_level cache_level
)
3751 struct drm_device
*dev
= obj
->base
.dev
;
3752 struct i915_vma
*vma
, *next
;
3755 if (obj
->cache_level
== cache_level
)
3758 if (i915_gem_obj_is_pinned(obj
)) {
3759 DRM_DEBUG("can not change the cache level of pinned objects\n");
3763 list_for_each_entry_safe(vma
, next
, &obj
->vma_list
, vma_link
) {
3764 if (!i915_gem_valid_gtt_space(vma
, cache_level
)) {
3765 ret
= i915_vma_unbind(vma
);
3771 if (i915_gem_obj_bound_any(obj
)) {
3772 ret
= i915_gem_object_finish_gpu(obj
);
3776 i915_gem_object_finish_gtt(obj
);
3778 /* Before SandyBridge, you could not use tiling or fence
3779 * registers with snooped memory, so relinquish any fences
3780 * currently pointing to our region in the aperture.
3782 if (INTEL_INFO(dev
)->gen
< 6) {
3783 ret
= i915_gem_object_put_fence(obj
);
3788 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
3789 if (drm_mm_node_allocated(&vma
->node
)) {
3790 ret
= i915_vma_bind(vma
, cache_level
,
3791 vma
->bound
& GLOBAL_BIND
);
3797 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
3798 vma
->node
.color
= cache_level
;
3799 obj
->cache_level
= cache_level
;
3801 if (obj
->cache_dirty
&&
3802 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
&&
3803 cpu_write_needs_clflush(obj
)) {
3804 if (i915_gem_clflush_object(obj
, true))
3805 i915_gem_chipset_flush(obj
->base
.dev
);
3811 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
3812 struct drm_file
*file
)
3814 struct drm_i915_gem_caching
*args
= data
;
3815 struct drm_i915_gem_object
*obj
;
3818 ret
= i915_mutex_lock_interruptible(dev
);
3822 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3823 if (&obj
->base
== NULL
) {
3828 switch (obj
->cache_level
) {
3829 case I915_CACHE_LLC
:
3830 case I915_CACHE_L3_LLC
:
3831 args
->caching
= I915_CACHING_CACHED
;
3835 args
->caching
= I915_CACHING_DISPLAY
;
3839 args
->caching
= I915_CACHING_NONE
;
3843 drm_gem_object_unreference(&obj
->base
);
3845 mutex_unlock(&dev
->struct_mutex
);
3849 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
3850 struct drm_file
*file
)
3852 struct drm_i915_gem_caching
*args
= data
;
3853 struct drm_i915_gem_object
*obj
;
3854 enum i915_cache_level level
;
3857 switch (args
->caching
) {
3858 case I915_CACHING_NONE
:
3859 level
= I915_CACHE_NONE
;
3861 case I915_CACHING_CACHED
:
3862 level
= I915_CACHE_LLC
;
3864 case I915_CACHING_DISPLAY
:
3865 level
= HAS_WT(dev
) ? I915_CACHE_WT
: I915_CACHE_NONE
;
3871 ret
= i915_mutex_lock_interruptible(dev
);
3875 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3876 if (&obj
->base
== NULL
) {
3881 ret
= i915_gem_object_set_cache_level(obj
, level
);
3883 drm_gem_object_unreference(&obj
->base
);
3885 mutex_unlock(&dev
->struct_mutex
);
3889 static bool is_pin_display(struct drm_i915_gem_object
*obj
)
3891 struct i915_vma
*vma
;
3893 vma
= i915_gem_obj_to_ggtt(obj
);
3897 /* There are 2 sources that pin objects:
3898 * 1. The display engine (scanouts, sprites, cursors);
3899 * 2. Reservations for execbuffer;
3901 * We can ignore reservations as we hold the struct_mutex and
3902 * are only called outside of the reservation path.
3904 return vma
->pin_count
;
3908 * Prepare buffer for display plane (scanout, cursors, etc).
3909 * Can be called from an uninterruptible phase (modesetting) and allows
3910 * any flushes to be pipelined (for pageflips).
3913 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
3915 struct intel_engine_cs
*pipelined
,
3916 const struct i915_ggtt_view
*view
)
3918 u32 old_read_domains
, old_write_domain
;
3919 bool was_pin_display
;
3922 if (pipelined
!= i915_gem_request_get_ring(obj
->last_read_req
)) {
3923 ret
= i915_gem_object_sync(obj
, pipelined
);
3928 /* Mark the pin_display early so that we account for the
3929 * display coherency whilst setting up the cache domains.
3931 was_pin_display
= obj
->pin_display
;
3932 obj
->pin_display
= true;
3934 /* The display engine is not coherent with the LLC cache on gen6. As
3935 * a result, we make sure that the pinning that is about to occur is
3936 * done with uncached PTEs. This is lowest common denominator for all
3939 * However for gen6+, we could do better by using the GFDT bit instead
3940 * of uncaching, which would allow us to flush all the LLC-cached data
3941 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3943 ret
= i915_gem_object_set_cache_level(obj
,
3944 HAS_WT(obj
->base
.dev
) ? I915_CACHE_WT
: I915_CACHE_NONE
);
3946 goto err_unpin_display
;
3948 /* As the user may map the buffer once pinned in the display plane
3949 * (e.g. libkms for the bootup splash), we have to ensure that we
3950 * always use map_and_fenceable for all scanout buffers.
3952 ret
= i915_gem_object_ggtt_pin(obj
, view
, alignment
,
3953 view
->type
== I915_GGTT_VIEW_NORMAL
?
3956 goto err_unpin_display
;
3958 i915_gem_object_flush_cpu_write_domain(obj
);
3960 old_write_domain
= obj
->base
.write_domain
;
3961 old_read_domains
= obj
->base
.read_domains
;
3963 /* It should now be out of any other write domains, and we can update
3964 * the domain values for our changes.
3966 obj
->base
.write_domain
= 0;
3967 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
3969 trace_i915_gem_object_change_domain(obj
,
3976 WARN_ON(was_pin_display
!= is_pin_display(obj
));
3977 obj
->pin_display
= was_pin_display
;
3982 i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object
*obj
,
3983 const struct i915_ggtt_view
*view
)
3985 i915_gem_object_ggtt_unpin_view(obj
, view
);
3987 obj
->pin_display
= is_pin_display(obj
);
3991 i915_gem_object_finish_gpu(struct drm_i915_gem_object
*obj
)
3995 if ((obj
->base
.read_domains
& I915_GEM_GPU_DOMAINS
) == 0)
3998 ret
= i915_gem_object_wait_rendering(obj
, false);
4002 /* Ensure that we invalidate the GPU's caches and TLBs. */
4003 obj
->base
.read_domains
&= ~I915_GEM_GPU_DOMAINS
;
4008 * Moves a single object to the CPU read, and possibly write domain.
4010 * This function returns when the move is complete, including waiting on
4014 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
)
4016 uint32_t old_write_domain
, old_read_domains
;
4019 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_CPU
)
4022 ret
= i915_gem_object_wait_rendering(obj
, !write
);
4026 i915_gem_object_retire(obj
);
4027 i915_gem_object_flush_gtt_write_domain(obj
);
4029 old_write_domain
= obj
->base
.write_domain
;
4030 old_read_domains
= obj
->base
.read_domains
;
4032 /* Flush the CPU cache if it's still invalid. */
4033 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) == 0) {
4034 i915_gem_clflush_object(obj
, false);
4036 obj
->base
.read_domains
|= I915_GEM_DOMAIN_CPU
;
4039 /* It should now be out of any other write domains, and we can update
4040 * the domain values for our changes.
4042 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
4044 /* If we're writing through the CPU, then the GPU read domains will
4045 * need to be invalidated at next use.
4048 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
4049 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
4053 intel_fb_obj_invalidate(obj
, NULL
, ORIGIN_CPU
);
4055 trace_i915_gem_object_change_domain(obj
,
4062 /* Throttle our rendering by waiting until the ring has completed our requests
4063 * emitted over 20 msec ago.
4065 * Note that if we were to use the current jiffies each time around the loop,
4066 * we wouldn't escape the function with any frames outstanding if the time to
4067 * render a frame was over 20ms.
4069 * This should get us reasonable parallelism between CPU and GPU but also
4070 * relatively low latency when blocking on a particular request to finish.
4073 i915_gem_ring_throttle(struct drm_device
*dev
, struct drm_file
*file
)
4075 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4076 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
4077 unsigned long recent_enough
= jiffies
- msecs_to_jiffies(20);
4078 struct drm_i915_gem_request
*request
, *target
= NULL
;
4079 unsigned reset_counter
;
4082 ret
= i915_gem_wait_for_error(&dev_priv
->gpu_error
);
4086 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, false);
4090 spin_lock(&file_priv
->mm
.lock
);
4091 list_for_each_entry(request
, &file_priv
->mm
.request_list
, client_list
) {
4092 if (time_after_eq(request
->emitted_jiffies
, recent_enough
))
4097 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
4099 i915_gem_request_reference(target
);
4100 spin_unlock(&file_priv
->mm
.lock
);
4105 ret
= __i915_wait_request(target
, reset_counter
, true, NULL
, NULL
);
4107 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, 0);
4109 i915_gem_request_unreference__unlocked(target
);
4115 i915_vma_misplaced(struct i915_vma
*vma
, uint32_t alignment
, uint64_t flags
)
4117 struct drm_i915_gem_object
*obj
= vma
->obj
;
4120 vma
->node
.start
& (alignment
- 1))
4123 if (flags
& PIN_MAPPABLE
&& !obj
->map_and_fenceable
)
4126 if (flags
& PIN_OFFSET_BIAS
&&
4127 vma
->node
.start
< (flags
& PIN_OFFSET_MASK
))
4134 i915_gem_object_do_pin(struct drm_i915_gem_object
*obj
,
4135 struct i915_address_space
*vm
,
4136 const struct i915_ggtt_view
*ggtt_view
,
4140 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
4141 struct i915_vma
*vma
;
4145 if (WARN_ON(vm
== &dev_priv
->mm
.aliasing_ppgtt
->base
))
4148 if (WARN_ON(flags
& (PIN_GLOBAL
| PIN_MAPPABLE
) && !i915_is_ggtt(vm
)))
4151 if (WARN_ON((flags
& (PIN_MAPPABLE
| PIN_GLOBAL
)) == PIN_MAPPABLE
))
4154 if (WARN_ON(i915_is_ggtt(vm
) != !!ggtt_view
))
4157 vma
= ggtt_view
? i915_gem_obj_to_ggtt_view(obj
, ggtt_view
) :
4158 i915_gem_obj_to_vma(obj
, vm
);
4161 return PTR_ERR(vma
);
4164 if (WARN_ON(vma
->pin_count
== DRM_I915_GEM_OBJECT_MAX_PIN_COUNT
))
4167 if (i915_vma_misplaced(vma
, alignment
, flags
)) {
4168 unsigned long offset
;
4169 offset
= ggtt_view
? i915_gem_obj_ggtt_offset_view(obj
, ggtt_view
) :
4170 i915_gem_obj_offset(obj
, vm
);
4171 WARN(vma
->pin_count
,
4172 "bo is already pinned in %s with incorrect alignment:"
4173 " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d,"
4174 " obj->map_and_fenceable=%d\n",
4175 ggtt_view
? "ggtt" : "ppgtt",
4178 !!(flags
& PIN_MAPPABLE
),
4179 obj
->map_and_fenceable
);
4180 ret
= i915_vma_unbind(vma
);
4188 bound
= vma
? vma
->bound
: 0;
4189 if (vma
== NULL
|| !drm_mm_node_allocated(&vma
->node
)) {
4190 /* In true PPGTT, bind has possibly changed PDEs, which
4191 * means we must do a context switch before the GPU can
4192 * accurately read some of the VMAs.
4194 vma
= i915_gem_object_bind_to_vm(obj
, vm
, ggtt_view
, alignment
,
4197 return PTR_ERR(vma
);
4200 if (flags
& PIN_GLOBAL
&& !(vma
->bound
& GLOBAL_BIND
)) {
4201 ret
= i915_vma_bind(vma
, obj
->cache_level
, GLOBAL_BIND
);
4206 if ((bound
^ vma
->bound
) & GLOBAL_BIND
) {
4207 bool mappable
, fenceable
;
4208 u32 fence_size
, fence_alignment
;
4210 fence_size
= i915_gem_get_gtt_size(obj
->base
.dev
,
4213 fence_alignment
= i915_gem_get_gtt_alignment(obj
->base
.dev
,
4218 fenceable
= (vma
->node
.size
== fence_size
&&
4219 (vma
->node
.start
& (fence_alignment
- 1)) == 0);
4221 mappable
= (vma
->node
.start
+ fence_size
<=
4222 dev_priv
->gtt
.mappable_end
);
4224 obj
->map_and_fenceable
= mappable
&& fenceable
;
4227 WARN_ON(flags
& PIN_MAPPABLE
&& !obj
->map_and_fenceable
);
4230 if (flags
& PIN_MAPPABLE
)
4231 obj
->pin_mappable
|= true;
4237 i915_gem_object_pin(struct drm_i915_gem_object
*obj
,
4238 struct i915_address_space
*vm
,
4242 return i915_gem_object_do_pin(obj
, vm
,
4243 i915_is_ggtt(vm
) ? &i915_ggtt_view_normal
: NULL
,
4248 i915_gem_object_ggtt_pin(struct drm_i915_gem_object
*obj
,
4249 const struct i915_ggtt_view
*view
,
4253 if (WARN_ONCE(!view
, "no view specified"))
4256 return i915_gem_object_do_pin(obj
, i915_obj_to_ggtt(obj
), view
,
4257 alignment
, flags
| PIN_GLOBAL
);
4261 i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object
*obj
,
4262 const struct i915_ggtt_view
*view
)
4264 struct i915_vma
*vma
= i915_gem_obj_to_ggtt_view(obj
, view
);
4267 WARN_ON(vma
->pin_count
== 0);
4268 WARN_ON(!i915_gem_obj_ggtt_bound_view(obj
, view
));
4270 if (--vma
->pin_count
== 0 && view
->type
== I915_GGTT_VIEW_NORMAL
)
4271 obj
->pin_mappable
= false;
4275 i915_gem_object_pin_fence(struct drm_i915_gem_object
*obj
)
4277 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
4278 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
4279 struct i915_vma
*ggtt_vma
= i915_gem_obj_to_ggtt(obj
);
4281 WARN_ON(!ggtt_vma
||
4282 dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
>
4283 ggtt_vma
->pin_count
);
4284 dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
++;
4291 i915_gem_object_unpin_fence(struct drm_i915_gem_object
*obj
)
4293 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
4294 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
4295 WARN_ON(dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
<= 0);
4296 dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
--;
4301 i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
4302 struct drm_file
*file
)
4304 struct drm_i915_gem_busy
*args
= data
;
4305 struct drm_i915_gem_object
*obj
;
4308 ret
= i915_mutex_lock_interruptible(dev
);
4312 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
4313 if (&obj
->base
== NULL
) {
4318 /* Count all active objects as busy, even if they are currently not used
4319 * by the gpu. Users of this interface expect objects to eventually
4320 * become non-busy without any further actions, therefore emit any
4321 * necessary flushes here.
4323 ret
= i915_gem_object_flush_active(obj
);
4325 args
->busy
= obj
->active
;
4326 if (obj
->last_read_req
) {
4327 struct intel_engine_cs
*ring
;
4328 BUILD_BUG_ON(I915_NUM_RINGS
> 16);
4329 ring
= i915_gem_request_get_ring(obj
->last_read_req
);
4330 args
->busy
|= intel_ring_flag(ring
) << 16;
4333 drm_gem_object_unreference(&obj
->base
);
4335 mutex_unlock(&dev
->struct_mutex
);
4340 i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
4341 struct drm_file
*file_priv
)
4343 return i915_gem_ring_throttle(dev
, file_priv
);
4347 i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
4348 struct drm_file
*file_priv
)
4350 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4351 struct drm_i915_gem_madvise
*args
= data
;
4352 struct drm_i915_gem_object
*obj
;
4355 switch (args
->madv
) {
4356 case I915_MADV_DONTNEED
:
4357 case I915_MADV_WILLNEED
:
4363 ret
= i915_mutex_lock_interruptible(dev
);
4367 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file_priv
, args
->handle
));
4368 if (&obj
->base
== NULL
) {
4373 if (i915_gem_obj_is_pinned(obj
)) {
4379 obj
->tiling_mode
!= I915_TILING_NONE
&&
4380 dev_priv
->quirks
& QUIRK_PIN_SWIZZLED_PAGES
) {
4381 if (obj
->madv
== I915_MADV_WILLNEED
)
4382 i915_gem_object_unpin_pages(obj
);
4383 if (args
->madv
== I915_MADV_WILLNEED
)
4384 i915_gem_object_pin_pages(obj
);
4387 if (obj
->madv
!= __I915_MADV_PURGED
)
4388 obj
->madv
= args
->madv
;
4390 /* if the object is no longer attached, discard its backing storage */
4391 if (obj
->madv
== I915_MADV_DONTNEED
&& obj
->pages
== NULL
)
4392 i915_gem_object_truncate(obj
);
4394 args
->retained
= obj
->madv
!= __I915_MADV_PURGED
;
4397 drm_gem_object_unreference(&obj
->base
);
4399 mutex_unlock(&dev
->struct_mutex
);
4403 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
4404 const struct drm_i915_gem_object_ops
*ops
)
4406 INIT_LIST_HEAD(&obj
->global_list
);
4407 INIT_LIST_HEAD(&obj
->ring_list
);
4408 INIT_LIST_HEAD(&obj
->obj_exec_link
);
4409 INIT_LIST_HEAD(&obj
->vma_list
);
4410 INIT_LIST_HEAD(&obj
->batch_pool_list
);
4414 obj
->fence_reg
= I915_FENCE_REG_NONE
;
4415 obj
->madv
= I915_MADV_WILLNEED
;
4417 i915_gem_info_add_obj(obj
->base
.dev
->dev_private
, obj
->base
.size
);
4420 static const struct drm_i915_gem_object_ops i915_gem_object_ops
= {
4421 .get_pages
= i915_gem_object_get_pages_gtt
,
4422 .put_pages
= i915_gem_object_put_pages_gtt
,
4425 struct drm_i915_gem_object
*i915_gem_alloc_object(struct drm_device
*dev
,
4428 struct drm_i915_gem_object
*obj
;
4429 struct address_space
*mapping
;
4432 obj
= i915_gem_object_alloc(dev
);
4436 if (drm_gem_object_init(dev
, &obj
->base
, size
) != 0) {
4437 i915_gem_object_free(obj
);
4441 mask
= GFP_HIGHUSER
| __GFP_RECLAIMABLE
;
4442 if (IS_CRESTLINE(dev
) || IS_BROADWATER(dev
)) {
4443 /* 965gm cannot relocate objects above 4GiB. */
4444 mask
&= ~__GFP_HIGHMEM
;
4445 mask
|= __GFP_DMA32
;
4448 mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
4449 mapping_set_gfp_mask(mapping
, mask
);
4451 i915_gem_object_init(obj
, &i915_gem_object_ops
);
4453 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
4454 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
4457 /* On some devices, we can have the GPU use the LLC (the CPU
4458 * cache) for about a 10% performance improvement
4459 * compared to uncached. Graphics requests other than
4460 * display scanout are coherent with the CPU in
4461 * accessing this cache. This means in this mode we
4462 * don't need to clflush on the CPU side, and on the
4463 * GPU side we only need to flush internal caches to
4464 * get data visible to the CPU.
4466 * However, we maintain the display planes as UC, and so
4467 * need to rebind when first used as such.
4469 obj
->cache_level
= I915_CACHE_LLC
;
4471 obj
->cache_level
= I915_CACHE_NONE
;
4473 trace_i915_gem_object_create(obj
);
4478 static bool discard_backing_storage(struct drm_i915_gem_object
*obj
)
4480 /* If we are the last user of the backing storage (be it shmemfs
4481 * pages or stolen etc), we know that the pages are going to be
4482 * immediately released. In this case, we can then skip copying
4483 * back the contents from the GPU.
4486 if (obj
->madv
!= I915_MADV_WILLNEED
)
4489 if (obj
->base
.filp
== NULL
)
4492 /* At first glance, this looks racy, but then again so would be
4493 * userspace racing mmap against close. However, the first external
4494 * reference to the filp can only be obtained through the
4495 * i915_gem_mmap_ioctl() which safeguards us against the user
4496 * acquiring such a reference whilst we are in the middle of
4497 * freeing the object.
4499 return atomic_long_read(&obj
->base
.filp
->f_count
) == 1;
4502 void i915_gem_free_object(struct drm_gem_object
*gem_obj
)
4504 struct drm_i915_gem_object
*obj
= to_intel_bo(gem_obj
);
4505 struct drm_device
*dev
= obj
->base
.dev
;
4506 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4507 struct i915_vma
*vma
, *next
;
4509 intel_runtime_pm_get(dev_priv
);
4511 trace_i915_gem_object_destroy(obj
);
4513 list_for_each_entry_safe(vma
, next
, &obj
->vma_list
, vma_link
) {
4517 ret
= i915_vma_unbind(vma
);
4518 if (WARN_ON(ret
== -ERESTARTSYS
)) {
4519 bool was_interruptible
;
4521 was_interruptible
= dev_priv
->mm
.interruptible
;
4522 dev_priv
->mm
.interruptible
= false;
4524 WARN_ON(i915_vma_unbind(vma
));
4526 dev_priv
->mm
.interruptible
= was_interruptible
;
4530 /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
4531 * before progressing. */
4533 i915_gem_object_unpin_pages(obj
);
4535 WARN_ON(obj
->frontbuffer_bits
);
4537 if (obj
->pages
&& obj
->madv
== I915_MADV_WILLNEED
&&
4538 dev_priv
->quirks
& QUIRK_PIN_SWIZZLED_PAGES
&&
4539 obj
->tiling_mode
!= I915_TILING_NONE
)
4540 i915_gem_object_unpin_pages(obj
);
4542 if (WARN_ON(obj
->pages_pin_count
))
4543 obj
->pages_pin_count
= 0;
4544 if (discard_backing_storage(obj
))
4545 obj
->madv
= I915_MADV_DONTNEED
;
4546 i915_gem_object_put_pages(obj
);
4547 i915_gem_object_free_mmap_offset(obj
);
4551 if (obj
->base
.import_attach
)
4552 drm_prime_gem_destroy(&obj
->base
, NULL
);
4554 if (obj
->ops
->release
)
4555 obj
->ops
->release(obj
);
4557 drm_gem_object_release(&obj
->base
);
4558 i915_gem_info_remove_obj(dev_priv
, obj
->base
.size
);
4561 i915_gem_object_free(obj
);
4563 intel_runtime_pm_put(dev_priv
);
4566 struct i915_vma
*i915_gem_obj_to_vma(struct drm_i915_gem_object
*obj
,
4567 struct i915_address_space
*vm
)
4569 struct i915_vma
*vma
;
4570 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
) {
4571 if (i915_is_ggtt(vma
->vm
) &&
4572 vma
->ggtt_view
.type
!= I915_GGTT_VIEW_NORMAL
)
4580 struct i915_vma
*i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object
*obj
,
4581 const struct i915_ggtt_view
*view
)
4583 struct i915_address_space
*ggtt
= i915_obj_to_ggtt(obj
);
4584 struct i915_vma
*vma
;
4586 if (WARN_ONCE(!view
, "no view specified"))
4587 return ERR_PTR(-EINVAL
);
4589 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
4590 if (vma
->vm
== ggtt
&&
4591 i915_ggtt_view_equal(&vma
->ggtt_view
, view
))
4596 void i915_gem_vma_destroy(struct i915_vma
*vma
)
4598 struct i915_address_space
*vm
= NULL
;
4599 WARN_ON(vma
->node
.allocated
);
4601 /* Keep the vma as a placeholder in the execbuffer reservation lists */
4602 if (!list_empty(&vma
->exec_list
))
4607 if (!i915_is_ggtt(vm
))
4608 i915_ppgtt_put(i915_vm_to_ppgtt(vm
));
4610 list_del(&vma
->vma_link
);
4616 i915_gem_stop_ringbuffers(struct drm_device
*dev
)
4618 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4619 struct intel_engine_cs
*ring
;
4622 for_each_ring(ring
, dev_priv
, i
)
4623 dev_priv
->gt
.stop_ring(ring
);
4627 i915_gem_suspend(struct drm_device
*dev
)
4629 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4632 mutex_lock(&dev
->struct_mutex
);
4633 ret
= i915_gpu_idle(dev
);
4637 i915_gem_retire_requests(dev
);
4639 i915_gem_stop_ringbuffers(dev
);
4640 mutex_unlock(&dev
->struct_mutex
);
4642 cancel_delayed_work_sync(&dev_priv
->gpu_error
.hangcheck_work
);
4643 cancel_delayed_work_sync(&dev_priv
->mm
.retire_work
);
4644 flush_delayed_work(&dev_priv
->mm
.idle_work
);
4646 /* Assert that we sucessfully flushed all the work and
4647 * reset the GPU back to its idle, low power state.
4649 WARN_ON(dev_priv
->mm
.busy
);
4654 mutex_unlock(&dev
->struct_mutex
);
4658 int i915_gem_l3_remap(struct intel_engine_cs
*ring
, int slice
)
4660 struct drm_device
*dev
= ring
->dev
;
4661 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4662 u32 reg_base
= GEN7_L3LOG_BASE
+ (slice
* 0x200);
4663 u32
*remap_info
= dev_priv
->l3_parity
.remap_info
[slice
];
4666 if (!HAS_L3_DPF(dev
) || !remap_info
)
4669 ret
= intel_ring_begin(ring
, GEN7_L3LOG_SIZE
/ 4 * 3);
4674 * Note: We do not worry about the concurrent register cacheline hang
4675 * here because no other code should access these registers other than
4676 * at initialization time.
4678 for (i
= 0; i
< GEN7_L3LOG_SIZE
; i
+= 4) {
4679 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
4680 intel_ring_emit(ring
, reg_base
+ i
);
4681 intel_ring_emit(ring
, remap_info
[i
/4]);
4684 intel_ring_advance(ring
);
4689 void i915_gem_init_swizzling(struct drm_device
*dev
)
4691 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4693 if (INTEL_INFO(dev
)->gen
< 5 ||
4694 dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_NONE
)
4697 I915_WRITE(DISP_ARB_CTL
, I915_READ(DISP_ARB_CTL
) |
4698 DISP_TILE_SURFACE_SWIZZLING
);
4703 I915_WRITE(TILECTL
, I915_READ(TILECTL
) | TILECTL_SWZCTL
);
4705 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB
));
4706 else if (IS_GEN7(dev
))
4707 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB
));
4708 else if (IS_GEN8(dev
))
4709 I915_WRITE(GAMTARBMODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW
));
4715 intel_enable_blt(struct drm_device
*dev
)
4720 /* The blitter was dysfunctional on early prototypes */
4721 if (IS_GEN6(dev
) && dev
->pdev
->revision
< 8) {
4722 DRM_INFO("BLT not supported on this pre-production hardware;"
4723 " graphics performance will be degraded.\n");
4730 static void init_unused_ring(struct drm_device
*dev
, u32 base
)
4732 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4734 I915_WRITE(RING_CTL(base
), 0);
4735 I915_WRITE(RING_HEAD(base
), 0);
4736 I915_WRITE(RING_TAIL(base
), 0);
4737 I915_WRITE(RING_START(base
), 0);
4740 static void init_unused_rings(struct drm_device
*dev
)
4743 init_unused_ring(dev
, PRB1_BASE
);
4744 init_unused_ring(dev
, SRB0_BASE
);
4745 init_unused_ring(dev
, SRB1_BASE
);
4746 init_unused_ring(dev
, SRB2_BASE
);
4747 init_unused_ring(dev
, SRB3_BASE
);
4748 } else if (IS_GEN2(dev
)) {
4749 init_unused_ring(dev
, SRB0_BASE
);
4750 init_unused_ring(dev
, SRB1_BASE
);
4751 } else if (IS_GEN3(dev
)) {
4752 init_unused_ring(dev
, PRB1_BASE
);
4753 init_unused_ring(dev
, PRB2_BASE
);
4757 int i915_gem_init_rings(struct drm_device
*dev
)
4759 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4762 ret
= intel_init_render_ring_buffer(dev
);
4767 ret
= intel_init_bsd_ring_buffer(dev
);
4769 goto cleanup_render_ring
;
4772 if (intel_enable_blt(dev
)) {
4773 ret
= intel_init_blt_ring_buffer(dev
);
4775 goto cleanup_bsd_ring
;
4778 if (HAS_VEBOX(dev
)) {
4779 ret
= intel_init_vebox_ring_buffer(dev
);
4781 goto cleanup_blt_ring
;
4784 if (HAS_BSD2(dev
)) {
4785 ret
= intel_init_bsd2_ring_buffer(dev
);
4787 goto cleanup_vebox_ring
;
4790 ret
= i915_gem_set_seqno(dev
, ((u32
)~0 - 0x1000));
4792 goto cleanup_bsd2_ring
;
4797 intel_cleanup_ring_buffer(&dev_priv
->ring
[VCS2
]);
4799 intel_cleanup_ring_buffer(&dev_priv
->ring
[VECS
]);
4801 intel_cleanup_ring_buffer(&dev_priv
->ring
[BCS
]);
4803 intel_cleanup_ring_buffer(&dev_priv
->ring
[VCS
]);
4804 cleanup_render_ring
:
4805 intel_cleanup_ring_buffer(&dev_priv
->ring
[RCS
]);
4811 i915_gem_init_hw(struct drm_device
*dev
)
4813 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4814 struct intel_engine_cs
*ring
;
4817 if (INTEL_INFO(dev
)->gen
< 6 && !intel_enable_gtt())
4820 /* Double layer security blanket, see i915_gem_init() */
4821 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
4823 if (dev_priv
->ellc_size
)
4824 I915_WRITE(HSW_IDICR
, I915_READ(HSW_IDICR
) | IDIHASHMSK(0xf));
4826 if (IS_HASWELL(dev
))
4827 I915_WRITE(MI_PREDICATE_RESULT_2
, IS_HSW_GT3(dev
) ?
4828 LOWER_SLICE_ENABLED
: LOWER_SLICE_DISABLED
);
4830 if (HAS_PCH_NOP(dev
)) {
4831 if (IS_IVYBRIDGE(dev
)) {
4832 u32 temp
= I915_READ(GEN7_MSG_CTL
);
4833 temp
&= ~(WAIT_FOR_PCH_FLR_ACK
| WAIT_FOR_PCH_RESET_ACK
);
4834 I915_WRITE(GEN7_MSG_CTL
, temp
);
4835 } else if (INTEL_INFO(dev
)->gen
>= 7) {
4836 u32 temp
= I915_READ(HSW_NDE_RSTWRN_OPT
);
4837 temp
&= ~RESET_PCH_HANDSHAKE_ENABLE
;
4838 I915_WRITE(HSW_NDE_RSTWRN_OPT
, temp
);
4842 i915_gem_init_swizzling(dev
);
4845 * At least 830 can leave some of the unused rings
4846 * "active" (ie. head != tail) after resume which
4847 * will prevent c3 entry. Makes sure all unused rings
4850 init_unused_rings(dev
);
4852 for_each_ring(ring
, dev_priv
, i
) {
4853 ret
= ring
->init_hw(ring
);
4858 for (i
= 0; i
< NUM_L3_SLICES(dev
); i
++)
4859 i915_gem_l3_remap(&dev_priv
->ring
[RCS
], i
);
4861 ret
= i915_ppgtt_init_hw(dev
);
4862 if (ret
&& ret
!= -EIO
) {
4863 DRM_ERROR("PPGTT enable failed %d\n", ret
);
4864 i915_gem_cleanup_ringbuffer(dev
);
4867 ret
= i915_gem_context_enable(dev_priv
);
4868 if (ret
&& ret
!= -EIO
) {
4869 DRM_ERROR("Context enable failed %d\n", ret
);
4870 i915_gem_cleanup_ringbuffer(dev
);
4876 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
4880 int i915_gem_init(struct drm_device
*dev
)
4882 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4885 i915
.enable_execlists
= intel_sanitize_enable_execlists(dev
,
4886 i915
.enable_execlists
);
4888 mutex_lock(&dev
->struct_mutex
);
4890 if (IS_VALLEYVIEW(dev
)) {
4891 /* VLVA0 (potential hack), BIOS isn't actually waking us */
4892 I915_WRITE(VLV_GTLC_WAKE_CTRL
, VLV_GTLC_ALLOWWAKEREQ
);
4893 if (wait_for((I915_READ(VLV_GTLC_PW_STATUS
) &
4894 VLV_GTLC_ALLOWWAKEACK
), 10))
4895 DRM_DEBUG_DRIVER("allow wake ack timed out\n");
4898 if (!i915
.enable_execlists
) {
4899 dev_priv
->gt
.execbuf_submit
= i915_gem_ringbuffer_submission
;
4900 dev_priv
->gt
.init_rings
= i915_gem_init_rings
;
4901 dev_priv
->gt
.cleanup_ring
= intel_cleanup_ring_buffer
;
4902 dev_priv
->gt
.stop_ring
= intel_stop_ring_buffer
;
4904 dev_priv
->gt
.execbuf_submit
= intel_execlists_submission
;
4905 dev_priv
->gt
.init_rings
= intel_logical_rings_init
;
4906 dev_priv
->gt
.cleanup_ring
= intel_logical_ring_cleanup
;
4907 dev_priv
->gt
.stop_ring
= intel_logical_ring_stop
;
4910 /* This is just a security blanket to placate dragons.
4911 * On some systems, we very sporadically observe that the first TLBs
4912 * used by the CS may be stale, despite us poking the TLB reset. If
4913 * we hold the forcewake during initialisation these problems
4914 * just magically go away.
4916 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
4918 ret
= i915_gem_init_userptr(dev
);
4922 i915_gem_init_global_gtt(dev
);
4924 ret
= i915_gem_context_init(dev
);
4928 ret
= dev_priv
->gt
.init_rings(dev
);
4932 ret
= i915_gem_init_hw(dev
);
4934 /* Allow ring initialisation to fail by marking the GPU as
4935 * wedged. But we only want to do this where the GPU is angry,
4936 * for all other failure, such as an allocation failure, bail.
4938 DRM_ERROR("Failed to initialize GPU, declaring it wedged\n");
4939 atomic_set_mask(I915_WEDGED
, &dev_priv
->gpu_error
.reset_counter
);
4944 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
4945 mutex_unlock(&dev
->struct_mutex
);
4951 i915_gem_cleanup_ringbuffer(struct drm_device
*dev
)
4953 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4954 struct intel_engine_cs
*ring
;
4957 for_each_ring(ring
, dev_priv
, i
)
4958 dev_priv
->gt
.cleanup_ring(ring
);
4962 init_ring_lists(struct intel_engine_cs
*ring
)
4964 INIT_LIST_HEAD(&ring
->active_list
);
4965 INIT_LIST_HEAD(&ring
->request_list
);
4968 void i915_init_vm(struct drm_i915_private
*dev_priv
,
4969 struct i915_address_space
*vm
)
4971 if (!i915_is_ggtt(vm
))
4972 drm_mm_init(&vm
->mm
, vm
->start
, vm
->total
);
4973 vm
->dev
= dev_priv
->dev
;
4974 INIT_LIST_HEAD(&vm
->active_list
);
4975 INIT_LIST_HEAD(&vm
->inactive_list
);
4976 INIT_LIST_HEAD(&vm
->global_link
);
4977 list_add_tail(&vm
->global_link
, &dev_priv
->vm_list
);
4981 i915_gem_load(struct drm_device
*dev
)
4983 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4987 kmem_cache_create("i915_gem_object",
4988 sizeof(struct drm_i915_gem_object
), 0,
4992 INIT_LIST_HEAD(&dev_priv
->vm_list
);
4993 i915_init_vm(dev_priv
, &dev_priv
->gtt
.base
);
4995 INIT_LIST_HEAD(&dev_priv
->context_list
);
4996 INIT_LIST_HEAD(&dev_priv
->mm
.unbound_list
);
4997 INIT_LIST_HEAD(&dev_priv
->mm
.bound_list
);
4998 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
4999 for (i
= 0; i
< I915_NUM_RINGS
; i
++)
5000 init_ring_lists(&dev_priv
->ring
[i
]);
5001 for (i
= 0; i
< I915_MAX_NUM_FENCES
; i
++)
5002 INIT_LIST_HEAD(&dev_priv
->fence_regs
[i
].lru_list
);
5003 INIT_DELAYED_WORK(&dev_priv
->mm
.retire_work
,
5004 i915_gem_retire_work_handler
);
5005 INIT_DELAYED_WORK(&dev_priv
->mm
.idle_work
,
5006 i915_gem_idle_work_handler
);
5007 init_waitqueue_head(&dev_priv
->gpu_error
.reset_queue
);
5009 dev_priv
->relative_constants_mode
= I915_EXEC_CONSTANTS_REL_GENERAL
;
5011 if (INTEL_INFO(dev
)->gen
>= 7 && !IS_VALLEYVIEW(dev
))
5012 dev_priv
->num_fence_regs
= 32;
5013 else if (INTEL_INFO(dev
)->gen
>= 4 || IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
5014 dev_priv
->num_fence_regs
= 16;
5016 dev_priv
->num_fence_regs
= 8;
5018 if (intel_vgpu_active(dev
))
5019 dev_priv
->num_fence_regs
=
5020 I915_READ(vgtif_reg(avail_rs
.fence_num
));
5022 /* Initialize fence registers to zero */
5023 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
5024 i915_gem_restore_fences(dev
);
5026 i915_gem_detect_bit_6_swizzle(dev
);
5027 init_waitqueue_head(&dev_priv
->pending_flip_queue
);
5029 dev_priv
->mm
.interruptible
= true;
5031 i915_gem_shrinker_init(dev_priv
);
5033 i915_gem_batch_pool_init(dev
, &dev_priv
->mm
.batch_pool
);
5035 mutex_init(&dev_priv
->fb_tracking
.lock
);
5038 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
)
5040 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
5042 cancel_delayed_work_sync(&file_priv
->mm
.idle_work
);
5044 /* Clean up our request list when the client is going away, so that
5045 * later retire_requests won't dereference our soon-to-be-gone
5048 spin_lock(&file_priv
->mm
.lock
);
5049 while (!list_empty(&file_priv
->mm
.request_list
)) {
5050 struct drm_i915_gem_request
*request
;
5052 request
= list_first_entry(&file_priv
->mm
.request_list
,
5053 struct drm_i915_gem_request
,
5055 list_del(&request
->client_list
);
5056 request
->file_priv
= NULL
;
5058 spin_unlock(&file_priv
->mm
.lock
);
5062 i915_gem_file_idle_work_handler(struct work_struct
*work
)
5064 struct drm_i915_file_private
*file_priv
=
5065 container_of(work
, typeof(*file_priv
), mm
.idle_work
.work
);
5067 atomic_set(&file_priv
->rps_wait_boost
, false);
5070 int i915_gem_open(struct drm_device
*dev
, struct drm_file
*file
)
5072 struct drm_i915_file_private
*file_priv
;
5075 DRM_DEBUG_DRIVER("\n");
5077 file_priv
= kzalloc(sizeof(*file_priv
), GFP_KERNEL
);
5081 file
->driver_priv
= file_priv
;
5082 file_priv
->dev_priv
= dev
->dev_private
;
5083 file_priv
->file
= file
;
5085 spin_lock_init(&file_priv
->mm
.lock
);
5086 INIT_LIST_HEAD(&file_priv
->mm
.request_list
);
5087 INIT_DELAYED_WORK(&file_priv
->mm
.idle_work
,
5088 i915_gem_file_idle_work_handler
);
5090 ret
= i915_gem_context_open(dev
, file
);
5098 * i915_gem_track_fb - update frontbuffer tracking
5099 * old: current GEM buffer for the frontbuffer slots
5100 * new: new GEM buffer for the frontbuffer slots
5101 * frontbuffer_bits: bitmask of frontbuffer slots
5103 * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them
5104 * from @old and setting them in @new. Both @old and @new can be NULL.
5106 void i915_gem_track_fb(struct drm_i915_gem_object
*old
,
5107 struct drm_i915_gem_object
*new,
5108 unsigned frontbuffer_bits
)
5111 WARN_ON(!mutex_is_locked(&old
->base
.dev
->struct_mutex
));
5112 WARN_ON(!(old
->frontbuffer_bits
& frontbuffer_bits
));
5113 old
->frontbuffer_bits
&= ~frontbuffer_bits
;
5117 WARN_ON(!mutex_is_locked(&new->base
.dev
->struct_mutex
));
5118 WARN_ON(new->frontbuffer_bits
& frontbuffer_bits
);
5119 new->frontbuffer_bits
|= frontbuffer_bits
;
5123 /* All the new VM stuff */
5125 i915_gem_obj_offset(struct drm_i915_gem_object
*o
,
5126 struct i915_address_space
*vm
)
5128 struct drm_i915_private
*dev_priv
= o
->base
.dev
->dev_private
;
5129 struct i915_vma
*vma
;
5131 WARN_ON(vm
== &dev_priv
->mm
.aliasing_ppgtt
->base
);
5133 list_for_each_entry(vma
, &o
->vma_list
, vma_link
) {
5134 if (i915_is_ggtt(vma
->vm
) &&
5135 vma
->ggtt_view
.type
!= I915_GGTT_VIEW_NORMAL
)
5138 return vma
->node
.start
;
5141 WARN(1, "%s vma for this object not found.\n",
5142 i915_is_ggtt(vm
) ? "global" : "ppgtt");
5147 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object
*o
,
5148 const struct i915_ggtt_view
*view
)
5150 struct i915_address_space
*ggtt
= i915_obj_to_ggtt(o
);
5151 struct i915_vma
*vma
;
5153 list_for_each_entry(vma
, &o
->vma_list
, vma_link
)
5154 if (vma
->vm
== ggtt
&&
5155 i915_ggtt_view_equal(&vma
->ggtt_view
, view
))
5156 return vma
->node
.start
;
5158 WARN(1, "global vma for this object not found.\n");
5162 bool i915_gem_obj_bound(struct drm_i915_gem_object
*o
,
5163 struct i915_address_space
*vm
)
5165 struct i915_vma
*vma
;
5167 list_for_each_entry(vma
, &o
->vma_list
, vma_link
) {
5168 if (i915_is_ggtt(vma
->vm
) &&
5169 vma
->ggtt_view
.type
!= I915_GGTT_VIEW_NORMAL
)
5171 if (vma
->vm
== vm
&& drm_mm_node_allocated(&vma
->node
))
5178 bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object
*o
,
5179 const struct i915_ggtt_view
*view
)
5181 struct i915_address_space
*ggtt
= i915_obj_to_ggtt(o
);
5182 struct i915_vma
*vma
;
5184 list_for_each_entry(vma
, &o
->vma_list
, vma_link
)
5185 if (vma
->vm
== ggtt
&&
5186 i915_ggtt_view_equal(&vma
->ggtt_view
, view
) &&
5187 drm_mm_node_allocated(&vma
->node
))
5193 bool i915_gem_obj_bound_any(struct drm_i915_gem_object
*o
)
5195 struct i915_vma
*vma
;
5197 list_for_each_entry(vma
, &o
->vma_list
, vma_link
)
5198 if (drm_mm_node_allocated(&vma
->node
))
5204 unsigned long i915_gem_obj_size(struct drm_i915_gem_object
*o
,
5205 struct i915_address_space
*vm
)
5207 struct drm_i915_private
*dev_priv
= o
->base
.dev
->dev_private
;
5208 struct i915_vma
*vma
;
5210 WARN_ON(vm
== &dev_priv
->mm
.aliasing_ppgtt
->base
);
5212 BUG_ON(list_empty(&o
->vma_list
));
5214 list_for_each_entry(vma
, &o
->vma_list
, vma_link
) {
5215 if (i915_is_ggtt(vma
->vm
) &&
5216 vma
->ggtt_view
.type
!= I915_GGTT_VIEW_NORMAL
)
5219 return vma
->node
.size
;
5224 bool i915_gem_obj_is_pinned(struct drm_i915_gem_object
*obj
)
5226 struct i915_vma
*vma
;
5227 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
) {
5228 if (i915_is_ggtt(vma
->vm
) &&
5229 vma
->ggtt_view
.type
!= I915_GGTT_VIEW_NORMAL
)
5231 if (vma
->pin_count
> 0)