2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/swap.h>
35 #include <linux/pci.h>
37 #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
39 static void i915_gem_object_flush_gpu_write_domain(struct drm_gem_object
*obj
);
40 static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object
*obj
);
41 static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object
*obj
);
42 static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object
*obj
,
44 static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object
*obj
,
47 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object
*obj
);
48 static int i915_gem_object_wait_rendering(struct drm_gem_object
*obj
);
49 static int i915_gem_object_bind_to_gtt(struct drm_gem_object
*obj
,
51 static void i915_gem_clear_fence_reg(struct drm_gem_object
*obj
);
52 static int i915_gem_evict_something(struct drm_device
*dev
, int min_size
);
53 static int i915_gem_evict_from_inactive_list(struct drm_device
*dev
);
54 static int i915_gem_phys_pwrite(struct drm_device
*dev
, struct drm_gem_object
*obj
,
55 struct drm_i915_gem_pwrite
*args
,
56 struct drm_file
*file_priv
);
58 static LIST_HEAD(shrink_list
);
59 static DEFINE_SPINLOCK(shrink_list_lock
);
61 int i915_gem_do_init(struct drm_device
*dev
, unsigned long start
,
64 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
67 (start
& (PAGE_SIZE
- 1)) != 0 ||
68 (end
& (PAGE_SIZE
- 1)) != 0) {
72 drm_mm_init(&dev_priv
->mm
.gtt_space
, start
,
75 dev
->gtt_total
= (uint32_t) (end
- start
);
81 i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
82 struct drm_file
*file_priv
)
84 struct drm_i915_gem_init
*args
= data
;
87 mutex_lock(&dev
->struct_mutex
);
88 ret
= i915_gem_do_init(dev
, args
->gtt_start
, args
->gtt_end
);
89 mutex_unlock(&dev
->struct_mutex
);
95 i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
96 struct drm_file
*file_priv
)
98 struct drm_i915_gem_get_aperture
*args
= data
;
100 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
103 args
->aper_size
= dev
->gtt_total
;
104 args
->aper_available_size
= (args
->aper_size
-
105 atomic_read(&dev
->pin_memory
));
112 * Creates a new mm object and returns a handle to it.
115 i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
116 struct drm_file
*file_priv
)
118 struct drm_i915_gem_create
*args
= data
;
119 struct drm_gem_object
*obj
;
123 args
->size
= roundup(args
->size
, PAGE_SIZE
);
125 /* Allocate the new object */
126 obj
= drm_gem_object_alloc(dev
, args
->size
);
130 ret
= drm_gem_handle_create(file_priv
, obj
, &handle
);
131 mutex_lock(&dev
->struct_mutex
);
132 drm_gem_object_handle_unreference(obj
);
133 mutex_unlock(&dev
->struct_mutex
);
138 args
->handle
= handle
;
144 fast_shmem_read(struct page
**pages
,
145 loff_t page_base
, int page_offset
,
152 vaddr
= kmap_atomic(pages
[page_base
>> PAGE_SHIFT
], KM_USER0
);
155 unwritten
= __copy_to_user_inatomic(data
, vaddr
+ page_offset
, length
);
156 kunmap_atomic(vaddr
, KM_USER0
);
164 static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object
*obj
)
166 drm_i915_private_t
*dev_priv
= obj
->dev
->dev_private
;
167 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
169 return dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_9_10_17
&&
170 obj_priv
->tiling_mode
!= I915_TILING_NONE
;
174 slow_shmem_copy(struct page
*dst_page
,
176 struct page
*src_page
,
180 char *dst_vaddr
, *src_vaddr
;
182 dst_vaddr
= kmap_atomic(dst_page
, KM_USER0
);
183 if (dst_vaddr
== NULL
)
186 src_vaddr
= kmap_atomic(src_page
, KM_USER1
);
187 if (src_vaddr
== NULL
) {
188 kunmap_atomic(dst_vaddr
, KM_USER0
);
192 memcpy(dst_vaddr
+ dst_offset
, src_vaddr
+ src_offset
, length
);
194 kunmap_atomic(src_vaddr
, KM_USER1
);
195 kunmap_atomic(dst_vaddr
, KM_USER0
);
201 slow_shmem_bit17_copy(struct page
*gpu_page
,
203 struct page
*cpu_page
,
208 char *gpu_vaddr
, *cpu_vaddr
;
210 /* Use the unswizzled path if this page isn't affected. */
211 if ((page_to_phys(gpu_page
) & (1 << 17)) == 0) {
213 return slow_shmem_copy(cpu_page
, cpu_offset
,
214 gpu_page
, gpu_offset
, length
);
216 return slow_shmem_copy(gpu_page
, gpu_offset
,
217 cpu_page
, cpu_offset
, length
);
220 gpu_vaddr
= kmap_atomic(gpu_page
, KM_USER0
);
221 if (gpu_vaddr
== NULL
)
224 cpu_vaddr
= kmap_atomic(cpu_page
, KM_USER1
);
225 if (cpu_vaddr
== NULL
) {
226 kunmap_atomic(gpu_vaddr
, KM_USER0
);
230 /* Copy the data, XORing A6 with A17 (1). The user already knows he's
231 * XORing with the other bits (A9 for Y, A9 and A10 for X)
234 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
235 int this_length
= min(cacheline_end
- gpu_offset
, length
);
236 int swizzled_gpu_offset
= gpu_offset
^ 64;
239 memcpy(cpu_vaddr
+ cpu_offset
,
240 gpu_vaddr
+ swizzled_gpu_offset
,
243 memcpy(gpu_vaddr
+ swizzled_gpu_offset
,
244 cpu_vaddr
+ cpu_offset
,
247 cpu_offset
+= this_length
;
248 gpu_offset
+= this_length
;
249 length
-= this_length
;
252 kunmap_atomic(cpu_vaddr
, KM_USER1
);
253 kunmap_atomic(gpu_vaddr
, KM_USER0
);
259 * This is the fast shmem pread path, which attempts to copy_from_user directly
260 * from the backing pages of the object to the user's address space. On a
261 * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
264 i915_gem_shmem_pread_fast(struct drm_device
*dev
, struct drm_gem_object
*obj
,
265 struct drm_i915_gem_pread
*args
,
266 struct drm_file
*file_priv
)
268 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
270 loff_t offset
, page_base
;
271 char __user
*user_data
;
272 int page_offset
, page_length
;
275 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
278 mutex_lock(&dev
->struct_mutex
);
280 ret
= i915_gem_object_get_pages(obj
, 0);
284 ret
= i915_gem_object_set_cpu_read_domain_range(obj
, args
->offset
,
289 obj_priv
= obj
->driver_private
;
290 offset
= args
->offset
;
293 /* Operation in this page
295 * page_base = page offset within aperture
296 * page_offset = offset within page
297 * page_length = bytes to copy for this page
299 page_base
= (offset
& ~(PAGE_SIZE
-1));
300 page_offset
= offset
& (PAGE_SIZE
-1);
301 page_length
= remain
;
302 if ((page_offset
+ remain
) > PAGE_SIZE
)
303 page_length
= PAGE_SIZE
- page_offset
;
305 ret
= fast_shmem_read(obj_priv
->pages
,
306 page_base
, page_offset
,
307 user_data
, page_length
);
311 remain
-= page_length
;
312 user_data
+= page_length
;
313 offset
+= page_length
;
317 i915_gem_object_put_pages(obj
);
319 mutex_unlock(&dev
->struct_mutex
);
325 i915_gem_object_get_pages_or_evict(struct drm_gem_object
*obj
)
329 ret
= i915_gem_object_get_pages(obj
, __GFP_NORETRY
| __GFP_NOWARN
);
331 /* If we've insufficient memory to map in the pages, attempt
332 * to make some space by throwing out some old buffers.
334 if (ret
== -ENOMEM
) {
335 struct drm_device
*dev
= obj
->dev
;
337 ret
= i915_gem_evict_something(dev
, obj
->size
);
341 ret
= i915_gem_object_get_pages(obj
, 0);
348 * This is the fallback shmem pread path, which allocates temporary storage
349 * in kernel space to copy_to_user into outside of the struct_mutex, so we
350 * can copy out of the object's backing pages while holding the struct mutex
351 * and not take page faults.
354 i915_gem_shmem_pread_slow(struct drm_device
*dev
, struct drm_gem_object
*obj
,
355 struct drm_i915_gem_pread
*args
,
356 struct drm_file
*file_priv
)
358 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
359 struct mm_struct
*mm
= current
->mm
;
360 struct page
**user_pages
;
362 loff_t offset
, pinned_pages
, i
;
363 loff_t first_data_page
, last_data_page
, num_pages
;
364 int shmem_page_index
, shmem_page_offset
;
365 int data_page_index
, data_page_offset
;
368 uint64_t data_ptr
= args
->data_ptr
;
369 int do_bit17_swizzling
;
373 /* Pin the user pages containing the data. We can't fault while
374 * holding the struct mutex, yet we want to hold it while
375 * dereferencing the user data.
377 first_data_page
= data_ptr
/ PAGE_SIZE
;
378 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
379 num_pages
= last_data_page
- first_data_page
+ 1;
381 user_pages
= drm_calloc_large(num_pages
, sizeof(struct page
*));
382 if (user_pages
== NULL
)
385 down_read(&mm
->mmap_sem
);
386 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
387 num_pages
, 1, 0, user_pages
, NULL
);
388 up_read(&mm
->mmap_sem
);
389 if (pinned_pages
< num_pages
) {
391 goto fail_put_user_pages
;
394 do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
396 mutex_lock(&dev
->struct_mutex
);
398 ret
= i915_gem_object_get_pages_or_evict(obj
);
402 ret
= i915_gem_object_set_cpu_read_domain_range(obj
, args
->offset
,
407 obj_priv
= obj
->driver_private
;
408 offset
= args
->offset
;
411 /* Operation in this page
413 * shmem_page_index = page number within shmem file
414 * shmem_page_offset = offset within page in shmem file
415 * data_page_index = page number in get_user_pages return
416 * data_page_offset = offset with data_page_index page.
417 * page_length = bytes to copy for this page
419 shmem_page_index
= offset
/ PAGE_SIZE
;
420 shmem_page_offset
= offset
& ~PAGE_MASK
;
421 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
422 data_page_offset
= data_ptr
& ~PAGE_MASK
;
424 page_length
= remain
;
425 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
426 page_length
= PAGE_SIZE
- shmem_page_offset
;
427 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
428 page_length
= PAGE_SIZE
- data_page_offset
;
430 if (do_bit17_swizzling
) {
431 ret
= slow_shmem_bit17_copy(obj_priv
->pages
[shmem_page_index
],
433 user_pages
[data_page_index
],
438 ret
= slow_shmem_copy(user_pages
[data_page_index
],
440 obj_priv
->pages
[shmem_page_index
],
447 remain
-= page_length
;
448 data_ptr
+= page_length
;
449 offset
+= page_length
;
453 i915_gem_object_put_pages(obj
);
455 mutex_unlock(&dev
->struct_mutex
);
457 for (i
= 0; i
< pinned_pages
; i
++) {
458 SetPageDirty(user_pages
[i
]);
459 page_cache_release(user_pages
[i
]);
461 drm_free_large(user_pages
);
467 * Reads data from the object referenced by handle.
469 * On error, the contents of *data are undefined.
472 i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
473 struct drm_file
*file_priv
)
475 struct drm_i915_gem_pread
*args
= data
;
476 struct drm_gem_object
*obj
;
477 struct drm_i915_gem_object
*obj_priv
;
480 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
483 obj_priv
= obj
->driver_private
;
485 /* Bounds check source.
487 * XXX: This could use review for overflow issues...
489 if (args
->offset
> obj
->size
|| args
->size
> obj
->size
||
490 args
->offset
+ args
->size
> obj
->size
) {
491 drm_gem_object_unreference(obj
);
495 if (i915_gem_object_needs_bit17_swizzle(obj
)) {
496 ret
= i915_gem_shmem_pread_slow(dev
, obj
, args
, file_priv
);
498 ret
= i915_gem_shmem_pread_fast(dev
, obj
, args
, file_priv
);
500 ret
= i915_gem_shmem_pread_slow(dev
, obj
, args
,
504 drm_gem_object_unreference(obj
);
509 /* This is the fast write path which cannot handle
510 * page faults in the source data
514 fast_user_write(struct io_mapping
*mapping
,
515 loff_t page_base
, int page_offset
,
516 char __user
*user_data
,
520 unsigned long unwritten
;
522 vaddr_atomic
= io_mapping_map_atomic_wc(mapping
, page_base
);
523 unwritten
= __copy_from_user_inatomic_nocache(vaddr_atomic
+ page_offset
,
525 io_mapping_unmap_atomic(vaddr_atomic
);
531 /* Here's the write path which can sleep for
536 slow_kernel_write(struct io_mapping
*mapping
,
537 loff_t gtt_base
, int gtt_offset
,
538 struct page
*user_page
, int user_offset
,
541 char *src_vaddr
, *dst_vaddr
;
542 unsigned long unwritten
;
544 dst_vaddr
= io_mapping_map_atomic_wc(mapping
, gtt_base
);
545 src_vaddr
= kmap_atomic(user_page
, KM_USER1
);
546 unwritten
= __copy_from_user_inatomic_nocache(dst_vaddr
+ gtt_offset
,
547 src_vaddr
+ user_offset
,
549 kunmap_atomic(src_vaddr
, KM_USER1
);
550 io_mapping_unmap_atomic(dst_vaddr
);
557 fast_shmem_write(struct page
**pages
,
558 loff_t page_base
, int page_offset
,
563 unsigned long unwritten
;
565 vaddr
= kmap_atomic(pages
[page_base
>> PAGE_SHIFT
], KM_USER0
);
568 unwritten
= __copy_from_user_inatomic(vaddr
+ page_offset
, data
, length
);
569 kunmap_atomic(vaddr
, KM_USER0
);
577 * This is the fast pwrite path, where we copy the data directly from the
578 * user into the GTT, uncached.
581 i915_gem_gtt_pwrite_fast(struct drm_device
*dev
, struct drm_gem_object
*obj
,
582 struct drm_i915_gem_pwrite
*args
,
583 struct drm_file
*file_priv
)
585 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
586 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
588 loff_t offset
, page_base
;
589 char __user
*user_data
;
590 int page_offset
, page_length
;
593 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
595 if (!access_ok(VERIFY_READ
, user_data
, remain
))
599 mutex_lock(&dev
->struct_mutex
);
600 ret
= i915_gem_object_pin(obj
, 0);
602 mutex_unlock(&dev
->struct_mutex
);
605 ret
= i915_gem_object_set_to_gtt_domain(obj
, 1);
609 obj_priv
= obj
->driver_private
;
610 offset
= obj_priv
->gtt_offset
+ args
->offset
;
613 /* Operation in this page
615 * page_base = page offset within aperture
616 * page_offset = offset within page
617 * page_length = bytes to copy for this page
619 page_base
= (offset
& ~(PAGE_SIZE
-1));
620 page_offset
= offset
& (PAGE_SIZE
-1);
621 page_length
= remain
;
622 if ((page_offset
+ remain
) > PAGE_SIZE
)
623 page_length
= PAGE_SIZE
- page_offset
;
625 ret
= fast_user_write (dev_priv
->mm
.gtt_mapping
, page_base
,
626 page_offset
, user_data
, page_length
);
628 /* If we get a fault while copying data, then (presumably) our
629 * source page isn't available. Return the error and we'll
630 * retry in the slow path.
635 remain
-= page_length
;
636 user_data
+= page_length
;
637 offset
+= page_length
;
641 i915_gem_object_unpin(obj
);
642 mutex_unlock(&dev
->struct_mutex
);
648 * This is the fallback GTT pwrite path, which uses get_user_pages to pin
649 * the memory and maps it using kmap_atomic for copying.
651 * This code resulted in x11perf -rgb10text consuming about 10% more CPU
652 * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
655 i915_gem_gtt_pwrite_slow(struct drm_device
*dev
, struct drm_gem_object
*obj
,
656 struct drm_i915_gem_pwrite
*args
,
657 struct drm_file
*file_priv
)
659 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
660 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
662 loff_t gtt_page_base
, offset
;
663 loff_t first_data_page
, last_data_page
, num_pages
;
664 loff_t pinned_pages
, i
;
665 struct page
**user_pages
;
666 struct mm_struct
*mm
= current
->mm
;
667 int gtt_page_offset
, data_page_offset
, data_page_index
, page_length
;
669 uint64_t data_ptr
= args
->data_ptr
;
673 /* Pin the user pages containing the data. We can't fault while
674 * holding the struct mutex, and all of the pwrite implementations
675 * want to hold it while dereferencing the user data.
677 first_data_page
= data_ptr
/ PAGE_SIZE
;
678 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
679 num_pages
= last_data_page
- first_data_page
+ 1;
681 user_pages
= drm_calloc_large(num_pages
, sizeof(struct page
*));
682 if (user_pages
== NULL
)
685 down_read(&mm
->mmap_sem
);
686 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
687 num_pages
, 0, 0, user_pages
, NULL
);
688 up_read(&mm
->mmap_sem
);
689 if (pinned_pages
< num_pages
) {
691 goto out_unpin_pages
;
694 mutex_lock(&dev
->struct_mutex
);
695 ret
= i915_gem_object_pin(obj
, 0);
699 ret
= i915_gem_object_set_to_gtt_domain(obj
, 1);
701 goto out_unpin_object
;
703 obj_priv
= obj
->driver_private
;
704 offset
= obj_priv
->gtt_offset
+ args
->offset
;
707 /* Operation in this page
709 * gtt_page_base = page offset within aperture
710 * gtt_page_offset = offset within page in aperture
711 * data_page_index = page number in get_user_pages return
712 * data_page_offset = offset with data_page_index page.
713 * page_length = bytes to copy for this page
715 gtt_page_base
= offset
& PAGE_MASK
;
716 gtt_page_offset
= offset
& ~PAGE_MASK
;
717 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
718 data_page_offset
= data_ptr
& ~PAGE_MASK
;
720 page_length
= remain
;
721 if ((gtt_page_offset
+ page_length
) > PAGE_SIZE
)
722 page_length
= PAGE_SIZE
- gtt_page_offset
;
723 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
724 page_length
= PAGE_SIZE
- data_page_offset
;
726 ret
= slow_kernel_write(dev_priv
->mm
.gtt_mapping
,
727 gtt_page_base
, gtt_page_offset
,
728 user_pages
[data_page_index
],
732 /* If we get a fault while copying data, then (presumably) our
733 * source page isn't available. Return the error and we'll
734 * retry in the slow path.
737 goto out_unpin_object
;
739 remain
-= page_length
;
740 offset
+= page_length
;
741 data_ptr
+= page_length
;
745 i915_gem_object_unpin(obj
);
747 mutex_unlock(&dev
->struct_mutex
);
749 for (i
= 0; i
< pinned_pages
; i
++)
750 page_cache_release(user_pages
[i
]);
751 drm_free_large(user_pages
);
757 * This is the fast shmem pwrite path, which attempts to directly
758 * copy_from_user into the kmapped pages backing the object.
761 i915_gem_shmem_pwrite_fast(struct drm_device
*dev
, struct drm_gem_object
*obj
,
762 struct drm_i915_gem_pwrite
*args
,
763 struct drm_file
*file_priv
)
765 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
767 loff_t offset
, page_base
;
768 char __user
*user_data
;
769 int page_offset
, page_length
;
772 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
775 mutex_lock(&dev
->struct_mutex
);
777 ret
= i915_gem_object_get_pages(obj
, 0);
781 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
785 obj_priv
= obj
->driver_private
;
786 offset
= args
->offset
;
790 /* Operation in this page
792 * page_base = page offset within aperture
793 * page_offset = offset within page
794 * page_length = bytes to copy for this page
796 page_base
= (offset
& ~(PAGE_SIZE
-1));
797 page_offset
= offset
& (PAGE_SIZE
-1);
798 page_length
= remain
;
799 if ((page_offset
+ remain
) > PAGE_SIZE
)
800 page_length
= PAGE_SIZE
- page_offset
;
802 ret
= fast_shmem_write(obj_priv
->pages
,
803 page_base
, page_offset
,
804 user_data
, page_length
);
808 remain
-= page_length
;
809 user_data
+= page_length
;
810 offset
+= page_length
;
814 i915_gem_object_put_pages(obj
);
816 mutex_unlock(&dev
->struct_mutex
);
822 * This is the fallback shmem pwrite path, which uses get_user_pages to pin
823 * the memory and maps it using kmap_atomic for copying.
825 * This avoids taking mmap_sem for faulting on the user's address while the
826 * struct_mutex is held.
829 i915_gem_shmem_pwrite_slow(struct drm_device
*dev
, struct drm_gem_object
*obj
,
830 struct drm_i915_gem_pwrite
*args
,
831 struct drm_file
*file_priv
)
833 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
834 struct mm_struct
*mm
= current
->mm
;
835 struct page
**user_pages
;
837 loff_t offset
, pinned_pages
, i
;
838 loff_t first_data_page
, last_data_page
, num_pages
;
839 int shmem_page_index
, shmem_page_offset
;
840 int data_page_index
, data_page_offset
;
843 uint64_t data_ptr
= args
->data_ptr
;
844 int do_bit17_swizzling
;
848 /* Pin the user pages containing the data. We can't fault while
849 * holding the struct mutex, and all of the pwrite implementations
850 * want to hold it while dereferencing the user data.
852 first_data_page
= data_ptr
/ PAGE_SIZE
;
853 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
854 num_pages
= last_data_page
- first_data_page
+ 1;
856 user_pages
= drm_calloc_large(num_pages
, sizeof(struct page
*));
857 if (user_pages
== NULL
)
860 down_read(&mm
->mmap_sem
);
861 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
862 num_pages
, 0, 0, user_pages
, NULL
);
863 up_read(&mm
->mmap_sem
);
864 if (pinned_pages
< num_pages
) {
866 goto fail_put_user_pages
;
869 do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
871 mutex_lock(&dev
->struct_mutex
);
873 ret
= i915_gem_object_get_pages_or_evict(obj
);
877 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
881 obj_priv
= obj
->driver_private
;
882 offset
= args
->offset
;
886 /* Operation in this page
888 * shmem_page_index = page number within shmem file
889 * shmem_page_offset = offset within page in shmem file
890 * data_page_index = page number in get_user_pages return
891 * data_page_offset = offset with data_page_index page.
892 * page_length = bytes to copy for this page
894 shmem_page_index
= offset
/ PAGE_SIZE
;
895 shmem_page_offset
= offset
& ~PAGE_MASK
;
896 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
897 data_page_offset
= data_ptr
& ~PAGE_MASK
;
899 page_length
= remain
;
900 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
901 page_length
= PAGE_SIZE
- shmem_page_offset
;
902 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
903 page_length
= PAGE_SIZE
- data_page_offset
;
905 if (do_bit17_swizzling
) {
906 ret
= slow_shmem_bit17_copy(obj_priv
->pages
[shmem_page_index
],
908 user_pages
[data_page_index
],
913 ret
= slow_shmem_copy(obj_priv
->pages
[shmem_page_index
],
915 user_pages
[data_page_index
],
922 remain
-= page_length
;
923 data_ptr
+= page_length
;
924 offset
+= page_length
;
928 i915_gem_object_put_pages(obj
);
930 mutex_unlock(&dev
->struct_mutex
);
932 for (i
= 0; i
< pinned_pages
; i
++)
933 page_cache_release(user_pages
[i
]);
934 drm_free_large(user_pages
);
940 * Writes data to the object referenced by handle.
942 * On error, the contents of the buffer that were to be modified are undefined.
945 i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
946 struct drm_file
*file_priv
)
948 struct drm_i915_gem_pwrite
*args
= data
;
949 struct drm_gem_object
*obj
;
950 struct drm_i915_gem_object
*obj_priv
;
953 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
956 obj_priv
= obj
->driver_private
;
958 /* Bounds check destination.
960 * XXX: This could use review for overflow issues...
962 if (args
->offset
> obj
->size
|| args
->size
> obj
->size
||
963 args
->offset
+ args
->size
> obj
->size
) {
964 drm_gem_object_unreference(obj
);
968 /* We can only do the GTT pwrite on untiled buffers, as otherwise
969 * it would end up going through the fenced access, and we'll get
970 * different detiling behavior between reading and writing.
971 * pread/pwrite currently are reading and writing from the CPU
972 * perspective, requiring manual detiling by the client.
974 if (obj_priv
->phys_obj
)
975 ret
= i915_gem_phys_pwrite(dev
, obj
, args
, file_priv
);
976 else if (obj_priv
->tiling_mode
== I915_TILING_NONE
&&
977 dev
->gtt_total
!= 0) {
978 ret
= i915_gem_gtt_pwrite_fast(dev
, obj
, args
, file_priv
);
979 if (ret
== -EFAULT
) {
980 ret
= i915_gem_gtt_pwrite_slow(dev
, obj
, args
,
983 } else if (i915_gem_object_needs_bit17_swizzle(obj
)) {
984 ret
= i915_gem_shmem_pwrite_slow(dev
, obj
, args
, file_priv
);
986 ret
= i915_gem_shmem_pwrite_fast(dev
, obj
, args
, file_priv
);
987 if (ret
== -EFAULT
) {
988 ret
= i915_gem_shmem_pwrite_slow(dev
, obj
, args
,
995 DRM_INFO("pwrite failed %d\n", ret
);
998 drm_gem_object_unreference(obj
);
1004 * Called when user space prepares to use an object with the CPU, either
1005 * through the mmap ioctl's mapping or a GTT mapping.
1008 i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
1009 struct drm_file
*file_priv
)
1011 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1012 struct drm_i915_gem_set_domain
*args
= data
;
1013 struct drm_gem_object
*obj
;
1014 struct drm_i915_gem_object
*obj_priv
;
1015 uint32_t read_domains
= args
->read_domains
;
1016 uint32_t write_domain
= args
->write_domain
;
1019 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1022 /* Only handle setting domains to types used by the CPU. */
1023 if (write_domain
& I915_GEM_GPU_DOMAINS
)
1026 if (read_domains
& I915_GEM_GPU_DOMAINS
)
1029 /* Having something in the write domain implies it's in the read
1030 * domain, and only that read domain. Enforce that in the request.
1032 if (write_domain
!= 0 && read_domains
!= write_domain
)
1035 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1038 obj_priv
= obj
->driver_private
;
1040 mutex_lock(&dev
->struct_mutex
);
1042 intel_mark_busy(dev
, obj
);
1045 DRM_INFO("set_domain_ioctl %p(%zd), %08x %08x\n",
1046 obj
, obj
->size
, read_domains
, write_domain
);
1048 if (read_domains
& I915_GEM_DOMAIN_GTT
) {
1049 ret
= i915_gem_object_set_to_gtt_domain(obj
, write_domain
!= 0);
1051 /* Update the LRU on the fence for the CPU access that's
1054 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
) {
1055 list_move_tail(&obj_priv
->fence_list
,
1056 &dev_priv
->mm
.fence_list
);
1059 /* Silently promote "you're not bound, there was nothing to do"
1060 * to success, since the client was just asking us to
1061 * make sure everything was done.
1066 ret
= i915_gem_object_set_to_cpu_domain(obj
, write_domain
!= 0);
1069 drm_gem_object_unreference(obj
);
1070 mutex_unlock(&dev
->struct_mutex
);
1075 * Called when user space has done writes to this buffer
1078 i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1079 struct drm_file
*file_priv
)
1081 struct drm_i915_gem_sw_finish
*args
= data
;
1082 struct drm_gem_object
*obj
;
1083 struct drm_i915_gem_object
*obj_priv
;
1086 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1089 mutex_lock(&dev
->struct_mutex
);
1090 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1092 mutex_unlock(&dev
->struct_mutex
);
1097 DRM_INFO("%s: sw_finish %d (%p %zd)\n",
1098 __func__
, args
->handle
, obj
, obj
->size
);
1100 obj_priv
= obj
->driver_private
;
1102 /* Pinned buffers may be scanout, so flush the cache */
1103 if (obj_priv
->pin_count
)
1104 i915_gem_object_flush_cpu_write_domain(obj
);
1106 drm_gem_object_unreference(obj
);
1107 mutex_unlock(&dev
->struct_mutex
);
1112 * Maps the contents of an object, returning the address it is mapped
1115 * While the mapping holds a reference on the contents of the object, it doesn't
1116 * imply a ref on the object itself.
1119 i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1120 struct drm_file
*file_priv
)
1122 struct drm_i915_gem_mmap
*args
= data
;
1123 struct drm_gem_object
*obj
;
1127 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1130 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1134 offset
= args
->offset
;
1136 down_write(¤t
->mm
->mmap_sem
);
1137 addr
= do_mmap(obj
->filp
, 0, args
->size
,
1138 PROT_READ
| PROT_WRITE
, MAP_SHARED
,
1140 up_write(¤t
->mm
->mmap_sem
);
1141 mutex_lock(&dev
->struct_mutex
);
1142 drm_gem_object_unreference(obj
);
1143 mutex_unlock(&dev
->struct_mutex
);
1144 if (IS_ERR((void *)addr
))
1147 args
->addr_ptr
= (uint64_t) addr
;
1153 * i915_gem_fault - fault a page into the GTT
1154 * vma: VMA in question
1157 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1158 * from userspace. The fault handler takes care of binding the object to
1159 * the GTT (if needed), allocating and programming a fence register (again,
1160 * only if needed based on whether the old reg is still valid or the object
1161 * is tiled) and inserting a new PTE into the faulting process.
1163 * Note that the faulting process may involve evicting existing objects
1164 * from the GTT and/or fence registers to make room. So performance may
1165 * suffer if the GTT working set is large or there are few fence registers
1168 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
)
1170 struct drm_gem_object
*obj
= vma
->vm_private_data
;
1171 struct drm_device
*dev
= obj
->dev
;
1172 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1173 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1174 pgoff_t page_offset
;
1177 bool write
= !!(vmf
->flags
& FAULT_FLAG_WRITE
);
1179 /* We don't use vmf->pgoff since that has the fake offset */
1180 page_offset
= ((unsigned long)vmf
->virtual_address
- vma
->vm_start
) >>
1183 /* Now bind it into the GTT if needed */
1184 mutex_lock(&dev
->struct_mutex
);
1185 if (!obj_priv
->gtt_space
) {
1186 ret
= i915_gem_object_bind_to_gtt(obj
, 0);
1190 list_add_tail(&obj_priv
->list
, &dev_priv
->mm
.inactive_list
);
1192 ret
= i915_gem_object_set_to_gtt_domain(obj
, write
);
1197 /* Need a new fence register? */
1198 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
) {
1199 ret
= i915_gem_object_get_fence_reg(obj
);
1204 pfn
= ((dev
->agp
->base
+ obj_priv
->gtt_offset
) >> PAGE_SHIFT
) +
1207 /* Finally, remap it using the new GTT offset */
1208 ret
= vm_insert_pfn(vma
, (unsigned long)vmf
->virtual_address
, pfn
);
1210 mutex_unlock(&dev
->struct_mutex
);
1215 return VM_FAULT_NOPAGE
;
1218 return VM_FAULT_OOM
;
1220 return VM_FAULT_SIGBUS
;
1225 * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1226 * @obj: obj in question
1228 * GEM memory mapping works by handing back to userspace a fake mmap offset
1229 * it can use in a subsequent mmap(2) call. The DRM core code then looks
1230 * up the object based on the offset and sets up the various memory mapping
1233 * This routine allocates and attaches a fake offset for @obj.
1236 i915_gem_create_mmap_offset(struct drm_gem_object
*obj
)
1238 struct drm_device
*dev
= obj
->dev
;
1239 struct drm_gem_mm
*mm
= dev
->mm_private
;
1240 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1241 struct drm_map_list
*list
;
1242 struct drm_local_map
*map
;
1245 /* Set the object up for mmap'ing */
1246 list
= &obj
->map_list
;
1247 list
->map
= kzalloc(sizeof(struct drm_map_list
), GFP_KERNEL
);
1252 map
->type
= _DRM_GEM
;
1253 map
->size
= obj
->size
;
1256 /* Get a DRM GEM mmap offset allocated... */
1257 list
->file_offset_node
= drm_mm_search_free(&mm
->offset_manager
,
1258 obj
->size
/ PAGE_SIZE
, 0, 0);
1259 if (!list
->file_offset_node
) {
1260 DRM_ERROR("failed to allocate offset for bo %d\n", obj
->name
);
1265 list
->file_offset_node
= drm_mm_get_block(list
->file_offset_node
,
1266 obj
->size
/ PAGE_SIZE
, 0);
1267 if (!list
->file_offset_node
) {
1272 list
->hash
.key
= list
->file_offset_node
->start
;
1273 if (drm_ht_insert_item(&mm
->offset_hash
, &list
->hash
)) {
1274 DRM_ERROR("failed to add to map hash\n");
1279 /* By now we should be all set, any drm_mmap request on the offset
1280 * below will get to our mmap & fault handler */
1281 obj_priv
->mmap_offset
= ((uint64_t) list
->hash
.key
) << PAGE_SHIFT
;
1286 drm_mm_put_block(list
->file_offset_node
);
1294 * i915_gem_release_mmap - remove physical page mappings
1295 * @obj: obj in question
1297 * Preserve the reservation of the mmapping with the DRM core code, but
1298 * relinquish ownership of the pages back to the system.
1300 * It is vital that we remove the page mapping if we have mapped a tiled
1301 * object through the GTT and then lose the fence register due to
1302 * resource pressure. Similarly if the object has been moved out of the
1303 * aperture, than pages mapped into userspace must be revoked. Removing the
1304 * mapping will then trigger a page fault on the next user access, allowing
1305 * fixup by i915_gem_fault().
1308 i915_gem_release_mmap(struct drm_gem_object
*obj
)
1310 struct drm_device
*dev
= obj
->dev
;
1311 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1313 if (dev
->dev_mapping
)
1314 unmap_mapping_range(dev
->dev_mapping
,
1315 obj_priv
->mmap_offset
, obj
->size
, 1);
1319 i915_gem_free_mmap_offset(struct drm_gem_object
*obj
)
1321 struct drm_device
*dev
= obj
->dev
;
1322 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1323 struct drm_gem_mm
*mm
= dev
->mm_private
;
1324 struct drm_map_list
*list
;
1326 list
= &obj
->map_list
;
1327 drm_ht_remove_item(&mm
->offset_hash
, &list
->hash
);
1329 if (list
->file_offset_node
) {
1330 drm_mm_put_block(list
->file_offset_node
);
1331 list
->file_offset_node
= NULL
;
1339 obj_priv
->mmap_offset
= 0;
1343 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1344 * @obj: object to check
1346 * Return the required GTT alignment for an object, taking into account
1347 * potential fence register mapping if needed.
1350 i915_gem_get_gtt_alignment(struct drm_gem_object
*obj
)
1352 struct drm_device
*dev
= obj
->dev
;
1353 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1357 * Minimum alignment is 4k (GTT page size), but might be greater
1358 * if a fence register is needed for the object.
1360 if (IS_I965G(dev
) || obj_priv
->tiling_mode
== I915_TILING_NONE
)
1364 * Previous chips need to be aligned to the size of the smallest
1365 * fence register that can contain the object.
1372 for (i
= start
; i
< obj
->size
; i
<<= 1)
1379 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1381 * @data: GTT mapping ioctl data
1382 * @file_priv: GEM object info
1384 * Simply returns the fake offset to userspace so it can mmap it.
1385 * The mmap call will end up in drm_gem_mmap(), which will set things
1386 * up so we can get faults in the handler above.
1388 * The fault handler will take care of binding the object into the GTT
1389 * (since it may have been evicted to make room for something), allocating
1390 * a fence register, and mapping the appropriate aperture address into
1394 i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
1395 struct drm_file
*file_priv
)
1397 struct drm_i915_gem_mmap_gtt
*args
= data
;
1398 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1399 struct drm_gem_object
*obj
;
1400 struct drm_i915_gem_object
*obj_priv
;
1403 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1406 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1410 mutex_lock(&dev
->struct_mutex
);
1412 obj_priv
= obj
->driver_private
;
1414 if (obj_priv
->madv
!= I915_MADV_WILLNEED
) {
1415 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1416 drm_gem_object_unreference(obj
);
1417 mutex_unlock(&dev
->struct_mutex
);
1422 if (!obj_priv
->mmap_offset
) {
1423 ret
= i915_gem_create_mmap_offset(obj
);
1425 drm_gem_object_unreference(obj
);
1426 mutex_unlock(&dev
->struct_mutex
);
1431 args
->offset
= obj_priv
->mmap_offset
;
1434 * Pull it into the GTT so that we have a page list (makes the
1435 * initial fault faster and any subsequent flushing possible).
1437 if (!obj_priv
->agp_mem
) {
1438 ret
= i915_gem_object_bind_to_gtt(obj
, 0);
1440 drm_gem_object_unreference(obj
);
1441 mutex_unlock(&dev
->struct_mutex
);
1444 list_add_tail(&obj_priv
->list
, &dev_priv
->mm
.inactive_list
);
1447 drm_gem_object_unreference(obj
);
1448 mutex_unlock(&dev
->struct_mutex
);
1454 i915_gem_object_put_pages(struct drm_gem_object
*obj
)
1456 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1457 int page_count
= obj
->size
/ PAGE_SIZE
;
1460 BUG_ON(obj_priv
->pages_refcount
== 0);
1461 BUG_ON(obj_priv
->madv
== __I915_MADV_PURGED
);
1463 if (--obj_priv
->pages_refcount
!= 0)
1466 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
)
1467 i915_gem_object_save_bit_17_swizzle(obj
);
1469 if (obj_priv
->madv
== I915_MADV_DONTNEED
)
1470 obj_priv
->dirty
= 0;
1472 for (i
= 0; i
< page_count
; i
++) {
1473 if (obj_priv
->pages
[i
] == NULL
)
1476 if (obj_priv
->dirty
)
1477 set_page_dirty(obj_priv
->pages
[i
]);
1479 if (obj_priv
->madv
== I915_MADV_WILLNEED
)
1480 mark_page_accessed(obj_priv
->pages
[i
]);
1482 page_cache_release(obj_priv
->pages
[i
]);
1484 obj_priv
->dirty
= 0;
1486 drm_free_large(obj_priv
->pages
);
1487 obj_priv
->pages
= NULL
;
1491 i915_gem_object_move_to_active(struct drm_gem_object
*obj
, uint32_t seqno
)
1493 struct drm_device
*dev
= obj
->dev
;
1494 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1495 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1497 /* Add a reference if we're newly entering the active list. */
1498 if (!obj_priv
->active
) {
1499 drm_gem_object_reference(obj
);
1500 obj_priv
->active
= 1;
1502 /* Move from whatever list we were on to the tail of execution. */
1503 spin_lock(&dev_priv
->mm
.active_list_lock
);
1504 list_move_tail(&obj_priv
->list
,
1505 &dev_priv
->mm
.active_list
);
1506 spin_unlock(&dev_priv
->mm
.active_list_lock
);
1507 obj_priv
->last_rendering_seqno
= seqno
;
1511 i915_gem_object_move_to_flushing(struct drm_gem_object
*obj
)
1513 struct drm_device
*dev
= obj
->dev
;
1514 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1515 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1517 BUG_ON(!obj_priv
->active
);
1518 list_move_tail(&obj_priv
->list
, &dev_priv
->mm
.flushing_list
);
1519 obj_priv
->last_rendering_seqno
= 0;
1522 /* Immediately discard the backing storage */
1524 i915_gem_object_truncate(struct drm_gem_object
*obj
)
1526 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1527 struct inode
*inode
;
1529 inode
= obj
->filp
->f_path
.dentry
->d_inode
;
1530 if (inode
->i_op
->truncate
)
1531 inode
->i_op
->truncate (inode
);
1533 obj_priv
->madv
= __I915_MADV_PURGED
;
1537 i915_gem_object_is_purgeable(struct drm_i915_gem_object
*obj_priv
)
1539 return obj_priv
->madv
== I915_MADV_DONTNEED
;
1543 i915_gem_object_move_to_inactive(struct drm_gem_object
*obj
)
1545 struct drm_device
*dev
= obj
->dev
;
1546 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1547 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1549 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
1550 if (obj_priv
->pin_count
!= 0)
1551 list_del_init(&obj_priv
->list
);
1553 list_move_tail(&obj_priv
->list
, &dev_priv
->mm
.inactive_list
);
1555 BUG_ON(!list_empty(&obj_priv
->gpu_write_list
));
1557 obj_priv
->last_rendering_seqno
= 0;
1558 if (obj_priv
->active
) {
1559 obj_priv
->active
= 0;
1560 drm_gem_object_unreference(obj
);
1562 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
1566 * Creates a new sequence number, emitting a write of it to the status page
1567 * plus an interrupt, which will trigger i915_user_interrupt_handler.
1569 * Must be called with struct_lock held.
1571 * Returned sequence numbers are nonzero on success.
1574 i915_add_request(struct drm_device
*dev
, struct drm_file
*file_priv
,
1575 uint32_t flush_domains
)
1577 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1578 struct drm_i915_file_private
*i915_file_priv
= NULL
;
1579 struct drm_i915_gem_request
*request
;
1584 if (file_priv
!= NULL
)
1585 i915_file_priv
= file_priv
->driver_priv
;
1587 request
= kzalloc(sizeof(*request
), GFP_KERNEL
);
1588 if (request
== NULL
)
1591 /* Grab the seqno we're going to make this request be, and bump the
1592 * next (skipping 0 so it can be the reserved no-seqno value).
1594 seqno
= dev_priv
->mm
.next_gem_seqno
;
1595 dev_priv
->mm
.next_gem_seqno
++;
1596 if (dev_priv
->mm
.next_gem_seqno
== 0)
1597 dev_priv
->mm
.next_gem_seqno
++;
1600 OUT_RING(MI_STORE_DWORD_INDEX
);
1601 OUT_RING(I915_GEM_HWS_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
);
1604 OUT_RING(MI_USER_INTERRUPT
);
1607 DRM_DEBUG_DRIVER("%d\n", seqno
);
1609 request
->seqno
= seqno
;
1610 request
->emitted_jiffies
= jiffies
;
1611 was_empty
= list_empty(&dev_priv
->mm
.request_list
);
1612 list_add_tail(&request
->list
, &dev_priv
->mm
.request_list
);
1613 if (i915_file_priv
) {
1614 list_add_tail(&request
->client_list
,
1615 &i915_file_priv
->mm
.request_list
);
1617 INIT_LIST_HEAD(&request
->client_list
);
1620 /* Associate any objects on the flushing list matching the write
1621 * domain we're flushing with our flush.
1623 if (flush_domains
!= 0) {
1624 struct drm_i915_gem_object
*obj_priv
, *next
;
1626 list_for_each_entry_safe(obj_priv
, next
,
1627 &dev_priv
->mm
.gpu_write_list
,
1629 struct drm_gem_object
*obj
= obj_priv
->obj
;
1631 if ((obj
->write_domain
& flush_domains
) ==
1632 obj
->write_domain
) {
1633 uint32_t old_write_domain
= obj
->write_domain
;
1635 obj
->write_domain
= 0;
1636 list_del_init(&obj_priv
->gpu_write_list
);
1637 i915_gem_object_move_to_active(obj
, seqno
);
1639 trace_i915_gem_object_change_domain(obj
,
1647 if (!dev_priv
->mm
.suspended
) {
1648 mod_timer(&dev_priv
->hangcheck_timer
, jiffies
+ DRM_I915_HANGCHECK_PERIOD
);
1650 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, HZ
);
1656 * Command execution barrier
1658 * Ensures that all commands in the ring are finished
1659 * before signalling the CPU
1662 i915_retire_commands(struct drm_device
*dev
)
1664 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1665 uint32_t cmd
= MI_FLUSH
| MI_NO_WRITE_FLUSH
;
1666 uint32_t flush_domains
= 0;
1669 /* The sampler always gets flushed on i965 (sigh) */
1671 flush_domains
|= I915_GEM_DOMAIN_SAMPLER
;
1674 OUT_RING(0); /* noop */
1676 return flush_domains
;
1680 * Moves buffers associated only with the given active seqno from the active
1681 * to inactive list, potentially freeing them.
1684 i915_gem_retire_request(struct drm_device
*dev
,
1685 struct drm_i915_gem_request
*request
)
1687 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1689 trace_i915_gem_request_retire(dev
, request
->seqno
);
1691 /* Move any buffers on the active list that are no longer referenced
1692 * by the ringbuffer to the flushing/inactive lists as appropriate.
1694 spin_lock(&dev_priv
->mm
.active_list_lock
);
1695 while (!list_empty(&dev_priv
->mm
.active_list
)) {
1696 struct drm_gem_object
*obj
;
1697 struct drm_i915_gem_object
*obj_priv
;
1699 obj_priv
= list_first_entry(&dev_priv
->mm
.active_list
,
1700 struct drm_i915_gem_object
,
1702 obj
= obj_priv
->obj
;
1704 /* If the seqno being retired doesn't match the oldest in the
1705 * list, then the oldest in the list must still be newer than
1708 if (obj_priv
->last_rendering_seqno
!= request
->seqno
)
1712 DRM_INFO("%s: retire %d moves to inactive list %p\n",
1713 __func__
, request
->seqno
, obj
);
1716 if (obj
->write_domain
!= 0)
1717 i915_gem_object_move_to_flushing(obj
);
1719 /* Take a reference on the object so it won't be
1720 * freed while the spinlock is held. The list
1721 * protection for this spinlock is safe when breaking
1722 * the lock like this since the next thing we do
1723 * is just get the head of the list again.
1725 drm_gem_object_reference(obj
);
1726 i915_gem_object_move_to_inactive(obj
);
1727 spin_unlock(&dev_priv
->mm
.active_list_lock
);
1728 drm_gem_object_unreference(obj
);
1729 spin_lock(&dev_priv
->mm
.active_list_lock
);
1733 spin_unlock(&dev_priv
->mm
.active_list_lock
);
1737 * Returns true if seq1 is later than seq2.
1740 i915_seqno_passed(uint32_t seq1
, uint32_t seq2
)
1742 return (int32_t)(seq1
- seq2
) >= 0;
1746 i915_get_gem_seqno(struct drm_device
*dev
)
1748 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1750 return READ_HWSP(dev_priv
, I915_GEM_HWS_INDEX
);
1754 * This function clears the request list as sequence numbers are passed.
1757 i915_gem_retire_requests(struct drm_device
*dev
)
1759 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1762 if (!dev_priv
->hw_status_page
|| list_empty(&dev_priv
->mm
.request_list
))
1765 seqno
= i915_get_gem_seqno(dev
);
1767 while (!list_empty(&dev_priv
->mm
.request_list
)) {
1768 struct drm_i915_gem_request
*request
;
1769 uint32_t retiring_seqno
;
1771 request
= list_first_entry(&dev_priv
->mm
.request_list
,
1772 struct drm_i915_gem_request
,
1774 retiring_seqno
= request
->seqno
;
1776 if (i915_seqno_passed(seqno
, retiring_seqno
) ||
1777 atomic_read(&dev_priv
->mm
.wedged
)) {
1778 i915_gem_retire_request(dev
, request
);
1780 list_del(&request
->list
);
1781 list_del(&request
->client_list
);
1787 if (unlikely (dev_priv
->trace_irq_seqno
&&
1788 i915_seqno_passed(dev_priv
->trace_irq_seqno
, seqno
))) {
1789 i915_user_irq_put(dev
);
1790 dev_priv
->trace_irq_seqno
= 0;
1795 i915_gem_retire_work_handler(struct work_struct
*work
)
1797 drm_i915_private_t
*dev_priv
;
1798 struct drm_device
*dev
;
1800 dev_priv
= container_of(work
, drm_i915_private_t
,
1801 mm
.retire_work
.work
);
1802 dev
= dev_priv
->dev
;
1804 mutex_lock(&dev
->struct_mutex
);
1805 i915_gem_retire_requests(dev
);
1806 if (!dev_priv
->mm
.suspended
&&
1807 !list_empty(&dev_priv
->mm
.request_list
))
1808 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, HZ
);
1809 mutex_unlock(&dev
->struct_mutex
);
1813 i915_do_wait_request(struct drm_device
*dev
, uint32_t seqno
, int interruptible
)
1815 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1821 if (atomic_read(&dev_priv
->mm
.wedged
))
1824 if (!i915_seqno_passed(i915_get_gem_seqno(dev
), seqno
)) {
1825 if (IS_IRONLAKE(dev
))
1826 ier
= I915_READ(DEIER
) | I915_READ(GTIER
);
1828 ier
= I915_READ(IER
);
1830 DRM_ERROR("something (likely vbetool) disabled "
1831 "interrupts, re-enabling\n");
1832 i915_driver_irq_preinstall(dev
);
1833 i915_driver_irq_postinstall(dev
);
1836 trace_i915_gem_request_wait_begin(dev
, seqno
);
1838 dev_priv
->mm
.waiting_gem_seqno
= seqno
;
1839 i915_user_irq_get(dev
);
1841 ret
= wait_event_interruptible(dev_priv
->irq_queue
,
1842 i915_seqno_passed(i915_get_gem_seqno(dev
), seqno
) ||
1843 atomic_read(&dev_priv
->mm
.wedged
));
1845 wait_event(dev_priv
->irq_queue
,
1846 i915_seqno_passed(i915_get_gem_seqno(dev
), seqno
) ||
1847 atomic_read(&dev_priv
->mm
.wedged
));
1849 i915_user_irq_put(dev
);
1850 dev_priv
->mm
.waiting_gem_seqno
= 0;
1852 trace_i915_gem_request_wait_end(dev
, seqno
);
1854 if (atomic_read(&dev_priv
->mm
.wedged
))
1857 if (ret
&& ret
!= -ERESTARTSYS
)
1858 DRM_ERROR("%s returns %d (awaiting %d at %d)\n",
1859 __func__
, ret
, seqno
, i915_get_gem_seqno(dev
));
1861 /* Directly dispatch request retiring. While we have the work queue
1862 * to handle this, the waiter on a request often wants an associated
1863 * buffer to have made it to the inactive list, and we would need
1864 * a separate wait queue to handle that.
1867 i915_gem_retire_requests(dev
);
1873 * Waits for a sequence number to be signaled, and cleans up the
1874 * request and object lists appropriately for that event.
1877 i915_wait_request(struct drm_device
*dev
, uint32_t seqno
)
1879 return i915_do_wait_request(dev
, seqno
, 1);
1883 i915_gem_flush(struct drm_device
*dev
,
1884 uint32_t invalidate_domains
,
1885 uint32_t flush_domains
)
1887 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1892 DRM_INFO("%s: invalidate %08x flush %08x\n", __func__
,
1893 invalidate_domains
, flush_domains
);
1895 trace_i915_gem_request_flush(dev
, dev_priv
->mm
.next_gem_seqno
,
1896 invalidate_domains
, flush_domains
);
1898 if (flush_domains
& I915_GEM_DOMAIN_CPU
)
1899 drm_agp_chipset_flush(dev
);
1901 if ((invalidate_domains
| flush_domains
) & I915_GEM_GPU_DOMAINS
) {
1903 * read/write caches:
1905 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
1906 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
1907 * also flushed at 2d versus 3d pipeline switches.
1911 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
1912 * MI_READ_FLUSH is set, and is always flushed on 965.
1914 * I915_GEM_DOMAIN_COMMAND may not exist?
1916 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
1917 * invalidated when MI_EXE_FLUSH is set.
1919 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
1920 * invalidated with every MI_FLUSH.
1924 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
1925 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
1926 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
1927 * are flushed at any MI_FLUSH.
1930 cmd
= MI_FLUSH
| MI_NO_WRITE_FLUSH
;
1931 if ((invalidate_domains
|flush_domains
) &
1932 I915_GEM_DOMAIN_RENDER
)
1933 cmd
&= ~MI_NO_WRITE_FLUSH
;
1934 if (!IS_I965G(dev
)) {
1936 * On the 965, the sampler cache always gets flushed
1937 * and this bit is reserved.
1939 if (invalidate_domains
& I915_GEM_DOMAIN_SAMPLER
)
1940 cmd
|= MI_READ_FLUSH
;
1942 if (invalidate_domains
& I915_GEM_DOMAIN_INSTRUCTION
)
1943 cmd
|= MI_EXE_FLUSH
;
1946 DRM_INFO("%s: queue flush %08x to ring\n", __func__
, cmd
);
1956 * Ensures that all rendering to the object has completed and the object is
1957 * safe to unbind from the GTT or access from the CPU.
1960 i915_gem_object_wait_rendering(struct drm_gem_object
*obj
)
1962 struct drm_device
*dev
= obj
->dev
;
1963 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1966 /* This function only exists to support waiting for existing rendering,
1967 * not for emitting required flushes.
1969 BUG_ON((obj
->write_domain
& I915_GEM_GPU_DOMAINS
) != 0);
1971 /* If there is rendering queued on the buffer being evicted, wait for
1974 if (obj_priv
->active
) {
1976 DRM_INFO("%s: object %p wait for seqno %08x\n",
1977 __func__
, obj
, obj_priv
->last_rendering_seqno
);
1979 ret
= i915_wait_request(dev
, obj_priv
->last_rendering_seqno
);
1988 * Unbinds an object from the GTT aperture.
1991 i915_gem_object_unbind(struct drm_gem_object
*obj
)
1993 struct drm_device
*dev
= obj
->dev
;
1994 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1998 DRM_INFO("%s:%d %p\n", __func__
, __LINE__
, obj
);
1999 DRM_INFO("gtt_space %p\n", obj_priv
->gtt_space
);
2001 if (obj_priv
->gtt_space
== NULL
)
2004 if (obj_priv
->pin_count
!= 0) {
2005 DRM_ERROR("Attempting to unbind pinned buffer\n");
2009 /* blow away mappings if mapped through GTT */
2010 i915_gem_release_mmap(obj
);
2012 /* Move the object to the CPU domain to ensure that
2013 * any possible CPU writes while it's not in the GTT
2014 * are flushed when we go to remap it. This will
2015 * also ensure that all pending GPU writes are finished
2018 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
2020 if (ret
!= -ERESTARTSYS
)
2021 DRM_ERROR("set_domain failed: %d\n", ret
);
2025 BUG_ON(obj_priv
->active
);
2027 /* release the fence reg _after_ flushing */
2028 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
)
2029 i915_gem_clear_fence_reg(obj
);
2031 if (obj_priv
->agp_mem
!= NULL
) {
2032 drm_unbind_agp(obj_priv
->agp_mem
);
2033 drm_free_agp(obj_priv
->agp_mem
, obj
->size
/ PAGE_SIZE
);
2034 obj_priv
->agp_mem
= NULL
;
2037 i915_gem_object_put_pages(obj
);
2038 BUG_ON(obj_priv
->pages_refcount
);
2040 if (obj_priv
->gtt_space
) {
2041 atomic_dec(&dev
->gtt_count
);
2042 atomic_sub(obj
->size
, &dev
->gtt_memory
);
2044 drm_mm_put_block(obj_priv
->gtt_space
);
2045 obj_priv
->gtt_space
= NULL
;
2048 /* Remove ourselves from the LRU list if present. */
2049 if (!list_empty(&obj_priv
->list
))
2050 list_del_init(&obj_priv
->list
);
2052 if (i915_gem_object_is_purgeable(obj_priv
))
2053 i915_gem_object_truncate(obj
);
2055 trace_i915_gem_object_unbind(obj
);
2060 static struct drm_gem_object
*
2061 i915_gem_find_inactive_object(struct drm_device
*dev
, int min_size
)
2063 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2064 struct drm_i915_gem_object
*obj_priv
;
2065 struct drm_gem_object
*best
= NULL
;
2066 struct drm_gem_object
*first
= NULL
;
2068 /* Try to find the smallest clean object */
2069 list_for_each_entry(obj_priv
, &dev_priv
->mm
.inactive_list
, list
) {
2070 struct drm_gem_object
*obj
= obj_priv
->obj
;
2071 if (obj
->size
>= min_size
) {
2072 if ((!obj_priv
->dirty
||
2073 i915_gem_object_is_purgeable(obj_priv
)) &&
2074 (!best
|| obj
->size
< best
->size
)) {
2076 if (best
->size
== min_size
)
2084 return best
? best
: first
;
2088 i915_gem_evict_everything(struct drm_device
*dev
)
2090 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2095 spin_lock(&dev_priv
->mm
.active_list_lock
);
2096 lists_empty
= (list_empty(&dev_priv
->mm
.inactive_list
) &&
2097 list_empty(&dev_priv
->mm
.flushing_list
) &&
2098 list_empty(&dev_priv
->mm
.active_list
));
2099 spin_unlock(&dev_priv
->mm
.active_list_lock
);
2104 /* Flush everything (on to the inactive lists) and evict */
2105 i915_gem_flush(dev
, I915_GEM_GPU_DOMAINS
, I915_GEM_GPU_DOMAINS
);
2106 seqno
= i915_add_request(dev
, NULL
, I915_GEM_GPU_DOMAINS
);
2110 ret
= i915_wait_request(dev
, seqno
);
2114 BUG_ON(!list_empty(&dev_priv
->mm
.flushing_list
));
2116 ret
= i915_gem_evict_from_inactive_list(dev
);
2120 spin_lock(&dev_priv
->mm
.active_list_lock
);
2121 lists_empty
= (list_empty(&dev_priv
->mm
.inactive_list
) &&
2122 list_empty(&dev_priv
->mm
.flushing_list
) &&
2123 list_empty(&dev_priv
->mm
.active_list
));
2124 spin_unlock(&dev_priv
->mm
.active_list_lock
);
2125 BUG_ON(!lists_empty
);
2131 i915_gem_evict_something(struct drm_device
*dev
, int min_size
)
2133 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2134 struct drm_gem_object
*obj
;
2138 i915_gem_retire_requests(dev
);
2140 /* If there's an inactive buffer available now, grab it
2143 obj
= i915_gem_find_inactive_object(dev
, min_size
);
2145 struct drm_i915_gem_object
*obj_priv
;
2148 DRM_INFO("%s: evicting %p\n", __func__
, obj
);
2150 obj_priv
= obj
->driver_private
;
2151 BUG_ON(obj_priv
->pin_count
!= 0);
2152 BUG_ON(obj_priv
->active
);
2154 /* Wait on the rendering and unbind the buffer. */
2155 return i915_gem_object_unbind(obj
);
2158 /* If we didn't get anything, but the ring is still processing
2159 * things, wait for the next to finish and hopefully leave us
2160 * a buffer to evict.
2162 if (!list_empty(&dev_priv
->mm
.request_list
)) {
2163 struct drm_i915_gem_request
*request
;
2165 request
= list_first_entry(&dev_priv
->mm
.request_list
,
2166 struct drm_i915_gem_request
,
2169 ret
= i915_wait_request(dev
, request
->seqno
);
2176 /* If we didn't have anything on the request list but there
2177 * are buffers awaiting a flush, emit one and try again.
2178 * When we wait on it, those buffers waiting for that flush
2179 * will get moved to inactive.
2181 if (!list_empty(&dev_priv
->mm
.flushing_list
)) {
2182 struct drm_i915_gem_object
*obj_priv
;
2184 /* Find an object that we can immediately reuse */
2185 list_for_each_entry(obj_priv
, &dev_priv
->mm
.flushing_list
, list
) {
2186 obj
= obj_priv
->obj
;
2187 if (obj
->size
>= min_size
)
2199 seqno
= i915_add_request(dev
, NULL
, obj
->write_domain
);
2203 ret
= i915_wait_request(dev
, seqno
);
2211 /* If we didn't do any of the above, there's no single buffer
2212 * large enough to swap out for the new one, so just evict
2213 * everything and start again. (This should be rare.)
2215 if (!list_empty (&dev_priv
->mm
.inactive_list
))
2216 return i915_gem_evict_from_inactive_list(dev
);
2218 return i915_gem_evict_everything(dev
);
2223 i915_gem_object_get_pages(struct drm_gem_object
*obj
,
2226 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2228 struct address_space
*mapping
;
2229 struct inode
*inode
;
2233 if (obj_priv
->pages_refcount
++ != 0)
2236 /* Get the list of pages out of our struct file. They'll be pinned
2237 * at this point until we release them.
2239 page_count
= obj
->size
/ PAGE_SIZE
;
2240 BUG_ON(obj_priv
->pages
!= NULL
);
2241 obj_priv
->pages
= drm_calloc_large(page_count
, sizeof(struct page
*));
2242 if (obj_priv
->pages
== NULL
) {
2243 obj_priv
->pages_refcount
--;
2247 inode
= obj
->filp
->f_path
.dentry
->d_inode
;
2248 mapping
= inode
->i_mapping
;
2249 for (i
= 0; i
< page_count
; i
++) {
2250 page
= read_cache_page_gfp(mapping
, i
,
2251 mapping_gfp_mask (mapping
) |
2255 ret
= PTR_ERR(page
);
2256 i915_gem_object_put_pages(obj
);
2259 obj_priv
->pages
[i
] = page
;
2262 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
)
2263 i915_gem_object_do_bit_17_swizzle(obj
);
2268 static void i965_write_fence_reg(struct drm_i915_fence_reg
*reg
)
2270 struct drm_gem_object
*obj
= reg
->obj
;
2271 struct drm_device
*dev
= obj
->dev
;
2272 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2273 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2274 int regnum
= obj_priv
->fence_reg
;
2277 val
= (uint64_t)((obj_priv
->gtt_offset
+ obj
->size
- 4096) &
2279 val
|= obj_priv
->gtt_offset
& 0xfffff000;
2280 val
|= ((obj_priv
->stride
/ 128) - 1) << I965_FENCE_PITCH_SHIFT
;
2281 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2282 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
2283 val
|= I965_FENCE_REG_VALID
;
2285 I915_WRITE64(FENCE_REG_965_0
+ (regnum
* 8), val
);
2288 static void i915_write_fence_reg(struct drm_i915_fence_reg
*reg
)
2290 struct drm_gem_object
*obj
= reg
->obj
;
2291 struct drm_device
*dev
= obj
->dev
;
2292 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2293 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2294 int regnum
= obj_priv
->fence_reg
;
2296 uint32_t fence_reg
, val
;
2299 if ((obj_priv
->gtt_offset
& ~I915_FENCE_START_MASK
) ||
2300 (obj_priv
->gtt_offset
& (obj
->size
- 1))) {
2301 WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
2302 __func__
, obj_priv
->gtt_offset
, obj
->size
);
2306 if (obj_priv
->tiling_mode
== I915_TILING_Y
&&
2307 HAS_128_BYTE_Y_TILING(dev
))
2312 /* Note: pitch better be a power of two tile widths */
2313 pitch_val
= obj_priv
->stride
/ tile_width
;
2314 pitch_val
= ffs(pitch_val
) - 1;
2316 val
= obj_priv
->gtt_offset
;
2317 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2318 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2319 val
|= I915_FENCE_SIZE_BITS(obj
->size
);
2320 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2321 val
|= I830_FENCE_REG_VALID
;
2324 fence_reg
= FENCE_REG_830_0
+ (regnum
* 4);
2326 fence_reg
= FENCE_REG_945_8
+ ((regnum
- 8) * 4);
2327 I915_WRITE(fence_reg
, val
);
2330 static void i830_write_fence_reg(struct drm_i915_fence_reg
*reg
)
2332 struct drm_gem_object
*obj
= reg
->obj
;
2333 struct drm_device
*dev
= obj
->dev
;
2334 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2335 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2336 int regnum
= obj_priv
->fence_reg
;
2339 uint32_t fence_size_bits
;
2341 if ((obj_priv
->gtt_offset
& ~I830_FENCE_START_MASK
) ||
2342 (obj_priv
->gtt_offset
& (obj
->size
- 1))) {
2343 WARN(1, "%s: object 0x%08x not 512K or size aligned\n",
2344 __func__
, obj_priv
->gtt_offset
);
2348 pitch_val
= obj_priv
->stride
/ 128;
2349 pitch_val
= ffs(pitch_val
) - 1;
2350 WARN_ON(pitch_val
> I830_FENCE_MAX_PITCH_VAL
);
2352 val
= obj_priv
->gtt_offset
;
2353 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2354 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2355 fence_size_bits
= I830_FENCE_SIZE_BITS(obj
->size
);
2356 WARN_ON(fence_size_bits
& ~0x00000f00);
2357 val
|= fence_size_bits
;
2358 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2359 val
|= I830_FENCE_REG_VALID
;
2361 I915_WRITE(FENCE_REG_830_0
+ (regnum
* 4), val
);
2365 * i915_gem_object_get_fence_reg - set up a fence reg for an object
2366 * @obj: object to map through a fence reg
2368 * When mapping objects through the GTT, userspace wants to be able to write
2369 * to them without having to worry about swizzling if the object is tiled.
2371 * This function walks the fence regs looking for a free one for @obj,
2372 * stealing one if it can't find any.
2374 * It then sets up the reg based on the object's properties: address, pitch
2375 * and tiling format.
2378 i915_gem_object_get_fence_reg(struct drm_gem_object
*obj
)
2380 struct drm_device
*dev
= obj
->dev
;
2381 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2382 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2383 struct drm_i915_fence_reg
*reg
= NULL
;
2384 struct drm_i915_gem_object
*old_obj_priv
= NULL
;
2387 /* Just update our place in the LRU if our fence is getting used. */
2388 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
) {
2389 list_move_tail(&obj_priv
->fence_list
, &dev_priv
->mm
.fence_list
);
2393 switch (obj_priv
->tiling_mode
) {
2394 case I915_TILING_NONE
:
2395 WARN(1, "allocating a fence for non-tiled object?\n");
2398 if (!obj_priv
->stride
)
2400 WARN((obj_priv
->stride
& (512 - 1)),
2401 "object 0x%08x is X tiled but has non-512B pitch\n",
2402 obj_priv
->gtt_offset
);
2405 if (!obj_priv
->stride
)
2407 WARN((obj_priv
->stride
& (128 - 1)),
2408 "object 0x%08x is Y tiled but has non-128B pitch\n",
2409 obj_priv
->gtt_offset
);
2413 /* First try to find a free reg */
2415 for (i
= dev_priv
->fence_reg_start
; i
< dev_priv
->num_fence_regs
; i
++) {
2416 reg
= &dev_priv
->fence_regs
[i
];
2420 old_obj_priv
= reg
->obj
->driver_private
;
2421 if (!old_obj_priv
->pin_count
)
2425 /* None available, try to steal one or wait for a user to finish */
2426 if (i
== dev_priv
->num_fence_regs
) {
2427 struct drm_gem_object
*old_obj
= NULL
;
2432 list_for_each_entry(old_obj_priv
, &dev_priv
->mm
.fence_list
,
2434 old_obj
= old_obj_priv
->obj
;
2436 if (old_obj_priv
->pin_count
)
2439 /* Take a reference, as otherwise the wait_rendering
2440 * below may cause the object to get freed out from
2443 drm_gem_object_reference(old_obj
);
2445 /* i915 uses fences for GPU access to tiled buffers */
2446 if (IS_I965G(dev
) || !old_obj_priv
->active
)
2449 /* This brings the object to the head of the LRU if it
2450 * had been written to. The only way this should
2451 * result in us waiting longer than the expected
2452 * optimal amount of time is if there was a
2453 * fence-using buffer later that was read-only.
2455 i915_gem_object_flush_gpu_write_domain(old_obj
);
2456 ret
= i915_gem_object_wait_rendering(old_obj
);
2458 drm_gem_object_unreference(old_obj
);
2466 * Zap this virtual mapping so we can set up a fence again
2467 * for this object next time we need it.
2469 i915_gem_release_mmap(old_obj
);
2471 i
= old_obj_priv
->fence_reg
;
2472 reg
= &dev_priv
->fence_regs
[i
];
2474 old_obj_priv
->fence_reg
= I915_FENCE_REG_NONE
;
2475 list_del_init(&old_obj_priv
->fence_list
);
2477 drm_gem_object_unreference(old_obj
);
2480 obj_priv
->fence_reg
= i
;
2481 list_add_tail(&obj_priv
->fence_list
, &dev_priv
->mm
.fence_list
);
2486 i965_write_fence_reg(reg
);
2487 else if (IS_I9XX(dev
))
2488 i915_write_fence_reg(reg
);
2490 i830_write_fence_reg(reg
);
2492 trace_i915_gem_object_get_fence(obj
, i
, obj_priv
->tiling_mode
);
2498 * i915_gem_clear_fence_reg - clear out fence register info
2499 * @obj: object to clear
2501 * Zeroes out the fence register itself and clears out the associated
2502 * data structures in dev_priv and obj_priv.
2505 i915_gem_clear_fence_reg(struct drm_gem_object
*obj
)
2507 struct drm_device
*dev
= obj
->dev
;
2508 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2509 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2512 I915_WRITE64(FENCE_REG_965_0
+ (obj_priv
->fence_reg
* 8), 0);
2516 if (obj_priv
->fence_reg
< 8)
2517 fence_reg
= FENCE_REG_830_0
+ obj_priv
->fence_reg
* 4;
2519 fence_reg
= FENCE_REG_945_8
+ (obj_priv
->fence_reg
-
2522 I915_WRITE(fence_reg
, 0);
2525 dev_priv
->fence_regs
[obj_priv
->fence_reg
].obj
= NULL
;
2526 obj_priv
->fence_reg
= I915_FENCE_REG_NONE
;
2527 list_del_init(&obj_priv
->fence_list
);
2531 * i915_gem_object_put_fence_reg - waits on outstanding fenced access
2532 * to the buffer to finish, and then resets the fence register.
2533 * @obj: tiled object holding a fence register.
2535 * Zeroes out the fence register itself and clears out the associated
2536 * data structures in dev_priv and obj_priv.
2539 i915_gem_object_put_fence_reg(struct drm_gem_object
*obj
)
2541 struct drm_device
*dev
= obj
->dev
;
2542 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2544 if (obj_priv
->fence_reg
== I915_FENCE_REG_NONE
)
2547 /* On the i915, GPU access to tiled buffers is via a fence,
2548 * therefore we must wait for any outstanding access to complete
2549 * before clearing the fence.
2551 if (!IS_I965G(dev
)) {
2554 i915_gem_object_flush_gpu_write_domain(obj
);
2555 i915_gem_object_flush_gtt_write_domain(obj
);
2556 ret
= i915_gem_object_wait_rendering(obj
);
2561 i915_gem_clear_fence_reg (obj
);
2567 * Finds free space in the GTT aperture and binds the object there.
2570 i915_gem_object_bind_to_gtt(struct drm_gem_object
*obj
, unsigned alignment
)
2572 struct drm_device
*dev
= obj
->dev
;
2573 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2574 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2575 struct drm_mm_node
*free_space
;
2576 gfp_t gfpmask
= __GFP_NORETRY
| __GFP_NOWARN
;
2579 if (obj_priv
->madv
!= I915_MADV_WILLNEED
) {
2580 DRM_ERROR("Attempting to bind a purgeable object\n");
2585 alignment
= i915_gem_get_gtt_alignment(obj
);
2586 if (alignment
& (i915_gem_get_gtt_alignment(obj
) - 1)) {
2587 DRM_ERROR("Invalid object alignment requested %u\n", alignment
);
2592 free_space
= drm_mm_search_free(&dev_priv
->mm
.gtt_space
,
2593 obj
->size
, alignment
, 0);
2594 if (free_space
!= NULL
) {
2595 obj_priv
->gtt_space
= drm_mm_get_block(free_space
, obj
->size
,
2597 if (obj_priv
->gtt_space
!= NULL
) {
2598 obj_priv
->gtt_space
->private = obj
;
2599 obj_priv
->gtt_offset
= obj_priv
->gtt_space
->start
;
2602 if (obj_priv
->gtt_space
== NULL
) {
2603 /* If the gtt is empty and we're still having trouble
2604 * fitting our object in, we're out of memory.
2607 DRM_INFO("%s: GTT full, evicting something\n", __func__
);
2609 ret
= i915_gem_evict_something(dev
, obj
->size
);
2617 DRM_INFO("Binding object of size %zd at 0x%08x\n",
2618 obj
->size
, obj_priv
->gtt_offset
);
2620 ret
= i915_gem_object_get_pages(obj
, gfpmask
);
2622 drm_mm_put_block(obj_priv
->gtt_space
);
2623 obj_priv
->gtt_space
= NULL
;
2625 if (ret
== -ENOMEM
) {
2626 /* first try to clear up some space from the GTT */
2627 ret
= i915_gem_evict_something(dev
, obj
->size
);
2629 /* now try to shrink everyone else */
2644 /* Create an AGP memory structure pointing at our pages, and bind it
2647 obj_priv
->agp_mem
= drm_agp_bind_pages(dev
,
2649 obj
->size
>> PAGE_SHIFT
,
2650 obj_priv
->gtt_offset
,
2651 obj_priv
->agp_type
);
2652 if (obj_priv
->agp_mem
== NULL
) {
2653 i915_gem_object_put_pages(obj
);
2654 drm_mm_put_block(obj_priv
->gtt_space
);
2655 obj_priv
->gtt_space
= NULL
;
2657 ret
= i915_gem_evict_something(dev
, obj
->size
);
2663 atomic_inc(&dev
->gtt_count
);
2664 atomic_add(obj
->size
, &dev
->gtt_memory
);
2666 /* Assert that the object is not currently in any GPU domain. As it
2667 * wasn't in the GTT, there shouldn't be any way it could have been in
2670 BUG_ON(obj
->read_domains
& I915_GEM_GPU_DOMAINS
);
2671 BUG_ON(obj
->write_domain
& I915_GEM_GPU_DOMAINS
);
2673 trace_i915_gem_object_bind(obj
, obj_priv
->gtt_offset
);
2679 i915_gem_clflush_object(struct drm_gem_object
*obj
)
2681 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2683 /* If we don't have a page list set up, then we're not pinned
2684 * to GPU, and we can ignore the cache flush because it'll happen
2685 * again at bind time.
2687 if (obj_priv
->pages
== NULL
)
2690 trace_i915_gem_object_clflush(obj
);
2692 drm_clflush_pages(obj_priv
->pages
, obj
->size
/ PAGE_SIZE
);
2695 /** Flushes any GPU write domain for the object if it's dirty. */
2697 i915_gem_object_flush_gpu_write_domain(struct drm_gem_object
*obj
)
2699 struct drm_device
*dev
= obj
->dev
;
2701 uint32_t old_write_domain
;
2703 if ((obj
->write_domain
& I915_GEM_GPU_DOMAINS
) == 0)
2706 /* Queue the GPU write cache flushing we need. */
2707 old_write_domain
= obj
->write_domain
;
2708 i915_gem_flush(dev
, 0, obj
->write_domain
);
2709 seqno
= i915_add_request(dev
, NULL
, obj
->write_domain
);
2710 BUG_ON(obj
->write_domain
);
2711 i915_gem_object_move_to_active(obj
, seqno
);
2713 trace_i915_gem_object_change_domain(obj
,
2718 /** Flushes the GTT write domain for the object if it's dirty. */
2720 i915_gem_object_flush_gtt_write_domain(struct drm_gem_object
*obj
)
2722 uint32_t old_write_domain
;
2724 if (obj
->write_domain
!= I915_GEM_DOMAIN_GTT
)
2727 /* No actual flushing is required for the GTT write domain. Writes
2728 * to it immediately go to main memory as far as we know, so there's
2729 * no chipset flush. It also doesn't land in render cache.
2731 old_write_domain
= obj
->write_domain
;
2732 obj
->write_domain
= 0;
2734 trace_i915_gem_object_change_domain(obj
,
2739 /** Flushes the CPU write domain for the object if it's dirty. */
2741 i915_gem_object_flush_cpu_write_domain(struct drm_gem_object
*obj
)
2743 struct drm_device
*dev
= obj
->dev
;
2744 uint32_t old_write_domain
;
2746 if (obj
->write_domain
!= I915_GEM_DOMAIN_CPU
)
2749 i915_gem_clflush_object(obj
);
2750 drm_agp_chipset_flush(dev
);
2751 old_write_domain
= obj
->write_domain
;
2752 obj
->write_domain
= 0;
2754 trace_i915_gem_object_change_domain(obj
,
2760 i915_gem_object_flush_write_domain(struct drm_gem_object
*obj
)
2762 switch (obj
->write_domain
) {
2763 case I915_GEM_DOMAIN_GTT
:
2764 i915_gem_object_flush_gtt_write_domain(obj
);
2766 case I915_GEM_DOMAIN_CPU
:
2767 i915_gem_object_flush_cpu_write_domain(obj
);
2770 i915_gem_object_flush_gpu_write_domain(obj
);
2776 * Moves a single object to the GTT read, and possibly write domain.
2778 * This function returns when the move is complete, including waiting on
2782 i915_gem_object_set_to_gtt_domain(struct drm_gem_object
*obj
, int write
)
2784 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2785 uint32_t old_write_domain
, old_read_domains
;
2788 /* Not valid to be called on unbound objects. */
2789 if (obj_priv
->gtt_space
== NULL
)
2792 i915_gem_object_flush_gpu_write_domain(obj
);
2793 /* Wait on any GPU rendering and flushing to occur. */
2794 ret
= i915_gem_object_wait_rendering(obj
);
2798 old_write_domain
= obj
->write_domain
;
2799 old_read_domains
= obj
->read_domains
;
2801 /* If we're writing through the GTT domain, then CPU and GPU caches
2802 * will need to be invalidated at next use.
2805 obj
->read_domains
&= I915_GEM_DOMAIN_GTT
;
2807 i915_gem_object_flush_cpu_write_domain(obj
);
2809 /* It should now be out of any other write domains, and we can update
2810 * the domain values for our changes.
2812 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
2813 obj
->read_domains
|= I915_GEM_DOMAIN_GTT
;
2815 obj
->write_domain
= I915_GEM_DOMAIN_GTT
;
2816 obj_priv
->dirty
= 1;
2819 trace_i915_gem_object_change_domain(obj
,
2827 * Prepare buffer for display plane. Use uninterruptible for possible flush
2828 * wait, as in modesetting process we're not supposed to be interrupted.
2831 i915_gem_object_set_to_display_plane(struct drm_gem_object
*obj
)
2833 struct drm_device
*dev
= obj
->dev
;
2834 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2835 uint32_t old_write_domain
, old_read_domains
;
2838 /* Not valid to be called on unbound objects. */
2839 if (obj_priv
->gtt_space
== NULL
)
2842 i915_gem_object_flush_gpu_write_domain(obj
);
2844 /* Wait on any GPU rendering and flushing to occur. */
2845 if (obj_priv
->active
) {
2847 DRM_INFO("%s: object %p wait for seqno %08x\n",
2848 __func__
, obj
, obj_priv
->last_rendering_seqno
);
2850 ret
= i915_do_wait_request(dev
, obj_priv
->last_rendering_seqno
, 0);
2855 old_write_domain
= obj
->write_domain
;
2856 old_read_domains
= obj
->read_domains
;
2858 obj
->read_domains
&= I915_GEM_DOMAIN_GTT
;
2860 i915_gem_object_flush_cpu_write_domain(obj
);
2862 /* It should now be out of any other write domains, and we can update
2863 * the domain values for our changes.
2865 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
2866 obj
->read_domains
|= I915_GEM_DOMAIN_GTT
;
2867 obj
->write_domain
= I915_GEM_DOMAIN_GTT
;
2868 obj_priv
->dirty
= 1;
2870 trace_i915_gem_object_change_domain(obj
,
2878 * Moves a single object to the CPU read, and possibly write domain.
2880 * This function returns when the move is complete, including waiting on
2884 i915_gem_object_set_to_cpu_domain(struct drm_gem_object
*obj
, int write
)
2886 uint32_t old_write_domain
, old_read_domains
;
2889 i915_gem_object_flush_gpu_write_domain(obj
);
2890 /* Wait on any GPU rendering and flushing to occur. */
2891 ret
= i915_gem_object_wait_rendering(obj
);
2895 i915_gem_object_flush_gtt_write_domain(obj
);
2897 /* If we have a partially-valid cache of the object in the CPU,
2898 * finish invalidating it and free the per-page flags.
2900 i915_gem_object_set_to_full_cpu_read_domain(obj
);
2902 old_write_domain
= obj
->write_domain
;
2903 old_read_domains
= obj
->read_domains
;
2905 /* Flush the CPU cache if it's still invalid. */
2906 if ((obj
->read_domains
& I915_GEM_DOMAIN_CPU
) == 0) {
2907 i915_gem_clflush_object(obj
);
2909 obj
->read_domains
|= I915_GEM_DOMAIN_CPU
;
2912 /* It should now be out of any other write domains, and we can update
2913 * the domain values for our changes.
2915 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
2917 /* If we're writing through the CPU, then the GPU read domains will
2918 * need to be invalidated at next use.
2921 obj
->read_domains
&= I915_GEM_DOMAIN_CPU
;
2922 obj
->write_domain
= I915_GEM_DOMAIN_CPU
;
2925 trace_i915_gem_object_change_domain(obj
,
2933 * Set the next domain for the specified object. This
2934 * may not actually perform the necessary flushing/invaliding though,
2935 * as that may want to be batched with other set_domain operations
2937 * This is (we hope) the only really tricky part of gem. The goal
2938 * is fairly simple -- track which caches hold bits of the object
2939 * and make sure they remain coherent. A few concrete examples may
2940 * help to explain how it works. For shorthand, we use the notation
2941 * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
2942 * a pair of read and write domain masks.
2944 * Case 1: the batch buffer
2950 * 5. Unmapped from GTT
2953 * Let's take these a step at a time
2956 * Pages allocated from the kernel may still have
2957 * cache contents, so we set them to (CPU, CPU) always.
2958 * 2. Written by CPU (using pwrite)
2959 * The pwrite function calls set_domain (CPU, CPU) and
2960 * this function does nothing (as nothing changes)
2962 * This function asserts that the object is not
2963 * currently in any GPU-based read or write domains
2965 * i915_gem_execbuffer calls set_domain (COMMAND, 0).
2966 * As write_domain is zero, this function adds in the
2967 * current read domains (CPU+COMMAND, 0).
2968 * flush_domains is set to CPU.
2969 * invalidate_domains is set to COMMAND
2970 * clflush is run to get data out of the CPU caches
2971 * then i915_dev_set_domain calls i915_gem_flush to
2972 * emit an MI_FLUSH and drm_agp_chipset_flush
2973 * 5. Unmapped from GTT
2974 * i915_gem_object_unbind calls set_domain (CPU, CPU)
2975 * flush_domains and invalidate_domains end up both zero
2976 * so no flushing/invalidating happens
2980 * Case 2: The shared render buffer
2984 * 3. Read/written by GPU
2985 * 4. set_domain to (CPU,CPU)
2986 * 5. Read/written by CPU
2987 * 6. Read/written by GPU
2990 * Same as last example, (CPU, CPU)
2992 * Nothing changes (assertions find that it is not in the GPU)
2993 * 3. Read/written by GPU
2994 * execbuffer calls set_domain (RENDER, RENDER)
2995 * flush_domains gets CPU
2996 * invalidate_domains gets GPU
2998 * MI_FLUSH and drm_agp_chipset_flush
2999 * 4. set_domain (CPU, CPU)
3000 * flush_domains gets GPU
3001 * invalidate_domains gets CPU
3002 * wait_rendering (obj) to make sure all drawing is complete.
3003 * This will include an MI_FLUSH to get the data from GPU
3005 * clflush (obj) to invalidate the CPU cache
3006 * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
3007 * 5. Read/written by CPU
3008 * cache lines are loaded and dirtied
3009 * 6. Read written by GPU
3010 * Same as last GPU access
3012 * Case 3: The constant buffer
3017 * 4. Updated (written) by CPU again
3026 * flush_domains = CPU
3027 * invalidate_domains = RENDER
3030 * drm_agp_chipset_flush
3031 * 4. Updated (written) by CPU again
3033 * flush_domains = 0 (no previous write domain)
3034 * invalidate_domains = 0 (no new read domains)
3037 * flush_domains = CPU
3038 * invalidate_domains = RENDER
3041 * drm_agp_chipset_flush
3044 i915_gem_object_set_to_gpu_domain(struct drm_gem_object
*obj
)
3046 struct drm_device
*dev
= obj
->dev
;
3047 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
3048 uint32_t invalidate_domains
= 0;
3049 uint32_t flush_domains
= 0;
3050 uint32_t old_read_domains
;
3052 BUG_ON(obj
->pending_read_domains
& I915_GEM_DOMAIN_CPU
);
3053 BUG_ON(obj
->pending_write_domain
== I915_GEM_DOMAIN_CPU
);
3055 intel_mark_busy(dev
, obj
);
3058 DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
3060 obj
->read_domains
, obj
->pending_read_domains
,
3061 obj
->write_domain
, obj
->pending_write_domain
);
3064 * If the object isn't moving to a new write domain,
3065 * let the object stay in multiple read domains
3067 if (obj
->pending_write_domain
== 0)
3068 obj
->pending_read_domains
|= obj
->read_domains
;
3070 obj_priv
->dirty
= 1;
3073 * Flush the current write domain if
3074 * the new read domains don't match. Invalidate
3075 * any read domains which differ from the old
3078 if (obj
->write_domain
&&
3079 obj
->write_domain
!= obj
->pending_read_domains
) {
3080 flush_domains
|= obj
->write_domain
;
3081 invalidate_domains
|=
3082 obj
->pending_read_domains
& ~obj
->write_domain
;
3085 * Invalidate any read caches which may have
3086 * stale data. That is, any new read domains.
3088 invalidate_domains
|= obj
->pending_read_domains
& ~obj
->read_domains
;
3089 if ((flush_domains
| invalidate_domains
) & I915_GEM_DOMAIN_CPU
) {
3091 DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
3092 __func__
, flush_domains
, invalidate_domains
);
3094 i915_gem_clflush_object(obj
);
3097 old_read_domains
= obj
->read_domains
;
3099 /* The actual obj->write_domain will be updated with
3100 * pending_write_domain after we emit the accumulated flush for all
3101 * of our domain changes in execbuffers (which clears objects'
3102 * write_domains). So if we have a current write domain that we
3103 * aren't changing, set pending_write_domain to that.
3105 if (flush_domains
== 0 && obj
->pending_write_domain
== 0)
3106 obj
->pending_write_domain
= obj
->write_domain
;
3107 obj
->read_domains
= obj
->pending_read_domains
;
3109 dev
->invalidate_domains
|= invalidate_domains
;
3110 dev
->flush_domains
|= flush_domains
;
3112 DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n",
3114 obj
->read_domains
, obj
->write_domain
,
3115 dev
->invalidate_domains
, dev
->flush_domains
);
3118 trace_i915_gem_object_change_domain(obj
,
3124 * Moves the object from a partially CPU read to a full one.
3126 * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3127 * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
3130 i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object
*obj
)
3132 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
3134 if (!obj_priv
->page_cpu_valid
)
3137 /* If we're partially in the CPU read domain, finish moving it in.
3139 if (obj
->read_domains
& I915_GEM_DOMAIN_CPU
) {
3142 for (i
= 0; i
<= (obj
->size
- 1) / PAGE_SIZE
; i
++) {
3143 if (obj_priv
->page_cpu_valid
[i
])
3145 drm_clflush_pages(obj_priv
->pages
+ i
, 1);
3149 /* Free the page_cpu_valid mappings which are now stale, whether
3150 * or not we've got I915_GEM_DOMAIN_CPU.
3152 kfree(obj_priv
->page_cpu_valid
);
3153 obj_priv
->page_cpu_valid
= NULL
;
3157 * Set the CPU read domain on a range of the object.
3159 * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3160 * not entirely valid. The page_cpu_valid member of the object flags which
3161 * pages have been flushed, and will be respected by
3162 * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3163 * of the whole object.
3165 * This function returns when the move is complete, including waiting on
3169 i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object
*obj
,
3170 uint64_t offset
, uint64_t size
)
3172 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
3173 uint32_t old_read_domains
;
3176 if (offset
== 0 && size
== obj
->size
)
3177 return i915_gem_object_set_to_cpu_domain(obj
, 0);
3179 i915_gem_object_flush_gpu_write_domain(obj
);
3180 /* Wait on any GPU rendering and flushing to occur. */
3181 ret
= i915_gem_object_wait_rendering(obj
);
3184 i915_gem_object_flush_gtt_write_domain(obj
);
3186 /* If we're already fully in the CPU read domain, we're done. */
3187 if (obj_priv
->page_cpu_valid
== NULL
&&
3188 (obj
->read_domains
& I915_GEM_DOMAIN_CPU
) != 0)
3191 /* Otherwise, create/clear the per-page CPU read domain flag if we're
3192 * newly adding I915_GEM_DOMAIN_CPU
3194 if (obj_priv
->page_cpu_valid
== NULL
) {
3195 obj_priv
->page_cpu_valid
= kzalloc(obj
->size
/ PAGE_SIZE
,
3197 if (obj_priv
->page_cpu_valid
== NULL
)
3199 } else if ((obj
->read_domains
& I915_GEM_DOMAIN_CPU
) == 0)
3200 memset(obj_priv
->page_cpu_valid
, 0, obj
->size
/ PAGE_SIZE
);
3202 /* Flush the cache on any pages that are still invalid from the CPU's
3205 for (i
= offset
/ PAGE_SIZE
; i
<= (offset
+ size
- 1) / PAGE_SIZE
;
3207 if (obj_priv
->page_cpu_valid
[i
])
3210 drm_clflush_pages(obj_priv
->pages
+ i
, 1);
3212 obj_priv
->page_cpu_valid
[i
] = 1;
3215 /* It should now be out of any other write domains, and we can update
3216 * the domain values for our changes.
3218 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
3220 old_read_domains
= obj
->read_domains
;
3221 obj
->read_domains
|= I915_GEM_DOMAIN_CPU
;
3223 trace_i915_gem_object_change_domain(obj
,
3231 * Pin an object to the GTT and evaluate the relocations landing in it.
3234 i915_gem_object_pin_and_relocate(struct drm_gem_object
*obj
,
3235 struct drm_file
*file_priv
,
3236 struct drm_i915_gem_exec_object2
*entry
,
3237 struct drm_i915_gem_relocation_entry
*relocs
)
3239 struct drm_device
*dev
= obj
->dev
;
3240 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3241 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
3243 void __iomem
*reloc_page
;
3246 need_fence
= entry
->flags
& EXEC_OBJECT_NEEDS_FENCE
&&
3247 obj_priv
->tiling_mode
!= I915_TILING_NONE
;
3249 /* Check fence reg constraints and rebind if necessary */
3250 if (need_fence
&& !i915_obj_fenceable(dev
, obj
))
3251 i915_gem_object_unbind(obj
);
3253 /* Choose the GTT offset for our buffer and put it there. */
3254 ret
= i915_gem_object_pin(obj
, (uint32_t) entry
->alignment
);
3259 * Pre-965 chips need a fence register set up in order to
3260 * properly handle blits to/from tiled surfaces.
3263 ret
= i915_gem_object_get_fence_reg(obj
);
3265 if (ret
!= -EBUSY
&& ret
!= -ERESTARTSYS
)
3266 DRM_ERROR("Failure to install fence: %d\n",
3268 i915_gem_object_unpin(obj
);
3273 entry
->offset
= obj_priv
->gtt_offset
;
3275 /* Apply the relocations, using the GTT aperture to avoid cache
3276 * flushing requirements.
3278 for (i
= 0; i
< entry
->relocation_count
; i
++) {
3279 struct drm_i915_gem_relocation_entry
*reloc
= &relocs
[i
];
3280 struct drm_gem_object
*target_obj
;
3281 struct drm_i915_gem_object
*target_obj_priv
;
3282 uint32_t reloc_val
, reloc_offset
;
3283 uint32_t __iomem
*reloc_entry
;
3285 target_obj
= drm_gem_object_lookup(obj
->dev
, file_priv
,
3286 reloc
->target_handle
);
3287 if (target_obj
== NULL
) {
3288 i915_gem_object_unpin(obj
);
3291 target_obj_priv
= target_obj
->driver_private
;
3294 DRM_INFO("%s: obj %p offset %08x target %d "
3295 "read %08x write %08x gtt %08x "
3296 "presumed %08x delta %08x\n",
3299 (int) reloc
->offset
,
3300 (int) reloc
->target_handle
,
3301 (int) reloc
->read_domains
,
3302 (int) reloc
->write_domain
,
3303 (int) target_obj_priv
->gtt_offset
,
3304 (int) reloc
->presumed_offset
,
3308 /* The target buffer should have appeared before us in the
3309 * exec_object list, so it should have a GTT space bound by now.
3311 if (target_obj_priv
->gtt_space
== NULL
) {
3312 DRM_ERROR("No GTT space found for object %d\n",
3313 reloc
->target_handle
);
3314 drm_gem_object_unreference(target_obj
);
3315 i915_gem_object_unpin(obj
);
3319 /* Validate that the target is in a valid r/w GPU domain */
3320 if (reloc
->write_domain
& I915_GEM_DOMAIN_CPU
||
3321 reloc
->read_domains
& I915_GEM_DOMAIN_CPU
) {
3322 DRM_ERROR("reloc with read/write CPU domains: "
3323 "obj %p target %d offset %d "
3324 "read %08x write %08x",
3325 obj
, reloc
->target_handle
,
3326 (int) reloc
->offset
,
3327 reloc
->read_domains
,
3328 reloc
->write_domain
);
3329 drm_gem_object_unreference(target_obj
);
3330 i915_gem_object_unpin(obj
);
3333 if (reloc
->write_domain
&& target_obj
->pending_write_domain
&&
3334 reloc
->write_domain
!= target_obj
->pending_write_domain
) {
3335 DRM_ERROR("Write domain conflict: "
3336 "obj %p target %d offset %d "
3337 "new %08x old %08x\n",
3338 obj
, reloc
->target_handle
,
3339 (int) reloc
->offset
,
3340 reloc
->write_domain
,
3341 target_obj
->pending_write_domain
);
3342 drm_gem_object_unreference(target_obj
);
3343 i915_gem_object_unpin(obj
);
3347 target_obj
->pending_read_domains
|= reloc
->read_domains
;
3348 target_obj
->pending_write_domain
|= reloc
->write_domain
;
3350 /* If the relocation already has the right value in it, no
3351 * more work needs to be done.
3353 if (target_obj_priv
->gtt_offset
== reloc
->presumed_offset
) {
3354 drm_gem_object_unreference(target_obj
);
3358 /* Check that the relocation address is valid... */
3359 if (reloc
->offset
> obj
->size
- 4) {
3360 DRM_ERROR("Relocation beyond object bounds: "
3361 "obj %p target %d offset %d size %d.\n",
3362 obj
, reloc
->target_handle
,
3363 (int) reloc
->offset
, (int) obj
->size
);
3364 drm_gem_object_unreference(target_obj
);
3365 i915_gem_object_unpin(obj
);
3368 if (reloc
->offset
& 3) {
3369 DRM_ERROR("Relocation not 4-byte aligned: "
3370 "obj %p target %d offset %d.\n",
3371 obj
, reloc
->target_handle
,
3372 (int) reloc
->offset
);
3373 drm_gem_object_unreference(target_obj
);
3374 i915_gem_object_unpin(obj
);
3378 /* and points to somewhere within the target object. */
3379 if (reloc
->delta
>= target_obj
->size
) {
3380 DRM_ERROR("Relocation beyond target object bounds: "
3381 "obj %p target %d delta %d size %d.\n",
3382 obj
, reloc
->target_handle
,
3383 (int) reloc
->delta
, (int) target_obj
->size
);
3384 drm_gem_object_unreference(target_obj
);
3385 i915_gem_object_unpin(obj
);
3389 ret
= i915_gem_object_set_to_gtt_domain(obj
, 1);
3391 drm_gem_object_unreference(target_obj
);
3392 i915_gem_object_unpin(obj
);
3396 /* Map the page containing the relocation we're going to
3399 reloc_offset
= obj_priv
->gtt_offset
+ reloc
->offset
;
3400 reloc_page
= io_mapping_map_atomic_wc(dev_priv
->mm
.gtt_mapping
,
3403 reloc_entry
= (uint32_t __iomem
*)(reloc_page
+
3404 (reloc_offset
& (PAGE_SIZE
- 1)));
3405 reloc_val
= target_obj_priv
->gtt_offset
+ reloc
->delta
;
3408 DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n",
3409 obj
, (unsigned int) reloc
->offset
,
3410 readl(reloc_entry
), reloc_val
);
3412 writel(reloc_val
, reloc_entry
);
3413 io_mapping_unmap_atomic(reloc_page
);
3415 /* The updated presumed offset for this entry will be
3416 * copied back out to the user.
3418 reloc
->presumed_offset
= target_obj_priv
->gtt_offset
;
3420 drm_gem_object_unreference(target_obj
);
3425 i915_gem_dump_object(obj
, 128, __func__
, ~0);
3430 /** Dispatch a batchbuffer to the ring
3433 i915_dispatch_gem_execbuffer(struct drm_device
*dev
,
3434 struct drm_i915_gem_execbuffer2
*exec
,
3435 struct drm_clip_rect
*cliprects
,
3436 uint64_t exec_offset
)
3438 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3439 int nbox
= exec
->num_cliprects
;
3441 uint32_t exec_start
, exec_len
;
3444 exec_start
= (uint32_t) exec_offset
+ exec
->batch_start_offset
;
3445 exec_len
= (uint32_t) exec
->batch_len
;
3447 trace_i915_gem_request_submit(dev
, dev_priv
->mm
.next_gem_seqno
+ 1);
3449 count
= nbox
? nbox
: 1;
3451 for (i
= 0; i
< count
; i
++) {
3453 int ret
= i915_emit_box(dev
, cliprects
, i
,
3454 exec
->DR1
, exec
->DR4
);
3459 if (IS_I830(dev
) || IS_845G(dev
)) {
3461 OUT_RING(MI_BATCH_BUFFER
);
3462 OUT_RING(exec_start
| MI_BATCH_NON_SECURE
);
3463 OUT_RING(exec_start
+ exec_len
- 4);
3468 if (IS_I965G(dev
)) {
3469 OUT_RING(MI_BATCH_BUFFER_START
|
3471 MI_BATCH_NON_SECURE_I965
);
3472 OUT_RING(exec_start
);
3474 OUT_RING(MI_BATCH_BUFFER_START
|
3476 OUT_RING(exec_start
| MI_BATCH_NON_SECURE
);
3482 /* XXX breadcrumb */
3486 /* Throttle our rendering by waiting until the ring has completed our requests
3487 * emitted over 20 msec ago.
3489 * Note that if we were to use the current jiffies each time around the loop,
3490 * we wouldn't escape the function with any frames outstanding if the time to
3491 * render a frame was over 20ms.
3493 * This should get us reasonable parallelism between CPU and GPU but also
3494 * relatively low latency when blocking on a particular request to finish.
3497 i915_gem_ring_throttle(struct drm_device
*dev
, struct drm_file
*file_priv
)
3499 struct drm_i915_file_private
*i915_file_priv
= file_priv
->driver_priv
;
3501 unsigned long recent_enough
= jiffies
- msecs_to_jiffies(20);
3503 mutex_lock(&dev
->struct_mutex
);
3504 while (!list_empty(&i915_file_priv
->mm
.request_list
)) {
3505 struct drm_i915_gem_request
*request
;
3507 request
= list_first_entry(&i915_file_priv
->mm
.request_list
,
3508 struct drm_i915_gem_request
,
3511 if (time_after_eq(request
->emitted_jiffies
, recent_enough
))
3514 ret
= i915_wait_request(dev
, request
->seqno
);
3518 mutex_unlock(&dev
->struct_mutex
);
3524 i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object2
*exec_list
,
3525 uint32_t buffer_count
,
3526 struct drm_i915_gem_relocation_entry
**relocs
)
3528 uint32_t reloc_count
= 0, reloc_index
= 0, i
;
3532 for (i
= 0; i
< buffer_count
; i
++) {
3533 if (reloc_count
+ exec_list
[i
].relocation_count
< reloc_count
)
3535 reloc_count
+= exec_list
[i
].relocation_count
;
3538 *relocs
= drm_calloc_large(reloc_count
, sizeof(**relocs
));
3539 if (*relocs
== NULL
) {
3540 DRM_ERROR("failed to alloc relocs, count %d\n", reloc_count
);
3544 for (i
= 0; i
< buffer_count
; i
++) {
3545 struct drm_i915_gem_relocation_entry __user
*user_relocs
;
3547 user_relocs
= (void __user
*)(uintptr_t)exec_list
[i
].relocs_ptr
;
3549 ret
= copy_from_user(&(*relocs
)[reloc_index
],
3551 exec_list
[i
].relocation_count
*
3554 drm_free_large(*relocs
);
3559 reloc_index
+= exec_list
[i
].relocation_count
;
3566 i915_gem_put_relocs_to_user(struct drm_i915_gem_exec_object2
*exec_list
,
3567 uint32_t buffer_count
,
3568 struct drm_i915_gem_relocation_entry
*relocs
)
3570 uint32_t reloc_count
= 0, i
;
3576 for (i
= 0; i
< buffer_count
; i
++) {
3577 struct drm_i915_gem_relocation_entry __user
*user_relocs
;
3580 user_relocs
= (void __user
*)(uintptr_t)exec_list
[i
].relocs_ptr
;
3582 unwritten
= copy_to_user(user_relocs
,
3583 &relocs
[reloc_count
],
3584 exec_list
[i
].relocation_count
*
3592 reloc_count
+= exec_list
[i
].relocation_count
;
3596 drm_free_large(relocs
);
3602 i915_gem_check_execbuffer (struct drm_i915_gem_execbuffer2
*exec
,
3603 uint64_t exec_offset
)
3605 uint32_t exec_start
, exec_len
;
3607 exec_start
= (uint32_t) exec_offset
+ exec
->batch_start_offset
;
3608 exec_len
= (uint32_t) exec
->batch_len
;
3610 if ((exec_start
| exec_len
) & 0x7)
3620 i915_gem_wait_for_pending_flip(struct drm_device
*dev
,
3621 struct drm_gem_object
**object_list
,
3624 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3625 struct drm_i915_gem_object
*obj_priv
;
3630 prepare_to_wait(&dev_priv
->pending_flip_queue
,
3631 &wait
, TASK_INTERRUPTIBLE
);
3632 for (i
= 0; i
< count
; i
++) {
3633 obj_priv
= object_list
[i
]->driver_private
;
3634 if (atomic_read(&obj_priv
->pending_flip
) > 0)
3640 if (!signal_pending(current
)) {
3641 mutex_unlock(&dev
->struct_mutex
);
3643 mutex_lock(&dev
->struct_mutex
);
3649 finish_wait(&dev_priv
->pending_flip_queue
, &wait
);
3655 i915_gem_do_execbuffer(struct drm_device
*dev
, void *data
,
3656 struct drm_file
*file_priv
,
3657 struct drm_i915_gem_execbuffer2
*args
,
3658 struct drm_i915_gem_exec_object2
*exec_list
)
3660 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3661 struct drm_gem_object
**object_list
= NULL
;
3662 struct drm_gem_object
*batch_obj
;
3663 struct drm_i915_gem_object
*obj_priv
;
3664 struct drm_clip_rect
*cliprects
= NULL
;
3665 struct drm_i915_gem_relocation_entry
*relocs
= NULL
;
3666 int ret
= 0, ret2
, i
, pinned
= 0;
3667 uint64_t exec_offset
;
3668 uint32_t seqno
, flush_domains
, reloc_index
;
3669 int pin_tries
, flips
;
3672 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3673 (int) args
->buffers_ptr
, args
->buffer_count
, args
->batch_len
);
3676 if (args
->buffer_count
< 1) {
3677 DRM_ERROR("execbuf with %d buffers\n", args
->buffer_count
);
3680 object_list
= drm_malloc_ab(sizeof(*object_list
), args
->buffer_count
);
3681 if (object_list
== NULL
) {
3682 DRM_ERROR("Failed to allocate object list for %d buffers\n",
3683 args
->buffer_count
);
3688 if (args
->num_cliprects
!= 0) {
3689 cliprects
= kcalloc(args
->num_cliprects
, sizeof(*cliprects
),
3691 if (cliprects
== NULL
) {
3696 ret
= copy_from_user(cliprects
,
3697 (struct drm_clip_rect __user
*)
3698 (uintptr_t) args
->cliprects_ptr
,
3699 sizeof(*cliprects
) * args
->num_cliprects
);
3701 DRM_ERROR("copy %d cliprects failed: %d\n",
3702 args
->num_cliprects
, ret
);
3707 ret
= i915_gem_get_relocs_from_user(exec_list
, args
->buffer_count
,
3712 mutex_lock(&dev
->struct_mutex
);
3714 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3716 if (atomic_read(&dev_priv
->mm
.wedged
)) {
3717 mutex_unlock(&dev
->struct_mutex
);
3722 if (dev_priv
->mm
.suspended
) {
3723 mutex_unlock(&dev
->struct_mutex
);
3728 /* Look up object handles */
3730 for (i
= 0; i
< args
->buffer_count
; i
++) {
3731 object_list
[i
] = drm_gem_object_lookup(dev
, file_priv
,
3732 exec_list
[i
].handle
);
3733 if (object_list
[i
] == NULL
) {
3734 DRM_ERROR("Invalid object handle %d at index %d\n",
3735 exec_list
[i
].handle
, i
);
3736 /* prevent error path from reading uninitialized data */
3737 args
->buffer_count
= i
+ 1;
3742 obj_priv
= object_list
[i
]->driver_private
;
3743 if (obj_priv
->in_execbuffer
) {
3744 DRM_ERROR("Object %p appears more than once in object list\n",
3746 /* prevent error path from reading uninitialized data */
3747 args
->buffer_count
= i
+ 1;
3751 obj_priv
->in_execbuffer
= true;
3752 flips
+= atomic_read(&obj_priv
->pending_flip
);
3756 ret
= i915_gem_wait_for_pending_flip(dev
, object_list
,
3757 args
->buffer_count
);
3762 /* Pin and relocate */
3763 for (pin_tries
= 0; ; pin_tries
++) {
3767 for (i
= 0; i
< args
->buffer_count
; i
++) {
3768 object_list
[i
]->pending_read_domains
= 0;
3769 object_list
[i
]->pending_write_domain
= 0;
3770 ret
= i915_gem_object_pin_and_relocate(object_list
[i
],
3773 &relocs
[reloc_index
]);
3777 reloc_index
+= exec_list
[i
].relocation_count
;
3783 /* error other than GTT full, or we've already tried again */
3784 if (ret
!= -ENOSPC
|| pin_tries
>= 1) {
3785 if (ret
!= -ERESTARTSYS
) {
3786 unsigned long long total_size
= 0;
3787 for (i
= 0; i
< args
->buffer_count
; i
++)
3788 total_size
+= object_list
[i
]->size
;
3789 DRM_ERROR("Failed to pin buffer %d of %d, total %llu bytes: %d\n",
3790 pinned
+1, args
->buffer_count
,
3792 DRM_ERROR("%d objects [%d pinned], "
3793 "%d object bytes [%d pinned], "
3794 "%d/%d gtt bytes\n",
3795 atomic_read(&dev
->object_count
),
3796 atomic_read(&dev
->pin_count
),
3797 atomic_read(&dev
->object_memory
),
3798 atomic_read(&dev
->pin_memory
),
3799 atomic_read(&dev
->gtt_memory
),
3805 /* unpin all of our buffers */
3806 for (i
= 0; i
< pinned
; i
++)
3807 i915_gem_object_unpin(object_list
[i
]);
3810 /* evict everyone we can from the aperture */
3811 ret
= i915_gem_evict_everything(dev
);
3812 if (ret
&& ret
!= -ENOSPC
)
3816 /* Set the pending read domains for the batch buffer to COMMAND */
3817 batch_obj
= object_list
[args
->buffer_count
-1];
3818 if (batch_obj
->pending_write_domain
) {
3819 DRM_ERROR("Attempting to use self-modifying batch buffer\n");
3823 batch_obj
->pending_read_domains
|= I915_GEM_DOMAIN_COMMAND
;
3825 /* Sanity check the batch buffer, prior to moving objects */
3826 exec_offset
= exec_list
[args
->buffer_count
- 1].offset
;
3827 ret
= i915_gem_check_execbuffer (args
, exec_offset
);
3829 DRM_ERROR("execbuf with invalid offset/length\n");
3833 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3835 /* Zero the global flush/invalidate flags. These
3836 * will be modified as new domains are computed
3839 dev
->invalidate_domains
= 0;
3840 dev
->flush_domains
= 0;
3842 for (i
= 0; i
< args
->buffer_count
; i
++) {
3843 struct drm_gem_object
*obj
= object_list
[i
];
3845 /* Compute new gpu domains and update invalidate/flush */
3846 i915_gem_object_set_to_gpu_domain(obj
);
3849 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3851 if (dev
->invalidate_domains
| dev
->flush_domains
) {
3853 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
3855 dev
->invalidate_domains
,
3856 dev
->flush_domains
);
3859 dev
->invalidate_domains
,
3860 dev
->flush_domains
);
3861 if (dev
->flush_domains
& I915_GEM_GPU_DOMAINS
)
3862 (void)i915_add_request(dev
, file_priv
,
3863 dev
->flush_domains
);
3866 for (i
= 0; i
< args
->buffer_count
; i
++) {
3867 struct drm_gem_object
*obj
= object_list
[i
];
3868 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
3869 uint32_t old_write_domain
= obj
->write_domain
;
3871 obj
->write_domain
= obj
->pending_write_domain
;
3872 if (obj
->write_domain
)
3873 list_move_tail(&obj_priv
->gpu_write_list
,
3874 &dev_priv
->mm
.gpu_write_list
);
3876 list_del_init(&obj_priv
->gpu_write_list
);
3878 trace_i915_gem_object_change_domain(obj
,
3883 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3886 for (i
= 0; i
< args
->buffer_count
; i
++) {
3887 i915_gem_object_check_coherency(object_list
[i
],
3888 exec_list
[i
].handle
);
3893 i915_gem_dump_object(batch_obj
,
3899 /* Exec the batchbuffer */
3900 ret
= i915_dispatch_gem_execbuffer(dev
, args
, cliprects
, exec_offset
);
3902 DRM_ERROR("dispatch failed %d\n", ret
);
3907 * Ensure that the commands in the batch buffer are
3908 * finished before the interrupt fires
3910 flush_domains
= i915_retire_commands(dev
);
3912 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3915 * Get a seqno representing the execution of the current buffer,
3916 * which we can wait on. We would like to mitigate these interrupts,
3917 * likely by only creating seqnos occasionally (so that we have
3918 * *some* interrupts representing completion of buffers that we can
3919 * wait on when trying to clear up gtt space).
3921 seqno
= i915_add_request(dev
, file_priv
, flush_domains
);
3923 for (i
= 0; i
< args
->buffer_count
; i
++) {
3924 struct drm_gem_object
*obj
= object_list
[i
];
3926 i915_gem_object_move_to_active(obj
, seqno
);
3928 DRM_INFO("%s: move to exec list %p\n", __func__
, obj
);
3932 i915_dump_lru(dev
, __func__
);
3935 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3938 for (i
= 0; i
< pinned
; i
++)
3939 i915_gem_object_unpin(object_list
[i
]);
3941 for (i
= 0; i
< args
->buffer_count
; i
++) {
3942 if (object_list
[i
]) {
3943 obj_priv
= object_list
[i
]->driver_private
;
3944 obj_priv
->in_execbuffer
= false;
3946 drm_gem_object_unreference(object_list
[i
]);
3949 mutex_unlock(&dev
->struct_mutex
);
3952 /* Copy the updated relocations out regardless of current error
3953 * state. Failure to update the relocs would mean that the next
3954 * time userland calls execbuf, it would do so with presumed offset
3955 * state that didn't match the actual object state.
3957 ret2
= i915_gem_put_relocs_to_user(exec_list
, args
->buffer_count
,
3960 DRM_ERROR("Failed to copy relocations back out: %d\n", ret2
);
3966 drm_free_large(object_list
);
3973 * Legacy execbuffer just creates an exec2 list from the original exec object
3974 * list array and passes it to the real function.
3977 i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
3978 struct drm_file
*file_priv
)
3980 struct drm_i915_gem_execbuffer
*args
= data
;
3981 struct drm_i915_gem_execbuffer2 exec2
;
3982 struct drm_i915_gem_exec_object
*exec_list
= NULL
;
3983 struct drm_i915_gem_exec_object2
*exec2_list
= NULL
;
3987 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3988 (int) args
->buffers_ptr
, args
->buffer_count
, args
->batch_len
);
3991 if (args
->buffer_count
< 1) {
3992 DRM_ERROR("execbuf with %d buffers\n", args
->buffer_count
);
3996 /* Copy in the exec list from userland */
3997 exec_list
= drm_malloc_ab(sizeof(*exec_list
), args
->buffer_count
);
3998 exec2_list
= drm_malloc_ab(sizeof(*exec2_list
), args
->buffer_count
);
3999 if (exec_list
== NULL
|| exec2_list
== NULL
) {
4000 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
4001 args
->buffer_count
);
4002 drm_free_large(exec_list
);
4003 drm_free_large(exec2_list
);
4006 ret
= copy_from_user(exec_list
,
4007 (struct drm_i915_relocation_entry __user
*)
4008 (uintptr_t) args
->buffers_ptr
,
4009 sizeof(*exec_list
) * args
->buffer_count
);
4011 DRM_ERROR("copy %d exec entries failed %d\n",
4012 args
->buffer_count
, ret
);
4013 drm_free_large(exec_list
);
4014 drm_free_large(exec2_list
);
4018 for (i
= 0; i
< args
->buffer_count
; i
++) {
4019 exec2_list
[i
].handle
= exec_list
[i
].handle
;
4020 exec2_list
[i
].relocation_count
= exec_list
[i
].relocation_count
;
4021 exec2_list
[i
].relocs_ptr
= exec_list
[i
].relocs_ptr
;
4022 exec2_list
[i
].alignment
= exec_list
[i
].alignment
;
4023 exec2_list
[i
].offset
= exec_list
[i
].offset
;
4025 exec2_list
[i
].flags
= EXEC_OBJECT_NEEDS_FENCE
;
4027 exec2_list
[i
].flags
= 0;
4030 exec2
.buffers_ptr
= args
->buffers_ptr
;
4031 exec2
.buffer_count
= args
->buffer_count
;
4032 exec2
.batch_start_offset
= args
->batch_start_offset
;
4033 exec2
.batch_len
= args
->batch_len
;
4034 exec2
.DR1
= args
->DR1
;
4035 exec2
.DR4
= args
->DR4
;
4036 exec2
.num_cliprects
= args
->num_cliprects
;
4037 exec2
.cliprects_ptr
= args
->cliprects_ptr
;
4040 ret
= i915_gem_do_execbuffer(dev
, data
, file_priv
, &exec2
, exec2_list
);
4042 /* Copy the new buffer offsets back to the user's exec list. */
4043 for (i
= 0; i
< args
->buffer_count
; i
++)
4044 exec_list
[i
].offset
= exec2_list
[i
].offset
;
4045 /* ... and back out to userspace */
4046 ret
= copy_to_user((struct drm_i915_relocation_entry __user
*)
4047 (uintptr_t) args
->buffers_ptr
,
4049 sizeof(*exec_list
) * args
->buffer_count
);
4052 DRM_ERROR("failed to copy %d exec entries "
4053 "back to user (%d)\n",
4054 args
->buffer_count
, ret
);
4058 drm_free_large(exec_list
);
4059 drm_free_large(exec2_list
);
4064 i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
4065 struct drm_file
*file_priv
)
4067 struct drm_i915_gem_execbuffer2
*args
= data
;
4068 struct drm_i915_gem_exec_object2
*exec2_list
= NULL
;
4072 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
4073 (int) args
->buffers_ptr
, args
->buffer_count
, args
->batch_len
);
4076 if (args
->buffer_count
< 1) {
4077 DRM_ERROR("execbuf2 with %d buffers\n", args
->buffer_count
);
4081 exec2_list
= drm_malloc_ab(sizeof(*exec2_list
), args
->buffer_count
);
4082 if (exec2_list
== NULL
) {
4083 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
4084 args
->buffer_count
);
4087 ret
= copy_from_user(exec2_list
,
4088 (struct drm_i915_relocation_entry __user
*)
4089 (uintptr_t) args
->buffers_ptr
,
4090 sizeof(*exec2_list
) * args
->buffer_count
);
4092 DRM_ERROR("copy %d exec entries failed %d\n",
4093 args
->buffer_count
, ret
);
4094 drm_free_large(exec2_list
);
4098 ret
= i915_gem_do_execbuffer(dev
, data
, file_priv
, args
, exec2_list
);
4100 /* Copy the new buffer offsets back to the user's exec list. */
4101 ret
= copy_to_user((struct drm_i915_relocation_entry __user
*)
4102 (uintptr_t) args
->buffers_ptr
,
4104 sizeof(*exec2_list
) * args
->buffer_count
);
4107 DRM_ERROR("failed to copy %d exec entries "
4108 "back to user (%d)\n",
4109 args
->buffer_count
, ret
);
4113 drm_free_large(exec2_list
);
4118 i915_gem_object_pin(struct drm_gem_object
*obj
, uint32_t alignment
)
4120 struct drm_device
*dev
= obj
->dev
;
4121 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
4124 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
4125 if (obj_priv
->gtt_space
== NULL
) {
4126 ret
= i915_gem_object_bind_to_gtt(obj
, alignment
);
4131 obj_priv
->pin_count
++;
4133 /* If the object is not active and not pending a flush,
4134 * remove it from the inactive list
4136 if (obj_priv
->pin_count
== 1) {
4137 atomic_inc(&dev
->pin_count
);
4138 atomic_add(obj
->size
, &dev
->pin_memory
);
4139 if (!obj_priv
->active
&&
4140 (obj
->write_domain
& I915_GEM_GPU_DOMAINS
) == 0 &&
4141 !list_empty(&obj_priv
->list
))
4142 list_del_init(&obj_priv
->list
);
4144 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
4150 i915_gem_object_unpin(struct drm_gem_object
*obj
)
4152 struct drm_device
*dev
= obj
->dev
;
4153 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4154 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
4156 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
4157 obj_priv
->pin_count
--;
4158 BUG_ON(obj_priv
->pin_count
< 0);
4159 BUG_ON(obj_priv
->gtt_space
== NULL
);
4161 /* If the object is no longer pinned, and is
4162 * neither active nor being flushed, then stick it on
4165 if (obj_priv
->pin_count
== 0) {
4166 if (!obj_priv
->active
&&
4167 (obj
->write_domain
& I915_GEM_GPU_DOMAINS
) == 0)
4168 list_move_tail(&obj_priv
->list
,
4169 &dev_priv
->mm
.inactive_list
);
4170 atomic_dec(&dev
->pin_count
);
4171 atomic_sub(obj
->size
, &dev
->pin_memory
);
4173 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
4177 i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
4178 struct drm_file
*file_priv
)
4180 struct drm_i915_gem_pin
*args
= data
;
4181 struct drm_gem_object
*obj
;
4182 struct drm_i915_gem_object
*obj_priv
;
4185 mutex_lock(&dev
->struct_mutex
);
4187 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4189 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
4191 mutex_unlock(&dev
->struct_mutex
);
4194 obj_priv
= obj
->driver_private
;
4196 if (obj_priv
->madv
!= I915_MADV_WILLNEED
) {
4197 DRM_ERROR("Attempting to pin a purgeable buffer\n");
4198 drm_gem_object_unreference(obj
);
4199 mutex_unlock(&dev
->struct_mutex
);
4203 if (obj_priv
->pin_filp
!= NULL
&& obj_priv
->pin_filp
!= file_priv
) {
4204 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
4206 drm_gem_object_unreference(obj
);
4207 mutex_unlock(&dev
->struct_mutex
);
4211 obj_priv
->user_pin_count
++;
4212 obj_priv
->pin_filp
= file_priv
;
4213 if (obj_priv
->user_pin_count
== 1) {
4214 ret
= i915_gem_object_pin(obj
, args
->alignment
);
4216 drm_gem_object_unreference(obj
);
4217 mutex_unlock(&dev
->struct_mutex
);
4222 /* XXX - flush the CPU caches for pinned objects
4223 * as the X server doesn't manage domains yet
4225 i915_gem_object_flush_cpu_write_domain(obj
);
4226 args
->offset
= obj_priv
->gtt_offset
;
4227 drm_gem_object_unreference(obj
);
4228 mutex_unlock(&dev
->struct_mutex
);
4234 i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
4235 struct drm_file
*file_priv
)
4237 struct drm_i915_gem_pin
*args
= data
;
4238 struct drm_gem_object
*obj
;
4239 struct drm_i915_gem_object
*obj_priv
;
4241 mutex_lock(&dev
->struct_mutex
);
4243 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4245 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
4247 mutex_unlock(&dev
->struct_mutex
);
4251 obj_priv
= obj
->driver_private
;
4252 if (obj_priv
->pin_filp
!= file_priv
) {
4253 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4255 drm_gem_object_unreference(obj
);
4256 mutex_unlock(&dev
->struct_mutex
);
4259 obj_priv
->user_pin_count
--;
4260 if (obj_priv
->user_pin_count
== 0) {
4261 obj_priv
->pin_filp
= NULL
;
4262 i915_gem_object_unpin(obj
);
4265 drm_gem_object_unreference(obj
);
4266 mutex_unlock(&dev
->struct_mutex
);
4271 i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
4272 struct drm_file
*file_priv
)
4274 struct drm_i915_gem_busy
*args
= data
;
4275 struct drm_gem_object
*obj
;
4276 struct drm_i915_gem_object
*obj_priv
;
4278 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4280 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
4285 mutex_lock(&dev
->struct_mutex
);
4286 /* Update the active list for the hardware's current position.
4287 * Otherwise this only updates on a delayed timer or when irqs are
4288 * actually unmasked, and our working set ends up being larger than
4291 i915_gem_retire_requests(dev
);
4293 obj_priv
= obj
->driver_private
;
4294 /* Don't count being on the flushing list against the object being
4295 * done. Otherwise, a buffer left on the flushing list but not getting
4296 * flushed (because nobody's flushing that domain) won't ever return
4297 * unbusy and get reused by libdrm's bo cache. The other expected
4298 * consumer of this interface, OpenGL's occlusion queries, also specs
4299 * that the objects get unbusy "eventually" without any interference.
4301 args
->busy
= obj_priv
->active
&& obj_priv
->last_rendering_seqno
!= 0;
4303 drm_gem_object_unreference(obj
);
4304 mutex_unlock(&dev
->struct_mutex
);
4309 i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
4310 struct drm_file
*file_priv
)
4312 return i915_gem_ring_throttle(dev
, file_priv
);
4316 i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
4317 struct drm_file
*file_priv
)
4319 struct drm_i915_gem_madvise
*args
= data
;
4320 struct drm_gem_object
*obj
;
4321 struct drm_i915_gem_object
*obj_priv
;
4323 switch (args
->madv
) {
4324 case I915_MADV_DONTNEED
:
4325 case I915_MADV_WILLNEED
:
4331 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4333 DRM_ERROR("Bad handle in i915_gem_madvise_ioctl(): %d\n",
4338 mutex_lock(&dev
->struct_mutex
);
4339 obj_priv
= obj
->driver_private
;
4341 if (obj_priv
->pin_count
) {
4342 drm_gem_object_unreference(obj
);
4343 mutex_unlock(&dev
->struct_mutex
);
4345 DRM_ERROR("Attempted i915_gem_madvise_ioctl() on a pinned object\n");
4349 if (obj_priv
->madv
!= __I915_MADV_PURGED
)
4350 obj_priv
->madv
= args
->madv
;
4352 /* if the object is no longer bound, discard its backing storage */
4353 if (i915_gem_object_is_purgeable(obj_priv
) &&
4354 obj_priv
->gtt_space
== NULL
)
4355 i915_gem_object_truncate(obj
);
4357 args
->retained
= obj_priv
->madv
!= __I915_MADV_PURGED
;
4359 drm_gem_object_unreference(obj
);
4360 mutex_unlock(&dev
->struct_mutex
);
4365 int i915_gem_init_object(struct drm_gem_object
*obj
)
4367 struct drm_i915_gem_object
*obj_priv
;
4369 obj_priv
= kzalloc(sizeof(*obj_priv
), GFP_KERNEL
);
4370 if (obj_priv
== NULL
)
4374 * We've just allocated pages from the kernel,
4375 * so they've just been written by the CPU with
4376 * zeros. They'll need to be clflushed before we
4377 * use them with the GPU.
4379 obj
->write_domain
= I915_GEM_DOMAIN_CPU
;
4380 obj
->read_domains
= I915_GEM_DOMAIN_CPU
;
4382 obj_priv
->agp_type
= AGP_USER_MEMORY
;
4384 obj
->driver_private
= obj_priv
;
4385 obj_priv
->obj
= obj
;
4386 obj_priv
->fence_reg
= I915_FENCE_REG_NONE
;
4387 INIT_LIST_HEAD(&obj_priv
->list
);
4388 INIT_LIST_HEAD(&obj_priv
->gpu_write_list
);
4389 INIT_LIST_HEAD(&obj_priv
->fence_list
);
4390 obj_priv
->madv
= I915_MADV_WILLNEED
;
4392 trace_i915_gem_object_create(obj
);
4397 void i915_gem_free_object(struct drm_gem_object
*obj
)
4399 struct drm_device
*dev
= obj
->dev
;
4400 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
4402 trace_i915_gem_object_destroy(obj
);
4404 while (obj_priv
->pin_count
> 0)
4405 i915_gem_object_unpin(obj
);
4407 if (obj_priv
->phys_obj
)
4408 i915_gem_detach_phys_object(dev
, obj
);
4410 i915_gem_object_unbind(obj
);
4412 if (obj_priv
->mmap_offset
)
4413 i915_gem_free_mmap_offset(obj
);
4415 kfree(obj_priv
->page_cpu_valid
);
4416 kfree(obj_priv
->bit_17
);
4417 kfree(obj
->driver_private
);
4420 /** Unbinds all inactive objects. */
4422 i915_gem_evict_from_inactive_list(struct drm_device
*dev
)
4424 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4426 while (!list_empty(&dev_priv
->mm
.inactive_list
)) {
4427 struct drm_gem_object
*obj
;
4430 obj
= list_first_entry(&dev_priv
->mm
.inactive_list
,
4431 struct drm_i915_gem_object
,
4434 ret
= i915_gem_object_unbind(obj
);
4436 DRM_ERROR("Error unbinding object: %d\n", ret
);
4445 i915_gem_idle(struct drm_device
*dev
)
4447 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4448 uint32_t seqno
, cur_seqno
, last_seqno
;
4451 mutex_lock(&dev
->struct_mutex
);
4453 if (dev_priv
->mm
.suspended
|| dev_priv
->ring
.ring_obj
== NULL
) {
4454 mutex_unlock(&dev
->struct_mutex
);
4458 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4459 * We need to replace this with a semaphore, or something.
4461 dev_priv
->mm
.suspended
= 1;
4462 del_timer(&dev_priv
->hangcheck_timer
);
4464 /* Cancel the retire work handler, wait for it to finish if running
4466 mutex_unlock(&dev
->struct_mutex
);
4467 cancel_delayed_work_sync(&dev_priv
->mm
.retire_work
);
4468 mutex_lock(&dev
->struct_mutex
);
4470 i915_kernel_lost_context(dev
);
4472 /* Flush the GPU along with all non-CPU write domains
4474 i915_gem_flush(dev
, I915_GEM_GPU_DOMAINS
, I915_GEM_GPU_DOMAINS
);
4475 seqno
= i915_add_request(dev
, NULL
, I915_GEM_GPU_DOMAINS
);
4478 mutex_unlock(&dev
->struct_mutex
);
4482 dev_priv
->mm
.waiting_gem_seqno
= seqno
;
4486 cur_seqno
= i915_get_gem_seqno(dev
);
4487 if (i915_seqno_passed(cur_seqno
, seqno
))
4489 if (last_seqno
== cur_seqno
) {
4490 if (stuck
++ > 100) {
4491 DRM_ERROR("hardware wedged\n");
4492 atomic_set(&dev_priv
->mm
.wedged
, 1);
4493 DRM_WAKEUP(&dev_priv
->irq_queue
);
4498 last_seqno
= cur_seqno
;
4500 dev_priv
->mm
.waiting_gem_seqno
= 0;
4502 i915_gem_retire_requests(dev
);
4504 spin_lock(&dev_priv
->mm
.active_list_lock
);
4505 if (!atomic_read(&dev_priv
->mm
.wedged
)) {
4506 /* Active and flushing should now be empty as we've
4507 * waited for a sequence higher than any pending execbuffer
4509 WARN_ON(!list_empty(&dev_priv
->mm
.active_list
));
4510 WARN_ON(!list_empty(&dev_priv
->mm
.flushing_list
));
4511 /* Request should now be empty as we've also waited
4512 * for the last request in the list
4514 WARN_ON(!list_empty(&dev_priv
->mm
.request_list
));
4517 /* Empty the active and flushing lists to inactive. If there's
4518 * anything left at this point, it means that we're wedged and
4519 * nothing good's going to happen by leaving them there. So strip
4520 * the GPU domains and just stuff them onto inactive.
4522 while (!list_empty(&dev_priv
->mm
.active_list
)) {
4523 struct drm_gem_object
*obj
;
4524 uint32_t old_write_domain
;
4526 obj
= list_first_entry(&dev_priv
->mm
.active_list
,
4527 struct drm_i915_gem_object
,
4529 old_write_domain
= obj
->write_domain
;
4530 obj
->write_domain
&= ~I915_GEM_GPU_DOMAINS
;
4531 i915_gem_object_move_to_inactive(obj
);
4533 trace_i915_gem_object_change_domain(obj
,
4537 spin_unlock(&dev_priv
->mm
.active_list_lock
);
4539 while (!list_empty(&dev_priv
->mm
.flushing_list
)) {
4540 struct drm_gem_object
*obj
;
4541 uint32_t old_write_domain
;
4543 obj
= list_first_entry(&dev_priv
->mm
.flushing_list
,
4544 struct drm_i915_gem_object
,
4546 old_write_domain
= obj
->write_domain
;
4547 obj
->write_domain
&= ~I915_GEM_GPU_DOMAINS
;
4548 i915_gem_object_move_to_inactive(obj
);
4550 trace_i915_gem_object_change_domain(obj
,
4556 /* Move all inactive buffers out of the GTT. */
4557 ret
= i915_gem_evict_from_inactive_list(dev
);
4558 WARN_ON(!list_empty(&dev_priv
->mm
.inactive_list
));
4560 mutex_unlock(&dev
->struct_mutex
);
4564 i915_gem_cleanup_ringbuffer(dev
);
4565 mutex_unlock(&dev
->struct_mutex
);
4571 i915_gem_init_hws(struct drm_device
*dev
)
4573 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4574 struct drm_gem_object
*obj
;
4575 struct drm_i915_gem_object
*obj_priv
;
4578 /* If we need a physical address for the status page, it's already
4579 * initialized at driver load time.
4581 if (!I915_NEED_GFX_HWS(dev
))
4584 obj
= drm_gem_object_alloc(dev
, 4096);
4586 DRM_ERROR("Failed to allocate status page\n");
4589 obj_priv
= obj
->driver_private
;
4590 obj_priv
->agp_type
= AGP_USER_CACHED_MEMORY
;
4592 ret
= i915_gem_object_pin(obj
, 4096);
4594 drm_gem_object_unreference(obj
);
4598 dev_priv
->status_gfx_addr
= obj_priv
->gtt_offset
;
4600 dev_priv
->hw_status_page
= kmap(obj_priv
->pages
[0]);
4601 if (dev_priv
->hw_status_page
== NULL
) {
4602 DRM_ERROR("Failed to map status page.\n");
4603 memset(&dev_priv
->hws_map
, 0, sizeof(dev_priv
->hws_map
));
4604 i915_gem_object_unpin(obj
);
4605 drm_gem_object_unreference(obj
);
4608 dev_priv
->hws_obj
= obj
;
4609 memset(dev_priv
->hw_status_page
, 0, PAGE_SIZE
);
4610 I915_WRITE(HWS_PGA
, dev_priv
->status_gfx_addr
);
4611 I915_READ(HWS_PGA
); /* posting read */
4612 DRM_DEBUG_DRIVER("hws offset: 0x%08x\n", dev_priv
->status_gfx_addr
);
4618 i915_gem_cleanup_hws(struct drm_device
*dev
)
4620 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4621 struct drm_gem_object
*obj
;
4622 struct drm_i915_gem_object
*obj_priv
;
4624 if (dev_priv
->hws_obj
== NULL
)
4627 obj
= dev_priv
->hws_obj
;
4628 obj_priv
= obj
->driver_private
;
4630 kunmap(obj_priv
->pages
[0]);
4631 i915_gem_object_unpin(obj
);
4632 drm_gem_object_unreference(obj
);
4633 dev_priv
->hws_obj
= NULL
;
4635 memset(&dev_priv
->hws_map
, 0, sizeof(dev_priv
->hws_map
));
4636 dev_priv
->hw_status_page
= NULL
;
4638 /* Write high address into HWS_PGA when disabling. */
4639 I915_WRITE(HWS_PGA
, 0x1ffff000);
4643 i915_gem_init_ringbuffer(struct drm_device
*dev
)
4645 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4646 struct drm_gem_object
*obj
;
4647 struct drm_i915_gem_object
*obj_priv
;
4648 drm_i915_ring_buffer_t
*ring
= &dev_priv
->ring
;
4652 ret
= i915_gem_init_hws(dev
);
4656 obj
= drm_gem_object_alloc(dev
, 128 * 1024);
4658 DRM_ERROR("Failed to allocate ringbuffer\n");
4659 i915_gem_cleanup_hws(dev
);
4662 obj_priv
= obj
->driver_private
;
4664 ret
= i915_gem_object_pin(obj
, 4096);
4666 drm_gem_object_unreference(obj
);
4667 i915_gem_cleanup_hws(dev
);
4671 /* Set up the kernel mapping for the ring. */
4672 ring
->Size
= obj
->size
;
4674 ring
->map
.offset
= dev
->agp
->base
+ obj_priv
->gtt_offset
;
4675 ring
->map
.size
= obj
->size
;
4677 ring
->map
.flags
= 0;
4680 drm_core_ioremap_wc(&ring
->map
, dev
);
4681 if (ring
->map
.handle
== NULL
) {
4682 DRM_ERROR("Failed to map ringbuffer.\n");
4683 memset(&dev_priv
->ring
, 0, sizeof(dev_priv
->ring
));
4684 i915_gem_object_unpin(obj
);
4685 drm_gem_object_unreference(obj
);
4686 i915_gem_cleanup_hws(dev
);
4689 ring
->ring_obj
= obj
;
4690 ring
->virtual_start
= ring
->map
.handle
;
4692 /* Stop the ring if it's running. */
4693 I915_WRITE(PRB0_CTL
, 0);
4694 I915_WRITE(PRB0_TAIL
, 0);
4695 I915_WRITE(PRB0_HEAD
, 0);
4697 /* Initialize the ring. */
4698 I915_WRITE(PRB0_START
, obj_priv
->gtt_offset
);
4699 head
= I915_READ(PRB0_HEAD
) & HEAD_ADDR
;
4701 /* G45 ring initialization fails to reset head to zero */
4703 DRM_ERROR("Ring head not reset to zero "
4704 "ctl %08x head %08x tail %08x start %08x\n",
4705 I915_READ(PRB0_CTL
),
4706 I915_READ(PRB0_HEAD
),
4707 I915_READ(PRB0_TAIL
),
4708 I915_READ(PRB0_START
));
4709 I915_WRITE(PRB0_HEAD
, 0);
4711 DRM_ERROR("Ring head forced to zero "
4712 "ctl %08x head %08x tail %08x start %08x\n",
4713 I915_READ(PRB0_CTL
),
4714 I915_READ(PRB0_HEAD
),
4715 I915_READ(PRB0_TAIL
),
4716 I915_READ(PRB0_START
));
4719 I915_WRITE(PRB0_CTL
,
4720 ((obj
->size
- 4096) & RING_NR_PAGES
) |
4724 head
= I915_READ(PRB0_HEAD
) & HEAD_ADDR
;
4726 /* If the head is still not zero, the ring is dead */
4728 DRM_ERROR("Ring initialization failed "
4729 "ctl %08x head %08x tail %08x start %08x\n",
4730 I915_READ(PRB0_CTL
),
4731 I915_READ(PRB0_HEAD
),
4732 I915_READ(PRB0_TAIL
),
4733 I915_READ(PRB0_START
));
4737 /* Update our cache of the ring state */
4738 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
4739 i915_kernel_lost_context(dev
);
4741 ring
->head
= I915_READ(PRB0_HEAD
) & HEAD_ADDR
;
4742 ring
->tail
= I915_READ(PRB0_TAIL
) & TAIL_ADDR
;
4743 ring
->space
= ring
->head
- (ring
->tail
+ 8);
4744 if (ring
->space
< 0)
4745 ring
->space
+= ring
->Size
;
4752 i915_gem_cleanup_ringbuffer(struct drm_device
*dev
)
4754 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4756 if (dev_priv
->ring
.ring_obj
== NULL
)
4759 drm_core_ioremapfree(&dev_priv
->ring
.map
, dev
);
4761 i915_gem_object_unpin(dev_priv
->ring
.ring_obj
);
4762 drm_gem_object_unreference(dev_priv
->ring
.ring_obj
);
4763 dev_priv
->ring
.ring_obj
= NULL
;
4764 memset(&dev_priv
->ring
, 0, sizeof(dev_priv
->ring
));
4766 i915_gem_cleanup_hws(dev
);
4770 i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
4771 struct drm_file
*file_priv
)
4773 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4776 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4779 if (atomic_read(&dev_priv
->mm
.wedged
)) {
4780 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4781 atomic_set(&dev_priv
->mm
.wedged
, 0);
4784 mutex_lock(&dev
->struct_mutex
);
4785 dev_priv
->mm
.suspended
= 0;
4787 ret
= i915_gem_init_ringbuffer(dev
);
4789 mutex_unlock(&dev
->struct_mutex
);
4793 spin_lock(&dev_priv
->mm
.active_list_lock
);
4794 BUG_ON(!list_empty(&dev_priv
->mm
.active_list
));
4795 spin_unlock(&dev_priv
->mm
.active_list_lock
);
4797 BUG_ON(!list_empty(&dev_priv
->mm
.flushing_list
));
4798 BUG_ON(!list_empty(&dev_priv
->mm
.inactive_list
));
4799 BUG_ON(!list_empty(&dev_priv
->mm
.request_list
));
4800 mutex_unlock(&dev
->struct_mutex
);
4802 drm_irq_install(dev
);
4808 i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
4809 struct drm_file
*file_priv
)
4811 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4814 drm_irq_uninstall(dev
);
4815 return i915_gem_idle(dev
);
4819 i915_gem_lastclose(struct drm_device
*dev
)
4823 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4826 ret
= i915_gem_idle(dev
);
4828 DRM_ERROR("failed to idle hardware: %d\n", ret
);
4832 i915_gem_load(struct drm_device
*dev
)
4835 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4837 spin_lock_init(&dev_priv
->mm
.active_list_lock
);
4838 INIT_LIST_HEAD(&dev_priv
->mm
.active_list
);
4839 INIT_LIST_HEAD(&dev_priv
->mm
.flushing_list
);
4840 INIT_LIST_HEAD(&dev_priv
->mm
.gpu_write_list
);
4841 INIT_LIST_HEAD(&dev_priv
->mm
.inactive_list
);
4842 INIT_LIST_HEAD(&dev_priv
->mm
.request_list
);
4843 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
4844 INIT_DELAYED_WORK(&dev_priv
->mm
.retire_work
,
4845 i915_gem_retire_work_handler
);
4846 dev_priv
->mm
.next_gem_seqno
= 1;
4848 spin_lock(&shrink_list_lock
);
4849 list_add(&dev_priv
->mm
.shrink_list
, &shrink_list
);
4850 spin_unlock(&shrink_list_lock
);
4852 /* Old X drivers will take 0-2 for front, back, depth buffers */
4853 dev_priv
->fence_reg_start
= 3;
4855 if (IS_I965G(dev
) || IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
4856 dev_priv
->num_fence_regs
= 16;
4858 dev_priv
->num_fence_regs
= 8;
4860 /* Initialize fence registers to zero */
4861 if (IS_I965G(dev
)) {
4862 for (i
= 0; i
< 16; i
++)
4863 I915_WRITE64(FENCE_REG_965_0
+ (i
* 8), 0);
4865 for (i
= 0; i
< 8; i
++)
4866 I915_WRITE(FENCE_REG_830_0
+ (i
* 4), 0);
4867 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
4868 for (i
= 0; i
< 8; i
++)
4869 I915_WRITE(FENCE_REG_945_8
+ (i
* 4), 0);
4871 i915_gem_detect_bit_6_swizzle(dev
);
4872 init_waitqueue_head(&dev_priv
->pending_flip_queue
);
4876 * Create a physically contiguous memory object for this object
4877 * e.g. for cursor + overlay regs
4879 int i915_gem_init_phys_object(struct drm_device
*dev
,
4882 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4883 struct drm_i915_gem_phys_object
*phys_obj
;
4886 if (dev_priv
->mm
.phys_objs
[id
- 1] || !size
)
4889 phys_obj
= kzalloc(sizeof(struct drm_i915_gem_phys_object
), GFP_KERNEL
);
4895 phys_obj
->handle
= drm_pci_alloc(dev
, size
, 0);
4896 if (!phys_obj
->handle
) {
4901 set_memory_wc((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
4904 dev_priv
->mm
.phys_objs
[id
- 1] = phys_obj
;
4912 void i915_gem_free_phys_object(struct drm_device
*dev
, int id
)
4914 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4915 struct drm_i915_gem_phys_object
*phys_obj
;
4917 if (!dev_priv
->mm
.phys_objs
[id
- 1])
4920 phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
4921 if (phys_obj
->cur_obj
) {
4922 i915_gem_detach_phys_object(dev
, phys_obj
->cur_obj
);
4926 set_memory_wb((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
4928 drm_pci_free(dev
, phys_obj
->handle
);
4930 dev_priv
->mm
.phys_objs
[id
- 1] = NULL
;
4933 void i915_gem_free_all_phys_object(struct drm_device
*dev
)
4937 for (i
= I915_GEM_PHYS_CURSOR_0
; i
<= I915_MAX_PHYS_OBJECT
; i
++)
4938 i915_gem_free_phys_object(dev
, i
);
4941 void i915_gem_detach_phys_object(struct drm_device
*dev
,
4942 struct drm_gem_object
*obj
)
4944 struct drm_i915_gem_object
*obj_priv
;
4949 obj_priv
= obj
->driver_private
;
4950 if (!obj_priv
->phys_obj
)
4953 ret
= i915_gem_object_get_pages(obj
, 0);
4957 page_count
= obj
->size
/ PAGE_SIZE
;
4959 for (i
= 0; i
< page_count
; i
++) {
4960 char *dst
= kmap_atomic(obj_priv
->pages
[i
], KM_USER0
);
4961 char *src
= obj_priv
->phys_obj
->handle
->vaddr
+ (i
* PAGE_SIZE
);
4963 memcpy(dst
, src
, PAGE_SIZE
);
4964 kunmap_atomic(dst
, KM_USER0
);
4966 drm_clflush_pages(obj_priv
->pages
, page_count
);
4967 drm_agp_chipset_flush(dev
);
4969 i915_gem_object_put_pages(obj
);
4971 obj_priv
->phys_obj
->cur_obj
= NULL
;
4972 obj_priv
->phys_obj
= NULL
;
4976 i915_gem_attach_phys_object(struct drm_device
*dev
,
4977 struct drm_gem_object
*obj
, int id
)
4979 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4980 struct drm_i915_gem_object
*obj_priv
;
4985 if (id
> I915_MAX_PHYS_OBJECT
)
4988 obj_priv
= obj
->driver_private
;
4990 if (obj_priv
->phys_obj
) {
4991 if (obj_priv
->phys_obj
->id
== id
)
4993 i915_gem_detach_phys_object(dev
, obj
);
4997 /* create a new object */
4998 if (!dev_priv
->mm
.phys_objs
[id
- 1]) {
4999 ret
= i915_gem_init_phys_object(dev
, id
,
5002 DRM_ERROR("failed to init phys object %d size: %zu\n", id
, obj
->size
);
5007 /* bind to the object */
5008 obj_priv
->phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
5009 obj_priv
->phys_obj
->cur_obj
= obj
;
5011 ret
= i915_gem_object_get_pages(obj
, 0);
5013 DRM_ERROR("failed to get page list\n");
5017 page_count
= obj
->size
/ PAGE_SIZE
;
5019 for (i
= 0; i
< page_count
; i
++) {
5020 char *src
= kmap_atomic(obj_priv
->pages
[i
], KM_USER0
);
5021 char *dst
= obj_priv
->phys_obj
->handle
->vaddr
+ (i
* PAGE_SIZE
);
5023 memcpy(dst
, src
, PAGE_SIZE
);
5024 kunmap_atomic(src
, KM_USER0
);
5027 i915_gem_object_put_pages(obj
);
5035 i915_gem_phys_pwrite(struct drm_device
*dev
, struct drm_gem_object
*obj
,
5036 struct drm_i915_gem_pwrite
*args
,
5037 struct drm_file
*file_priv
)
5039 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
5042 char __user
*user_data
;
5044 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
5045 obj_addr
= obj_priv
->phys_obj
->handle
->vaddr
+ args
->offset
;
5047 DRM_DEBUG_DRIVER("obj_addr %p, %lld\n", obj_addr
, args
->size
);
5048 ret
= copy_from_user(obj_addr
, user_data
, args
->size
);
5052 drm_agp_chipset_flush(dev
);
5056 void i915_gem_release(struct drm_device
* dev
, struct drm_file
*file_priv
)
5058 struct drm_i915_file_private
*i915_file_priv
= file_priv
->driver_priv
;
5060 /* Clean up our request list when the client is going away, so that
5061 * later retire_requests won't dereference our soon-to-be-gone
5064 mutex_lock(&dev
->struct_mutex
);
5065 while (!list_empty(&i915_file_priv
->mm
.request_list
))
5066 list_del_init(i915_file_priv
->mm
.request_list
.next
);
5067 mutex_unlock(&dev
->struct_mutex
);
5071 i915_gem_shrink(int nr_to_scan
, gfp_t gfp_mask
)
5073 drm_i915_private_t
*dev_priv
, *next_dev
;
5074 struct drm_i915_gem_object
*obj_priv
, *next_obj
;
5076 int would_deadlock
= 1;
5078 /* "fast-path" to count number of available objects */
5079 if (nr_to_scan
== 0) {
5080 spin_lock(&shrink_list_lock
);
5081 list_for_each_entry(dev_priv
, &shrink_list
, mm
.shrink_list
) {
5082 struct drm_device
*dev
= dev_priv
->dev
;
5084 if (mutex_trylock(&dev
->struct_mutex
)) {
5085 list_for_each_entry(obj_priv
,
5086 &dev_priv
->mm
.inactive_list
,
5089 mutex_unlock(&dev
->struct_mutex
);
5092 spin_unlock(&shrink_list_lock
);
5094 return (cnt
/ 100) * sysctl_vfs_cache_pressure
;
5097 spin_lock(&shrink_list_lock
);
5099 /* first scan for clean buffers */
5100 list_for_each_entry_safe(dev_priv
, next_dev
,
5101 &shrink_list
, mm
.shrink_list
) {
5102 struct drm_device
*dev
= dev_priv
->dev
;
5104 if (! mutex_trylock(&dev
->struct_mutex
))
5107 spin_unlock(&shrink_list_lock
);
5109 i915_gem_retire_requests(dev
);
5111 list_for_each_entry_safe(obj_priv
, next_obj
,
5112 &dev_priv
->mm
.inactive_list
,
5114 if (i915_gem_object_is_purgeable(obj_priv
)) {
5115 i915_gem_object_unbind(obj_priv
->obj
);
5116 if (--nr_to_scan
<= 0)
5121 spin_lock(&shrink_list_lock
);
5122 mutex_unlock(&dev
->struct_mutex
);
5126 if (nr_to_scan
<= 0)
5130 /* second pass, evict/count anything still on the inactive list */
5131 list_for_each_entry_safe(dev_priv
, next_dev
,
5132 &shrink_list
, mm
.shrink_list
) {
5133 struct drm_device
*dev
= dev_priv
->dev
;
5135 if (! mutex_trylock(&dev
->struct_mutex
))
5138 spin_unlock(&shrink_list_lock
);
5140 list_for_each_entry_safe(obj_priv
, next_obj
,
5141 &dev_priv
->mm
.inactive_list
,
5143 if (nr_to_scan
> 0) {
5144 i915_gem_object_unbind(obj_priv
->obj
);
5150 spin_lock(&shrink_list_lock
);
5151 mutex_unlock(&dev
->struct_mutex
);
5156 spin_unlock(&shrink_list_lock
);
5161 return (cnt
/ 100) * sysctl_vfs_cache_pressure
;
5166 static struct shrinker shrinker
= {
5167 .shrink
= i915_gem_shrink
,
5168 .seeks
= DEFAULT_SEEKS
,
5172 i915_gem_shrinker_init(void)
5174 register_shrinker(&shrinker
);
5178 i915_gem_shrinker_exit(void)
5180 unregister_shrinker(&shrinker
);