2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/i915_drm.h>
31 #include "i915_trace.h"
32 #include "intel_drv.h"
33 #include <linux/shmem_fs.h>
34 #include <linux/slab.h>
35 #include <linux/swap.h>
36 #include <linux/pci.h>
37 #include <linux/dma-buf.h>
39 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
);
40 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
);
41 static __must_check
int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object
*obj
,
43 bool map_and_fenceable
,
45 static int i915_gem_phys_pwrite(struct drm_device
*dev
,
46 struct drm_i915_gem_object
*obj
,
47 struct drm_i915_gem_pwrite
*args
,
48 struct drm_file
*file
);
50 static void i915_gem_write_fence(struct drm_device
*dev
, int reg
,
51 struct drm_i915_gem_object
*obj
);
52 static void i915_gem_object_update_fence(struct drm_i915_gem_object
*obj
,
53 struct drm_i915_fence_reg
*fence
,
56 static int i915_gem_inactive_shrink(struct shrinker
*shrinker
,
57 struct shrink_control
*sc
);
58 static long i915_gem_purge(struct drm_i915_private
*dev_priv
, long target
);
59 static void i915_gem_shrink_all(struct drm_i915_private
*dev_priv
);
60 static void i915_gem_object_truncate(struct drm_i915_gem_object
*obj
);
62 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object
*obj
)
65 i915_gem_release_mmap(obj
);
67 /* As we do not have an associated fence register, we will force
68 * a tiling change if we ever need to acquire one.
70 obj
->fence_dirty
= false;
71 obj
->fence_reg
= I915_FENCE_REG_NONE
;
74 /* some bookkeeping */
75 static void i915_gem_info_add_obj(struct drm_i915_private
*dev_priv
,
78 dev_priv
->mm
.object_count
++;
79 dev_priv
->mm
.object_memory
+= size
;
82 static void i915_gem_info_remove_obj(struct drm_i915_private
*dev_priv
,
85 dev_priv
->mm
.object_count
--;
86 dev_priv
->mm
.object_memory
-= size
;
90 i915_gem_wait_for_error(struct drm_device
*dev
)
92 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
93 struct completion
*x
= &dev_priv
->error_completion
;
97 if (!atomic_read(&dev_priv
->mm
.wedged
))
101 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
102 * userspace. If it takes that long something really bad is going on and
103 * we should simply try to bail out and fail as gracefully as possible.
105 ret
= wait_for_completion_interruptible_timeout(x
, 10*HZ
);
107 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
109 } else if (ret
< 0) {
113 if (atomic_read(&dev_priv
->mm
.wedged
)) {
114 /* GPU is hung, bump the completion count to account for
115 * the token we just consumed so that we never hit zero and
116 * end up waiting upon a subsequent completion event that
119 spin_lock_irqsave(&x
->wait
.lock
, flags
);
121 spin_unlock_irqrestore(&x
->wait
.lock
, flags
);
126 int i915_mutex_lock_interruptible(struct drm_device
*dev
)
130 ret
= i915_gem_wait_for_error(dev
);
134 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
138 WARN_ON(i915_verify_lists(dev
));
143 i915_gem_object_is_inactive(struct drm_i915_gem_object
*obj
)
145 return obj
->gtt_space
&& !obj
->active
;
149 i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
150 struct drm_file
*file
)
152 struct drm_i915_gem_init
*args
= data
;
154 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
157 if (args
->gtt_start
>= args
->gtt_end
||
158 (args
->gtt_end
| args
->gtt_start
) & (PAGE_SIZE
- 1))
161 /* GEM with user mode setting was never supported on ilk and later. */
162 if (INTEL_INFO(dev
)->gen
>= 5)
165 mutex_lock(&dev
->struct_mutex
);
166 i915_gem_init_global_gtt(dev
, args
->gtt_start
,
167 args
->gtt_end
, args
->gtt_end
);
168 mutex_unlock(&dev
->struct_mutex
);
174 i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
175 struct drm_file
*file
)
177 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
178 struct drm_i915_gem_get_aperture
*args
= data
;
179 struct drm_i915_gem_object
*obj
;
183 mutex_lock(&dev
->struct_mutex
);
184 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, gtt_list
)
186 pinned
+= obj
->gtt_space
->size
;
187 mutex_unlock(&dev
->struct_mutex
);
189 args
->aper_size
= dev_priv
->mm
.gtt_total
;
190 args
->aper_available_size
= args
->aper_size
- pinned
;
196 i915_gem_create(struct drm_file
*file
,
197 struct drm_device
*dev
,
201 struct drm_i915_gem_object
*obj
;
205 size
= roundup(size
, PAGE_SIZE
);
209 /* Allocate the new object */
210 obj
= i915_gem_alloc_object(dev
, size
);
214 ret
= drm_gem_handle_create(file
, &obj
->base
, &handle
);
216 drm_gem_object_release(&obj
->base
);
217 i915_gem_info_remove_obj(dev
->dev_private
, obj
->base
.size
);
222 /* drop reference from allocate - handle holds it now */
223 drm_gem_object_unreference(&obj
->base
);
224 trace_i915_gem_object_create(obj
);
231 i915_gem_dumb_create(struct drm_file
*file
,
232 struct drm_device
*dev
,
233 struct drm_mode_create_dumb
*args
)
235 /* have to work out size/pitch and return them */
236 args
->pitch
= ALIGN(args
->width
* ((args
->bpp
+ 7) / 8), 64);
237 args
->size
= args
->pitch
* args
->height
;
238 return i915_gem_create(file
, dev
,
239 args
->size
, &args
->handle
);
242 int i915_gem_dumb_destroy(struct drm_file
*file
,
243 struct drm_device
*dev
,
246 return drm_gem_handle_delete(file
, handle
);
250 * Creates a new mm object and returns a handle to it.
253 i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
254 struct drm_file
*file
)
256 struct drm_i915_gem_create
*args
= data
;
258 return i915_gem_create(file
, dev
,
259 args
->size
, &args
->handle
);
262 static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object
*obj
)
264 drm_i915_private_t
*dev_priv
= obj
->base
.dev
->dev_private
;
266 return dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_9_10_17
&&
267 obj
->tiling_mode
!= I915_TILING_NONE
;
271 __copy_to_user_swizzled(char __user
*cpu_vaddr
,
272 const char *gpu_vaddr
, int gpu_offset
,
275 int ret
, cpu_offset
= 0;
278 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
279 int this_length
= min(cacheline_end
- gpu_offset
, length
);
280 int swizzled_gpu_offset
= gpu_offset
^ 64;
282 ret
= __copy_to_user(cpu_vaddr
+ cpu_offset
,
283 gpu_vaddr
+ swizzled_gpu_offset
,
288 cpu_offset
+= this_length
;
289 gpu_offset
+= this_length
;
290 length
-= this_length
;
297 __copy_from_user_swizzled(char *gpu_vaddr
, int gpu_offset
,
298 const char __user
*cpu_vaddr
,
301 int ret
, cpu_offset
= 0;
304 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
305 int this_length
= min(cacheline_end
- gpu_offset
, length
);
306 int swizzled_gpu_offset
= gpu_offset
^ 64;
308 ret
= __copy_from_user(gpu_vaddr
+ swizzled_gpu_offset
,
309 cpu_vaddr
+ cpu_offset
,
314 cpu_offset
+= this_length
;
315 gpu_offset
+= this_length
;
316 length
-= this_length
;
322 /* Per-page copy function for the shmem pread fastpath.
323 * Flushes invalid cachelines before reading the target if
324 * needs_clflush is set. */
326 shmem_pread_fast(struct page
*page
, int shmem_page_offset
, int page_length
,
327 char __user
*user_data
,
328 bool page_do_bit17_swizzling
, bool needs_clflush
)
333 if (unlikely(page_do_bit17_swizzling
))
336 vaddr
= kmap_atomic(page
);
338 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
340 ret
= __copy_to_user_inatomic(user_data
,
341 vaddr
+ shmem_page_offset
,
343 kunmap_atomic(vaddr
);
345 return ret
? -EFAULT
: 0;
349 shmem_clflush_swizzled_range(char *addr
, unsigned long length
,
352 if (unlikely(swizzled
)) {
353 unsigned long start
= (unsigned long) addr
;
354 unsigned long end
= (unsigned long) addr
+ length
;
356 /* For swizzling simply ensure that we always flush both
357 * channels. Lame, but simple and it works. Swizzled
358 * pwrite/pread is far from a hotpath - current userspace
359 * doesn't use it at all. */
360 start
= round_down(start
, 128);
361 end
= round_up(end
, 128);
363 drm_clflush_virt_range((void *)start
, end
- start
);
365 drm_clflush_virt_range(addr
, length
);
370 /* Only difference to the fast-path function is that this can handle bit17
371 * and uses non-atomic copy and kmap functions. */
373 shmem_pread_slow(struct page
*page
, int shmem_page_offset
, int page_length
,
374 char __user
*user_data
,
375 bool page_do_bit17_swizzling
, bool needs_clflush
)
382 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
384 page_do_bit17_swizzling
);
386 if (page_do_bit17_swizzling
)
387 ret
= __copy_to_user_swizzled(user_data
,
388 vaddr
, shmem_page_offset
,
391 ret
= __copy_to_user(user_data
,
392 vaddr
+ shmem_page_offset
,
396 return ret
? - EFAULT
: 0;
400 i915_gem_shmem_pread(struct drm_device
*dev
,
401 struct drm_i915_gem_object
*obj
,
402 struct drm_i915_gem_pread
*args
,
403 struct drm_file
*file
)
405 char __user
*user_data
;
408 int shmem_page_offset
, page_length
, ret
= 0;
409 int obj_do_bit17_swizzling
, page_do_bit17_swizzling
;
410 int hit_slowpath
= 0;
412 int needs_clflush
= 0;
413 struct scatterlist
*sg
;
416 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
419 obj_do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
421 if (!(obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
)) {
422 /* If we're not in the cpu read domain, set ourself into the gtt
423 * read domain and manually flush cachelines (if required). This
424 * optimizes for the case when the gpu will dirty the data
425 * anyway again before the next pread happens. */
426 if (obj
->cache_level
== I915_CACHE_NONE
)
428 if (obj
->gtt_space
) {
429 ret
= i915_gem_object_set_to_gtt_domain(obj
, false);
435 ret
= i915_gem_object_get_pages(obj
);
439 i915_gem_object_pin_pages(obj
);
441 offset
= args
->offset
;
443 for_each_sg(obj
->pages
->sgl
, sg
, obj
->pages
->nents
, i
) {
446 if (i
< offset
>> PAGE_SHIFT
)
452 /* Operation in this page
454 * shmem_page_offset = offset within page in shmem file
455 * page_length = bytes to copy for this page
457 shmem_page_offset
= offset_in_page(offset
);
458 page_length
= remain
;
459 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
460 page_length
= PAGE_SIZE
- shmem_page_offset
;
463 page_do_bit17_swizzling
= obj_do_bit17_swizzling
&&
464 (page_to_phys(page
) & (1 << 17)) != 0;
466 ret
= shmem_pread_fast(page
, shmem_page_offset
, page_length
,
467 user_data
, page_do_bit17_swizzling
,
473 mutex_unlock(&dev
->struct_mutex
);
476 ret
= fault_in_multipages_writeable(user_data
, remain
);
477 /* Userspace is tricking us, but we've already clobbered
478 * its pages with the prefault and promised to write the
479 * data up to the first fault. Hence ignore any errors
480 * and just continue. */
485 ret
= shmem_pread_slow(page
, shmem_page_offset
, page_length
,
486 user_data
, page_do_bit17_swizzling
,
489 mutex_lock(&dev
->struct_mutex
);
492 mark_page_accessed(page
);
497 remain
-= page_length
;
498 user_data
+= page_length
;
499 offset
+= page_length
;
503 i915_gem_object_unpin_pages(obj
);
506 /* Fixup: Kill any reinstated backing storage pages */
507 if (obj
->madv
== __I915_MADV_PURGED
)
508 i915_gem_object_truncate(obj
);
515 * Reads data from the object referenced by handle.
517 * On error, the contents of *data are undefined.
520 i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
521 struct drm_file
*file
)
523 struct drm_i915_gem_pread
*args
= data
;
524 struct drm_i915_gem_object
*obj
;
530 if (!access_ok(VERIFY_WRITE
,
531 (char __user
*)(uintptr_t)args
->data_ptr
,
535 ret
= i915_mutex_lock_interruptible(dev
);
539 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
540 if (&obj
->base
== NULL
) {
545 /* Bounds check source. */
546 if (args
->offset
> obj
->base
.size
||
547 args
->size
> obj
->base
.size
- args
->offset
) {
552 /* prime objects have no backing filp to GEM pread/pwrite
555 if (!obj
->base
.filp
) {
560 trace_i915_gem_object_pread(obj
, args
->offset
, args
->size
);
562 ret
= i915_gem_shmem_pread(dev
, obj
, args
, file
);
565 drm_gem_object_unreference(&obj
->base
);
567 mutex_unlock(&dev
->struct_mutex
);
571 /* This is the fast write path which cannot handle
572 * page faults in the source data
576 fast_user_write(struct io_mapping
*mapping
,
577 loff_t page_base
, int page_offset
,
578 char __user
*user_data
,
581 void __iomem
*vaddr_atomic
;
583 unsigned long unwritten
;
585 vaddr_atomic
= io_mapping_map_atomic_wc(mapping
, page_base
);
586 /* We can use the cpu mem copy function because this is X86. */
587 vaddr
= (void __force
*)vaddr_atomic
+ page_offset
;
588 unwritten
= __copy_from_user_inatomic_nocache(vaddr
,
590 io_mapping_unmap_atomic(vaddr_atomic
);
595 * This is the fast pwrite path, where we copy the data directly from the
596 * user into the GTT, uncached.
599 i915_gem_gtt_pwrite_fast(struct drm_device
*dev
,
600 struct drm_i915_gem_object
*obj
,
601 struct drm_i915_gem_pwrite
*args
,
602 struct drm_file
*file
)
604 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
606 loff_t offset
, page_base
;
607 char __user
*user_data
;
608 int page_offset
, page_length
, ret
;
610 ret
= i915_gem_object_pin(obj
, 0, true, true);
614 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
618 ret
= i915_gem_object_put_fence(obj
);
622 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
625 offset
= obj
->gtt_offset
+ args
->offset
;
628 /* Operation in this page
630 * page_base = page offset within aperture
631 * page_offset = offset within page
632 * page_length = bytes to copy for this page
634 page_base
= offset
& PAGE_MASK
;
635 page_offset
= offset_in_page(offset
);
636 page_length
= remain
;
637 if ((page_offset
+ remain
) > PAGE_SIZE
)
638 page_length
= PAGE_SIZE
- page_offset
;
640 /* If we get a fault while copying data, then (presumably) our
641 * source page isn't available. Return the error and we'll
642 * retry in the slow path.
644 if (fast_user_write(dev_priv
->mm
.gtt_mapping
, page_base
,
645 page_offset
, user_data
, page_length
)) {
650 remain
-= page_length
;
651 user_data
+= page_length
;
652 offset
+= page_length
;
656 i915_gem_object_unpin(obj
);
661 /* Per-page copy function for the shmem pwrite fastpath.
662 * Flushes invalid cachelines before writing to the target if
663 * needs_clflush_before is set and flushes out any written cachelines after
664 * writing if needs_clflush is set. */
666 shmem_pwrite_fast(struct page
*page
, int shmem_page_offset
, int page_length
,
667 char __user
*user_data
,
668 bool page_do_bit17_swizzling
,
669 bool needs_clflush_before
,
670 bool needs_clflush_after
)
675 if (unlikely(page_do_bit17_swizzling
))
678 vaddr
= kmap_atomic(page
);
679 if (needs_clflush_before
)
680 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
682 ret
= __copy_from_user_inatomic_nocache(vaddr
+ shmem_page_offset
,
685 if (needs_clflush_after
)
686 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
688 kunmap_atomic(vaddr
);
690 return ret
? -EFAULT
: 0;
693 /* Only difference to the fast-path function is that this can handle bit17
694 * and uses non-atomic copy and kmap functions. */
696 shmem_pwrite_slow(struct page
*page
, int shmem_page_offset
, int page_length
,
697 char __user
*user_data
,
698 bool page_do_bit17_swizzling
,
699 bool needs_clflush_before
,
700 bool needs_clflush_after
)
706 if (unlikely(needs_clflush_before
|| page_do_bit17_swizzling
))
707 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
709 page_do_bit17_swizzling
);
710 if (page_do_bit17_swizzling
)
711 ret
= __copy_from_user_swizzled(vaddr
, shmem_page_offset
,
715 ret
= __copy_from_user(vaddr
+ shmem_page_offset
,
718 if (needs_clflush_after
)
719 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
721 page_do_bit17_swizzling
);
724 return ret
? -EFAULT
: 0;
728 i915_gem_shmem_pwrite(struct drm_device
*dev
,
729 struct drm_i915_gem_object
*obj
,
730 struct drm_i915_gem_pwrite
*args
,
731 struct drm_file
*file
)
735 char __user
*user_data
;
736 int shmem_page_offset
, page_length
, ret
= 0;
737 int obj_do_bit17_swizzling
, page_do_bit17_swizzling
;
738 int hit_slowpath
= 0;
739 int needs_clflush_after
= 0;
740 int needs_clflush_before
= 0;
742 struct scatterlist
*sg
;
744 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
747 obj_do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
749 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
750 /* If we're not in the cpu write domain, set ourself into the gtt
751 * write domain and manually flush cachelines (if required). This
752 * optimizes for the case when the gpu will use the data
753 * right away and we therefore have to clflush anyway. */
754 if (obj
->cache_level
== I915_CACHE_NONE
)
755 needs_clflush_after
= 1;
756 if (obj
->gtt_space
) {
757 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
762 /* Same trick applies for invalidate partially written cachelines before
764 if (!(obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
)
765 && obj
->cache_level
== I915_CACHE_NONE
)
766 needs_clflush_before
= 1;
768 ret
= i915_gem_object_get_pages(obj
);
772 i915_gem_object_pin_pages(obj
);
774 offset
= args
->offset
;
777 for_each_sg(obj
->pages
->sgl
, sg
, obj
->pages
->nents
, i
) {
779 int partial_cacheline_write
;
781 if (i
< offset
>> PAGE_SHIFT
)
787 /* Operation in this page
789 * shmem_page_offset = offset within page in shmem file
790 * page_length = bytes to copy for this page
792 shmem_page_offset
= offset_in_page(offset
);
794 page_length
= remain
;
795 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
796 page_length
= PAGE_SIZE
- shmem_page_offset
;
798 /* If we don't overwrite a cacheline completely we need to be
799 * careful to have up-to-date data by first clflushing. Don't
800 * overcomplicate things and flush the entire patch. */
801 partial_cacheline_write
= needs_clflush_before
&&
802 ((shmem_page_offset
| page_length
)
803 & (boot_cpu_data
.x86_clflush_size
- 1));
806 page_do_bit17_swizzling
= obj_do_bit17_swizzling
&&
807 (page_to_phys(page
) & (1 << 17)) != 0;
809 ret
= shmem_pwrite_fast(page
, shmem_page_offset
, page_length
,
810 user_data
, page_do_bit17_swizzling
,
811 partial_cacheline_write
,
812 needs_clflush_after
);
817 mutex_unlock(&dev
->struct_mutex
);
818 ret
= shmem_pwrite_slow(page
, shmem_page_offset
, page_length
,
819 user_data
, page_do_bit17_swizzling
,
820 partial_cacheline_write
,
821 needs_clflush_after
);
823 mutex_lock(&dev
->struct_mutex
);
826 set_page_dirty(page
);
827 mark_page_accessed(page
);
832 remain
-= page_length
;
833 user_data
+= page_length
;
834 offset
+= page_length
;
838 i915_gem_object_unpin_pages(obj
);
841 /* Fixup: Kill any reinstated backing storage pages */
842 if (obj
->madv
== __I915_MADV_PURGED
)
843 i915_gem_object_truncate(obj
);
844 /* and flush dirty cachelines in case the object isn't in the cpu write
846 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
847 i915_gem_clflush_object(obj
);
848 intel_gtt_chipset_flush();
852 if (needs_clflush_after
)
853 intel_gtt_chipset_flush();
859 * Writes data to the object referenced by handle.
861 * On error, the contents of the buffer that were to be modified are undefined.
864 i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
865 struct drm_file
*file
)
867 struct drm_i915_gem_pwrite
*args
= data
;
868 struct drm_i915_gem_object
*obj
;
874 if (!access_ok(VERIFY_READ
,
875 (char __user
*)(uintptr_t)args
->data_ptr
,
879 ret
= fault_in_multipages_readable((char __user
*)(uintptr_t)args
->data_ptr
,
884 ret
= i915_mutex_lock_interruptible(dev
);
888 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
889 if (&obj
->base
== NULL
) {
894 /* Bounds check destination. */
895 if (args
->offset
> obj
->base
.size
||
896 args
->size
> obj
->base
.size
- args
->offset
) {
901 /* prime objects have no backing filp to GEM pread/pwrite
904 if (!obj
->base
.filp
) {
909 trace_i915_gem_object_pwrite(obj
, args
->offset
, args
->size
);
912 /* We can only do the GTT pwrite on untiled buffers, as otherwise
913 * it would end up going through the fenced access, and we'll get
914 * different detiling behavior between reading and writing.
915 * pread/pwrite currently are reading and writing from the CPU
916 * perspective, requiring manual detiling by the client.
919 ret
= i915_gem_phys_pwrite(dev
, obj
, args
, file
);
923 if (obj
->cache_level
== I915_CACHE_NONE
&&
924 obj
->tiling_mode
== I915_TILING_NONE
&&
925 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
926 ret
= i915_gem_gtt_pwrite_fast(dev
, obj
, args
, file
);
927 /* Note that the gtt paths might fail with non-page-backed user
928 * pointers (e.g. gtt mappings when moving data between
929 * textures). Fallback to the shmem path in that case. */
932 if (ret
== -EFAULT
|| ret
== -ENOSPC
)
933 ret
= i915_gem_shmem_pwrite(dev
, obj
, args
, file
);
936 drm_gem_object_unreference(&obj
->base
);
938 mutex_unlock(&dev
->struct_mutex
);
943 i915_gem_check_wedge(struct drm_i915_private
*dev_priv
,
946 if (atomic_read(&dev_priv
->mm
.wedged
)) {
947 struct completion
*x
= &dev_priv
->error_completion
;
948 bool recovery_complete
;
951 /* Give the error handler a chance to run. */
952 spin_lock_irqsave(&x
->wait
.lock
, flags
);
953 recovery_complete
= x
->done
> 0;
954 spin_unlock_irqrestore(&x
->wait
.lock
, flags
);
956 /* Non-interruptible callers can't handle -EAGAIN, hence return
957 * -EIO unconditionally for these. */
961 /* Recovery complete, but still wedged means reset failure. */
962 if (recovery_complete
)
972 * Compare seqno against outstanding lazy request. Emit a request if they are
976 i915_gem_check_olr(struct intel_ring_buffer
*ring
, u32 seqno
)
980 BUG_ON(!mutex_is_locked(&ring
->dev
->struct_mutex
));
983 if (seqno
== ring
->outstanding_lazy_request
)
984 ret
= i915_add_request(ring
, NULL
, NULL
);
990 * __wait_seqno - wait until execution of seqno has finished
991 * @ring: the ring expected to report seqno
993 * @interruptible: do an interruptible wait (normally yes)
994 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
996 * Returns 0 if the seqno was found within the alloted time. Else returns the
997 * errno with remaining time filled in timeout argument.
999 static int __wait_seqno(struct intel_ring_buffer
*ring
, u32 seqno
,
1000 bool interruptible
, struct timespec
*timeout
)
1002 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
1003 struct timespec before
, now
, wait_time
={1,0};
1004 unsigned long timeout_jiffies
;
1006 bool wait_forever
= true;
1009 if (i915_seqno_passed(ring
->get_seqno(ring
, true), seqno
))
1012 trace_i915_gem_request_wait_begin(ring
, seqno
);
1014 if (timeout
!= NULL
) {
1015 wait_time
= *timeout
;
1016 wait_forever
= false;
1019 timeout_jiffies
= timespec_to_jiffies(&wait_time
);
1021 if (WARN_ON(!ring
->irq_get(ring
)))
1024 /* Record current time in case interrupted by signal, or wedged * */
1025 getrawmonotonic(&before
);
1028 (i915_seqno_passed(ring->get_seqno(ring, false), seqno) || \
1029 atomic_read(&dev_priv->mm.wedged))
1032 end
= wait_event_interruptible_timeout(ring
->irq_queue
,
1036 end
= wait_event_timeout(ring
->irq_queue
, EXIT_COND
,
1039 ret
= i915_gem_check_wedge(dev_priv
, interruptible
);
1042 } while (end
== 0 && wait_forever
);
1044 getrawmonotonic(&now
);
1046 ring
->irq_put(ring
);
1047 trace_i915_gem_request_wait_end(ring
, seqno
);
1051 struct timespec sleep_time
= timespec_sub(now
, before
);
1052 *timeout
= timespec_sub(*timeout
, sleep_time
);
1057 case -EAGAIN
: /* Wedged */
1058 case -ERESTARTSYS
: /* Signal */
1060 case 0: /* Timeout */
1062 set_normalized_timespec(timeout
, 0, 0);
1064 default: /* Completed */
1065 WARN_ON(end
< 0); /* We're not aware of other errors */
1071 * Waits for a sequence number to be signaled, and cleans up the
1072 * request and object lists appropriately for that event.
1075 i915_wait_seqno(struct intel_ring_buffer
*ring
, uint32_t seqno
)
1077 struct drm_device
*dev
= ring
->dev
;
1078 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1079 bool interruptible
= dev_priv
->mm
.interruptible
;
1082 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
1085 ret
= i915_gem_check_wedge(dev_priv
, interruptible
);
1089 ret
= i915_gem_check_olr(ring
, seqno
);
1093 return __wait_seqno(ring
, seqno
, interruptible
, NULL
);
1097 * Ensures that all rendering to the object has completed and the object is
1098 * safe to unbind from the GTT or access from the CPU.
1100 static __must_check
int
1101 i915_gem_object_wait_rendering(struct drm_i915_gem_object
*obj
,
1104 struct intel_ring_buffer
*ring
= obj
->ring
;
1108 seqno
= readonly
? obj
->last_write_seqno
: obj
->last_read_seqno
;
1112 ret
= i915_wait_seqno(ring
, seqno
);
1116 i915_gem_retire_requests_ring(ring
);
1118 /* Manually manage the write flush as we may have not yet
1119 * retired the buffer.
1121 if (obj
->last_write_seqno
&&
1122 i915_seqno_passed(seqno
, obj
->last_write_seqno
)) {
1123 obj
->last_write_seqno
= 0;
1124 obj
->base
.write_domain
&= ~I915_GEM_GPU_DOMAINS
;
1130 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1131 * as the object state may change during this call.
1133 static __must_check
int
1134 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object
*obj
,
1137 struct drm_device
*dev
= obj
->base
.dev
;
1138 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1139 struct intel_ring_buffer
*ring
= obj
->ring
;
1143 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
1144 BUG_ON(!dev_priv
->mm
.interruptible
);
1146 seqno
= readonly
? obj
->last_write_seqno
: obj
->last_read_seqno
;
1150 ret
= i915_gem_check_wedge(dev_priv
, true);
1154 ret
= i915_gem_check_olr(ring
, seqno
);
1158 mutex_unlock(&dev
->struct_mutex
);
1159 ret
= __wait_seqno(ring
, seqno
, true, NULL
);
1160 mutex_lock(&dev
->struct_mutex
);
1162 i915_gem_retire_requests_ring(ring
);
1164 /* Manually manage the write flush as we may have not yet
1165 * retired the buffer.
1167 if (obj
->last_write_seqno
&&
1168 i915_seqno_passed(seqno
, obj
->last_write_seqno
)) {
1169 obj
->last_write_seqno
= 0;
1170 obj
->base
.write_domain
&= ~I915_GEM_GPU_DOMAINS
;
1177 * Called when user space prepares to use an object with the CPU, either
1178 * through the mmap ioctl's mapping or a GTT mapping.
1181 i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
1182 struct drm_file
*file
)
1184 struct drm_i915_gem_set_domain
*args
= data
;
1185 struct drm_i915_gem_object
*obj
;
1186 uint32_t read_domains
= args
->read_domains
;
1187 uint32_t write_domain
= args
->write_domain
;
1190 /* Only handle setting domains to types used by the CPU. */
1191 if (write_domain
& I915_GEM_GPU_DOMAINS
)
1194 if (read_domains
& I915_GEM_GPU_DOMAINS
)
1197 /* Having something in the write domain implies it's in the read
1198 * domain, and only that read domain. Enforce that in the request.
1200 if (write_domain
!= 0 && read_domains
!= write_domain
)
1203 ret
= i915_mutex_lock_interruptible(dev
);
1207 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1208 if (&obj
->base
== NULL
) {
1213 /* Try to flush the object off the GPU without holding the lock.
1214 * We will repeat the flush holding the lock in the normal manner
1215 * to catch cases where we are gazumped.
1217 ret
= i915_gem_object_wait_rendering__nonblocking(obj
, !write_domain
);
1221 if (read_domains
& I915_GEM_DOMAIN_GTT
) {
1222 ret
= i915_gem_object_set_to_gtt_domain(obj
, write_domain
!= 0);
1224 /* Silently promote "you're not bound, there was nothing to do"
1225 * to success, since the client was just asking us to
1226 * make sure everything was done.
1231 ret
= i915_gem_object_set_to_cpu_domain(obj
, write_domain
!= 0);
1235 drm_gem_object_unreference(&obj
->base
);
1237 mutex_unlock(&dev
->struct_mutex
);
1242 * Called when user space has done writes to this buffer
1245 i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1246 struct drm_file
*file
)
1248 struct drm_i915_gem_sw_finish
*args
= data
;
1249 struct drm_i915_gem_object
*obj
;
1252 ret
= i915_mutex_lock_interruptible(dev
);
1256 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1257 if (&obj
->base
== NULL
) {
1262 /* Pinned buffers may be scanout, so flush the cache */
1264 i915_gem_object_flush_cpu_write_domain(obj
);
1266 drm_gem_object_unreference(&obj
->base
);
1268 mutex_unlock(&dev
->struct_mutex
);
1273 * Maps the contents of an object, returning the address it is mapped
1276 * While the mapping holds a reference on the contents of the object, it doesn't
1277 * imply a ref on the object itself.
1280 i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1281 struct drm_file
*file
)
1283 struct drm_i915_gem_mmap
*args
= data
;
1284 struct drm_gem_object
*obj
;
1287 obj
= drm_gem_object_lookup(dev
, file
, args
->handle
);
1291 /* prime objects have no backing filp to GEM mmap
1295 drm_gem_object_unreference_unlocked(obj
);
1299 addr
= vm_mmap(obj
->filp
, 0, args
->size
,
1300 PROT_READ
| PROT_WRITE
, MAP_SHARED
,
1302 drm_gem_object_unreference_unlocked(obj
);
1303 if (IS_ERR((void *)addr
))
1306 args
->addr_ptr
= (uint64_t) addr
;
1312 * i915_gem_fault - fault a page into the GTT
1313 * vma: VMA in question
1316 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1317 * from userspace. The fault handler takes care of binding the object to
1318 * the GTT (if needed), allocating and programming a fence register (again,
1319 * only if needed based on whether the old reg is still valid or the object
1320 * is tiled) and inserting a new PTE into the faulting process.
1322 * Note that the faulting process may involve evicting existing objects
1323 * from the GTT and/or fence registers to make room. So performance may
1324 * suffer if the GTT working set is large or there are few fence registers
1327 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
)
1329 struct drm_i915_gem_object
*obj
= to_intel_bo(vma
->vm_private_data
);
1330 struct drm_device
*dev
= obj
->base
.dev
;
1331 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1332 pgoff_t page_offset
;
1335 bool write
= !!(vmf
->flags
& FAULT_FLAG_WRITE
);
1337 /* We don't use vmf->pgoff since that has the fake offset */
1338 page_offset
= ((unsigned long)vmf
->virtual_address
- vma
->vm_start
) >>
1341 ret
= i915_mutex_lock_interruptible(dev
);
1345 trace_i915_gem_object_fault(obj
, page_offset
, true, write
);
1347 /* Now bind it into the GTT if needed */
1348 if (!obj
->map_and_fenceable
) {
1349 ret
= i915_gem_object_unbind(obj
);
1353 if (!obj
->gtt_space
) {
1354 ret
= i915_gem_object_bind_to_gtt(obj
, 0, true, false);
1358 ret
= i915_gem_object_set_to_gtt_domain(obj
, write
);
1363 if (!obj
->has_global_gtt_mapping
)
1364 i915_gem_gtt_bind_object(obj
, obj
->cache_level
);
1366 ret
= i915_gem_object_get_fence(obj
);
1370 if (i915_gem_object_is_inactive(obj
))
1371 list_move_tail(&obj
->mm_list
, &dev_priv
->mm
.inactive_list
);
1373 obj
->fault_mappable
= true;
1375 pfn
= ((dev_priv
->mm
.gtt_base_addr
+ obj
->gtt_offset
) >> PAGE_SHIFT
) +
1378 /* Finally, remap it using the new GTT offset */
1379 ret
= vm_insert_pfn(vma
, (unsigned long)vmf
->virtual_address
, pfn
);
1381 mutex_unlock(&dev
->struct_mutex
);
1385 /* If this -EIO is due to a gpu hang, give the reset code a
1386 * chance to clean up the mess. Otherwise return the proper
1388 if (!atomic_read(&dev_priv
->mm
.wedged
))
1389 return VM_FAULT_SIGBUS
;
1391 /* Give the error handler a chance to run and move the
1392 * objects off the GPU active list. Next time we service the
1393 * fault, we should be able to transition the page into the
1394 * GTT without touching the GPU (and so avoid further
1395 * EIO/EGAIN). If the GPU is wedged, then there is no issue
1396 * with coherency, just lost writes.
1404 * EBUSY is ok: this just means that another thread
1405 * already did the job.
1407 return VM_FAULT_NOPAGE
;
1409 return VM_FAULT_OOM
;
1411 return VM_FAULT_SIGBUS
;
1413 WARN_ONCE(ret
, "unhandled error in i915_gem_fault: %i\n", ret
);
1414 return VM_FAULT_SIGBUS
;
1419 * i915_gem_release_mmap - remove physical page mappings
1420 * @obj: obj in question
1422 * Preserve the reservation of the mmapping with the DRM core code, but
1423 * relinquish ownership of the pages back to the system.
1425 * It is vital that we remove the page mapping if we have mapped a tiled
1426 * object through the GTT and then lose the fence register due to
1427 * resource pressure. Similarly if the object has been moved out of the
1428 * aperture, than pages mapped into userspace must be revoked. Removing the
1429 * mapping will then trigger a page fault on the next user access, allowing
1430 * fixup by i915_gem_fault().
1433 i915_gem_release_mmap(struct drm_i915_gem_object
*obj
)
1435 if (!obj
->fault_mappable
)
1438 if (obj
->base
.dev
->dev_mapping
)
1439 unmap_mapping_range(obj
->base
.dev
->dev_mapping
,
1440 (loff_t
)obj
->base
.map_list
.hash
.key
<<PAGE_SHIFT
,
1443 obj
->fault_mappable
= false;
1447 i915_gem_get_gtt_size(struct drm_device
*dev
, uint32_t size
, int tiling_mode
)
1451 if (INTEL_INFO(dev
)->gen
>= 4 ||
1452 tiling_mode
== I915_TILING_NONE
)
1455 /* Previous chips need a power-of-two fence region when tiling */
1456 if (INTEL_INFO(dev
)->gen
== 3)
1457 gtt_size
= 1024*1024;
1459 gtt_size
= 512*1024;
1461 while (gtt_size
< size
)
1468 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1469 * @obj: object to check
1471 * Return the required GTT alignment for an object, taking into account
1472 * potential fence register mapping.
1475 i915_gem_get_gtt_alignment(struct drm_device
*dev
,
1480 * Minimum alignment is 4k (GTT page size), but might be greater
1481 * if a fence register is needed for the object.
1483 if (INTEL_INFO(dev
)->gen
>= 4 ||
1484 tiling_mode
== I915_TILING_NONE
)
1488 * Previous chips need to be aligned to the size of the smallest
1489 * fence register that can contain the object.
1491 return i915_gem_get_gtt_size(dev
, size
, tiling_mode
);
1495 * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an
1498 * @size: size of the object
1499 * @tiling_mode: tiling mode of the object
1501 * Return the required GTT alignment for an object, only taking into account
1502 * unfenced tiled surface requirements.
1505 i915_gem_get_unfenced_gtt_alignment(struct drm_device
*dev
,
1510 * Minimum alignment is 4k (GTT page size) for sane hw.
1512 if (INTEL_INFO(dev
)->gen
>= 4 || IS_G33(dev
) ||
1513 tiling_mode
== I915_TILING_NONE
)
1516 /* Previous hardware however needs to be aligned to a power-of-two
1517 * tile height. The simplest method for determining this is to reuse
1518 * the power-of-tile object size.
1520 return i915_gem_get_gtt_size(dev
, size
, tiling_mode
);
1523 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object
*obj
)
1525 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
1528 if (obj
->base
.map_list
.map
)
1531 ret
= drm_gem_create_mmap_offset(&obj
->base
);
1535 /* Badly fragmented mmap space? The only way we can recover
1536 * space is by destroying unwanted objects. We can't randomly release
1537 * mmap_offsets as userspace expects them to be persistent for the
1538 * lifetime of the objects. The closest we can is to release the
1539 * offsets on purgeable objects by truncating it and marking it purged,
1540 * which prevents userspace from ever using that object again.
1542 i915_gem_purge(dev_priv
, obj
->base
.size
>> PAGE_SHIFT
);
1543 ret
= drm_gem_create_mmap_offset(&obj
->base
);
1547 i915_gem_shrink_all(dev_priv
);
1548 return drm_gem_create_mmap_offset(&obj
->base
);
1551 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object
*obj
)
1553 if (!obj
->base
.map_list
.map
)
1556 drm_gem_free_mmap_offset(&obj
->base
);
1560 i915_gem_mmap_gtt(struct drm_file
*file
,
1561 struct drm_device
*dev
,
1565 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1566 struct drm_i915_gem_object
*obj
;
1569 ret
= i915_mutex_lock_interruptible(dev
);
1573 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, handle
));
1574 if (&obj
->base
== NULL
) {
1579 if (obj
->base
.size
> dev_priv
->mm
.gtt_mappable_end
) {
1584 if (obj
->madv
!= I915_MADV_WILLNEED
) {
1585 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1590 ret
= i915_gem_object_create_mmap_offset(obj
);
1594 *offset
= (u64
)obj
->base
.map_list
.hash
.key
<< PAGE_SHIFT
;
1597 drm_gem_object_unreference(&obj
->base
);
1599 mutex_unlock(&dev
->struct_mutex
);
1604 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1606 * @data: GTT mapping ioctl data
1607 * @file: GEM object info
1609 * Simply returns the fake offset to userspace so it can mmap it.
1610 * The mmap call will end up in drm_gem_mmap(), which will set things
1611 * up so we can get faults in the handler above.
1613 * The fault handler will take care of binding the object into the GTT
1614 * (since it may have been evicted to make room for something), allocating
1615 * a fence register, and mapping the appropriate aperture address into
1619 i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
1620 struct drm_file
*file
)
1622 struct drm_i915_gem_mmap_gtt
*args
= data
;
1624 return i915_gem_mmap_gtt(file
, dev
, args
->handle
, &args
->offset
);
1627 /* Immediately discard the backing storage */
1629 i915_gem_object_truncate(struct drm_i915_gem_object
*obj
)
1631 struct inode
*inode
;
1633 i915_gem_object_free_mmap_offset(obj
);
1635 if (obj
->base
.filp
== NULL
)
1638 /* Our goal here is to return as much of the memory as
1639 * is possible back to the system as we are called from OOM.
1640 * To do this we must instruct the shmfs to drop all of its
1641 * backing pages, *now*.
1643 inode
= obj
->base
.filp
->f_path
.dentry
->d_inode
;
1644 shmem_truncate_range(inode
, 0, (loff_t
)-1);
1646 obj
->madv
= __I915_MADV_PURGED
;
1650 i915_gem_object_is_purgeable(struct drm_i915_gem_object
*obj
)
1652 return obj
->madv
== I915_MADV_DONTNEED
;
1656 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object
*obj
)
1658 int page_count
= obj
->base
.size
/ PAGE_SIZE
;
1659 struct scatterlist
*sg
;
1662 BUG_ON(obj
->madv
== __I915_MADV_PURGED
);
1664 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
1666 /* In the event of a disaster, abandon all caches and
1667 * hope for the best.
1669 WARN_ON(ret
!= -EIO
);
1670 i915_gem_clflush_object(obj
);
1671 obj
->base
.read_domains
= obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
1674 if (i915_gem_object_needs_bit17_swizzle(obj
))
1675 i915_gem_object_save_bit_17_swizzle(obj
);
1677 if (obj
->madv
== I915_MADV_DONTNEED
)
1680 for_each_sg(obj
->pages
->sgl
, sg
, page_count
, i
) {
1681 struct page
*page
= sg_page(sg
);
1684 set_page_dirty(page
);
1686 if (obj
->madv
== I915_MADV_WILLNEED
)
1687 mark_page_accessed(page
);
1689 page_cache_release(page
);
1693 sg_free_table(obj
->pages
);
1698 i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
)
1700 const struct drm_i915_gem_object_ops
*ops
= obj
->ops
;
1702 if (obj
->pages
== NULL
)
1705 BUG_ON(obj
->gtt_space
);
1707 if (obj
->pages_pin_count
)
1710 ops
->put_pages(obj
);
1713 list_del(&obj
->gtt_list
);
1714 if (i915_gem_object_is_purgeable(obj
))
1715 i915_gem_object_truncate(obj
);
1721 i915_gem_purge(struct drm_i915_private
*dev_priv
, long target
)
1723 struct drm_i915_gem_object
*obj
, *next
;
1726 list_for_each_entry_safe(obj
, next
,
1727 &dev_priv
->mm
.unbound_list
,
1729 if (i915_gem_object_is_purgeable(obj
) &&
1730 i915_gem_object_put_pages(obj
) == 0) {
1731 count
+= obj
->base
.size
>> PAGE_SHIFT
;
1732 if (count
>= target
)
1737 list_for_each_entry_safe(obj
, next
,
1738 &dev_priv
->mm
.inactive_list
,
1740 if (i915_gem_object_is_purgeable(obj
) &&
1741 i915_gem_object_unbind(obj
) == 0 &&
1742 i915_gem_object_put_pages(obj
) == 0) {
1743 count
+= obj
->base
.size
>> PAGE_SHIFT
;
1744 if (count
>= target
)
1753 i915_gem_shrink_all(struct drm_i915_private
*dev_priv
)
1755 struct drm_i915_gem_object
*obj
, *next
;
1757 i915_gem_evict_everything(dev_priv
->dev
);
1759 list_for_each_entry_safe(obj
, next
, &dev_priv
->mm
.unbound_list
, gtt_list
)
1760 i915_gem_object_put_pages(obj
);
1764 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object
*obj
)
1766 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
1768 struct address_space
*mapping
;
1769 struct sg_table
*st
;
1770 struct scatterlist
*sg
;
1774 /* Assert that the object is not currently in any GPU domain. As it
1775 * wasn't in the GTT, there shouldn't be any way it could have been in
1778 BUG_ON(obj
->base
.read_domains
& I915_GEM_GPU_DOMAINS
);
1779 BUG_ON(obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
);
1781 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
1785 page_count
= obj
->base
.size
/ PAGE_SIZE
;
1786 if (sg_alloc_table(st
, page_count
, GFP_KERNEL
)) {
1792 /* Get the list of pages out of our struct file. They'll be pinned
1793 * at this point until we release them.
1795 * Fail silently without starting the shrinker
1797 mapping
= obj
->base
.filp
->f_path
.dentry
->d_inode
->i_mapping
;
1798 gfp
= mapping_gfp_mask(mapping
);
1799 gfp
|= __GFP_NORETRY
| __GFP_NOWARN
;
1800 gfp
&= ~(__GFP_IO
| __GFP_WAIT
);
1801 for_each_sg(st
->sgl
, sg
, page_count
, i
) {
1802 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
1804 i915_gem_purge(dev_priv
, page_count
);
1805 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
1808 /* We've tried hard to allocate the memory by reaping
1809 * our own buffer, now let the real VM do its job and
1810 * go down in flames if truly OOM.
1812 gfp
&= ~(__GFP_NORETRY
| __GFP_NOWARN
);
1813 gfp
|= __GFP_IO
| __GFP_WAIT
;
1815 i915_gem_shrink_all(dev_priv
);
1816 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
1820 gfp
|= __GFP_NORETRY
| __GFP_NOWARN
;
1821 gfp
&= ~(__GFP_IO
| __GFP_WAIT
);
1824 sg_set_page(sg
, page
, PAGE_SIZE
, 0);
1829 if (i915_gem_object_needs_bit17_swizzle(obj
))
1830 i915_gem_object_do_bit_17_swizzle(obj
);
1835 for_each_sg(st
->sgl
, sg
, i
, page_count
)
1836 page_cache_release(sg_page(sg
));
1839 return PTR_ERR(page
);
1842 /* Ensure that the associated pages are gathered from the backing storage
1843 * and pinned into our object. i915_gem_object_get_pages() may be called
1844 * multiple times before they are released by a single call to
1845 * i915_gem_object_put_pages() - once the pages are no longer referenced
1846 * either as a result of memory pressure (reaping pages under the shrinker)
1847 * or as the object is itself released.
1850 i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
)
1852 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
1853 const struct drm_i915_gem_object_ops
*ops
= obj
->ops
;
1859 BUG_ON(obj
->pages_pin_count
);
1861 ret
= ops
->get_pages(obj
);
1865 list_add_tail(&obj
->gtt_list
, &dev_priv
->mm
.unbound_list
);
1870 i915_gem_object_move_to_active(struct drm_i915_gem_object
*obj
,
1871 struct intel_ring_buffer
*ring
,
1874 struct drm_device
*dev
= obj
->base
.dev
;
1875 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1877 BUG_ON(ring
== NULL
);
1880 /* Add a reference if we're newly entering the active list. */
1882 drm_gem_object_reference(&obj
->base
);
1886 /* Move from whatever list we were on to the tail of execution. */
1887 list_move_tail(&obj
->mm_list
, &dev_priv
->mm
.active_list
);
1888 list_move_tail(&obj
->ring_list
, &ring
->active_list
);
1890 obj
->last_read_seqno
= seqno
;
1892 if (obj
->fenced_gpu_access
) {
1893 obj
->last_fenced_seqno
= seqno
;
1895 /* Bump MRU to take account of the delayed flush */
1896 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
1897 struct drm_i915_fence_reg
*reg
;
1899 reg
= &dev_priv
->fence_regs
[obj
->fence_reg
];
1900 list_move_tail(®
->lru_list
,
1901 &dev_priv
->mm
.fence_list
);
1907 i915_gem_object_move_to_inactive(struct drm_i915_gem_object
*obj
)
1909 struct drm_device
*dev
= obj
->base
.dev
;
1910 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1912 BUG_ON(obj
->base
.write_domain
& ~I915_GEM_GPU_DOMAINS
);
1913 BUG_ON(!obj
->active
);
1915 if (obj
->pin_count
) /* are we a framebuffer? */
1916 intel_mark_fb_idle(obj
);
1918 list_move_tail(&obj
->mm_list
, &dev_priv
->mm
.inactive_list
);
1920 list_del_init(&obj
->ring_list
);
1923 obj
->last_read_seqno
= 0;
1924 obj
->last_write_seqno
= 0;
1925 obj
->base
.write_domain
= 0;
1927 obj
->last_fenced_seqno
= 0;
1928 obj
->fenced_gpu_access
= false;
1931 drm_gem_object_unreference(&obj
->base
);
1933 WARN_ON(i915_verify_lists(dev
));
1937 i915_gem_get_seqno(struct drm_device
*dev
)
1939 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1940 u32 seqno
= dev_priv
->next_seqno
;
1942 /* reserve 0 for non-seqno */
1943 if (++dev_priv
->next_seqno
== 0)
1944 dev_priv
->next_seqno
= 1;
1950 i915_gem_next_request_seqno(struct intel_ring_buffer
*ring
)
1952 if (ring
->outstanding_lazy_request
== 0)
1953 ring
->outstanding_lazy_request
= i915_gem_get_seqno(ring
->dev
);
1955 return ring
->outstanding_lazy_request
;
1959 i915_add_request(struct intel_ring_buffer
*ring
,
1960 struct drm_file
*file
,
1963 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
1964 struct drm_i915_gem_request
*request
;
1965 u32 request_ring_position
;
1971 * Emit any outstanding flushes - execbuf can fail to emit the flush
1972 * after having emitted the batchbuffer command. Hence we need to fix
1973 * things up similar to emitting the lazy request. The difference here
1974 * is that the flush _must_ happen before the next request, no matter
1977 ret
= intel_ring_flush_all_caches(ring
);
1981 request
= kmalloc(sizeof(*request
), GFP_KERNEL
);
1982 if (request
== NULL
)
1985 seqno
= i915_gem_next_request_seqno(ring
);
1987 /* Record the position of the start of the request so that
1988 * should we detect the updated seqno part-way through the
1989 * GPU processing the request, we never over-estimate the
1990 * position of the head.
1992 request_ring_position
= intel_ring_get_tail(ring
);
1994 ret
= ring
->add_request(ring
, &seqno
);
2000 trace_i915_gem_request_add(ring
, seqno
);
2002 request
->seqno
= seqno
;
2003 request
->ring
= ring
;
2004 request
->tail
= request_ring_position
;
2005 request
->emitted_jiffies
= jiffies
;
2006 was_empty
= list_empty(&ring
->request_list
);
2007 list_add_tail(&request
->list
, &ring
->request_list
);
2008 request
->file_priv
= NULL
;
2011 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
2013 spin_lock(&file_priv
->mm
.lock
);
2014 request
->file_priv
= file_priv
;
2015 list_add_tail(&request
->client_list
,
2016 &file_priv
->mm
.request_list
);
2017 spin_unlock(&file_priv
->mm
.lock
);
2020 ring
->outstanding_lazy_request
= 0;
2022 if (!dev_priv
->mm
.suspended
) {
2023 if (i915_enable_hangcheck
) {
2024 mod_timer(&dev_priv
->hangcheck_timer
,
2026 msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD
));
2029 queue_delayed_work(dev_priv
->wq
,
2030 &dev_priv
->mm
.retire_work
, HZ
);
2031 intel_mark_busy(dev_priv
->dev
);
2041 i915_gem_request_remove_from_client(struct drm_i915_gem_request
*request
)
2043 struct drm_i915_file_private
*file_priv
= request
->file_priv
;
2048 spin_lock(&file_priv
->mm
.lock
);
2049 if (request
->file_priv
) {
2050 list_del(&request
->client_list
);
2051 request
->file_priv
= NULL
;
2053 spin_unlock(&file_priv
->mm
.lock
);
2056 static void i915_gem_reset_ring_lists(struct drm_i915_private
*dev_priv
,
2057 struct intel_ring_buffer
*ring
)
2059 while (!list_empty(&ring
->request_list
)) {
2060 struct drm_i915_gem_request
*request
;
2062 request
= list_first_entry(&ring
->request_list
,
2063 struct drm_i915_gem_request
,
2066 list_del(&request
->list
);
2067 i915_gem_request_remove_from_client(request
);
2071 while (!list_empty(&ring
->active_list
)) {
2072 struct drm_i915_gem_object
*obj
;
2074 obj
= list_first_entry(&ring
->active_list
,
2075 struct drm_i915_gem_object
,
2078 i915_gem_object_move_to_inactive(obj
);
2082 static void i915_gem_reset_fences(struct drm_device
*dev
)
2084 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2087 for (i
= 0; i
< dev_priv
->num_fence_regs
; i
++) {
2088 struct drm_i915_fence_reg
*reg
= &dev_priv
->fence_regs
[i
];
2090 i915_gem_write_fence(dev
, i
, NULL
);
2093 i915_gem_object_fence_lost(reg
->obj
);
2097 INIT_LIST_HEAD(®
->lru_list
);
2100 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
2103 void i915_gem_reset(struct drm_device
*dev
)
2105 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2106 struct drm_i915_gem_object
*obj
;
2107 struct intel_ring_buffer
*ring
;
2110 for_each_ring(ring
, dev_priv
, i
)
2111 i915_gem_reset_ring_lists(dev_priv
, ring
);
2113 /* Move everything out of the GPU domains to ensure we do any
2114 * necessary invalidation upon reuse.
2116 list_for_each_entry(obj
,
2117 &dev_priv
->mm
.inactive_list
,
2120 obj
->base
.read_domains
&= ~I915_GEM_GPU_DOMAINS
;
2123 /* The fence registers are invalidated so clear them out */
2124 i915_gem_reset_fences(dev
);
2128 * This function clears the request list as sequence numbers are passed.
2131 i915_gem_retire_requests_ring(struct intel_ring_buffer
*ring
)
2136 if (list_empty(&ring
->request_list
))
2139 WARN_ON(i915_verify_lists(ring
->dev
));
2141 seqno
= ring
->get_seqno(ring
, true);
2143 for (i
= 0; i
< ARRAY_SIZE(ring
->sync_seqno
); i
++)
2144 if (seqno
>= ring
->sync_seqno
[i
])
2145 ring
->sync_seqno
[i
] = 0;
2147 while (!list_empty(&ring
->request_list
)) {
2148 struct drm_i915_gem_request
*request
;
2150 request
= list_first_entry(&ring
->request_list
,
2151 struct drm_i915_gem_request
,
2154 if (!i915_seqno_passed(seqno
, request
->seqno
))
2157 trace_i915_gem_request_retire(ring
, request
->seqno
);
2158 /* We know the GPU must have read the request to have
2159 * sent us the seqno + interrupt, so use the position
2160 * of tail of the request to update the last known position
2163 ring
->last_retired_head
= request
->tail
;
2165 list_del(&request
->list
);
2166 i915_gem_request_remove_from_client(request
);
2170 /* Move any buffers on the active list that are no longer referenced
2171 * by the ringbuffer to the flushing/inactive lists as appropriate.
2173 while (!list_empty(&ring
->active_list
)) {
2174 struct drm_i915_gem_object
*obj
;
2176 obj
= list_first_entry(&ring
->active_list
,
2177 struct drm_i915_gem_object
,
2180 if (!i915_seqno_passed(seqno
, obj
->last_read_seqno
))
2183 i915_gem_object_move_to_inactive(obj
);
2186 if (unlikely(ring
->trace_irq_seqno
&&
2187 i915_seqno_passed(seqno
, ring
->trace_irq_seqno
))) {
2188 ring
->irq_put(ring
);
2189 ring
->trace_irq_seqno
= 0;
2192 WARN_ON(i915_verify_lists(ring
->dev
));
2196 i915_gem_retire_requests(struct drm_device
*dev
)
2198 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2199 struct intel_ring_buffer
*ring
;
2202 for_each_ring(ring
, dev_priv
, i
)
2203 i915_gem_retire_requests_ring(ring
);
2207 i915_gem_retire_work_handler(struct work_struct
*work
)
2209 drm_i915_private_t
*dev_priv
;
2210 struct drm_device
*dev
;
2211 struct intel_ring_buffer
*ring
;
2215 dev_priv
= container_of(work
, drm_i915_private_t
,
2216 mm
.retire_work
.work
);
2217 dev
= dev_priv
->dev
;
2219 /* Come back later if the device is busy... */
2220 if (!mutex_trylock(&dev
->struct_mutex
)) {
2221 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, HZ
);
2225 i915_gem_retire_requests(dev
);
2227 /* Send a periodic flush down the ring so we don't hold onto GEM
2228 * objects indefinitely.
2231 for_each_ring(ring
, dev_priv
, i
) {
2232 if (ring
->gpu_caches_dirty
)
2233 i915_add_request(ring
, NULL
, NULL
);
2235 idle
&= list_empty(&ring
->request_list
);
2238 if (!dev_priv
->mm
.suspended
&& !idle
)
2239 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, HZ
);
2241 intel_mark_idle(dev
);
2243 mutex_unlock(&dev
->struct_mutex
);
2247 * Ensures that an object will eventually get non-busy by flushing any required
2248 * write domains, emitting any outstanding lazy request and retiring and
2249 * completed requests.
2252 i915_gem_object_flush_active(struct drm_i915_gem_object
*obj
)
2257 ret
= i915_gem_check_olr(obj
->ring
, obj
->last_read_seqno
);
2261 i915_gem_retire_requests_ring(obj
->ring
);
2268 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2269 * @DRM_IOCTL_ARGS: standard ioctl arguments
2271 * Returns 0 if successful, else an error is returned with the remaining time in
2272 * the timeout parameter.
2273 * -ETIME: object is still busy after timeout
2274 * -ERESTARTSYS: signal interrupted the wait
2275 * -ENONENT: object doesn't exist
2276 * Also possible, but rare:
2277 * -EAGAIN: GPU wedged
2279 * -ENODEV: Internal IRQ fail
2280 * -E?: The add request failed
2282 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2283 * non-zero timeout parameter the wait ioctl will wait for the given number of
2284 * nanoseconds on an object becoming unbusy. Since the wait itself does so
2285 * without holding struct_mutex the object may become re-busied before this
2286 * function completes. A similar but shorter * race condition exists in the busy
2290 i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
, struct drm_file
*file
)
2292 struct drm_i915_gem_wait
*args
= data
;
2293 struct drm_i915_gem_object
*obj
;
2294 struct intel_ring_buffer
*ring
= NULL
;
2295 struct timespec timeout_stack
, *timeout
= NULL
;
2299 if (args
->timeout_ns
>= 0) {
2300 timeout_stack
= ns_to_timespec(args
->timeout_ns
);
2301 timeout
= &timeout_stack
;
2304 ret
= i915_mutex_lock_interruptible(dev
);
2308 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->bo_handle
));
2309 if (&obj
->base
== NULL
) {
2310 mutex_unlock(&dev
->struct_mutex
);
2314 /* Need to make sure the object gets inactive eventually. */
2315 ret
= i915_gem_object_flush_active(obj
);
2320 seqno
= obj
->last_read_seqno
;
2327 /* Do this after OLR check to make sure we make forward progress polling
2328 * on this IOCTL with a 0 timeout (like busy ioctl)
2330 if (!args
->timeout_ns
) {
2335 drm_gem_object_unreference(&obj
->base
);
2336 mutex_unlock(&dev
->struct_mutex
);
2338 ret
= __wait_seqno(ring
, seqno
, true, timeout
);
2340 WARN_ON(!timespec_valid(timeout
));
2341 args
->timeout_ns
= timespec_to_ns(timeout
);
2346 drm_gem_object_unreference(&obj
->base
);
2347 mutex_unlock(&dev
->struct_mutex
);
2352 * i915_gem_object_sync - sync an object to a ring.
2354 * @obj: object which may be in use on another ring.
2355 * @to: ring we wish to use the object on. May be NULL.
2357 * This code is meant to abstract object synchronization with the GPU.
2358 * Calling with NULL implies synchronizing the object with the CPU
2359 * rather than a particular GPU ring.
2361 * Returns 0 if successful, else propagates up the lower layer error.
2364 i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
2365 struct intel_ring_buffer
*to
)
2367 struct intel_ring_buffer
*from
= obj
->ring
;
2371 if (from
== NULL
|| to
== from
)
2374 if (to
== NULL
|| !i915_semaphore_is_enabled(obj
->base
.dev
))
2375 return i915_gem_object_wait_rendering(obj
, false);
2377 idx
= intel_ring_sync_index(from
, to
);
2379 seqno
= obj
->last_read_seqno
;
2380 if (seqno
<= from
->sync_seqno
[idx
])
2383 ret
= i915_gem_check_olr(obj
->ring
, seqno
);
2387 ret
= to
->sync_to(to
, from
, seqno
);
2389 from
->sync_seqno
[idx
] = seqno
;
2394 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object
*obj
)
2396 u32 old_write_domain
, old_read_domains
;
2398 /* Act a barrier for all accesses through the GTT */
2401 /* Force a pagefault for domain tracking on next user access */
2402 i915_gem_release_mmap(obj
);
2404 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
) == 0)
2407 old_read_domains
= obj
->base
.read_domains
;
2408 old_write_domain
= obj
->base
.write_domain
;
2410 obj
->base
.read_domains
&= ~I915_GEM_DOMAIN_GTT
;
2411 obj
->base
.write_domain
&= ~I915_GEM_DOMAIN_GTT
;
2413 trace_i915_gem_object_change_domain(obj
,
2419 * Unbinds an object from the GTT aperture.
2422 i915_gem_object_unbind(struct drm_i915_gem_object
*obj
)
2424 drm_i915_private_t
*dev_priv
= obj
->base
.dev
->dev_private
;
2427 if (obj
->gtt_space
== NULL
)
2433 BUG_ON(obj
->pages
== NULL
);
2435 ret
= i915_gem_object_finish_gpu(obj
);
2438 /* Continue on if we fail due to EIO, the GPU is hung so we
2439 * should be safe and we need to cleanup or else we might
2440 * cause memory corruption through use-after-free.
2443 i915_gem_object_finish_gtt(obj
);
2445 /* release the fence reg _after_ flushing */
2446 ret
= i915_gem_object_put_fence(obj
);
2450 trace_i915_gem_object_unbind(obj
);
2452 if (obj
->has_global_gtt_mapping
)
2453 i915_gem_gtt_unbind_object(obj
);
2454 if (obj
->has_aliasing_ppgtt_mapping
) {
2455 i915_ppgtt_unbind_object(dev_priv
->mm
.aliasing_ppgtt
, obj
);
2456 obj
->has_aliasing_ppgtt_mapping
= 0;
2458 i915_gem_gtt_finish_object(obj
);
2460 list_del(&obj
->mm_list
);
2461 list_move_tail(&obj
->gtt_list
, &dev_priv
->mm
.unbound_list
);
2462 /* Avoid an unnecessary call to unbind on rebind. */
2463 obj
->map_and_fenceable
= true;
2465 drm_mm_put_block(obj
->gtt_space
);
2466 obj
->gtt_space
= NULL
;
2467 obj
->gtt_offset
= 0;
2472 static int i915_ring_idle(struct intel_ring_buffer
*ring
)
2474 if (list_empty(&ring
->active_list
))
2477 return i915_wait_seqno(ring
, i915_gem_next_request_seqno(ring
));
2480 int i915_gpu_idle(struct drm_device
*dev
)
2482 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2483 struct intel_ring_buffer
*ring
;
2486 /* Flush everything onto the inactive list. */
2487 for_each_ring(ring
, dev_priv
, i
) {
2488 ret
= i915_switch_context(ring
, NULL
, DEFAULT_CONTEXT_ID
);
2492 ret
= i915_ring_idle(ring
);
2500 static void sandybridge_write_fence_reg(struct drm_device
*dev
, int reg
,
2501 struct drm_i915_gem_object
*obj
)
2503 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2507 u32 size
= obj
->gtt_space
->size
;
2509 val
= (uint64_t)((obj
->gtt_offset
+ size
- 4096) &
2511 val
|= obj
->gtt_offset
& 0xfffff000;
2512 val
|= (uint64_t)((obj
->stride
/ 128) - 1) <<
2513 SANDYBRIDGE_FENCE_PITCH_SHIFT
;
2515 if (obj
->tiling_mode
== I915_TILING_Y
)
2516 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
2517 val
|= I965_FENCE_REG_VALID
;
2521 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0
+ reg
* 8, val
);
2522 POSTING_READ(FENCE_REG_SANDYBRIDGE_0
+ reg
* 8);
2525 static void i965_write_fence_reg(struct drm_device
*dev
, int reg
,
2526 struct drm_i915_gem_object
*obj
)
2528 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2532 u32 size
= obj
->gtt_space
->size
;
2534 val
= (uint64_t)((obj
->gtt_offset
+ size
- 4096) &
2536 val
|= obj
->gtt_offset
& 0xfffff000;
2537 val
|= ((obj
->stride
/ 128) - 1) << I965_FENCE_PITCH_SHIFT
;
2538 if (obj
->tiling_mode
== I915_TILING_Y
)
2539 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
2540 val
|= I965_FENCE_REG_VALID
;
2544 I915_WRITE64(FENCE_REG_965_0
+ reg
* 8, val
);
2545 POSTING_READ(FENCE_REG_965_0
+ reg
* 8);
2548 static void i915_write_fence_reg(struct drm_device
*dev
, int reg
,
2549 struct drm_i915_gem_object
*obj
)
2551 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2555 u32 size
= obj
->gtt_space
->size
;
2559 WARN((obj
->gtt_offset
& ~I915_FENCE_START_MASK
) ||
2560 (size
& -size
) != size
||
2561 (obj
->gtt_offset
& (size
- 1)),
2562 "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2563 obj
->gtt_offset
, obj
->map_and_fenceable
, size
);
2565 if (obj
->tiling_mode
== I915_TILING_Y
&& HAS_128_BYTE_Y_TILING(dev
))
2570 /* Note: pitch better be a power of two tile widths */
2571 pitch_val
= obj
->stride
/ tile_width
;
2572 pitch_val
= ffs(pitch_val
) - 1;
2574 val
= obj
->gtt_offset
;
2575 if (obj
->tiling_mode
== I915_TILING_Y
)
2576 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2577 val
|= I915_FENCE_SIZE_BITS(size
);
2578 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2579 val
|= I830_FENCE_REG_VALID
;
2584 reg
= FENCE_REG_830_0
+ reg
* 4;
2586 reg
= FENCE_REG_945_8
+ (reg
- 8) * 4;
2588 I915_WRITE(reg
, val
);
2592 static void i830_write_fence_reg(struct drm_device
*dev
, int reg
,
2593 struct drm_i915_gem_object
*obj
)
2595 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2599 u32 size
= obj
->gtt_space
->size
;
2602 WARN((obj
->gtt_offset
& ~I830_FENCE_START_MASK
) ||
2603 (size
& -size
) != size
||
2604 (obj
->gtt_offset
& (size
- 1)),
2605 "object 0x%08x not 512K or pot-size 0x%08x aligned\n",
2606 obj
->gtt_offset
, size
);
2608 pitch_val
= obj
->stride
/ 128;
2609 pitch_val
= ffs(pitch_val
) - 1;
2611 val
= obj
->gtt_offset
;
2612 if (obj
->tiling_mode
== I915_TILING_Y
)
2613 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2614 val
|= I830_FENCE_SIZE_BITS(size
);
2615 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2616 val
|= I830_FENCE_REG_VALID
;
2620 I915_WRITE(FENCE_REG_830_0
+ reg
* 4, val
);
2621 POSTING_READ(FENCE_REG_830_0
+ reg
* 4);
2624 static void i915_gem_write_fence(struct drm_device
*dev
, int reg
,
2625 struct drm_i915_gem_object
*obj
)
2627 switch (INTEL_INFO(dev
)->gen
) {
2629 case 6: sandybridge_write_fence_reg(dev
, reg
, obj
); break;
2631 case 4: i965_write_fence_reg(dev
, reg
, obj
); break;
2632 case 3: i915_write_fence_reg(dev
, reg
, obj
); break;
2633 case 2: i830_write_fence_reg(dev
, reg
, obj
); break;
2638 static inline int fence_number(struct drm_i915_private
*dev_priv
,
2639 struct drm_i915_fence_reg
*fence
)
2641 return fence
- dev_priv
->fence_regs
;
2644 static void i915_gem_object_update_fence(struct drm_i915_gem_object
*obj
,
2645 struct drm_i915_fence_reg
*fence
,
2648 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2649 int reg
= fence_number(dev_priv
, fence
);
2651 i915_gem_write_fence(obj
->base
.dev
, reg
, enable
? obj
: NULL
);
2654 obj
->fence_reg
= reg
;
2656 list_move_tail(&fence
->lru_list
, &dev_priv
->mm
.fence_list
);
2658 obj
->fence_reg
= I915_FENCE_REG_NONE
;
2660 list_del_init(&fence
->lru_list
);
2665 i915_gem_object_flush_fence(struct drm_i915_gem_object
*obj
)
2667 if (obj
->last_fenced_seqno
) {
2668 int ret
= i915_wait_seqno(obj
->ring
, obj
->last_fenced_seqno
);
2672 obj
->last_fenced_seqno
= 0;
2675 /* Ensure that all CPU reads are completed before installing a fence
2676 * and all writes before removing the fence.
2678 if (obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
)
2681 obj
->fenced_gpu_access
= false;
2686 i915_gem_object_put_fence(struct drm_i915_gem_object
*obj
)
2688 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2691 ret
= i915_gem_object_flush_fence(obj
);
2695 if (obj
->fence_reg
== I915_FENCE_REG_NONE
)
2698 i915_gem_object_update_fence(obj
,
2699 &dev_priv
->fence_regs
[obj
->fence_reg
],
2701 i915_gem_object_fence_lost(obj
);
2706 static struct drm_i915_fence_reg
*
2707 i915_find_fence_reg(struct drm_device
*dev
)
2709 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2710 struct drm_i915_fence_reg
*reg
, *avail
;
2713 /* First try to find a free reg */
2715 for (i
= dev_priv
->fence_reg_start
; i
< dev_priv
->num_fence_regs
; i
++) {
2716 reg
= &dev_priv
->fence_regs
[i
];
2720 if (!reg
->pin_count
)
2727 /* None available, try to steal one or wait for a user to finish */
2728 list_for_each_entry(reg
, &dev_priv
->mm
.fence_list
, lru_list
) {
2739 * i915_gem_object_get_fence - set up fencing for an object
2740 * @obj: object to map through a fence reg
2742 * When mapping objects through the GTT, userspace wants to be able to write
2743 * to them without having to worry about swizzling if the object is tiled.
2744 * This function walks the fence regs looking for a free one for @obj,
2745 * stealing one if it can't find any.
2747 * It then sets up the reg based on the object's properties: address, pitch
2748 * and tiling format.
2750 * For an untiled surface, this removes any existing fence.
2753 i915_gem_object_get_fence(struct drm_i915_gem_object
*obj
)
2755 struct drm_device
*dev
= obj
->base
.dev
;
2756 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2757 bool enable
= obj
->tiling_mode
!= I915_TILING_NONE
;
2758 struct drm_i915_fence_reg
*reg
;
2761 /* Have we updated the tiling parameters upon the object and so
2762 * will need to serialise the write to the associated fence register?
2764 if (obj
->fence_dirty
) {
2765 ret
= i915_gem_object_flush_fence(obj
);
2770 /* Just update our place in the LRU if our fence is getting reused. */
2771 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
2772 reg
= &dev_priv
->fence_regs
[obj
->fence_reg
];
2773 if (!obj
->fence_dirty
) {
2774 list_move_tail(®
->lru_list
,
2775 &dev_priv
->mm
.fence_list
);
2778 } else if (enable
) {
2779 reg
= i915_find_fence_reg(dev
);
2784 struct drm_i915_gem_object
*old
= reg
->obj
;
2786 ret
= i915_gem_object_flush_fence(old
);
2790 i915_gem_object_fence_lost(old
);
2795 i915_gem_object_update_fence(obj
, reg
, enable
);
2796 obj
->fence_dirty
= false;
2801 static bool i915_gem_valid_gtt_space(struct drm_device
*dev
,
2802 struct drm_mm_node
*gtt_space
,
2803 unsigned long cache_level
)
2805 struct drm_mm_node
*other
;
2807 /* On non-LLC machines we have to be careful when putting differing
2808 * types of snoopable memory together to avoid the prefetcher
2809 * crossing memory domains and dieing.
2814 if (gtt_space
== NULL
)
2817 if (list_empty(>t_space
->node_list
))
2820 other
= list_entry(gtt_space
->node_list
.prev
, struct drm_mm_node
, node_list
);
2821 if (other
->allocated
&& !other
->hole_follows
&& other
->color
!= cache_level
)
2824 other
= list_entry(gtt_space
->node_list
.next
, struct drm_mm_node
, node_list
);
2825 if (other
->allocated
&& !gtt_space
->hole_follows
&& other
->color
!= cache_level
)
2831 static void i915_gem_verify_gtt(struct drm_device
*dev
)
2834 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2835 struct drm_i915_gem_object
*obj
;
2838 list_for_each_entry(obj
, &dev_priv
->mm
.gtt_list
, gtt_list
) {
2839 if (obj
->gtt_space
== NULL
) {
2840 printk(KERN_ERR
"object found on GTT list with no space reserved\n");
2845 if (obj
->cache_level
!= obj
->gtt_space
->color
) {
2846 printk(KERN_ERR
"object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n",
2847 obj
->gtt_space
->start
,
2848 obj
->gtt_space
->start
+ obj
->gtt_space
->size
,
2850 obj
->gtt_space
->color
);
2855 if (!i915_gem_valid_gtt_space(dev
,
2857 obj
->cache_level
)) {
2858 printk(KERN_ERR
"invalid GTT space found at [%08lx, %08lx] - color=%x\n",
2859 obj
->gtt_space
->start
,
2860 obj
->gtt_space
->start
+ obj
->gtt_space
->size
,
2872 * Finds free space in the GTT aperture and binds the object there.
2875 i915_gem_object_bind_to_gtt(struct drm_i915_gem_object
*obj
,
2877 bool map_and_fenceable
,
2880 struct drm_device
*dev
= obj
->base
.dev
;
2881 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2882 struct drm_mm_node
*free_space
;
2883 u32 size
, fence_size
, fence_alignment
, unfenced_alignment
;
2884 bool mappable
, fenceable
;
2887 if (obj
->madv
!= I915_MADV_WILLNEED
) {
2888 DRM_ERROR("Attempting to bind a purgeable object\n");
2892 fence_size
= i915_gem_get_gtt_size(dev
,
2895 fence_alignment
= i915_gem_get_gtt_alignment(dev
,
2898 unfenced_alignment
=
2899 i915_gem_get_unfenced_gtt_alignment(dev
,
2904 alignment
= map_and_fenceable
? fence_alignment
:
2906 if (map_and_fenceable
&& alignment
& (fence_alignment
- 1)) {
2907 DRM_ERROR("Invalid object alignment requested %u\n", alignment
);
2911 size
= map_and_fenceable
? fence_size
: obj
->base
.size
;
2913 /* If the object is bigger than the entire aperture, reject it early
2914 * before evicting everything in a vain attempt to find space.
2916 if (obj
->base
.size
>
2917 (map_and_fenceable
? dev_priv
->mm
.gtt_mappable_end
: dev_priv
->mm
.gtt_total
)) {
2918 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2922 ret
= i915_gem_object_get_pages(obj
);
2927 if (map_and_fenceable
)
2929 drm_mm_search_free_in_range_color(&dev_priv
->mm
.gtt_space
,
2930 size
, alignment
, obj
->cache_level
,
2931 0, dev_priv
->mm
.gtt_mappable_end
,
2934 free_space
= drm_mm_search_free_color(&dev_priv
->mm
.gtt_space
,
2935 size
, alignment
, obj
->cache_level
,
2938 if (free_space
!= NULL
) {
2939 if (map_and_fenceable
)
2941 drm_mm_get_block_range_generic(free_space
,
2942 size
, alignment
, obj
->cache_level
,
2943 0, dev_priv
->mm
.gtt_mappable_end
,
2947 drm_mm_get_block_generic(free_space
,
2948 size
, alignment
, obj
->cache_level
,
2951 if (obj
->gtt_space
== NULL
) {
2952 ret
= i915_gem_evict_something(dev
, size
, alignment
,
2961 if (WARN_ON(!i915_gem_valid_gtt_space(dev
,
2963 obj
->cache_level
))) {
2964 drm_mm_put_block(obj
->gtt_space
);
2965 obj
->gtt_space
= NULL
;
2970 ret
= i915_gem_gtt_prepare_object(obj
);
2972 drm_mm_put_block(obj
->gtt_space
);
2973 obj
->gtt_space
= NULL
;
2977 if (!dev_priv
->mm
.aliasing_ppgtt
)
2978 i915_gem_gtt_bind_object(obj
, obj
->cache_level
);
2980 list_move_tail(&obj
->gtt_list
, &dev_priv
->mm
.bound_list
);
2981 list_add_tail(&obj
->mm_list
, &dev_priv
->mm
.inactive_list
);
2983 obj
->gtt_offset
= obj
->gtt_space
->start
;
2986 obj
->gtt_space
->size
== fence_size
&&
2987 (obj
->gtt_space
->start
& (fence_alignment
- 1)) == 0;
2990 obj
->gtt_offset
+ obj
->base
.size
<= dev_priv
->mm
.gtt_mappable_end
;
2992 obj
->map_and_fenceable
= mappable
&& fenceable
;
2994 trace_i915_gem_object_bind(obj
, map_and_fenceable
);
2995 i915_gem_verify_gtt(dev
);
3000 i915_gem_clflush_object(struct drm_i915_gem_object
*obj
)
3002 /* If we don't have a page list set up, then we're not pinned
3003 * to GPU, and we can ignore the cache flush because it'll happen
3004 * again at bind time.
3006 if (obj
->pages
== NULL
)
3009 /* If the GPU is snooping the contents of the CPU cache,
3010 * we do not need to manually clear the CPU cache lines. However,
3011 * the caches are only snooped when the render cache is
3012 * flushed/invalidated. As we always have to emit invalidations
3013 * and flushes when moving into and out of the RENDER domain, correct
3014 * snooping behaviour occurs naturally as the result of our domain
3017 if (obj
->cache_level
!= I915_CACHE_NONE
)
3020 trace_i915_gem_object_clflush(obj
);
3022 drm_clflush_sg(obj
->pages
);
3025 /** Flushes the GTT write domain for the object if it's dirty. */
3027 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
)
3029 uint32_t old_write_domain
;
3031 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_GTT
)
3034 /* No actual flushing is required for the GTT write domain. Writes
3035 * to it immediately go to main memory as far as we know, so there's
3036 * no chipset flush. It also doesn't land in render cache.
3038 * However, we do have to enforce the order so that all writes through
3039 * the GTT land before any writes to the device, such as updates to
3044 old_write_domain
= obj
->base
.write_domain
;
3045 obj
->base
.write_domain
= 0;
3047 trace_i915_gem_object_change_domain(obj
,
3048 obj
->base
.read_domains
,
3052 /** Flushes the CPU write domain for the object if it's dirty. */
3054 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
)
3056 uint32_t old_write_domain
;
3058 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
)
3061 i915_gem_clflush_object(obj
);
3062 intel_gtt_chipset_flush();
3063 old_write_domain
= obj
->base
.write_domain
;
3064 obj
->base
.write_domain
= 0;
3066 trace_i915_gem_object_change_domain(obj
,
3067 obj
->base
.read_domains
,
3072 * Moves a single object to the GTT read, and possibly write domain.
3074 * This function returns when the move is complete, including waiting on
3078 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
, bool write
)
3080 drm_i915_private_t
*dev_priv
= obj
->base
.dev
->dev_private
;
3081 uint32_t old_write_domain
, old_read_domains
;
3084 /* Not valid to be called on unbound objects. */
3085 if (obj
->gtt_space
== NULL
)
3088 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_GTT
)
3091 ret
= i915_gem_object_wait_rendering(obj
, !write
);
3095 i915_gem_object_flush_cpu_write_domain(obj
);
3097 old_write_domain
= obj
->base
.write_domain
;
3098 old_read_domains
= obj
->base
.read_domains
;
3100 /* It should now be out of any other write domains, and we can update
3101 * the domain values for our changes.
3103 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
3104 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
3106 obj
->base
.read_domains
= I915_GEM_DOMAIN_GTT
;
3107 obj
->base
.write_domain
= I915_GEM_DOMAIN_GTT
;
3111 trace_i915_gem_object_change_domain(obj
,
3115 /* And bump the LRU for this access */
3116 if (i915_gem_object_is_inactive(obj
))
3117 list_move_tail(&obj
->mm_list
, &dev_priv
->mm
.inactive_list
);
3122 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
3123 enum i915_cache_level cache_level
)
3125 struct drm_device
*dev
= obj
->base
.dev
;
3126 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3129 if (obj
->cache_level
== cache_level
)
3132 if (obj
->pin_count
) {
3133 DRM_DEBUG("can not change the cache level of pinned objects\n");
3137 if (!i915_gem_valid_gtt_space(dev
, obj
->gtt_space
, cache_level
)) {
3138 ret
= i915_gem_object_unbind(obj
);
3143 if (obj
->gtt_space
) {
3144 ret
= i915_gem_object_finish_gpu(obj
);
3148 i915_gem_object_finish_gtt(obj
);
3150 /* Before SandyBridge, you could not use tiling or fence
3151 * registers with snooped memory, so relinquish any fences
3152 * currently pointing to our region in the aperture.
3154 if (INTEL_INFO(dev
)->gen
< 6) {
3155 ret
= i915_gem_object_put_fence(obj
);
3160 if (obj
->has_global_gtt_mapping
)
3161 i915_gem_gtt_bind_object(obj
, cache_level
);
3162 if (obj
->has_aliasing_ppgtt_mapping
)
3163 i915_ppgtt_bind_object(dev_priv
->mm
.aliasing_ppgtt
,
3166 obj
->gtt_space
->color
= cache_level
;
3169 if (cache_level
== I915_CACHE_NONE
) {
3170 u32 old_read_domains
, old_write_domain
;
3172 /* If we're coming from LLC cached, then we haven't
3173 * actually been tracking whether the data is in the
3174 * CPU cache or not, since we only allow one bit set
3175 * in obj->write_domain and have been skipping the clflushes.
3176 * Just set it to the CPU cache for now.
3178 WARN_ON(obj
->base
.write_domain
& ~I915_GEM_DOMAIN_CPU
);
3179 WARN_ON(obj
->base
.read_domains
& ~I915_GEM_DOMAIN_CPU
);
3181 old_read_domains
= obj
->base
.read_domains
;
3182 old_write_domain
= obj
->base
.write_domain
;
3184 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
3185 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
3187 trace_i915_gem_object_change_domain(obj
,
3192 obj
->cache_level
= cache_level
;
3193 i915_gem_verify_gtt(dev
);
3197 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
3198 struct drm_file
*file
)
3200 struct drm_i915_gem_caching
*args
= data
;
3201 struct drm_i915_gem_object
*obj
;
3204 ret
= i915_mutex_lock_interruptible(dev
);
3208 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3209 if (&obj
->base
== NULL
) {
3214 args
->caching
= obj
->cache_level
!= I915_CACHE_NONE
;
3216 drm_gem_object_unreference(&obj
->base
);
3218 mutex_unlock(&dev
->struct_mutex
);
3222 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
3223 struct drm_file
*file
)
3225 struct drm_i915_gem_caching
*args
= data
;
3226 struct drm_i915_gem_object
*obj
;
3227 enum i915_cache_level level
;
3230 switch (args
->caching
) {
3231 case I915_CACHING_NONE
:
3232 level
= I915_CACHE_NONE
;
3234 case I915_CACHING_CACHED
:
3235 level
= I915_CACHE_LLC
;
3241 ret
= i915_mutex_lock_interruptible(dev
);
3245 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3246 if (&obj
->base
== NULL
) {
3251 ret
= i915_gem_object_set_cache_level(obj
, level
);
3253 drm_gem_object_unreference(&obj
->base
);
3255 mutex_unlock(&dev
->struct_mutex
);
3260 * Prepare buffer for display plane (scanout, cursors, etc).
3261 * Can be called from an uninterruptible phase (modesetting) and allows
3262 * any flushes to be pipelined (for pageflips).
3265 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
3267 struct intel_ring_buffer
*pipelined
)
3269 u32 old_read_domains
, old_write_domain
;
3272 if (pipelined
!= obj
->ring
) {
3273 ret
= i915_gem_object_sync(obj
, pipelined
);
3278 /* The display engine is not coherent with the LLC cache on gen6. As
3279 * a result, we make sure that the pinning that is about to occur is
3280 * done with uncached PTEs. This is lowest common denominator for all
3283 * However for gen6+, we could do better by using the GFDT bit instead
3284 * of uncaching, which would allow us to flush all the LLC-cached data
3285 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3287 ret
= i915_gem_object_set_cache_level(obj
, I915_CACHE_NONE
);
3291 /* As the user may map the buffer once pinned in the display plane
3292 * (e.g. libkms for the bootup splash), we have to ensure that we
3293 * always use map_and_fenceable for all scanout buffers.
3295 ret
= i915_gem_object_pin(obj
, alignment
, true, false);
3299 i915_gem_object_flush_cpu_write_domain(obj
);
3301 old_write_domain
= obj
->base
.write_domain
;
3302 old_read_domains
= obj
->base
.read_domains
;
3304 /* It should now be out of any other write domains, and we can update
3305 * the domain values for our changes.
3307 obj
->base
.write_domain
= 0;
3308 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
3310 trace_i915_gem_object_change_domain(obj
,
3318 i915_gem_object_finish_gpu(struct drm_i915_gem_object
*obj
)
3322 if ((obj
->base
.read_domains
& I915_GEM_GPU_DOMAINS
) == 0)
3325 ret
= i915_gem_object_wait_rendering(obj
, false);
3329 /* Ensure that we invalidate the GPU's caches and TLBs. */
3330 obj
->base
.read_domains
&= ~I915_GEM_GPU_DOMAINS
;
3335 * Moves a single object to the CPU read, and possibly write domain.
3337 * This function returns when the move is complete, including waiting on
3341 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
)
3343 uint32_t old_write_domain
, old_read_domains
;
3346 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_CPU
)
3349 ret
= i915_gem_object_wait_rendering(obj
, !write
);
3353 i915_gem_object_flush_gtt_write_domain(obj
);
3355 old_write_domain
= obj
->base
.write_domain
;
3356 old_read_domains
= obj
->base
.read_domains
;
3358 /* Flush the CPU cache if it's still invalid. */
3359 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) == 0) {
3360 i915_gem_clflush_object(obj
);
3362 obj
->base
.read_domains
|= I915_GEM_DOMAIN_CPU
;
3365 /* It should now be out of any other write domains, and we can update
3366 * the domain values for our changes.
3368 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
3370 /* If we're writing through the CPU, then the GPU read domains will
3371 * need to be invalidated at next use.
3374 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
3375 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
3378 trace_i915_gem_object_change_domain(obj
,
3385 /* Throttle our rendering by waiting until the ring has completed our requests
3386 * emitted over 20 msec ago.
3388 * Note that if we were to use the current jiffies each time around the loop,
3389 * we wouldn't escape the function with any frames outstanding if the time to
3390 * render a frame was over 20ms.
3392 * This should get us reasonable parallelism between CPU and GPU but also
3393 * relatively low latency when blocking on a particular request to finish.
3396 i915_gem_ring_throttle(struct drm_device
*dev
, struct drm_file
*file
)
3398 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3399 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
3400 unsigned long recent_enough
= jiffies
- msecs_to_jiffies(20);
3401 struct drm_i915_gem_request
*request
;
3402 struct intel_ring_buffer
*ring
= NULL
;
3406 if (atomic_read(&dev_priv
->mm
.wedged
))
3409 spin_lock(&file_priv
->mm
.lock
);
3410 list_for_each_entry(request
, &file_priv
->mm
.request_list
, client_list
) {
3411 if (time_after_eq(request
->emitted_jiffies
, recent_enough
))
3414 ring
= request
->ring
;
3415 seqno
= request
->seqno
;
3417 spin_unlock(&file_priv
->mm
.lock
);
3422 ret
= __wait_seqno(ring
, seqno
, true, NULL
);
3424 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, 0);
3430 i915_gem_object_pin(struct drm_i915_gem_object
*obj
,
3432 bool map_and_fenceable
,
3437 if (WARN_ON(obj
->pin_count
== DRM_I915_GEM_OBJECT_MAX_PIN_COUNT
))
3440 if (obj
->gtt_space
!= NULL
) {
3441 if ((alignment
&& obj
->gtt_offset
& (alignment
- 1)) ||
3442 (map_and_fenceable
&& !obj
->map_and_fenceable
)) {
3443 WARN(obj
->pin_count
,
3444 "bo is already pinned with incorrect alignment:"
3445 " offset=%x, req.alignment=%x, req.map_and_fenceable=%d,"
3446 " obj->map_and_fenceable=%d\n",
3447 obj
->gtt_offset
, alignment
,
3449 obj
->map_and_fenceable
);
3450 ret
= i915_gem_object_unbind(obj
);
3456 if (obj
->gtt_space
== NULL
) {
3457 ret
= i915_gem_object_bind_to_gtt(obj
, alignment
,
3464 if (!obj
->has_global_gtt_mapping
&& map_and_fenceable
)
3465 i915_gem_gtt_bind_object(obj
, obj
->cache_level
);
3468 obj
->pin_mappable
|= map_and_fenceable
;
3474 i915_gem_object_unpin(struct drm_i915_gem_object
*obj
)
3476 BUG_ON(obj
->pin_count
== 0);
3477 BUG_ON(obj
->gtt_space
== NULL
);
3479 if (--obj
->pin_count
== 0)
3480 obj
->pin_mappable
= false;
3484 i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
3485 struct drm_file
*file
)
3487 struct drm_i915_gem_pin
*args
= data
;
3488 struct drm_i915_gem_object
*obj
;
3491 ret
= i915_mutex_lock_interruptible(dev
);
3495 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3496 if (&obj
->base
== NULL
) {
3501 if (obj
->madv
!= I915_MADV_WILLNEED
) {
3502 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3507 if (obj
->pin_filp
!= NULL
&& obj
->pin_filp
!= file
) {
3508 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3514 obj
->user_pin_count
++;
3515 obj
->pin_filp
= file
;
3516 if (obj
->user_pin_count
== 1) {
3517 ret
= i915_gem_object_pin(obj
, args
->alignment
, true, false);
3522 /* XXX - flush the CPU caches for pinned objects
3523 * as the X server doesn't manage domains yet
3525 i915_gem_object_flush_cpu_write_domain(obj
);
3526 args
->offset
= obj
->gtt_offset
;
3528 drm_gem_object_unreference(&obj
->base
);
3530 mutex_unlock(&dev
->struct_mutex
);
3535 i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
3536 struct drm_file
*file
)
3538 struct drm_i915_gem_pin
*args
= data
;
3539 struct drm_i915_gem_object
*obj
;
3542 ret
= i915_mutex_lock_interruptible(dev
);
3546 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3547 if (&obj
->base
== NULL
) {
3552 if (obj
->pin_filp
!= file
) {
3553 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3558 obj
->user_pin_count
--;
3559 if (obj
->user_pin_count
== 0) {
3560 obj
->pin_filp
= NULL
;
3561 i915_gem_object_unpin(obj
);
3565 drm_gem_object_unreference(&obj
->base
);
3567 mutex_unlock(&dev
->struct_mutex
);
3572 i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
3573 struct drm_file
*file
)
3575 struct drm_i915_gem_busy
*args
= data
;
3576 struct drm_i915_gem_object
*obj
;
3579 ret
= i915_mutex_lock_interruptible(dev
);
3583 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3584 if (&obj
->base
== NULL
) {
3589 /* Count all active objects as busy, even if they are currently not used
3590 * by the gpu. Users of this interface expect objects to eventually
3591 * become non-busy without any further actions, therefore emit any
3592 * necessary flushes here.
3594 ret
= i915_gem_object_flush_active(obj
);
3596 args
->busy
= obj
->active
;
3598 BUILD_BUG_ON(I915_NUM_RINGS
> 16);
3599 args
->busy
|= intel_ring_flag(obj
->ring
) << 16;
3602 drm_gem_object_unreference(&obj
->base
);
3604 mutex_unlock(&dev
->struct_mutex
);
3609 i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
3610 struct drm_file
*file_priv
)
3612 return i915_gem_ring_throttle(dev
, file_priv
);
3616 i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
3617 struct drm_file
*file_priv
)
3619 struct drm_i915_gem_madvise
*args
= data
;
3620 struct drm_i915_gem_object
*obj
;
3623 switch (args
->madv
) {
3624 case I915_MADV_DONTNEED
:
3625 case I915_MADV_WILLNEED
:
3631 ret
= i915_mutex_lock_interruptible(dev
);
3635 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file_priv
, args
->handle
));
3636 if (&obj
->base
== NULL
) {
3641 if (obj
->pin_count
) {
3646 if (obj
->madv
!= __I915_MADV_PURGED
)
3647 obj
->madv
= args
->madv
;
3649 /* if the object is no longer attached, discard its backing storage */
3650 if (i915_gem_object_is_purgeable(obj
) && obj
->pages
== NULL
)
3651 i915_gem_object_truncate(obj
);
3653 args
->retained
= obj
->madv
!= __I915_MADV_PURGED
;
3656 drm_gem_object_unreference(&obj
->base
);
3658 mutex_unlock(&dev
->struct_mutex
);
3662 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
3663 const struct drm_i915_gem_object_ops
*ops
)
3665 INIT_LIST_HEAD(&obj
->mm_list
);
3666 INIT_LIST_HEAD(&obj
->gtt_list
);
3667 INIT_LIST_HEAD(&obj
->ring_list
);
3668 INIT_LIST_HEAD(&obj
->exec_list
);
3672 obj
->fence_reg
= I915_FENCE_REG_NONE
;
3673 obj
->madv
= I915_MADV_WILLNEED
;
3674 /* Avoid an unnecessary call to unbind on the first bind. */
3675 obj
->map_and_fenceable
= true;
3677 i915_gem_info_add_obj(obj
->base
.dev
->dev_private
, obj
->base
.size
);
3680 static const struct drm_i915_gem_object_ops i915_gem_object_ops
= {
3681 .get_pages
= i915_gem_object_get_pages_gtt
,
3682 .put_pages
= i915_gem_object_put_pages_gtt
,
3685 struct drm_i915_gem_object
*i915_gem_alloc_object(struct drm_device
*dev
,
3688 struct drm_i915_gem_object
*obj
;
3689 struct address_space
*mapping
;
3692 obj
= kzalloc(sizeof(*obj
), GFP_KERNEL
);
3696 if (drm_gem_object_init(dev
, &obj
->base
, size
) != 0) {
3701 mask
= GFP_HIGHUSER
| __GFP_RECLAIMABLE
;
3702 if (IS_CRESTLINE(dev
) || IS_BROADWATER(dev
)) {
3703 /* 965gm cannot relocate objects above 4GiB. */
3704 mask
&= ~__GFP_HIGHMEM
;
3705 mask
|= __GFP_DMA32
;
3708 mapping
= obj
->base
.filp
->f_path
.dentry
->d_inode
->i_mapping
;
3709 mapping_set_gfp_mask(mapping
, mask
);
3711 i915_gem_object_init(obj
, &i915_gem_object_ops
);
3713 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
3714 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
3717 /* On some devices, we can have the GPU use the LLC (the CPU
3718 * cache) for about a 10% performance improvement
3719 * compared to uncached. Graphics requests other than
3720 * display scanout are coherent with the CPU in
3721 * accessing this cache. This means in this mode we
3722 * don't need to clflush on the CPU side, and on the
3723 * GPU side we only need to flush internal caches to
3724 * get data visible to the CPU.
3726 * However, we maintain the display planes as UC, and so
3727 * need to rebind when first used as such.
3729 obj
->cache_level
= I915_CACHE_LLC
;
3731 obj
->cache_level
= I915_CACHE_NONE
;
3736 int i915_gem_init_object(struct drm_gem_object
*obj
)
3743 void i915_gem_free_object(struct drm_gem_object
*gem_obj
)
3745 struct drm_i915_gem_object
*obj
= to_intel_bo(gem_obj
);
3746 struct drm_device
*dev
= obj
->base
.dev
;
3747 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3749 trace_i915_gem_object_destroy(obj
);
3752 i915_gem_detach_phys_object(dev
, obj
);
3755 if (WARN_ON(i915_gem_object_unbind(obj
) == -ERESTARTSYS
)) {
3756 bool was_interruptible
;
3758 was_interruptible
= dev_priv
->mm
.interruptible
;
3759 dev_priv
->mm
.interruptible
= false;
3761 WARN_ON(i915_gem_object_unbind(obj
));
3763 dev_priv
->mm
.interruptible
= was_interruptible
;
3766 obj
->pages_pin_count
= 0;
3767 i915_gem_object_put_pages(obj
);
3768 i915_gem_object_free_mmap_offset(obj
);
3772 if (obj
->base
.import_attach
)
3773 drm_prime_gem_destroy(&obj
->base
, NULL
);
3775 drm_gem_object_release(&obj
->base
);
3776 i915_gem_info_remove_obj(dev_priv
, obj
->base
.size
);
3783 i915_gem_idle(struct drm_device
*dev
)
3785 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3788 mutex_lock(&dev
->struct_mutex
);
3790 if (dev_priv
->mm
.suspended
) {
3791 mutex_unlock(&dev
->struct_mutex
);
3795 ret
= i915_gpu_idle(dev
);
3797 mutex_unlock(&dev
->struct_mutex
);
3800 i915_gem_retire_requests(dev
);
3802 /* Under UMS, be paranoid and evict. */
3803 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
3804 i915_gem_evict_everything(dev
);
3806 i915_gem_reset_fences(dev
);
3808 /* Hack! Don't let anybody do execbuf while we don't control the chip.
3809 * We need to replace this with a semaphore, or something.
3810 * And not confound mm.suspended!
3812 dev_priv
->mm
.suspended
= 1;
3813 del_timer_sync(&dev_priv
->hangcheck_timer
);
3815 i915_kernel_lost_context(dev
);
3816 i915_gem_cleanup_ringbuffer(dev
);
3818 mutex_unlock(&dev
->struct_mutex
);
3820 /* Cancel the retire work handler, which should be idle now. */
3821 cancel_delayed_work_sync(&dev_priv
->mm
.retire_work
);
3826 void i915_gem_l3_remap(struct drm_device
*dev
)
3828 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3832 if (!IS_IVYBRIDGE(dev
))
3835 if (!dev_priv
->mm
.l3_remap_info
)
3838 misccpctl
= I915_READ(GEN7_MISCCPCTL
);
3839 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
& ~GEN7_DOP_CLOCK_GATE_ENABLE
);
3840 POSTING_READ(GEN7_MISCCPCTL
);
3842 for (i
= 0; i
< GEN7_L3LOG_SIZE
; i
+= 4) {
3843 u32 remap
= I915_READ(GEN7_L3LOG_BASE
+ i
);
3844 if (remap
&& remap
!= dev_priv
->mm
.l3_remap_info
[i
/4])
3845 DRM_DEBUG("0x%x was already programmed to %x\n",
3846 GEN7_L3LOG_BASE
+ i
, remap
);
3847 if (remap
&& !dev_priv
->mm
.l3_remap_info
[i
/4])
3848 DRM_DEBUG_DRIVER("Clearing remapped register\n");
3849 I915_WRITE(GEN7_L3LOG_BASE
+ i
, dev_priv
->mm
.l3_remap_info
[i
/4]);
3852 /* Make sure all the writes land before disabling dop clock gating */
3853 POSTING_READ(GEN7_L3LOG_BASE
);
3855 I915_WRITE(GEN7_MISCCPCTL
, misccpctl
);
3858 void i915_gem_init_swizzling(struct drm_device
*dev
)
3860 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3862 if (INTEL_INFO(dev
)->gen
< 5 ||
3863 dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_NONE
)
3866 I915_WRITE(DISP_ARB_CTL
, I915_READ(DISP_ARB_CTL
) |
3867 DISP_TILE_SURFACE_SWIZZLING
);
3872 I915_WRITE(TILECTL
, I915_READ(TILECTL
) | TILECTL_SWZCTL
);
3874 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB
));
3876 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB
));
3879 void i915_gem_init_ppgtt(struct drm_device
*dev
)
3881 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3883 struct intel_ring_buffer
*ring
;
3884 struct i915_hw_ppgtt
*ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
3885 uint32_t __iomem
*pd_addr
;
3889 if (!dev_priv
->mm
.aliasing_ppgtt
)
3893 pd_addr
= dev_priv
->mm
.gtt
->gtt
+ ppgtt
->pd_offset
/sizeof(uint32_t);
3894 for (i
= 0; i
< ppgtt
->num_pd_entries
; i
++) {
3897 if (dev_priv
->mm
.gtt
->needs_dmar
)
3898 pt_addr
= ppgtt
->pt_dma_addr
[i
];
3900 pt_addr
= page_to_phys(ppgtt
->pt_pages
[i
]);
3902 pd_entry
= GEN6_PDE_ADDR_ENCODE(pt_addr
);
3903 pd_entry
|= GEN6_PDE_VALID
;
3905 writel(pd_entry
, pd_addr
+ i
);
3909 pd_offset
= ppgtt
->pd_offset
;
3910 pd_offset
/= 64; /* in cachelines, */
3913 if (INTEL_INFO(dev
)->gen
== 6) {
3914 uint32_t ecochk
, gab_ctl
, ecobits
;
3916 ecobits
= I915_READ(GAC_ECO_BITS
);
3917 I915_WRITE(GAC_ECO_BITS
, ecobits
| ECOBITS_PPGTT_CACHE64B
);
3919 gab_ctl
= I915_READ(GAB_CTL
);
3920 I915_WRITE(GAB_CTL
, gab_ctl
| GAB_CTL_CONT_AFTER_PAGEFAULT
);
3922 ecochk
= I915_READ(GAM_ECOCHK
);
3923 I915_WRITE(GAM_ECOCHK
, ecochk
| ECOCHK_SNB_BIT
|
3924 ECOCHK_PPGTT_CACHE64B
);
3925 I915_WRITE(GFX_MODE
, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE
));
3926 } else if (INTEL_INFO(dev
)->gen
>= 7) {
3927 I915_WRITE(GAM_ECOCHK
, ECOCHK_PPGTT_CACHE64B
);
3928 /* GFX_MODE is per-ring on gen7+ */
3931 for_each_ring(ring
, dev_priv
, i
) {
3932 if (INTEL_INFO(dev
)->gen
>= 7)
3933 I915_WRITE(RING_MODE_GEN7(ring
),
3934 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE
));
3936 I915_WRITE(RING_PP_DIR_DCLV(ring
), PP_DIR_DCLV_2G
);
3937 I915_WRITE(RING_PP_DIR_BASE(ring
), pd_offset
);
3942 intel_enable_blt(struct drm_device
*dev
)
3947 /* The blitter was dysfunctional on early prototypes */
3948 if (IS_GEN6(dev
) && dev
->pdev
->revision
< 8) {
3949 DRM_INFO("BLT not supported on this pre-production hardware;"
3950 " graphics performance will be degraded.\n");
3958 i915_gem_init_hw(struct drm_device
*dev
)
3960 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3963 if (!intel_enable_gtt())
3966 if (IS_HASWELL(dev
) && (I915_READ(0x120010) == 1))
3967 I915_WRITE(0x9008, I915_READ(0x9008) | 0xf0000);
3969 i915_gem_l3_remap(dev
);
3971 i915_gem_init_swizzling(dev
);
3973 ret
= intel_init_render_ring_buffer(dev
);
3978 ret
= intel_init_bsd_ring_buffer(dev
);
3980 goto cleanup_render_ring
;
3983 if (intel_enable_blt(dev
)) {
3984 ret
= intel_init_blt_ring_buffer(dev
);
3986 goto cleanup_bsd_ring
;
3989 dev_priv
->next_seqno
= 1;
3992 * XXX: There was some w/a described somewhere suggesting loading
3993 * contexts before PPGTT.
3995 i915_gem_context_init(dev
);
3996 i915_gem_init_ppgtt(dev
);
4001 intel_cleanup_ring_buffer(&dev_priv
->ring
[VCS
]);
4002 cleanup_render_ring
:
4003 intel_cleanup_ring_buffer(&dev_priv
->ring
[RCS
]);
4008 intel_enable_ppgtt(struct drm_device
*dev
)
4010 if (i915_enable_ppgtt
>= 0)
4011 return i915_enable_ppgtt
;
4013 #ifdef CONFIG_INTEL_IOMMU
4014 /* Disable ppgtt on SNB if VT-d is on. */
4015 if (INTEL_INFO(dev
)->gen
== 6 && intel_iommu_gfx_mapped
)
4022 int i915_gem_init(struct drm_device
*dev
)
4024 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4025 unsigned long gtt_size
, mappable_size
;
4028 gtt_size
= dev_priv
->mm
.gtt
->gtt_total_entries
<< PAGE_SHIFT
;
4029 mappable_size
= dev_priv
->mm
.gtt
->gtt_mappable_entries
<< PAGE_SHIFT
;
4031 mutex_lock(&dev
->struct_mutex
);
4032 if (intel_enable_ppgtt(dev
) && HAS_ALIASING_PPGTT(dev
)) {
4033 /* PPGTT pdes are stolen from global gtt ptes, so shrink the
4034 * aperture accordingly when using aliasing ppgtt. */
4035 gtt_size
-= I915_PPGTT_PD_ENTRIES
*PAGE_SIZE
;
4037 i915_gem_init_global_gtt(dev
, 0, mappable_size
, gtt_size
);
4039 ret
= i915_gem_init_aliasing_ppgtt(dev
);
4041 mutex_unlock(&dev
->struct_mutex
);
4045 /* Let GEM Manage all of the aperture.
4047 * However, leave one page at the end still bound to the scratch
4048 * page. There are a number of places where the hardware
4049 * apparently prefetches past the end of the object, and we've
4050 * seen multiple hangs with the GPU head pointer stuck in a
4051 * batchbuffer bound at the last page of the aperture. One page
4052 * should be enough to keep any prefetching inside of the
4055 i915_gem_init_global_gtt(dev
, 0, mappable_size
,
4059 ret
= i915_gem_init_hw(dev
);
4060 mutex_unlock(&dev
->struct_mutex
);
4062 i915_gem_cleanup_aliasing_ppgtt(dev
);
4066 /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */
4067 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
4068 dev_priv
->dri1
.allow_batchbuffer
= 1;
4073 i915_gem_cleanup_ringbuffer(struct drm_device
*dev
)
4075 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4076 struct intel_ring_buffer
*ring
;
4079 for_each_ring(ring
, dev_priv
, i
)
4080 intel_cleanup_ring_buffer(ring
);
4084 i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
4085 struct drm_file
*file_priv
)
4087 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4090 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4093 if (atomic_read(&dev_priv
->mm
.wedged
)) {
4094 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4095 atomic_set(&dev_priv
->mm
.wedged
, 0);
4098 mutex_lock(&dev
->struct_mutex
);
4099 dev_priv
->mm
.suspended
= 0;
4101 ret
= i915_gem_init_hw(dev
);
4103 mutex_unlock(&dev
->struct_mutex
);
4107 BUG_ON(!list_empty(&dev_priv
->mm
.active_list
));
4108 mutex_unlock(&dev
->struct_mutex
);
4110 ret
= drm_irq_install(dev
);
4112 goto cleanup_ringbuffer
;
4117 mutex_lock(&dev
->struct_mutex
);
4118 i915_gem_cleanup_ringbuffer(dev
);
4119 dev_priv
->mm
.suspended
= 1;
4120 mutex_unlock(&dev
->struct_mutex
);
4126 i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
4127 struct drm_file
*file_priv
)
4129 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4132 drm_irq_uninstall(dev
);
4133 return i915_gem_idle(dev
);
4137 i915_gem_lastclose(struct drm_device
*dev
)
4141 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4144 ret
= i915_gem_idle(dev
);
4146 DRM_ERROR("failed to idle hardware: %d\n", ret
);
4150 init_ring_lists(struct intel_ring_buffer
*ring
)
4152 INIT_LIST_HEAD(&ring
->active_list
);
4153 INIT_LIST_HEAD(&ring
->request_list
);
4157 i915_gem_load(struct drm_device
*dev
)
4160 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4162 INIT_LIST_HEAD(&dev_priv
->mm
.active_list
);
4163 INIT_LIST_HEAD(&dev_priv
->mm
.inactive_list
);
4164 INIT_LIST_HEAD(&dev_priv
->mm
.unbound_list
);
4165 INIT_LIST_HEAD(&dev_priv
->mm
.bound_list
);
4166 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
4167 for (i
= 0; i
< I915_NUM_RINGS
; i
++)
4168 init_ring_lists(&dev_priv
->ring
[i
]);
4169 for (i
= 0; i
< I915_MAX_NUM_FENCES
; i
++)
4170 INIT_LIST_HEAD(&dev_priv
->fence_regs
[i
].lru_list
);
4171 INIT_DELAYED_WORK(&dev_priv
->mm
.retire_work
,
4172 i915_gem_retire_work_handler
);
4173 init_completion(&dev_priv
->error_completion
);
4175 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4177 I915_WRITE(MI_ARB_STATE
,
4178 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE
));
4181 dev_priv
->relative_constants_mode
= I915_EXEC_CONSTANTS_REL_GENERAL
;
4183 /* Old X drivers will take 0-2 for front, back, depth buffers */
4184 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
4185 dev_priv
->fence_reg_start
= 3;
4187 if (INTEL_INFO(dev
)->gen
>= 4 || IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
4188 dev_priv
->num_fence_regs
= 16;
4190 dev_priv
->num_fence_regs
= 8;
4192 /* Initialize fence registers to zero */
4193 i915_gem_reset_fences(dev
);
4195 i915_gem_detect_bit_6_swizzle(dev
);
4196 init_waitqueue_head(&dev_priv
->pending_flip_queue
);
4198 dev_priv
->mm
.interruptible
= true;
4200 dev_priv
->mm
.inactive_shrinker
.shrink
= i915_gem_inactive_shrink
;
4201 dev_priv
->mm
.inactive_shrinker
.seeks
= DEFAULT_SEEKS
;
4202 register_shrinker(&dev_priv
->mm
.inactive_shrinker
);
4206 * Create a physically contiguous memory object for this object
4207 * e.g. for cursor + overlay regs
4209 static int i915_gem_init_phys_object(struct drm_device
*dev
,
4210 int id
, int size
, int align
)
4212 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4213 struct drm_i915_gem_phys_object
*phys_obj
;
4216 if (dev_priv
->mm
.phys_objs
[id
- 1] || !size
)
4219 phys_obj
= kzalloc(sizeof(struct drm_i915_gem_phys_object
), GFP_KERNEL
);
4225 phys_obj
->handle
= drm_pci_alloc(dev
, size
, align
);
4226 if (!phys_obj
->handle
) {
4231 set_memory_wc((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
4234 dev_priv
->mm
.phys_objs
[id
- 1] = phys_obj
;
4242 static void i915_gem_free_phys_object(struct drm_device
*dev
, int id
)
4244 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4245 struct drm_i915_gem_phys_object
*phys_obj
;
4247 if (!dev_priv
->mm
.phys_objs
[id
- 1])
4250 phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
4251 if (phys_obj
->cur_obj
) {
4252 i915_gem_detach_phys_object(dev
, phys_obj
->cur_obj
);
4256 set_memory_wb((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
4258 drm_pci_free(dev
, phys_obj
->handle
);
4260 dev_priv
->mm
.phys_objs
[id
- 1] = NULL
;
4263 void i915_gem_free_all_phys_object(struct drm_device
*dev
)
4267 for (i
= I915_GEM_PHYS_CURSOR_0
; i
<= I915_MAX_PHYS_OBJECT
; i
++)
4268 i915_gem_free_phys_object(dev
, i
);
4271 void i915_gem_detach_phys_object(struct drm_device
*dev
,
4272 struct drm_i915_gem_object
*obj
)
4274 struct address_space
*mapping
= obj
->base
.filp
->f_path
.dentry
->d_inode
->i_mapping
;
4281 vaddr
= obj
->phys_obj
->handle
->vaddr
;
4283 page_count
= obj
->base
.size
/ PAGE_SIZE
;
4284 for (i
= 0; i
< page_count
; i
++) {
4285 struct page
*page
= shmem_read_mapping_page(mapping
, i
);
4286 if (!IS_ERR(page
)) {
4287 char *dst
= kmap_atomic(page
);
4288 memcpy(dst
, vaddr
+ i
*PAGE_SIZE
, PAGE_SIZE
);
4291 drm_clflush_pages(&page
, 1);
4293 set_page_dirty(page
);
4294 mark_page_accessed(page
);
4295 page_cache_release(page
);
4298 intel_gtt_chipset_flush();
4300 obj
->phys_obj
->cur_obj
= NULL
;
4301 obj
->phys_obj
= NULL
;
4305 i915_gem_attach_phys_object(struct drm_device
*dev
,
4306 struct drm_i915_gem_object
*obj
,
4310 struct address_space
*mapping
= obj
->base
.filp
->f_path
.dentry
->d_inode
->i_mapping
;
4311 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4316 if (id
> I915_MAX_PHYS_OBJECT
)
4319 if (obj
->phys_obj
) {
4320 if (obj
->phys_obj
->id
== id
)
4322 i915_gem_detach_phys_object(dev
, obj
);
4325 /* create a new object */
4326 if (!dev_priv
->mm
.phys_objs
[id
- 1]) {
4327 ret
= i915_gem_init_phys_object(dev
, id
,
4328 obj
->base
.size
, align
);
4330 DRM_ERROR("failed to init phys object %d size: %zu\n",
4331 id
, obj
->base
.size
);
4336 /* bind to the object */
4337 obj
->phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
4338 obj
->phys_obj
->cur_obj
= obj
;
4340 page_count
= obj
->base
.size
/ PAGE_SIZE
;
4342 for (i
= 0; i
< page_count
; i
++) {
4346 page
= shmem_read_mapping_page(mapping
, i
);
4348 return PTR_ERR(page
);
4350 src
= kmap_atomic(page
);
4351 dst
= obj
->phys_obj
->handle
->vaddr
+ (i
* PAGE_SIZE
);
4352 memcpy(dst
, src
, PAGE_SIZE
);
4355 mark_page_accessed(page
);
4356 page_cache_release(page
);
4363 i915_gem_phys_pwrite(struct drm_device
*dev
,
4364 struct drm_i915_gem_object
*obj
,
4365 struct drm_i915_gem_pwrite
*args
,
4366 struct drm_file
*file_priv
)
4368 void *vaddr
= obj
->phys_obj
->handle
->vaddr
+ args
->offset
;
4369 char __user
*user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
4371 if (__copy_from_user_inatomic_nocache(vaddr
, user_data
, args
->size
)) {
4372 unsigned long unwritten
;
4374 /* The physical object once assigned is fixed for the lifetime
4375 * of the obj, so we can safely drop the lock and continue
4378 mutex_unlock(&dev
->struct_mutex
);
4379 unwritten
= copy_from_user(vaddr
, user_data
, args
->size
);
4380 mutex_lock(&dev
->struct_mutex
);
4385 intel_gtt_chipset_flush();
4389 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
)
4391 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
4393 /* Clean up our request list when the client is going away, so that
4394 * later retire_requests won't dereference our soon-to-be-gone
4397 spin_lock(&file_priv
->mm
.lock
);
4398 while (!list_empty(&file_priv
->mm
.request_list
)) {
4399 struct drm_i915_gem_request
*request
;
4401 request
= list_first_entry(&file_priv
->mm
.request_list
,
4402 struct drm_i915_gem_request
,
4404 list_del(&request
->client_list
);
4405 request
->file_priv
= NULL
;
4407 spin_unlock(&file_priv
->mm
.lock
);
4411 i915_gem_inactive_shrink(struct shrinker
*shrinker
, struct shrink_control
*sc
)
4413 struct drm_i915_private
*dev_priv
=
4414 container_of(shrinker
,
4415 struct drm_i915_private
,
4416 mm
.inactive_shrinker
);
4417 struct drm_device
*dev
= dev_priv
->dev
;
4418 struct drm_i915_gem_object
*obj
;
4419 int nr_to_scan
= sc
->nr_to_scan
;
4422 if (!mutex_trylock(&dev
->struct_mutex
))
4426 nr_to_scan
-= i915_gem_purge(dev_priv
, nr_to_scan
);
4428 i915_gem_shrink_all(dev_priv
);
4432 list_for_each_entry(obj
, &dev_priv
->mm
.unbound_list
, gtt_list
)
4433 if (obj
->pages_pin_count
== 0)
4434 cnt
+= obj
->base
.size
>> PAGE_SHIFT
;
4435 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, gtt_list
)
4436 if (obj
->pin_count
== 0 && obj
->pages_pin_count
== 0)
4437 cnt
+= obj
->base
.size
>> PAGE_SHIFT
;
4439 mutex_unlock(&dev
->struct_mutex
);