2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/swap.h>
35 #include <linux/pci.h>
37 #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
39 static void i915_gem_object_flush_gpu_write_domain(struct drm_gem_object
*obj
);
40 static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object
*obj
);
41 static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object
*obj
);
42 static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object
*obj
,
44 static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object
*obj
,
47 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object
*obj
);
48 static int i915_gem_object_wait_rendering(struct drm_gem_object
*obj
);
49 static int i915_gem_object_bind_to_gtt(struct drm_gem_object
*obj
,
51 static void i915_gem_clear_fence_reg(struct drm_gem_object
*obj
);
52 static int i915_gem_evict_something(struct drm_device
*dev
, int min_size
);
53 static int i915_gem_evict_from_inactive_list(struct drm_device
*dev
);
54 static int i915_gem_phys_pwrite(struct drm_device
*dev
, struct drm_gem_object
*obj
,
55 struct drm_i915_gem_pwrite
*args
,
56 struct drm_file
*file_priv
);
58 static LIST_HEAD(shrink_list
);
59 static DEFINE_SPINLOCK(shrink_list_lock
);
61 int i915_gem_do_init(struct drm_device
*dev
, unsigned long start
,
64 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
67 (start
& (PAGE_SIZE
- 1)) != 0 ||
68 (end
& (PAGE_SIZE
- 1)) != 0) {
72 drm_mm_init(&dev_priv
->mm
.gtt_space
, start
,
75 dev
->gtt_total
= (uint32_t) (end
- start
);
81 i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
82 struct drm_file
*file_priv
)
84 struct drm_i915_gem_init
*args
= data
;
87 mutex_lock(&dev
->struct_mutex
);
88 ret
= i915_gem_do_init(dev
, args
->gtt_start
, args
->gtt_end
);
89 mutex_unlock(&dev
->struct_mutex
);
95 i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
96 struct drm_file
*file_priv
)
98 struct drm_i915_gem_get_aperture
*args
= data
;
100 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
103 args
->aper_size
= dev
->gtt_total
;
104 args
->aper_available_size
= (args
->aper_size
-
105 atomic_read(&dev
->pin_memory
));
112 * Creates a new mm object and returns a handle to it.
115 i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
116 struct drm_file
*file_priv
)
118 struct drm_i915_gem_create
*args
= data
;
119 struct drm_gem_object
*obj
;
123 args
->size
= roundup(args
->size
, PAGE_SIZE
);
125 /* Allocate the new object */
126 obj
= drm_gem_object_alloc(dev
, args
->size
);
130 ret
= drm_gem_handle_create(file_priv
, obj
, &handle
);
131 drm_gem_object_handle_unreference_unlocked(obj
);
136 args
->handle
= handle
;
142 fast_shmem_read(struct page
**pages
,
143 loff_t page_base
, int page_offset
,
150 vaddr
= kmap_atomic(pages
[page_base
>> PAGE_SHIFT
], KM_USER0
);
153 unwritten
= __copy_to_user_inatomic(data
, vaddr
+ page_offset
, length
);
154 kunmap_atomic(vaddr
, KM_USER0
);
162 static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object
*obj
)
164 drm_i915_private_t
*dev_priv
= obj
->dev
->dev_private
;
165 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
167 return dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_9_10_17
&&
168 obj_priv
->tiling_mode
!= I915_TILING_NONE
;
172 slow_shmem_copy(struct page
*dst_page
,
174 struct page
*src_page
,
178 char *dst_vaddr
, *src_vaddr
;
180 dst_vaddr
= kmap_atomic(dst_page
, KM_USER0
);
181 if (dst_vaddr
== NULL
)
184 src_vaddr
= kmap_atomic(src_page
, KM_USER1
);
185 if (src_vaddr
== NULL
) {
186 kunmap_atomic(dst_vaddr
, KM_USER0
);
190 memcpy(dst_vaddr
+ dst_offset
, src_vaddr
+ src_offset
, length
);
192 kunmap_atomic(src_vaddr
, KM_USER1
);
193 kunmap_atomic(dst_vaddr
, KM_USER0
);
199 slow_shmem_bit17_copy(struct page
*gpu_page
,
201 struct page
*cpu_page
,
206 char *gpu_vaddr
, *cpu_vaddr
;
208 /* Use the unswizzled path if this page isn't affected. */
209 if ((page_to_phys(gpu_page
) & (1 << 17)) == 0) {
211 return slow_shmem_copy(cpu_page
, cpu_offset
,
212 gpu_page
, gpu_offset
, length
);
214 return slow_shmem_copy(gpu_page
, gpu_offset
,
215 cpu_page
, cpu_offset
, length
);
218 gpu_vaddr
= kmap_atomic(gpu_page
, KM_USER0
);
219 if (gpu_vaddr
== NULL
)
222 cpu_vaddr
= kmap_atomic(cpu_page
, KM_USER1
);
223 if (cpu_vaddr
== NULL
) {
224 kunmap_atomic(gpu_vaddr
, KM_USER0
);
228 /* Copy the data, XORing A6 with A17 (1). The user already knows he's
229 * XORing with the other bits (A9 for Y, A9 and A10 for X)
232 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
233 int this_length
= min(cacheline_end
- gpu_offset
, length
);
234 int swizzled_gpu_offset
= gpu_offset
^ 64;
237 memcpy(cpu_vaddr
+ cpu_offset
,
238 gpu_vaddr
+ swizzled_gpu_offset
,
241 memcpy(gpu_vaddr
+ swizzled_gpu_offset
,
242 cpu_vaddr
+ cpu_offset
,
245 cpu_offset
+= this_length
;
246 gpu_offset
+= this_length
;
247 length
-= this_length
;
250 kunmap_atomic(cpu_vaddr
, KM_USER1
);
251 kunmap_atomic(gpu_vaddr
, KM_USER0
);
257 * This is the fast shmem pread path, which attempts to copy_from_user directly
258 * from the backing pages of the object to the user's address space. On a
259 * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
262 i915_gem_shmem_pread_fast(struct drm_device
*dev
, struct drm_gem_object
*obj
,
263 struct drm_i915_gem_pread
*args
,
264 struct drm_file
*file_priv
)
266 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
268 loff_t offset
, page_base
;
269 char __user
*user_data
;
270 int page_offset
, page_length
;
273 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
276 mutex_lock(&dev
->struct_mutex
);
278 ret
= i915_gem_object_get_pages(obj
, 0);
282 ret
= i915_gem_object_set_cpu_read_domain_range(obj
, args
->offset
,
287 obj_priv
= obj
->driver_private
;
288 offset
= args
->offset
;
291 /* Operation in this page
293 * page_base = page offset within aperture
294 * page_offset = offset within page
295 * page_length = bytes to copy for this page
297 page_base
= (offset
& ~(PAGE_SIZE
-1));
298 page_offset
= offset
& (PAGE_SIZE
-1);
299 page_length
= remain
;
300 if ((page_offset
+ remain
) > PAGE_SIZE
)
301 page_length
= PAGE_SIZE
- page_offset
;
303 ret
= fast_shmem_read(obj_priv
->pages
,
304 page_base
, page_offset
,
305 user_data
, page_length
);
309 remain
-= page_length
;
310 user_data
+= page_length
;
311 offset
+= page_length
;
315 i915_gem_object_put_pages(obj
);
317 mutex_unlock(&dev
->struct_mutex
);
323 i915_gem_object_get_pages_or_evict(struct drm_gem_object
*obj
)
327 ret
= i915_gem_object_get_pages(obj
, __GFP_NORETRY
| __GFP_NOWARN
);
329 /* If we've insufficient memory to map in the pages, attempt
330 * to make some space by throwing out some old buffers.
332 if (ret
== -ENOMEM
) {
333 struct drm_device
*dev
= obj
->dev
;
335 ret
= i915_gem_evict_something(dev
, obj
->size
);
339 ret
= i915_gem_object_get_pages(obj
, 0);
346 * This is the fallback shmem pread path, which allocates temporary storage
347 * in kernel space to copy_to_user into outside of the struct_mutex, so we
348 * can copy out of the object's backing pages while holding the struct mutex
349 * and not take page faults.
352 i915_gem_shmem_pread_slow(struct drm_device
*dev
, struct drm_gem_object
*obj
,
353 struct drm_i915_gem_pread
*args
,
354 struct drm_file
*file_priv
)
356 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
357 struct mm_struct
*mm
= current
->mm
;
358 struct page
**user_pages
;
360 loff_t offset
, pinned_pages
, i
;
361 loff_t first_data_page
, last_data_page
, num_pages
;
362 int shmem_page_index
, shmem_page_offset
;
363 int data_page_index
, data_page_offset
;
366 uint64_t data_ptr
= args
->data_ptr
;
367 int do_bit17_swizzling
;
371 /* Pin the user pages containing the data. We can't fault while
372 * holding the struct mutex, yet we want to hold it while
373 * dereferencing the user data.
375 first_data_page
= data_ptr
/ PAGE_SIZE
;
376 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
377 num_pages
= last_data_page
- first_data_page
+ 1;
379 user_pages
= drm_calloc_large(num_pages
, sizeof(struct page
*));
380 if (user_pages
== NULL
)
383 down_read(&mm
->mmap_sem
);
384 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
385 num_pages
, 1, 0, user_pages
, NULL
);
386 up_read(&mm
->mmap_sem
);
387 if (pinned_pages
< num_pages
) {
389 goto fail_put_user_pages
;
392 do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
394 mutex_lock(&dev
->struct_mutex
);
396 ret
= i915_gem_object_get_pages_or_evict(obj
);
400 ret
= i915_gem_object_set_cpu_read_domain_range(obj
, args
->offset
,
405 obj_priv
= obj
->driver_private
;
406 offset
= args
->offset
;
409 /* Operation in this page
411 * shmem_page_index = page number within shmem file
412 * shmem_page_offset = offset within page in shmem file
413 * data_page_index = page number in get_user_pages return
414 * data_page_offset = offset with data_page_index page.
415 * page_length = bytes to copy for this page
417 shmem_page_index
= offset
/ PAGE_SIZE
;
418 shmem_page_offset
= offset
& ~PAGE_MASK
;
419 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
420 data_page_offset
= data_ptr
& ~PAGE_MASK
;
422 page_length
= remain
;
423 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
424 page_length
= PAGE_SIZE
- shmem_page_offset
;
425 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
426 page_length
= PAGE_SIZE
- data_page_offset
;
428 if (do_bit17_swizzling
) {
429 ret
= slow_shmem_bit17_copy(obj_priv
->pages
[shmem_page_index
],
431 user_pages
[data_page_index
],
436 ret
= slow_shmem_copy(user_pages
[data_page_index
],
438 obj_priv
->pages
[shmem_page_index
],
445 remain
-= page_length
;
446 data_ptr
+= page_length
;
447 offset
+= page_length
;
451 i915_gem_object_put_pages(obj
);
453 mutex_unlock(&dev
->struct_mutex
);
455 for (i
= 0; i
< pinned_pages
; i
++) {
456 SetPageDirty(user_pages
[i
]);
457 page_cache_release(user_pages
[i
]);
459 drm_free_large(user_pages
);
465 * Reads data from the object referenced by handle.
467 * On error, the contents of *data are undefined.
470 i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
471 struct drm_file
*file_priv
)
473 struct drm_i915_gem_pread
*args
= data
;
474 struct drm_gem_object
*obj
;
475 struct drm_i915_gem_object
*obj_priv
;
478 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
481 obj_priv
= obj
->driver_private
;
483 /* Bounds check source.
485 * XXX: This could use review for overflow issues...
487 if (args
->offset
> obj
->size
|| args
->size
> obj
->size
||
488 args
->offset
+ args
->size
> obj
->size
) {
489 drm_gem_object_unreference_unlocked(obj
);
493 if (i915_gem_object_needs_bit17_swizzle(obj
)) {
494 ret
= i915_gem_shmem_pread_slow(dev
, obj
, args
, file_priv
);
496 ret
= i915_gem_shmem_pread_fast(dev
, obj
, args
, file_priv
);
498 ret
= i915_gem_shmem_pread_slow(dev
, obj
, args
,
502 drm_gem_object_unreference_unlocked(obj
);
507 /* This is the fast write path which cannot handle
508 * page faults in the source data
512 fast_user_write(struct io_mapping
*mapping
,
513 loff_t page_base
, int page_offset
,
514 char __user
*user_data
,
518 unsigned long unwritten
;
520 vaddr_atomic
= io_mapping_map_atomic_wc(mapping
, page_base
);
521 unwritten
= __copy_from_user_inatomic_nocache(vaddr_atomic
+ page_offset
,
523 io_mapping_unmap_atomic(vaddr_atomic
);
529 /* Here's the write path which can sleep for
534 slow_kernel_write(struct io_mapping
*mapping
,
535 loff_t gtt_base
, int gtt_offset
,
536 struct page
*user_page
, int user_offset
,
539 char *src_vaddr
, *dst_vaddr
;
540 unsigned long unwritten
;
542 dst_vaddr
= io_mapping_map_atomic_wc(mapping
, gtt_base
);
543 src_vaddr
= kmap_atomic(user_page
, KM_USER1
);
544 unwritten
= __copy_from_user_inatomic_nocache(dst_vaddr
+ gtt_offset
,
545 src_vaddr
+ user_offset
,
547 kunmap_atomic(src_vaddr
, KM_USER1
);
548 io_mapping_unmap_atomic(dst_vaddr
);
555 fast_shmem_write(struct page
**pages
,
556 loff_t page_base
, int page_offset
,
561 unsigned long unwritten
;
563 vaddr
= kmap_atomic(pages
[page_base
>> PAGE_SHIFT
], KM_USER0
);
566 unwritten
= __copy_from_user_inatomic(vaddr
+ page_offset
, data
, length
);
567 kunmap_atomic(vaddr
, KM_USER0
);
575 * This is the fast pwrite path, where we copy the data directly from the
576 * user into the GTT, uncached.
579 i915_gem_gtt_pwrite_fast(struct drm_device
*dev
, struct drm_gem_object
*obj
,
580 struct drm_i915_gem_pwrite
*args
,
581 struct drm_file
*file_priv
)
583 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
584 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
586 loff_t offset
, page_base
;
587 char __user
*user_data
;
588 int page_offset
, page_length
;
591 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
593 if (!access_ok(VERIFY_READ
, user_data
, remain
))
597 mutex_lock(&dev
->struct_mutex
);
598 ret
= i915_gem_object_pin(obj
, 0);
600 mutex_unlock(&dev
->struct_mutex
);
603 ret
= i915_gem_object_set_to_gtt_domain(obj
, 1);
607 obj_priv
= obj
->driver_private
;
608 offset
= obj_priv
->gtt_offset
+ args
->offset
;
611 /* Operation in this page
613 * page_base = page offset within aperture
614 * page_offset = offset within page
615 * page_length = bytes to copy for this page
617 page_base
= (offset
& ~(PAGE_SIZE
-1));
618 page_offset
= offset
& (PAGE_SIZE
-1);
619 page_length
= remain
;
620 if ((page_offset
+ remain
) > PAGE_SIZE
)
621 page_length
= PAGE_SIZE
- page_offset
;
623 ret
= fast_user_write (dev_priv
->mm
.gtt_mapping
, page_base
,
624 page_offset
, user_data
, page_length
);
626 /* If we get a fault while copying data, then (presumably) our
627 * source page isn't available. Return the error and we'll
628 * retry in the slow path.
633 remain
-= page_length
;
634 user_data
+= page_length
;
635 offset
+= page_length
;
639 i915_gem_object_unpin(obj
);
640 mutex_unlock(&dev
->struct_mutex
);
646 * This is the fallback GTT pwrite path, which uses get_user_pages to pin
647 * the memory and maps it using kmap_atomic for copying.
649 * This code resulted in x11perf -rgb10text consuming about 10% more CPU
650 * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
653 i915_gem_gtt_pwrite_slow(struct drm_device
*dev
, struct drm_gem_object
*obj
,
654 struct drm_i915_gem_pwrite
*args
,
655 struct drm_file
*file_priv
)
657 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
658 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
660 loff_t gtt_page_base
, offset
;
661 loff_t first_data_page
, last_data_page
, num_pages
;
662 loff_t pinned_pages
, i
;
663 struct page
**user_pages
;
664 struct mm_struct
*mm
= current
->mm
;
665 int gtt_page_offset
, data_page_offset
, data_page_index
, page_length
;
667 uint64_t data_ptr
= args
->data_ptr
;
671 /* Pin the user pages containing the data. We can't fault while
672 * holding the struct mutex, and all of the pwrite implementations
673 * want to hold it while dereferencing the user data.
675 first_data_page
= data_ptr
/ PAGE_SIZE
;
676 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
677 num_pages
= last_data_page
- first_data_page
+ 1;
679 user_pages
= drm_calloc_large(num_pages
, sizeof(struct page
*));
680 if (user_pages
== NULL
)
683 down_read(&mm
->mmap_sem
);
684 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
685 num_pages
, 0, 0, user_pages
, NULL
);
686 up_read(&mm
->mmap_sem
);
687 if (pinned_pages
< num_pages
) {
689 goto out_unpin_pages
;
692 mutex_lock(&dev
->struct_mutex
);
693 ret
= i915_gem_object_pin(obj
, 0);
697 ret
= i915_gem_object_set_to_gtt_domain(obj
, 1);
699 goto out_unpin_object
;
701 obj_priv
= obj
->driver_private
;
702 offset
= obj_priv
->gtt_offset
+ args
->offset
;
705 /* Operation in this page
707 * gtt_page_base = page offset within aperture
708 * gtt_page_offset = offset within page in aperture
709 * data_page_index = page number in get_user_pages return
710 * data_page_offset = offset with data_page_index page.
711 * page_length = bytes to copy for this page
713 gtt_page_base
= offset
& PAGE_MASK
;
714 gtt_page_offset
= offset
& ~PAGE_MASK
;
715 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
716 data_page_offset
= data_ptr
& ~PAGE_MASK
;
718 page_length
= remain
;
719 if ((gtt_page_offset
+ page_length
) > PAGE_SIZE
)
720 page_length
= PAGE_SIZE
- gtt_page_offset
;
721 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
722 page_length
= PAGE_SIZE
- data_page_offset
;
724 ret
= slow_kernel_write(dev_priv
->mm
.gtt_mapping
,
725 gtt_page_base
, gtt_page_offset
,
726 user_pages
[data_page_index
],
730 /* If we get a fault while copying data, then (presumably) our
731 * source page isn't available. Return the error and we'll
732 * retry in the slow path.
735 goto out_unpin_object
;
737 remain
-= page_length
;
738 offset
+= page_length
;
739 data_ptr
+= page_length
;
743 i915_gem_object_unpin(obj
);
745 mutex_unlock(&dev
->struct_mutex
);
747 for (i
= 0; i
< pinned_pages
; i
++)
748 page_cache_release(user_pages
[i
]);
749 drm_free_large(user_pages
);
755 * This is the fast shmem pwrite path, which attempts to directly
756 * copy_from_user into the kmapped pages backing the object.
759 i915_gem_shmem_pwrite_fast(struct drm_device
*dev
, struct drm_gem_object
*obj
,
760 struct drm_i915_gem_pwrite
*args
,
761 struct drm_file
*file_priv
)
763 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
765 loff_t offset
, page_base
;
766 char __user
*user_data
;
767 int page_offset
, page_length
;
770 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
773 mutex_lock(&dev
->struct_mutex
);
775 ret
= i915_gem_object_get_pages(obj
, 0);
779 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
783 obj_priv
= obj
->driver_private
;
784 offset
= args
->offset
;
788 /* Operation in this page
790 * page_base = page offset within aperture
791 * page_offset = offset within page
792 * page_length = bytes to copy for this page
794 page_base
= (offset
& ~(PAGE_SIZE
-1));
795 page_offset
= offset
& (PAGE_SIZE
-1);
796 page_length
= remain
;
797 if ((page_offset
+ remain
) > PAGE_SIZE
)
798 page_length
= PAGE_SIZE
- page_offset
;
800 ret
= fast_shmem_write(obj_priv
->pages
,
801 page_base
, page_offset
,
802 user_data
, page_length
);
806 remain
-= page_length
;
807 user_data
+= page_length
;
808 offset
+= page_length
;
812 i915_gem_object_put_pages(obj
);
814 mutex_unlock(&dev
->struct_mutex
);
820 * This is the fallback shmem pwrite path, which uses get_user_pages to pin
821 * the memory and maps it using kmap_atomic for copying.
823 * This avoids taking mmap_sem for faulting on the user's address while the
824 * struct_mutex is held.
827 i915_gem_shmem_pwrite_slow(struct drm_device
*dev
, struct drm_gem_object
*obj
,
828 struct drm_i915_gem_pwrite
*args
,
829 struct drm_file
*file_priv
)
831 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
832 struct mm_struct
*mm
= current
->mm
;
833 struct page
**user_pages
;
835 loff_t offset
, pinned_pages
, i
;
836 loff_t first_data_page
, last_data_page
, num_pages
;
837 int shmem_page_index
, shmem_page_offset
;
838 int data_page_index
, data_page_offset
;
841 uint64_t data_ptr
= args
->data_ptr
;
842 int do_bit17_swizzling
;
846 /* Pin the user pages containing the data. We can't fault while
847 * holding the struct mutex, and all of the pwrite implementations
848 * want to hold it while dereferencing the user data.
850 first_data_page
= data_ptr
/ PAGE_SIZE
;
851 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
852 num_pages
= last_data_page
- first_data_page
+ 1;
854 user_pages
= drm_calloc_large(num_pages
, sizeof(struct page
*));
855 if (user_pages
== NULL
)
858 down_read(&mm
->mmap_sem
);
859 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
860 num_pages
, 0, 0, user_pages
, NULL
);
861 up_read(&mm
->mmap_sem
);
862 if (pinned_pages
< num_pages
) {
864 goto fail_put_user_pages
;
867 do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
869 mutex_lock(&dev
->struct_mutex
);
871 ret
= i915_gem_object_get_pages_or_evict(obj
);
875 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
879 obj_priv
= obj
->driver_private
;
880 offset
= args
->offset
;
884 /* Operation in this page
886 * shmem_page_index = page number within shmem file
887 * shmem_page_offset = offset within page in shmem file
888 * data_page_index = page number in get_user_pages return
889 * data_page_offset = offset with data_page_index page.
890 * page_length = bytes to copy for this page
892 shmem_page_index
= offset
/ PAGE_SIZE
;
893 shmem_page_offset
= offset
& ~PAGE_MASK
;
894 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
895 data_page_offset
= data_ptr
& ~PAGE_MASK
;
897 page_length
= remain
;
898 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
899 page_length
= PAGE_SIZE
- shmem_page_offset
;
900 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
901 page_length
= PAGE_SIZE
- data_page_offset
;
903 if (do_bit17_swizzling
) {
904 ret
= slow_shmem_bit17_copy(obj_priv
->pages
[shmem_page_index
],
906 user_pages
[data_page_index
],
911 ret
= slow_shmem_copy(obj_priv
->pages
[shmem_page_index
],
913 user_pages
[data_page_index
],
920 remain
-= page_length
;
921 data_ptr
+= page_length
;
922 offset
+= page_length
;
926 i915_gem_object_put_pages(obj
);
928 mutex_unlock(&dev
->struct_mutex
);
930 for (i
= 0; i
< pinned_pages
; i
++)
931 page_cache_release(user_pages
[i
]);
932 drm_free_large(user_pages
);
938 * Writes data to the object referenced by handle.
940 * On error, the contents of the buffer that were to be modified are undefined.
943 i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
944 struct drm_file
*file_priv
)
946 struct drm_i915_gem_pwrite
*args
= data
;
947 struct drm_gem_object
*obj
;
948 struct drm_i915_gem_object
*obj_priv
;
951 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
954 obj_priv
= obj
->driver_private
;
956 /* Bounds check destination.
958 * XXX: This could use review for overflow issues...
960 if (args
->offset
> obj
->size
|| args
->size
> obj
->size
||
961 args
->offset
+ args
->size
> obj
->size
) {
962 drm_gem_object_unreference_unlocked(obj
);
966 /* We can only do the GTT pwrite on untiled buffers, as otherwise
967 * it would end up going through the fenced access, and we'll get
968 * different detiling behavior between reading and writing.
969 * pread/pwrite currently are reading and writing from the CPU
970 * perspective, requiring manual detiling by the client.
972 if (obj_priv
->phys_obj
)
973 ret
= i915_gem_phys_pwrite(dev
, obj
, args
, file_priv
);
974 else if (obj_priv
->tiling_mode
== I915_TILING_NONE
&&
975 dev
->gtt_total
!= 0) {
976 ret
= i915_gem_gtt_pwrite_fast(dev
, obj
, args
, file_priv
);
977 if (ret
== -EFAULT
) {
978 ret
= i915_gem_gtt_pwrite_slow(dev
, obj
, args
,
981 } else if (i915_gem_object_needs_bit17_swizzle(obj
)) {
982 ret
= i915_gem_shmem_pwrite_slow(dev
, obj
, args
, file_priv
);
984 ret
= i915_gem_shmem_pwrite_fast(dev
, obj
, args
, file_priv
);
985 if (ret
== -EFAULT
) {
986 ret
= i915_gem_shmem_pwrite_slow(dev
, obj
, args
,
993 DRM_INFO("pwrite failed %d\n", ret
);
996 drm_gem_object_unreference_unlocked(obj
);
1002 * Called when user space prepares to use an object with the CPU, either
1003 * through the mmap ioctl's mapping or a GTT mapping.
1006 i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
1007 struct drm_file
*file_priv
)
1009 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1010 struct drm_i915_gem_set_domain
*args
= data
;
1011 struct drm_gem_object
*obj
;
1012 struct drm_i915_gem_object
*obj_priv
;
1013 uint32_t read_domains
= args
->read_domains
;
1014 uint32_t write_domain
= args
->write_domain
;
1017 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1020 /* Only handle setting domains to types used by the CPU. */
1021 if (write_domain
& I915_GEM_GPU_DOMAINS
)
1024 if (read_domains
& I915_GEM_GPU_DOMAINS
)
1027 /* Having something in the write domain implies it's in the read
1028 * domain, and only that read domain. Enforce that in the request.
1030 if (write_domain
!= 0 && read_domains
!= write_domain
)
1033 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1036 obj_priv
= obj
->driver_private
;
1038 mutex_lock(&dev
->struct_mutex
);
1040 intel_mark_busy(dev
, obj
);
1043 DRM_INFO("set_domain_ioctl %p(%zd), %08x %08x\n",
1044 obj
, obj
->size
, read_domains
, write_domain
);
1046 if (read_domains
& I915_GEM_DOMAIN_GTT
) {
1047 ret
= i915_gem_object_set_to_gtt_domain(obj
, write_domain
!= 0);
1049 /* Update the LRU on the fence for the CPU access that's
1052 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
) {
1053 list_move_tail(&obj_priv
->fence_list
,
1054 &dev_priv
->mm
.fence_list
);
1057 /* Silently promote "you're not bound, there was nothing to do"
1058 * to success, since the client was just asking us to
1059 * make sure everything was done.
1064 ret
= i915_gem_object_set_to_cpu_domain(obj
, write_domain
!= 0);
1067 drm_gem_object_unreference(obj
);
1068 mutex_unlock(&dev
->struct_mutex
);
1073 * Called when user space has done writes to this buffer
1076 i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1077 struct drm_file
*file_priv
)
1079 struct drm_i915_gem_sw_finish
*args
= data
;
1080 struct drm_gem_object
*obj
;
1081 struct drm_i915_gem_object
*obj_priv
;
1084 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1087 mutex_lock(&dev
->struct_mutex
);
1088 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1090 mutex_unlock(&dev
->struct_mutex
);
1095 DRM_INFO("%s: sw_finish %d (%p %zd)\n",
1096 __func__
, args
->handle
, obj
, obj
->size
);
1098 obj_priv
= obj
->driver_private
;
1100 /* Pinned buffers may be scanout, so flush the cache */
1101 if (obj_priv
->pin_count
)
1102 i915_gem_object_flush_cpu_write_domain(obj
);
1104 drm_gem_object_unreference(obj
);
1105 mutex_unlock(&dev
->struct_mutex
);
1110 * Maps the contents of an object, returning the address it is mapped
1113 * While the mapping holds a reference on the contents of the object, it doesn't
1114 * imply a ref on the object itself.
1117 i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1118 struct drm_file
*file_priv
)
1120 struct drm_i915_gem_mmap
*args
= data
;
1121 struct drm_gem_object
*obj
;
1125 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1128 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1132 offset
= args
->offset
;
1134 down_write(¤t
->mm
->mmap_sem
);
1135 addr
= do_mmap(obj
->filp
, 0, args
->size
,
1136 PROT_READ
| PROT_WRITE
, MAP_SHARED
,
1138 up_write(¤t
->mm
->mmap_sem
);
1139 drm_gem_object_unreference_unlocked(obj
);
1140 if (IS_ERR((void *)addr
))
1143 args
->addr_ptr
= (uint64_t) addr
;
1149 * i915_gem_fault - fault a page into the GTT
1150 * vma: VMA in question
1153 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1154 * from userspace. The fault handler takes care of binding the object to
1155 * the GTT (if needed), allocating and programming a fence register (again,
1156 * only if needed based on whether the old reg is still valid or the object
1157 * is tiled) and inserting a new PTE into the faulting process.
1159 * Note that the faulting process may involve evicting existing objects
1160 * from the GTT and/or fence registers to make room. So performance may
1161 * suffer if the GTT working set is large or there are few fence registers
1164 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
)
1166 struct drm_gem_object
*obj
= vma
->vm_private_data
;
1167 struct drm_device
*dev
= obj
->dev
;
1168 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1169 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1170 pgoff_t page_offset
;
1173 bool write
= !!(vmf
->flags
& FAULT_FLAG_WRITE
);
1175 /* We don't use vmf->pgoff since that has the fake offset */
1176 page_offset
= ((unsigned long)vmf
->virtual_address
- vma
->vm_start
) >>
1179 /* Now bind it into the GTT if needed */
1180 mutex_lock(&dev
->struct_mutex
);
1181 if (!obj_priv
->gtt_space
) {
1182 ret
= i915_gem_object_bind_to_gtt(obj
, 0);
1186 list_add_tail(&obj_priv
->list
, &dev_priv
->mm
.inactive_list
);
1188 ret
= i915_gem_object_set_to_gtt_domain(obj
, write
);
1193 /* Need a new fence register? */
1194 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
) {
1195 ret
= i915_gem_object_get_fence_reg(obj
);
1200 pfn
= ((dev
->agp
->base
+ obj_priv
->gtt_offset
) >> PAGE_SHIFT
) +
1203 /* Finally, remap it using the new GTT offset */
1204 ret
= vm_insert_pfn(vma
, (unsigned long)vmf
->virtual_address
, pfn
);
1206 mutex_unlock(&dev
->struct_mutex
);
1211 return VM_FAULT_NOPAGE
;
1214 return VM_FAULT_OOM
;
1216 return VM_FAULT_SIGBUS
;
1221 * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1222 * @obj: obj in question
1224 * GEM memory mapping works by handing back to userspace a fake mmap offset
1225 * it can use in a subsequent mmap(2) call. The DRM core code then looks
1226 * up the object based on the offset and sets up the various memory mapping
1229 * This routine allocates and attaches a fake offset for @obj.
1232 i915_gem_create_mmap_offset(struct drm_gem_object
*obj
)
1234 struct drm_device
*dev
= obj
->dev
;
1235 struct drm_gem_mm
*mm
= dev
->mm_private
;
1236 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1237 struct drm_map_list
*list
;
1238 struct drm_local_map
*map
;
1241 /* Set the object up for mmap'ing */
1242 list
= &obj
->map_list
;
1243 list
->map
= kzalloc(sizeof(struct drm_map_list
), GFP_KERNEL
);
1248 map
->type
= _DRM_GEM
;
1249 map
->size
= obj
->size
;
1252 /* Get a DRM GEM mmap offset allocated... */
1253 list
->file_offset_node
= drm_mm_search_free(&mm
->offset_manager
,
1254 obj
->size
/ PAGE_SIZE
, 0, 0);
1255 if (!list
->file_offset_node
) {
1256 DRM_ERROR("failed to allocate offset for bo %d\n", obj
->name
);
1261 list
->file_offset_node
= drm_mm_get_block(list
->file_offset_node
,
1262 obj
->size
/ PAGE_SIZE
, 0);
1263 if (!list
->file_offset_node
) {
1268 list
->hash
.key
= list
->file_offset_node
->start
;
1269 if (drm_ht_insert_item(&mm
->offset_hash
, &list
->hash
)) {
1270 DRM_ERROR("failed to add to map hash\n");
1275 /* By now we should be all set, any drm_mmap request on the offset
1276 * below will get to our mmap & fault handler */
1277 obj_priv
->mmap_offset
= ((uint64_t) list
->hash
.key
) << PAGE_SHIFT
;
1282 drm_mm_put_block(list
->file_offset_node
);
1290 * i915_gem_release_mmap - remove physical page mappings
1291 * @obj: obj in question
1293 * Preserve the reservation of the mmapping with the DRM core code, but
1294 * relinquish ownership of the pages back to the system.
1296 * It is vital that we remove the page mapping if we have mapped a tiled
1297 * object through the GTT and then lose the fence register due to
1298 * resource pressure. Similarly if the object has been moved out of the
1299 * aperture, than pages mapped into userspace must be revoked. Removing the
1300 * mapping will then trigger a page fault on the next user access, allowing
1301 * fixup by i915_gem_fault().
1304 i915_gem_release_mmap(struct drm_gem_object
*obj
)
1306 struct drm_device
*dev
= obj
->dev
;
1307 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1309 if (dev
->dev_mapping
)
1310 unmap_mapping_range(dev
->dev_mapping
,
1311 obj_priv
->mmap_offset
, obj
->size
, 1);
1315 i915_gem_free_mmap_offset(struct drm_gem_object
*obj
)
1317 struct drm_device
*dev
= obj
->dev
;
1318 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1319 struct drm_gem_mm
*mm
= dev
->mm_private
;
1320 struct drm_map_list
*list
;
1322 list
= &obj
->map_list
;
1323 drm_ht_remove_item(&mm
->offset_hash
, &list
->hash
);
1325 if (list
->file_offset_node
) {
1326 drm_mm_put_block(list
->file_offset_node
);
1327 list
->file_offset_node
= NULL
;
1335 obj_priv
->mmap_offset
= 0;
1339 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1340 * @obj: object to check
1342 * Return the required GTT alignment for an object, taking into account
1343 * potential fence register mapping if needed.
1346 i915_gem_get_gtt_alignment(struct drm_gem_object
*obj
)
1348 struct drm_device
*dev
= obj
->dev
;
1349 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1353 * Minimum alignment is 4k (GTT page size), but might be greater
1354 * if a fence register is needed for the object.
1356 if (IS_I965G(dev
) || obj_priv
->tiling_mode
== I915_TILING_NONE
)
1360 * Previous chips need to be aligned to the size of the smallest
1361 * fence register that can contain the object.
1368 for (i
= start
; i
< obj
->size
; i
<<= 1)
1375 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1377 * @data: GTT mapping ioctl data
1378 * @file_priv: GEM object info
1380 * Simply returns the fake offset to userspace so it can mmap it.
1381 * The mmap call will end up in drm_gem_mmap(), which will set things
1382 * up so we can get faults in the handler above.
1384 * The fault handler will take care of binding the object into the GTT
1385 * (since it may have been evicted to make room for something), allocating
1386 * a fence register, and mapping the appropriate aperture address into
1390 i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
1391 struct drm_file
*file_priv
)
1393 struct drm_i915_gem_mmap_gtt
*args
= data
;
1394 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1395 struct drm_gem_object
*obj
;
1396 struct drm_i915_gem_object
*obj_priv
;
1399 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1402 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1406 mutex_lock(&dev
->struct_mutex
);
1408 obj_priv
= obj
->driver_private
;
1410 if (obj_priv
->madv
!= I915_MADV_WILLNEED
) {
1411 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1412 drm_gem_object_unreference(obj
);
1413 mutex_unlock(&dev
->struct_mutex
);
1418 if (!obj_priv
->mmap_offset
) {
1419 ret
= i915_gem_create_mmap_offset(obj
);
1421 drm_gem_object_unreference(obj
);
1422 mutex_unlock(&dev
->struct_mutex
);
1427 args
->offset
= obj_priv
->mmap_offset
;
1430 * Pull it into the GTT so that we have a page list (makes the
1431 * initial fault faster and any subsequent flushing possible).
1433 if (!obj_priv
->agp_mem
) {
1434 ret
= i915_gem_object_bind_to_gtt(obj
, 0);
1436 drm_gem_object_unreference(obj
);
1437 mutex_unlock(&dev
->struct_mutex
);
1440 list_add_tail(&obj_priv
->list
, &dev_priv
->mm
.inactive_list
);
1443 drm_gem_object_unreference(obj
);
1444 mutex_unlock(&dev
->struct_mutex
);
1450 i915_gem_object_put_pages(struct drm_gem_object
*obj
)
1452 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1453 int page_count
= obj
->size
/ PAGE_SIZE
;
1456 BUG_ON(obj_priv
->pages_refcount
== 0);
1457 BUG_ON(obj_priv
->madv
== __I915_MADV_PURGED
);
1459 if (--obj_priv
->pages_refcount
!= 0)
1462 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
)
1463 i915_gem_object_save_bit_17_swizzle(obj
);
1465 if (obj_priv
->madv
== I915_MADV_DONTNEED
)
1466 obj_priv
->dirty
= 0;
1468 for (i
= 0; i
< page_count
; i
++) {
1469 if (obj_priv
->pages
[i
] == NULL
)
1472 if (obj_priv
->dirty
)
1473 set_page_dirty(obj_priv
->pages
[i
]);
1475 if (obj_priv
->madv
== I915_MADV_WILLNEED
)
1476 mark_page_accessed(obj_priv
->pages
[i
]);
1478 page_cache_release(obj_priv
->pages
[i
]);
1480 obj_priv
->dirty
= 0;
1482 drm_free_large(obj_priv
->pages
);
1483 obj_priv
->pages
= NULL
;
1487 i915_gem_object_move_to_active(struct drm_gem_object
*obj
, uint32_t seqno
)
1489 struct drm_device
*dev
= obj
->dev
;
1490 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1491 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1493 /* Add a reference if we're newly entering the active list. */
1494 if (!obj_priv
->active
) {
1495 drm_gem_object_reference(obj
);
1496 obj_priv
->active
= 1;
1498 /* Move from whatever list we were on to the tail of execution. */
1499 spin_lock(&dev_priv
->mm
.active_list_lock
);
1500 list_move_tail(&obj_priv
->list
,
1501 &dev_priv
->mm
.active_list
);
1502 spin_unlock(&dev_priv
->mm
.active_list_lock
);
1503 obj_priv
->last_rendering_seqno
= seqno
;
1507 i915_gem_object_move_to_flushing(struct drm_gem_object
*obj
)
1509 struct drm_device
*dev
= obj
->dev
;
1510 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1511 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1513 BUG_ON(!obj_priv
->active
);
1514 list_move_tail(&obj_priv
->list
, &dev_priv
->mm
.flushing_list
);
1515 obj_priv
->last_rendering_seqno
= 0;
1518 /* Immediately discard the backing storage */
1520 i915_gem_object_truncate(struct drm_gem_object
*obj
)
1522 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1523 struct inode
*inode
;
1525 inode
= obj
->filp
->f_path
.dentry
->d_inode
;
1526 if (inode
->i_op
->truncate
)
1527 inode
->i_op
->truncate (inode
);
1529 obj_priv
->madv
= __I915_MADV_PURGED
;
1533 i915_gem_object_is_purgeable(struct drm_i915_gem_object
*obj_priv
)
1535 return obj_priv
->madv
== I915_MADV_DONTNEED
;
1539 i915_gem_object_move_to_inactive(struct drm_gem_object
*obj
)
1541 struct drm_device
*dev
= obj
->dev
;
1542 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1543 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1545 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
1546 if (obj_priv
->pin_count
!= 0)
1547 list_del_init(&obj_priv
->list
);
1549 list_move_tail(&obj_priv
->list
, &dev_priv
->mm
.inactive_list
);
1551 BUG_ON(!list_empty(&obj_priv
->gpu_write_list
));
1553 obj_priv
->last_rendering_seqno
= 0;
1554 if (obj_priv
->active
) {
1555 obj_priv
->active
= 0;
1556 drm_gem_object_unreference(obj
);
1558 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
1562 * Creates a new sequence number, emitting a write of it to the status page
1563 * plus an interrupt, which will trigger i915_user_interrupt_handler.
1565 * Must be called with struct_lock held.
1567 * Returned sequence numbers are nonzero on success.
1570 i915_add_request(struct drm_device
*dev
, struct drm_file
*file_priv
,
1571 uint32_t flush_domains
)
1573 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1574 struct drm_i915_file_private
*i915_file_priv
= NULL
;
1575 struct drm_i915_gem_request
*request
;
1580 if (file_priv
!= NULL
)
1581 i915_file_priv
= file_priv
->driver_priv
;
1583 request
= kzalloc(sizeof(*request
), GFP_KERNEL
);
1584 if (request
== NULL
)
1587 /* Grab the seqno we're going to make this request be, and bump the
1588 * next (skipping 0 so it can be the reserved no-seqno value).
1590 seqno
= dev_priv
->mm
.next_gem_seqno
;
1591 dev_priv
->mm
.next_gem_seqno
++;
1592 if (dev_priv
->mm
.next_gem_seqno
== 0)
1593 dev_priv
->mm
.next_gem_seqno
++;
1596 OUT_RING(MI_STORE_DWORD_INDEX
);
1597 OUT_RING(I915_GEM_HWS_INDEX
<< MI_STORE_DWORD_INDEX_SHIFT
);
1600 OUT_RING(MI_USER_INTERRUPT
);
1603 DRM_DEBUG_DRIVER("%d\n", seqno
);
1605 request
->seqno
= seqno
;
1606 request
->emitted_jiffies
= jiffies
;
1607 was_empty
= list_empty(&dev_priv
->mm
.request_list
);
1608 list_add_tail(&request
->list
, &dev_priv
->mm
.request_list
);
1609 if (i915_file_priv
) {
1610 list_add_tail(&request
->client_list
,
1611 &i915_file_priv
->mm
.request_list
);
1613 INIT_LIST_HEAD(&request
->client_list
);
1616 /* Associate any objects on the flushing list matching the write
1617 * domain we're flushing with our flush.
1619 if (flush_domains
!= 0) {
1620 struct drm_i915_gem_object
*obj_priv
, *next
;
1622 list_for_each_entry_safe(obj_priv
, next
,
1623 &dev_priv
->mm
.gpu_write_list
,
1625 struct drm_gem_object
*obj
= obj_priv
->obj
;
1627 if ((obj
->write_domain
& flush_domains
) ==
1628 obj
->write_domain
) {
1629 uint32_t old_write_domain
= obj
->write_domain
;
1631 obj
->write_domain
= 0;
1632 list_del_init(&obj_priv
->gpu_write_list
);
1633 i915_gem_object_move_to_active(obj
, seqno
);
1635 trace_i915_gem_object_change_domain(obj
,
1643 if (!dev_priv
->mm
.suspended
) {
1644 mod_timer(&dev_priv
->hangcheck_timer
, jiffies
+ DRM_I915_HANGCHECK_PERIOD
);
1646 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, HZ
);
1652 * Command execution barrier
1654 * Ensures that all commands in the ring are finished
1655 * before signalling the CPU
1658 i915_retire_commands(struct drm_device
*dev
)
1660 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1661 uint32_t cmd
= MI_FLUSH
| MI_NO_WRITE_FLUSH
;
1662 uint32_t flush_domains
= 0;
1665 /* The sampler always gets flushed on i965 (sigh) */
1667 flush_domains
|= I915_GEM_DOMAIN_SAMPLER
;
1670 OUT_RING(0); /* noop */
1672 return flush_domains
;
1676 * Moves buffers associated only with the given active seqno from the active
1677 * to inactive list, potentially freeing them.
1680 i915_gem_retire_request(struct drm_device
*dev
,
1681 struct drm_i915_gem_request
*request
)
1683 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1685 trace_i915_gem_request_retire(dev
, request
->seqno
);
1687 /* Move any buffers on the active list that are no longer referenced
1688 * by the ringbuffer to the flushing/inactive lists as appropriate.
1690 spin_lock(&dev_priv
->mm
.active_list_lock
);
1691 while (!list_empty(&dev_priv
->mm
.active_list
)) {
1692 struct drm_gem_object
*obj
;
1693 struct drm_i915_gem_object
*obj_priv
;
1695 obj_priv
= list_first_entry(&dev_priv
->mm
.active_list
,
1696 struct drm_i915_gem_object
,
1698 obj
= obj_priv
->obj
;
1700 /* If the seqno being retired doesn't match the oldest in the
1701 * list, then the oldest in the list must still be newer than
1704 if (obj_priv
->last_rendering_seqno
!= request
->seqno
)
1708 DRM_INFO("%s: retire %d moves to inactive list %p\n",
1709 __func__
, request
->seqno
, obj
);
1712 if (obj
->write_domain
!= 0)
1713 i915_gem_object_move_to_flushing(obj
);
1715 /* Take a reference on the object so it won't be
1716 * freed while the spinlock is held. The list
1717 * protection for this spinlock is safe when breaking
1718 * the lock like this since the next thing we do
1719 * is just get the head of the list again.
1721 drm_gem_object_reference(obj
);
1722 i915_gem_object_move_to_inactive(obj
);
1723 spin_unlock(&dev_priv
->mm
.active_list_lock
);
1724 drm_gem_object_unreference(obj
);
1725 spin_lock(&dev_priv
->mm
.active_list_lock
);
1729 spin_unlock(&dev_priv
->mm
.active_list_lock
);
1733 * Returns true if seq1 is later than seq2.
1736 i915_seqno_passed(uint32_t seq1
, uint32_t seq2
)
1738 return (int32_t)(seq1
- seq2
) >= 0;
1742 i915_get_gem_seqno(struct drm_device
*dev
)
1744 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1746 return READ_HWSP(dev_priv
, I915_GEM_HWS_INDEX
);
1750 * This function clears the request list as sequence numbers are passed.
1753 i915_gem_retire_requests(struct drm_device
*dev
)
1755 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1758 if (!dev_priv
->hw_status_page
|| list_empty(&dev_priv
->mm
.request_list
))
1761 seqno
= i915_get_gem_seqno(dev
);
1763 while (!list_empty(&dev_priv
->mm
.request_list
)) {
1764 struct drm_i915_gem_request
*request
;
1765 uint32_t retiring_seqno
;
1767 request
= list_first_entry(&dev_priv
->mm
.request_list
,
1768 struct drm_i915_gem_request
,
1770 retiring_seqno
= request
->seqno
;
1772 if (i915_seqno_passed(seqno
, retiring_seqno
) ||
1773 atomic_read(&dev_priv
->mm
.wedged
)) {
1774 i915_gem_retire_request(dev
, request
);
1776 list_del(&request
->list
);
1777 list_del(&request
->client_list
);
1783 if (unlikely (dev_priv
->trace_irq_seqno
&&
1784 i915_seqno_passed(dev_priv
->trace_irq_seqno
, seqno
))) {
1785 i915_user_irq_put(dev
);
1786 dev_priv
->trace_irq_seqno
= 0;
1791 i915_gem_retire_work_handler(struct work_struct
*work
)
1793 drm_i915_private_t
*dev_priv
;
1794 struct drm_device
*dev
;
1796 dev_priv
= container_of(work
, drm_i915_private_t
,
1797 mm
.retire_work
.work
);
1798 dev
= dev_priv
->dev
;
1800 mutex_lock(&dev
->struct_mutex
);
1801 i915_gem_retire_requests(dev
);
1802 if (!dev_priv
->mm
.suspended
&&
1803 !list_empty(&dev_priv
->mm
.request_list
))
1804 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, HZ
);
1805 mutex_unlock(&dev
->struct_mutex
);
1809 i915_do_wait_request(struct drm_device
*dev
, uint32_t seqno
, int interruptible
)
1811 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1817 if (atomic_read(&dev_priv
->mm
.wedged
))
1820 if (!i915_seqno_passed(i915_get_gem_seqno(dev
), seqno
)) {
1821 if (IS_IRONLAKE(dev
))
1822 ier
= I915_READ(DEIER
) | I915_READ(GTIER
);
1824 ier
= I915_READ(IER
);
1826 DRM_ERROR("something (likely vbetool) disabled "
1827 "interrupts, re-enabling\n");
1828 i915_driver_irq_preinstall(dev
);
1829 i915_driver_irq_postinstall(dev
);
1832 trace_i915_gem_request_wait_begin(dev
, seqno
);
1834 dev_priv
->mm
.waiting_gem_seqno
= seqno
;
1835 i915_user_irq_get(dev
);
1837 ret
= wait_event_interruptible(dev_priv
->irq_queue
,
1838 i915_seqno_passed(i915_get_gem_seqno(dev
), seqno
) ||
1839 atomic_read(&dev_priv
->mm
.wedged
));
1841 wait_event(dev_priv
->irq_queue
,
1842 i915_seqno_passed(i915_get_gem_seqno(dev
), seqno
) ||
1843 atomic_read(&dev_priv
->mm
.wedged
));
1845 i915_user_irq_put(dev
);
1846 dev_priv
->mm
.waiting_gem_seqno
= 0;
1848 trace_i915_gem_request_wait_end(dev
, seqno
);
1850 if (atomic_read(&dev_priv
->mm
.wedged
))
1853 if (ret
&& ret
!= -ERESTARTSYS
)
1854 DRM_ERROR("%s returns %d (awaiting %d at %d)\n",
1855 __func__
, ret
, seqno
, i915_get_gem_seqno(dev
));
1857 /* Directly dispatch request retiring. While we have the work queue
1858 * to handle this, the waiter on a request often wants an associated
1859 * buffer to have made it to the inactive list, and we would need
1860 * a separate wait queue to handle that.
1863 i915_gem_retire_requests(dev
);
1869 * Waits for a sequence number to be signaled, and cleans up the
1870 * request and object lists appropriately for that event.
1873 i915_wait_request(struct drm_device
*dev
, uint32_t seqno
)
1875 return i915_do_wait_request(dev
, seqno
, 1);
1879 i915_gem_flush(struct drm_device
*dev
,
1880 uint32_t invalidate_domains
,
1881 uint32_t flush_domains
)
1883 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1888 DRM_INFO("%s: invalidate %08x flush %08x\n", __func__
,
1889 invalidate_domains
, flush_domains
);
1891 trace_i915_gem_request_flush(dev
, dev_priv
->mm
.next_gem_seqno
,
1892 invalidate_domains
, flush_domains
);
1894 if (flush_domains
& I915_GEM_DOMAIN_CPU
)
1895 drm_agp_chipset_flush(dev
);
1897 if ((invalidate_domains
| flush_domains
) & I915_GEM_GPU_DOMAINS
) {
1899 * read/write caches:
1901 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
1902 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
1903 * also flushed at 2d versus 3d pipeline switches.
1907 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
1908 * MI_READ_FLUSH is set, and is always flushed on 965.
1910 * I915_GEM_DOMAIN_COMMAND may not exist?
1912 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
1913 * invalidated when MI_EXE_FLUSH is set.
1915 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
1916 * invalidated with every MI_FLUSH.
1920 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
1921 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
1922 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
1923 * are flushed at any MI_FLUSH.
1926 cmd
= MI_FLUSH
| MI_NO_WRITE_FLUSH
;
1927 if ((invalidate_domains
|flush_domains
) &
1928 I915_GEM_DOMAIN_RENDER
)
1929 cmd
&= ~MI_NO_WRITE_FLUSH
;
1930 if (!IS_I965G(dev
)) {
1932 * On the 965, the sampler cache always gets flushed
1933 * and this bit is reserved.
1935 if (invalidate_domains
& I915_GEM_DOMAIN_SAMPLER
)
1936 cmd
|= MI_READ_FLUSH
;
1938 if (invalidate_domains
& I915_GEM_DOMAIN_INSTRUCTION
)
1939 cmd
|= MI_EXE_FLUSH
;
1942 DRM_INFO("%s: queue flush %08x to ring\n", __func__
, cmd
);
1952 * Ensures that all rendering to the object has completed and the object is
1953 * safe to unbind from the GTT or access from the CPU.
1956 i915_gem_object_wait_rendering(struct drm_gem_object
*obj
)
1958 struct drm_device
*dev
= obj
->dev
;
1959 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1962 /* This function only exists to support waiting for existing rendering,
1963 * not for emitting required flushes.
1965 BUG_ON((obj
->write_domain
& I915_GEM_GPU_DOMAINS
) != 0);
1967 /* If there is rendering queued on the buffer being evicted, wait for
1970 if (obj_priv
->active
) {
1972 DRM_INFO("%s: object %p wait for seqno %08x\n",
1973 __func__
, obj
, obj_priv
->last_rendering_seqno
);
1975 ret
= i915_wait_request(dev
, obj_priv
->last_rendering_seqno
);
1984 * Unbinds an object from the GTT aperture.
1987 i915_gem_object_unbind(struct drm_gem_object
*obj
)
1989 struct drm_device
*dev
= obj
->dev
;
1990 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
1994 DRM_INFO("%s:%d %p\n", __func__
, __LINE__
, obj
);
1995 DRM_INFO("gtt_space %p\n", obj_priv
->gtt_space
);
1997 if (obj_priv
->gtt_space
== NULL
)
2000 if (obj_priv
->pin_count
!= 0) {
2001 DRM_ERROR("Attempting to unbind pinned buffer\n");
2005 /* blow away mappings if mapped through GTT */
2006 i915_gem_release_mmap(obj
);
2008 /* Move the object to the CPU domain to ensure that
2009 * any possible CPU writes while it's not in the GTT
2010 * are flushed when we go to remap it. This will
2011 * also ensure that all pending GPU writes are finished
2014 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
2016 if (ret
!= -ERESTARTSYS
)
2017 DRM_ERROR("set_domain failed: %d\n", ret
);
2021 BUG_ON(obj_priv
->active
);
2023 /* release the fence reg _after_ flushing */
2024 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
)
2025 i915_gem_clear_fence_reg(obj
);
2027 if (obj_priv
->agp_mem
!= NULL
) {
2028 drm_unbind_agp(obj_priv
->agp_mem
);
2029 drm_free_agp(obj_priv
->agp_mem
, obj
->size
/ PAGE_SIZE
);
2030 obj_priv
->agp_mem
= NULL
;
2033 i915_gem_object_put_pages(obj
);
2034 BUG_ON(obj_priv
->pages_refcount
);
2036 if (obj_priv
->gtt_space
) {
2037 atomic_dec(&dev
->gtt_count
);
2038 atomic_sub(obj
->size
, &dev
->gtt_memory
);
2040 drm_mm_put_block(obj_priv
->gtt_space
);
2041 obj_priv
->gtt_space
= NULL
;
2044 /* Remove ourselves from the LRU list if present. */
2045 if (!list_empty(&obj_priv
->list
))
2046 list_del_init(&obj_priv
->list
);
2048 if (i915_gem_object_is_purgeable(obj_priv
))
2049 i915_gem_object_truncate(obj
);
2051 trace_i915_gem_object_unbind(obj
);
2056 static struct drm_gem_object
*
2057 i915_gem_find_inactive_object(struct drm_device
*dev
, int min_size
)
2059 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2060 struct drm_i915_gem_object
*obj_priv
;
2061 struct drm_gem_object
*best
= NULL
;
2062 struct drm_gem_object
*first
= NULL
;
2064 /* Try to find the smallest clean object */
2065 list_for_each_entry(obj_priv
, &dev_priv
->mm
.inactive_list
, list
) {
2066 struct drm_gem_object
*obj
= obj_priv
->obj
;
2067 if (obj
->size
>= min_size
) {
2068 if ((!obj_priv
->dirty
||
2069 i915_gem_object_is_purgeable(obj_priv
)) &&
2070 (!best
|| obj
->size
< best
->size
)) {
2072 if (best
->size
== min_size
)
2080 return best
? best
: first
;
2084 i915_gem_evict_everything(struct drm_device
*dev
)
2086 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2091 spin_lock(&dev_priv
->mm
.active_list_lock
);
2092 lists_empty
= (list_empty(&dev_priv
->mm
.inactive_list
) &&
2093 list_empty(&dev_priv
->mm
.flushing_list
) &&
2094 list_empty(&dev_priv
->mm
.active_list
));
2095 spin_unlock(&dev_priv
->mm
.active_list_lock
);
2100 /* Flush everything (on to the inactive lists) and evict */
2101 i915_gem_flush(dev
, I915_GEM_GPU_DOMAINS
, I915_GEM_GPU_DOMAINS
);
2102 seqno
= i915_add_request(dev
, NULL
, I915_GEM_GPU_DOMAINS
);
2106 ret
= i915_wait_request(dev
, seqno
);
2110 BUG_ON(!list_empty(&dev_priv
->mm
.flushing_list
));
2112 ret
= i915_gem_evict_from_inactive_list(dev
);
2116 spin_lock(&dev_priv
->mm
.active_list_lock
);
2117 lists_empty
= (list_empty(&dev_priv
->mm
.inactive_list
) &&
2118 list_empty(&dev_priv
->mm
.flushing_list
) &&
2119 list_empty(&dev_priv
->mm
.active_list
));
2120 spin_unlock(&dev_priv
->mm
.active_list_lock
);
2121 BUG_ON(!lists_empty
);
2127 i915_gem_evict_something(struct drm_device
*dev
, int min_size
)
2129 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2130 struct drm_gem_object
*obj
;
2134 i915_gem_retire_requests(dev
);
2136 /* If there's an inactive buffer available now, grab it
2139 obj
= i915_gem_find_inactive_object(dev
, min_size
);
2141 struct drm_i915_gem_object
*obj_priv
;
2144 DRM_INFO("%s: evicting %p\n", __func__
, obj
);
2146 obj_priv
= obj
->driver_private
;
2147 BUG_ON(obj_priv
->pin_count
!= 0);
2148 BUG_ON(obj_priv
->active
);
2150 /* Wait on the rendering and unbind the buffer. */
2151 return i915_gem_object_unbind(obj
);
2154 /* If we didn't get anything, but the ring is still processing
2155 * things, wait for the next to finish and hopefully leave us
2156 * a buffer to evict.
2158 if (!list_empty(&dev_priv
->mm
.request_list
)) {
2159 struct drm_i915_gem_request
*request
;
2161 request
= list_first_entry(&dev_priv
->mm
.request_list
,
2162 struct drm_i915_gem_request
,
2165 ret
= i915_wait_request(dev
, request
->seqno
);
2172 /* If we didn't have anything on the request list but there
2173 * are buffers awaiting a flush, emit one and try again.
2174 * When we wait on it, those buffers waiting for that flush
2175 * will get moved to inactive.
2177 if (!list_empty(&dev_priv
->mm
.flushing_list
)) {
2178 struct drm_i915_gem_object
*obj_priv
;
2180 /* Find an object that we can immediately reuse */
2181 list_for_each_entry(obj_priv
, &dev_priv
->mm
.flushing_list
, list
) {
2182 obj
= obj_priv
->obj
;
2183 if (obj
->size
>= min_size
)
2195 seqno
= i915_add_request(dev
, NULL
, obj
->write_domain
);
2199 ret
= i915_wait_request(dev
, seqno
);
2207 /* If we didn't do any of the above, there's no single buffer
2208 * large enough to swap out for the new one, so just evict
2209 * everything and start again. (This should be rare.)
2211 if (!list_empty (&dev_priv
->mm
.inactive_list
))
2212 return i915_gem_evict_from_inactive_list(dev
);
2214 return i915_gem_evict_everything(dev
);
2219 i915_gem_object_get_pages(struct drm_gem_object
*obj
,
2222 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2224 struct address_space
*mapping
;
2225 struct inode
*inode
;
2229 if (obj_priv
->pages_refcount
++ != 0)
2232 /* Get the list of pages out of our struct file. They'll be pinned
2233 * at this point until we release them.
2235 page_count
= obj
->size
/ PAGE_SIZE
;
2236 BUG_ON(obj_priv
->pages
!= NULL
);
2237 obj_priv
->pages
= drm_calloc_large(page_count
, sizeof(struct page
*));
2238 if (obj_priv
->pages
== NULL
) {
2239 obj_priv
->pages_refcount
--;
2243 inode
= obj
->filp
->f_path
.dentry
->d_inode
;
2244 mapping
= inode
->i_mapping
;
2245 for (i
= 0; i
< page_count
; i
++) {
2246 page
= read_cache_page_gfp(mapping
, i
,
2247 mapping_gfp_mask (mapping
) |
2251 ret
= PTR_ERR(page
);
2252 i915_gem_object_put_pages(obj
);
2255 obj_priv
->pages
[i
] = page
;
2258 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
)
2259 i915_gem_object_do_bit_17_swizzle(obj
);
2264 static void i965_write_fence_reg(struct drm_i915_fence_reg
*reg
)
2266 struct drm_gem_object
*obj
= reg
->obj
;
2267 struct drm_device
*dev
= obj
->dev
;
2268 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2269 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2270 int regnum
= obj_priv
->fence_reg
;
2273 val
= (uint64_t)((obj_priv
->gtt_offset
+ obj
->size
- 4096) &
2275 val
|= obj_priv
->gtt_offset
& 0xfffff000;
2276 val
|= ((obj_priv
->stride
/ 128) - 1) << I965_FENCE_PITCH_SHIFT
;
2277 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2278 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
2279 val
|= I965_FENCE_REG_VALID
;
2281 I915_WRITE64(FENCE_REG_965_0
+ (regnum
* 8), val
);
2284 static void i915_write_fence_reg(struct drm_i915_fence_reg
*reg
)
2286 struct drm_gem_object
*obj
= reg
->obj
;
2287 struct drm_device
*dev
= obj
->dev
;
2288 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2289 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2290 int regnum
= obj_priv
->fence_reg
;
2292 uint32_t fence_reg
, val
;
2295 if ((obj_priv
->gtt_offset
& ~I915_FENCE_START_MASK
) ||
2296 (obj_priv
->gtt_offset
& (obj
->size
- 1))) {
2297 WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
2298 __func__
, obj_priv
->gtt_offset
, obj
->size
);
2302 if (obj_priv
->tiling_mode
== I915_TILING_Y
&&
2303 HAS_128_BYTE_Y_TILING(dev
))
2308 /* Note: pitch better be a power of two tile widths */
2309 pitch_val
= obj_priv
->stride
/ tile_width
;
2310 pitch_val
= ffs(pitch_val
) - 1;
2312 val
= obj_priv
->gtt_offset
;
2313 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2314 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2315 val
|= I915_FENCE_SIZE_BITS(obj
->size
);
2316 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2317 val
|= I830_FENCE_REG_VALID
;
2320 fence_reg
= FENCE_REG_830_0
+ (regnum
* 4);
2322 fence_reg
= FENCE_REG_945_8
+ ((regnum
- 8) * 4);
2323 I915_WRITE(fence_reg
, val
);
2326 static void i830_write_fence_reg(struct drm_i915_fence_reg
*reg
)
2328 struct drm_gem_object
*obj
= reg
->obj
;
2329 struct drm_device
*dev
= obj
->dev
;
2330 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2331 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2332 int regnum
= obj_priv
->fence_reg
;
2335 uint32_t fence_size_bits
;
2337 if ((obj_priv
->gtt_offset
& ~I830_FENCE_START_MASK
) ||
2338 (obj_priv
->gtt_offset
& (obj
->size
- 1))) {
2339 WARN(1, "%s: object 0x%08x not 512K or size aligned\n",
2340 __func__
, obj_priv
->gtt_offset
);
2344 pitch_val
= obj_priv
->stride
/ 128;
2345 pitch_val
= ffs(pitch_val
) - 1;
2346 WARN_ON(pitch_val
> I830_FENCE_MAX_PITCH_VAL
);
2348 val
= obj_priv
->gtt_offset
;
2349 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2350 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2351 fence_size_bits
= I830_FENCE_SIZE_BITS(obj
->size
);
2352 WARN_ON(fence_size_bits
& ~0x00000f00);
2353 val
|= fence_size_bits
;
2354 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2355 val
|= I830_FENCE_REG_VALID
;
2357 I915_WRITE(FENCE_REG_830_0
+ (regnum
* 4), val
);
2361 * i915_gem_object_get_fence_reg - set up a fence reg for an object
2362 * @obj: object to map through a fence reg
2364 * When mapping objects through the GTT, userspace wants to be able to write
2365 * to them without having to worry about swizzling if the object is tiled.
2367 * This function walks the fence regs looking for a free one for @obj,
2368 * stealing one if it can't find any.
2370 * It then sets up the reg based on the object's properties: address, pitch
2371 * and tiling format.
2374 i915_gem_object_get_fence_reg(struct drm_gem_object
*obj
)
2376 struct drm_device
*dev
= obj
->dev
;
2377 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2378 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2379 struct drm_i915_fence_reg
*reg
= NULL
;
2380 struct drm_i915_gem_object
*old_obj_priv
= NULL
;
2383 /* Just update our place in the LRU if our fence is getting used. */
2384 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
) {
2385 list_move_tail(&obj_priv
->fence_list
, &dev_priv
->mm
.fence_list
);
2389 switch (obj_priv
->tiling_mode
) {
2390 case I915_TILING_NONE
:
2391 WARN(1, "allocating a fence for non-tiled object?\n");
2394 if (!obj_priv
->stride
)
2396 WARN((obj_priv
->stride
& (512 - 1)),
2397 "object 0x%08x is X tiled but has non-512B pitch\n",
2398 obj_priv
->gtt_offset
);
2401 if (!obj_priv
->stride
)
2403 WARN((obj_priv
->stride
& (128 - 1)),
2404 "object 0x%08x is Y tiled but has non-128B pitch\n",
2405 obj_priv
->gtt_offset
);
2409 /* First try to find a free reg */
2411 for (i
= dev_priv
->fence_reg_start
; i
< dev_priv
->num_fence_regs
; i
++) {
2412 reg
= &dev_priv
->fence_regs
[i
];
2416 old_obj_priv
= reg
->obj
->driver_private
;
2417 if (!old_obj_priv
->pin_count
)
2421 /* None available, try to steal one or wait for a user to finish */
2422 if (i
== dev_priv
->num_fence_regs
) {
2423 struct drm_gem_object
*old_obj
= NULL
;
2428 list_for_each_entry(old_obj_priv
, &dev_priv
->mm
.fence_list
,
2430 old_obj
= old_obj_priv
->obj
;
2432 if (old_obj_priv
->pin_count
)
2435 /* Take a reference, as otherwise the wait_rendering
2436 * below may cause the object to get freed out from
2439 drm_gem_object_reference(old_obj
);
2441 /* i915 uses fences for GPU access to tiled buffers */
2442 if (IS_I965G(dev
) || !old_obj_priv
->active
)
2445 /* This brings the object to the head of the LRU if it
2446 * had been written to. The only way this should
2447 * result in us waiting longer than the expected
2448 * optimal amount of time is if there was a
2449 * fence-using buffer later that was read-only.
2451 i915_gem_object_flush_gpu_write_domain(old_obj
);
2452 ret
= i915_gem_object_wait_rendering(old_obj
);
2454 drm_gem_object_unreference(old_obj
);
2462 * Zap this virtual mapping so we can set up a fence again
2463 * for this object next time we need it.
2465 i915_gem_release_mmap(old_obj
);
2467 i
= old_obj_priv
->fence_reg
;
2468 reg
= &dev_priv
->fence_regs
[i
];
2470 old_obj_priv
->fence_reg
= I915_FENCE_REG_NONE
;
2471 list_del_init(&old_obj_priv
->fence_list
);
2473 drm_gem_object_unreference(old_obj
);
2476 obj_priv
->fence_reg
= i
;
2477 list_add_tail(&obj_priv
->fence_list
, &dev_priv
->mm
.fence_list
);
2482 i965_write_fence_reg(reg
);
2483 else if (IS_I9XX(dev
))
2484 i915_write_fence_reg(reg
);
2486 i830_write_fence_reg(reg
);
2488 trace_i915_gem_object_get_fence(obj
, i
, obj_priv
->tiling_mode
);
2494 * i915_gem_clear_fence_reg - clear out fence register info
2495 * @obj: object to clear
2497 * Zeroes out the fence register itself and clears out the associated
2498 * data structures in dev_priv and obj_priv.
2501 i915_gem_clear_fence_reg(struct drm_gem_object
*obj
)
2503 struct drm_device
*dev
= obj
->dev
;
2504 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2505 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2508 I915_WRITE64(FENCE_REG_965_0
+ (obj_priv
->fence_reg
* 8), 0);
2512 if (obj_priv
->fence_reg
< 8)
2513 fence_reg
= FENCE_REG_830_0
+ obj_priv
->fence_reg
* 4;
2515 fence_reg
= FENCE_REG_945_8
+ (obj_priv
->fence_reg
-
2518 I915_WRITE(fence_reg
, 0);
2521 dev_priv
->fence_regs
[obj_priv
->fence_reg
].obj
= NULL
;
2522 obj_priv
->fence_reg
= I915_FENCE_REG_NONE
;
2523 list_del_init(&obj_priv
->fence_list
);
2527 * i915_gem_object_put_fence_reg - waits on outstanding fenced access
2528 * to the buffer to finish, and then resets the fence register.
2529 * @obj: tiled object holding a fence register.
2531 * Zeroes out the fence register itself and clears out the associated
2532 * data structures in dev_priv and obj_priv.
2535 i915_gem_object_put_fence_reg(struct drm_gem_object
*obj
)
2537 struct drm_device
*dev
= obj
->dev
;
2538 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2540 if (obj_priv
->fence_reg
== I915_FENCE_REG_NONE
)
2543 /* On the i915, GPU access to tiled buffers is via a fence,
2544 * therefore we must wait for any outstanding access to complete
2545 * before clearing the fence.
2547 if (!IS_I965G(dev
)) {
2550 i915_gem_object_flush_gpu_write_domain(obj
);
2551 i915_gem_object_flush_gtt_write_domain(obj
);
2552 ret
= i915_gem_object_wait_rendering(obj
);
2557 i915_gem_clear_fence_reg (obj
);
2563 * Finds free space in the GTT aperture and binds the object there.
2566 i915_gem_object_bind_to_gtt(struct drm_gem_object
*obj
, unsigned alignment
)
2568 struct drm_device
*dev
= obj
->dev
;
2569 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2570 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2571 struct drm_mm_node
*free_space
;
2572 gfp_t gfpmask
= __GFP_NORETRY
| __GFP_NOWARN
;
2575 if (obj_priv
->madv
!= I915_MADV_WILLNEED
) {
2576 DRM_ERROR("Attempting to bind a purgeable object\n");
2581 alignment
= i915_gem_get_gtt_alignment(obj
);
2582 if (alignment
& (i915_gem_get_gtt_alignment(obj
) - 1)) {
2583 DRM_ERROR("Invalid object alignment requested %u\n", alignment
);
2588 free_space
= drm_mm_search_free(&dev_priv
->mm
.gtt_space
,
2589 obj
->size
, alignment
, 0);
2590 if (free_space
!= NULL
) {
2591 obj_priv
->gtt_space
= drm_mm_get_block(free_space
, obj
->size
,
2593 if (obj_priv
->gtt_space
!= NULL
) {
2594 obj_priv
->gtt_space
->private = obj
;
2595 obj_priv
->gtt_offset
= obj_priv
->gtt_space
->start
;
2598 if (obj_priv
->gtt_space
== NULL
) {
2599 /* If the gtt is empty and we're still having trouble
2600 * fitting our object in, we're out of memory.
2603 DRM_INFO("%s: GTT full, evicting something\n", __func__
);
2605 ret
= i915_gem_evict_something(dev
, obj
->size
);
2613 DRM_INFO("Binding object of size %zd at 0x%08x\n",
2614 obj
->size
, obj_priv
->gtt_offset
);
2616 ret
= i915_gem_object_get_pages(obj
, gfpmask
);
2618 drm_mm_put_block(obj_priv
->gtt_space
);
2619 obj_priv
->gtt_space
= NULL
;
2621 if (ret
== -ENOMEM
) {
2622 /* first try to clear up some space from the GTT */
2623 ret
= i915_gem_evict_something(dev
, obj
->size
);
2625 /* now try to shrink everyone else */
2640 /* Create an AGP memory structure pointing at our pages, and bind it
2643 obj_priv
->agp_mem
= drm_agp_bind_pages(dev
,
2645 obj
->size
>> PAGE_SHIFT
,
2646 obj_priv
->gtt_offset
,
2647 obj_priv
->agp_type
);
2648 if (obj_priv
->agp_mem
== NULL
) {
2649 i915_gem_object_put_pages(obj
);
2650 drm_mm_put_block(obj_priv
->gtt_space
);
2651 obj_priv
->gtt_space
= NULL
;
2653 ret
= i915_gem_evict_something(dev
, obj
->size
);
2659 atomic_inc(&dev
->gtt_count
);
2660 atomic_add(obj
->size
, &dev
->gtt_memory
);
2662 /* Assert that the object is not currently in any GPU domain. As it
2663 * wasn't in the GTT, there shouldn't be any way it could have been in
2666 BUG_ON(obj
->read_domains
& I915_GEM_GPU_DOMAINS
);
2667 BUG_ON(obj
->write_domain
& I915_GEM_GPU_DOMAINS
);
2669 trace_i915_gem_object_bind(obj
, obj_priv
->gtt_offset
);
2675 i915_gem_clflush_object(struct drm_gem_object
*obj
)
2677 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2679 /* If we don't have a page list set up, then we're not pinned
2680 * to GPU, and we can ignore the cache flush because it'll happen
2681 * again at bind time.
2683 if (obj_priv
->pages
== NULL
)
2686 trace_i915_gem_object_clflush(obj
);
2688 drm_clflush_pages(obj_priv
->pages
, obj
->size
/ PAGE_SIZE
);
2691 /** Flushes any GPU write domain for the object if it's dirty. */
2693 i915_gem_object_flush_gpu_write_domain(struct drm_gem_object
*obj
)
2695 struct drm_device
*dev
= obj
->dev
;
2697 uint32_t old_write_domain
;
2699 if ((obj
->write_domain
& I915_GEM_GPU_DOMAINS
) == 0)
2702 /* Queue the GPU write cache flushing we need. */
2703 old_write_domain
= obj
->write_domain
;
2704 i915_gem_flush(dev
, 0, obj
->write_domain
);
2705 seqno
= i915_add_request(dev
, NULL
, obj
->write_domain
);
2706 BUG_ON(obj
->write_domain
);
2707 i915_gem_object_move_to_active(obj
, seqno
);
2709 trace_i915_gem_object_change_domain(obj
,
2714 /** Flushes the GTT write domain for the object if it's dirty. */
2716 i915_gem_object_flush_gtt_write_domain(struct drm_gem_object
*obj
)
2718 uint32_t old_write_domain
;
2720 if (obj
->write_domain
!= I915_GEM_DOMAIN_GTT
)
2723 /* No actual flushing is required for the GTT write domain. Writes
2724 * to it immediately go to main memory as far as we know, so there's
2725 * no chipset flush. It also doesn't land in render cache.
2727 old_write_domain
= obj
->write_domain
;
2728 obj
->write_domain
= 0;
2730 trace_i915_gem_object_change_domain(obj
,
2735 /** Flushes the CPU write domain for the object if it's dirty. */
2737 i915_gem_object_flush_cpu_write_domain(struct drm_gem_object
*obj
)
2739 struct drm_device
*dev
= obj
->dev
;
2740 uint32_t old_write_domain
;
2742 if (obj
->write_domain
!= I915_GEM_DOMAIN_CPU
)
2745 i915_gem_clflush_object(obj
);
2746 drm_agp_chipset_flush(dev
);
2747 old_write_domain
= obj
->write_domain
;
2748 obj
->write_domain
= 0;
2750 trace_i915_gem_object_change_domain(obj
,
2756 i915_gem_object_flush_write_domain(struct drm_gem_object
*obj
)
2758 switch (obj
->write_domain
) {
2759 case I915_GEM_DOMAIN_GTT
:
2760 i915_gem_object_flush_gtt_write_domain(obj
);
2762 case I915_GEM_DOMAIN_CPU
:
2763 i915_gem_object_flush_cpu_write_domain(obj
);
2766 i915_gem_object_flush_gpu_write_domain(obj
);
2772 * Moves a single object to the GTT read, and possibly write domain.
2774 * This function returns when the move is complete, including waiting on
2778 i915_gem_object_set_to_gtt_domain(struct drm_gem_object
*obj
, int write
)
2780 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2781 uint32_t old_write_domain
, old_read_domains
;
2784 /* Not valid to be called on unbound objects. */
2785 if (obj_priv
->gtt_space
== NULL
)
2788 i915_gem_object_flush_gpu_write_domain(obj
);
2789 /* Wait on any GPU rendering and flushing to occur. */
2790 ret
= i915_gem_object_wait_rendering(obj
);
2794 old_write_domain
= obj
->write_domain
;
2795 old_read_domains
= obj
->read_domains
;
2797 /* If we're writing through the GTT domain, then CPU and GPU caches
2798 * will need to be invalidated at next use.
2801 obj
->read_domains
&= I915_GEM_DOMAIN_GTT
;
2803 i915_gem_object_flush_cpu_write_domain(obj
);
2805 /* It should now be out of any other write domains, and we can update
2806 * the domain values for our changes.
2808 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
2809 obj
->read_domains
|= I915_GEM_DOMAIN_GTT
;
2811 obj
->write_domain
= I915_GEM_DOMAIN_GTT
;
2812 obj_priv
->dirty
= 1;
2815 trace_i915_gem_object_change_domain(obj
,
2823 * Prepare buffer for display plane. Use uninterruptible for possible flush
2824 * wait, as in modesetting process we're not supposed to be interrupted.
2827 i915_gem_object_set_to_display_plane(struct drm_gem_object
*obj
)
2829 struct drm_device
*dev
= obj
->dev
;
2830 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
2831 uint32_t old_write_domain
, old_read_domains
;
2834 /* Not valid to be called on unbound objects. */
2835 if (obj_priv
->gtt_space
== NULL
)
2838 i915_gem_object_flush_gpu_write_domain(obj
);
2840 /* Wait on any GPU rendering and flushing to occur. */
2841 if (obj_priv
->active
) {
2843 DRM_INFO("%s: object %p wait for seqno %08x\n",
2844 __func__
, obj
, obj_priv
->last_rendering_seqno
);
2846 ret
= i915_do_wait_request(dev
, obj_priv
->last_rendering_seqno
, 0);
2851 old_write_domain
= obj
->write_domain
;
2852 old_read_domains
= obj
->read_domains
;
2854 obj
->read_domains
&= I915_GEM_DOMAIN_GTT
;
2856 i915_gem_object_flush_cpu_write_domain(obj
);
2858 /* It should now be out of any other write domains, and we can update
2859 * the domain values for our changes.
2861 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
2862 obj
->read_domains
|= I915_GEM_DOMAIN_GTT
;
2863 obj
->write_domain
= I915_GEM_DOMAIN_GTT
;
2864 obj_priv
->dirty
= 1;
2866 trace_i915_gem_object_change_domain(obj
,
2874 * Moves a single object to the CPU read, and possibly write domain.
2876 * This function returns when the move is complete, including waiting on
2880 i915_gem_object_set_to_cpu_domain(struct drm_gem_object
*obj
, int write
)
2882 uint32_t old_write_domain
, old_read_domains
;
2885 i915_gem_object_flush_gpu_write_domain(obj
);
2886 /* Wait on any GPU rendering and flushing to occur. */
2887 ret
= i915_gem_object_wait_rendering(obj
);
2891 i915_gem_object_flush_gtt_write_domain(obj
);
2893 /* If we have a partially-valid cache of the object in the CPU,
2894 * finish invalidating it and free the per-page flags.
2896 i915_gem_object_set_to_full_cpu_read_domain(obj
);
2898 old_write_domain
= obj
->write_domain
;
2899 old_read_domains
= obj
->read_domains
;
2901 /* Flush the CPU cache if it's still invalid. */
2902 if ((obj
->read_domains
& I915_GEM_DOMAIN_CPU
) == 0) {
2903 i915_gem_clflush_object(obj
);
2905 obj
->read_domains
|= I915_GEM_DOMAIN_CPU
;
2908 /* It should now be out of any other write domains, and we can update
2909 * the domain values for our changes.
2911 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
2913 /* If we're writing through the CPU, then the GPU read domains will
2914 * need to be invalidated at next use.
2917 obj
->read_domains
&= I915_GEM_DOMAIN_CPU
;
2918 obj
->write_domain
= I915_GEM_DOMAIN_CPU
;
2921 trace_i915_gem_object_change_domain(obj
,
2929 * Set the next domain for the specified object. This
2930 * may not actually perform the necessary flushing/invaliding though,
2931 * as that may want to be batched with other set_domain operations
2933 * This is (we hope) the only really tricky part of gem. The goal
2934 * is fairly simple -- track which caches hold bits of the object
2935 * and make sure they remain coherent. A few concrete examples may
2936 * help to explain how it works. For shorthand, we use the notation
2937 * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
2938 * a pair of read and write domain masks.
2940 * Case 1: the batch buffer
2946 * 5. Unmapped from GTT
2949 * Let's take these a step at a time
2952 * Pages allocated from the kernel may still have
2953 * cache contents, so we set them to (CPU, CPU) always.
2954 * 2. Written by CPU (using pwrite)
2955 * The pwrite function calls set_domain (CPU, CPU) and
2956 * this function does nothing (as nothing changes)
2958 * This function asserts that the object is not
2959 * currently in any GPU-based read or write domains
2961 * i915_gem_execbuffer calls set_domain (COMMAND, 0).
2962 * As write_domain is zero, this function adds in the
2963 * current read domains (CPU+COMMAND, 0).
2964 * flush_domains is set to CPU.
2965 * invalidate_domains is set to COMMAND
2966 * clflush is run to get data out of the CPU caches
2967 * then i915_dev_set_domain calls i915_gem_flush to
2968 * emit an MI_FLUSH and drm_agp_chipset_flush
2969 * 5. Unmapped from GTT
2970 * i915_gem_object_unbind calls set_domain (CPU, CPU)
2971 * flush_domains and invalidate_domains end up both zero
2972 * so no flushing/invalidating happens
2976 * Case 2: The shared render buffer
2980 * 3. Read/written by GPU
2981 * 4. set_domain to (CPU,CPU)
2982 * 5. Read/written by CPU
2983 * 6. Read/written by GPU
2986 * Same as last example, (CPU, CPU)
2988 * Nothing changes (assertions find that it is not in the GPU)
2989 * 3. Read/written by GPU
2990 * execbuffer calls set_domain (RENDER, RENDER)
2991 * flush_domains gets CPU
2992 * invalidate_domains gets GPU
2994 * MI_FLUSH and drm_agp_chipset_flush
2995 * 4. set_domain (CPU, CPU)
2996 * flush_domains gets GPU
2997 * invalidate_domains gets CPU
2998 * wait_rendering (obj) to make sure all drawing is complete.
2999 * This will include an MI_FLUSH to get the data from GPU
3001 * clflush (obj) to invalidate the CPU cache
3002 * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
3003 * 5. Read/written by CPU
3004 * cache lines are loaded and dirtied
3005 * 6. Read written by GPU
3006 * Same as last GPU access
3008 * Case 3: The constant buffer
3013 * 4. Updated (written) by CPU again
3022 * flush_domains = CPU
3023 * invalidate_domains = RENDER
3026 * drm_agp_chipset_flush
3027 * 4. Updated (written) by CPU again
3029 * flush_domains = 0 (no previous write domain)
3030 * invalidate_domains = 0 (no new read domains)
3033 * flush_domains = CPU
3034 * invalidate_domains = RENDER
3037 * drm_agp_chipset_flush
3040 i915_gem_object_set_to_gpu_domain(struct drm_gem_object
*obj
)
3042 struct drm_device
*dev
= obj
->dev
;
3043 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
3044 uint32_t invalidate_domains
= 0;
3045 uint32_t flush_domains
= 0;
3046 uint32_t old_read_domains
;
3048 BUG_ON(obj
->pending_read_domains
& I915_GEM_DOMAIN_CPU
);
3049 BUG_ON(obj
->pending_write_domain
== I915_GEM_DOMAIN_CPU
);
3051 intel_mark_busy(dev
, obj
);
3054 DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
3056 obj
->read_domains
, obj
->pending_read_domains
,
3057 obj
->write_domain
, obj
->pending_write_domain
);
3060 * If the object isn't moving to a new write domain,
3061 * let the object stay in multiple read domains
3063 if (obj
->pending_write_domain
== 0)
3064 obj
->pending_read_domains
|= obj
->read_domains
;
3066 obj_priv
->dirty
= 1;
3069 * Flush the current write domain if
3070 * the new read domains don't match. Invalidate
3071 * any read domains which differ from the old
3074 if (obj
->write_domain
&&
3075 obj
->write_domain
!= obj
->pending_read_domains
) {
3076 flush_domains
|= obj
->write_domain
;
3077 invalidate_domains
|=
3078 obj
->pending_read_domains
& ~obj
->write_domain
;
3081 * Invalidate any read caches which may have
3082 * stale data. That is, any new read domains.
3084 invalidate_domains
|= obj
->pending_read_domains
& ~obj
->read_domains
;
3085 if ((flush_domains
| invalidate_domains
) & I915_GEM_DOMAIN_CPU
) {
3087 DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
3088 __func__
, flush_domains
, invalidate_domains
);
3090 i915_gem_clflush_object(obj
);
3093 old_read_domains
= obj
->read_domains
;
3095 /* The actual obj->write_domain will be updated with
3096 * pending_write_domain after we emit the accumulated flush for all
3097 * of our domain changes in execbuffers (which clears objects'
3098 * write_domains). So if we have a current write domain that we
3099 * aren't changing, set pending_write_domain to that.
3101 if (flush_domains
== 0 && obj
->pending_write_domain
== 0)
3102 obj
->pending_write_domain
= obj
->write_domain
;
3103 obj
->read_domains
= obj
->pending_read_domains
;
3105 dev
->invalidate_domains
|= invalidate_domains
;
3106 dev
->flush_domains
|= flush_domains
;
3108 DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n",
3110 obj
->read_domains
, obj
->write_domain
,
3111 dev
->invalidate_domains
, dev
->flush_domains
);
3114 trace_i915_gem_object_change_domain(obj
,
3120 * Moves the object from a partially CPU read to a full one.
3122 * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3123 * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
3126 i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object
*obj
)
3128 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
3130 if (!obj_priv
->page_cpu_valid
)
3133 /* If we're partially in the CPU read domain, finish moving it in.
3135 if (obj
->read_domains
& I915_GEM_DOMAIN_CPU
) {
3138 for (i
= 0; i
<= (obj
->size
- 1) / PAGE_SIZE
; i
++) {
3139 if (obj_priv
->page_cpu_valid
[i
])
3141 drm_clflush_pages(obj_priv
->pages
+ i
, 1);
3145 /* Free the page_cpu_valid mappings which are now stale, whether
3146 * or not we've got I915_GEM_DOMAIN_CPU.
3148 kfree(obj_priv
->page_cpu_valid
);
3149 obj_priv
->page_cpu_valid
= NULL
;
3153 * Set the CPU read domain on a range of the object.
3155 * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3156 * not entirely valid. The page_cpu_valid member of the object flags which
3157 * pages have been flushed, and will be respected by
3158 * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3159 * of the whole object.
3161 * This function returns when the move is complete, including waiting on
3165 i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object
*obj
,
3166 uint64_t offset
, uint64_t size
)
3168 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
3169 uint32_t old_read_domains
;
3172 if (offset
== 0 && size
== obj
->size
)
3173 return i915_gem_object_set_to_cpu_domain(obj
, 0);
3175 i915_gem_object_flush_gpu_write_domain(obj
);
3176 /* Wait on any GPU rendering and flushing to occur. */
3177 ret
= i915_gem_object_wait_rendering(obj
);
3180 i915_gem_object_flush_gtt_write_domain(obj
);
3182 /* If we're already fully in the CPU read domain, we're done. */
3183 if (obj_priv
->page_cpu_valid
== NULL
&&
3184 (obj
->read_domains
& I915_GEM_DOMAIN_CPU
) != 0)
3187 /* Otherwise, create/clear the per-page CPU read domain flag if we're
3188 * newly adding I915_GEM_DOMAIN_CPU
3190 if (obj_priv
->page_cpu_valid
== NULL
) {
3191 obj_priv
->page_cpu_valid
= kzalloc(obj
->size
/ PAGE_SIZE
,
3193 if (obj_priv
->page_cpu_valid
== NULL
)
3195 } else if ((obj
->read_domains
& I915_GEM_DOMAIN_CPU
) == 0)
3196 memset(obj_priv
->page_cpu_valid
, 0, obj
->size
/ PAGE_SIZE
);
3198 /* Flush the cache on any pages that are still invalid from the CPU's
3201 for (i
= offset
/ PAGE_SIZE
; i
<= (offset
+ size
- 1) / PAGE_SIZE
;
3203 if (obj_priv
->page_cpu_valid
[i
])
3206 drm_clflush_pages(obj_priv
->pages
+ i
, 1);
3208 obj_priv
->page_cpu_valid
[i
] = 1;
3211 /* It should now be out of any other write domains, and we can update
3212 * the domain values for our changes.
3214 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
3216 old_read_domains
= obj
->read_domains
;
3217 obj
->read_domains
|= I915_GEM_DOMAIN_CPU
;
3219 trace_i915_gem_object_change_domain(obj
,
3227 * Pin an object to the GTT and evaluate the relocations landing in it.
3230 i915_gem_object_pin_and_relocate(struct drm_gem_object
*obj
,
3231 struct drm_file
*file_priv
,
3232 struct drm_i915_gem_exec_object2
*entry
,
3233 struct drm_i915_gem_relocation_entry
*relocs
)
3235 struct drm_device
*dev
= obj
->dev
;
3236 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3237 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
3239 void __iomem
*reloc_page
;
3242 need_fence
= entry
->flags
& EXEC_OBJECT_NEEDS_FENCE
&&
3243 obj_priv
->tiling_mode
!= I915_TILING_NONE
;
3245 /* Check fence reg constraints and rebind if necessary */
3246 if (need_fence
&& !i915_obj_fenceable(dev
, obj
))
3247 i915_gem_object_unbind(obj
);
3249 /* Choose the GTT offset for our buffer and put it there. */
3250 ret
= i915_gem_object_pin(obj
, (uint32_t) entry
->alignment
);
3255 * Pre-965 chips need a fence register set up in order to
3256 * properly handle blits to/from tiled surfaces.
3259 ret
= i915_gem_object_get_fence_reg(obj
);
3261 if (ret
!= -EBUSY
&& ret
!= -ERESTARTSYS
)
3262 DRM_ERROR("Failure to install fence: %d\n",
3264 i915_gem_object_unpin(obj
);
3269 entry
->offset
= obj_priv
->gtt_offset
;
3271 /* Apply the relocations, using the GTT aperture to avoid cache
3272 * flushing requirements.
3274 for (i
= 0; i
< entry
->relocation_count
; i
++) {
3275 struct drm_i915_gem_relocation_entry
*reloc
= &relocs
[i
];
3276 struct drm_gem_object
*target_obj
;
3277 struct drm_i915_gem_object
*target_obj_priv
;
3278 uint32_t reloc_val
, reloc_offset
;
3279 uint32_t __iomem
*reloc_entry
;
3281 target_obj
= drm_gem_object_lookup(obj
->dev
, file_priv
,
3282 reloc
->target_handle
);
3283 if (target_obj
== NULL
) {
3284 i915_gem_object_unpin(obj
);
3287 target_obj_priv
= target_obj
->driver_private
;
3290 DRM_INFO("%s: obj %p offset %08x target %d "
3291 "read %08x write %08x gtt %08x "
3292 "presumed %08x delta %08x\n",
3295 (int) reloc
->offset
,
3296 (int) reloc
->target_handle
,
3297 (int) reloc
->read_domains
,
3298 (int) reloc
->write_domain
,
3299 (int) target_obj_priv
->gtt_offset
,
3300 (int) reloc
->presumed_offset
,
3304 /* The target buffer should have appeared before us in the
3305 * exec_object list, so it should have a GTT space bound by now.
3307 if (target_obj_priv
->gtt_space
== NULL
) {
3308 DRM_ERROR("No GTT space found for object %d\n",
3309 reloc
->target_handle
);
3310 drm_gem_object_unreference(target_obj
);
3311 i915_gem_object_unpin(obj
);
3315 /* Validate that the target is in a valid r/w GPU domain */
3316 if (reloc
->write_domain
& I915_GEM_DOMAIN_CPU
||
3317 reloc
->read_domains
& I915_GEM_DOMAIN_CPU
) {
3318 DRM_ERROR("reloc with read/write CPU domains: "
3319 "obj %p target %d offset %d "
3320 "read %08x write %08x",
3321 obj
, reloc
->target_handle
,
3322 (int) reloc
->offset
,
3323 reloc
->read_domains
,
3324 reloc
->write_domain
);
3325 drm_gem_object_unreference(target_obj
);
3326 i915_gem_object_unpin(obj
);
3329 if (reloc
->write_domain
&& target_obj
->pending_write_domain
&&
3330 reloc
->write_domain
!= target_obj
->pending_write_domain
) {
3331 DRM_ERROR("Write domain conflict: "
3332 "obj %p target %d offset %d "
3333 "new %08x old %08x\n",
3334 obj
, reloc
->target_handle
,
3335 (int) reloc
->offset
,
3336 reloc
->write_domain
,
3337 target_obj
->pending_write_domain
);
3338 drm_gem_object_unreference(target_obj
);
3339 i915_gem_object_unpin(obj
);
3343 target_obj
->pending_read_domains
|= reloc
->read_domains
;
3344 target_obj
->pending_write_domain
|= reloc
->write_domain
;
3346 /* If the relocation already has the right value in it, no
3347 * more work needs to be done.
3349 if (target_obj_priv
->gtt_offset
== reloc
->presumed_offset
) {
3350 drm_gem_object_unreference(target_obj
);
3354 /* Check that the relocation address is valid... */
3355 if (reloc
->offset
> obj
->size
- 4) {
3356 DRM_ERROR("Relocation beyond object bounds: "
3357 "obj %p target %d offset %d size %d.\n",
3358 obj
, reloc
->target_handle
,
3359 (int) reloc
->offset
, (int) obj
->size
);
3360 drm_gem_object_unreference(target_obj
);
3361 i915_gem_object_unpin(obj
);
3364 if (reloc
->offset
& 3) {
3365 DRM_ERROR("Relocation not 4-byte aligned: "
3366 "obj %p target %d offset %d.\n",
3367 obj
, reloc
->target_handle
,
3368 (int) reloc
->offset
);
3369 drm_gem_object_unreference(target_obj
);
3370 i915_gem_object_unpin(obj
);
3374 /* and points to somewhere within the target object. */
3375 if (reloc
->delta
>= target_obj
->size
) {
3376 DRM_ERROR("Relocation beyond target object bounds: "
3377 "obj %p target %d delta %d size %d.\n",
3378 obj
, reloc
->target_handle
,
3379 (int) reloc
->delta
, (int) target_obj
->size
);
3380 drm_gem_object_unreference(target_obj
);
3381 i915_gem_object_unpin(obj
);
3385 ret
= i915_gem_object_set_to_gtt_domain(obj
, 1);
3387 drm_gem_object_unreference(target_obj
);
3388 i915_gem_object_unpin(obj
);
3392 /* Map the page containing the relocation we're going to
3395 reloc_offset
= obj_priv
->gtt_offset
+ reloc
->offset
;
3396 reloc_page
= io_mapping_map_atomic_wc(dev_priv
->mm
.gtt_mapping
,
3399 reloc_entry
= (uint32_t __iomem
*)(reloc_page
+
3400 (reloc_offset
& (PAGE_SIZE
- 1)));
3401 reloc_val
= target_obj_priv
->gtt_offset
+ reloc
->delta
;
3404 DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n",
3405 obj
, (unsigned int) reloc
->offset
,
3406 readl(reloc_entry
), reloc_val
);
3408 writel(reloc_val
, reloc_entry
);
3409 io_mapping_unmap_atomic(reloc_page
);
3411 /* The updated presumed offset for this entry will be
3412 * copied back out to the user.
3414 reloc
->presumed_offset
= target_obj_priv
->gtt_offset
;
3416 drm_gem_object_unreference(target_obj
);
3421 i915_gem_dump_object(obj
, 128, __func__
, ~0);
3426 /** Dispatch a batchbuffer to the ring
3429 i915_dispatch_gem_execbuffer(struct drm_device
*dev
,
3430 struct drm_i915_gem_execbuffer2
*exec
,
3431 struct drm_clip_rect
*cliprects
,
3432 uint64_t exec_offset
)
3434 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3435 int nbox
= exec
->num_cliprects
;
3437 uint32_t exec_start
, exec_len
;
3440 exec_start
= (uint32_t) exec_offset
+ exec
->batch_start_offset
;
3441 exec_len
= (uint32_t) exec
->batch_len
;
3443 trace_i915_gem_request_submit(dev
, dev_priv
->mm
.next_gem_seqno
+ 1);
3445 count
= nbox
? nbox
: 1;
3447 for (i
= 0; i
< count
; i
++) {
3449 int ret
= i915_emit_box(dev
, cliprects
, i
,
3450 exec
->DR1
, exec
->DR4
);
3455 if (IS_I830(dev
) || IS_845G(dev
)) {
3457 OUT_RING(MI_BATCH_BUFFER
);
3458 OUT_RING(exec_start
| MI_BATCH_NON_SECURE
);
3459 OUT_RING(exec_start
+ exec_len
- 4);
3464 if (IS_I965G(dev
)) {
3465 OUT_RING(MI_BATCH_BUFFER_START
|
3467 MI_BATCH_NON_SECURE_I965
);
3468 OUT_RING(exec_start
);
3470 OUT_RING(MI_BATCH_BUFFER_START
|
3472 OUT_RING(exec_start
| MI_BATCH_NON_SECURE
);
3478 /* XXX breadcrumb */
3482 /* Throttle our rendering by waiting until the ring has completed our requests
3483 * emitted over 20 msec ago.
3485 * Note that if we were to use the current jiffies each time around the loop,
3486 * we wouldn't escape the function with any frames outstanding if the time to
3487 * render a frame was over 20ms.
3489 * This should get us reasonable parallelism between CPU and GPU but also
3490 * relatively low latency when blocking on a particular request to finish.
3493 i915_gem_ring_throttle(struct drm_device
*dev
, struct drm_file
*file_priv
)
3495 struct drm_i915_file_private
*i915_file_priv
= file_priv
->driver_priv
;
3497 unsigned long recent_enough
= jiffies
- msecs_to_jiffies(20);
3499 mutex_lock(&dev
->struct_mutex
);
3500 while (!list_empty(&i915_file_priv
->mm
.request_list
)) {
3501 struct drm_i915_gem_request
*request
;
3503 request
= list_first_entry(&i915_file_priv
->mm
.request_list
,
3504 struct drm_i915_gem_request
,
3507 if (time_after_eq(request
->emitted_jiffies
, recent_enough
))
3510 ret
= i915_wait_request(dev
, request
->seqno
);
3514 mutex_unlock(&dev
->struct_mutex
);
3520 i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object2
*exec_list
,
3521 uint32_t buffer_count
,
3522 struct drm_i915_gem_relocation_entry
**relocs
)
3524 uint32_t reloc_count
= 0, reloc_index
= 0, i
;
3528 for (i
= 0; i
< buffer_count
; i
++) {
3529 if (reloc_count
+ exec_list
[i
].relocation_count
< reloc_count
)
3531 reloc_count
+= exec_list
[i
].relocation_count
;
3534 *relocs
= drm_calloc_large(reloc_count
, sizeof(**relocs
));
3535 if (*relocs
== NULL
) {
3536 DRM_ERROR("failed to alloc relocs, count %d\n", reloc_count
);
3540 for (i
= 0; i
< buffer_count
; i
++) {
3541 struct drm_i915_gem_relocation_entry __user
*user_relocs
;
3543 user_relocs
= (void __user
*)(uintptr_t)exec_list
[i
].relocs_ptr
;
3545 ret
= copy_from_user(&(*relocs
)[reloc_index
],
3547 exec_list
[i
].relocation_count
*
3550 drm_free_large(*relocs
);
3555 reloc_index
+= exec_list
[i
].relocation_count
;
3562 i915_gem_put_relocs_to_user(struct drm_i915_gem_exec_object2
*exec_list
,
3563 uint32_t buffer_count
,
3564 struct drm_i915_gem_relocation_entry
*relocs
)
3566 uint32_t reloc_count
= 0, i
;
3572 for (i
= 0; i
< buffer_count
; i
++) {
3573 struct drm_i915_gem_relocation_entry __user
*user_relocs
;
3576 user_relocs
= (void __user
*)(uintptr_t)exec_list
[i
].relocs_ptr
;
3578 unwritten
= copy_to_user(user_relocs
,
3579 &relocs
[reloc_count
],
3580 exec_list
[i
].relocation_count
*
3588 reloc_count
+= exec_list
[i
].relocation_count
;
3592 drm_free_large(relocs
);
3598 i915_gem_check_execbuffer (struct drm_i915_gem_execbuffer2
*exec
,
3599 uint64_t exec_offset
)
3601 uint32_t exec_start
, exec_len
;
3603 exec_start
= (uint32_t) exec_offset
+ exec
->batch_start_offset
;
3604 exec_len
= (uint32_t) exec
->batch_len
;
3606 if ((exec_start
| exec_len
) & 0x7)
3616 i915_gem_wait_for_pending_flip(struct drm_device
*dev
,
3617 struct drm_gem_object
**object_list
,
3620 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3621 struct drm_i915_gem_object
*obj_priv
;
3626 prepare_to_wait(&dev_priv
->pending_flip_queue
,
3627 &wait
, TASK_INTERRUPTIBLE
);
3628 for (i
= 0; i
< count
; i
++) {
3629 obj_priv
= object_list
[i
]->driver_private
;
3630 if (atomic_read(&obj_priv
->pending_flip
) > 0)
3636 if (!signal_pending(current
)) {
3637 mutex_unlock(&dev
->struct_mutex
);
3639 mutex_lock(&dev
->struct_mutex
);
3645 finish_wait(&dev_priv
->pending_flip_queue
, &wait
);
3651 i915_gem_do_execbuffer(struct drm_device
*dev
, void *data
,
3652 struct drm_file
*file_priv
,
3653 struct drm_i915_gem_execbuffer2
*args
,
3654 struct drm_i915_gem_exec_object2
*exec_list
)
3656 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3657 struct drm_gem_object
**object_list
= NULL
;
3658 struct drm_gem_object
*batch_obj
;
3659 struct drm_i915_gem_object
*obj_priv
;
3660 struct drm_clip_rect
*cliprects
= NULL
;
3661 struct drm_i915_gem_relocation_entry
*relocs
= NULL
;
3662 int ret
= 0, ret2
, i
, pinned
= 0;
3663 uint64_t exec_offset
;
3664 uint32_t seqno
, flush_domains
, reloc_index
;
3665 int pin_tries
, flips
;
3668 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3669 (int) args
->buffers_ptr
, args
->buffer_count
, args
->batch_len
);
3672 if (args
->buffer_count
< 1) {
3673 DRM_ERROR("execbuf with %d buffers\n", args
->buffer_count
);
3676 object_list
= drm_malloc_ab(sizeof(*object_list
), args
->buffer_count
);
3677 if (object_list
== NULL
) {
3678 DRM_ERROR("Failed to allocate object list for %d buffers\n",
3679 args
->buffer_count
);
3684 if (args
->num_cliprects
!= 0) {
3685 cliprects
= kcalloc(args
->num_cliprects
, sizeof(*cliprects
),
3687 if (cliprects
== NULL
) {
3692 ret
= copy_from_user(cliprects
,
3693 (struct drm_clip_rect __user
*)
3694 (uintptr_t) args
->cliprects_ptr
,
3695 sizeof(*cliprects
) * args
->num_cliprects
);
3697 DRM_ERROR("copy %d cliprects failed: %d\n",
3698 args
->num_cliprects
, ret
);
3703 ret
= i915_gem_get_relocs_from_user(exec_list
, args
->buffer_count
,
3708 mutex_lock(&dev
->struct_mutex
);
3710 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3712 if (atomic_read(&dev_priv
->mm
.wedged
)) {
3713 mutex_unlock(&dev
->struct_mutex
);
3718 if (dev_priv
->mm
.suspended
) {
3719 mutex_unlock(&dev
->struct_mutex
);
3724 /* Look up object handles */
3726 for (i
= 0; i
< args
->buffer_count
; i
++) {
3727 object_list
[i
] = drm_gem_object_lookup(dev
, file_priv
,
3728 exec_list
[i
].handle
);
3729 if (object_list
[i
] == NULL
) {
3730 DRM_ERROR("Invalid object handle %d at index %d\n",
3731 exec_list
[i
].handle
, i
);
3732 /* prevent error path from reading uninitialized data */
3733 args
->buffer_count
= i
+ 1;
3738 obj_priv
= object_list
[i
]->driver_private
;
3739 if (obj_priv
->in_execbuffer
) {
3740 DRM_ERROR("Object %p appears more than once in object list\n",
3742 /* prevent error path from reading uninitialized data */
3743 args
->buffer_count
= i
+ 1;
3747 obj_priv
->in_execbuffer
= true;
3748 flips
+= atomic_read(&obj_priv
->pending_flip
);
3752 ret
= i915_gem_wait_for_pending_flip(dev
, object_list
,
3753 args
->buffer_count
);
3758 /* Pin and relocate */
3759 for (pin_tries
= 0; ; pin_tries
++) {
3763 for (i
= 0; i
< args
->buffer_count
; i
++) {
3764 object_list
[i
]->pending_read_domains
= 0;
3765 object_list
[i
]->pending_write_domain
= 0;
3766 ret
= i915_gem_object_pin_and_relocate(object_list
[i
],
3769 &relocs
[reloc_index
]);
3773 reloc_index
+= exec_list
[i
].relocation_count
;
3779 /* error other than GTT full, or we've already tried again */
3780 if (ret
!= -ENOSPC
|| pin_tries
>= 1) {
3781 if (ret
!= -ERESTARTSYS
) {
3782 unsigned long long total_size
= 0;
3783 for (i
= 0; i
< args
->buffer_count
; i
++)
3784 total_size
+= object_list
[i
]->size
;
3785 DRM_ERROR("Failed to pin buffer %d of %d, total %llu bytes: %d\n",
3786 pinned
+1, args
->buffer_count
,
3788 DRM_ERROR("%d objects [%d pinned], "
3789 "%d object bytes [%d pinned], "
3790 "%d/%d gtt bytes\n",
3791 atomic_read(&dev
->object_count
),
3792 atomic_read(&dev
->pin_count
),
3793 atomic_read(&dev
->object_memory
),
3794 atomic_read(&dev
->pin_memory
),
3795 atomic_read(&dev
->gtt_memory
),
3801 /* unpin all of our buffers */
3802 for (i
= 0; i
< pinned
; i
++)
3803 i915_gem_object_unpin(object_list
[i
]);
3806 /* evict everyone we can from the aperture */
3807 ret
= i915_gem_evict_everything(dev
);
3808 if (ret
&& ret
!= -ENOSPC
)
3812 /* Set the pending read domains for the batch buffer to COMMAND */
3813 batch_obj
= object_list
[args
->buffer_count
-1];
3814 if (batch_obj
->pending_write_domain
) {
3815 DRM_ERROR("Attempting to use self-modifying batch buffer\n");
3819 batch_obj
->pending_read_domains
|= I915_GEM_DOMAIN_COMMAND
;
3821 /* Sanity check the batch buffer, prior to moving objects */
3822 exec_offset
= exec_list
[args
->buffer_count
- 1].offset
;
3823 ret
= i915_gem_check_execbuffer (args
, exec_offset
);
3825 DRM_ERROR("execbuf with invalid offset/length\n");
3829 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3831 /* Zero the global flush/invalidate flags. These
3832 * will be modified as new domains are computed
3835 dev
->invalidate_domains
= 0;
3836 dev
->flush_domains
= 0;
3838 for (i
= 0; i
< args
->buffer_count
; i
++) {
3839 struct drm_gem_object
*obj
= object_list
[i
];
3841 /* Compute new gpu domains and update invalidate/flush */
3842 i915_gem_object_set_to_gpu_domain(obj
);
3845 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3847 if (dev
->invalidate_domains
| dev
->flush_domains
) {
3849 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
3851 dev
->invalidate_domains
,
3852 dev
->flush_domains
);
3855 dev
->invalidate_domains
,
3856 dev
->flush_domains
);
3857 if (dev
->flush_domains
& I915_GEM_GPU_DOMAINS
)
3858 (void)i915_add_request(dev
, file_priv
,
3859 dev
->flush_domains
);
3862 for (i
= 0; i
< args
->buffer_count
; i
++) {
3863 struct drm_gem_object
*obj
= object_list
[i
];
3864 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
3865 uint32_t old_write_domain
= obj
->write_domain
;
3867 obj
->write_domain
= obj
->pending_write_domain
;
3868 if (obj
->write_domain
)
3869 list_move_tail(&obj_priv
->gpu_write_list
,
3870 &dev_priv
->mm
.gpu_write_list
);
3872 list_del_init(&obj_priv
->gpu_write_list
);
3874 trace_i915_gem_object_change_domain(obj
,
3879 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3882 for (i
= 0; i
< args
->buffer_count
; i
++) {
3883 i915_gem_object_check_coherency(object_list
[i
],
3884 exec_list
[i
].handle
);
3889 i915_gem_dump_object(batch_obj
,
3895 /* Exec the batchbuffer */
3896 ret
= i915_dispatch_gem_execbuffer(dev
, args
, cliprects
, exec_offset
);
3898 DRM_ERROR("dispatch failed %d\n", ret
);
3903 * Ensure that the commands in the batch buffer are
3904 * finished before the interrupt fires
3906 flush_domains
= i915_retire_commands(dev
);
3908 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3911 * Get a seqno representing the execution of the current buffer,
3912 * which we can wait on. We would like to mitigate these interrupts,
3913 * likely by only creating seqnos occasionally (so that we have
3914 * *some* interrupts representing completion of buffers that we can
3915 * wait on when trying to clear up gtt space).
3917 seqno
= i915_add_request(dev
, file_priv
, flush_domains
);
3919 for (i
= 0; i
< args
->buffer_count
; i
++) {
3920 struct drm_gem_object
*obj
= object_list
[i
];
3922 i915_gem_object_move_to_active(obj
, seqno
);
3924 DRM_INFO("%s: move to exec list %p\n", __func__
, obj
);
3928 i915_dump_lru(dev
, __func__
);
3931 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
3934 for (i
= 0; i
< pinned
; i
++)
3935 i915_gem_object_unpin(object_list
[i
]);
3937 for (i
= 0; i
< args
->buffer_count
; i
++) {
3938 if (object_list
[i
]) {
3939 obj_priv
= object_list
[i
]->driver_private
;
3940 obj_priv
->in_execbuffer
= false;
3942 drm_gem_object_unreference(object_list
[i
]);
3945 mutex_unlock(&dev
->struct_mutex
);
3948 /* Copy the updated relocations out regardless of current error
3949 * state. Failure to update the relocs would mean that the next
3950 * time userland calls execbuf, it would do so with presumed offset
3951 * state that didn't match the actual object state.
3953 ret2
= i915_gem_put_relocs_to_user(exec_list
, args
->buffer_count
,
3956 DRM_ERROR("Failed to copy relocations back out: %d\n", ret2
);
3962 drm_free_large(object_list
);
3969 * Legacy execbuffer just creates an exec2 list from the original exec object
3970 * list array and passes it to the real function.
3973 i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
3974 struct drm_file
*file_priv
)
3976 struct drm_i915_gem_execbuffer
*args
= data
;
3977 struct drm_i915_gem_execbuffer2 exec2
;
3978 struct drm_i915_gem_exec_object
*exec_list
= NULL
;
3979 struct drm_i915_gem_exec_object2
*exec2_list
= NULL
;
3983 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3984 (int) args
->buffers_ptr
, args
->buffer_count
, args
->batch_len
);
3987 if (args
->buffer_count
< 1) {
3988 DRM_ERROR("execbuf with %d buffers\n", args
->buffer_count
);
3992 /* Copy in the exec list from userland */
3993 exec_list
= drm_malloc_ab(sizeof(*exec_list
), args
->buffer_count
);
3994 exec2_list
= drm_malloc_ab(sizeof(*exec2_list
), args
->buffer_count
);
3995 if (exec_list
== NULL
|| exec2_list
== NULL
) {
3996 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
3997 args
->buffer_count
);
3998 drm_free_large(exec_list
);
3999 drm_free_large(exec2_list
);
4002 ret
= copy_from_user(exec_list
,
4003 (struct drm_i915_relocation_entry __user
*)
4004 (uintptr_t) args
->buffers_ptr
,
4005 sizeof(*exec_list
) * args
->buffer_count
);
4007 DRM_ERROR("copy %d exec entries failed %d\n",
4008 args
->buffer_count
, ret
);
4009 drm_free_large(exec_list
);
4010 drm_free_large(exec2_list
);
4014 for (i
= 0; i
< args
->buffer_count
; i
++) {
4015 exec2_list
[i
].handle
= exec_list
[i
].handle
;
4016 exec2_list
[i
].relocation_count
= exec_list
[i
].relocation_count
;
4017 exec2_list
[i
].relocs_ptr
= exec_list
[i
].relocs_ptr
;
4018 exec2_list
[i
].alignment
= exec_list
[i
].alignment
;
4019 exec2_list
[i
].offset
= exec_list
[i
].offset
;
4021 exec2_list
[i
].flags
= EXEC_OBJECT_NEEDS_FENCE
;
4023 exec2_list
[i
].flags
= 0;
4026 exec2
.buffers_ptr
= args
->buffers_ptr
;
4027 exec2
.buffer_count
= args
->buffer_count
;
4028 exec2
.batch_start_offset
= args
->batch_start_offset
;
4029 exec2
.batch_len
= args
->batch_len
;
4030 exec2
.DR1
= args
->DR1
;
4031 exec2
.DR4
= args
->DR4
;
4032 exec2
.num_cliprects
= args
->num_cliprects
;
4033 exec2
.cliprects_ptr
= args
->cliprects_ptr
;
4036 ret
= i915_gem_do_execbuffer(dev
, data
, file_priv
, &exec2
, exec2_list
);
4038 /* Copy the new buffer offsets back to the user's exec list. */
4039 for (i
= 0; i
< args
->buffer_count
; i
++)
4040 exec_list
[i
].offset
= exec2_list
[i
].offset
;
4041 /* ... and back out to userspace */
4042 ret
= copy_to_user((struct drm_i915_relocation_entry __user
*)
4043 (uintptr_t) args
->buffers_ptr
,
4045 sizeof(*exec_list
) * args
->buffer_count
);
4048 DRM_ERROR("failed to copy %d exec entries "
4049 "back to user (%d)\n",
4050 args
->buffer_count
, ret
);
4054 drm_free_large(exec_list
);
4055 drm_free_large(exec2_list
);
4060 i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
4061 struct drm_file
*file_priv
)
4063 struct drm_i915_gem_execbuffer2
*args
= data
;
4064 struct drm_i915_gem_exec_object2
*exec2_list
= NULL
;
4068 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
4069 (int) args
->buffers_ptr
, args
->buffer_count
, args
->batch_len
);
4072 if (args
->buffer_count
< 1) {
4073 DRM_ERROR("execbuf2 with %d buffers\n", args
->buffer_count
);
4077 exec2_list
= drm_malloc_ab(sizeof(*exec2_list
), args
->buffer_count
);
4078 if (exec2_list
== NULL
) {
4079 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
4080 args
->buffer_count
);
4083 ret
= copy_from_user(exec2_list
,
4084 (struct drm_i915_relocation_entry __user
*)
4085 (uintptr_t) args
->buffers_ptr
,
4086 sizeof(*exec2_list
) * args
->buffer_count
);
4088 DRM_ERROR("copy %d exec entries failed %d\n",
4089 args
->buffer_count
, ret
);
4090 drm_free_large(exec2_list
);
4094 ret
= i915_gem_do_execbuffer(dev
, data
, file_priv
, args
, exec2_list
);
4096 /* Copy the new buffer offsets back to the user's exec list. */
4097 ret
= copy_to_user((struct drm_i915_relocation_entry __user
*)
4098 (uintptr_t) args
->buffers_ptr
,
4100 sizeof(*exec2_list
) * args
->buffer_count
);
4103 DRM_ERROR("failed to copy %d exec entries "
4104 "back to user (%d)\n",
4105 args
->buffer_count
, ret
);
4109 drm_free_large(exec2_list
);
4114 i915_gem_object_pin(struct drm_gem_object
*obj
, uint32_t alignment
)
4116 struct drm_device
*dev
= obj
->dev
;
4117 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
4120 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
4121 if (obj_priv
->gtt_space
== NULL
) {
4122 ret
= i915_gem_object_bind_to_gtt(obj
, alignment
);
4127 obj_priv
->pin_count
++;
4129 /* If the object is not active and not pending a flush,
4130 * remove it from the inactive list
4132 if (obj_priv
->pin_count
== 1) {
4133 atomic_inc(&dev
->pin_count
);
4134 atomic_add(obj
->size
, &dev
->pin_memory
);
4135 if (!obj_priv
->active
&&
4136 (obj
->write_domain
& I915_GEM_GPU_DOMAINS
) == 0 &&
4137 !list_empty(&obj_priv
->list
))
4138 list_del_init(&obj_priv
->list
);
4140 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
4146 i915_gem_object_unpin(struct drm_gem_object
*obj
)
4148 struct drm_device
*dev
= obj
->dev
;
4149 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4150 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
4152 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
4153 obj_priv
->pin_count
--;
4154 BUG_ON(obj_priv
->pin_count
< 0);
4155 BUG_ON(obj_priv
->gtt_space
== NULL
);
4157 /* If the object is no longer pinned, and is
4158 * neither active nor being flushed, then stick it on
4161 if (obj_priv
->pin_count
== 0) {
4162 if (!obj_priv
->active
&&
4163 (obj
->write_domain
& I915_GEM_GPU_DOMAINS
) == 0)
4164 list_move_tail(&obj_priv
->list
,
4165 &dev_priv
->mm
.inactive_list
);
4166 atomic_dec(&dev
->pin_count
);
4167 atomic_sub(obj
->size
, &dev
->pin_memory
);
4169 i915_verify_inactive(dev
, __FILE__
, __LINE__
);
4173 i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
4174 struct drm_file
*file_priv
)
4176 struct drm_i915_gem_pin
*args
= data
;
4177 struct drm_gem_object
*obj
;
4178 struct drm_i915_gem_object
*obj_priv
;
4181 mutex_lock(&dev
->struct_mutex
);
4183 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4185 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
4187 mutex_unlock(&dev
->struct_mutex
);
4190 obj_priv
= obj
->driver_private
;
4192 if (obj_priv
->madv
!= I915_MADV_WILLNEED
) {
4193 DRM_ERROR("Attempting to pin a purgeable buffer\n");
4194 drm_gem_object_unreference(obj
);
4195 mutex_unlock(&dev
->struct_mutex
);
4199 if (obj_priv
->pin_filp
!= NULL
&& obj_priv
->pin_filp
!= file_priv
) {
4200 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
4202 drm_gem_object_unreference(obj
);
4203 mutex_unlock(&dev
->struct_mutex
);
4207 obj_priv
->user_pin_count
++;
4208 obj_priv
->pin_filp
= file_priv
;
4209 if (obj_priv
->user_pin_count
== 1) {
4210 ret
= i915_gem_object_pin(obj
, args
->alignment
);
4212 drm_gem_object_unreference(obj
);
4213 mutex_unlock(&dev
->struct_mutex
);
4218 /* XXX - flush the CPU caches for pinned objects
4219 * as the X server doesn't manage domains yet
4221 i915_gem_object_flush_cpu_write_domain(obj
);
4222 args
->offset
= obj_priv
->gtt_offset
;
4223 drm_gem_object_unreference(obj
);
4224 mutex_unlock(&dev
->struct_mutex
);
4230 i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
4231 struct drm_file
*file_priv
)
4233 struct drm_i915_gem_pin
*args
= data
;
4234 struct drm_gem_object
*obj
;
4235 struct drm_i915_gem_object
*obj_priv
;
4237 mutex_lock(&dev
->struct_mutex
);
4239 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4241 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
4243 mutex_unlock(&dev
->struct_mutex
);
4247 obj_priv
= obj
->driver_private
;
4248 if (obj_priv
->pin_filp
!= file_priv
) {
4249 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4251 drm_gem_object_unreference(obj
);
4252 mutex_unlock(&dev
->struct_mutex
);
4255 obj_priv
->user_pin_count
--;
4256 if (obj_priv
->user_pin_count
== 0) {
4257 obj_priv
->pin_filp
= NULL
;
4258 i915_gem_object_unpin(obj
);
4261 drm_gem_object_unreference(obj
);
4262 mutex_unlock(&dev
->struct_mutex
);
4267 i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
4268 struct drm_file
*file_priv
)
4270 struct drm_i915_gem_busy
*args
= data
;
4271 struct drm_gem_object
*obj
;
4272 struct drm_i915_gem_object
*obj_priv
;
4274 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4276 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
4281 mutex_lock(&dev
->struct_mutex
);
4282 /* Update the active list for the hardware's current position.
4283 * Otherwise this only updates on a delayed timer or when irqs are
4284 * actually unmasked, and our working set ends up being larger than
4287 i915_gem_retire_requests(dev
);
4289 obj_priv
= obj
->driver_private
;
4290 /* Don't count being on the flushing list against the object being
4291 * done. Otherwise, a buffer left on the flushing list but not getting
4292 * flushed (because nobody's flushing that domain) won't ever return
4293 * unbusy and get reused by libdrm's bo cache. The other expected
4294 * consumer of this interface, OpenGL's occlusion queries, also specs
4295 * that the objects get unbusy "eventually" without any interference.
4297 args
->busy
= obj_priv
->active
&& obj_priv
->last_rendering_seqno
!= 0;
4299 drm_gem_object_unreference(obj
);
4300 mutex_unlock(&dev
->struct_mutex
);
4305 i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
4306 struct drm_file
*file_priv
)
4308 return i915_gem_ring_throttle(dev
, file_priv
);
4312 i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
4313 struct drm_file
*file_priv
)
4315 struct drm_i915_gem_madvise
*args
= data
;
4316 struct drm_gem_object
*obj
;
4317 struct drm_i915_gem_object
*obj_priv
;
4319 switch (args
->madv
) {
4320 case I915_MADV_DONTNEED
:
4321 case I915_MADV_WILLNEED
:
4327 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4329 DRM_ERROR("Bad handle in i915_gem_madvise_ioctl(): %d\n",
4334 mutex_lock(&dev
->struct_mutex
);
4335 obj_priv
= obj
->driver_private
;
4337 if (obj_priv
->pin_count
) {
4338 drm_gem_object_unreference(obj
);
4339 mutex_unlock(&dev
->struct_mutex
);
4341 DRM_ERROR("Attempted i915_gem_madvise_ioctl() on a pinned object\n");
4345 if (obj_priv
->madv
!= __I915_MADV_PURGED
)
4346 obj_priv
->madv
= args
->madv
;
4348 /* if the object is no longer bound, discard its backing storage */
4349 if (i915_gem_object_is_purgeable(obj_priv
) &&
4350 obj_priv
->gtt_space
== NULL
)
4351 i915_gem_object_truncate(obj
);
4353 args
->retained
= obj_priv
->madv
!= __I915_MADV_PURGED
;
4355 drm_gem_object_unreference(obj
);
4356 mutex_unlock(&dev
->struct_mutex
);
4361 int i915_gem_init_object(struct drm_gem_object
*obj
)
4363 struct drm_i915_gem_object
*obj_priv
;
4365 obj_priv
= kzalloc(sizeof(*obj_priv
), GFP_KERNEL
);
4366 if (obj_priv
== NULL
)
4370 * We've just allocated pages from the kernel,
4371 * so they've just been written by the CPU with
4372 * zeros. They'll need to be clflushed before we
4373 * use them with the GPU.
4375 obj
->write_domain
= I915_GEM_DOMAIN_CPU
;
4376 obj
->read_domains
= I915_GEM_DOMAIN_CPU
;
4378 obj_priv
->agp_type
= AGP_USER_MEMORY
;
4380 obj
->driver_private
= obj_priv
;
4381 obj_priv
->obj
= obj
;
4382 obj_priv
->fence_reg
= I915_FENCE_REG_NONE
;
4383 INIT_LIST_HEAD(&obj_priv
->list
);
4384 INIT_LIST_HEAD(&obj_priv
->gpu_write_list
);
4385 INIT_LIST_HEAD(&obj_priv
->fence_list
);
4386 obj_priv
->madv
= I915_MADV_WILLNEED
;
4388 trace_i915_gem_object_create(obj
);
4393 void i915_gem_free_object(struct drm_gem_object
*obj
)
4395 struct drm_device
*dev
= obj
->dev
;
4396 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
4398 trace_i915_gem_object_destroy(obj
);
4400 while (obj_priv
->pin_count
> 0)
4401 i915_gem_object_unpin(obj
);
4403 if (obj_priv
->phys_obj
)
4404 i915_gem_detach_phys_object(dev
, obj
);
4406 i915_gem_object_unbind(obj
);
4408 if (obj_priv
->mmap_offset
)
4409 i915_gem_free_mmap_offset(obj
);
4411 kfree(obj_priv
->page_cpu_valid
);
4412 kfree(obj_priv
->bit_17
);
4413 kfree(obj
->driver_private
);
4416 /** Unbinds all inactive objects. */
4418 i915_gem_evict_from_inactive_list(struct drm_device
*dev
)
4420 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4422 while (!list_empty(&dev_priv
->mm
.inactive_list
)) {
4423 struct drm_gem_object
*obj
;
4426 obj
= list_first_entry(&dev_priv
->mm
.inactive_list
,
4427 struct drm_i915_gem_object
,
4430 ret
= i915_gem_object_unbind(obj
);
4432 DRM_ERROR("Error unbinding object: %d\n", ret
);
4441 i915_gem_idle(struct drm_device
*dev
)
4443 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4444 uint32_t seqno
, cur_seqno
, last_seqno
;
4447 mutex_lock(&dev
->struct_mutex
);
4449 if (dev_priv
->mm
.suspended
|| dev_priv
->ring
.ring_obj
== NULL
) {
4450 mutex_unlock(&dev
->struct_mutex
);
4454 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4455 * We need to replace this with a semaphore, or something.
4457 dev_priv
->mm
.suspended
= 1;
4458 del_timer(&dev_priv
->hangcheck_timer
);
4460 /* Cancel the retire work handler, wait for it to finish if running
4462 mutex_unlock(&dev
->struct_mutex
);
4463 cancel_delayed_work_sync(&dev_priv
->mm
.retire_work
);
4464 mutex_lock(&dev
->struct_mutex
);
4466 i915_kernel_lost_context(dev
);
4468 /* Flush the GPU along with all non-CPU write domains
4470 i915_gem_flush(dev
, I915_GEM_GPU_DOMAINS
, I915_GEM_GPU_DOMAINS
);
4471 seqno
= i915_add_request(dev
, NULL
, I915_GEM_GPU_DOMAINS
);
4474 mutex_unlock(&dev
->struct_mutex
);
4478 dev_priv
->mm
.waiting_gem_seqno
= seqno
;
4482 cur_seqno
= i915_get_gem_seqno(dev
);
4483 if (i915_seqno_passed(cur_seqno
, seqno
))
4485 if (last_seqno
== cur_seqno
) {
4486 if (stuck
++ > 100) {
4487 DRM_ERROR("hardware wedged\n");
4488 atomic_set(&dev_priv
->mm
.wedged
, 1);
4489 DRM_WAKEUP(&dev_priv
->irq_queue
);
4494 last_seqno
= cur_seqno
;
4496 dev_priv
->mm
.waiting_gem_seqno
= 0;
4498 i915_gem_retire_requests(dev
);
4500 spin_lock(&dev_priv
->mm
.active_list_lock
);
4501 if (!atomic_read(&dev_priv
->mm
.wedged
)) {
4502 /* Active and flushing should now be empty as we've
4503 * waited for a sequence higher than any pending execbuffer
4505 WARN_ON(!list_empty(&dev_priv
->mm
.active_list
));
4506 WARN_ON(!list_empty(&dev_priv
->mm
.flushing_list
));
4507 /* Request should now be empty as we've also waited
4508 * for the last request in the list
4510 WARN_ON(!list_empty(&dev_priv
->mm
.request_list
));
4513 /* Empty the active and flushing lists to inactive. If there's
4514 * anything left at this point, it means that we're wedged and
4515 * nothing good's going to happen by leaving them there. So strip
4516 * the GPU domains and just stuff them onto inactive.
4518 while (!list_empty(&dev_priv
->mm
.active_list
)) {
4519 struct drm_gem_object
*obj
;
4520 uint32_t old_write_domain
;
4522 obj
= list_first_entry(&dev_priv
->mm
.active_list
,
4523 struct drm_i915_gem_object
,
4525 old_write_domain
= obj
->write_domain
;
4526 obj
->write_domain
&= ~I915_GEM_GPU_DOMAINS
;
4527 i915_gem_object_move_to_inactive(obj
);
4529 trace_i915_gem_object_change_domain(obj
,
4533 spin_unlock(&dev_priv
->mm
.active_list_lock
);
4535 while (!list_empty(&dev_priv
->mm
.flushing_list
)) {
4536 struct drm_gem_object
*obj
;
4537 uint32_t old_write_domain
;
4539 obj
= list_first_entry(&dev_priv
->mm
.flushing_list
,
4540 struct drm_i915_gem_object
,
4542 old_write_domain
= obj
->write_domain
;
4543 obj
->write_domain
&= ~I915_GEM_GPU_DOMAINS
;
4544 i915_gem_object_move_to_inactive(obj
);
4546 trace_i915_gem_object_change_domain(obj
,
4552 /* Move all inactive buffers out of the GTT. */
4553 ret
= i915_gem_evict_from_inactive_list(dev
);
4554 WARN_ON(!list_empty(&dev_priv
->mm
.inactive_list
));
4556 mutex_unlock(&dev
->struct_mutex
);
4560 i915_gem_cleanup_ringbuffer(dev
);
4561 mutex_unlock(&dev
->struct_mutex
);
4567 i915_gem_init_hws(struct drm_device
*dev
)
4569 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4570 struct drm_gem_object
*obj
;
4571 struct drm_i915_gem_object
*obj_priv
;
4574 /* If we need a physical address for the status page, it's already
4575 * initialized at driver load time.
4577 if (!I915_NEED_GFX_HWS(dev
))
4580 obj
= drm_gem_object_alloc(dev
, 4096);
4582 DRM_ERROR("Failed to allocate status page\n");
4585 obj_priv
= obj
->driver_private
;
4586 obj_priv
->agp_type
= AGP_USER_CACHED_MEMORY
;
4588 ret
= i915_gem_object_pin(obj
, 4096);
4590 drm_gem_object_unreference(obj
);
4594 dev_priv
->status_gfx_addr
= obj_priv
->gtt_offset
;
4596 dev_priv
->hw_status_page
= kmap(obj_priv
->pages
[0]);
4597 if (dev_priv
->hw_status_page
== NULL
) {
4598 DRM_ERROR("Failed to map status page.\n");
4599 memset(&dev_priv
->hws_map
, 0, sizeof(dev_priv
->hws_map
));
4600 i915_gem_object_unpin(obj
);
4601 drm_gem_object_unreference(obj
);
4604 dev_priv
->hws_obj
= obj
;
4605 memset(dev_priv
->hw_status_page
, 0, PAGE_SIZE
);
4606 I915_WRITE(HWS_PGA
, dev_priv
->status_gfx_addr
);
4607 I915_READ(HWS_PGA
); /* posting read */
4608 DRM_DEBUG_DRIVER("hws offset: 0x%08x\n", dev_priv
->status_gfx_addr
);
4614 i915_gem_cleanup_hws(struct drm_device
*dev
)
4616 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4617 struct drm_gem_object
*obj
;
4618 struct drm_i915_gem_object
*obj_priv
;
4620 if (dev_priv
->hws_obj
== NULL
)
4623 obj
= dev_priv
->hws_obj
;
4624 obj_priv
= obj
->driver_private
;
4626 kunmap(obj_priv
->pages
[0]);
4627 i915_gem_object_unpin(obj
);
4628 drm_gem_object_unreference(obj
);
4629 dev_priv
->hws_obj
= NULL
;
4631 memset(&dev_priv
->hws_map
, 0, sizeof(dev_priv
->hws_map
));
4632 dev_priv
->hw_status_page
= NULL
;
4634 /* Write high address into HWS_PGA when disabling. */
4635 I915_WRITE(HWS_PGA
, 0x1ffff000);
4639 i915_gem_init_ringbuffer(struct drm_device
*dev
)
4641 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4642 struct drm_gem_object
*obj
;
4643 struct drm_i915_gem_object
*obj_priv
;
4644 drm_i915_ring_buffer_t
*ring
= &dev_priv
->ring
;
4648 ret
= i915_gem_init_hws(dev
);
4652 obj
= drm_gem_object_alloc(dev
, 128 * 1024);
4654 DRM_ERROR("Failed to allocate ringbuffer\n");
4655 i915_gem_cleanup_hws(dev
);
4658 obj_priv
= obj
->driver_private
;
4660 ret
= i915_gem_object_pin(obj
, 4096);
4662 drm_gem_object_unreference(obj
);
4663 i915_gem_cleanup_hws(dev
);
4667 /* Set up the kernel mapping for the ring. */
4668 ring
->Size
= obj
->size
;
4670 ring
->map
.offset
= dev
->agp
->base
+ obj_priv
->gtt_offset
;
4671 ring
->map
.size
= obj
->size
;
4673 ring
->map
.flags
= 0;
4676 drm_core_ioremap_wc(&ring
->map
, dev
);
4677 if (ring
->map
.handle
== NULL
) {
4678 DRM_ERROR("Failed to map ringbuffer.\n");
4679 memset(&dev_priv
->ring
, 0, sizeof(dev_priv
->ring
));
4680 i915_gem_object_unpin(obj
);
4681 drm_gem_object_unreference(obj
);
4682 i915_gem_cleanup_hws(dev
);
4685 ring
->ring_obj
= obj
;
4686 ring
->virtual_start
= ring
->map
.handle
;
4688 /* Stop the ring if it's running. */
4689 I915_WRITE(PRB0_CTL
, 0);
4690 I915_WRITE(PRB0_TAIL
, 0);
4691 I915_WRITE(PRB0_HEAD
, 0);
4693 /* Initialize the ring. */
4694 I915_WRITE(PRB0_START
, obj_priv
->gtt_offset
);
4695 head
= I915_READ(PRB0_HEAD
) & HEAD_ADDR
;
4697 /* G45 ring initialization fails to reset head to zero */
4699 DRM_ERROR("Ring head not reset to zero "
4700 "ctl %08x head %08x tail %08x start %08x\n",
4701 I915_READ(PRB0_CTL
),
4702 I915_READ(PRB0_HEAD
),
4703 I915_READ(PRB0_TAIL
),
4704 I915_READ(PRB0_START
));
4705 I915_WRITE(PRB0_HEAD
, 0);
4707 DRM_ERROR("Ring head forced to zero "
4708 "ctl %08x head %08x tail %08x start %08x\n",
4709 I915_READ(PRB0_CTL
),
4710 I915_READ(PRB0_HEAD
),
4711 I915_READ(PRB0_TAIL
),
4712 I915_READ(PRB0_START
));
4715 I915_WRITE(PRB0_CTL
,
4716 ((obj
->size
- 4096) & RING_NR_PAGES
) |
4720 head
= I915_READ(PRB0_HEAD
) & HEAD_ADDR
;
4722 /* If the head is still not zero, the ring is dead */
4724 DRM_ERROR("Ring initialization failed "
4725 "ctl %08x head %08x tail %08x start %08x\n",
4726 I915_READ(PRB0_CTL
),
4727 I915_READ(PRB0_HEAD
),
4728 I915_READ(PRB0_TAIL
),
4729 I915_READ(PRB0_START
));
4733 /* Update our cache of the ring state */
4734 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
4735 i915_kernel_lost_context(dev
);
4737 ring
->head
= I915_READ(PRB0_HEAD
) & HEAD_ADDR
;
4738 ring
->tail
= I915_READ(PRB0_TAIL
) & TAIL_ADDR
;
4739 ring
->space
= ring
->head
- (ring
->tail
+ 8);
4740 if (ring
->space
< 0)
4741 ring
->space
+= ring
->Size
;
4748 i915_gem_cleanup_ringbuffer(struct drm_device
*dev
)
4750 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4752 if (dev_priv
->ring
.ring_obj
== NULL
)
4755 drm_core_ioremapfree(&dev_priv
->ring
.map
, dev
);
4757 i915_gem_object_unpin(dev_priv
->ring
.ring_obj
);
4758 drm_gem_object_unreference(dev_priv
->ring
.ring_obj
);
4759 dev_priv
->ring
.ring_obj
= NULL
;
4760 memset(&dev_priv
->ring
, 0, sizeof(dev_priv
->ring
));
4762 i915_gem_cleanup_hws(dev
);
4766 i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
4767 struct drm_file
*file_priv
)
4769 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4772 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4775 if (atomic_read(&dev_priv
->mm
.wedged
)) {
4776 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4777 atomic_set(&dev_priv
->mm
.wedged
, 0);
4780 mutex_lock(&dev
->struct_mutex
);
4781 dev_priv
->mm
.suspended
= 0;
4783 ret
= i915_gem_init_ringbuffer(dev
);
4785 mutex_unlock(&dev
->struct_mutex
);
4789 spin_lock(&dev_priv
->mm
.active_list_lock
);
4790 BUG_ON(!list_empty(&dev_priv
->mm
.active_list
));
4791 spin_unlock(&dev_priv
->mm
.active_list_lock
);
4793 BUG_ON(!list_empty(&dev_priv
->mm
.flushing_list
));
4794 BUG_ON(!list_empty(&dev_priv
->mm
.inactive_list
));
4795 BUG_ON(!list_empty(&dev_priv
->mm
.request_list
));
4796 mutex_unlock(&dev
->struct_mutex
);
4798 drm_irq_install(dev
);
4804 i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
4805 struct drm_file
*file_priv
)
4807 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4810 drm_irq_uninstall(dev
);
4811 return i915_gem_idle(dev
);
4815 i915_gem_lastclose(struct drm_device
*dev
)
4819 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4822 ret
= i915_gem_idle(dev
);
4824 DRM_ERROR("failed to idle hardware: %d\n", ret
);
4828 i915_gem_load(struct drm_device
*dev
)
4831 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4833 spin_lock_init(&dev_priv
->mm
.active_list_lock
);
4834 INIT_LIST_HEAD(&dev_priv
->mm
.active_list
);
4835 INIT_LIST_HEAD(&dev_priv
->mm
.flushing_list
);
4836 INIT_LIST_HEAD(&dev_priv
->mm
.gpu_write_list
);
4837 INIT_LIST_HEAD(&dev_priv
->mm
.inactive_list
);
4838 INIT_LIST_HEAD(&dev_priv
->mm
.request_list
);
4839 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
4840 INIT_DELAYED_WORK(&dev_priv
->mm
.retire_work
,
4841 i915_gem_retire_work_handler
);
4842 dev_priv
->mm
.next_gem_seqno
= 1;
4844 spin_lock(&shrink_list_lock
);
4845 list_add(&dev_priv
->mm
.shrink_list
, &shrink_list
);
4846 spin_unlock(&shrink_list_lock
);
4848 /* Old X drivers will take 0-2 for front, back, depth buffers */
4849 dev_priv
->fence_reg_start
= 3;
4851 if (IS_I965G(dev
) || IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
4852 dev_priv
->num_fence_regs
= 16;
4854 dev_priv
->num_fence_regs
= 8;
4856 /* Initialize fence registers to zero */
4857 if (IS_I965G(dev
)) {
4858 for (i
= 0; i
< 16; i
++)
4859 I915_WRITE64(FENCE_REG_965_0
+ (i
* 8), 0);
4861 for (i
= 0; i
< 8; i
++)
4862 I915_WRITE(FENCE_REG_830_0
+ (i
* 4), 0);
4863 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
4864 for (i
= 0; i
< 8; i
++)
4865 I915_WRITE(FENCE_REG_945_8
+ (i
* 4), 0);
4867 i915_gem_detect_bit_6_swizzle(dev
);
4868 init_waitqueue_head(&dev_priv
->pending_flip_queue
);
4872 * Create a physically contiguous memory object for this object
4873 * e.g. for cursor + overlay regs
4875 int i915_gem_init_phys_object(struct drm_device
*dev
,
4878 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4879 struct drm_i915_gem_phys_object
*phys_obj
;
4882 if (dev_priv
->mm
.phys_objs
[id
- 1] || !size
)
4885 phys_obj
= kzalloc(sizeof(struct drm_i915_gem_phys_object
), GFP_KERNEL
);
4891 phys_obj
->handle
= drm_pci_alloc(dev
, size
, 0);
4892 if (!phys_obj
->handle
) {
4897 set_memory_wc((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
4900 dev_priv
->mm
.phys_objs
[id
- 1] = phys_obj
;
4908 void i915_gem_free_phys_object(struct drm_device
*dev
, int id
)
4910 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4911 struct drm_i915_gem_phys_object
*phys_obj
;
4913 if (!dev_priv
->mm
.phys_objs
[id
- 1])
4916 phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
4917 if (phys_obj
->cur_obj
) {
4918 i915_gem_detach_phys_object(dev
, phys_obj
->cur_obj
);
4922 set_memory_wb((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
4924 drm_pci_free(dev
, phys_obj
->handle
);
4926 dev_priv
->mm
.phys_objs
[id
- 1] = NULL
;
4929 void i915_gem_free_all_phys_object(struct drm_device
*dev
)
4933 for (i
= I915_GEM_PHYS_CURSOR_0
; i
<= I915_MAX_PHYS_OBJECT
; i
++)
4934 i915_gem_free_phys_object(dev
, i
);
4937 void i915_gem_detach_phys_object(struct drm_device
*dev
,
4938 struct drm_gem_object
*obj
)
4940 struct drm_i915_gem_object
*obj_priv
;
4945 obj_priv
= obj
->driver_private
;
4946 if (!obj_priv
->phys_obj
)
4949 ret
= i915_gem_object_get_pages(obj
, 0);
4953 page_count
= obj
->size
/ PAGE_SIZE
;
4955 for (i
= 0; i
< page_count
; i
++) {
4956 char *dst
= kmap_atomic(obj_priv
->pages
[i
], KM_USER0
);
4957 char *src
= obj_priv
->phys_obj
->handle
->vaddr
+ (i
* PAGE_SIZE
);
4959 memcpy(dst
, src
, PAGE_SIZE
);
4960 kunmap_atomic(dst
, KM_USER0
);
4962 drm_clflush_pages(obj_priv
->pages
, page_count
);
4963 drm_agp_chipset_flush(dev
);
4965 i915_gem_object_put_pages(obj
);
4967 obj_priv
->phys_obj
->cur_obj
= NULL
;
4968 obj_priv
->phys_obj
= NULL
;
4972 i915_gem_attach_phys_object(struct drm_device
*dev
,
4973 struct drm_gem_object
*obj
, int id
)
4975 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4976 struct drm_i915_gem_object
*obj_priv
;
4981 if (id
> I915_MAX_PHYS_OBJECT
)
4984 obj_priv
= obj
->driver_private
;
4986 if (obj_priv
->phys_obj
) {
4987 if (obj_priv
->phys_obj
->id
== id
)
4989 i915_gem_detach_phys_object(dev
, obj
);
4993 /* create a new object */
4994 if (!dev_priv
->mm
.phys_objs
[id
- 1]) {
4995 ret
= i915_gem_init_phys_object(dev
, id
,
4998 DRM_ERROR("failed to init phys object %d size: %zu\n", id
, obj
->size
);
5003 /* bind to the object */
5004 obj_priv
->phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
5005 obj_priv
->phys_obj
->cur_obj
= obj
;
5007 ret
= i915_gem_object_get_pages(obj
, 0);
5009 DRM_ERROR("failed to get page list\n");
5013 page_count
= obj
->size
/ PAGE_SIZE
;
5015 for (i
= 0; i
< page_count
; i
++) {
5016 char *src
= kmap_atomic(obj_priv
->pages
[i
], KM_USER0
);
5017 char *dst
= obj_priv
->phys_obj
->handle
->vaddr
+ (i
* PAGE_SIZE
);
5019 memcpy(dst
, src
, PAGE_SIZE
);
5020 kunmap_atomic(src
, KM_USER0
);
5023 i915_gem_object_put_pages(obj
);
5031 i915_gem_phys_pwrite(struct drm_device
*dev
, struct drm_gem_object
*obj
,
5032 struct drm_i915_gem_pwrite
*args
,
5033 struct drm_file
*file_priv
)
5035 struct drm_i915_gem_object
*obj_priv
= obj
->driver_private
;
5038 char __user
*user_data
;
5040 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
5041 obj_addr
= obj_priv
->phys_obj
->handle
->vaddr
+ args
->offset
;
5043 DRM_DEBUG_DRIVER("obj_addr %p, %lld\n", obj_addr
, args
->size
);
5044 ret
= copy_from_user(obj_addr
, user_data
, args
->size
);
5048 drm_agp_chipset_flush(dev
);
5052 void i915_gem_release(struct drm_device
* dev
, struct drm_file
*file_priv
)
5054 struct drm_i915_file_private
*i915_file_priv
= file_priv
->driver_priv
;
5056 /* Clean up our request list when the client is going away, so that
5057 * later retire_requests won't dereference our soon-to-be-gone
5060 mutex_lock(&dev
->struct_mutex
);
5061 while (!list_empty(&i915_file_priv
->mm
.request_list
))
5062 list_del_init(i915_file_priv
->mm
.request_list
.next
);
5063 mutex_unlock(&dev
->struct_mutex
);
5067 i915_gem_shrink(int nr_to_scan
, gfp_t gfp_mask
)
5069 drm_i915_private_t
*dev_priv
, *next_dev
;
5070 struct drm_i915_gem_object
*obj_priv
, *next_obj
;
5072 int would_deadlock
= 1;
5074 /* "fast-path" to count number of available objects */
5075 if (nr_to_scan
== 0) {
5076 spin_lock(&shrink_list_lock
);
5077 list_for_each_entry(dev_priv
, &shrink_list
, mm
.shrink_list
) {
5078 struct drm_device
*dev
= dev_priv
->dev
;
5080 if (mutex_trylock(&dev
->struct_mutex
)) {
5081 list_for_each_entry(obj_priv
,
5082 &dev_priv
->mm
.inactive_list
,
5085 mutex_unlock(&dev
->struct_mutex
);
5088 spin_unlock(&shrink_list_lock
);
5090 return (cnt
/ 100) * sysctl_vfs_cache_pressure
;
5093 spin_lock(&shrink_list_lock
);
5095 /* first scan for clean buffers */
5096 list_for_each_entry_safe(dev_priv
, next_dev
,
5097 &shrink_list
, mm
.shrink_list
) {
5098 struct drm_device
*dev
= dev_priv
->dev
;
5100 if (! mutex_trylock(&dev
->struct_mutex
))
5103 spin_unlock(&shrink_list_lock
);
5105 i915_gem_retire_requests(dev
);
5107 list_for_each_entry_safe(obj_priv
, next_obj
,
5108 &dev_priv
->mm
.inactive_list
,
5110 if (i915_gem_object_is_purgeable(obj_priv
)) {
5111 i915_gem_object_unbind(obj_priv
->obj
);
5112 if (--nr_to_scan
<= 0)
5117 spin_lock(&shrink_list_lock
);
5118 mutex_unlock(&dev
->struct_mutex
);
5122 if (nr_to_scan
<= 0)
5126 /* second pass, evict/count anything still on the inactive list */
5127 list_for_each_entry_safe(dev_priv
, next_dev
,
5128 &shrink_list
, mm
.shrink_list
) {
5129 struct drm_device
*dev
= dev_priv
->dev
;
5131 if (! mutex_trylock(&dev
->struct_mutex
))
5134 spin_unlock(&shrink_list_lock
);
5136 list_for_each_entry_safe(obj_priv
, next_obj
,
5137 &dev_priv
->mm
.inactive_list
,
5139 if (nr_to_scan
> 0) {
5140 i915_gem_object_unbind(obj_priv
->obj
);
5146 spin_lock(&shrink_list_lock
);
5147 mutex_unlock(&dev
->struct_mutex
);
5152 spin_unlock(&shrink_list_lock
);
5157 return (cnt
/ 100) * sysctl_vfs_cache_pressure
;
5162 static struct shrinker shrinker
= {
5163 .shrink
= i915_gem_shrink
,
5164 .seeks
= DEFAULT_SEEKS
,
5168 i915_gem_shrinker_init(void)
5170 register_shrinker(&shrinker
);
5174 i915_gem_shrinker_exit(void)
5176 unregister_shrinker(&shrinker
);