2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/slab.h>
35 #include <linux/swap.h>
36 #include <linux/pci.h>
38 struct change_domains
{
39 uint32_t invalidate_domains
;
40 uint32_t flush_domains
;
44 static uint32_t i915_gem_get_gtt_alignment(struct drm_i915_gem_object
*obj_priv
);
45 static uint32_t i915_gem_get_gtt_size(struct drm_i915_gem_object
*obj_priv
);
47 static int i915_gem_object_flush_gpu_write_domain(struct drm_gem_object
*obj
,
49 static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object
*obj
);
50 static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object
*obj
);
51 static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object
*obj
,
53 static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object
*obj
,
56 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object
*obj
);
57 static int i915_gem_object_wait_rendering(struct drm_gem_object
*obj
,
59 static int i915_gem_object_bind_to_gtt(struct drm_gem_object
*obj
,
61 bool map_and_fenceable
);
62 static void i915_gem_clear_fence_reg(struct drm_gem_object
*obj
);
63 static int i915_gem_phys_pwrite(struct drm_device
*dev
, struct drm_gem_object
*obj
,
64 struct drm_i915_gem_pwrite
*args
,
65 struct drm_file
*file_priv
);
66 static void i915_gem_free_object_tail(struct drm_gem_object
*obj
);
68 static int i915_gem_inactive_shrink(struct shrinker
*shrinker
,
73 /* some bookkeeping */
74 static void i915_gem_info_add_obj(struct drm_i915_private
*dev_priv
,
77 dev_priv
->mm
.object_count
++;
78 dev_priv
->mm
.object_memory
+= size
;
81 static void i915_gem_info_remove_obj(struct drm_i915_private
*dev_priv
,
84 dev_priv
->mm
.object_count
--;
85 dev_priv
->mm
.object_memory
-= size
;
88 static void i915_gem_info_add_gtt(struct drm_i915_private
*dev_priv
,
89 struct drm_i915_gem_object
*obj
)
91 dev_priv
->mm
.gtt_count
++;
92 dev_priv
->mm
.gtt_memory
+= obj
->gtt_space
->size
;
93 if (obj
->gtt_offset
< dev_priv
->mm
.gtt_mappable_end
) {
94 dev_priv
->mm
.mappable_gtt_used
+=
95 min_t(size_t, obj
->gtt_space
->size
,
96 dev_priv
->mm
.gtt_mappable_end
- obj
->gtt_offset
);
98 list_add_tail(&obj
->gtt_list
, &dev_priv
->mm
.gtt_list
);
101 static void i915_gem_info_remove_gtt(struct drm_i915_private
*dev_priv
,
102 struct drm_i915_gem_object
*obj
)
104 dev_priv
->mm
.gtt_count
--;
105 dev_priv
->mm
.gtt_memory
-= obj
->gtt_space
->size
;
106 if (obj
->gtt_offset
< dev_priv
->mm
.gtt_mappable_end
) {
107 dev_priv
->mm
.mappable_gtt_used
-=
108 min_t(size_t, obj
->gtt_space
->size
,
109 dev_priv
->mm
.gtt_mappable_end
- obj
->gtt_offset
);
111 list_del_init(&obj
->gtt_list
);
115 * Update the mappable working set counters. Call _only_ when there is a change
116 * in one of (pin|fault)_mappable and update *_mappable _before_ calling.
117 * @mappable: new state the changed mappable flag (either pin_ or fault_).
120 i915_gem_info_update_mappable(struct drm_i915_private
*dev_priv
,
121 struct drm_i915_gem_object
*obj
,
125 if (obj
->pin_mappable
&& obj
->fault_mappable
)
126 /* Combined state was already mappable. */
128 dev_priv
->mm
.gtt_mappable_count
++;
129 dev_priv
->mm
.gtt_mappable_memory
+= obj
->gtt_space
->size
;
131 if (obj
->pin_mappable
|| obj
->fault_mappable
)
132 /* Combined state still mappable. */
134 dev_priv
->mm
.gtt_mappable_count
--;
135 dev_priv
->mm
.gtt_mappable_memory
-= obj
->gtt_space
->size
;
139 static void i915_gem_info_add_pin(struct drm_i915_private
*dev_priv
,
140 struct drm_i915_gem_object
*obj
,
143 dev_priv
->mm
.pin_count
++;
144 dev_priv
->mm
.pin_memory
+= obj
->gtt_space
->size
;
146 obj
->pin_mappable
= true;
147 i915_gem_info_update_mappable(dev_priv
, obj
, true);
151 static void i915_gem_info_remove_pin(struct drm_i915_private
*dev_priv
,
152 struct drm_i915_gem_object
*obj
)
154 dev_priv
->mm
.pin_count
--;
155 dev_priv
->mm
.pin_memory
-= obj
->gtt_space
->size
;
156 if (obj
->pin_mappable
) {
157 obj
->pin_mappable
= false;
158 i915_gem_info_update_mappable(dev_priv
, obj
, false);
163 i915_gem_check_is_wedged(struct drm_device
*dev
)
165 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
166 struct completion
*x
= &dev_priv
->error_completion
;
170 if (!atomic_read(&dev_priv
->mm
.wedged
))
173 ret
= wait_for_completion_interruptible(x
);
177 /* Success, we reset the GPU! */
178 if (!atomic_read(&dev_priv
->mm
.wedged
))
181 /* GPU is hung, bump the completion count to account for
182 * the token we just consumed so that we never hit zero and
183 * end up waiting upon a subsequent completion event that
186 spin_lock_irqsave(&x
->wait
.lock
, flags
);
188 spin_unlock_irqrestore(&x
->wait
.lock
, flags
);
192 static int i915_mutex_lock_interruptible(struct drm_device
*dev
)
194 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
197 ret
= i915_gem_check_is_wedged(dev
);
201 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
205 if (atomic_read(&dev_priv
->mm
.wedged
)) {
206 mutex_unlock(&dev
->struct_mutex
);
210 WARN_ON(i915_verify_lists(dev
));
215 i915_gem_object_is_inactive(struct drm_i915_gem_object
*obj_priv
)
217 return obj_priv
->gtt_space
&&
219 obj_priv
->pin_count
== 0;
222 int i915_gem_do_init(struct drm_device
*dev
,
224 unsigned long mappable_end
,
227 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
230 (start
& (PAGE_SIZE
- 1)) != 0 ||
231 (end
& (PAGE_SIZE
- 1)) != 0) {
235 drm_mm_init(&dev_priv
->mm
.gtt_space
, start
,
238 dev_priv
->mm
.gtt_total
= end
- start
;
239 dev_priv
->mm
.mappable_gtt_total
= min(end
, mappable_end
) - start
;
240 dev_priv
->mm
.gtt_mappable_end
= mappable_end
;
246 i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
247 struct drm_file
*file_priv
)
249 struct drm_i915_gem_init
*args
= data
;
252 mutex_lock(&dev
->struct_mutex
);
253 ret
= i915_gem_do_init(dev
, args
->gtt_start
, args
->gtt_end
, args
->gtt_end
);
254 mutex_unlock(&dev
->struct_mutex
);
260 i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
261 struct drm_file
*file_priv
)
263 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
264 struct drm_i915_gem_get_aperture
*args
= data
;
266 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
269 mutex_lock(&dev
->struct_mutex
);
270 args
->aper_size
= dev_priv
->mm
.gtt_total
;
271 args
->aper_available_size
= args
->aper_size
- dev_priv
->mm
.pin_memory
;
272 mutex_unlock(&dev
->struct_mutex
);
279 * Creates a new mm object and returns a handle to it.
282 i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
283 struct drm_file
*file_priv
)
285 struct drm_i915_gem_create
*args
= data
;
286 struct drm_gem_object
*obj
;
290 args
->size
= roundup(args
->size
, PAGE_SIZE
);
292 /* Allocate the new object */
293 obj
= i915_gem_alloc_object(dev
, args
->size
);
297 ret
= drm_gem_handle_create(file_priv
, obj
, &handle
);
299 drm_gem_object_release(obj
);
300 i915_gem_info_remove_obj(dev
->dev_private
, obj
->size
);
305 /* drop reference from allocate - handle holds it now */
306 drm_gem_object_unreference(obj
);
307 trace_i915_gem_object_create(obj
);
309 args
->handle
= handle
;
313 static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object
*obj
)
315 drm_i915_private_t
*dev_priv
= obj
->dev
->dev_private
;
316 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
318 return dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_9_10_17
&&
319 obj_priv
->tiling_mode
!= I915_TILING_NONE
;
323 slow_shmem_copy(struct page
*dst_page
,
325 struct page
*src_page
,
329 char *dst_vaddr
, *src_vaddr
;
331 dst_vaddr
= kmap(dst_page
);
332 src_vaddr
= kmap(src_page
);
334 memcpy(dst_vaddr
+ dst_offset
, src_vaddr
+ src_offset
, length
);
341 slow_shmem_bit17_copy(struct page
*gpu_page
,
343 struct page
*cpu_page
,
348 char *gpu_vaddr
, *cpu_vaddr
;
350 /* Use the unswizzled path if this page isn't affected. */
351 if ((page_to_phys(gpu_page
) & (1 << 17)) == 0) {
353 return slow_shmem_copy(cpu_page
, cpu_offset
,
354 gpu_page
, gpu_offset
, length
);
356 return slow_shmem_copy(gpu_page
, gpu_offset
,
357 cpu_page
, cpu_offset
, length
);
360 gpu_vaddr
= kmap(gpu_page
);
361 cpu_vaddr
= kmap(cpu_page
);
363 /* Copy the data, XORing A6 with A17 (1). The user already knows he's
364 * XORing with the other bits (A9 for Y, A9 and A10 for X)
367 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
368 int this_length
= min(cacheline_end
- gpu_offset
, length
);
369 int swizzled_gpu_offset
= gpu_offset
^ 64;
372 memcpy(cpu_vaddr
+ cpu_offset
,
373 gpu_vaddr
+ swizzled_gpu_offset
,
376 memcpy(gpu_vaddr
+ swizzled_gpu_offset
,
377 cpu_vaddr
+ cpu_offset
,
380 cpu_offset
+= this_length
;
381 gpu_offset
+= this_length
;
382 length
-= this_length
;
390 * This is the fast shmem pread path, which attempts to copy_from_user directly
391 * from the backing pages of the object to the user's address space. On a
392 * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
395 i915_gem_shmem_pread_fast(struct drm_device
*dev
, struct drm_gem_object
*obj
,
396 struct drm_i915_gem_pread
*args
,
397 struct drm_file
*file_priv
)
399 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
400 struct address_space
*mapping
= obj
->filp
->f_path
.dentry
->d_inode
->i_mapping
;
403 char __user
*user_data
;
404 int page_offset
, page_length
;
406 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
409 obj_priv
= to_intel_bo(obj
);
410 offset
= args
->offset
;
417 /* Operation in this page
419 * page_offset = offset within page
420 * page_length = bytes to copy for this page
422 page_offset
= offset
& (PAGE_SIZE
-1);
423 page_length
= remain
;
424 if ((page_offset
+ remain
) > PAGE_SIZE
)
425 page_length
= PAGE_SIZE
- page_offset
;
427 page
= read_cache_page_gfp(mapping
, offset
>> PAGE_SHIFT
,
428 GFP_HIGHUSER
| __GFP_RECLAIMABLE
);
430 return PTR_ERR(page
);
432 vaddr
= kmap_atomic(page
);
433 ret
= __copy_to_user_inatomic(user_data
,
436 kunmap_atomic(vaddr
);
438 mark_page_accessed(page
);
439 page_cache_release(page
);
443 remain
-= page_length
;
444 user_data
+= page_length
;
445 offset
+= page_length
;
452 * This is the fallback shmem pread path, which allocates temporary storage
453 * in kernel space to copy_to_user into outside of the struct_mutex, so we
454 * can copy out of the object's backing pages while holding the struct mutex
455 * and not take page faults.
458 i915_gem_shmem_pread_slow(struct drm_device
*dev
, struct drm_gem_object
*obj
,
459 struct drm_i915_gem_pread
*args
,
460 struct drm_file
*file_priv
)
462 struct address_space
*mapping
= obj
->filp
->f_path
.dentry
->d_inode
->i_mapping
;
463 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
464 struct mm_struct
*mm
= current
->mm
;
465 struct page
**user_pages
;
467 loff_t offset
, pinned_pages
, i
;
468 loff_t first_data_page
, last_data_page
, num_pages
;
469 int shmem_page_offset
;
470 int data_page_index
, data_page_offset
;
473 uint64_t data_ptr
= args
->data_ptr
;
474 int do_bit17_swizzling
;
478 /* Pin the user pages containing the data. We can't fault while
479 * holding the struct mutex, yet we want to hold it while
480 * dereferencing the user data.
482 first_data_page
= data_ptr
/ PAGE_SIZE
;
483 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
484 num_pages
= last_data_page
- first_data_page
+ 1;
486 user_pages
= drm_malloc_ab(num_pages
, sizeof(struct page
*));
487 if (user_pages
== NULL
)
490 mutex_unlock(&dev
->struct_mutex
);
491 down_read(&mm
->mmap_sem
);
492 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
493 num_pages
, 1, 0, user_pages
, NULL
);
494 up_read(&mm
->mmap_sem
);
495 mutex_lock(&dev
->struct_mutex
);
496 if (pinned_pages
< num_pages
) {
501 ret
= i915_gem_object_set_cpu_read_domain_range(obj
,
507 do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
509 obj_priv
= to_intel_bo(obj
);
510 offset
= args
->offset
;
515 /* Operation in this page
517 * shmem_page_offset = offset within page in shmem file
518 * data_page_index = page number in get_user_pages return
519 * data_page_offset = offset with data_page_index page.
520 * page_length = bytes to copy for this page
522 shmem_page_offset
= offset
& ~PAGE_MASK
;
523 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
524 data_page_offset
= data_ptr
& ~PAGE_MASK
;
526 page_length
= remain
;
527 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
528 page_length
= PAGE_SIZE
- shmem_page_offset
;
529 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
530 page_length
= PAGE_SIZE
- data_page_offset
;
532 page
= read_cache_page_gfp(mapping
, offset
>> PAGE_SHIFT
,
533 GFP_HIGHUSER
| __GFP_RECLAIMABLE
);
535 return PTR_ERR(page
);
537 if (do_bit17_swizzling
) {
538 slow_shmem_bit17_copy(page
,
540 user_pages
[data_page_index
],
545 slow_shmem_copy(user_pages
[data_page_index
],
552 mark_page_accessed(page
);
553 page_cache_release(page
);
555 remain
-= page_length
;
556 data_ptr
+= page_length
;
557 offset
+= page_length
;
561 for (i
= 0; i
< pinned_pages
; i
++) {
562 SetPageDirty(user_pages
[i
]);
563 mark_page_accessed(user_pages
[i
]);
564 page_cache_release(user_pages
[i
]);
566 drm_free_large(user_pages
);
572 * Reads data from the object referenced by handle.
574 * On error, the contents of *data are undefined.
577 i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
578 struct drm_file
*file_priv
)
580 struct drm_i915_gem_pread
*args
= data
;
581 struct drm_gem_object
*obj
;
582 struct drm_i915_gem_object
*obj_priv
;
588 if (!access_ok(VERIFY_WRITE
,
589 (char __user
*)(uintptr_t)args
->data_ptr
,
593 ret
= fault_in_pages_writeable((char __user
*)(uintptr_t)args
->data_ptr
,
598 ret
= i915_mutex_lock_interruptible(dev
);
602 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
607 obj_priv
= to_intel_bo(obj
);
609 /* Bounds check source. */
610 if (args
->offset
> obj
->size
|| args
->size
> obj
->size
- args
->offset
) {
615 ret
= i915_gem_object_set_cpu_read_domain_range(obj
,
622 if (!i915_gem_object_needs_bit17_swizzle(obj
))
623 ret
= i915_gem_shmem_pread_fast(dev
, obj
, args
, file_priv
);
625 ret
= i915_gem_shmem_pread_slow(dev
, obj
, args
, file_priv
);
628 drm_gem_object_unreference(obj
);
630 mutex_unlock(&dev
->struct_mutex
);
634 /* This is the fast write path which cannot handle
635 * page faults in the source data
639 fast_user_write(struct io_mapping
*mapping
,
640 loff_t page_base
, int page_offset
,
641 char __user
*user_data
,
645 unsigned long unwritten
;
647 vaddr_atomic
= io_mapping_map_atomic_wc(mapping
, page_base
);
648 unwritten
= __copy_from_user_inatomic_nocache(vaddr_atomic
+ page_offset
,
650 io_mapping_unmap_atomic(vaddr_atomic
);
654 /* Here's the write path which can sleep for
659 slow_kernel_write(struct io_mapping
*mapping
,
660 loff_t gtt_base
, int gtt_offset
,
661 struct page
*user_page
, int user_offset
,
664 char __iomem
*dst_vaddr
;
667 dst_vaddr
= io_mapping_map_wc(mapping
, gtt_base
);
668 src_vaddr
= kmap(user_page
);
670 memcpy_toio(dst_vaddr
+ gtt_offset
,
671 src_vaddr
+ user_offset
,
675 io_mapping_unmap(dst_vaddr
);
679 * This is the fast pwrite path, where we copy the data directly from the
680 * user into the GTT, uncached.
683 i915_gem_gtt_pwrite_fast(struct drm_device
*dev
, struct drm_gem_object
*obj
,
684 struct drm_i915_gem_pwrite
*args
,
685 struct drm_file
*file_priv
)
687 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
688 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
690 loff_t offset
, page_base
;
691 char __user
*user_data
;
692 int page_offset
, page_length
;
694 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
697 obj_priv
= to_intel_bo(obj
);
698 offset
= obj_priv
->gtt_offset
+ args
->offset
;
701 /* Operation in this page
703 * page_base = page offset within aperture
704 * page_offset = offset within page
705 * page_length = bytes to copy for this page
707 page_base
= (offset
& ~(PAGE_SIZE
-1));
708 page_offset
= offset
& (PAGE_SIZE
-1);
709 page_length
= remain
;
710 if ((page_offset
+ remain
) > PAGE_SIZE
)
711 page_length
= PAGE_SIZE
- page_offset
;
713 /* If we get a fault while copying data, then (presumably) our
714 * source page isn't available. Return the error and we'll
715 * retry in the slow path.
717 if (fast_user_write(dev_priv
->mm
.gtt_mapping
, page_base
,
718 page_offset
, user_data
, page_length
))
722 remain
-= page_length
;
723 user_data
+= page_length
;
724 offset
+= page_length
;
731 * This is the fallback GTT pwrite path, which uses get_user_pages to pin
732 * the memory and maps it using kmap_atomic for copying.
734 * This code resulted in x11perf -rgb10text consuming about 10% more CPU
735 * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
738 i915_gem_gtt_pwrite_slow(struct drm_device
*dev
, struct drm_gem_object
*obj
,
739 struct drm_i915_gem_pwrite
*args
,
740 struct drm_file
*file_priv
)
742 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
743 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
745 loff_t gtt_page_base
, offset
;
746 loff_t first_data_page
, last_data_page
, num_pages
;
747 loff_t pinned_pages
, i
;
748 struct page
**user_pages
;
749 struct mm_struct
*mm
= current
->mm
;
750 int gtt_page_offset
, data_page_offset
, data_page_index
, page_length
;
752 uint64_t data_ptr
= args
->data_ptr
;
756 /* Pin the user pages containing the data. We can't fault while
757 * holding the struct mutex, and all of the pwrite implementations
758 * want to hold it while dereferencing the user data.
760 first_data_page
= data_ptr
/ PAGE_SIZE
;
761 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
762 num_pages
= last_data_page
- first_data_page
+ 1;
764 user_pages
= drm_malloc_ab(num_pages
, sizeof(struct page
*));
765 if (user_pages
== NULL
)
768 mutex_unlock(&dev
->struct_mutex
);
769 down_read(&mm
->mmap_sem
);
770 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
771 num_pages
, 0, 0, user_pages
, NULL
);
772 up_read(&mm
->mmap_sem
);
773 mutex_lock(&dev
->struct_mutex
);
774 if (pinned_pages
< num_pages
) {
776 goto out_unpin_pages
;
779 ret
= i915_gem_object_set_to_gtt_domain(obj
, 1);
781 goto out_unpin_pages
;
783 obj_priv
= to_intel_bo(obj
);
784 offset
= obj_priv
->gtt_offset
+ args
->offset
;
787 /* Operation in this page
789 * gtt_page_base = page offset within aperture
790 * gtt_page_offset = offset within page in aperture
791 * data_page_index = page number in get_user_pages return
792 * data_page_offset = offset with data_page_index page.
793 * page_length = bytes to copy for this page
795 gtt_page_base
= offset
& PAGE_MASK
;
796 gtt_page_offset
= offset
& ~PAGE_MASK
;
797 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
798 data_page_offset
= data_ptr
& ~PAGE_MASK
;
800 page_length
= remain
;
801 if ((gtt_page_offset
+ page_length
) > PAGE_SIZE
)
802 page_length
= PAGE_SIZE
- gtt_page_offset
;
803 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
804 page_length
= PAGE_SIZE
- data_page_offset
;
806 slow_kernel_write(dev_priv
->mm
.gtt_mapping
,
807 gtt_page_base
, gtt_page_offset
,
808 user_pages
[data_page_index
],
812 remain
-= page_length
;
813 offset
+= page_length
;
814 data_ptr
+= page_length
;
818 for (i
= 0; i
< pinned_pages
; i
++)
819 page_cache_release(user_pages
[i
]);
820 drm_free_large(user_pages
);
826 * This is the fast shmem pwrite path, which attempts to directly
827 * copy_from_user into the kmapped pages backing the object.
830 i915_gem_shmem_pwrite_fast(struct drm_device
*dev
, struct drm_gem_object
*obj
,
831 struct drm_i915_gem_pwrite
*args
,
832 struct drm_file
*file_priv
)
834 struct address_space
*mapping
= obj
->filp
->f_path
.dentry
->d_inode
->i_mapping
;
835 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
838 char __user
*user_data
;
839 int page_offset
, page_length
;
841 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
844 obj_priv
= to_intel_bo(obj
);
845 offset
= args
->offset
;
853 /* Operation in this page
855 * page_offset = offset within page
856 * page_length = bytes to copy for this page
858 page_offset
= offset
& (PAGE_SIZE
-1);
859 page_length
= remain
;
860 if ((page_offset
+ remain
) > PAGE_SIZE
)
861 page_length
= PAGE_SIZE
- page_offset
;
863 page
= read_cache_page_gfp(mapping
, offset
>> PAGE_SHIFT
,
864 GFP_HIGHUSER
| __GFP_RECLAIMABLE
);
866 return PTR_ERR(page
);
868 vaddr
= kmap_atomic(page
, KM_USER0
);
869 ret
= __copy_from_user_inatomic(vaddr
+ page_offset
,
872 kunmap_atomic(vaddr
, KM_USER0
);
874 set_page_dirty(page
);
875 mark_page_accessed(page
);
876 page_cache_release(page
);
878 /* If we get a fault while copying data, then (presumably) our
879 * source page isn't available. Return the error and we'll
880 * retry in the slow path.
885 remain
-= page_length
;
886 user_data
+= page_length
;
887 offset
+= page_length
;
894 * This is the fallback shmem pwrite path, which uses get_user_pages to pin
895 * the memory and maps it using kmap_atomic for copying.
897 * This avoids taking mmap_sem for faulting on the user's address while the
898 * struct_mutex is held.
901 i915_gem_shmem_pwrite_slow(struct drm_device
*dev
, struct drm_gem_object
*obj
,
902 struct drm_i915_gem_pwrite
*args
,
903 struct drm_file
*file_priv
)
905 struct address_space
*mapping
= obj
->filp
->f_path
.dentry
->d_inode
->i_mapping
;
906 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
907 struct mm_struct
*mm
= current
->mm
;
908 struct page
**user_pages
;
910 loff_t offset
, pinned_pages
, i
;
911 loff_t first_data_page
, last_data_page
, num_pages
;
912 int shmem_page_offset
;
913 int data_page_index
, data_page_offset
;
916 uint64_t data_ptr
= args
->data_ptr
;
917 int do_bit17_swizzling
;
921 /* Pin the user pages containing the data. We can't fault while
922 * holding the struct mutex, and all of the pwrite implementations
923 * want to hold it while dereferencing the user data.
925 first_data_page
= data_ptr
/ PAGE_SIZE
;
926 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
927 num_pages
= last_data_page
- first_data_page
+ 1;
929 user_pages
= drm_malloc_ab(num_pages
, sizeof(struct page
*));
930 if (user_pages
== NULL
)
933 mutex_unlock(&dev
->struct_mutex
);
934 down_read(&mm
->mmap_sem
);
935 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
936 num_pages
, 0, 0, user_pages
, NULL
);
937 up_read(&mm
->mmap_sem
);
938 mutex_lock(&dev
->struct_mutex
);
939 if (pinned_pages
< num_pages
) {
944 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
948 do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
950 obj_priv
= to_intel_bo(obj
);
951 offset
= args
->offset
;
957 /* Operation in this page
959 * shmem_page_offset = offset within page in shmem file
960 * data_page_index = page number in get_user_pages return
961 * data_page_offset = offset with data_page_index page.
962 * page_length = bytes to copy for this page
964 shmem_page_offset
= offset
& ~PAGE_MASK
;
965 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
966 data_page_offset
= data_ptr
& ~PAGE_MASK
;
968 page_length
= remain
;
969 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
970 page_length
= PAGE_SIZE
- shmem_page_offset
;
971 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
972 page_length
= PAGE_SIZE
- data_page_offset
;
974 page
= read_cache_page_gfp(mapping
, offset
>> PAGE_SHIFT
,
975 GFP_HIGHUSER
| __GFP_RECLAIMABLE
);
981 if (do_bit17_swizzling
) {
982 slow_shmem_bit17_copy(page
,
984 user_pages
[data_page_index
],
989 slow_shmem_copy(page
,
991 user_pages
[data_page_index
],
996 set_page_dirty(page
);
997 mark_page_accessed(page
);
998 page_cache_release(page
);
1000 remain
-= page_length
;
1001 data_ptr
+= page_length
;
1002 offset
+= page_length
;
1006 for (i
= 0; i
< pinned_pages
; i
++)
1007 page_cache_release(user_pages
[i
]);
1008 drm_free_large(user_pages
);
1014 * Writes data to the object referenced by handle.
1016 * On error, the contents of the buffer that were to be modified are undefined.
1019 i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
1020 struct drm_file
*file
)
1022 struct drm_i915_gem_pwrite
*args
= data
;
1023 struct drm_gem_object
*obj
;
1024 struct drm_i915_gem_object
*obj_priv
;
1027 if (args
->size
== 0)
1030 if (!access_ok(VERIFY_READ
,
1031 (char __user
*)(uintptr_t)args
->data_ptr
,
1035 ret
= fault_in_pages_readable((char __user
*)(uintptr_t)args
->data_ptr
,
1040 ret
= i915_mutex_lock_interruptible(dev
);
1044 obj
= drm_gem_object_lookup(dev
, file
, args
->handle
);
1049 obj_priv
= to_intel_bo(obj
);
1051 /* Bounds check destination. */
1052 if (args
->offset
> obj
->size
|| args
->size
> obj
->size
- args
->offset
) {
1057 /* We can only do the GTT pwrite on untiled buffers, as otherwise
1058 * it would end up going through the fenced access, and we'll get
1059 * different detiling behavior between reading and writing.
1060 * pread/pwrite currently are reading and writing from the CPU
1061 * perspective, requiring manual detiling by the client.
1063 if (obj_priv
->phys_obj
)
1064 ret
= i915_gem_phys_pwrite(dev
, obj
, args
, file
);
1065 else if (obj_priv
->tiling_mode
== I915_TILING_NONE
&&
1066 obj_priv
->gtt_space
&&
1067 obj
->write_domain
!= I915_GEM_DOMAIN_CPU
) {
1068 ret
= i915_gem_object_pin(obj
, 0, true);
1072 ret
= i915_gem_object_set_to_gtt_domain(obj
, 1);
1076 ret
= i915_gem_gtt_pwrite_fast(dev
, obj
, args
, file
);
1078 ret
= i915_gem_gtt_pwrite_slow(dev
, obj
, args
, file
);
1081 i915_gem_object_unpin(obj
);
1083 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
1088 if (!i915_gem_object_needs_bit17_swizzle(obj
))
1089 ret
= i915_gem_shmem_pwrite_fast(dev
, obj
, args
, file
);
1091 ret
= i915_gem_shmem_pwrite_slow(dev
, obj
, args
, file
);
1095 drm_gem_object_unreference(obj
);
1097 mutex_unlock(&dev
->struct_mutex
);
1102 * Called when user space prepares to use an object with the CPU, either
1103 * through the mmap ioctl's mapping or a GTT mapping.
1106 i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
1107 struct drm_file
*file_priv
)
1109 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1110 struct drm_i915_gem_set_domain
*args
= data
;
1111 struct drm_gem_object
*obj
;
1112 struct drm_i915_gem_object
*obj_priv
;
1113 uint32_t read_domains
= args
->read_domains
;
1114 uint32_t write_domain
= args
->write_domain
;
1117 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1120 /* Only handle setting domains to types used by the CPU. */
1121 if (write_domain
& I915_GEM_GPU_DOMAINS
)
1124 if (read_domains
& I915_GEM_GPU_DOMAINS
)
1127 /* Having something in the write domain implies it's in the read
1128 * domain, and only that read domain. Enforce that in the request.
1130 if (write_domain
!= 0 && read_domains
!= write_domain
)
1133 ret
= i915_mutex_lock_interruptible(dev
);
1137 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1142 obj_priv
= to_intel_bo(obj
);
1144 intel_mark_busy(dev
, obj
);
1146 if (read_domains
& I915_GEM_DOMAIN_GTT
) {
1147 ret
= i915_gem_object_set_to_gtt_domain(obj
, write_domain
!= 0);
1149 /* Update the LRU on the fence for the CPU access that's
1152 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
) {
1153 struct drm_i915_fence_reg
*reg
=
1154 &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
1155 list_move_tail(®
->lru_list
,
1156 &dev_priv
->mm
.fence_list
);
1159 /* Silently promote "you're not bound, there was nothing to do"
1160 * to success, since the client was just asking us to
1161 * make sure everything was done.
1166 ret
= i915_gem_object_set_to_cpu_domain(obj
, write_domain
!= 0);
1169 /* Maintain LRU order of "inactive" objects */
1170 if (ret
== 0 && i915_gem_object_is_inactive(obj_priv
))
1171 list_move_tail(&obj_priv
->mm_list
, &dev_priv
->mm
.inactive_list
);
1173 drm_gem_object_unreference(obj
);
1175 mutex_unlock(&dev
->struct_mutex
);
1180 * Called when user space has done writes to this buffer
1183 i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1184 struct drm_file
*file_priv
)
1186 struct drm_i915_gem_sw_finish
*args
= data
;
1187 struct drm_gem_object
*obj
;
1190 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1193 ret
= i915_mutex_lock_interruptible(dev
);
1197 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1203 /* Pinned buffers may be scanout, so flush the cache */
1204 if (to_intel_bo(obj
)->pin_count
)
1205 i915_gem_object_flush_cpu_write_domain(obj
);
1207 drm_gem_object_unreference(obj
);
1209 mutex_unlock(&dev
->struct_mutex
);
1214 * Maps the contents of an object, returning the address it is mapped
1217 * While the mapping holds a reference on the contents of the object, it doesn't
1218 * imply a ref on the object itself.
1221 i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1222 struct drm_file
*file_priv
)
1224 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1225 struct drm_i915_gem_mmap
*args
= data
;
1226 struct drm_gem_object
*obj
;
1230 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1233 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1237 if (obj
->size
> dev_priv
->mm
.gtt_mappable_end
) {
1238 drm_gem_object_unreference_unlocked(obj
);
1242 offset
= args
->offset
;
1244 down_write(¤t
->mm
->mmap_sem
);
1245 addr
= do_mmap(obj
->filp
, 0, args
->size
,
1246 PROT_READ
| PROT_WRITE
, MAP_SHARED
,
1248 up_write(¤t
->mm
->mmap_sem
);
1249 drm_gem_object_unreference_unlocked(obj
);
1250 if (IS_ERR((void *)addr
))
1253 args
->addr_ptr
= (uint64_t) addr
;
1259 * i915_gem_fault - fault a page into the GTT
1260 * vma: VMA in question
1263 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1264 * from userspace. The fault handler takes care of binding the object to
1265 * the GTT (if needed), allocating and programming a fence register (again,
1266 * only if needed based on whether the old reg is still valid or the object
1267 * is tiled) and inserting a new PTE into the faulting process.
1269 * Note that the faulting process may involve evicting existing objects
1270 * from the GTT and/or fence registers to make room. So performance may
1271 * suffer if the GTT working set is large or there are few fence registers
1274 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
)
1276 struct drm_gem_object
*obj
= vma
->vm_private_data
;
1277 struct drm_device
*dev
= obj
->dev
;
1278 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1279 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1280 pgoff_t page_offset
;
1283 bool write
= !!(vmf
->flags
& FAULT_FLAG_WRITE
);
1285 /* We don't use vmf->pgoff since that has the fake offset */
1286 page_offset
= ((unsigned long)vmf
->virtual_address
- vma
->vm_start
) >>
1289 /* Now bind it into the GTT if needed */
1290 mutex_lock(&dev
->struct_mutex
);
1291 BUG_ON(obj_priv
->pin_count
&& !obj_priv
->pin_mappable
);
1293 if (obj_priv
->gtt_space
) {
1294 if (!obj_priv
->map_and_fenceable
) {
1295 ret
= i915_gem_object_unbind(obj
);
1301 if (!obj_priv
->gtt_space
) {
1302 ret
= i915_gem_object_bind_to_gtt(obj
, 0, true);
1307 ret
= i915_gem_object_set_to_gtt_domain(obj
, write
);
1311 if (!obj_priv
->fault_mappable
) {
1312 obj_priv
->fault_mappable
= true;
1313 i915_gem_info_update_mappable(dev_priv
, obj_priv
, true);
1316 /* Need a new fence register? */
1317 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
) {
1318 ret
= i915_gem_object_get_fence_reg(obj
, true);
1323 if (i915_gem_object_is_inactive(obj_priv
))
1324 list_move_tail(&obj_priv
->mm_list
, &dev_priv
->mm
.inactive_list
);
1326 pfn
= ((dev
->agp
->base
+ obj_priv
->gtt_offset
) >> PAGE_SHIFT
) +
1329 /* Finally, remap it using the new GTT offset */
1330 ret
= vm_insert_pfn(vma
, (unsigned long)vmf
->virtual_address
, pfn
);
1332 mutex_unlock(&dev
->struct_mutex
);
1339 return VM_FAULT_NOPAGE
;
1341 return VM_FAULT_OOM
;
1343 return VM_FAULT_SIGBUS
;
1348 * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1349 * @obj: obj in question
1351 * GEM memory mapping works by handing back to userspace a fake mmap offset
1352 * it can use in a subsequent mmap(2) call. The DRM core code then looks
1353 * up the object based on the offset and sets up the various memory mapping
1356 * This routine allocates and attaches a fake offset for @obj.
1359 i915_gem_create_mmap_offset(struct drm_gem_object
*obj
)
1361 struct drm_device
*dev
= obj
->dev
;
1362 struct drm_gem_mm
*mm
= dev
->mm_private
;
1363 struct drm_map_list
*list
;
1364 struct drm_local_map
*map
;
1367 /* Set the object up for mmap'ing */
1368 list
= &obj
->map_list
;
1369 list
->map
= kzalloc(sizeof(struct drm_map_list
), GFP_KERNEL
);
1374 map
->type
= _DRM_GEM
;
1375 map
->size
= obj
->size
;
1378 /* Get a DRM GEM mmap offset allocated... */
1379 list
->file_offset_node
= drm_mm_search_free(&mm
->offset_manager
,
1380 obj
->size
/ PAGE_SIZE
, 0, 0);
1381 if (!list
->file_offset_node
) {
1382 DRM_ERROR("failed to allocate offset for bo %d\n", obj
->name
);
1387 list
->file_offset_node
= drm_mm_get_block(list
->file_offset_node
,
1388 obj
->size
/ PAGE_SIZE
, 0);
1389 if (!list
->file_offset_node
) {
1394 list
->hash
.key
= list
->file_offset_node
->start
;
1395 ret
= drm_ht_insert_item(&mm
->offset_hash
, &list
->hash
);
1397 DRM_ERROR("failed to add to map hash\n");
1404 drm_mm_put_block(list
->file_offset_node
);
1413 * i915_gem_release_mmap - remove physical page mappings
1414 * @obj: obj in question
1416 * Preserve the reservation of the mmapping with the DRM core code, but
1417 * relinquish ownership of the pages back to the system.
1419 * It is vital that we remove the page mapping if we have mapped a tiled
1420 * object through the GTT and then lose the fence register due to
1421 * resource pressure. Similarly if the object has been moved out of the
1422 * aperture, than pages mapped into userspace must be revoked. Removing the
1423 * mapping will then trigger a page fault on the next user access, allowing
1424 * fixup by i915_gem_fault().
1427 i915_gem_release_mmap(struct drm_gem_object
*obj
)
1429 struct drm_device
*dev
= obj
->dev
;
1430 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1431 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1433 if (unlikely(obj
->map_list
.map
&& dev
->dev_mapping
))
1434 unmap_mapping_range(dev
->dev_mapping
,
1435 (loff_t
)obj
->map_list
.hash
.key
<<PAGE_SHIFT
,
1438 if (obj_priv
->fault_mappable
) {
1439 obj_priv
->fault_mappable
= false;
1440 i915_gem_info_update_mappable(dev_priv
, obj_priv
, false);
1445 i915_gem_free_mmap_offset(struct drm_gem_object
*obj
)
1447 struct drm_device
*dev
= obj
->dev
;
1448 struct drm_gem_mm
*mm
= dev
->mm_private
;
1449 struct drm_map_list
*list
= &obj
->map_list
;
1451 drm_ht_remove_item(&mm
->offset_hash
, &list
->hash
);
1452 drm_mm_put_block(list
->file_offset_node
);
1458 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1459 * @obj: object to check
1461 * Return the required GTT alignment for an object, taking into account
1462 * potential fence register mapping.
1465 i915_gem_get_gtt_alignment(struct drm_i915_gem_object
*obj_priv
)
1467 struct drm_device
*dev
= obj_priv
->base
.dev
;
1470 * Minimum alignment is 4k (GTT page size), but might be greater
1471 * if a fence register is needed for the object.
1473 if (INTEL_INFO(dev
)->gen
>= 4 ||
1474 obj_priv
->tiling_mode
== I915_TILING_NONE
)
1478 * Previous chips need to be aligned to the size of the smallest
1479 * fence register that can contain the object.
1481 return i915_gem_get_gtt_size(obj_priv
);
1485 * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an
1487 * @obj: object to check
1489 * Return the required GTT alignment for an object, only taking into account
1490 * unfenced tiled surface requirements.
1493 i915_gem_get_unfenced_gtt_alignment(struct drm_i915_gem_object
*obj_priv
)
1495 struct drm_device
*dev
= obj_priv
->base
.dev
;
1499 * Minimum alignment is 4k (GTT page size) for sane hw.
1501 if (INTEL_INFO(dev
)->gen
>= 4 || IS_G33(dev
) ||
1502 obj_priv
->tiling_mode
== I915_TILING_NONE
)
1506 * Older chips need unfenced tiled buffers to be aligned to the left
1507 * edge of an even tile row (where tile rows are counted as if the bo is
1508 * placed in a fenced gtt region).
1511 (obj_priv
->tiling_mode
== I915_TILING_Y
&& HAS_128_BYTE_Y_TILING(dev
)))
1516 return tile_height
* obj_priv
->stride
* 2;
1520 i915_gem_get_gtt_size(struct drm_i915_gem_object
*obj_priv
)
1522 struct drm_device
*dev
= obj_priv
->base
.dev
;
1526 * Minimum alignment is 4k (GTT page size), but might be greater
1527 * if a fence register is needed for the object.
1529 if (INTEL_INFO(dev
)->gen
>= 4)
1530 return obj_priv
->base
.size
;
1533 * Previous chips need to be aligned to the size of the smallest
1534 * fence register that can contain the object.
1536 if (INTEL_INFO(dev
)->gen
== 3)
1541 while (size
< obj_priv
->base
.size
)
1548 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1550 * @data: GTT mapping ioctl data
1551 * @file_priv: GEM object info
1553 * Simply returns the fake offset to userspace so it can mmap it.
1554 * The mmap call will end up in drm_gem_mmap(), which will set things
1555 * up so we can get faults in the handler above.
1557 * The fault handler will take care of binding the object into the GTT
1558 * (since it may have been evicted to make room for something), allocating
1559 * a fence register, and mapping the appropriate aperture address into
1563 i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
1564 struct drm_file
*file_priv
)
1566 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1567 struct drm_i915_gem_mmap_gtt
*args
= data
;
1568 struct drm_gem_object
*obj
;
1569 struct drm_i915_gem_object
*obj_priv
;
1572 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1575 ret
= i915_mutex_lock_interruptible(dev
);
1579 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1584 obj_priv
= to_intel_bo(obj
);
1586 if (obj
->size
> dev_priv
->mm
.gtt_mappable_end
) {
1591 if (obj_priv
->madv
!= I915_MADV_WILLNEED
) {
1592 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1597 if (!obj
->map_list
.map
) {
1598 ret
= i915_gem_create_mmap_offset(obj
);
1603 args
->offset
= (u64
)obj
->map_list
.hash
.key
<< PAGE_SHIFT
;
1606 drm_gem_object_unreference(obj
);
1608 mutex_unlock(&dev
->struct_mutex
);
1613 i915_gem_object_get_pages_gtt(struct drm_gem_object
*obj
,
1616 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1618 struct address_space
*mapping
;
1619 struct inode
*inode
;
1622 /* Get the list of pages out of our struct file. They'll be pinned
1623 * at this point until we release them.
1625 page_count
= obj
->size
/ PAGE_SIZE
;
1626 BUG_ON(obj_priv
->pages
!= NULL
);
1627 obj_priv
->pages
= drm_malloc_ab(page_count
, sizeof(struct page
*));
1628 if (obj_priv
->pages
== NULL
)
1631 inode
= obj
->filp
->f_path
.dentry
->d_inode
;
1632 mapping
= inode
->i_mapping
;
1633 for (i
= 0; i
< page_count
; i
++) {
1634 page
= read_cache_page_gfp(mapping
, i
,
1642 obj_priv
->pages
[i
] = page
;
1645 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
)
1646 i915_gem_object_do_bit_17_swizzle(obj
);
1652 page_cache_release(obj_priv
->pages
[i
]);
1654 drm_free_large(obj_priv
->pages
);
1655 obj_priv
->pages
= NULL
;
1656 return PTR_ERR(page
);
1660 i915_gem_object_put_pages_gtt(struct drm_gem_object
*obj
)
1662 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1663 int page_count
= obj
->size
/ PAGE_SIZE
;
1666 BUG_ON(obj_priv
->madv
== __I915_MADV_PURGED
);
1668 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
)
1669 i915_gem_object_save_bit_17_swizzle(obj
);
1671 if (obj_priv
->madv
== I915_MADV_DONTNEED
)
1672 obj_priv
->dirty
= 0;
1674 for (i
= 0; i
< page_count
; i
++) {
1675 if (obj_priv
->dirty
)
1676 set_page_dirty(obj_priv
->pages
[i
]);
1678 if (obj_priv
->madv
== I915_MADV_WILLNEED
)
1679 mark_page_accessed(obj_priv
->pages
[i
]);
1681 page_cache_release(obj_priv
->pages
[i
]);
1683 obj_priv
->dirty
= 0;
1685 drm_free_large(obj_priv
->pages
);
1686 obj_priv
->pages
= NULL
;
1690 i915_gem_next_request_seqno(struct drm_device
*dev
,
1691 struct intel_ring_buffer
*ring
)
1693 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1694 return ring
->outstanding_lazy_request
= dev_priv
->next_seqno
;
1698 i915_gem_object_move_to_active(struct drm_gem_object
*obj
,
1699 struct intel_ring_buffer
*ring
)
1701 struct drm_device
*dev
= obj
->dev
;
1702 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1703 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1704 uint32_t seqno
= i915_gem_next_request_seqno(dev
, ring
);
1706 BUG_ON(ring
== NULL
);
1707 obj_priv
->ring
= ring
;
1709 /* Add a reference if we're newly entering the active list. */
1710 if (!obj_priv
->active
) {
1711 drm_gem_object_reference(obj
);
1712 obj_priv
->active
= 1;
1715 /* Move from whatever list we were on to the tail of execution. */
1716 list_move_tail(&obj_priv
->mm_list
, &dev_priv
->mm
.active_list
);
1717 list_move_tail(&obj_priv
->ring_list
, &ring
->active_list
);
1718 obj_priv
->last_rendering_seqno
= seqno
;
1722 i915_gem_object_move_to_flushing(struct drm_gem_object
*obj
)
1724 struct drm_device
*dev
= obj
->dev
;
1725 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1726 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1728 BUG_ON(!obj_priv
->active
);
1729 list_move_tail(&obj_priv
->mm_list
, &dev_priv
->mm
.flushing_list
);
1730 list_del_init(&obj_priv
->ring_list
);
1731 obj_priv
->last_rendering_seqno
= 0;
1734 /* Immediately discard the backing storage */
1736 i915_gem_object_truncate(struct drm_gem_object
*obj
)
1738 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1739 struct inode
*inode
;
1741 /* Our goal here is to return as much of the memory as
1742 * is possible back to the system as we are called from OOM.
1743 * To do this we must instruct the shmfs to drop all of its
1744 * backing pages, *now*. Here we mirror the actions taken
1745 * when by shmem_delete_inode() to release the backing store.
1747 inode
= obj
->filp
->f_path
.dentry
->d_inode
;
1748 truncate_inode_pages(inode
->i_mapping
, 0);
1749 if (inode
->i_op
->truncate_range
)
1750 inode
->i_op
->truncate_range(inode
, 0, (loff_t
)-1);
1752 obj_priv
->madv
= __I915_MADV_PURGED
;
1756 i915_gem_object_is_purgeable(struct drm_i915_gem_object
*obj_priv
)
1758 return obj_priv
->madv
== I915_MADV_DONTNEED
;
1762 i915_gem_object_move_to_inactive(struct drm_gem_object
*obj
)
1764 struct drm_device
*dev
= obj
->dev
;
1765 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1766 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1768 if (obj_priv
->pin_count
!= 0)
1769 list_move_tail(&obj_priv
->mm_list
, &dev_priv
->mm
.pinned_list
);
1771 list_move_tail(&obj_priv
->mm_list
, &dev_priv
->mm
.inactive_list
);
1772 list_del_init(&obj_priv
->ring_list
);
1774 BUG_ON(!list_empty(&obj_priv
->gpu_write_list
));
1776 obj_priv
->last_rendering_seqno
= 0;
1777 obj_priv
->ring
= NULL
;
1778 if (obj_priv
->active
) {
1779 obj_priv
->active
= 0;
1780 drm_gem_object_unreference(obj
);
1782 WARN_ON(i915_verify_lists(dev
));
1786 i915_gem_process_flushing_list(struct drm_device
*dev
,
1787 uint32_t flush_domains
,
1788 struct intel_ring_buffer
*ring
)
1790 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1791 struct drm_i915_gem_object
*obj_priv
, *next
;
1793 list_for_each_entry_safe(obj_priv
, next
,
1794 &ring
->gpu_write_list
,
1796 struct drm_gem_object
*obj
= &obj_priv
->base
;
1798 if (obj
->write_domain
& flush_domains
) {
1799 uint32_t old_write_domain
= obj
->write_domain
;
1801 obj
->write_domain
= 0;
1802 list_del_init(&obj_priv
->gpu_write_list
);
1803 i915_gem_object_move_to_active(obj
, ring
);
1805 /* update the fence lru list */
1806 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
) {
1807 struct drm_i915_fence_reg
*reg
=
1808 &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
1809 list_move_tail(®
->lru_list
,
1810 &dev_priv
->mm
.fence_list
);
1813 trace_i915_gem_object_change_domain(obj
,
1821 i915_add_request(struct drm_device
*dev
,
1822 struct drm_file
*file
,
1823 struct drm_i915_gem_request
*request
,
1824 struct intel_ring_buffer
*ring
)
1826 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1827 struct drm_i915_file_private
*file_priv
= NULL
;
1832 BUG_ON(request
== NULL
);
1835 file_priv
= file
->driver_priv
;
1837 ret
= ring
->add_request(ring
, &seqno
);
1841 ring
->outstanding_lazy_request
= false;
1843 request
->seqno
= seqno
;
1844 request
->ring
= ring
;
1845 request
->emitted_jiffies
= jiffies
;
1846 was_empty
= list_empty(&ring
->request_list
);
1847 list_add_tail(&request
->list
, &ring
->request_list
);
1850 spin_lock(&file_priv
->mm
.lock
);
1851 request
->file_priv
= file_priv
;
1852 list_add_tail(&request
->client_list
,
1853 &file_priv
->mm
.request_list
);
1854 spin_unlock(&file_priv
->mm
.lock
);
1857 if (!dev_priv
->mm
.suspended
) {
1858 mod_timer(&dev_priv
->hangcheck_timer
,
1859 jiffies
+ msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD
));
1861 queue_delayed_work(dev_priv
->wq
,
1862 &dev_priv
->mm
.retire_work
, HZ
);
1868 * Command execution barrier
1870 * Ensures that all commands in the ring are finished
1871 * before signalling the CPU
1874 i915_retire_commands(struct drm_device
*dev
, struct intel_ring_buffer
*ring
)
1876 uint32_t flush_domains
= 0;
1878 /* The sampler always gets flushed on i965 (sigh) */
1879 if (INTEL_INFO(dev
)->gen
>= 4)
1880 flush_domains
|= I915_GEM_DOMAIN_SAMPLER
;
1882 ring
->flush(ring
, I915_GEM_DOMAIN_COMMAND
, flush_domains
);
1886 i915_gem_request_remove_from_client(struct drm_i915_gem_request
*request
)
1888 struct drm_i915_file_private
*file_priv
= request
->file_priv
;
1893 spin_lock(&file_priv
->mm
.lock
);
1894 list_del(&request
->client_list
);
1895 request
->file_priv
= NULL
;
1896 spin_unlock(&file_priv
->mm
.lock
);
1899 static void i915_gem_reset_ring_lists(struct drm_i915_private
*dev_priv
,
1900 struct intel_ring_buffer
*ring
)
1902 while (!list_empty(&ring
->request_list
)) {
1903 struct drm_i915_gem_request
*request
;
1905 request
= list_first_entry(&ring
->request_list
,
1906 struct drm_i915_gem_request
,
1909 list_del(&request
->list
);
1910 i915_gem_request_remove_from_client(request
);
1914 while (!list_empty(&ring
->active_list
)) {
1915 struct drm_i915_gem_object
*obj_priv
;
1917 obj_priv
= list_first_entry(&ring
->active_list
,
1918 struct drm_i915_gem_object
,
1921 obj_priv
->base
.write_domain
= 0;
1922 list_del_init(&obj_priv
->gpu_write_list
);
1923 i915_gem_object_move_to_inactive(&obj_priv
->base
);
1927 void i915_gem_reset(struct drm_device
*dev
)
1929 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1930 struct drm_i915_gem_object
*obj_priv
;
1933 i915_gem_reset_ring_lists(dev_priv
, &dev_priv
->render_ring
);
1934 i915_gem_reset_ring_lists(dev_priv
, &dev_priv
->bsd_ring
);
1935 i915_gem_reset_ring_lists(dev_priv
, &dev_priv
->blt_ring
);
1937 /* Remove anything from the flushing lists. The GPU cache is likely
1938 * to be lost on reset along with the data, so simply move the
1939 * lost bo to the inactive list.
1941 while (!list_empty(&dev_priv
->mm
.flushing_list
)) {
1942 obj_priv
= list_first_entry(&dev_priv
->mm
.flushing_list
,
1943 struct drm_i915_gem_object
,
1946 obj_priv
->base
.write_domain
= 0;
1947 list_del_init(&obj_priv
->gpu_write_list
);
1948 i915_gem_object_move_to_inactive(&obj_priv
->base
);
1951 /* Move everything out of the GPU domains to ensure we do any
1952 * necessary invalidation upon reuse.
1954 list_for_each_entry(obj_priv
,
1955 &dev_priv
->mm
.inactive_list
,
1958 obj_priv
->base
.read_domains
&= ~I915_GEM_GPU_DOMAINS
;
1961 /* The fence registers are invalidated so clear them out */
1962 for (i
= 0; i
< 16; i
++) {
1963 struct drm_i915_fence_reg
*reg
;
1965 reg
= &dev_priv
->fence_regs
[i
];
1969 i915_gem_clear_fence_reg(reg
->obj
);
1974 * This function clears the request list as sequence numbers are passed.
1977 i915_gem_retire_requests_ring(struct drm_device
*dev
,
1978 struct intel_ring_buffer
*ring
)
1980 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1983 if (!ring
->status_page
.page_addr
||
1984 list_empty(&ring
->request_list
))
1987 WARN_ON(i915_verify_lists(dev
));
1989 seqno
= ring
->get_seqno(ring
);
1990 while (!list_empty(&ring
->request_list
)) {
1991 struct drm_i915_gem_request
*request
;
1993 request
= list_first_entry(&ring
->request_list
,
1994 struct drm_i915_gem_request
,
1997 if (!i915_seqno_passed(seqno
, request
->seqno
))
2000 trace_i915_gem_request_retire(dev
, request
->seqno
);
2002 list_del(&request
->list
);
2003 i915_gem_request_remove_from_client(request
);
2007 /* Move any buffers on the active list that are no longer referenced
2008 * by the ringbuffer to the flushing/inactive lists as appropriate.
2010 while (!list_empty(&ring
->active_list
)) {
2011 struct drm_gem_object
*obj
;
2012 struct drm_i915_gem_object
*obj_priv
;
2014 obj_priv
= list_first_entry(&ring
->active_list
,
2015 struct drm_i915_gem_object
,
2018 if (!i915_seqno_passed(seqno
, obj_priv
->last_rendering_seqno
))
2021 obj
= &obj_priv
->base
;
2022 if (obj
->write_domain
!= 0)
2023 i915_gem_object_move_to_flushing(obj
);
2025 i915_gem_object_move_to_inactive(obj
);
2028 if (unlikely (dev_priv
->trace_irq_seqno
&&
2029 i915_seqno_passed(dev_priv
->trace_irq_seqno
, seqno
))) {
2030 ring
->user_irq_put(ring
);
2031 dev_priv
->trace_irq_seqno
= 0;
2034 WARN_ON(i915_verify_lists(dev
));
2038 i915_gem_retire_requests(struct drm_device
*dev
)
2040 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2042 if (!list_empty(&dev_priv
->mm
.deferred_free_list
)) {
2043 struct drm_i915_gem_object
*obj_priv
, *tmp
;
2045 /* We must be careful that during unbind() we do not
2046 * accidentally infinitely recurse into retire requests.
2048 * retire -> free -> unbind -> wait -> retire_ring
2050 list_for_each_entry_safe(obj_priv
, tmp
,
2051 &dev_priv
->mm
.deferred_free_list
,
2053 i915_gem_free_object_tail(&obj_priv
->base
);
2056 i915_gem_retire_requests_ring(dev
, &dev_priv
->render_ring
);
2057 i915_gem_retire_requests_ring(dev
, &dev_priv
->bsd_ring
);
2058 i915_gem_retire_requests_ring(dev
, &dev_priv
->blt_ring
);
2062 i915_gem_retire_work_handler(struct work_struct
*work
)
2064 drm_i915_private_t
*dev_priv
;
2065 struct drm_device
*dev
;
2067 dev_priv
= container_of(work
, drm_i915_private_t
,
2068 mm
.retire_work
.work
);
2069 dev
= dev_priv
->dev
;
2071 /* Come back later if the device is busy... */
2072 if (!mutex_trylock(&dev
->struct_mutex
)) {
2073 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, HZ
);
2077 i915_gem_retire_requests(dev
);
2079 if (!dev_priv
->mm
.suspended
&&
2080 (!list_empty(&dev_priv
->render_ring
.request_list
) ||
2081 !list_empty(&dev_priv
->bsd_ring
.request_list
) ||
2082 !list_empty(&dev_priv
->blt_ring
.request_list
)))
2083 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, HZ
);
2084 mutex_unlock(&dev
->struct_mutex
);
2088 i915_do_wait_request(struct drm_device
*dev
, uint32_t seqno
,
2089 bool interruptible
, struct intel_ring_buffer
*ring
)
2091 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2097 if (atomic_read(&dev_priv
->mm
.wedged
))
2100 if (seqno
== ring
->outstanding_lazy_request
) {
2101 struct drm_i915_gem_request
*request
;
2103 request
= kzalloc(sizeof(*request
), GFP_KERNEL
);
2104 if (request
== NULL
)
2107 ret
= i915_add_request(dev
, NULL
, request
, ring
);
2113 seqno
= request
->seqno
;
2116 if (!i915_seqno_passed(ring
->get_seqno(ring
), seqno
)) {
2117 if (HAS_PCH_SPLIT(dev
))
2118 ier
= I915_READ(DEIER
) | I915_READ(GTIER
);
2120 ier
= I915_READ(IER
);
2122 DRM_ERROR("something (likely vbetool) disabled "
2123 "interrupts, re-enabling\n");
2124 i915_driver_irq_preinstall(dev
);
2125 i915_driver_irq_postinstall(dev
);
2128 trace_i915_gem_request_wait_begin(dev
, seqno
);
2130 ring
->waiting_seqno
= seqno
;
2131 ring
->user_irq_get(ring
);
2133 ret
= wait_event_interruptible(ring
->irq_queue
,
2134 i915_seqno_passed(ring
->get_seqno(ring
), seqno
)
2135 || atomic_read(&dev_priv
->mm
.wedged
));
2137 wait_event(ring
->irq_queue
,
2138 i915_seqno_passed(ring
->get_seqno(ring
), seqno
)
2139 || atomic_read(&dev_priv
->mm
.wedged
));
2141 ring
->user_irq_put(ring
);
2142 ring
->waiting_seqno
= 0;
2144 trace_i915_gem_request_wait_end(dev
, seqno
);
2146 if (atomic_read(&dev_priv
->mm
.wedged
))
2149 if (ret
&& ret
!= -ERESTARTSYS
)
2150 DRM_ERROR("%s returns %d (awaiting %d at %d, next %d)\n",
2151 __func__
, ret
, seqno
, ring
->get_seqno(ring
),
2152 dev_priv
->next_seqno
);
2154 /* Directly dispatch request retiring. While we have the work queue
2155 * to handle this, the waiter on a request often wants an associated
2156 * buffer to have made it to the inactive list, and we would need
2157 * a separate wait queue to handle that.
2160 i915_gem_retire_requests_ring(dev
, ring
);
2166 * Waits for a sequence number to be signaled, and cleans up the
2167 * request and object lists appropriately for that event.
2170 i915_wait_request(struct drm_device
*dev
, uint32_t seqno
,
2171 struct intel_ring_buffer
*ring
)
2173 return i915_do_wait_request(dev
, seqno
, 1, ring
);
2177 i915_gem_flush_ring(struct drm_device
*dev
,
2178 struct drm_file
*file_priv
,
2179 struct intel_ring_buffer
*ring
,
2180 uint32_t invalidate_domains
,
2181 uint32_t flush_domains
)
2183 ring
->flush(ring
, invalidate_domains
, flush_domains
);
2184 i915_gem_process_flushing_list(dev
, flush_domains
, ring
);
2188 i915_gem_flush(struct drm_device
*dev
,
2189 struct drm_file
*file_priv
,
2190 uint32_t invalidate_domains
,
2191 uint32_t flush_domains
,
2192 uint32_t flush_rings
)
2194 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2196 if (flush_domains
& I915_GEM_DOMAIN_CPU
)
2197 intel_gtt_chipset_flush();
2199 if ((flush_domains
| invalidate_domains
) & I915_GEM_GPU_DOMAINS
) {
2200 if (flush_rings
& RING_RENDER
)
2201 i915_gem_flush_ring(dev
, file_priv
,
2202 &dev_priv
->render_ring
,
2203 invalidate_domains
, flush_domains
);
2204 if (flush_rings
& RING_BSD
)
2205 i915_gem_flush_ring(dev
, file_priv
,
2206 &dev_priv
->bsd_ring
,
2207 invalidate_domains
, flush_domains
);
2208 if (flush_rings
& RING_BLT
)
2209 i915_gem_flush_ring(dev
, file_priv
,
2210 &dev_priv
->blt_ring
,
2211 invalidate_domains
, flush_domains
);
2216 * Ensures that all rendering to the object has completed and the object is
2217 * safe to unbind from the GTT or access from the CPU.
2220 i915_gem_object_wait_rendering(struct drm_gem_object
*obj
,
2223 struct drm_device
*dev
= obj
->dev
;
2224 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2227 /* This function only exists to support waiting for existing rendering,
2228 * not for emitting required flushes.
2230 BUG_ON((obj
->write_domain
& I915_GEM_GPU_DOMAINS
) != 0);
2232 /* If there is rendering queued on the buffer being evicted, wait for
2235 if (obj_priv
->active
) {
2236 ret
= i915_do_wait_request(dev
,
2237 obj_priv
->last_rendering_seqno
,
2248 * Unbinds an object from the GTT aperture.
2251 i915_gem_object_unbind(struct drm_gem_object
*obj
)
2253 struct drm_device
*dev
= obj
->dev
;
2254 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2255 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2258 if (obj_priv
->gtt_space
== NULL
)
2261 if (obj_priv
->pin_count
!= 0) {
2262 DRM_ERROR("Attempting to unbind pinned buffer\n");
2266 /* blow away mappings if mapped through GTT */
2267 i915_gem_release_mmap(obj
);
2269 /* Move the object to the CPU domain to ensure that
2270 * any possible CPU writes while it's not in the GTT
2271 * are flushed when we go to remap it. This will
2272 * also ensure that all pending GPU writes are finished
2275 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
2276 if (ret
== -ERESTARTSYS
)
2278 /* Continue on if we fail due to EIO, the GPU is hung so we
2279 * should be safe and we need to cleanup or else we might
2280 * cause memory corruption through use-after-free.
2283 i915_gem_clflush_object(obj
);
2284 obj
->read_domains
= obj
->write_domain
= I915_GEM_DOMAIN_CPU
;
2287 /* release the fence reg _after_ flushing */
2288 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
)
2289 i915_gem_clear_fence_reg(obj
);
2291 i915_gem_gtt_unbind_object(obj
);
2293 i915_gem_object_put_pages_gtt(obj
);
2295 i915_gem_info_remove_gtt(dev_priv
, obj_priv
);
2296 list_del_init(&obj_priv
->mm_list
);
2297 /* Avoid an unnecessary call to unbind on rebind. */
2298 obj_priv
->map_and_fenceable
= true;
2300 drm_mm_put_block(obj_priv
->gtt_space
);
2301 obj_priv
->gtt_space
= NULL
;
2302 obj_priv
->gtt_offset
= 0;
2304 if (i915_gem_object_is_purgeable(obj_priv
))
2305 i915_gem_object_truncate(obj
);
2307 trace_i915_gem_object_unbind(obj
);
2312 static int i915_ring_idle(struct drm_device
*dev
,
2313 struct intel_ring_buffer
*ring
)
2315 if (list_empty(&ring
->gpu_write_list
) && list_empty(&ring
->active_list
))
2318 i915_gem_flush_ring(dev
, NULL
, ring
,
2319 I915_GEM_GPU_DOMAINS
, I915_GEM_GPU_DOMAINS
);
2320 return i915_wait_request(dev
,
2321 i915_gem_next_request_seqno(dev
, ring
),
2326 i915_gpu_idle(struct drm_device
*dev
)
2328 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2332 lists_empty
= (list_empty(&dev_priv
->mm
.flushing_list
) &&
2333 list_empty(&dev_priv
->mm
.active_list
));
2337 /* Flush everything onto the inactive list. */
2338 ret
= i915_ring_idle(dev
, &dev_priv
->render_ring
);
2342 ret
= i915_ring_idle(dev
, &dev_priv
->bsd_ring
);
2346 ret
= i915_ring_idle(dev
, &dev_priv
->blt_ring
);
2353 static void sandybridge_write_fence_reg(struct drm_gem_object
*obj
)
2355 struct drm_device
*dev
= obj
->dev
;
2356 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2357 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2358 u32 size
= i915_gem_get_gtt_size(obj_priv
);
2359 int regnum
= obj_priv
->fence_reg
;
2362 val
= (uint64_t)((obj_priv
->gtt_offset
+ size
- 4096) &
2364 val
|= obj_priv
->gtt_offset
& 0xfffff000;
2365 val
|= (uint64_t)((obj_priv
->stride
/ 128) - 1) <<
2366 SANDYBRIDGE_FENCE_PITCH_SHIFT
;
2368 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2369 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
2370 val
|= I965_FENCE_REG_VALID
;
2372 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0
+ (regnum
* 8), val
);
2375 static void i965_write_fence_reg(struct drm_gem_object
*obj
)
2377 struct drm_device
*dev
= obj
->dev
;
2378 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2379 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2380 u32 size
= i915_gem_get_gtt_size(obj_priv
);
2381 int regnum
= obj_priv
->fence_reg
;
2384 val
= (uint64_t)((obj_priv
->gtt_offset
+ size
- 4096) &
2386 val
|= obj_priv
->gtt_offset
& 0xfffff000;
2387 val
|= ((obj_priv
->stride
/ 128) - 1) << I965_FENCE_PITCH_SHIFT
;
2388 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2389 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
2390 val
|= I965_FENCE_REG_VALID
;
2392 I915_WRITE64(FENCE_REG_965_0
+ (regnum
* 8), val
);
2395 static void i915_write_fence_reg(struct drm_gem_object
*obj
)
2397 struct drm_device
*dev
= obj
->dev
;
2398 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2399 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2400 u32 size
= i915_gem_get_gtt_size(obj_priv
);
2401 uint32_t fence_reg
, val
, pitch_val
;
2404 if ((obj_priv
->gtt_offset
& ~I915_FENCE_START_MASK
) ||
2405 (obj_priv
->gtt_offset
& (size
- 1))) {
2406 WARN(1, "%s: object 0x%08x [fenceable? %d] not 1M or size (0x%08x) aligned [gtt_space offset=%lx, size=%lx]\n",
2407 __func__
, obj_priv
->gtt_offset
, obj_priv
->map_and_fenceable
, size
,
2408 obj_priv
->gtt_space
->start
, obj_priv
->gtt_space
->size
);
2412 if (obj_priv
->tiling_mode
== I915_TILING_Y
&&
2413 HAS_128_BYTE_Y_TILING(dev
))
2418 /* Note: pitch better be a power of two tile widths */
2419 pitch_val
= obj_priv
->stride
/ tile_width
;
2420 pitch_val
= ffs(pitch_val
) - 1;
2422 if (obj_priv
->tiling_mode
== I915_TILING_Y
&&
2423 HAS_128_BYTE_Y_TILING(dev
))
2424 WARN_ON(pitch_val
> I830_FENCE_MAX_PITCH_VAL
);
2426 WARN_ON(pitch_val
> I915_FENCE_MAX_PITCH_VAL
);
2428 val
= obj_priv
->gtt_offset
;
2429 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2430 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2431 val
|= I915_FENCE_SIZE_BITS(size
);
2432 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2433 val
|= I830_FENCE_REG_VALID
;
2435 fence_reg
= obj_priv
->fence_reg
;
2437 fence_reg
= FENCE_REG_830_0
+ fence_reg
* 4;
2439 fence_reg
= FENCE_REG_945_8
+ (fence_reg
- 8) * 4;
2440 I915_WRITE(fence_reg
, val
);
2443 static void i830_write_fence_reg(struct drm_gem_object
*obj
)
2445 struct drm_device
*dev
= obj
->dev
;
2446 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2447 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2448 u32 size
= i915_gem_get_gtt_size(obj_priv
);
2449 int regnum
= obj_priv
->fence_reg
;
2452 uint32_t fence_size_bits
;
2454 if ((obj_priv
->gtt_offset
& ~I830_FENCE_START_MASK
) ||
2455 (obj_priv
->gtt_offset
& (obj
->size
- 1))) {
2456 WARN(1, "%s: object 0x%08x not 512K or size aligned\n",
2457 __func__
, obj_priv
->gtt_offset
);
2461 pitch_val
= obj_priv
->stride
/ 128;
2462 pitch_val
= ffs(pitch_val
) - 1;
2463 WARN_ON(pitch_val
> I830_FENCE_MAX_PITCH_VAL
);
2465 val
= obj_priv
->gtt_offset
;
2466 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2467 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2468 fence_size_bits
= I830_FENCE_SIZE_BITS(size
);
2469 WARN_ON(fence_size_bits
& ~0x00000f00);
2470 val
|= fence_size_bits
;
2471 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2472 val
|= I830_FENCE_REG_VALID
;
2474 I915_WRITE(FENCE_REG_830_0
+ (regnum
* 4), val
);
2477 static int i915_find_fence_reg(struct drm_device
*dev
,
2480 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2481 struct drm_i915_fence_reg
*reg
;
2482 struct drm_i915_gem_object
*obj_priv
= NULL
;
2485 /* First try to find a free reg */
2487 for (i
= dev_priv
->fence_reg_start
; i
< dev_priv
->num_fence_regs
; i
++) {
2488 reg
= &dev_priv
->fence_regs
[i
];
2492 obj_priv
= to_intel_bo(reg
->obj
);
2493 if (!obj_priv
->pin_count
)
2500 /* None available, try to steal one or wait for a user to finish */
2501 avail
= I915_FENCE_REG_NONE
;
2502 list_for_each_entry(reg
, &dev_priv
->mm
.fence_list
,
2504 obj_priv
= to_intel_bo(reg
->obj
);
2505 if (obj_priv
->pin_count
)
2509 avail
= obj_priv
->fence_reg
;
2513 BUG_ON(avail
== I915_FENCE_REG_NONE
);
2515 /* We only have a reference on obj from the active list. put_fence_reg
2516 * might drop that one, causing a use-after-free in it. So hold a
2517 * private reference to obj like the other callers of put_fence_reg
2518 * (set_tiling ioctl) do. */
2519 drm_gem_object_reference(&obj_priv
->base
);
2520 ret
= i915_gem_object_put_fence_reg(&obj_priv
->base
, interruptible
);
2521 drm_gem_object_unreference(&obj_priv
->base
);
2529 * i915_gem_object_get_fence_reg - set up a fence reg for an object
2530 * @obj: object to map through a fence reg
2532 * When mapping objects through the GTT, userspace wants to be able to write
2533 * to them without having to worry about swizzling if the object is tiled.
2535 * This function walks the fence regs looking for a free one for @obj,
2536 * stealing one if it can't find any.
2538 * It then sets up the reg based on the object's properties: address, pitch
2539 * and tiling format.
2542 i915_gem_object_get_fence_reg(struct drm_gem_object
*obj
,
2545 struct drm_device
*dev
= obj
->dev
;
2546 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2547 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2548 struct drm_i915_fence_reg
*reg
= NULL
;
2551 /* Just update our place in the LRU if our fence is getting used. */
2552 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
) {
2553 reg
= &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
2554 list_move_tail(®
->lru_list
, &dev_priv
->mm
.fence_list
);
2558 switch (obj_priv
->tiling_mode
) {
2559 case I915_TILING_NONE
:
2560 WARN(1, "allocating a fence for non-tiled object?\n");
2563 if (!obj_priv
->stride
)
2565 WARN((obj_priv
->stride
& (512 - 1)),
2566 "object 0x%08x is X tiled but has non-512B pitch\n",
2567 obj_priv
->gtt_offset
);
2570 if (!obj_priv
->stride
)
2572 WARN((obj_priv
->stride
& (128 - 1)),
2573 "object 0x%08x is Y tiled but has non-128B pitch\n",
2574 obj_priv
->gtt_offset
);
2578 ret
= i915_find_fence_reg(dev
, interruptible
);
2582 obj_priv
->fence_reg
= ret
;
2583 reg
= &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
2584 list_add_tail(®
->lru_list
, &dev_priv
->mm
.fence_list
);
2588 switch (INTEL_INFO(dev
)->gen
) {
2590 sandybridge_write_fence_reg(obj
);
2594 i965_write_fence_reg(obj
);
2597 i915_write_fence_reg(obj
);
2600 i830_write_fence_reg(obj
);
2604 trace_i915_gem_object_get_fence(obj
,
2605 obj_priv
->fence_reg
,
2606 obj_priv
->tiling_mode
);
2612 * i915_gem_clear_fence_reg - clear out fence register info
2613 * @obj: object to clear
2615 * Zeroes out the fence register itself and clears out the associated
2616 * data structures in dev_priv and obj_priv.
2619 i915_gem_clear_fence_reg(struct drm_gem_object
*obj
)
2621 struct drm_device
*dev
= obj
->dev
;
2622 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2623 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2624 struct drm_i915_fence_reg
*reg
=
2625 &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
2628 switch (INTEL_INFO(dev
)->gen
) {
2630 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0
+
2631 (obj_priv
->fence_reg
* 8), 0);
2635 I915_WRITE64(FENCE_REG_965_0
+ (obj_priv
->fence_reg
* 8), 0);
2638 if (obj_priv
->fence_reg
>= 8)
2639 fence_reg
= FENCE_REG_945_8
+ (obj_priv
->fence_reg
- 8) * 4;
2642 fence_reg
= FENCE_REG_830_0
+ obj_priv
->fence_reg
* 4;
2644 I915_WRITE(fence_reg
, 0);
2649 obj_priv
->fence_reg
= I915_FENCE_REG_NONE
;
2650 list_del_init(®
->lru_list
);
2654 * i915_gem_object_put_fence_reg - waits on outstanding fenced access
2655 * to the buffer to finish, and then resets the fence register.
2656 * @obj: tiled object holding a fence register.
2657 * @bool: whether the wait upon the fence is interruptible
2659 * Zeroes out the fence register itself and clears out the associated
2660 * data structures in dev_priv and obj_priv.
2663 i915_gem_object_put_fence_reg(struct drm_gem_object
*obj
,
2666 struct drm_device
*dev
= obj
->dev
;
2667 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2668 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2669 struct drm_i915_fence_reg
*reg
;
2671 if (obj_priv
->fence_reg
== I915_FENCE_REG_NONE
)
2674 /* If we've changed tiling, GTT-mappings of the object
2675 * need to re-fault to ensure that the correct fence register
2676 * setup is in place.
2678 i915_gem_release_mmap(obj
);
2680 /* On the i915, GPU access to tiled buffers is via a fence,
2681 * therefore we must wait for any outstanding access to complete
2682 * before clearing the fence.
2684 reg
= &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
2688 ret
= i915_gem_object_flush_gpu_write_domain(obj
, true);
2692 ret
= i915_gem_object_wait_rendering(obj
, interruptible
);
2699 i915_gem_object_flush_gtt_write_domain(obj
);
2700 i915_gem_clear_fence_reg(obj
);
2706 * Finds free space in the GTT aperture and binds the object there.
2709 i915_gem_object_bind_to_gtt(struct drm_gem_object
*obj
,
2711 bool map_and_fenceable
)
2713 struct drm_device
*dev
= obj
->dev
;
2714 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2715 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2716 struct drm_mm_node
*free_space
;
2717 gfp_t gfpmask
= __GFP_NORETRY
| __GFP_NOWARN
;
2718 u32 size
, fence_size
, fence_alignment
, unfenced_alignment
;
2719 bool mappable
, fenceable
;
2722 if (obj_priv
->madv
!= I915_MADV_WILLNEED
) {
2723 DRM_ERROR("Attempting to bind a purgeable object\n");
2727 fence_size
= i915_gem_get_gtt_size(obj_priv
);
2728 fence_alignment
= i915_gem_get_gtt_alignment(obj_priv
);
2729 unfenced_alignment
= i915_gem_get_unfenced_gtt_alignment(obj_priv
);
2732 alignment
= map_and_fenceable
? fence_alignment
:
2734 if (map_and_fenceable
&& alignment
& (fence_alignment
- 1)) {
2735 DRM_ERROR("Invalid object alignment requested %u\n", alignment
);
2739 size
= map_and_fenceable
? fence_size
: obj
->size
;
2741 /* If the object is bigger than the entire aperture, reject it early
2742 * before evicting everything in a vain attempt to find space.
2745 (map_and_fenceable
? dev_priv
->mm
.gtt_mappable_end
: dev_priv
->mm
.gtt_total
)) {
2746 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2751 if (map_and_fenceable
)
2753 drm_mm_search_free_in_range(&dev_priv
->mm
.gtt_space
,
2755 dev_priv
->mm
.gtt_mappable_end
,
2758 free_space
= drm_mm_search_free(&dev_priv
->mm
.gtt_space
,
2759 size
, alignment
, 0);
2761 if (free_space
!= NULL
) {
2762 if (map_and_fenceable
)
2763 obj_priv
->gtt_space
=
2764 drm_mm_get_block_range_generic(free_space
,
2766 dev_priv
->mm
.gtt_mappable_end
,
2769 obj_priv
->gtt_space
=
2770 drm_mm_get_block(free_space
, size
, alignment
);
2772 if (obj_priv
->gtt_space
== NULL
) {
2773 /* If the gtt is empty and we're still having trouble
2774 * fitting our object in, we're out of memory.
2776 ret
= i915_gem_evict_something(dev
, size
, alignment
,
2784 ret
= i915_gem_object_get_pages_gtt(obj
, gfpmask
);
2786 drm_mm_put_block(obj_priv
->gtt_space
);
2787 obj_priv
->gtt_space
= NULL
;
2789 if (ret
== -ENOMEM
) {
2790 /* first try to clear up some space from the GTT */
2791 ret
= i915_gem_evict_something(dev
, size
,
2795 /* now try to shrink everyone else */
2810 ret
= i915_gem_gtt_bind_object(obj
);
2812 i915_gem_object_put_pages_gtt(obj
);
2813 drm_mm_put_block(obj_priv
->gtt_space
);
2814 obj_priv
->gtt_space
= NULL
;
2816 ret
= i915_gem_evict_something(dev
, size
,
2817 alignment
, map_and_fenceable
);
2824 obj_priv
->gtt_offset
= obj_priv
->gtt_space
->start
;
2826 /* keep track of bounds object by adding it to the inactive list */
2827 list_add_tail(&obj_priv
->mm_list
, &dev_priv
->mm
.inactive_list
);
2828 i915_gem_info_add_gtt(dev_priv
, obj_priv
);
2830 /* Assert that the object is not currently in any GPU domain. As it
2831 * wasn't in the GTT, there shouldn't be any way it could have been in
2834 BUG_ON(obj
->read_domains
& I915_GEM_GPU_DOMAINS
);
2835 BUG_ON(obj
->write_domain
& I915_GEM_GPU_DOMAINS
);
2837 trace_i915_gem_object_bind(obj
, obj_priv
->gtt_offset
, map_and_fenceable
);
2840 obj_priv
->gtt_space
->size
== fence_size
&&
2841 (obj_priv
->gtt_space
->start
& (fence_alignment
-1)) == 0;
2844 obj_priv
->gtt_offset
+ obj
->size
<= dev_priv
->mm
.gtt_mappable_end
;
2846 obj_priv
->map_and_fenceable
= mappable
&& fenceable
;
2852 i915_gem_clflush_object(struct drm_gem_object
*obj
)
2854 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2856 /* If we don't have a page list set up, then we're not pinned
2857 * to GPU, and we can ignore the cache flush because it'll happen
2858 * again at bind time.
2860 if (obj_priv
->pages
== NULL
)
2863 trace_i915_gem_object_clflush(obj
);
2865 drm_clflush_pages(obj_priv
->pages
, obj
->size
/ PAGE_SIZE
);
2868 /** Flushes any GPU write domain for the object if it's dirty. */
2870 i915_gem_object_flush_gpu_write_domain(struct drm_gem_object
*obj
,
2873 struct drm_device
*dev
= obj
->dev
;
2875 if ((obj
->write_domain
& I915_GEM_GPU_DOMAINS
) == 0)
2878 /* Queue the GPU write cache flushing we need. */
2879 i915_gem_flush_ring(dev
, NULL
,
2880 to_intel_bo(obj
)->ring
,
2881 0, obj
->write_domain
);
2882 BUG_ON(obj
->write_domain
);
2887 return i915_gem_object_wait_rendering(obj
, true);
2890 /** Flushes the GTT write domain for the object if it's dirty. */
2892 i915_gem_object_flush_gtt_write_domain(struct drm_gem_object
*obj
)
2894 uint32_t old_write_domain
;
2896 if (obj
->write_domain
!= I915_GEM_DOMAIN_GTT
)
2899 /* No actual flushing is required for the GTT write domain. Writes
2900 * to it immediately go to main memory as far as we know, so there's
2901 * no chipset flush. It also doesn't land in render cache.
2903 i915_gem_release_mmap(obj
);
2905 old_write_domain
= obj
->write_domain
;
2906 obj
->write_domain
= 0;
2908 trace_i915_gem_object_change_domain(obj
,
2913 /** Flushes the CPU write domain for the object if it's dirty. */
2915 i915_gem_object_flush_cpu_write_domain(struct drm_gem_object
*obj
)
2917 uint32_t old_write_domain
;
2919 if (obj
->write_domain
!= I915_GEM_DOMAIN_CPU
)
2922 i915_gem_clflush_object(obj
);
2923 intel_gtt_chipset_flush();
2924 old_write_domain
= obj
->write_domain
;
2925 obj
->write_domain
= 0;
2927 trace_i915_gem_object_change_domain(obj
,
2933 * Moves a single object to the GTT read, and possibly write domain.
2935 * This function returns when the move is complete, including waiting on
2939 i915_gem_object_set_to_gtt_domain(struct drm_gem_object
*obj
, int write
)
2941 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2942 uint32_t old_write_domain
, old_read_domains
;
2945 /* Not valid to be called on unbound objects. */
2946 if (obj_priv
->gtt_space
== NULL
)
2949 ret
= i915_gem_object_flush_gpu_write_domain(obj
, false);
2953 i915_gem_object_flush_cpu_write_domain(obj
);
2956 ret
= i915_gem_object_wait_rendering(obj
, true);
2961 old_write_domain
= obj
->write_domain
;
2962 old_read_domains
= obj
->read_domains
;
2964 /* It should now be out of any other write domains, and we can update
2965 * the domain values for our changes.
2967 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
2968 obj
->read_domains
|= I915_GEM_DOMAIN_GTT
;
2970 obj
->read_domains
= I915_GEM_DOMAIN_GTT
;
2971 obj
->write_domain
= I915_GEM_DOMAIN_GTT
;
2972 obj_priv
->dirty
= 1;
2975 trace_i915_gem_object_change_domain(obj
,
2983 * Prepare buffer for display plane. Use uninterruptible for possible flush
2984 * wait, as in modesetting process we're not supposed to be interrupted.
2987 i915_gem_object_set_to_display_plane(struct drm_gem_object
*obj
,
2990 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2991 uint32_t old_read_domains
;
2994 /* Not valid to be called on unbound objects. */
2995 if (obj_priv
->gtt_space
== NULL
)
2998 ret
= i915_gem_object_flush_gpu_write_domain(obj
, true);
3002 /* Currently, we are always called from an non-interruptible context. */
3004 ret
= i915_gem_object_wait_rendering(obj
, false);
3009 i915_gem_object_flush_cpu_write_domain(obj
);
3011 old_read_domains
= obj
->read_domains
;
3012 obj
->read_domains
|= I915_GEM_DOMAIN_GTT
;
3014 trace_i915_gem_object_change_domain(obj
,
3022 i915_gem_object_flush_gpu(struct drm_i915_gem_object
*obj
,
3028 if (obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
)
3029 i915_gem_flush_ring(obj
->base
.dev
, NULL
, obj
->ring
,
3030 0, obj
->base
.write_domain
);
3032 return i915_gem_object_wait_rendering(&obj
->base
, interruptible
);
3036 * Moves a single object to the CPU read, and possibly write domain.
3038 * This function returns when the move is complete, including waiting on
3042 i915_gem_object_set_to_cpu_domain(struct drm_gem_object
*obj
, int write
)
3044 uint32_t old_write_domain
, old_read_domains
;
3047 ret
= i915_gem_object_flush_gpu_write_domain(obj
, false);
3051 i915_gem_object_flush_gtt_write_domain(obj
);
3053 /* If we have a partially-valid cache of the object in the CPU,
3054 * finish invalidating it and free the per-page flags.
3056 i915_gem_object_set_to_full_cpu_read_domain(obj
);
3059 ret
= i915_gem_object_wait_rendering(obj
, true);
3064 old_write_domain
= obj
->write_domain
;
3065 old_read_domains
= obj
->read_domains
;
3067 /* Flush the CPU cache if it's still invalid. */
3068 if ((obj
->read_domains
& I915_GEM_DOMAIN_CPU
) == 0) {
3069 i915_gem_clflush_object(obj
);
3071 obj
->read_domains
|= I915_GEM_DOMAIN_CPU
;
3074 /* It should now be out of any other write domains, and we can update
3075 * the domain values for our changes.
3077 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
3079 /* If we're writing through the CPU, then the GPU read domains will
3080 * need to be invalidated at next use.
3083 obj
->read_domains
= I915_GEM_DOMAIN_CPU
;
3084 obj
->write_domain
= I915_GEM_DOMAIN_CPU
;
3087 trace_i915_gem_object_change_domain(obj
,
3095 * Set the next domain for the specified object. This
3096 * may not actually perform the necessary flushing/invaliding though,
3097 * as that may want to be batched with other set_domain operations
3099 * This is (we hope) the only really tricky part of gem. The goal
3100 * is fairly simple -- track which caches hold bits of the object
3101 * and make sure they remain coherent. A few concrete examples may
3102 * help to explain how it works. For shorthand, we use the notation
3103 * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
3104 * a pair of read and write domain masks.
3106 * Case 1: the batch buffer
3112 * 5. Unmapped from GTT
3115 * Let's take these a step at a time
3118 * Pages allocated from the kernel may still have
3119 * cache contents, so we set them to (CPU, CPU) always.
3120 * 2. Written by CPU (using pwrite)
3121 * The pwrite function calls set_domain (CPU, CPU) and
3122 * this function does nothing (as nothing changes)
3124 * This function asserts that the object is not
3125 * currently in any GPU-based read or write domains
3127 * i915_gem_execbuffer calls set_domain (COMMAND, 0).
3128 * As write_domain is zero, this function adds in the
3129 * current read domains (CPU+COMMAND, 0).
3130 * flush_domains is set to CPU.
3131 * invalidate_domains is set to COMMAND
3132 * clflush is run to get data out of the CPU caches
3133 * then i915_dev_set_domain calls i915_gem_flush to
3134 * emit an MI_FLUSH and drm_agp_chipset_flush
3135 * 5. Unmapped from GTT
3136 * i915_gem_object_unbind calls set_domain (CPU, CPU)
3137 * flush_domains and invalidate_domains end up both zero
3138 * so no flushing/invalidating happens
3142 * Case 2: The shared render buffer
3146 * 3. Read/written by GPU
3147 * 4. set_domain to (CPU,CPU)
3148 * 5. Read/written by CPU
3149 * 6. Read/written by GPU
3152 * Same as last example, (CPU, CPU)
3154 * Nothing changes (assertions find that it is not in the GPU)
3155 * 3. Read/written by GPU
3156 * execbuffer calls set_domain (RENDER, RENDER)
3157 * flush_domains gets CPU
3158 * invalidate_domains gets GPU
3160 * MI_FLUSH and drm_agp_chipset_flush
3161 * 4. set_domain (CPU, CPU)
3162 * flush_domains gets GPU
3163 * invalidate_domains gets CPU
3164 * wait_rendering (obj) to make sure all drawing is complete.
3165 * This will include an MI_FLUSH to get the data from GPU
3167 * clflush (obj) to invalidate the CPU cache
3168 * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
3169 * 5. Read/written by CPU
3170 * cache lines are loaded and dirtied
3171 * 6. Read written by GPU
3172 * Same as last GPU access
3174 * Case 3: The constant buffer
3179 * 4. Updated (written) by CPU again
3188 * flush_domains = CPU
3189 * invalidate_domains = RENDER
3192 * drm_agp_chipset_flush
3193 * 4. Updated (written) by CPU again
3195 * flush_domains = 0 (no previous write domain)
3196 * invalidate_domains = 0 (no new read domains)
3199 * flush_domains = CPU
3200 * invalidate_domains = RENDER
3203 * drm_agp_chipset_flush
3206 i915_gem_object_set_to_gpu_domain(struct drm_gem_object
*obj
,
3207 struct intel_ring_buffer
*ring
,
3208 struct change_domains
*cd
)
3210 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
3211 uint32_t invalidate_domains
= 0;
3212 uint32_t flush_domains
= 0;
3215 * If the object isn't moving to a new write domain,
3216 * let the object stay in multiple read domains
3218 if (obj
->pending_write_domain
== 0)
3219 obj
->pending_read_domains
|= obj
->read_domains
;
3222 * Flush the current write domain if
3223 * the new read domains don't match. Invalidate
3224 * any read domains which differ from the old
3227 if (obj
->write_domain
&&
3228 (obj
->write_domain
!= obj
->pending_read_domains
||
3229 obj_priv
->ring
!= ring
)) {
3230 flush_domains
|= obj
->write_domain
;
3231 invalidate_domains
|=
3232 obj
->pending_read_domains
& ~obj
->write_domain
;
3235 * Invalidate any read caches which may have
3236 * stale data. That is, any new read domains.
3238 invalidate_domains
|= obj
->pending_read_domains
& ~obj
->read_domains
;
3239 if ((flush_domains
| invalidate_domains
) & I915_GEM_DOMAIN_CPU
)
3240 i915_gem_clflush_object(obj
);
3242 /* blow away mappings if mapped through GTT */
3243 if ((flush_domains
| invalidate_domains
) & I915_GEM_DOMAIN_GTT
)
3244 i915_gem_release_mmap(obj
);
3246 /* The actual obj->write_domain will be updated with
3247 * pending_write_domain after we emit the accumulated flush for all
3248 * of our domain changes in execbuffers (which clears objects'
3249 * write_domains). So if we have a current write domain that we
3250 * aren't changing, set pending_write_domain to that.
3252 if (flush_domains
== 0 && obj
->pending_write_domain
== 0)
3253 obj
->pending_write_domain
= obj
->write_domain
;
3255 cd
->invalidate_domains
|= invalidate_domains
;
3256 cd
->flush_domains
|= flush_domains
;
3257 if (flush_domains
& I915_GEM_GPU_DOMAINS
)
3258 cd
->flush_rings
|= obj_priv
->ring
->id
;
3259 if (invalidate_domains
& I915_GEM_GPU_DOMAINS
)
3260 cd
->flush_rings
|= ring
->id
;
3264 * Moves the object from a partially CPU read to a full one.
3266 * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3267 * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
3270 i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object
*obj
)
3272 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
3274 if (!obj_priv
->page_cpu_valid
)
3277 /* If we're partially in the CPU read domain, finish moving it in.
3279 if (obj
->read_domains
& I915_GEM_DOMAIN_CPU
) {
3282 for (i
= 0; i
<= (obj
->size
- 1) / PAGE_SIZE
; i
++) {
3283 if (obj_priv
->page_cpu_valid
[i
])
3285 drm_clflush_pages(obj_priv
->pages
+ i
, 1);
3289 /* Free the page_cpu_valid mappings which are now stale, whether
3290 * or not we've got I915_GEM_DOMAIN_CPU.
3292 kfree(obj_priv
->page_cpu_valid
);
3293 obj_priv
->page_cpu_valid
= NULL
;
3297 * Set the CPU read domain on a range of the object.
3299 * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3300 * not entirely valid. The page_cpu_valid member of the object flags which
3301 * pages have been flushed, and will be respected by
3302 * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3303 * of the whole object.
3305 * This function returns when the move is complete, including waiting on
3309 i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object
*obj
,
3310 uint64_t offset
, uint64_t size
)
3312 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
3313 uint32_t old_read_domains
;
3316 if (offset
== 0 && size
== obj
->size
)
3317 return i915_gem_object_set_to_cpu_domain(obj
, 0);
3319 ret
= i915_gem_object_flush_gpu_write_domain(obj
, false);
3322 i915_gem_object_flush_gtt_write_domain(obj
);
3324 /* If we're already fully in the CPU read domain, we're done. */
3325 if (obj_priv
->page_cpu_valid
== NULL
&&
3326 (obj
->read_domains
& I915_GEM_DOMAIN_CPU
) != 0)
3329 /* Otherwise, create/clear the per-page CPU read domain flag if we're
3330 * newly adding I915_GEM_DOMAIN_CPU
3332 if (obj_priv
->page_cpu_valid
== NULL
) {
3333 obj_priv
->page_cpu_valid
= kzalloc(obj
->size
/ PAGE_SIZE
,
3335 if (obj_priv
->page_cpu_valid
== NULL
)
3337 } else if ((obj
->read_domains
& I915_GEM_DOMAIN_CPU
) == 0)
3338 memset(obj_priv
->page_cpu_valid
, 0, obj
->size
/ PAGE_SIZE
);
3340 /* Flush the cache on any pages that are still invalid from the CPU's
3343 for (i
= offset
/ PAGE_SIZE
; i
<= (offset
+ size
- 1) / PAGE_SIZE
;
3345 if (obj_priv
->page_cpu_valid
[i
])
3348 drm_clflush_pages(obj_priv
->pages
+ i
, 1);
3350 obj_priv
->page_cpu_valid
[i
] = 1;
3353 /* It should now be out of any other write domains, and we can update
3354 * the domain values for our changes.
3356 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
3358 old_read_domains
= obj
->read_domains
;
3359 obj
->read_domains
|= I915_GEM_DOMAIN_CPU
;
3361 trace_i915_gem_object_change_domain(obj
,
3369 i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object
*obj
,
3370 struct drm_file
*file_priv
,
3371 struct drm_i915_gem_exec_object2
*entry
,
3372 struct drm_i915_gem_relocation_entry
*reloc
)
3374 struct drm_device
*dev
= obj
->base
.dev
;
3375 struct drm_gem_object
*target_obj
;
3376 uint32_t target_offset
;
3379 target_obj
= drm_gem_object_lookup(dev
, file_priv
,
3380 reloc
->target_handle
);
3381 if (target_obj
== NULL
)
3384 target_offset
= to_intel_bo(target_obj
)->gtt_offset
;
3387 DRM_INFO("%s: obj %p offset %08x target %d "
3388 "read %08x write %08x gtt %08x "
3389 "presumed %08x delta %08x\n",
3392 (int) reloc
->offset
,
3393 (int) reloc
->target_handle
,
3394 (int) reloc
->read_domains
,
3395 (int) reloc
->write_domain
,
3396 (int) target_offset
,
3397 (int) reloc
->presumed_offset
,
3401 /* The target buffer should have appeared before us in the
3402 * exec_object list, so it should have a GTT space bound by now.
3404 if (target_offset
== 0) {
3405 DRM_ERROR("No GTT space found for object %d\n",
3406 reloc
->target_handle
);
3410 /* Validate that the target is in a valid r/w GPU domain */
3411 if (reloc
->write_domain
& (reloc
->write_domain
- 1)) {
3412 DRM_ERROR("reloc with multiple write domains: "
3413 "obj %p target %d offset %d "
3414 "read %08x write %08x",
3415 obj
, reloc
->target_handle
,
3416 (int) reloc
->offset
,
3417 reloc
->read_domains
,
3418 reloc
->write_domain
);
3421 if (reloc
->write_domain
& I915_GEM_DOMAIN_CPU
||
3422 reloc
->read_domains
& I915_GEM_DOMAIN_CPU
) {
3423 DRM_ERROR("reloc with read/write CPU domains: "
3424 "obj %p target %d offset %d "
3425 "read %08x write %08x",
3426 obj
, reloc
->target_handle
,
3427 (int) reloc
->offset
,
3428 reloc
->read_domains
,
3429 reloc
->write_domain
);
3432 if (reloc
->write_domain
&& target_obj
->pending_write_domain
&&
3433 reloc
->write_domain
!= target_obj
->pending_write_domain
) {
3434 DRM_ERROR("Write domain conflict: "
3435 "obj %p target %d offset %d "
3436 "new %08x old %08x\n",
3437 obj
, reloc
->target_handle
,
3438 (int) reloc
->offset
,
3439 reloc
->write_domain
,
3440 target_obj
->pending_write_domain
);
3444 target_obj
->pending_read_domains
|= reloc
->read_domains
;
3445 target_obj
->pending_write_domain
|= reloc
->write_domain
;
3447 /* If the relocation already has the right value in it, no
3448 * more work needs to be done.
3450 if (target_offset
== reloc
->presumed_offset
)
3453 /* Check that the relocation address is valid... */
3454 if (reloc
->offset
> obj
->base
.size
- 4) {
3455 DRM_ERROR("Relocation beyond object bounds: "
3456 "obj %p target %d offset %d size %d.\n",
3457 obj
, reloc
->target_handle
,
3458 (int) reloc
->offset
,
3459 (int) obj
->base
.size
);
3462 if (reloc
->offset
& 3) {
3463 DRM_ERROR("Relocation not 4-byte aligned: "
3464 "obj %p target %d offset %d.\n",
3465 obj
, reloc
->target_handle
,
3466 (int) reloc
->offset
);
3470 /* and points to somewhere within the target object. */
3471 if (reloc
->delta
>= target_obj
->size
) {
3472 DRM_ERROR("Relocation beyond target object bounds: "
3473 "obj %p target %d delta %d size %d.\n",
3474 obj
, reloc
->target_handle
,
3476 (int) target_obj
->size
);
3480 reloc
->delta
+= target_offset
;
3481 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_CPU
) {
3482 uint32_t page_offset
= reloc
->offset
& ~PAGE_MASK
;
3485 vaddr
= kmap_atomic(obj
->pages
[reloc
->offset
>> PAGE_SHIFT
]);
3486 *(uint32_t *)(vaddr
+ page_offset
) = reloc
->delta
;
3487 kunmap_atomic(vaddr
);
3489 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3490 uint32_t __iomem
*reloc_entry
;
3491 void __iomem
*reloc_page
;
3493 ret
= i915_gem_object_set_to_gtt_domain(&obj
->base
, 1);
3497 /* Map the page containing the relocation we're going to perform. */
3498 reloc
->offset
+= obj
->gtt_offset
;
3499 reloc_page
= io_mapping_map_atomic_wc(dev_priv
->mm
.gtt_mapping
,
3500 reloc
->offset
& PAGE_MASK
);
3501 reloc_entry
= (uint32_t __iomem
*)
3502 (reloc_page
+ (reloc
->offset
& ~PAGE_MASK
));
3503 iowrite32(reloc
->delta
, reloc_entry
);
3504 io_mapping_unmap_atomic(reloc_page
);
3507 /* and update the user's relocation entry */
3508 reloc
->presumed_offset
= target_offset
;
3513 drm_gem_object_unreference(target_obj
);
3518 i915_gem_execbuffer_relocate_object(struct drm_i915_gem_object
*obj
,
3519 struct drm_file
*file_priv
,
3520 struct drm_i915_gem_exec_object2
*entry
)
3522 struct drm_i915_gem_relocation_entry __user
*user_relocs
;
3525 user_relocs
= (void __user
*)(uintptr_t)entry
->relocs_ptr
;
3526 for (i
= 0; i
< entry
->relocation_count
; i
++) {
3527 struct drm_i915_gem_relocation_entry reloc
;
3529 if (__copy_from_user_inatomic(&reloc
,
3534 ret
= i915_gem_execbuffer_relocate_entry(obj
, file_priv
, entry
, &reloc
);
3538 if (__copy_to_user_inatomic(&user_relocs
[i
].presumed_offset
,
3539 &reloc
.presumed_offset
,
3540 sizeof(reloc
.presumed_offset
)))
3548 i915_gem_execbuffer_relocate_object_slow(struct drm_i915_gem_object
*obj
,
3549 struct drm_file
*file_priv
,
3550 struct drm_i915_gem_exec_object2
*entry
,
3551 struct drm_i915_gem_relocation_entry
*relocs
)
3555 for (i
= 0; i
< entry
->relocation_count
; i
++) {
3556 ret
= i915_gem_execbuffer_relocate_entry(obj
, file_priv
, entry
, &relocs
[i
]);
3565 i915_gem_execbuffer_relocate(struct drm_device
*dev
,
3566 struct drm_file
*file
,
3567 struct drm_gem_object
**object_list
,
3568 struct drm_i915_gem_exec_object2
*exec_list
,
3573 for (i
= 0; i
< count
; i
++) {
3574 struct drm_i915_gem_object
*obj
= to_intel_bo(object_list
[i
]);
3575 obj
->base
.pending_read_domains
= 0;
3576 obj
->base
.pending_write_domain
= 0;
3577 ret
= i915_gem_execbuffer_relocate_object(obj
, file
,
3587 i915_gem_execbuffer_reserve(struct drm_device
*dev
,
3588 struct drm_file
*file
,
3589 struct drm_gem_object
**object_list
,
3590 struct drm_i915_gem_exec_object2
*exec_list
,
3593 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3596 /* attempt to pin all of the buffers into the GTT */
3600 for (i
= 0; i
< count
; i
++) {
3601 struct drm_i915_gem_exec_object2
*entry
= &exec_list
[i
];
3602 struct drm_i915_gem_object
*obj
= to_intel_bo(object_list
[i
]);
3604 entry
->flags
& EXEC_OBJECT_NEEDS_FENCE
&&
3605 obj
->tiling_mode
!= I915_TILING_NONE
;
3607 /* g33/pnv can't fence buffers in the unmappable part */
3608 bool need_mappable
=
3609 entry
->relocation_count
? true : need_fence
;
3611 /* Check fence reg constraints and rebind if necessary */
3612 if (need_mappable
&& !obj
->map_and_fenceable
) {
3613 ret
= i915_gem_object_unbind(&obj
->base
);
3618 ret
= i915_gem_object_pin(&obj
->base
,
3625 * Pre-965 chips need a fence register set up in order
3626 * to properly handle blits to/from tiled surfaces.
3629 ret
= i915_gem_object_get_fence_reg(&obj
->base
, true);
3631 i915_gem_object_unpin(&obj
->base
);
3635 dev_priv
->fence_regs
[obj
->fence_reg
].gpu
= true;
3638 entry
->offset
= obj
->gtt_offset
;
3642 i915_gem_object_unpin(object_list
[i
]);
3644 if (ret
!= -ENOSPC
|| retry
> 1)
3647 /* First attempt, just clear anything that is purgeable.
3648 * Second attempt, clear the entire GTT.
3650 ret
= i915_gem_evict_everything(dev
, retry
== 0);
3659 i915_gem_execbuffer_relocate_slow(struct drm_device
*dev
,
3660 struct drm_file
*file
,
3661 struct drm_gem_object
**object_list
,
3662 struct drm_i915_gem_exec_object2
*exec_list
,
3665 struct drm_i915_gem_relocation_entry
*reloc
;
3668 for (i
= 0; i
< count
; i
++) {
3669 struct drm_i915_gem_object
*obj
= to_intel_bo(object_list
[i
]);
3670 obj
->in_execbuffer
= false;
3673 mutex_unlock(&dev
->struct_mutex
);
3676 for (i
= 0; i
< count
; i
++)
3677 total
+= exec_list
[i
].relocation_count
;
3679 reloc
= drm_malloc_ab(total
, sizeof(*reloc
));
3680 if (reloc
== NULL
) {
3681 mutex_lock(&dev
->struct_mutex
);
3686 for (i
= 0; i
< count
; i
++) {
3687 struct drm_i915_gem_relocation_entry __user
*user_relocs
;
3689 user_relocs
= (void __user
*)(uintptr_t)exec_list
[i
].relocs_ptr
;
3691 if (copy_from_user(reloc
+total
, user_relocs
,
3692 exec_list
[i
].relocation_count
*
3695 mutex_lock(&dev
->struct_mutex
);
3699 total
+= exec_list
[i
].relocation_count
;
3702 ret
= i915_mutex_lock_interruptible(dev
);
3704 mutex_lock(&dev
->struct_mutex
);
3708 ret
= i915_gem_execbuffer_reserve(dev
, file
,
3709 object_list
, exec_list
,
3715 for (i
= 0; i
< count
; i
++) {
3716 struct drm_i915_gem_object
*obj
= to_intel_bo(object_list
[i
]);
3717 obj
->base
.pending_read_domains
= 0;
3718 obj
->base
.pending_write_domain
= 0;
3719 ret
= i915_gem_execbuffer_relocate_object_slow(obj
, file
,
3725 total
+= exec_list
[i
].relocation_count
;
3728 /* Leave the user relocations as are, this is the painfully slow path,
3729 * and we want to avoid the complication of dropping the lock whilst
3730 * having buffers reserved in the aperture and so causing spurious
3731 * ENOSPC for random operations.
3735 drm_free_large(reloc
);
3740 i915_gem_execbuffer_move_to_gpu(struct drm_device
*dev
,
3741 struct drm_file
*file
,
3742 struct intel_ring_buffer
*ring
,
3743 struct drm_gem_object
**objects
,
3746 struct change_domains cd
;
3749 cd
.invalidate_domains
= 0;
3750 cd
.flush_domains
= 0;
3752 for (i
= 0; i
< count
; i
++)
3753 i915_gem_object_set_to_gpu_domain(objects
[i
], ring
, &cd
);
3755 if (cd
.invalidate_domains
| cd
.flush_domains
) {
3757 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
3759 cd
.invalidate_domains
,
3762 i915_gem_flush(dev
, file
,
3763 cd
.invalidate_domains
,
3768 for (i
= 0; i
< count
; i
++) {
3769 struct drm_i915_gem_object
*obj
= to_intel_bo(objects
[i
]);
3770 /* XXX replace with semaphores */
3771 if (obj
->ring
&& ring
!= obj
->ring
) {
3772 ret
= i915_gem_object_wait_rendering(&obj
->base
, true);
3781 /* Throttle our rendering by waiting until the ring has completed our requests
3782 * emitted over 20 msec ago.
3784 * Note that if we were to use the current jiffies each time around the loop,
3785 * we wouldn't escape the function with any frames outstanding if the time to
3786 * render a frame was over 20ms.
3788 * This should get us reasonable parallelism between CPU and GPU but also
3789 * relatively low latency when blocking on a particular request to finish.
3792 i915_gem_ring_throttle(struct drm_device
*dev
, struct drm_file
*file
)
3794 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3795 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
3796 unsigned long recent_enough
= jiffies
- msecs_to_jiffies(20);
3797 struct drm_i915_gem_request
*request
;
3798 struct intel_ring_buffer
*ring
= NULL
;
3802 spin_lock(&file_priv
->mm
.lock
);
3803 list_for_each_entry(request
, &file_priv
->mm
.request_list
, client_list
) {
3804 if (time_after_eq(request
->emitted_jiffies
, recent_enough
))
3807 ring
= request
->ring
;
3808 seqno
= request
->seqno
;
3810 spin_unlock(&file_priv
->mm
.lock
);
3816 if (!i915_seqno_passed(ring
->get_seqno(ring
), seqno
)) {
3817 /* And wait for the seqno passing without holding any locks and
3818 * causing extra latency for others. This is safe as the irq
3819 * generation is designed to be run atomically and so is
3822 ring
->user_irq_get(ring
);
3823 ret
= wait_event_interruptible(ring
->irq_queue
,
3824 i915_seqno_passed(ring
->get_seqno(ring
), seqno
)
3825 || atomic_read(&dev_priv
->mm
.wedged
));
3826 ring
->user_irq_put(ring
);
3828 if (ret
== 0 && atomic_read(&dev_priv
->mm
.wedged
))
3833 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, 0);
3839 i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2
*exec
,
3840 uint64_t exec_offset
)
3842 uint32_t exec_start
, exec_len
;
3844 exec_start
= (uint32_t) exec_offset
+ exec
->batch_start_offset
;
3845 exec_len
= (uint32_t) exec
->batch_len
;
3847 if ((exec_start
| exec_len
) & 0x7)
3857 validate_exec_list(struct drm_i915_gem_exec_object2
*exec
,
3862 for (i
= 0; i
< count
; i
++) {
3863 char __user
*ptr
= (char __user
*)(uintptr_t)exec
[i
].relocs_ptr
;
3864 int length
; /* limited by fault_in_pages_readable() */
3866 /* First check for malicious input causing overflow */
3867 if (exec
[i
].relocation_count
>
3868 INT_MAX
/ sizeof(struct drm_i915_gem_relocation_entry
))
3871 length
= exec
[i
].relocation_count
*
3872 sizeof(struct drm_i915_gem_relocation_entry
);
3873 if (!access_ok(VERIFY_READ
, ptr
, length
))
3876 /* we may also need to update the presumed offsets */
3877 if (!access_ok(VERIFY_WRITE
, ptr
, length
))
3880 if (fault_in_pages_readable(ptr
, length
))
3888 i915_gem_do_execbuffer(struct drm_device
*dev
, void *data
,
3889 struct drm_file
*file
,
3890 struct drm_i915_gem_execbuffer2
*args
,
3891 struct drm_i915_gem_exec_object2
*exec_list
)
3893 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3894 struct drm_gem_object
**object_list
= NULL
;
3895 struct drm_gem_object
*batch_obj
;
3896 struct drm_clip_rect
*cliprects
= NULL
;
3897 struct drm_i915_gem_request
*request
= NULL
;
3899 uint64_t exec_offset
;
3901 struct intel_ring_buffer
*ring
= NULL
;
3903 ret
= i915_gem_check_is_wedged(dev
);
3907 ret
= validate_exec_list(exec_list
, args
->buffer_count
);
3912 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3913 (int) args
->buffers_ptr
, args
->buffer_count
, args
->batch_len
);
3915 switch (args
->flags
& I915_EXEC_RING_MASK
) {
3916 case I915_EXEC_DEFAULT
:
3917 case I915_EXEC_RENDER
:
3918 ring
= &dev_priv
->render_ring
;
3921 if (!HAS_BSD(dev
)) {
3922 DRM_ERROR("execbuf with invalid ring (BSD)\n");
3925 ring
= &dev_priv
->bsd_ring
;
3928 if (!HAS_BLT(dev
)) {
3929 DRM_ERROR("execbuf with invalid ring (BLT)\n");
3932 ring
= &dev_priv
->blt_ring
;
3935 DRM_ERROR("execbuf with unknown ring: %d\n",
3936 (int)(args
->flags
& I915_EXEC_RING_MASK
));
3940 if (args
->buffer_count
< 1) {
3941 DRM_ERROR("execbuf with %d buffers\n", args
->buffer_count
);
3944 object_list
= drm_malloc_ab(sizeof(*object_list
), args
->buffer_count
);
3945 if (object_list
== NULL
) {
3946 DRM_ERROR("Failed to allocate object list for %d buffers\n",
3947 args
->buffer_count
);
3952 if (args
->num_cliprects
!= 0) {
3953 cliprects
= kcalloc(args
->num_cliprects
, sizeof(*cliprects
),
3955 if (cliprects
== NULL
) {
3960 ret
= copy_from_user(cliprects
,
3961 (struct drm_clip_rect __user
*)
3962 (uintptr_t) args
->cliprects_ptr
,
3963 sizeof(*cliprects
) * args
->num_cliprects
);
3965 DRM_ERROR("copy %d cliprects failed: %d\n",
3966 args
->num_cliprects
, ret
);
3972 request
= kzalloc(sizeof(*request
), GFP_KERNEL
);
3973 if (request
== NULL
) {
3978 ret
= i915_mutex_lock_interruptible(dev
);
3982 if (dev_priv
->mm
.suspended
) {
3983 mutex_unlock(&dev
->struct_mutex
);
3988 /* Look up object handles */
3989 for (i
= 0; i
< args
->buffer_count
; i
++) {
3990 struct drm_i915_gem_object
*obj_priv
;
3992 object_list
[i
] = drm_gem_object_lookup(dev
, file
,
3993 exec_list
[i
].handle
);
3994 if (object_list
[i
] == NULL
) {
3995 DRM_ERROR("Invalid object handle %d at index %d\n",
3996 exec_list
[i
].handle
, i
);
3997 /* prevent error path from reading uninitialized data */
3998 args
->buffer_count
= i
+ 1;
4003 obj_priv
= to_intel_bo(object_list
[i
]);
4004 if (obj_priv
->in_execbuffer
) {
4005 DRM_ERROR("Object %p appears more than once in object list\n",
4007 /* prevent error path from reading uninitialized data */
4008 args
->buffer_count
= i
+ 1;
4012 obj_priv
->in_execbuffer
= true;
4015 /* Move the objects en-masse into the GTT, evicting if necessary. */
4016 ret
= i915_gem_execbuffer_reserve(dev
, file
,
4017 object_list
, exec_list
,
4018 args
->buffer_count
);
4022 /* The objects are in their final locations, apply the relocations. */
4023 ret
= i915_gem_execbuffer_relocate(dev
, file
,
4024 object_list
, exec_list
,
4025 args
->buffer_count
);
4027 if (ret
== -EFAULT
) {
4028 ret
= i915_gem_execbuffer_relocate_slow(dev
, file
,
4031 args
->buffer_count
);
4032 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
4038 /* Set the pending read domains for the batch buffer to COMMAND */
4039 batch_obj
= object_list
[args
->buffer_count
-1];
4040 if (batch_obj
->pending_write_domain
) {
4041 DRM_ERROR("Attempting to use self-modifying batch buffer\n");
4045 batch_obj
->pending_read_domains
|= I915_GEM_DOMAIN_COMMAND
;
4047 /* Sanity check the batch buffer */
4048 exec_offset
= to_intel_bo(batch_obj
)->gtt_offset
;
4049 ret
= i915_gem_check_execbuffer(args
, exec_offset
);
4051 DRM_ERROR("execbuf with invalid offset/length\n");
4055 ret
= i915_gem_execbuffer_move_to_gpu(dev
, file
, ring
,
4056 object_list
, args
->buffer_count
);
4061 for (i
= 0; i
< args
->buffer_count
; i
++) {
4062 i915_gem_object_check_coherency(object_list
[i
],
4063 exec_list
[i
].handle
);
4068 i915_gem_dump_object(batch_obj
,
4074 /* Check for any pending flips. As we only maintain a flip queue depth
4075 * of 1, we can simply insert a WAIT for the next display flip prior
4076 * to executing the batch and avoid stalling the CPU.
4079 for (i
= 0; i
< args
->buffer_count
; i
++) {
4080 if (object_list
[i
]->write_domain
)
4081 flips
|= atomic_read(&to_intel_bo(object_list
[i
])->pending_flip
);
4084 int plane
, flip_mask
;
4086 for (plane
= 0; flips
>> plane
; plane
++) {
4087 if (((flips
>> plane
) & 1) == 0)
4091 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
4093 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
4095 ret
= intel_ring_begin(ring
, 2);
4099 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
4100 intel_ring_emit(ring
, MI_NOOP
);
4101 intel_ring_advance(ring
);
4105 /* Exec the batchbuffer */
4106 ret
= ring
->dispatch_execbuffer(ring
, args
, cliprects
, exec_offset
);
4108 DRM_ERROR("dispatch failed %d\n", ret
);
4112 for (i
= 0; i
< args
->buffer_count
; i
++) {
4113 struct drm_gem_object
*obj
= object_list
[i
];
4115 obj
->read_domains
= obj
->pending_read_domains
;
4116 obj
->write_domain
= obj
->pending_write_domain
;
4118 i915_gem_object_move_to_active(obj
, ring
);
4119 if (obj
->write_domain
) {
4120 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
4121 obj_priv
->dirty
= 1;
4122 list_move_tail(&obj_priv
->gpu_write_list
,
4123 &ring
->gpu_write_list
);
4124 intel_mark_busy(dev
, obj
);
4127 trace_i915_gem_object_change_domain(obj
,
4133 * Ensure that the commands in the batch buffer are
4134 * finished before the interrupt fires
4136 i915_retire_commands(dev
, ring
);
4138 if (i915_add_request(dev
, file
, request
, ring
))
4139 i915_gem_next_request_seqno(dev
, ring
);
4144 for (i
= 0; i
< args
->buffer_count
; i
++) {
4145 if (object_list
[i
] == NULL
)
4148 to_intel_bo(object_list
[i
])->in_execbuffer
= false;
4149 drm_gem_object_unreference(object_list
[i
]);
4152 mutex_unlock(&dev
->struct_mutex
);
4155 drm_free_large(object_list
);
4163 * Legacy execbuffer just creates an exec2 list from the original exec object
4164 * list array and passes it to the real function.
4167 i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
4168 struct drm_file
*file_priv
)
4170 struct drm_i915_gem_execbuffer
*args
= data
;
4171 struct drm_i915_gem_execbuffer2 exec2
;
4172 struct drm_i915_gem_exec_object
*exec_list
= NULL
;
4173 struct drm_i915_gem_exec_object2
*exec2_list
= NULL
;
4177 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
4178 (int) args
->buffers_ptr
, args
->buffer_count
, args
->batch_len
);
4181 if (args
->buffer_count
< 1) {
4182 DRM_ERROR("execbuf with %d buffers\n", args
->buffer_count
);
4186 /* Copy in the exec list from userland */
4187 exec_list
= drm_malloc_ab(sizeof(*exec_list
), args
->buffer_count
);
4188 exec2_list
= drm_malloc_ab(sizeof(*exec2_list
), args
->buffer_count
);
4189 if (exec_list
== NULL
|| exec2_list
== NULL
) {
4190 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
4191 args
->buffer_count
);
4192 drm_free_large(exec_list
);
4193 drm_free_large(exec2_list
);
4196 ret
= copy_from_user(exec_list
,
4197 (struct drm_i915_relocation_entry __user
*)
4198 (uintptr_t) args
->buffers_ptr
,
4199 sizeof(*exec_list
) * args
->buffer_count
);
4201 DRM_ERROR("copy %d exec entries failed %d\n",
4202 args
->buffer_count
, ret
);
4203 drm_free_large(exec_list
);
4204 drm_free_large(exec2_list
);
4208 for (i
= 0; i
< args
->buffer_count
; i
++) {
4209 exec2_list
[i
].handle
= exec_list
[i
].handle
;
4210 exec2_list
[i
].relocation_count
= exec_list
[i
].relocation_count
;
4211 exec2_list
[i
].relocs_ptr
= exec_list
[i
].relocs_ptr
;
4212 exec2_list
[i
].alignment
= exec_list
[i
].alignment
;
4213 exec2_list
[i
].offset
= exec_list
[i
].offset
;
4214 if (INTEL_INFO(dev
)->gen
< 4)
4215 exec2_list
[i
].flags
= EXEC_OBJECT_NEEDS_FENCE
;
4217 exec2_list
[i
].flags
= 0;
4220 exec2
.buffers_ptr
= args
->buffers_ptr
;
4221 exec2
.buffer_count
= args
->buffer_count
;
4222 exec2
.batch_start_offset
= args
->batch_start_offset
;
4223 exec2
.batch_len
= args
->batch_len
;
4224 exec2
.DR1
= args
->DR1
;
4225 exec2
.DR4
= args
->DR4
;
4226 exec2
.num_cliprects
= args
->num_cliprects
;
4227 exec2
.cliprects_ptr
= args
->cliprects_ptr
;
4228 exec2
.flags
= I915_EXEC_RENDER
;
4230 ret
= i915_gem_do_execbuffer(dev
, data
, file_priv
, &exec2
, exec2_list
);
4232 /* Copy the new buffer offsets back to the user's exec list. */
4233 for (i
= 0; i
< args
->buffer_count
; i
++)
4234 exec_list
[i
].offset
= exec2_list
[i
].offset
;
4235 /* ... and back out to userspace */
4236 ret
= copy_to_user((struct drm_i915_relocation_entry __user
*)
4237 (uintptr_t) args
->buffers_ptr
,
4239 sizeof(*exec_list
) * args
->buffer_count
);
4242 DRM_ERROR("failed to copy %d exec entries "
4243 "back to user (%d)\n",
4244 args
->buffer_count
, ret
);
4248 drm_free_large(exec_list
);
4249 drm_free_large(exec2_list
);
4254 i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
4255 struct drm_file
*file_priv
)
4257 struct drm_i915_gem_execbuffer2
*args
= data
;
4258 struct drm_i915_gem_exec_object2
*exec2_list
= NULL
;
4262 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
4263 (int) args
->buffers_ptr
, args
->buffer_count
, args
->batch_len
);
4266 if (args
->buffer_count
< 1) {
4267 DRM_ERROR("execbuf2 with %d buffers\n", args
->buffer_count
);
4271 exec2_list
= drm_malloc_ab(sizeof(*exec2_list
), args
->buffer_count
);
4272 if (exec2_list
== NULL
) {
4273 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
4274 args
->buffer_count
);
4277 ret
= copy_from_user(exec2_list
,
4278 (struct drm_i915_relocation_entry __user
*)
4279 (uintptr_t) args
->buffers_ptr
,
4280 sizeof(*exec2_list
) * args
->buffer_count
);
4282 DRM_ERROR("copy %d exec entries failed %d\n",
4283 args
->buffer_count
, ret
);
4284 drm_free_large(exec2_list
);
4288 ret
= i915_gem_do_execbuffer(dev
, data
, file_priv
, args
, exec2_list
);
4290 /* Copy the new buffer offsets back to the user's exec list. */
4291 ret
= copy_to_user((struct drm_i915_relocation_entry __user
*)
4292 (uintptr_t) args
->buffers_ptr
,
4294 sizeof(*exec2_list
) * args
->buffer_count
);
4297 DRM_ERROR("failed to copy %d exec entries "
4298 "back to user (%d)\n",
4299 args
->buffer_count
, ret
);
4303 drm_free_large(exec2_list
);
4308 i915_gem_object_pin(struct drm_gem_object
*obj
, uint32_t alignment
,
4309 bool map_and_fenceable
)
4311 struct drm_device
*dev
= obj
->dev
;
4312 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4313 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
4316 BUG_ON(obj_priv
->pin_count
== DRM_I915_GEM_OBJECT_MAX_PIN_COUNT
);
4317 BUG_ON(map_and_fenceable
&& !map_and_fenceable
);
4318 WARN_ON(i915_verify_lists(dev
));
4320 if (obj_priv
->gtt_space
!= NULL
) {
4321 if ((alignment
&& obj_priv
->gtt_offset
& (alignment
- 1)) ||
4322 (map_and_fenceable
&& !obj_priv
->map_and_fenceable
)) {
4323 WARN(obj_priv
->pin_count
,
4324 "bo is already pinned with incorrect alignment:"
4325 " offset=%x, req.alignment=%x, req.map_and_fenceable=%d,"
4326 " obj->map_and_fenceable=%d\n",
4327 obj_priv
->gtt_offset
, alignment
,
4329 obj_priv
->map_and_fenceable
);
4330 ret
= i915_gem_object_unbind(obj
);
4336 if (obj_priv
->gtt_space
== NULL
) {
4337 ret
= i915_gem_object_bind_to_gtt(obj
, alignment
,
4343 if (obj_priv
->pin_count
++ == 0) {
4344 i915_gem_info_add_pin(dev_priv
, obj_priv
, map_and_fenceable
);
4345 if (!obj_priv
->active
)
4346 list_move_tail(&obj_priv
->mm_list
,
4347 &dev_priv
->mm
.pinned_list
);
4349 BUG_ON(!obj_priv
->pin_mappable
&& map_and_fenceable
);
4351 WARN_ON(i915_verify_lists(dev
));
4356 i915_gem_object_unpin(struct drm_gem_object
*obj
)
4358 struct drm_device
*dev
= obj
->dev
;
4359 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4360 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
4362 WARN_ON(i915_verify_lists(dev
));
4363 BUG_ON(obj_priv
->pin_count
== 0);
4364 BUG_ON(obj_priv
->gtt_space
== NULL
);
4366 if (--obj_priv
->pin_count
== 0) {
4367 if (!obj_priv
->active
)
4368 list_move_tail(&obj_priv
->mm_list
,
4369 &dev_priv
->mm
.inactive_list
);
4370 i915_gem_info_remove_pin(dev_priv
, obj_priv
);
4372 WARN_ON(i915_verify_lists(dev
));
4376 i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
4377 struct drm_file
*file_priv
)
4379 struct drm_i915_gem_pin
*args
= data
;
4380 struct drm_gem_object
*obj
;
4381 struct drm_i915_gem_object
*obj_priv
;
4384 ret
= i915_mutex_lock_interruptible(dev
);
4388 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4393 obj_priv
= to_intel_bo(obj
);
4395 if (obj_priv
->madv
!= I915_MADV_WILLNEED
) {
4396 DRM_ERROR("Attempting to pin a purgeable buffer\n");
4401 if (obj_priv
->pin_filp
!= NULL
&& obj_priv
->pin_filp
!= file_priv
) {
4402 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
4408 obj_priv
->user_pin_count
++;
4409 obj_priv
->pin_filp
= file_priv
;
4410 if (obj_priv
->user_pin_count
== 1) {
4411 ret
= i915_gem_object_pin(obj
, args
->alignment
, true);
4416 /* XXX - flush the CPU caches for pinned objects
4417 * as the X server doesn't manage domains yet
4419 i915_gem_object_flush_cpu_write_domain(obj
);
4420 args
->offset
= obj_priv
->gtt_offset
;
4422 drm_gem_object_unreference(obj
);
4424 mutex_unlock(&dev
->struct_mutex
);
4429 i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
4430 struct drm_file
*file_priv
)
4432 struct drm_i915_gem_pin
*args
= data
;
4433 struct drm_gem_object
*obj
;
4434 struct drm_i915_gem_object
*obj_priv
;
4437 ret
= i915_mutex_lock_interruptible(dev
);
4441 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4446 obj_priv
= to_intel_bo(obj
);
4448 if (obj_priv
->pin_filp
!= file_priv
) {
4449 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4454 obj_priv
->user_pin_count
--;
4455 if (obj_priv
->user_pin_count
== 0) {
4456 obj_priv
->pin_filp
= NULL
;
4457 i915_gem_object_unpin(obj
);
4461 drm_gem_object_unreference(obj
);
4463 mutex_unlock(&dev
->struct_mutex
);
4468 i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
4469 struct drm_file
*file_priv
)
4471 struct drm_i915_gem_busy
*args
= data
;
4472 struct drm_gem_object
*obj
;
4473 struct drm_i915_gem_object
*obj_priv
;
4476 ret
= i915_mutex_lock_interruptible(dev
);
4480 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4485 obj_priv
= to_intel_bo(obj
);
4487 /* Count all active objects as busy, even if they are currently not used
4488 * by the gpu. Users of this interface expect objects to eventually
4489 * become non-busy without any further actions, therefore emit any
4490 * necessary flushes here.
4492 args
->busy
= obj_priv
->active
;
4494 /* Unconditionally flush objects, even when the gpu still uses this
4495 * object. Userspace calling this function indicates that it wants to
4496 * use this buffer rather sooner than later, so issuing the required
4497 * flush earlier is beneficial.
4499 if (obj
->write_domain
& I915_GEM_GPU_DOMAINS
)
4500 i915_gem_flush_ring(dev
, file_priv
,
4502 0, obj
->write_domain
);
4504 /* Update the active list for the hardware's current position.
4505 * Otherwise this only updates on a delayed timer or when irqs
4506 * are actually unmasked, and our working set ends up being
4507 * larger than required.
4509 i915_gem_retire_requests_ring(dev
, obj_priv
->ring
);
4511 args
->busy
= obj_priv
->active
;
4514 drm_gem_object_unreference(obj
);
4516 mutex_unlock(&dev
->struct_mutex
);
4521 i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
4522 struct drm_file
*file_priv
)
4524 return i915_gem_ring_throttle(dev
, file_priv
);
4528 i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
4529 struct drm_file
*file_priv
)
4531 struct drm_i915_gem_madvise
*args
= data
;
4532 struct drm_gem_object
*obj
;
4533 struct drm_i915_gem_object
*obj_priv
;
4536 switch (args
->madv
) {
4537 case I915_MADV_DONTNEED
:
4538 case I915_MADV_WILLNEED
:
4544 ret
= i915_mutex_lock_interruptible(dev
);
4548 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4553 obj_priv
= to_intel_bo(obj
);
4555 if (obj_priv
->pin_count
) {
4560 if (obj_priv
->madv
!= __I915_MADV_PURGED
)
4561 obj_priv
->madv
= args
->madv
;
4563 /* if the object is no longer bound, discard its backing storage */
4564 if (i915_gem_object_is_purgeable(obj_priv
) &&
4565 obj_priv
->gtt_space
== NULL
)
4566 i915_gem_object_truncate(obj
);
4568 args
->retained
= obj_priv
->madv
!= __I915_MADV_PURGED
;
4571 drm_gem_object_unreference(obj
);
4573 mutex_unlock(&dev
->struct_mutex
);
4577 struct drm_gem_object
* i915_gem_alloc_object(struct drm_device
*dev
,
4580 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4581 struct drm_i915_gem_object
*obj
;
4583 obj
= kzalloc(sizeof(*obj
), GFP_KERNEL
);
4587 if (drm_gem_object_init(dev
, &obj
->base
, size
) != 0) {
4592 i915_gem_info_add_obj(dev_priv
, size
);
4594 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
4595 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
4597 obj
->agp_type
= AGP_USER_MEMORY
;
4598 obj
->base
.driver_private
= NULL
;
4599 obj
->fence_reg
= I915_FENCE_REG_NONE
;
4600 INIT_LIST_HEAD(&obj
->mm_list
);
4601 INIT_LIST_HEAD(&obj
->gtt_list
);
4602 INIT_LIST_HEAD(&obj
->ring_list
);
4603 INIT_LIST_HEAD(&obj
->gpu_write_list
);
4604 obj
->madv
= I915_MADV_WILLNEED
;
4605 /* Avoid an unnecessary call to unbind on the first bind. */
4606 obj
->map_and_fenceable
= true;
4611 int i915_gem_init_object(struct drm_gem_object
*obj
)
4618 static void i915_gem_free_object_tail(struct drm_gem_object
*obj
)
4620 struct drm_device
*dev
= obj
->dev
;
4621 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4622 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
4625 ret
= i915_gem_object_unbind(obj
);
4626 if (ret
== -ERESTARTSYS
) {
4627 list_move(&obj_priv
->mm_list
,
4628 &dev_priv
->mm
.deferred_free_list
);
4632 if (obj
->map_list
.map
)
4633 i915_gem_free_mmap_offset(obj
);
4635 drm_gem_object_release(obj
);
4636 i915_gem_info_remove_obj(dev_priv
, obj
->size
);
4638 kfree(obj_priv
->page_cpu_valid
);
4639 kfree(obj_priv
->bit_17
);
4643 void i915_gem_free_object(struct drm_gem_object
*obj
)
4645 struct drm_device
*dev
= obj
->dev
;
4646 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
4648 trace_i915_gem_object_destroy(obj
);
4650 while (obj_priv
->pin_count
> 0)
4651 i915_gem_object_unpin(obj
);
4653 if (obj_priv
->phys_obj
)
4654 i915_gem_detach_phys_object(dev
, obj
);
4656 i915_gem_free_object_tail(obj
);
4660 i915_gem_idle(struct drm_device
*dev
)
4662 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4665 mutex_lock(&dev
->struct_mutex
);
4667 if (dev_priv
->mm
.suspended
) {
4668 mutex_unlock(&dev
->struct_mutex
);
4672 ret
= i915_gpu_idle(dev
);
4674 mutex_unlock(&dev
->struct_mutex
);
4678 /* Under UMS, be paranoid and evict. */
4679 if (!drm_core_check_feature(dev
, DRIVER_MODESET
)) {
4680 ret
= i915_gem_evict_inactive(dev
, false);
4682 mutex_unlock(&dev
->struct_mutex
);
4687 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4688 * We need to replace this with a semaphore, or something.
4689 * And not confound mm.suspended!
4691 dev_priv
->mm
.suspended
= 1;
4692 del_timer_sync(&dev_priv
->hangcheck_timer
);
4694 i915_kernel_lost_context(dev
);
4695 i915_gem_cleanup_ringbuffer(dev
);
4697 mutex_unlock(&dev
->struct_mutex
);
4699 /* Cancel the retire work handler, which should be idle now. */
4700 cancel_delayed_work_sync(&dev_priv
->mm
.retire_work
);
4706 * 965+ support PIPE_CONTROL commands, which provide finer grained control
4707 * over cache flushing.
4710 i915_gem_init_pipe_control(struct drm_device
*dev
)
4712 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4713 struct drm_gem_object
*obj
;
4714 struct drm_i915_gem_object
*obj_priv
;
4717 obj
= i915_gem_alloc_object(dev
, 4096);
4719 DRM_ERROR("Failed to allocate seqno page\n");
4723 obj_priv
= to_intel_bo(obj
);
4724 obj_priv
->agp_type
= AGP_USER_CACHED_MEMORY
;
4726 ret
= i915_gem_object_pin(obj
, 4096, true);
4730 dev_priv
->seqno_gfx_addr
= obj_priv
->gtt_offset
;
4731 dev_priv
->seqno_page
= kmap(obj_priv
->pages
[0]);
4732 if (dev_priv
->seqno_page
== NULL
)
4735 dev_priv
->seqno_obj
= obj
;
4736 memset(dev_priv
->seqno_page
, 0, PAGE_SIZE
);
4741 i915_gem_object_unpin(obj
);
4743 drm_gem_object_unreference(obj
);
4750 i915_gem_cleanup_pipe_control(struct drm_device
*dev
)
4752 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4753 struct drm_gem_object
*obj
;
4754 struct drm_i915_gem_object
*obj_priv
;
4756 obj
= dev_priv
->seqno_obj
;
4757 obj_priv
= to_intel_bo(obj
);
4758 kunmap(obj_priv
->pages
[0]);
4759 i915_gem_object_unpin(obj
);
4760 drm_gem_object_unreference(obj
);
4761 dev_priv
->seqno_obj
= NULL
;
4763 dev_priv
->seqno_page
= NULL
;
4767 i915_gem_init_ringbuffer(struct drm_device
*dev
)
4769 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4772 if (HAS_PIPE_CONTROL(dev
)) {
4773 ret
= i915_gem_init_pipe_control(dev
);
4778 ret
= intel_init_render_ring_buffer(dev
);
4780 goto cleanup_pipe_control
;
4783 ret
= intel_init_bsd_ring_buffer(dev
);
4785 goto cleanup_render_ring
;
4789 ret
= intel_init_blt_ring_buffer(dev
);
4791 goto cleanup_bsd_ring
;
4794 dev_priv
->next_seqno
= 1;
4799 intel_cleanup_ring_buffer(&dev_priv
->bsd_ring
);
4800 cleanup_render_ring
:
4801 intel_cleanup_ring_buffer(&dev_priv
->render_ring
);
4802 cleanup_pipe_control
:
4803 if (HAS_PIPE_CONTROL(dev
))
4804 i915_gem_cleanup_pipe_control(dev
);
4809 i915_gem_cleanup_ringbuffer(struct drm_device
*dev
)
4811 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4813 intel_cleanup_ring_buffer(&dev_priv
->render_ring
);
4814 intel_cleanup_ring_buffer(&dev_priv
->bsd_ring
);
4815 intel_cleanup_ring_buffer(&dev_priv
->blt_ring
);
4816 if (HAS_PIPE_CONTROL(dev
))
4817 i915_gem_cleanup_pipe_control(dev
);
4821 i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
4822 struct drm_file
*file_priv
)
4824 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4827 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4830 if (atomic_read(&dev_priv
->mm
.wedged
)) {
4831 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4832 atomic_set(&dev_priv
->mm
.wedged
, 0);
4835 mutex_lock(&dev
->struct_mutex
);
4836 dev_priv
->mm
.suspended
= 0;
4838 ret
= i915_gem_init_ringbuffer(dev
);
4840 mutex_unlock(&dev
->struct_mutex
);
4844 BUG_ON(!list_empty(&dev_priv
->mm
.active_list
));
4845 BUG_ON(!list_empty(&dev_priv
->render_ring
.active_list
));
4846 BUG_ON(!list_empty(&dev_priv
->bsd_ring
.active_list
));
4847 BUG_ON(!list_empty(&dev_priv
->blt_ring
.active_list
));
4848 BUG_ON(!list_empty(&dev_priv
->mm
.flushing_list
));
4849 BUG_ON(!list_empty(&dev_priv
->mm
.inactive_list
));
4850 BUG_ON(!list_empty(&dev_priv
->render_ring
.request_list
));
4851 BUG_ON(!list_empty(&dev_priv
->bsd_ring
.request_list
));
4852 BUG_ON(!list_empty(&dev_priv
->blt_ring
.request_list
));
4853 mutex_unlock(&dev
->struct_mutex
);
4855 ret
= drm_irq_install(dev
);
4857 goto cleanup_ringbuffer
;
4862 mutex_lock(&dev
->struct_mutex
);
4863 i915_gem_cleanup_ringbuffer(dev
);
4864 dev_priv
->mm
.suspended
= 1;
4865 mutex_unlock(&dev
->struct_mutex
);
4871 i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
4872 struct drm_file
*file_priv
)
4874 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4877 drm_irq_uninstall(dev
);
4878 return i915_gem_idle(dev
);
4882 i915_gem_lastclose(struct drm_device
*dev
)
4886 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4889 ret
= i915_gem_idle(dev
);
4891 DRM_ERROR("failed to idle hardware: %d\n", ret
);
4895 init_ring_lists(struct intel_ring_buffer
*ring
)
4897 INIT_LIST_HEAD(&ring
->active_list
);
4898 INIT_LIST_HEAD(&ring
->request_list
);
4899 INIT_LIST_HEAD(&ring
->gpu_write_list
);
4903 i915_gem_load(struct drm_device
*dev
)
4906 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4908 INIT_LIST_HEAD(&dev_priv
->mm
.active_list
);
4909 INIT_LIST_HEAD(&dev_priv
->mm
.flushing_list
);
4910 INIT_LIST_HEAD(&dev_priv
->mm
.inactive_list
);
4911 INIT_LIST_HEAD(&dev_priv
->mm
.pinned_list
);
4912 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
4913 INIT_LIST_HEAD(&dev_priv
->mm
.deferred_free_list
);
4914 INIT_LIST_HEAD(&dev_priv
->mm
.gtt_list
);
4915 init_ring_lists(&dev_priv
->render_ring
);
4916 init_ring_lists(&dev_priv
->bsd_ring
);
4917 init_ring_lists(&dev_priv
->blt_ring
);
4918 for (i
= 0; i
< 16; i
++)
4919 INIT_LIST_HEAD(&dev_priv
->fence_regs
[i
].lru_list
);
4920 INIT_DELAYED_WORK(&dev_priv
->mm
.retire_work
,
4921 i915_gem_retire_work_handler
);
4922 init_completion(&dev_priv
->error_completion
);
4924 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4926 u32 tmp
= I915_READ(MI_ARB_STATE
);
4927 if (!(tmp
& MI_ARB_C3_LP_WRITE_ENABLE
)) {
4928 /* arb state is a masked write, so set bit + bit in mask */
4929 tmp
= MI_ARB_C3_LP_WRITE_ENABLE
| (MI_ARB_C3_LP_WRITE_ENABLE
<< MI_ARB_MASK_SHIFT
);
4930 I915_WRITE(MI_ARB_STATE
, tmp
);
4934 /* Old X drivers will take 0-2 for front, back, depth buffers */
4935 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
4936 dev_priv
->fence_reg_start
= 3;
4938 if (INTEL_INFO(dev
)->gen
>= 4 || IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
4939 dev_priv
->num_fence_regs
= 16;
4941 dev_priv
->num_fence_regs
= 8;
4943 /* Initialize fence registers to zero */
4944 switch (INTEL_INFO(dev
)->gen
) {
4946 for (i
= 0; i
< 16; i
++)
4947 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0
+ (i
* 8), 0);
4951 for (i
= 0; i
< 16; i
++)
4952 I915_WRITE64(FENCE_REG_965_0
+ (i
* 8), 0);
4955 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
4956 for (i
= 0; i
< 8; i
++)
4957 I915_WRITE(FENCE_REG_945_8
+ (i
* 4), 0);
4959 for (i
= 0; i
< 8; i
++)
4960 I915_WRITE(FENCE_REG_830_0
+ (i
* 4), 0);
4963 i915_gem_detect_bit_6_swizzle(dev
);
4964 init_waitqueue_head(&dev_priv
->pending_flip_queue
);
4966 dev_priv
->mm
.inactive_shrinker
.shrink
= i915_gem_inactive_shrink
;
4967 dev_priv
->mm
.inactive_shrinker
.seeks
= DEFAULT_SEEKS
;
4968 register_shrinker(&dev_priv
->mm
.inactive_shrinker
);
4972 * Create a physically contiguous memory object for this object
4973 * e.g. for cursor + overlay regs
4975 static int i915_gem_init_phys_object(struct drm_device
*dev
,
4976 int id
, int size
, int align
)
4978 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4979 struct drm_i915_gem_phys_object
*phys_obj
;
4982 if (dev_priv
->mm
.phys_objs
[id
- 1] || !size
)
4985 phys_obj
= kzalloc(sizeof(struct drm_i915_gem_phys_object
), GFP_KERNEL
);
4991 phys_obj
->handle
= drm_pci_alloc(dev
, size
, align
);
4992 if (!phys_obj
->handle
) {
4997 set_memory_wc((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
5000 dev_priv
->mm
.phys_objs
[id
- 1] = phys_obj
;
5008 static void i915_gem_free_phys_object(struct drm_device
*dev
, int id
)
5010 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
5011 struct drm_i915_gem_phys_object
*phys_obj
;
5013 if (!dev_priv
->mm
.phys_objs
[id
- 1])
5016 phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
5017 if (phys_obj
->cur_obj
) {
5018 i915_gem_detach_phys_object(dev
, phys_obj
->cur_obj
);
5022 set_memory_wb((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
5024 drm_pci_free(dev
, phys_obj
->handle
);
5026 dev_priv
->mm
.phys_objs
[id
- 1] = NULL
;
5029 void i915_gem_free_all_phys_object(struct drm_device
*dev
)
5033 for (i
= I915_GEM_PHYS_CURSOR_0
; i
<= I915_MAX_PHYS_OBJECT
; i
++)
5034 i915_gem_free_phys_object(dev
, i
);
5037 void i915_gem_detach_phys_object(struct drm_device
*dev
,
5038 struct drm_gem_object
*obj
)
5040 struct address_space
*mapping
= obj
->filp
->f_path
.dentry
->d_inode
->i_mapping
;
5041 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
5046 if (!obj_priv
->phys_obj
)
5048 vaddr
= obj_priv
->phys_obj
->handle
->vaddr
;
5050 page_count
= obj
->size
/ PAGE_SIZE
;
5052 for (i
= 0; i
< page_count
; i
++) {
5053 struct page
*page
= read_cache_page_gfp(mapping
, i
,
5054 GFP_HIGHUSER
| __GFP_RECLAIMABLE
);
5055 if (!IS_ERR(page
)) {
5056 char *dst
= kmap_atomic(page
);
5057 memcpy(dst
, vaddr
+ i
*PAGE_SIZE
, PAGE_SIZE
);
5060 drm_clflush_pages(&page
, 1);
5062 set_page_dirty(page
);
5063 mark_page_accessed(page
);
5064 page_cache_release(page
);
5067 intel_gtt_chipset_flush();
5069 obj_priv
->phys_obj
->cur_obj
= NULL
;
5070 obj_priv
->phys_obj
= NULL
;
5074 i915_gem_attach_phys_object(struct drm_device
*dev
,
5075 struct drm_gem_object
*obj
,
5079 struct address_space
*mapping
= obj
->filp
->f_path
.dentry
->d_inode
->i_mapping
;
5080 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
5081 struct drm_i915_gem_object
*obj_priv
;
5086 if (id
> I915_MAX_PHYS_OBJECT
)
5089 obj_priv
= to_intel_bo(obj
);
5091 if (obj_priv
->phys_obj
) {
5092 if (obj_priv
->phys_obj
->id
== id
)
5094 i915_gem_detach_phys_object(dev
, obj
);
5097 /* create a new object */
5098 if (!dev_priv
->mm
.phys_objs
[id
- 1]) {
5099 ret
= i915_gem_init_phys_object(dev
, id
,
5102 DRM_ERROR("failed to init phys object %d size: %zu\n", id
, obj
->size
);
5107 /* bind to the object */
5108 obj_priv
->phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
5109 obj_priv
->phys_obj
->cur_obj
= obj
;
5111 page_count
= obj
->size
/ PAGE_SIZE
;
5113 for (i
= 0; i
< page_count
; i
++) {
5117 page
= read_cache_page_gfp(mapping
, i
,
5118 GFP_HIGHUSER
| __GFP_RECLAIMABLE
);
5120 return PTR_ERR(page
);
5122 src
= kmap_atomic(page
);
5123 dst
= obj_priv
->phys_obj
->handle
->vaddr
+ (i
* PAGE_SIZE
);
5124 memcpy(dst
, src
, PAGE_SIZE
);
5127 mark_page_accessed(page
);
5128 page_cache_release(page
);
5135 i915_gem_phys_pwrite(struct drm_device
*dev
, struct drm_gem_object
*obj
,
5136 struct drm_i915_gem_pwrite
*args
,
5137 struct drm_file
*file_priv
)
5139 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
5140 void *vaddr
= obj_priv
->phys_obj
->handle
->vaddr
+ args
->offset
;
5141 char __user
*user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
5143 DRM_DEBUG_DRIVER("vaddr %p, %lld\n", vaddr
, args
->size
);
5145 if (__copy_from_user_inatomic_nocache(vaddr
, user_data
, args
->size
)) {
5146 unsigned long unwritten
;
5148 /* The physical object once assigned is fixed for the lifetime
5149 * of the obj, so we can safely drop the lock and continue
5152 mutex_unlock(&dev
->struct_mutex
);
5153 unwritten
= copy_from_user(vaddr
, user_data
, args
->size
);
5154 mutex_lock(&dev
->struct_mutex
);
5159 intel_gtt_chipset_flush();
5163 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
)
5165 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
5167 /* Clean up our request list when the client is going away, so that
5168 * later retire_requests won't dereference our soon-to-be-gone
5171 spin_lock(&file_priv
->mm
.lock
);
5172 while (!list_empty(&file_priv
->mm
.request_list
)) {
5173 struct drm_i915_gem_request
*request
;
5175 request
= list_first_entry(&file_priv
->mm
.request_list
,
5176 struct drm_i915_gem_request
,
5178 list_del(&request
->client_list
);
5179 request
->file_priv
= NULL
;
5181 spin_unlock(&file_priv
->mm
.lock
);
5185 i915_gpu_is_active(struct drm_device
*dev
)
5187 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
5190 lists_empty
= list_empty(&dev_priv
->mm
.flushing_list
) &&
5191 list_empty(&dev_priv
->mm
.active_list
);
5193 return !lists_empty
;
5197 i915_gem_inactive_shrink(struct shrinker
*shrinker
,
5201 struct drm_i915_private
*dev_priv
=
5202 container_of(shrinker
,
5203 struct drm_i915_private
,
5204 mm
.inactive_shrinker
);
5205 struct drm_device
*dev
= dev_priv
->dev
;
5206 struct drm_i915_gem_object
*obj
, *next
;
5209 if (!mutex_trylock(&dev
->struct_mutex
))
5212 /* "fast-path" to count number of available objects */
5213 if (nr_to_scan
== 0) {
5215 list_for_each_entry(obj
,
5216 &dev_priv
->mm
.inactive_list
,
5219 mutex_unlock(&dev
->struct_mutex
);
5220 return cnt
/ 100 * sysctl_vfs_cache_pressure
;
5224 /* first scan for clean buffers */
5225 i915_gem_retire_requests(dev
);
5227 list_for_each_entry_safe(obj
, next
,
5228 &dev_priv
->mm
.inactive_list
,
5230 if (i915_gem_object_is_purgeable(obj
)) {
5231 i915_gem_object_unbind(&obj
->base
);
5232 if (--nr_to_scan
== 0)
5237 /* second pass, evict/count anything still on the inactive list */
5239 list_for_each_entry_safe(obj
, next
,
5240 &dev_priv
->mm
.inactive_list
,
5243 i915_gem_object_unbind(&obj
->base
);
5249 if (nr_to_scan
&& i915_gpu_is_active(dev
)) {
5251 * We are desperate for pages, so as a last resort, wait
5252 * for the GPU to finish and discard whatever we can.
5253 * This has a dramatic impact to reduce the number of
5254 * OOM-killer events whilst running the GPU aggressively.
5256 if (i915_gpu_idle(dev
) == 0)
5259 mutex_unlock(&dev
->struct_mutex
);
5260 return cnt
/ 100 * sysctl_vfs_cache_pressure
;