2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/slab.h>
35 #include <linux/swap.h>
36 #include <linux/pci.h>
37 #include <linux/intel-gtt.h>
39 static uint32_t i915_gem_get_gtt_alignment(struct drm_gem_object
*obj
);
41 static int i915_gem_object_flush_gpu_write_domain(struct drm_gem_object
*obj
,
43 static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object
*obj
);
44 static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object
*obj
);
45 static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object
*obj
,
47 static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object
*obj
,
50 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object
*obj
);
51 static int i915_gem_object_wait_rendering(struct drm_gem_object
*obj
,
53 static int i915_gem_object_bind_to_gtt(struct drm_gem_object
*obj
,
55 static void i915_gem_clear_fence_reg(struct drm_gem_object
*obj
);
56 static int i915_gem_phys_pwrite(struct drm_device
*dev
, struct drm_gem_object
*obj
,
57 struct drm_i915_gem_pwrite
*args
,
58 struct drm_file
*file_priv
);
59 static void i915_gem_free_object_tail(struct drm_gem_object
*obj
);
62 i915_gem_object_get_pages(struct drm_gem_object
*obj
,
66 i915_gem_object_put_pages(struct drm_gem_object
*obj
);
68 static LIST_HEAD(shrink_list
);
69 static DEFINE_SPINLOCK(shrink_list_lock
);
71 /* some bookkeeping */
72 static void i915_gem_info_add_obj(struct drm_i915_private
*dev_priv
,
75 dev_priv
->mm
.object_count
++;
76 dev_priv
->mm
.object_memory
+= size
;
79 static void i915_gem_info_remove_obj(struct drm_i915_private
*dev_priv
,
82 dev_priv
->mm
.object_count
--;
83 dev_priv
->mm
.object_memory
-= size
;
86 static void i915_gem_info_add_gtt(struct drm_i915_private
*dev_priv
,
89 dev_priv
->mm
.gtt_count
++;
90 dev_priv
->mm
.gtt_memory
+= size
;
93 static void i915_gem_info_remove_gtt(struct drm_i915_private
*dev_priv
,
96 dev_priv
->mm
.gtt_count
--;
97 dev_priv
->mm
.gtt_memory
-= size
;
100 static void i915_gem_info_add_pin(struct drm_i915_private
*dev_priv
,
103 dev_priv
->mm
.pin_count
++;
104 dev_priv
->mm
.pin_memory
+= size
;
107 static void i915_gem_info_remove_pin(struct drm_i915_private
*dev_priv
,
110 dev_priv
->mm
.pin_count
--;
111 dev_priv
->mm
.pin_memory
-= size
;
115 i915_gem_check_is_wedged(struct drm_device
*dev
)
117 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
118 struct completion
*x
= &dev_priv
->error_completion
;
122 if (!atomic_read(&dev_priv
->mm
.wedged
))
125 ret
= wait_for_completion_interruptible(x
);
129 /* Success, we reset the GPU! */
130 if (!atomic_read(&dev_priv
->mm
.wedged
))
133 /* GPU is hung, bump the completion count to account for
134 * the token we just consumed so that we never hit zero and
135 * end up waiting upon a subsequent completion event that
138 spin_lock_irqsave(&x
->wait
.lock
, flags
);
140 spin_unlock_irqrestore(&x
->wait
.lock
, flags
);
144 static int i915_mutex_lock_interruptible(struct drm_device
*dev
)
146 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
149 ret
= i915_gem_check_is_wedged(dev
);
153 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
157 if (atomic_read(&dev_priv
->mm
.wedged
)) {
158 mutex_unlock(&dev
->struct_mutex
);
162 WARN_ON(i915_verify_lists(dev
));
167 i915_gem_object_is_inactive(struct drm_i915_gem_object
*obj_priv
)
169 return obj_priv
->gtt_space
&&
171 obj_priv
->pin_count
== 0;
174 int i915_gem_do_init(struct drm_device
*dev
,
178 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
181 (start
& (PAGE_SIZE
- 1)) != 0 ||
182 (end
& (PAGE_SIZE
- 1)) != 0) {
186 drm_mm_init(&dev_priv
->mm
.gtt_space
, start
,
189 dev_priv
->mm
.gtt_total
= end
- start
;
195 i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
196 struct drm_file
*file_priv
)
198 struct drm_i915_gem_init
*args
= data
;
201 mutex_lock(&dev
->struct_mutex
);
202 ret
= i915_gem_do_init(dev
, args
->gtt_start
, args
->gtt_end
);
203 mutex_unlock(&dev
->struct_mutex
);
209 i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
210 struct drm_file
*file_priv
)
212 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
213 struct drm_i915_gem_get_aperture
*args
= data
;
215 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
218 mutex_lock(&dev
->struct_mutex
);
219 args
->aper_size
= dev_priv
->mm
.gtt_total
;
220 args
->aper_available_size
= args
->aper_size
- dev_priv
->mm
.pin_memory
;
221 mutex_unlock(&dev
->struct_mutex
);
228 * Creates a new mm object and returns a handle to it.
231 i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
232 struct drm_file
*file_priv
)
234 struct drm_i915_gem_create
*args
= data
;
235 struct drm_gem_object
*obj
;
239 args
->size
= roundup(args
->size
, PAGE_SIZE
);
241 /* Allocate the new object */
242 obj
= i915_gem_alloc_object(dev
, args
->size
);
246 ret
= drm_gem_handle_create(file_priv
, obj
, &handle
);
248 drm_gem_object_release(obj
);
249 i915_gem_info_remove_obj(dev
->dev_private
, obj
->size
);
254 /* drop reference from allocate - handle holds it now */
255 drm_gem_object_unreference(obj
);
256 trace_i915_gem_object_create(obj
);
258 args
->handle
= handle
;
263 fast_shmem_read(struct page
**pages
,
264 loff_t page_base
, int page_offset
,
271 vaddr
= kmap_atomic(pages
[page_base
>> PAGE_SHIFT
], KM_USER0
);
272 ret
= __copy_to_user_inatomic(data
, vaddr
+ page_offset
, length
);
273 kunmap_atomic(vaddr
, KM_USER0
);
278 static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object
*obj
)
280 drm_i915_private_t
*dev_priv
= obj
->dev
->dev_private
;
281 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
283 return dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_9_10_17
&&
284 obj_priv
->tiling_mode
!= I915_TILING_NONE
;
288 slow_shmem_copy(struct page
*dst_page
,
290 struct page
*src_page
,
294 char *dst_vaddr
, *src_vaddr
;
296 dst_vaddr
= kmap(dst_page
);
297 src_vaddr
= kmap(src_page
);
299 memcpy(dst_vaddr
+ dst_offset
, src_vaddr
+ src_offset
, length
);
306 slow_shmem_bit17_copy(struct page
*gpu_page
,
308 struct page
*cpu_page
,
313 char *gpu_vaddr
, *cpu_vaddr
;
315 /* Use the unswizzled path if this page isn't affected. */
316 if ((page_to_phys(gpu_page
) & (1 << 17)) == 0) {
318 return slow_shmem_copy(cpu_page
, cpu_offset
,
319 gpu_page
, gpu_offset
, length
);
321 return slow_shmem_copy(gpu_page
, gpu_offset
,
322 cpu_page
, cpu_offset
, length
);
325 gpu_vaddr
= kmap(gpu_page
);
326 cpu_vaddr
= kmap(cpu_page
);
328 /* Copy the data, XORing A6 with A17 (1). The user already knows he's
329 * XORing with the other bits (A9 for Y, A9 and A10 for X)
332 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
333 int this_length
= min(cacheline_end
- gpu_offset
, length
);
334 int swizzled_gpu_offset
= gpu_offset
^ 64;
337 memcpy(cpu_vaddr
+ cpu_offset
,
338 gpu_vaddr
+ swizzled_gpu_offset
,
341 memcpy(gpu_vaddr
+ swizzled_gpu_offset
,
342 cpu_vaddr
+ cpu_offset
,
345 cpu_offset
+= this_length
;
346 gpu_offset
+= this_length
;
347 length
-= this_length
;
355 * This is the fast shmem pread path, which attempts to copy_from_user directly
356 * from the backing pages of the object to the user's address space. On a
357 * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
360 i915_gem_shmem_pread_fast(struct drm_device
*dev
, struct drm_gem_object
*obj
,
361 struct drm_i915_gem_pread
*args
,
362 struct drm_file
*file_priv
)
364 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
366 loff_t offset
, page_base
;
367 char __user
*user_data
;
368 int page_offset
, page_length
;
370 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
373 obj_priv
= to_intel_bo(obj
);
374 offset
= args
->offset
;
377 /* Operation in this page
379 * page_base = page offset within aperture
380 * page_offset = offset within page
381 * page_length = bytes to copy for this page
383 page_base
= (offset
& ~(PAGE_SIZE
-1));
384 page_offset
= offset
& (PAGE_SIZE
-1);
385 page_length
= remain
;
386 if ((page_offset
+ remain
) > PAGE_SIZE
)
387 page_length
= PAGE_SIZE
- page_offset
;
389 if (fast_shmem_read(obj_priv
->pages
,
390 page_base
, page_offset
,
391 user_data
, page_length
))
394 remain
-= page_length
;
395 user_data
+= page_length
;
396 offset
+= page_length
;
403 i915_gem_object_get_pages_or_evict(struct drm_gem_object
*obj
)
407 ret
= i915_gem_object_get_pages(obj
, __GFP_NORETRY
| __GFP_NOWARN
);
409 /* If we've insufficient memory to map in the pages, attempt
410 * to make some space by throwing out some old buffers.
412 if (ret
== -ENOMEM
) {
413 struct drm_device
*dev
= obj
->dev
;
415 ret
= i915_gem_evict_something(dev
, obj
->size
,
416 i915_gem_get_gtt_alignment(obj
));
420 ret
= i915_gem_object_get_pages(obj
, 0);
427 * This is the fallback shmem pread path, which allocates temporary storage
428 * in kernel space to copy_to_user into outside of the struct_mutex, so we
429 * can copy out of the object's backing pages while holding the struct mutex
430 * and not take page faults.
433 i915_gem_shmem_pread_slow(struct drm_device
*dev
, struct drm_gem_object
*obj
,
434 struct drm_i915_gem_pread
*args
,
435 struct drm_file
*file_priv
)
437 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
438 struct mm_struct
*mm
= current
->mm
;
439 struct page
**user_pages
;
441 loff_t offset
, pinned_pages
, i
;
442 loff_t first_data_page
, last_data_page
, num_pages
;
443 int shmem_page_index
, shmem_page_offset
;
444 int data_page_index
, data_page_offset
;
447 uint64_t data_ptr
= args
->data_ptr
;
448 int do_bit17_swizzling
;
452 /* Pin the user pages containing the data. We can't fault while
453 * holding the struct mutex, yet we want to hold it while
454 * dereferencing the user data.
456 first_data_page
= data_ptr
/ PAGE_SIZE
;
457 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
458 num_pages
= last_data_page
- first_data_page
+ 1;
460 user_pages
= drm_malloc_ab(num_pages
, sizeof(struct page
*));
461 if (user_pages
== NULL
)
464 mutex_unlock(&dev
->struct_mutex
);
465 down_read(&mm
->mmap_sem
);
466 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
467 num_pages
, 1, 0, user_pages
, NULL
);
468 up_read(&mm
->mmap_sem
);
469 mutex_lock(&dev
->struct_mutex
);
470 if (pinned_pages
< num_pages
) {
475 ret
= i915_gem_object_set_cpu_read_domain_range(obj
,
481 do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
483 obj_priv
= to_intel_bo(obj
);
484 offset
= args
->offset
;
487 /* Operation in this page
489 * shmem_page_index = page number within shmem file
490 * shmem_page_offset = offset within page in shmem file
491 * data_page_index = page number in get_user_pages return
492 * data_page_offset = offset with data_page_index page.
493 * page_length = bytes to copy for this page
495 shmem_page_index
= offset
/ PAGE_SIZE
;
496 shmem_page_offset
= offset
& ~PAGE_MASK
;
497 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
498 data_page_offset
= data_ptr
& ~PAGE_MASK
;
500 page_length
= remain
;
501 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
502 page_length
= PAGE_SIZE
- shmem_page_offset
;
503 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
504 page_length
= PAGE_SIZE
- data_page_offset
;
506 if (do_bit17_swizzling
) {
507 slow_shmem_bit17_copy(obj_priv
->pages
[shmem_page_index
],
509 user_pages
[data_page_index
],
514 slow_shmem_copy(user_pages
[data_page_index
],
516 obj_priv
->pages
[shmem_page_index
],
521 remain
-= page_length
;
522 data_ptr
+= page_length
;
523 offset
+= page_length
;
527 for (i
= 0; i
< pinned_pages
; i
++) {
528 SetPageDirty(user_pages
[i
]);
529 page_cache_release(user_pages
[i
]);
531 drm_free_large(user_pages
);
537 * Reads data from the object referenced by handle.
539 * On error, the contents of *data are undefined.
542 i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
543 struct drm_file
*file_priv
)
545 struct drm_i915_gem_pread
*args
= data
;
546 struct drm_gem_object
*obj
;
547 struct drm_i915_gem_object
*obj_priv
;
550 ret
= i915_mutex_lock_interruptible(dev
);
554 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
559 obj_priv
= to_intel_bo(obj
);
561 /* Bounds check source. */
562 if (args
->offset
> obj
->size
|| args
->size
> obj
->size
- args
->offset
) {
570 if (!access_ok(VERIFY_WRITE
,
571 (char __user
*)(uintptr_t)args
->data_ptr
,
577 ret
= fault_in_pages_writeable((char __user
*)(uintptr_t)args
->data_ptr
,
584 ret
= i915_gem_object_get_pages_or_evict(obj
);
588 ret
= i915_gem_object_set_cpu_read_domain_range(obj
,
595 if (!i915_gem_object_needs_bit17_swizzle(obj
))
596 ret
= i915_gem_shmem_pread_fast(dev
, obj
, args
, file_priv
);
598 ret
= i915_gem_shmem_pread_slow(dev
, obj
, args
, file_priv
);
601 i915_gem_object_put_pages(obj
);
603 drm_gem_object_unreference(obj
);
605 mutex_unlock(&dev
->struct_mutex
);
609 /* This is the fast write path which cannot handle
610 * page faults in the source data
614 fast_user_write(struct io_mapping
*mapping
,
615 loff_t page_base
, int page_offset
,
616 char __user
*user_data
,
620 unsigned long unwritten
;
622 vaddr_atomic
= io_mapping_map_atomic_wc(mapping
, page_base
, KM_USER0
);
623 unwritten
= __copy_from_user_inatomic_nocache(vaddr_atomic
+ page_offset
,
625 io_mapping_unmap_atomic(vaddr_atomic
, KM_USER0
);
629 /* Here's the write path which can sleep for
634 slow_kernel_write(struct io_mapping
*mapping
,
635 loff_t gtt_base
, int gtt_offset
,
636 struct page
*user_page
, int user_offset
,
639 char __iomem
*dst_vaddr
;
642 dst_vaddr
= io_mapping_map_wc(mapping
, gtt_base
);
643 src_vaddr
= kmap(user_page
);
645 memcpy_toio(dst_vaddr
+ gtt_offset
,
646 src_vaddr
+ user_offset
,
650 io_mapping_unmap(dst_vaddr
);
654 fast_shmem_write(struct page
**pages
,
655 loff_t page_base
, int page_offset
,
662 vaddr
= kmap_atomic(pages
[page_base
>> PAGE_SHIFT
], KM_USER0
);
663 ret
= __copy_from_user_inatomic(vaddr
+ page_offset
, data
, length
);
664 kunmap_atomic(vaddr
, KM_USER0
);
670 * This is the fast pwrite path, where we copy the data directly from the
671 * user into the GTT, uncached.
674 i915_gem_gtt_pwrite_fast(struct drm_device
*dev
, struct drm_gem_object
*obj
,
675 struct drm_i915_gem_pwrite
*args
,
676 struct drm_file
*file_priv
)
678 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
679 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
681 loff_t offset
, page_base
;
682 char __user
*user_data
;
683 int page_offset
, page_length
;
685 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
688 obj_priv
= to_intel_bo(obj
);
689 offset
= obj_priv
->gtt_offset
+ args
->offset
;
692 /* Operation in this page
694 * page_base = page offset within aperture
695 * page_offset = offset within page
696 * page_length = bytes to copy for this page
698 page_base
= (offset
& ~(PAGE_SIZE
-1));
699 page_offset
= offset
& (PAGE_SIZE
-1);
700 page_length
= remain
;
701 if ((page_offset
+ remain
) > PAGE_SIZE
)
702 page_length
= PAGE_SIZE
- page_offset
;
704 /* If we get a fault while copying data, then (presumably) our
705 * source page isn't available. Return the error and we'll
706 * retry in the slow path.
708 if (fast_user_write(dev_priv
->mm
.gtt_mapping
, page_base
,
709 page_offset
, user_data
, page_length
))
713 remain
-= page_length
;
714 user_data
+= page_length
;
715 offset
+= page_length
;
722 * This is the fallback GTT pwrite path, which uses get_user_pages to pin
723 * the memory and maps it using kmap_atomic for copying.
725 * This code resulted in x11perf -rgb10text consuming about 10% more CPU
726 * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
729 i915_gem_gtt_pwrite_slow(struct drm_device
*dev
, struct drm_gem_object
*obj
,
730 struct drm_i915_gem_pwrite
*args
,
731 struct drm_file
*file_priv
)
733 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
734 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
736 loff_t gtt_page_base
, offset
;
737 loff_t first_data_page
, last_data_page
, num_pages
;
738 loff_t pinned_pages
, i
;
739 struct page
**user_pages
;
740 struct mm_struct
*mm
= current
->mm
;
741 int gtt_page_offset
, data_page_offset
, data_page_index
, page_length
;
743 uint64_t data_ptr
= args
->data_ptr
;
747 /* Pin the user pages containing the data. We can't fault while
748 * holding the struct mutex, and all of the pwrite implementations
749 * want to hold it while dereferencing the user data.
751 first_data_page
= data_ptr
/ PAGE_SIZE
;
752 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
753 num_pages
= last_data_page
- first_data_page
+ 1;
755 user_pages
= drm_malloc_ab(num_pages
, sizeof(struct page
*));
756 if (user_pages
== NULL
)
759 mutex_unlock(&dev
->struct_mutex
);
760 down_read(&mm
->mmap_sem
);
761 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
762 num_pages
, 0, 0, user_pages
, NULL
);
763 up_read(&mm
->mmap_sem
);
764 mutex_lock(&dev
->struct_mutex
);
765 if (pinned_pages
< num_pages
) {
767 goto out_unpin_pages
;
770 ret
= i915_gem_object_set_to_gtt_domain(obj
, 1);
772 goto out_unpin_pages
;
774 obj_priv
= to_intel_bo(obj
);
775 offset
= obj_priv
->gtt_offset
+ args
->offset
;
778 /* Operation in this page
780 * gtt_page_base = page offset within aperture
781 * gtt_page_offset = offset within page in aperture
782 * data_page_index = page number in get_user_pages return
783 * data_page_offset = offset with data_page_index page.
784 * page_length = bytes to copy for this page
786 gtt_page_base
= offset
& PAGE_MASK
;
787 gtt_page_offset
= offset
& ~PAGE_MASK
;
788 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
789 data_page_offset
= data_ptr
& ~PAGE_MASK
;
791 page_length
= remain
;
792 if ((gtt_page_offset
+ page_length
) > PAGE_SIZE
)
793 page_length
= PAGE_SIZE
- gtt_page_offset
;
794 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
795 page_length
= PAGE_SIZE
- data_page_offset
;
797 slow_kernel_write(dev_priv
->mm
.gtt_mapping
,
798 gtt_page_base
, gtt_page_offset
,
799 user_pages
[data_page_index
],
803 remain
-= page_length
;
804 offset
+= page_length
;
805 data_ptr
+= page_length
;
809 for (i
= 0; i
< pinned_pages
; i
++)
810 page_cache_release(user_pages
[i
]);
811 drm_free_large(user_pages
);
817 * This is the fast shmem pwrite path, which attempts to directly
818 * copy_from_user into the kmapped pages backing the object.
821 i915_gem_shmem_pwrite_fast(struct drm_device
*dev
, struct drm_gem_object
*obj
,
822 struct drm_i915_gem_pwrite
*args
,
823 struct drm_file
*file_priv
)
825 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
827 loff_t offset
, page_base
;
828 char __user
*user_data
;
829 int page_offset
, page_length
;
831 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
834 obj_priv
= to_intel_bo(obj
);
835 offset
= args
->offset
;
839 /* Operation in this page
841 * page_base = page offset within aperture
842 * page_offset = offset within page
843 * page_length = bytes to copy for this page
845 page_base
= (offset
& ~(PAGE_SIZE
-1));
846 page_offset
= offset
& (PAGE_SIZE
-1);
847 page_length
= remain
;
848 if ((page_offset
+ remain
) > PAGE_SIZE
)
849 page_length
= PAGE_SIZE
- page_offset
;
851 if (fast_shmem_write(obj_priv
->pages
,
852 page_base
, page_offset
,
853 user_data
, page_length
))
856 remain
-= page_length
;
857 user_data
+= page_length
;
858 offset
+= page_length
;
865 * This is the fallback shmem pwrite path, which uses get_user_pages to pin
866 * the memory and maps it using kmap_atomic for copying.
868 * This avoids taking mmap_sem for faulting on the user's address while the
869 * struct_mutex is held.
872 i915_gem_shmem_pwrite_slow(struct drm_device
*dev
, struct drm_gem_object
*obj
,
873 struct drm_i915_gem_pwrite
*args
,
874 struct drm_file
*file_priv
)
876 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
877 struct mm_struct
*mm
= current
->mm
;
878 struct page
**user_pages
;
880 loff_t offset
, pinned_pages
, i
;
881 loff_t first_data_page
, last_data_page
, num_pages
;
882 int shmem_page_index
, shmem_page_offset
;
883 int data_page_index
, data_page_offset
;
886 uint64_t data_ptr
= args
->data_ptr
;
887 int do_bit17_swizzling
;
891 /* Pin the user pages containing the data. We can't fault while
892 * holding the struct mutex, and all of the pwrite implementations
893 * want to hold it while dereferencing the user data.
895 first_data_page
= data_ptr
/ PAGE_SIZE
;
896 last_data_page
= (data_ptr
+ args
->size
- 1) / PAGE_SIZE
;
897 num_pages
= last_data_page
- first_data_page
+ 1;
899 user_pages
= drm_malloc_ab(num_pages
, sizeof(struct page
*));
900 if (user_pages
== NULL
)
903 mutex_unlock(&dev
->struct_mutex
);
904 down_read(&mm
->mmap_sem
);
905 pinned_pages
= get_user_pages(current
, mm
, (uintptr_t)args
->data_ptr
,
906 num_pages
, 0, 0, user_pages
, NULL
);
907 up_read(&mm
->mmap_sem
);
908 mutex_lock(&dev
->struct_mutex
);
909 if (pinned_pages
< num_pages
) {
914 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
918 do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
920 obj_priv
= to_intel_bo(obj
);
921 offset
= args
->offset
;
925 /* Operation in this page
927 * shmem_page_index = page number within shmem file
928 * shmem_page_offset = offset within page in shmem file
929 * data_page_index = page number in get_user_pages return
930 * data_page_offset = offset with data_page_index page.
931 * page_length = bytes to copy for this page
933 shmem_page_index
= offset
/ PAGE_SIZE
;
934 shmem_page_offset
= offset
& ~PAGE_MASK
;
935 data_page_index
= data_ptr
/ PAGE_SIZE
- first_data_page
;
936 data_page_offset
= data_ptr
& ~PAGE_MASK
;
938 page_length
= remain
;
939 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
940 page_length
= PAGE_SIZE
- shmem_page_offset
;
941 if ((data_page_offset
+ page_length
) > PAGE_SIZE
)
942 page_length
= PAGE_SIZE
- data_page_offset
;
944 if (do_bit17_swizzling
) {
945 slow_shmem_bit17_copy(obj_priv
->pages
[shmem_page_index
],
947 user_pages
[data_page_index
],
952 slow_shmem_copy(obj_priv
->pages
[shmem_page_index
],
954 user_pages
[data_page_index
],
959 remain
-= page_length
;
960 data_ptr
+= page_length
;
961 offset
+= page_length
;
965 for (i
= 0; i
< pinned_pages
; i
++)
966 page_cache_release(user_pages
[i
]);
967 drm_free_large(user_pages
);
973 * Writes data to the object referenced by handle.
975 * On error, the contents of the buffer that were to be modified are undefined.
978 i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
979 struct drm_file
*file
)
981 struct drm_i915_gem_pwrite
*args
= data
;
982 struct drm_gem_object
*obj
;
983 struct drm_i915_gem_object
*obj_priv
;
986 ret
= i915_mutex_lock_interruptible(dev
);
990 obj
= drm_gem_object_lookup(dev
, file
, args
->handle
);
995 obj_priv
= to_intel_bo(obj
);
998 /* Bounds check destination. */
999 if (args
->offset
> obj
->size
|| args
->size
> obj
->size
- args
->offset
) {
1004 if (args
->size
== 0)
1007 if (!access_ok(VERIFY_READ
,
1008 (char __user
*)(uintptr_t)args
->data_ptr
,
1014 ret
= fault_in_pages_readable((char __user
*)(uintptr_t)args
->data_ptr
,
1021 /* We can only do the GTT pwrite on untiled buffers, as otherwise
1022 * it would end up going through the fenced access, and we'll get
1023 * different detiling behavior between reading and writing.
1024 * pread/pwrite currently are reading and writing from the CPU
1025 * perspective, requiring manual detiling by the client.
1027 if (obj_priv
->phys_obj
)
1028 ret
= i915_gem_phys_pwrite(dev
, obj
, args
, file
);
1029 else if (obj_priv
->tiling_mode
== I915_TILING_NONE
&&
1030 obj_priv
->gtt_space
&&
1031 obj
->write_domain
!= I915_GEM_DOMAIN_CPU
) {
1032 ret
= i915_gem_object_pin(obj
, 0);
1036 ret
= i915_gem_object_set_to_gtt_domain(obj
, 1);
1040 ret
= i915_gem_gtt_pwrite_fast(dev
, obj
, args
, file
);
1042 ret
= i915_gem_gtt_pwrite_slow(dev
, obj
, args
, file
);
1045 i915_gem_object_unpin(obj
);
1047 ret
= i915_gem_object_get_pages_or_evict(obj
);
1051 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
1056 if (!i915_gem_object_needs_bit17_swizzle(obj
))
1057 ret
= i915_gem_shmem_pwrite_fast(dev
, obj
, args
, file
);
1059 ret
= i915_gem_shmem_pwrite_slow(dev
, obj
, args
, file
);
1062 i915_gem_object_put_pages(obj
);
1066 drm_gem_object_unreference(obj
);
1068 mutex_unlock(&dev
->struct_mutex
);
1073 * Called when user space prepares to use an object with the CPU, either
1074 * through the mmap ioctl's mapping or a GTT mapping.
1077 i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
1078 struct drm_file
*file_priv
)
1080 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1081 struct drm_i915_gem_set_domain
*args
= data
;
1082 struct drm_gem_object
*obj
;
1083 struct drm_i915_gem_object
*obj_priv
;
1084 uint32_t read_domains
= args
->read_domains
;
1085 uint32_t write_domain
= args
->write_domain
;
1088 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1091 /* Only handle setting domains to types used by the CPU. */
1092 if (write_domain
& I915_GEM_GPU_DOMAINS
)
1095 if (read_domains
& I915_GEM_GPU_DOMAINS
)
1098 /* Having something in the write domain implies it's in the read
1099 * domain, and only that read domain. Enforce that in the request.
1101 if (write_domain
!= 0 && read_domains
!= write_domain
)
1104 ret
= i915_mutex_lock_interruptible(dev
);
1108 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1113 obj_priv
= to_intel_bo(obj
);
1115 intel_mark_busy(dev
, obj
);
1117 if (read_domains
& I915_GEM_DOMAIN_GTT
) {
1118 ret
= i915_gem_object_set_to_gtt_domain(obj
, write_domain
!= 0);
1120 /* Update the LRU on the fence for the CPU access that's
1123 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
) {
1124 struct drm_i915_fence_reg
*reg
=
1125 &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
1126 list_move_tail(®
->lru_list
,
1127 &dev_priv
->mm
.fence_list
);
1130 /* Silently promote "you're not bound, there was nothing to do"
1131 * to success, since the client was just asking us to
1132 * make sure everything was done.
1137 ret
= i915_gem_object_set_to_cpu_domain(obj
, write_domain
!= 0);
1140 /* Maintain LRU order of "inactive" objects */
1141 if (ret
== 0 && i915_gem_object_is_inactive(obj_priv
))
1142 list_move_tail(&obj_priv
->list
, &dev_priv
->mm
.inactive_list
);
1144 drm_gem_object_unreference(obj
);
1146 mutex_unlock(&dev
->struct_mutex
);
1151 * Called when user space has done writes to this buffer
1154 i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1155 struct drm_file
*file_priv
)
1157 struct drm_i915_gem_sw_finish
*args
= data
;
1158 struct drm_gem_object
*obj
;
1161 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1164 ret
= i915_mutex_lock_interruptible(dev
);
1168 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1174 /* Pinned buffers may be scanout, so flush the cache */
1175 if (to_intel_bo(obj
)->pin_count
)
1176 i915_gem_object_flush_cpu_write_domain(obj
);
1178 drm_gem_object_unreference(obj
);
1180 mutex_unlock(&dev
->struct_mutex
);
1185 * Maps the contents of an object, returning the address it is mapped
1188 * While the mapping holds a reference on the contents of the object, it doesn't
1189 * imply a ref on the object itself.
1192 i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1193 struct drm_file
*file_priv
)
1195 struct drm_i915_gem_mmap
*args
= data
;
1196 struct drm_gem_object
*obj
;
1200 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1203 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1207 offset
= args
->offset
;
1209 down_write(¤t
->mm
->mmap_sem
);
1210 addr
= do_mmap(obj
->filp
, 0, args
->size
,
1211 PROT_READ
| PROT_WRITE
, MAP_SHARED
,
1213 up_write(¤t
->mm
->mmap_sem
);
1214 drm_gem_object_unreference_unlocked(obj
);
1215 if (IS_ERR((void *)addr
))
1218 args
->addr_ptr
= (uint64_t) addr
;
1224 * i915_gem_fault - fault a page into the GTT
1225 * vma: VMA in question
1228 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1229 * from userspace. The fault handler takes care of binding the object to
1230 * the GTT (if needed), allocating and programming a fence register (again,
1231 * only if needed based on whether the old reg is still valid or the object
1232 * is tiled) and inserting a new PTE into the faulting process.
1234 * Note that the faulting process may involve evicting existing objects
1235 * from the GTT and/or fence registers to make room. So performance may
1236 * suffer if the GTT working set is large or there are few fence registers
1239 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
)
1241 struct drm_gem_object
*obj
= vma
->vm_private_data
;
1242 struct drm_device
*dev
= obj
->dev
;
1243 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1244 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1245 pgoff_t page_offset
;
1248 bool write
= !!(vmf
->flags
& FAULT_FLAG_WRITE
);
1250 /* We don't use vmf->pgoff since that has the fake offset */
1251 page_offset
= ((unsigned long)vmf
->virtual_address
- vma
->vm_start
) >>
1254 /* Now bind it into the GTT if needed */
1255 mutex_lock(&dev
->struct_mutex
);
1256 if (!obj_priv
->gtt_space
) {
1257 ret
= i915_gem_object_bind_to_gtt(obj
, 0);
1261 ret
= i915_gem_object_set_to_gtt_domain(obj
, write
);
1266 /* Need a new fence register? */
1267 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
) {
1268 ret
= i915_gem_object_get_fence_reg(obj
, true);
1273 if (i915_gem_object_is_inactive(obj_priv
))
1274 list_move_tail(&obj_priv
->list
, &dev_priv
->mm
.inactive_list
);
1276 pfn
= ((dev
->agp
->base
+ obj_priv
->gtt_offset
) >> PAGE_SHIFT
) +
1279 /* Finally, remap it using the new GTT offset */
1280 ret
= vm_insert_pfn(vma
, (unsigned long)vmf
->virtual_address
, pfn
);
1282 mutex_unlock(&dev
->struct_mutex
);
1287 return VM_FAULT_NOPAGE
;
1290 return VM_FAULT_OOM
;
1292 return VM_FAULT_SIGBUS
;
1297 * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1298 * @obj: obj in question
1300 * GEM memory mapping works by handing back to userspace a fake mmap offset
1301 * it can use in a subsequent mmap(2) call. The DRM core code then looks
1302 * up the object based on the offset and sets up the various memory mapping
1305 * This routine allocates and attaches a fake offset for @obj.
1308 i915_gem_create_mmap_offset(struct drm_gem_object
*obj
)
1310 struct drm_device
*dev
= obj
->dev
;
1311 struct drm_gem_mm
*mm
= dev
->mm_private
;
1312 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1313 struct drm_map_list
*list
;
1314 struct drm_local_map
*map
;
1317 /* Set the object up for mmap'ing */
1318 list
= &obj
->map_list
;
1319 list
->map
= kzalloc(sizeof(struct drm_map_list
), GFP_KERNEL
);
1324 map
->type
= _DRM_GEM
;
1325 map
->size
= obj
->size
;
1328 /* Get a DRM GEM mmap offset allocated... */
1329 list
->file_offset_node
= drm_mm_search_free(&mm
->offset_manager
,
1330 obj
->size
/ PAGE_SIZE
, 0, 0);
1331 if (!list
->file_offset_node
) {
1332 DRM_ERROR("failed to allocate offset for bo %d\n", obj
->name
);
1337 list
->file_offset_node
= drm_mm_get_block(list
->file_offset_node
,
1338 obj
->size
/ PAGE_SIZE
, 0);
1339 if (!list
->file_offset_node
) {
1344 list
->hash
.key
= list
->file_offset_node
->start
;
1345 ret
= drm_ht_insert_item(&mm
->offset_hash
, &list
->hash
);
1347 DRM_ERROR("failed to add to map hash\n");
1351 /* By now we should be all set, any drm_mmap request on the offset
1352 * below will get to our mmap & fault handler */
1353 obj_priv
->mmap_offset
= ((uint64_t) list
->hash
.key
) << PAGE_SHIFT
;
1358 drm_mm_put_block(list
->file_offset_node
);
1366 * i915_gem_release_mmap - remove physical page mappings
1367 * @obj: obj in question
1369 * Preserve the reservation of the mmapping with the DRM core code, but
1370 * relinquish ownership of the pages back to the system.
1372 * It is vital that we remove the page mapping if we have mapped a tiled
1373 * object through the GTT and then lose the fence register due to
1374 * resource pressure. Similarly if the object has been moved out of the
1375 * aperture, than pages mapped into userspace must be revoked. Removing the
1376 * mapping will then trigger a page fault on the next user access, allowing
1377 * fixup by i915_gem_fault().
1380 i915_gem_release_mmap(struct drm_gem_object
*obj
)
1382 struct drm_device
*dev
= obj
->dev
;
1383 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1385 if (dev
->dev_mapping
)
1386 unmap_mapping_range(dev
->dev_mapping
,
1387 obj_priv
->mmap_offset
, obj
->size
, 1);
1391 i915_gem_free_mmap_offset(struct drm_gem_object
*obj
)
1393 struct drm_device
*dev
= obj
->dev
;
1394 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1395 struct drm_gem_mm
*mm
= dev
->mm_private
;
1396 struct drm_map_list
*list
;
1398 list
= &obj
->map_list
;
1399 drm_ht_remove_item(&mm
->offset_hash
, &list
->hash
);
1401 if (list
->file_offset_node
) {
1402 drm_mm_put_block(list
->file_offset_node
);
1403 list
->file_offset_node
= NULL
;
1411 obj_priv
->mmap_offset
= 0;
1415 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1416 * @obj: object to check
1418 * Return the required GTT alignment for an object, taking into account
1419 * potential fence register mapping if needed.
1422 i915_gem_get_gtt_alignment(struct drm_gem_object
*obj
)
1424 struct drm_device
*dev
= obj
->dev
;
1425 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1429 * Minimum alignment is 4k (GTT page size), but might be greater
1430 * if a fence register is needed for the object.
1432 if (INTEL_INFO(dev
)->gen
>= 4 || obj_priv
->tiling_mode
== I915_TILING_NONE
)
1436 * Previous chips need to be aligned to the size of the smallest
1437 * fence register that can contain the object.
1439 if (INTEL_INFO(dev
)->gen
== 3)
1444 for (i
= start
; i
< obj
->size
; i
<<= 1)
1451 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1453 * @data: GTT mapping ioctl data
1454 * @file_priv: GEM object info
1456 * Simply returns the fake offset to userspace so it can mmap it.
1457 * The mmap call will end up in drm_gem_mmap(), which will set things
1458 * up so we can get faults in the handler above.
1460 * The fault handler will take care of binding the object into the GTT
1461 * (since it may have been evicted to make room for something), allocating
1462 * a fence register, and mapping the appropriate aperture address into
1466 i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
1467 struct drm_file
*file_priv
)
1469 struct drm_i915_gem_mmap_gtt
*args
= data
;
1470 struct drm_gem_object
*obj
;
1471 struct drm_i915_gem_object
*obj_priv
;
1474 if (!(dev
->driver
->driver_features
& DRIVER_GEM
))
1477 ret
= i915_mutex_lock_interruptible(dev
);
1481 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
1486 obj_priv
= to_intel_bo(obj
);
1488 if (obj_priv
->madv
!= I915_MADV_WILLNEED
) {
1489 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1494 if (!obj_priv
->mmap_offset
) {
1495 ret
= i915_gem_create_mmap_offset(obj
);
1500 args
->offset
= obj_priv
->mmap_offset
;
1503 * Pull it into the GTT so that we have a page list (makes the
1504 * initial fault faster and any subsequent flushing possible).
1506 if (!obj_priv
->agp_mem
) {
1507 ret
= i915_gem_object_bind_to_gtt(obj
, 0);
1513 drm_gem_object_unreference(obj
);
1515 mutex_unlock(&dev
->struct_mutex
);
1520 i915_gem_object_put_pages(struct drm_gem_object
*obj
)
1522 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1523 int page_count
= obj
->size
/ PAGE_SIZE
;
1526 BUG_ON(obj_priv
->pages_refcount
== 0);
1527 BUG_ON(obj_priv
->madv
== __I915_MADV_PURGED
);
1529 if (--obj_priv
->pages_refcount
!= 0)
1532 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
)
1533 i915_gem_object_save_bit_17_swizzle(obj
);
1535 if (obj_priv
->madv
== I915_MADV_DONTNEED
)
1536 obj_priv
->dirty
= 0;
1538 for (i
= 0; i
< page_count
; i
++) {
1539 if (obj_priv
->dirty
)
1540 set_page_dirty(obj_priv
->pages
[i
]);
1542 if (obj_priv
->madv
== I915_MADV_WILLNEED
)
1543 mark_page_accessed(obj_priv
->pages
[i
]);
1545 page_cache_release(obj_priv
->pages
[i
]);
1547 obj_priv
->dirty
= 0;
1549 drm_free_large(obj_priv
->pages
);
1550 obj_priv
->pages
= NULL
;
1554 i915_gem_next_request_seqno(struct drm_device
*dev
,
1555 struct intel_ring_buffer
*ring
)
1557 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1559 ring
->outstanding_lazy_request
= true;
1560 return dev_priv
->next_seqno
;
1564 i915_gem_object_move_to_active(struct drm_gem_object
*obj
,
1565 struct intel_ring_buffer
*ring
)
1567 struct drm_device
*dev
= obj
->dev
;
1568 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1569 uint32_t seqno
= i915_gem_next_request_seqno(dev
, ring
);
1571 BUG_ON(ring
== NULL
);
1572 obj_priv
->ring
= ring
;
1574 /* Add a reference if we're newly entering the active list. */
1575 if (!obj_priv
->active
) {
1576 drm_gem_object_reference(obj
);
1577 obj_priv
->active
= 1;
1580 /* Move from whatever list we were on to the tail of execution. */
1581 list_move_tail(&obj_priv
->list
, &ring
->active_list
);
1582 obj_priv
->last_rendering_seqno
= seqno
;
1586 i915_gem_object_move_to_flushing(struct drm_gem_object
*obj
)
1588 struct drm_device
*dev
= obj
->dev
;
1589 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1590 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1592 BUG_ON(!obj_priv
->active
);
1593 list_move_tail(&obj_priv
->list
, &dev_priv
->mm
.flushing_list
);
1594 obj_priv
->last_rendering_seqno
= 0;
1597 /* Immediately discard the backing storage */
1599 i915_gem_object_truncate(struct drm_gem_object
*obj
)
1601 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1602 struct inode
*inode
;
1604 /* Our goal here is to return as much of the memory as
1605 * is possible back to the system as we are called from OOM.
1606 * To do this we must instruct the shmfs to drop all of its
1607 * backing pages, *now*. Here we mirror the actions taken
1608 * when by shmem_delete_inode() to release the backing store.
1610 inode
= obj
->filp
->f_path
.dentry
->d_inode
;
1611 truncate_inode_pages(inode
->i_mapping
, 0);
1612 if (inode
->i_op
->truncate_range
)
1613 inode
->i_op
->truncate_range(inode
, 0, (loff_t
)-1);
1615 obj_priv
->madv
= __I915_MADV_PURGED
;
1619 i915_gem_object_is_purgeable(struct drm_i915_gem_object
*obj_priv
)
1621 return obj_priv
->madv
== I915_MADV_DONTNEED
;
1625 i915_gem_object_move_to_inactive(struct drm_gem_object
*obj
)
1627 struct drm_device
*dev
= obj
->dev
;
1628 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1629 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1631 if (obj_priv
->pin_count
!= 0)
1632 list_move_tail(&obj_priv
->list
, &dev_priv
->mm
.pinned_list
);
1634 list_move_tail(&obj_priv
->list
, &dev_priv
->mm
.inactive_list
);
1636 BUG_ON(!list_empty(&obj_priv
->gpu_write_list
));
1638 obj_priv
->last_rendering_seqno
= 0;
1639 obj_priv
->ring
= NULL
;
1640 if (obj_priv
->active
) {
1641 obj_priv
->active
= 0;
1642 drm_gem_object_unreference(obj
);
1644 WARN_ON(i915_verify_lists(dev
));
1648 i915_gem_process_flushing_list(struct drm_device
*dev
,
1649 uint32_t flush_domains
,
1650 struct intel_ring_buffer
*ring
)
1652 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1653 struct drm_i915_gem_object
*obj_priv
, *next
;
1655 list_for_each_entry_safe(obj_priv
, next
,
1656 &dev_priv
->mm
.gpu_write_list
,
1658 struct drm_gem_object
*obj
= &obj_priv
->base
;
1660 if (obj
->write_domain
& flush_domains
&&
1661 obj_priv
->ring
== ring
) {
1662 uint32_t old_write_domain
= obj
->write_domain
;
1664 obj
->write_domain
= 0;
1665 list_del_init(&obj_priv
->gpu_write_list
);
1666 i915_gem_object_move_to_active(obj
, ring
);
1668 /* update the fence lru list */
1669 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
) {
1670 struct drm_i915_fence_reg
*reg
=
1671 &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
1672 list_move_tail(®
->lru_list
,
1673 &dev_priv
->mm
.fence_list
);
1676 trace_i915_gem_object_change_domain(obj
,
1684 i915_add_request(struct drm_device
*dev
,
1685 struct drm_file
*file
,
1686 struct drm_i915_gem_request
*request
,
1687 struct intel_ring_buffer
*ring
)
1689 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1690 struct drm_i915_file_private
*file_priv
= NULL
;
1695 file_priv
= file
->driver_priv
;
1697 if (request
== NULL
) {
1698 request
= kzalloc(sizeof(*request
), GFP_KERNEL
);
1699 if (request
== NULL
)
1703 seqno
= ring
->add_request(dev
, ring
, 0);
1704 ring
->outstanding_lazy_request
= false;
1706 request
->seqno
= seqno
;
1707 request
->ring
= ring
;
1708 request
->emitted_jiffies
= jiffies
;
1709 was_empty
= list_empty(&ring
->request_list
);
1710 list_add_tail(&request
->list
, &ring
->request_list
);
1713 spin_lock(&file_priv
->mm
.lock
);
1714 request
->file_priv
= file_priv
;
1715 list_add_tail(&request
->client_list
,
1716 &file_priv
->mm
.request_list
);
1717 spin_unlock(&file_priv
->mm
.lock
);
1720 if (!dev_priv
->mm
.suspended
) {
1721 mod_timer(&dev_priv
->hangcheck_timer
,
1722 jiffies
+ msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD
));
1724 queue_delayed_work(dev_priv
->wq
,
1725 &dev_priv
->mm
.retire_work
, HZ
);
1731 * Command execution barrier
1733 * Ensures that all commands in the ring are finished
1734 * before signalling the CPU
1737 i915_retire_commands(struct drm_device
*dev
, struct intel_ring_buffer
*ring
)
1739 uint32_t flush_domains
= 0;
1741 /* The sampler always gets flushed on i965 (sigh) */
1742 if (INTEL_INFO(dev
)->gen
>= 4)
1743 flush_domains
|= I915_GEM_DOMAIN_SAMPLER
;
1745 ring
->flush(dev
, ring
,
1746 I915_GEM_DOMAIN_COMMAND
, flush_domains
);
1750 i915_gem_request_remove_from_client(struct drm_i915_gem_request
*request
)
1752 struct drm_i915_file_private
*file_priv
= request
->file_priv
;
1757 spin_lock(&file_priv
->mm
.lock
);
1758 list_del(&request
->client_list
);
1759 request
->file_priv
= NULL
;
1760 spin_unlock(&file_priv
->mm
.lock
);
1763 static void i915_gem_reset_ring_lists(struct drm_i915_private
*dev_priv
,
1764 struct intel_ring_buffer
*ring
)
1766 while (!list_empty(&ring
->request_list
)) {
1767 struct drm_i915_gem_request
*request
;
1769 request
= list_first_entry(&ring
->request_list
,
1770 struct drm_i915_gem_request
,
1773 list_del(&request
->list
);
1774 i915_gem_request_remove_from_client(request
);
1778 while (!list_empty(&ring
->active_list
)) {
1779 struct drm_i915_gem_object
*obj_priv
;
1781 obj_priv
= list_first_entry(&ring
->active_list
,
1782 struct drm_i915_gem_object
,
1785 obj_priv
->base
.write_domain
= 0;
1786 list_del_init(&obj_priv
->gpu_write_list
);
1787 i915_gem_object_move_to_inactive(&obj_priv
->base
);
1791 void i915_gem_reset(struct drm_device
*dev
)
1793 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1794 struct drm_i915_gem_object
*obj_priv
;
1797 i915_gem_reset_ring_lists(dev_priv
, &dev_priv
->render_ring
);
1798 i915_gem_reset_ring_lists(dev_priv
, &dev_priv
->bsd_ring
);
1800 /* Remove anything from the flushing lists. The GPU cache is likely
1801 * to be lost on reset along with the data, so simply move the
1802 * lost bo to the inactive list.
1804 while (!list_empty(&dev_priv
->mm
.flushing_list
)) {
1805 obj_priv
= list_first_entry(&dev_priv
->mm
.flushing_list
,
1806 struct drm_i915_gem_object
,
1809 obj_priv
->base
.write_domain
= 0;
1810 list_del_init(&obj_priv
->gpu_write_list
);
1811 i915_gem_object_move_to_inactive(&obj_priv
->base
);
1814 /* Move everything out of the GPU domains to ensure we do any
1815 * necessary invalidation upon reuse.
1817 list_for_each_entry(obj_priv
,
1818 &dev_priv
->mm
.inactive_list
,
1821 obj_priv
->base
.read_domains
&= ~I915_GEM_GPU_DOMAINS
;
1824 /* The fence registers are invalidated so clear them out */
1825 for (i
= 0; i
< 16; i
++) {
1826 struct drm_i915_fence_reg
*reg
;
1828 reg
= &dev_priv
->fence_regs
[i
];
1832 i915_gem_clear_fence_reg(reg
->obj
);
1837 * This function clears the request list as sequence numbers are passed.
1840 i915_gem_retire_requests_ring(struct drm_device
*dev
,
1841 struct intel_ring_buffer
*ring
)
1843 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1846 if (!ring
->status_page
.page_addr
||
1847 list_empty(&ring
->request_list
))
1850 WARN_ON(i915_verify_lists(dev
));
1852 seqno
= ring
->get_seqno(dev
, ring
);
1853 while (!list_empty(&ring
->request_list
)) {
1854 struct drm_i915_gem_request
*request
;
1856 request
= list_first_entry(&ring
->request_list
,
1857 struct drm_i915_gem_request
,
1860 if (!i915_seqno_passed(seqno
, request
->seqno
))
1863 trace_i915_gem_request_retire(dev
, request
->seqno
);
1865 list_del(&request
->list
);
1866 i915_gem_request_remove_from_client(request
);
1870 /* Move any buffers on the active list that are no longer referenced
1871 * by the ringbuffer to the flushing/inactive lists as appropriate.
1873 while (!list_empty(&ring
->active_list
)) {
1874 struct drm_gem_object
*obj
;
1875 struct drm_i915_gem_object
*obj_priv
;
1877 obj_priv
= list_first_entry(&ring
->active_list
,
1878 struct drm_i915_gem_object
,
1881 if (!i915_seqno_passed(seqno
, obj_priv
->last_rendering_seqno
))
1884 obj
= &obj_priv
->base
;
1885 if (obj
->write_domain
!= 0)
1886 i915_gem_object_move_to_flushing(obj
);
1888 i915_gem_object_move_to_inactive(obj
);
1891 if (unlikely (dev_priv
->trace_irq_seqno
&&
1892 i915_seqno_passed(dev_priv
->trace_irq_seqno
, seqno
))) {
1893 ring
->user_irq_put(dev
, ring
);
1894 dev_priv
->trace_irq_seqno
= 0;
1897 WARN_ON(i915_verify_lists(dev
));
1901 i915_gem_retire_requests(struct drm_device
*dev
)
1903 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1905 if (!list_empty(&dev_priv
->mm
.deferred_free_list
)) {
1906 struct drm_i915_gem_object
*obj_priv
, *tmp
;
1908 /* We must be careful that during unbind() we do not
1909 * accidentally infinitely recurse into retire requests.
1911 * retire -> free -> unbind -> wait -> retire_ring
1913 list_for_each_entry_safe(obj_priv
, tmp
,
1914 &dev_priv
->mm
.deferred_free_list
,
1916 i915_gem_free_object_tail(&obj_priv
->base
);
1919 i915_gem_retire_requests_ring(dev
, &dev_priv
->render_ring
);
1920 i915_gem_retire_requests_ring(dev
, &dev_priv
->bsd_ring
);
1924 i915_gem_retire_work_handler(struct work_struct
*work
)
1926 drm_i915_private_t
*dev_priv
;
1927 struct drm_device
*dev
;
1929 dev_priv
= container_of(work
, drm_i915_private_t
,
1930 mm
.retire_work
.work
);
1931 dev
= dev_priv
->dev
;
1933 /* Come back later if the device is busy... */
1934 if (!mutex_trylock(&dev
->struct_mutex
)) {
1935 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, HZ
);
1939 i915_gem_retire_requests(dev
);
1941 if (!dev_priv
->mm
.suspended
&&
1942 (!list_empty(&dev_priv
->render_ring
.request_list
) ||
1943 !list_empty(&dev_priv
->bsd_ring
.request_list
)))
1944 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, HZ
);
1945 mutex_unlock(&dev
->struct_mutex
);
1949 i915_do_wait_request(struct drm_device
*dev
, uint32_t seqno
,
1950 bool interruptible
, struct intel_ring_buffer
*ring
)
1952 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
1958 if (atomic_read(&dev_priv
->mm
.wedged
))
1961 if (ring
->outstanding_lazy_request
) {
1962 seqno
= i915_add_request(dev
, NULL
, NULL
, ring
);
1966 BUG_ON(seqno
== dev_priv
->next_seqno
);
1968 if (!i915_seqno_passed(ring
->get_seqno(dev
, ring
), seqno
)) {
1969 if (HAS_PCH_SPLIT(dev
))
1970 ier
= I915_READ(DEIER
) | I915_READ(GTIER
);
1972 ier
= I915_READ(IER
);
1974 DRM_ERROR("something (likely vbetool) disabled "
1975 "interrupts, re-enabling\n");
1976 i915_driver_irq_preinstall(dev
);
1977 i915_driver_irq_postinstall(dev
);
1980 trace_i915_gem_request_wait_begin(dev
, seqno
);
1982 ring
->waiting_gem_seqno
= seqno
;
1983 ring
->user_irq_get(dev
, ring
);
1985 ret
= wait_event_interruptible(ring
->irq_queue
,
1987 ring
->get_seqno(dev
, ring
), seqno
)
1988 || atomic_read(&dev_priv
->mm
.wedged
));
1990 wait_event(ring
->irq_queue
,
1992 ring
->get_seqno(dev
, ring
), seqno
)
1993 || atomic_read(&dev_priv
->mm
.wedged
));
1995 ring
->user_irq_put(dev
, ring
);
1996 ring
->waiting_gem_seqno
= 0;
1998 trace_i915_gem_request_wait_end(dev
, seqno
);
2000 if (atomic_read(&dev_priv
->mm
.wedged
))
2003 if (ret
&& ret
!= -ERESTARTSYS
)
2004 DRM_ERROR("%s returns %d (awaiting %d at %d, next %d)\n",
2005 __func__
, ret
, seqno
, ring
->get_seqno(dev
, ring
),
2006 dev_priv
->next_seqno
);
2008 /* Directly dispatch request retiring. While we have the work queue
2009 * to handle this, the waiter on a request often wants an associated
2010 * buffer to have made it to the inactive list, and we would need
2011 * a separate wait queue to handle that.
2014 i915_gem_retire_requests_ring(dev
, ring
);
2020 * Waits for a sequence number to be signaled, and cleans up the
2021 * request and object lists appropriately for that event.
2024 i915_wait_request(struct drm_device
*dev
, uint32_t seqno
,
2025 struct intel_ring_buffer
*ring
)
2027 return i915_do_wait_request(dev
, seqno
, 1, ring
);
2031 i915_gem_flush_ring(struct drm_device
*dev
,
2032 struct drm_file
*file_priv
,
2033 struct intel_ring_buffer
*ring
,
2034 uint32_t invalidate_domains
,
2035 uint32_t flush_domains
)
2037 ring
->flush(dev
, ring
, invalidate_domains
, flush_domains
);
2038 i915_gem_process_flushing_list(dev
, flush_domains
, ring
);
2042 i915_gem_flush(struct drm_device
*dev
,
2043 struct drm_file
*file_priv
,
2044 uint32_t invalidate_domains
,
2045 uint32_t flush_domains
,
2046 uint32_t flush_rings
)
2048 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2050 if (flush_domains
& I915_GEM_DOMAIN_CPU
)
2051 drm_agp_chipset_flush(dev
);
2053 if ((flush_domains
| invalidate_domains
) & I915_GEM_GPU_DOMAINS
) {
2054 if (flush_rings
& RING_RENDER
)
2055 i915_gem_flush_ring(dev
, file_priv
,
2056 &dev_priv
->render_ring
,
2057 invalidate_domains
, flush_domains
);
2058 if (flush_rings
& RING_BSD
)
2059 i915_gem_flush_ring(dev
, file_priv
,
2060 &dev_priv
->bsd_ring
,
2061 invalidate_domains
, flush_domains
);
2066 * Ensures that all rendering to the object has completed and the object is
2067 * safe to unbind from the GTT or access from the CPU.
2070 i915_gem_object_wait_rendering(struct drm_gem_object
*obj
,
2073 struct drm_device
*dev
= obj
->dev
;
2074 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2077 /* This function only exists to support waiting for existing rendering,
2078 * not for emitting required flushes.
2080 BUG_ON((obj
->write_domain
& I915_GEM_GPU_DOMAINS
) != 0);
2082 /* If there is rendering queued on the buffer being evicted, wait for
2085 if (obj_priv
->active
) {
2086 ret
= i915_do_wait_request(dev
,
2087 obj_priv
->last_rendering_seqno
,
2098 * Unbinds an object from the GTT aperture.
2101 i915_gem_object_unbind(struct drm_gem_object
*obj
)
2103 struct drm_device
*dev
= obj
->dev
;
2104 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2105 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2108 if (obj_priv
->gtt_space
== NULL
)
2111 if (obj_priv
->pin_count
!= 0) {
2112 DRM_ERROR("Attempting to unbind pinned buffer\n");
2116 /* blow away mappings if mapped through GTT */
2117 i915_gem_release_mmap(obj
);
2119 /* Move the object to the CPU domain to ensure that
2120 * any possible CPU writes while it's not in the GTT
2121 * are flushed when we go to remap it. This will
2122 * also ensure that all pending GPU writes are finished
2125 ret
= i915_gem_object_set_to_cpu_domain(obj
, 1);
2126 if (ret
== -ERESTARTSYS
)
2128 /* Continue on if we fail due to EIO, the GPU is hung so we
2129 * should be safe and we need to cleanup or else we might
2130 * cause memory corruption through use-after-free.
2133 i915_gem_clflush_object(obj
);
2134 obj
->read_domains
= obj
->write_domain
= I915_GEM_DOMAIN_CPU
;
2137 /* release the fence reg _after_ flushing */
2138 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
)
2139 i915_gem_clear_fence_reg(obj
);
2141 drm_unbind_agp(obj_priv
->agp_mem
);
2142 drm_free_agp(obj_priv
->agp_mem
, obj
->size
/ PAGE_SIZE
);
2144 i915_gem_object_put_pages(obj
);
2145 BUG_ON(obj_priv
->pages_refcount
);
2147 i915_gem_info_remove_gtt(dev_priv
, obj
->size
);
2148 list_del_init(&obj_priv
->list
);
2150 drm_mm_put_block(obj_priv
->gtt_space
);
2151 obj_priv
->gtt_space
= NULL
;
2152 obj_priv
->gtt_offset
= 0;
2154 if (i915_gem_object_is_purgeable(obj_priv
))
2155 i915_gem_object_truncate(obj
);
2157 trace_i915_gem_object_unbind(obj
);
2162 static int i915_ring_idle(struct drm_device
*dev
,
2163 struct intel_ring_buffer
*ring
)
2165 i915_gem_flush_ring(dev
, NULL
, ring
,
2166 I915_GEM_GPU_DOMAINS
, I915_GEM_GPU_DOMAINS
);
2167 return i915_wait_request(dev
,
2168 i915_gem_next_request_seqno(dev
, ring
),
2173 i915_gpu_idle(struct drm_device
*dev
)
2175 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2179 lists_empty
= (list_empty(&dev_priv
->mm
.flushing_list
) &&
2180 list_empty(&dev_priv
->render_ring
.active_list
) &&
2181 list_empty(&dev_priv
->bsd_ring
.active_list
));
2185 /* Flush everything onto the inactive list. */
2186 ret
= i915_ring_idle(dev
, &dev_priv
->render_ring
);
2190 ret
= i915_ring_idle(dev
, &dev_priv
->bsd_ring
);
2198 i915_gem_object_get_pages(struct drm_gem_object
*obj
,
2201 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2203 struct address_space
*mapping
;
2204 struct inode
*inode
;
2207 BUG_ON(obj_priv
->pages_refcount
2208 == DRM_I915_GEM_OBJECT_MAX_PAGES_REFCOUNT
);
2210 if (obj_priv
->pages_refcount
++ != 0)
2213 /* Get the list of pages out of our struct file. They'll be pinned
2214 * at this point until we release them.
2216 page_count
= obj
->size
/ PAGE_SIZE
;
2217 BUG_ON(obj_priv
->pages
!= NULL
);
2218 obj_priv
->pages
= drm_calloc_large(page_count
, sizeof(struct page
*));
2219 if (obj_priv
->pages
== NULL
) {
2220 obj_priv
->pages_refcount
--;
2224 inode
= obj
->filp
->f_path
.dentry
->d_inode
;
2225 mapping
= inode
->i_mapping
;
2226 for (i
= 0; i
< page_count
; i
++) {
2227 page
= read_cache_page_gfp(mapping
, i
,
2235 obj_priv
->pages
[i
] = page
;
2238 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
)
2239 i915_gem_object_do_bit_17_swizzle(obj
);
2245 page_cache_release(obj_priv
->pages
[i
]);
2247 drm_free_large(obj_priv
->pages
);
2248 obj_priv
->pages
= NULL
;
2249 obj_priv
->pages_refcount
--;
2250 return PTR_ERR(page
);
2253 static void sandybridge_write_fence_reg(struct drm_i915_fence_reg
*reg
)
2255 struct drm_gem_object
*obj
= reg
->obj
;
2256 struct drm_device
*dev
= obj
->dev
;
2257 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2258 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2259 int regnum
= obj_priv
->fence_reg
;
2262 val
= (uint64_t)((obj_priv
->gtt_offset
+ obj
->size
- 4096) &
2264 val
|= obj_priv
->gtt_offset
& 0xfffff000;
2265 val
|= (uint64_t)((obj_priv
->stride
/ 128) - 1) <<
2266 SANDYBRIDGE_FENCE_PITCH_SHIFT
;
2268 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2269 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
2270 val
|= I965_FENCE_REG_VALID
;
2272 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0
+ (regnum
* 8), val
);
2275 static void i965_write_fence_reg(struct drm_i915_fence_reg
*reg
)
2277 struct drm_gem_object
*obj
= reg
->obj
;
2278 struct drm_device
*dev
= obj
->dev
;
2279 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2280 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2281 int regnum
= obj_priv
->fence_reg
;
2284 val
= (uint64_t)((obj_priv
->gtt_offset
+ obj
->size
- 4096) &
2286 val
|= obj_priv
->gtt_offset
& 0xfffff000;
2287 val
|= ((obj_priv
->stride
/ 128) - 1) << I965_FENCE_PITCH_SHIFT
;
2288 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2289 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
2290 val
|= I965_FENCE_REG_VALID
;
2292 I915_WRITE64(FENCE_REG_965_0
+ (regnum
* 8), val
);
2295 static void i915_write_fence_reg(struct drm_i915_fence_reg
*reg
)
2297 struct drm_gem_object
*obj
= reg
->obj
;
2298 struct drm_device
*dev
= obj
->dev
;
2299 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2300 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2301 int regnum
= obj_priv
->fence_reg
;
2303 uint32_t fence_reg
, val
;
2306 if ((obj_priv
->gtt_offset
& ~I915_FENCE_START_MASK
) ||
2307 (obj_priv
->gtt_offset
& (obj
->size
- 1))) {
2308 WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
2309 __func__
, obj_priv
->gtt_offset
, obj
->size
);
2313 if (obj_priv
->tiling_mode
== I915_TILING_Y
&&
2314 HAS_128_BYTE_Y_TILING(dev
))
2319 /* Note: pitch better be a power of two tile widths */
2320 pitch_val
= obj_priv
->stride
/ tile_width
;
2321 pitch_val
= ffs(pitch_val
) - 1;
2323 if (obj_priv
->tiling_mode
== I915_TILING_Y
&&
2324 HAS_128_BYTE_Y_TILING(dev
))
2325 WARN_ON(pitch_val
> I830_FENCE_MAX_PITCH_VAL
);
2327 WARN_ON(pitch_val
> I915_FENCE_MAX_PITCH_VAL
);
2329 val
= obj_priv
->gtt_offset
;
2330 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2331 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2332 val
|= I915_FENCE_SIZE_BITS(obj
->size
);
2333 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2334 val
|= I830_FENCE_REG_VALID
;
2337 fence_reg
= FENCE_REG_830_0
+ (regnum
* 4);
2339 fence_reg
= FENCE_REG_945_8
+ ((regnum
- 8) * 4);
2340 I915_WRITE(fence_reg
, val
);
2343 static void i830_write_fence_reg(struct drm_i915_fence_reg
*reg
)
2345 struct drm_gem_object
*obj
= reg
->obj
;
2346 struct drm_device
*dev
= obj
->dev
;
2347 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2348 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2349 int regnum
= obj_priv
->fence_reg
;
2352 uint32_t fence_size_bits
;
2354 if ((obj_priv
->gtt_offset
& ~I830_FENCE_START_MASK
) ||
2355 (obj_priv
->gtt_offset
& (obj
->size
- 1))) {
2356 WARN(1, "%s: object 0x%08x not 512K or size aligned\n",
2357 __func__
, obj_priv
->gtt_offset
);
2361 pitch_val
= obj_priv
->stride
/ 128;
2362 pitch_val
= ffs(pitch_val
) - 1;
2363 WARN_ON(pitch_val
> I830_FENCE_MAX_PITCH_VAL
);
2365 val
= obj_priv
->gtt_offset
;
2366 if (obj_priv
->tiling_mode
== I915_TILING_Y
)
2367 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
2368 fence_size_bits
= I830_FENCE_SIZE_BITS(obj
->size
);
2369 WARN_ON(fence_size_bits
& ~0x00000f00);
2370 val
|= fence_size_bits
;
2371 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
2372 val
|= I830_FENCE_REG_VALID
;
2374 I915_WRITE(FENCE_REG_830_0
+ (regnum
* 4), val
);
2377 static int i915_find_fence_reg(struct drm_device
*dev
,
2380 struct drm_i915_fence_reg
*reg
= NULL
;
2381 struct drm_i915_gem_object
*obj_priv
= NULL
;
2382 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2383 struct drm_gem_object
*obj
= NULL
;
2386 /* First try to find a free reg */
2388 for (i
= dev_priv
->fence_reg_start
; i
< dev_priv
->num_fence_regs
; i
++) {
2389 reg
= &dev_priv
->fence_regs
[i
];
2393 obj_priv
= to_intel_bo(reg
->obj
);
2394 if (!obj_priv
->pin_count
)
2401 /* None available, try to steal one or wait for a user to finish */
2402 i
= I915_FENCE_REG_NONE
;
2403 list_for_each_entry(reg
, &dev_priv
->mm
.fence_list
,
2406 obj_priv
= to_intel_bo(obj
);
2408 if (obj_priv
->pin_count
)
2412 i
= obj_priv
->fence_reg
;
2416 BUG_ON(i
== I915_FENCE_REG_NONE
);
2418 /* We only have a reference on obj from the active list. put_fence_reg
2419 * might drop that one, causing a use-after-free in it. So hold a
2420 * private reference to obj like the other callers of put_fence_reg
2421 * (set_tiling ioctl) do. */
2422 drm_gem_object_reference(obj
);
2423 ret
= i915_gem_object_put_fence_reg(obj
, interruptible
);
2424 drm_gem_object_unreference(obj
);
2432 * i915_gem_object_get_fence_reg - set up a fence reg for an object
2433 * @obj: object to map through a fence reg
2435 * When mapping objects through the GTT, userspace wants to be able to write
2436 * to them without having to worry about swizzling if the object is tiled.
2438 * This function walks the fence regs looking for a free one for @obj,
2439 * stealing one if it can't find any.
2441 * It then sets up the reg based on the object's properties: address, pitch
2442 * and tiling format.
2445 i915_gem_object_get_fence_reg(struct drm_gem_object
*obj
,
2448 struct drm_device
*dev
= obj
->dev
;
2449 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2450 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2451 struct drm_i915_fence_reg
*reg
= NULL
;
2454 /* Just update our place in the LRU if our fence is getting used. */
2455 if (obj_priv
->fence_reg
!= I915_FENCE_REG_NONE
) {
2456 reg
= &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
2457 list_move_tail(®
->lru_list
, &dev_priv
->mm
.fence_list
);
2461 switch (obj_priv
->tiling_mode
) {
2462 case I915_TILING_NONE
:
2463 WARN(1, "allocating a fence for non-tiled object?\n");
2466 if (!obj_priv
->stride
)
2468 WARN((obj_priv
->stride
& (512 - 1)),
2469 "object 0x%08x is X tiled but has non-512B pitch\n",
2470 obj_priv
->gtt_offset
);
2473 if (!obj_priv
->stride
)
2475 WARN((obj_priv
->stride
& (128 - 1)),
2476 "object 0x%08x is Y tiled but has non-128B pitch\n",
2477 obj_priv
->gtt_offset
);
2481 ret
= i915_find_fence_reg(dev
, interruptible
);
2485 obj_priv
->fence_reg
= ret
;
2486 reg
= &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
2487 list_add_tail(®
->lru_list
, &dev_priv
->mm
.fence_list
);
2491 switch (INTEL_INFO(dev
)->gen
) {
2493 sandybridge_write_fence_reg(reg
);
2497 i965_write_fence_reg(reg
);
2500 i915_write_fence_reg(reg
);
2503 i830_write_fence_reg(reg
);
2507 trace_i915_gem_object_get_fence(obj
, obj_priv
->fence_reg
,
2508 obj_priv
->tiling_mode
);
2514 * i915_gem_clear_fence_reg - clear out fence register info
2515 * @obj: object to clear
2517 * Zeroes out the fence register itself and clears out the associated
2518 * data structures in dev_priv and obj_priv.
2521 i915_gem_clear_fence_reg(struct drm_gem_object
*obj
)
2523 struct drm_device
*dev
= obj
->dev
;
2524 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2525 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2526 struct drm_i915_fence_reg
*reg
=
2527 &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
2530 switch (INTEL_INFO(dev
)->gen
) {
2532 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0
+
2533 (obj_priv
->fence_reg
* 8), 0);
2537 I915_WRITE64(FENCE_REG_965_0
+ (obj_priv
->fence_reg
* 8), 0);
2540 if (obj_priv
->fence_reg
>= 8)
2541 fence_reg
= FENCE_REG_945_8
+ (obj_priv
->fence_reg
- 8) * 4;
2544 fence_reg
= FENCE_REG_830_0
+ obj_priv
->fence_reg
* 4;
2546 I915_WRITE(fence_reg
, 0);
2551 obj_priv
->fence_reg
= I915_FENCE_REG_NONE
;
2552 list_del_init(®
->lru_list
);
2556 * i915_gem_object_put_fence_reg - waits on outstanding fenced access
2557 * to the buffer to finish, and then resets the fence register.
2558 * @obj: tiled object holding a fence register.
2559 * @bool: whether the wait upon the fence is interruptible
2561 * Zeroes out the fence register itself and clears out the associated
2562 * data structures in dev_priv and obj_priv.
2565 i915_gem_object_put_fence_reg(struct drm_gem_object
*obj
,
2568 struct drm_device
*dev
= obj
->dev
;
2569 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2570 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2571 struct drm_i915_fence_reg
*reg
;
2573 if (obj_priv
->fence_reg
== I915_FENCE_REG_NONE
)
2576 /* If we've changed tiling, GTT-mappings of the object
2577 * need to re-fault to ensure that the correct fence register
2578 * setup is in place.
2580 i915_gem_release_mmap(obj
);
2582 /* On the i915, GPU access to tiled buffers is via a fence,
2583 * therefore we must wait for any outstanding access to complete
2584 * before clearing the fence.
2586 reg
= &dev_priv
->fence_regs
[obj_priv
->fence_reg
];
2590 ret
= i915_gem_object_flush_gpu_write_domain(obj
, true);
2594 ret
= i915_gem_object_wait_rendering(obj
, interruptible
);
2601 i915_gem_object_flush_gtt_write_domain(obj
);
2602 i915_gem_clear_fence_reg(obj
);
2608 * Finds free space in the GTT aperture and binds the object there.
2611 i915_gem_object_bind_to_gtt(struct drm_gem_object
*obj
, unsigned alignment
)
2613 struct drm_device
*dev
= obj
->dev
;
2614 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
2615 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2616 struct drm_mm_node
*free_space
;
2617 gfp_t gfpmask
= __GFP_NORETRY
| __GFP_NOWARN
;
2620 if (obj_priv
->madv
!= I915_MADV_WILLNEED
) {
2621 DRM_ERROR("Attempting to bind a purgeable object\n");
2626 alignment
= i915_gem_get_gtt_alignment(obj
);
2627 if (alignment
& (i915_gem_get_gtt_alignment(obj
) - 1)) {
2628 DRM_ERROR("Invalid object alignment requested %u\n", alignment
);
2632 /* If the object is bigger than the entire aperture, reject it early
2633 * before evicting everything in a vain attempt to find space.
2635 if (obj
->size
> dev_priv
->mm
.gtt_total
) {
2636 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2641 free_space
= drm_mm_search_free(&dev_priv
->mm
.gtt_space
,
2642 obj
->size
, alignment
, 0);
2643 if (free_space
!= NULL
)
2644 obj_priv
->gtt_space
= drm_mm_get_block(free_space
, obj
->size
,
2646 if (obj_priv
->gtt_space
== NULL
) {
2647 /* If the gtt is empty and we're still having trouble
2648 * fitting our object in, we're out of memory.
2650 ret
= i915_gem_evict_something(dev
, obj
->size
, alignment
);
2657 ret
= i915_gem_object_get_pages(obj
, gfpmask
);
2659 drm_mm_put_block(obj_priv
->gtt_space
);
2660 obj_priv
->gtt_space
= NULL
;
2662 if (ret
== -ENOMEM
) {
2663 /* first try to clear up some space from the GTT */
2664 ret
= i915_gem_evict_something(dev
, obj
->size
,
2667 /* now try to shrink everyone else */
2682 /* Create an AGP memory structure pointing at our pages, and bind it
2685 obj_priv
->agp_mem
= drm_agp_bind_pages(dev
,
2687 obj
->size
>> PAGE_SHIFT
,
2688 obj_priv
->gtt_space
->start
,
2689 obj_priv
->agp_type
);
2690 if (obj_priv
->agp_mem
== NULL
) {
2691 i915_gem_object_put_pages(obj
);
2692 drm_mm_put_block(obj_priv
->gtt_space
);
2693 obj_priv
->gtt_space
= NULL
;
2695 ret
= i915_gem_evict_something(dev
, obj
->size
, alignment
);
2702 /* keep track of bounds object by adding it to the inactive list */
2703 list_add_tail(&obj_priv
->list
, &dev_priv
->mm
.inactive_list
);
2704 i915_gem_info_add_gtt(dev_priv
, obj
->size
);
2706 /* Assert that the object is not currently in any GPU domain. As it
2707 * wasn't in the GTT, there shouldn't be any way it could have been in
2710 BUG_ON(obj
->read_domains
& I915_GEM_GPU_DOMAINS
);
2711 BUG_ON(obj
->write_domain
& I915_GEM_GPU_DOMAINS
);
2713 obj_priv
->gtt_offset
= obj_priv
->gtt_space
->start
;
2714 trace_i915_gem_object_bind(obj
, obj_priv
->gtt_offset
);
2720 i915_gem_clflush_object(struct drm_gem_object
*obj
)
2722 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2724 /* If we don't have a page list set up, then we're not pinned
2725 * to GPU, and we can ignore the cache flush because it'll happen
2726 * again at bind time.
2728 if (obj_priv
->pages
== NULL
)
2731 trace_i915_gem_object_clflush(obj
);
2733 drm_clflush_pages(obj_priv
->pages
, obj
->size
/ PAGE_SIZE
);
2736 /** Flushes any GPU write domain for the object if it's dirty. */
2738 i915_gem_object_flush_gpu_write_domain(struct drm_gem_object
*obj
,
2741 struct drm_device
*dev
= obj
->dev
;
2742 uint32_t old_write_domain
;
2744 if ((obj
->write_domain
& I915_GEM_GPU_DOMAINS
) == 0)
2747 /* Queue the GPU write cache flushing we need. */
2748 old_write_domain
= obj
->write_domain
;
2749 i915_gem_flush_ring(dev
, NULL
,
2750 to_intel_bo(obj
)->ring
,
2751 0, obj
->write_domain
);
2752 BUG_ON(obj
->write_domain
);
2754 trace_i915_gem_object_change_domain(obj
,
2761 return i915_gem_object_wait_rendering(obj
, true);
2764 /** Flushes the GTT write domain for the object if it's dirty. */
2766 i915_gem_object_flush_gtt_write_domain(struct drm_gem_object
*obj
)
2768 uint32_t old_write_domain
;
2770 if (obj
->write_domain
!= I915_GEM_DOMAIN_GTT
)
2773 /* No actual flushing is required for the GTT write domain. Writes
2774 * to it immediately go to main memory as far as we know, so there's
2775 * no chipset flush. It also doesn't land in render cache.
2777 old_write_domain
= obj
->write_domain
;
2778 obj
->write_domain
= 0;
2780 trace_i915_gem_object_change_domain(obj
,
2785 /** Flushes the CPU write domain for the object if it's dirty. */
2787 i915_gem_object_flush_cpu_write_domain(struct drm_gem_object
*obj
)
2789 struct drm_device
*dev
= obj
->dev
;
2790 uint32_t old_write_domain
;
2792 if (obj
->write_domain
!= I915_GEM_DOMAIN_CPU
)
2795 i915_gem_clflush_object(obj
);
2796 drm_agp_chipset_flush(dev
);
2797 old_write_domain
= obj
->write_domain
;
2798 obj
->write_domain
= 0;
2800 trace_i915_gem_object_change_domain(obj
,
2806 * Moves a single object to the GTT read, and possibly write domain.
2808 * This function returns when the move is complete, including waiting on
2812 i915_gem_object_set_to_gtt_domain(struct drm_gem_object
*obj
, int write
)
2814 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2815 uint32_t old_write_domain
, old_read_domains
;
2818 /* Not valid to be called on unbound objects. */
2819 if (obj_priv
->gtt_space
== NULL
)
2822 ret
= i915_gem_object_flush_gpu_write_domain(obj
, false);
2826 i915_gem_object_flush_cpu_write_domain(obj
);
2829 ret
= i915_gem_object_wait_rendering(obj
, true);
2834 old_write_domain
= obj
->write_domain
;
2835 old_read_domains
= obj
->read_domains
;
2837 /* It should now be out of any other write domains, and we can update
2838 * the domain values for our changes.
2840 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
2841 obj
->read_domains
|= I915_GEM_DOMAIN_GTT
;
2843 obj
->read_domains
= I915_GEM_DOMAIN_GTT
;
2844 obj
->write_domain
= I915_GEM_DOMAIN_GTT
;
2845 obj_priv
->dirty
= 1;
2848 trace_i915_gem_object_change_domain(obj
,
2856 * Prepare buffer for display plane. Use uninterruptible for possible flush
2857 * wait, as in modesetting process we're not supposed to be interrupted.
2860 i915_gem_object_set_to_display_plane(struct drm_gem_object
*obj
,
2863 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
2864 uint32_t old_read_domains
;
2867 /* Not valid to be called on unbound objects. */
2868 if (obj_priv
->gtt_space
== NULL
)
2871 ret
= i915_gem_object_flush_gpu_write_domain(obj
, true);
2875 /* Currently, we are always called from an non-interruptible context. */
2877 ret
= i915_gem_object_wait_rendering(obj
, false);
2882 i915_gem_object_flush_cpu_write_domain(obj
);
2884 old_read_domains
= obj
->read_domains
;
2885 obj
->read_domains
|= I915_GEM_DOMAIN_GTT
;
2887 trace_i915_gem_object_change_domain(obj
,
2895 * Moves a single object to the CPU read, and possibly write domain.
2897 * This function returns when the move is complete, including waiting on
2901 i915_gem_object_set_to_cpu_domain(struct drm_gem_object
*obj
, int write
)
2903 uint32_t old_write_domain
, old_read_domains
;
2906 ret
= i915_gem_object_flush_gpu_write_domain(obj
, false);
2910 i915_gem_object_flush_gtt_write_domain(obj
);
2912 /* If we have a partially-valid cache of the object in the CPU,
2913 * finish invalidating it and free the per-page flags.
2915 i915_gem_object_set_to_full_cpu_read_domain(obj
);
2918 ret
= i915_gem_object_wait_rendering(obj
, true);
2923 old_write_domain
= obj
->write_domain
;
2924 old_read_domains
= obj
->read_domains
;
2926 /* Flush the CPU cache if it's still invalid. */
2927 if ((obj
->read_domains
& I915_GEM_DOMAIN_CPU
) == 0) {
2928 i915_gem_clflush_object(obj
);
2930 obj
->read_domains
|= I915_GEM_DOMAIN_CPU
;
2933 /* It should now be out of any other write domains, and we can update
2934 * the domain values for our changes.
2936 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
2938 /* If we're writing through the CPU, then the GPU read domains will
2939 * need to be invalidated at next use.
2942 obj
->read_domains
= I915_GEM_DOMAIN_CPU
;
2943 obj
->write_domain
= I915_GEM_DOMAIN_CPU
;
2946 trace_i915_gem_object_change_domain(obj
,
2954 * Set the next domain for the specified object. This
2955 * may not actually perform the necessary flushing/invaliding though,
2956 * as that may want to be batched with other set_domain operations
2958 * This is (we hope) the only really tricky part of gem. The goal
2959 * is fairly simple -- track which caches hold bits of the object
2960 * and make sure they remain coherent. A few concrete examples may
2961 * help to explain how it works. For shorthand, we use the notation
2962 * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
2963 * a pair of read and write domain masks.
2965 * Case 1: the batch buffer
2971 * 5. Unmapped from GTT
2974 * Let's take these a step at a time
2977 * Pages allocated from the kernel may still have
2978 * cache contents, so we set them to (CPU, CPU) always.
2979 * 2. Written by CPU (using pwrite)
2980 * The pwrite function calls set_domain (CPU, CPU) and
2981 * this function does nothing (as nothing changes)
2983 * This function asserts that the object is not
2984 * currently in any GPU-based read or write domains
2986 * i915_gem_execbuffer calls set_domain (COMMAND, 0).
2987 * As write_domain is zero, this function adds in the
2988 * current read domains (CPU+COMMAND, 0).
2989 * flush_domains is set to CPU.
2990 * invalidate_domains is set to COMMAND
2991 * clflush is run to get data out of the CPU caches
2992 * then i915_dev_set_domain calls i915_gem_flush to
2993 * emit an MI_FLUSH and drm_agp_chipset_flush
2994 * 5. Unmapped from GTT
2995 * i915_gem_object_unbind calls set_domain (CPU, CPU)
2996 * flush_domains and invalidate_domains end up both zero
2997 * so no flushing/invalidating happens
3001 * Case 2: The shared render buffer
3005 * 3. Read/written by GPU
3006 * 4. set_domain to (CPU,CPU)
3007 * 5. Read/written by CPU
3008 * 6. Read/written by GPU
3011 * Same as last example, (CPU, CPU)
3013 * Nothing changes (assertions find that it is not in the GPU)
3014 * 3. Read/written by GPU
3015 * execbuffer calls set_domain (RENDER, RENDER)
3016 * flush_domains gets CPU
3017 * invalidate_domains gets GPU
3019 * MI_FLUSH and drm_agp_chipset_flush
3020 * 4. set_domain (CPU, CPU)
3021 * flush_domains gets GPU
3022 * invalidate_domains gets CPU
3023 * wait_rendering (obj) to make sure all drawing is complete.
3024 * This will include an MI_FLUSH to get the data from GPU
3026 * clflush (obj) to invalidate the CPU cache
3027 * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
3028 * 5. Read/written by CPU
3029 * cache lines are loaded and dirtied
3030 * 6. Read written by GPU
3031 * Same as last GPU access
3033 * Case 3: The constant buffer
3038 * 4. Updated (written) by CPU again
3047 * flush_domains = CPU
3048 * invalidate_domains = RENDER
3051 * drm_agp_chipset_flush
3052 * 4. Updated (written) by CPU again
3054 * flush_domains = 0 (no previous write domain)
3055 * invalidate_domains = 0 (no new read domains)
3058 * flush_domains = CPU
3059 * invalidate_domains = RENDER
3062 * drm_agp_chipset_flush
3065 i915_gem_object_set_to_gpu_domain(struct drm_gem_object
*obj
)
3067 struct drm_device
*dev
= obj
->dev
;
3068 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3069 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
3070 uint32_t invalidate_domains
= 0;
3071 uint32_t flush_domains
= 0;
3072 uint32_t old_read_domains
;
3074 intel_mark_busy(dev
, obj
);
3077 * If the object isn't moving to a new write domain,
3078 * let the object stay in multiple read domains
3080 if (obj
->pending_write_domain
== 0)
3081 obj
->pending_read_domains
|= obj
->read_domains
;
3083 obj_priv
->dirty
= 1;
3086 * Flush the current write domain if
3087 * the new read domains don't match. Invalidate
3088 * any read domains which differ from the old
3091 if (obj
->write_domain
&&
3092 obj
->write_domain
!= obj
->pending_read_domains
) {
3093 flush_domains
|= obj
->write_domain
;
3094 invalidate_domains
|=
3095 obj
->pending_read_domains
& ~obj
->write_domain
;
3098 * Invalidate any read caches which may have
3099 * stale data. That is, any new read domains.
3101 invalidate_domains
|= obj
->pending_read_domains
& ~obj
->read_domains
;
3102 if ((flush_domains
| invalidate_domains
) & I915_GEM_DOMAIN_CPU
)
3103 i915_gem_clflush_object(obj
);
3105 old_read_domains
= obj
->read_domains
;
3107 /* The actual obj->write_domain will be updated with
3108 * pending_write_domain after we emit the accumulated flush for all
3109 * of our domain changes in execbuffers (which clears objects'
3110 * write_domains). So if we have a current write domain that we
3111 * aren't changing, set pending_write_domain to that.
3113 if (flush_domains
== 0 && obj
->pending_write_domain
== 0)
3114 obj
->pending_write_domain
= obj
->write_domain
;
3115 obj
->read_domains
= obj
->pending_read_domains
;
3117 dev
->invalidate_domains
|= invalidate_domains
;
3118 dev
->flush_domains
|= flush_domains
;
3120 dev_priv
->mm
.flush_rings
|= obj_priv
->ring
->id
;
3122 trace_i915_gem_object_change_domain(obj
,
3128 * Moves the object from a partially CPU read to a full one.
3130 * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3131 * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
3134 i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object
*obj
)
3136 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
3138 if (!obj_priv
->page_cpu_valid
)
3141 /* If we're partially in the CPU read domain, finish moving it in.
3143 if (obj
->read_domains
& I915_GEM_DOMAIN_CPU
) {
3146 for (i
= 0; i
<= (obj
->size
- 1) / PAGE_SIZE
; i
++) {
3147 if (obj_priv
->page_cpu_valid
[i
])
3149 drm_clflush_pages(obj_priv
->pages
+ i
, 1);
3153 /* Free the page_cpu_valid mappings which are now stale, whether
3154 * or not we've got I915_GEM_DOMAIN_CPU.
3156 kfree(obj_priv
->page_cpu_valid
);
3157 obj_priv
->page_cpu_valid
= NULL
;
3161 * Set the CPU read domain on a range of the object.
3163 * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3164 * not entirely valid. The page_cpu_valid member of the object flags which
3165 * pages have been flushed, and will be respected by
3166 * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3167 * of the whole object.
3169 * This function returns when the move is complete, including waiting on
3173 i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object
*obj
,
3174 uint64_t offset
, uint64_t size
)
3176 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
3177 uint32_t old_read_domains
;
3180 if (offset
== 0 && size
== obj
->size
)
3181 return i915_gem_object_set_to_cpu_domain(obj
, 0);
3183 ret
= i915_gem_object_flush_gpu_write_domain(obj
, false);
3186 i915_gem_object_flush_gtt_write_domain(obj
);
3188 /* If we're already fully in the CPU read domain, we're done. */
3189 if (obj_priv
->page_cpu_valid
== NULL
&&
3190 (obj
->read_domains
& I915_GEM_DOMAIN_CPU
) != 0)
3193 /* Otherwise, create/clear the per-page CPU read domain flag if we're
3194 * newly adding I915_GEM_DOMAIN_CPU
3196 if (obj_priv
->page_cpu_valid
== NULL
) {
3197 obj_priv
->page_cpu_valid
= kzalloc(obj
->size
/ PAGE_SIZE
,
3199 if (obj_priv
->page_cpu_valid
== NULL
)
3201 } else if ((obj
->read_domains
& I915_GEM_DOMAIN_CPU
) == 0)
3202 memset(obj_priv
->page_cpu_valid
, 0, obj
->size
/ PAGE_SIZE
);
3204 /* Flush the cache on any pages that are still invalid from the CPU's
3207 for (i
= offset
/ PAGE_SIZE
; i
<= (offset
+ size
- 1) / PAGE_SIZE
;
3209 if (obj_priv
->page_cpu_valid
[i
])
3212 drm_clflush_pages(obj_priv
->pages
+ i
, 1);
3214 obj_priv
->page_cpu_valid
[i
] = 1;
3217 /* It should now be out of any other write domains, and we can update
3218 * the domain values for our changes.
3220 BUG_ON((obj
->write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
3222 old_read_domains
= obj
->read_domains
;
3223 obj
->read_domains
|= I915_GEM_DOMAIN_CPU
;
3225 trace_i915_gem_object_change_domain(obj
,
3233 * Pin an object to the GTT and evaluate the relocations landing in it.
3236 i915_gem_execbuffer_relocate(struct drm_i915_gem_object
*obj
,
3237 struct drm_file
*file_priv
,
3238 struct drm_i915_gem_exec_object2
*entry
)
3240 struct drm_device
*dev
= obj
->base
.dev
;
3241 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3242 struct drm_i915_gem_relocation_entry __user
*user_relocs
;
3243 struct drm_gem_object
*target_obj
= NULL
;
3244 uint32_t target_handle
= 0;
3247 user_relocs
= (void __user
*)(uintptr_t)entry
->relocs_ptr
;
3248 for (i
= 0; i
< entry
->relocation_count
; i
++) {
3249 struct drm_i915_gem_relocation_entry reloc
;
3250 uint32_t target_offset
;
3252 if (__copy_from_user_inatomic(&reloc
,
3259 if (reloc
.target_handle
!= target_handle
) {
3260 drm_gem_object_unreference(target_obj
);
3262 target_obj
= drm_gem_object_lookup(dev
, file_priv
,
3263 reloc
.target_handle
);
3264 if (target_obj
== NULL
) {
3269 target_handle
= reloc
.target_handle
;
3271 target_offset
= to_intel_bo(target_obj
)->gtt_offset
;
3274 DRM_INFO("%s: obj %p offset %08x target %d "
3275 "read %08x write %08x gtt %08x "
3276 "presumed %08x delta %08x\n",
3280 (int) reloc
.target_handle
,
3281 (int) reloc
.read_domains
,
3282 (int) reloc
.write_domain
,
3283 (int) target_offset
,
3284 (int) reloc
.presumed_offset
,
3288 /* The target buffer should have appeared before us in the
3289 * exec_object list, so it should have a GTT space bound by now.
3291 if (target_offset
== 0) {
3292 DRM_ERROR("No GTT space found for object %d\n",
3293 reloc
.target_handle
);
3298 /* Validate that the target is in a valid r/w GPU domain */
3299 if (reloc
.write_domain
& (reloc
.write_domain
- 1)) {
3300 DRM_ERROR("reloc with multiple write domains: "
3301 "obj %p target %d offset %d "
3302 "read %08x write %08x",
3303 obj
, reloc
.target_handle
,
3306 reloc
.write_domain
);
3310 if (reloc
.write_domain
& I915_GEM_DOMAIN_CPU
||
3311 reloc
.read_domains
& I915_GEM_DOMAIN_CPU
) {
3312 DRM_ERROR("reloc with read/write CPU domains: "
3313 "obj %p target %d offset %d "
3314 "read %08x write %08x",
3315 obj
, reloc
.target_handle
,
3318 reloc
.write_domain
);
3322 if (reloc
.write_domain
&& target_obj
->pending_write_domain
&&
3323 reloc
.write_domain
!= target_obj
->pending_write_domain
) {
3324 DRM_ERROR("Write domain conflict: "
3325 "obj %p target %d offset %d "
3326 "new %08x old %08x\n",
3327 obj
, reloc
.target_handle
,
3330 target_obj
->pending_write_domain
);
3335 target_obj
->pending_read_domains
|= reloc
.read_domains
;
3336 target_obj
->pending_write_domain
= reloc
.write_domain
;
3338 /* If the relocation already has the right value in it, no
3339 * more work needs to be done.
3341 if (target_offset
== reloc
.presumed_offset
)
3344 /* Check that the relocation address is valid... */
3345 if (reloc
.offset
> obj
->base
.size
- 4) {
3346 DRM_ERROR("Relocation beyond object bounds: "
3347 "obj %p target %d offset %d size %d.\n",
3348 obj
, reloc
.target_handle
,
3349 (int) reloc
.offset
, (int) obj
->base
.size
);
3353 if (reloc
.offset
& 3) {
3354 DRM_ERROR("Relocation not 4-byte aligned: "
3355 "obj %p target %d offset %d.\n",
3356 obj
, reloc
.target_handle
,
3357 (int) reloc
.offset
);
3362 /* and points to somewhere within the target object. */
3363 if (reloc
.delta
>= target_obj
->size
) {
3364 DRM_ERROR("Relocation beyond target object bounds: "
3365 "obj %p target %d delta %d size %d.\n",
3366 obj
, reloc
.target_handle
,
3367 (int) reloc
.delta
, (int) target_obj
->size
);
3372 reloc
.delta
+= target_offset
;
3373 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_CPU
) {
3374 uint32_t page_offset
= reloc
.offset
& ~PAGE_MASK
;
3377 vaddr
= kmap_atomic(obj
->pages
[reloc
.offset
>> PAGE_SHIFT
], KM_USER0
);
3378 *(uint32_t *)(vaddr
+ page_offset
) = reloc
.delta
;
3379 kunmap_atomic(vaddr
, KM_USER0
);
3381 uint32_t __iomem
*reloc_entry
;
3382 void __iomem
*reloc_page
;
3384 ret
= i915_gem_object_set_to_gtt_domain(&obj
->base
, 1);
3388 /* Map the page containing the relocation we're going to perform. */
3389 reloc
.offset
+= obj
->gtt_offset
;
3390 reloc_page
= io_mapping_map_atomic_wc(dev_priv
->mm
.gtt_mapping
,
3391 reloc
.offset
& PAGE_MASK
,
3393 reloc_entry
= (uint32_t __iomem
*)
3394 (reloc_page
+ (reloc
.offset
& ~PAGE_MASK
));
3395 iowrite32(reloc
.delta
, reloc_entry
);
3396 io_mapping_unmap_atomic(reloc_page
, KM_USER0
);
3400 drm_gem_object_unreference(target_obj
);
3405 i915_gem_execbuffer_pin(struct drm_device
*dev
,
3406 struct drm_file
*file
,
3407 struct drm_gem_object
**object_list
,
3408 struct drm_i915_gem_exec_object2
*exec_list
,
3411 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3414 /* attempt to pin all of the buffers into the GTT */
3415 for (retry
= 0; retry
< 2; retry
++) {
3417 for (i
= 0; i
< count
; i
++) {
3418 struct drm_i915_gem_exec_object2
*entry
= &exec_list
[i
];
3419 struct drm_i915_gem_object
*obj
= to_intel_bo(object_list
[i
]);
3421 entry
->flags
& EXEC_OBJECT_NEEDS_FENCE
&&
3422 obj
->tiling_mode
!= I915_TILING_NONE
;
3424 /* Check fence reg constraints and rebind if necessary */
3426 !i915_gem_object_fence_offset_ok(&obj
->base
,
3427 obj
->tiling_mode
)) {
3428 ret
= i915_gem_object_unbind(&obj
->base
);
3433 ret
= i915_gem_object_pin(&obj
->base
, entry
->alignment
);
3438 * Pre-965 chips need a fence register set up in order
3439 * to properly handle blits to/from tiled surfaces.
3442 ret
= i915_gem_object_get_fence_reg(&obj
->base
, true);
3444 i915_gem_object_unpin(&obj
->base
);
3448 dev_priv
->fence_regs
[obj
->fence_reg
].gpu
= true;
3451 entry
->offset
= obj
->gtt_offset
;
3455 i915_gem_object_unpin(object_list
[i
]);
3460 if (ret
!= -ENOSPC
|| retry
)
3463 ret
= i915_gem_evict_everything(dev
);
3471 /* Throttle our rendering by waiting until the ring has completed our requests
3472 * emitted over 20 msec ago.
3474 * Note that if we were to use the current jiffies each time around the loop,
3475 * we wouldn't escape the function with any frames outstanding if the time to
3476 * render a frame was over 20ms.
3478 * This should get us reasonable parallelism between CPU and GPU but also
3479 * relatively low latency when blocking on a particular request to finish.
3482 i915_gem_ring_throttle(struct drm_device
*dev
, struct drm_file
*file
)
3484 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3485 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
3486 unsigned long recent_enough
= jiffies
- msecs_to_jiffies(20);
3487 struct drm_i915_gem_request
*request
;
3488 struct intel_ring_buffer
*ring
= NULL
;
3492 spin_lock(&file_priv
->mm
.lock
);
3493 list_for_each_entry(request
, &file_priv
->mm
.request_list
, client_list
) {
3494 if (time_after_eq(request
->emitted_jiffies
, recent_enough
))
3497 ring
= request
->ring
;
3498 seqno
= request
->seqno
;
3500 spin_unlock(&file_priv
->mm
.lock
);
3506 if (!i915_seqno_passed(ring
->get_seqno(dev
, ring
), seqno
)) {
3507 /* And wait for the seqno passing without holding any locks and
3508 * causing extra latency for others. This is safe as the irq
3509 * generation is designed to be run atomically and so is
3512 ring
->user_irq_get(dev
, ring
);
3513 ret
= wait_event_interruptible(ring
->irq_queue
,
3514 i915_seqno_passed(ring
->get_seqno(dev
, ring
), seqno
)
3515 || atomic_read(&dev_priv
->mm
.wedged
));
3516 ring
->user_irq_put(dev
, ring
);
3518 if (ret
== 0 && atomic_read(&dev_priv
->mm
.wedged
))
3523 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, 0);
3529 i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2
*exec
,
3530 uint64_t exec_offset
)
3532 uint32_t exec_start
, exec_len
;
3534 exec_start
= (uint32_t) exec_offset
+ exec
->batch_start_offset
;
3535 exec_len
= (uint32_t) exec
->batch_len
;
3537 if ((exec_start
| exec_len
) & 0x7)
3547 validate_exec_list(struct drm_i915_gem_exec_object2
*exec
,
3552 for (i
= 0; i
< count
; i
++) {
3553 char __user
*ptr
= (char __user
*)(uintptr_t)exec
[i
].relocs_ptr
;
3554 size_t length
= exec
[i
].relocation_count
* sizeof(struct drm_i915_gem_relocation_entry
);
3556 if (!access_ok(VERIFY_READ
, ptr
, length
))
3559 if (fault_in_pages_readable(ptr
, length
))
3567 i915_gem_do_execbuffer(struct drm_device
*dev
, void *data
,
3568 struct drm_file
*file
,
3569 struct drm_i915_gem_execbuffer2
*args
,
3570 struct drm_i915_gem_exec_object2
*exec_list
)
3572 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3573 struct drm_gem_object
**object_list
= NULL
;
3574 struct drm_gem_object
*batch_obj
;
3575 struct drm_i915_gem_object
*obj_priv
;
3576 struct drm_clip_rect
*cliprects
= NULL
;
3577 struct drm_i915_gem_request
*request
= NULL
;
3579 uint64_t exec_offset
;
3581 struct intel_ring_buffer
*ring
= NULL
;
3583 ret
= i915_gem_check_is_wedged(dev
);
3587 ret
= validate_exec_list(exec_list
, args
->buffer_count
);
3592 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3593 (int) args
->buffers_ptr
, args
->buffer_count
, args
->batch_len
);
3595 if (args
->flags
& I915_EXEC_BSD
) {
3596 if (!HAS_BSD(dev
)) {
3597 DRM_ERROR("execbuf with wrong flag\n");
3600 ring
= &dev_priv
->bsd_ring
;
3602 ring
= &dev_priv
->render_ring
;
3605 if (args
->buffer_count
< 1) {
3606 DRM_ERROR("execbuf with %d buffers\n", args
->buffer_count
);
3609 object_list
= drm_malloc_ab(sizeof(*object_list
), args
->buffer_count
);
3610 if (object_list
== NULL
) {
3611 DRM_ERROR("Failed to allocate object list for %d buffers\n",
3612 args
->buffer_count
);
3617 if (args
->num_cliprects
!= 0) {
3618 cliprects
= kcalloc(args
->num_cliprects
, sizeof(*cliprects
),
3620 if (cliprects
== NULL
) {
3625 ret
= copy_from_user(cliprects
,
3626 (struct drm_clip_rect __user
*)
3627 (uintptr_t) args
->cliprects_ptr
,
3628 sizeof(*cliprects
) * args
->num_cliprects
);
3630 DRM_ERROR("copy %d cliprects failed: %d\n",
3631 args
->num_cliprects
, ret
);
3637 request
= kzalloc(sizeof(*request
), GFP_KERNEL
);
3638 if (request
== NULL
) {
3643 ret
= i915_mutex_lock_interruptible(dev
);
3647 if (dev_priv
->mm
.suspended
) {
3648 mutex_unlock(&dev
->struct_mutex
);
3653 /* Look up object handles */
3654 for (i
= 0; i
< args
->buffer_count
; i
++) {
3655 object_list
[i
] = drm_gem_object_lookup(dev
, file
,
3656 exec_list
[i
].handle
);
3657 if (object_list
[i
] == NULL
) {
3658 DRM_ERROR("Invalid object handle %d at index %d\n",
3659 exec_list
[i
].handle
, i
);
3660 /* prevent error path from reading uninitialized data */
3661 args
->buffer_count
= i
+ 1;
3666 obj_priv
= to_intel_bo(object_list
[i
]);
3667 if (obj_priv
->in_execbuffer
) {
3668 DRM_ERROR("Object %p appears more than once in object list\n",
3670 /* prevent error path from reading uninitialized data */
3671 args
->buffer_count
= i
+ 1;
3675 obj_priv
->in_execbuffer
= true;
3678 /* Move the objects en-masse into the GTT, evicting if necessary. */
3679 ret
= i915_gem_execbuffer_pin(dev
, file
,
3680 object_list
, exec_list
,
3681 args
->buffer_count
);
3685 /* The objects are in their final locations, apply the relocations. */
3686 for (i
= 0; i
< args
->buffer_count
; i
++) {
3687 struct drm_i915_gem_object
*obj
= to_intel_bo(object_list
[i
]);
3688 obj
->base
.pending_read_domains
= 0;
3689 obj
->base
.pending_write_domain
= 0;
3690 ret
= i915_gem_execbuffer_relocate(obj
, file
, &exec_list
[i
]);
3695 /* Set the pending read domains for the batch buffer to COMMAND */
3696 batch_obj
= object_list
[args
->buffer_count
-1];
3697 if (batch_obj
->pending_write_domain
) {
3698 DRM_ERROR("Attempting to use self-modifying batch buffer\n");
3702 batch_obj
->pending_read_domains
|= I915_GEM_DOMAIN_COMMAND
;
3704 /* Sanity check the batch buffer */
3705 exec_offset
= to_intel_bo(batch_obj
)->gtt_offset
;
3706 ret
= i915_gem_check_execbuffer(args
, exec_offset
);
3708 DRM_ERROR("execbuf with invalid offset/length\n");
3712 /* Zero the global flush/invalidate flags. These
3713 * will be modified as new domains are computed
3716 dev
->invalidate_domains
= 0;
3717 dev
->flush_domains
= 0;
3718 dev_priv
->mm
.flush_rings
= 0;
3720 for (i
= 0; i
< args
->buffer_count
; i
++) {
3721 struct drm_gem_object
*obj
= object_list
[i
];
3723 /* Compute new gpu domains and update invalidate/flush */
3724 i915_gem_object_set_to_gpu_domain(obj
);
3727 if (dev
->invalidate_domains
| dev
->flush_domains
) {
3729 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
3731 dev
->invalidate_domains
,
3732 dev
->flush_domains
);
3734 i915_gem_flush(dev
, file
,
3735 dev
->invalidate_domains
,
3737 dev_priv
->mm
.flush_rings
);
3740 for (i
= 0; i
< args
->buffer_count
; i
++) {
3741 struct drm_gem_object
*obj
= object_list
[i
];
3742 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
3743 uint32_t old_write_domain
= obj
->write_domain
;
3745 obj
->write_domain
= obj
->pending_write_domain
;
3746 if (obj
->write_domain
)
3747 list_move_tail(&obj_priv
->gpu_write_list
,
3748 &dev_priv
->mm
.gpu_write_list
);
3750 trace_i915_gem_object_change_domain(obj
,
3756 for (i
= 0; i
< args
->buffer_count
; i
++) {
3757 i915_gem_object_check_coherency(object_list
[i
],
3758 exec_list
[i
].handle
);
3763 i915_gem_dump_object(batch_obj
,
3769 /* Check for any pending flips. As we only maintain a flip queue depth
3770 * of 1, we can simply insert a WAIT for the next display flip prior
3771 * to executing the batch and avoid stalling the CPU.
3774 for (i
= 0; i
< args
->buffer_count
; i
++) {
3775 if (object_list
[i
]->write_domain
)
3776 flips
|= atomic_read(&to_intel_bo(object_list
[i
])->pending_flip
);
3779 int plane
, flip_mask
;
3781 for (plane
= 0; flips
>> plane
; plane
++) {
3782 if (((flips
>> plane
) & 1) == 0)
3786 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
3788 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
3790 intel_ring_begin(dev
, ring
, 2);
3791 intel_ring_emit(dev
, ring
,
3792 MI_WAIT_FOR_EVENT
| flip_mask
);
3793 intel_ring_emit(dev
, ring
, MI_NOOP
);
3794 intel_ring_advance(dev
, ring
);
3798 /* Exec the batchbuffer */
3799 ret
= ring
->dispatch_gem_execbuffer(dev
, ring
, args
,
3800 cliprects
, exec_offset
);
3802 DRM_ERROR("dispatch failed %d\n", ret
);
3807 * Ensure that the commands in the batch buffer are
3808 * finished before the interrupt fires
3810 i915_retire_commands(dev
, ring
);
3812 for (i
= 0; i
< args
->buffer_count
; i
++) {
3813 struct drm_gem_object
*obj
= object_list
[i
];
3814 obj_priv
= to_intel_bo(obj
);
3816 i915_gem_object_move_to_active(obj
, ring
);
3819 i915_add_request(dev
, file
, request
, ring
);
3823 for (i
= 0; i
< args
->buffer_count
; i
++) {
3824 if (object_list
[i
]) {
3825 obj_priv
= to_intel_bo(object_list
[i
]);
3826 obj_priv
->in_execbuffer
= false;
3828 drm_gem_object_unreference(object_list
[i
]);
3831 mutex_unlock(&dev
->struct_mutex
);
3834 drm_free_large(object_list
);
3842 * Legacy execbuffer just creates an exec2 list from the original exec object
3843 * list array and passes it to the real function.
3846 i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
3847 struct drm_file
*file_priv
)
3849 struct drm_i915_gem_execbuffer
*args
= data
;
3850 struct drm_i915_gem_execbuffer2 exec2
;
3851 struct drm_i915_gem_exec_object
*exec_list
= NULL
;
3852 struct drm_i915_gem_exec_object2
*exec2_list
= NULL
;
3856 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3857 (int) args
->buffers_ptr
, args
->buffer_count
, args
->batch_len
);
3860 if (args
->buffer_count
< 1) {
3861 DRM_ERROR("execbuf with %d buffers\n", args
->buffer_count
);
3865 /* Copy in the exec list from userland */
3866 exec_list
= drm_malloc_ab(sizeof(*exec_list
), args
->buffer_count
);
3867 exec2_list
= drm_malloc_ab(sizeof(*exec2_list
), args
->buffer_count
);
3868 if (exec_list
== NULL
|| exec2_list
== NULL
) {
3869 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
3870 args
->buffer_count
);
3871 drm_free_large(exec_list
);
3872 drm_free_large(exec2_list
);
3875 ret
= copy_from_user(exec_list
,
3876 (struct drm_i915_relocation_entry __user
*)
3877 (uintptr_t) args
->buffers_ptr
,
3878 sizeof(*exec_list
) * args
->buffer_count
);
3880 DRM_ERROR("copy %d exec entries failed %d\n",
3881 args
->buffer_count
, ret
);
3882 drm_free_large(exec_list
);
3883 drm_free_large(exec2_list
);
3887 for (i
= 0; i
< args
->buffer_count
; i
++) {
3888 exec2_list
[i
].handle
= exec_list
[i
].handle
;
3889 exec2_list
[i
].relocation_count
= exec_list
[i
].relocation_count
;
3890 exec2_list
[i
].relocs_ptr
= exec_list
[i
].relocs_ptr
;
3891 exec2_list
[i
].alignment
= exec_list
[i
].alignment
;
3892 exec2_list
[i
].offset
= exec_list
[i
].offset
;
3893 if (INTEL_INFO(dev
)->gen
< 4)
3894 exec2_list
[i
].flags
= EXEC_OBJECT_NEEDS_FENCE
;
3896 exec2_list
[i
].flags
= 0;
3899 exec2
.buffers_ptr
= args
->buffers_ptr
;
3900 exec2
.buffer_count
= args
->buffer_count
;
3901 exec2
.batch_start_offset
= args
->batch_start_offset
;
3902 exec2
.batch_len
= args
->batch_len
;
3903 exec2
.DR1
= args
->DR1
;
3904 exec2
.DR4
= args
->DR4
;
3905 exec2
.num_cliprects
= args
->num_cliprects
;
3906 exec2
.cliprects_ptr
= args
->cliprects_ptr
;
3907 exec2
.flags
= I915_EXEC_RENDER
;
3909 ret
= i915_gem_do_execbuffer(dev
, data
, file_priv
, &exec2
, exec2_list
);
3911 /* Copy the new buffer offsets back to the user's exec list. */
3912 for (i
= 0; i
< args
->buffer_count
; i
++)
3913 exec_list
[i
].offset
= exec2_list
[i
].offset
;
3914 /* ... and back out to userspace */
3915 ret
= copy_to_user((struct drm_i915_relocation_entry __user
*)
3916 (uintptr_t) args
->buffers_ptr
,
3918 sizeof(*exec_list
) * args
->buffer_count
);
3921 DRM_ERROR("failed to copy %d exec entries "
3922 "back to user (%d)\n",
3923 args
->buffer_count
, ret
);
3927 drm_free_large(exec_list
);
3928 drm_free_large(exec2_list
);
3933 i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
3934 struct drm_file
*file_priv
)
3936 struct drm_i915_gem_execbuffer2
*args
= data
;
3937 struct drm_i915_gem_exec_object2
*exec2_list
= NULL
;
3941 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3942 (int) args
->buffers_ptr
, args
->buffer_count
, args
->batch_len
);
3945 if (args
->buffer_count
< 1) {
3946 DRM_ERROR("execbuf2 with %d buffers\n", args
->buffer_count
);
3950 exec2_list
= drm_malloc_ab(sizeof(*exec2_list
), args
->buffer_count
);
3951 if (exec2_list
== NULL
) {
3952 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
3953 args
->buffer_count
);
3956 ret
= copy_from_user(exec2_list
,
3957 (struct drm_i915_relocation_entry __user
*)
3958 (uintptr_t) args
->buffers_ptr
,
3959 sizeof(*exec2_list
) * args
->buffer_count
);
3961 DRM_ERROR("copy %d exec entries failed %d\n",
3962 args
->buffer_count
, ret
);
3963 drm_free_large(exec2_list
);
3967 ret
= i915_gem_do_execbuffer(dev
, data
, file_priv
, args
, exec2_list
);
3969 /* Copy the new buffer offsets back to the user's exec list. */
3970 ret
= copy_to_user((struct drm_i915_relocation_entry __user
*)
3971 (uintptr_t) args
->buffers_ptr
,
3973 sizeof(*exec2_list
) * args
->buffer_count
);
3976 DRM_ERROR("failed to copy %d exec entries "
3977 "back to user (%d)\n",
3978 args
->buffer_count
, ret
);
3982 drm_free_large(exec2_list
);
3987 i915_gem_object_pin(struct drm_gem_object
*obj
, uint32_t alignment
)
3989 struct drm_device
*dev
= obj
->dev
;
3990 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3991 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
3994 BUG_ON(obj_priv
->pin_count
== DRM_I915_GEM_OBJECT_MAX_PIN_COUNT
);
3995 WARN_ON(i915_verify_lists(dev
));
3997 if (obj_priv
->gtt_space
!= NULL
) {
3999 alignment
= i915_gem_get_gtt_alignment(obj
);
4000 if (obj_priv
->gtt_offset
& (alignment
- 1)) {
4001 WARN(obj_priv
->pin_count
,
4002 "bo is already pinned with incorrect alignment:"
4003 " offset=%x, req.alignment=%x\n",
4004 obj_priv
->gtt_offset
, alignment
);
4005 ret
= i915_gem_object_unbind(obj
);
4011 if (obj_priv
->gtt_space
== NULL
) {
4012 ret
= i915_gem_object_bind_to_gtt(obj
, alignment
);
4017 obj_priv
->pin_count
++;
4019 /* If the object is not active and not pending a flush,
4020 * remove it from the inactive list
4022 if (obj_priv
->pin_count
== 1) {
4023 i915_gem_info_add_pin(dev_priv
, obj
->size
);
4024 if (!obj_priv
->active
)
4025 list_move_tail(&obj_priv
->list
,
4026 &dev_priv
->mm
.pinned_list
);
4029 WARN_ON(i915_verify_lists(dev
));
4034 i915_gem_object_unpin(struct drm_gem_object
*obj
)
4036 struct drm_device
*dev
= obj
->dev
;
4037 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4038 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
4040 WARN_ON(i915_verify_lists(dev
));
4041 obj_priv
->pin_count
--;
4042 BUG_ON(obj_priv
->pin_count
< 0);
4043 BUG_ON(obj_priv
->gtt_space
== NULL
);
4045 /* If the object is no longer pinned, and is
4046 * neither active nor being flushed, then stick it on
4049 if (obj_priv
->pin_count
== 0) {
4050 if (!obj_priv
->active
)
4051 list_move_tail(&obj_priv
->list
,
4052 &dev_priv
->mm
.inactive_list
);
4053 i915_gem_info_remove_pin(dev_priv
, obj
->size
);
4055 WARN_ON(i915_verify_lists(dev
));
4059 i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
4060 struct drm_file
*file_priv
)
4062 struct drm_i915_gem_pin
*args
= data
;
4063 struct drm_gem_object
*obj
;
4064 struct drm_i915_gem_object
*obj_priv
;
4067 ret
= i915_mutex_lock_interruptible(dev
);
4071 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4076 obj_priv
= to_intel_bo(obj
);
4078 if (obj_priv
->madv
!= I915_MADV_WILLNEED
) {
4079 DRM_ERROR("Attempting to pin a purgeable buffer\n");
4084 if (obj_priv
->pin_filp
!= NULL
&& obj_priv
->pin_filp
!= file_priv
) {
4085 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
4091 obj_priv
->user_pin_count
++;
4092 obj_priv
->pin_filp
= file_priv
;
4093 if (obj_priv
->user_pin_count
== 1) {
4094 ret
= i915_gem_object_pin(obj
, args
->alignment
);
4099 /* XXX - flush the CPU caches for pinned objects
4100 * as the X server doesn't manage domains yet
4102 i915_gem_object_flush_cpu_write_domain(obj
);
4103 args
->offset
= obj_priv
->gtt_offset
;
4105 drm_gem_object_unreference(obj
);
4107 mutex_unlock(&dev
->struct_mutex
);
4112 i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
4113 struct drm_file
*file_priv
)
4115 struct drm_i915_gem_pin
*args
= data
;
4116 struct drm_gem_object
*obj
;
4117 struct drm_i915_gem_object
*obj_priv
;
4120 ret
= i915_mutex_lock_interruptible(dev
);
4124 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4129 obj_priv
= to_intel_bo(obj
);
4131 if (obj_priv
->pin_filp
!= file_priv
) {
4132 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4137 obj_priv
->user_pin_count
--;
4138 if (obj_priv
->user_pin_count
== 0) {
4139 obj_priv
->pin_filp
= NULL
;
4140 i915_gem_object_unpin(obj
);
4144 drm_gem_object_unreference(obj
);
4146 mutex_unlock(&dev
->struct_mutex
);
4151 i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
4152 struct drm_file
*file_priv
)
4154 struct drm_i915_gem_busy
*args
= data
;
4155 struct drm_gem_object
*obj
;
4156 struct drm_i915_gem_object
*obj_priv
;
4159 ret
= i915_mutex_lock_interruptible(dev
);
4163 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4168 obj_priv
= to_intel_bo(obj
);
4170 /* Count all active objects as busy, even if they are currently not used
4171 * by the gpu. Users of this interface expect objects to eventually
4172 * become non-busy without any further actions, therefore emit any
4173 * necessary flushes here.
4175 args
->busy
= obj_priv
->active
;
4177 /* Unconditionally flush objects, even when the gpu still uses this
4178 * object. Userspace calling this function indicates that it wants to
4179 * use this buffer rather sooner than later, so issuing the required
4180 * flush earlier is beneficial.
4182 if (obj
->write_domain
& I915_GEM_GPU_DOMAINS
)
4183 i915_gem_flush_ring(dev
, file_priv
,
4185 0, obj
->write_domain
);
4187 /* Update the active list for the hardware's current position.
4188 * Otherwise this only updates on a delayed timer or when irqs
4189 * are actually unmasked, and our working set ends up being
4190 * larger than required.
4192 i915_gem_retire_requests_ring(dev
, obj_priv
->ring
);
4194 args
->busy
= obj_priv
->active
;
4197 drm_gem_object_unreference(obj
);
4199 mutex_unlock(&dev
->struct_mutex
);
4204 i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
4205 struct drm_file
*file_priv
)
4207 return i915_gem_ring_throttle(dev
, file_priv
);
4211 i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
4212 struct drm_file
*file_priv
)
4214 struct drm_i915_gem_madvise
*args
= data
;
4215 struct drm_gem_object
*obj
;
4216 struct drm_i915_gem_object
*obj_priv
;
4219 switch (args
->madv
) {
4220 case I915_MADV_DONTNEED
:
4221 case I915_MADV_WILLNEED
:
4227 ret
= i915_mutex_lock_interruptible(dev
);
4231 obj
= drm_gem_object_lookup(dev
, file_priv
, args
->handle
);
4236 obj_priv
= to_intel_bo(obj
);
4238 if (obj_priv
->pin_count
) {
4243 if (obj_priv
->madv
!= __I915_MADV_PURGED
)
4244 obj_priv
->madv
= args
->madv
;
4246 /* if the object is no longer bound, discard its backing storage */
4247 if (i915_gem_object_is_purgeable(obj_priv
) &&
4248 obj_priv
->gtt_space
== NULL
)
4249 i915_gem_object_truncate(obj
);
4251 args
->retained
= obj_priv
->madv
!= __I915_MADV_PURGED
;
4254 drm_gem_object_unreference(obj
);
4256 mutex_unlock(&dev
->struct_mutex
);
4260 struct drm_gem_object
* i915_gem_alloc_object(struct drm_device
*dev
,
4263 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4264 struct drm_i915_gem_object
*obj
;
4266 obj
= kzalloc(sizeof(*obj
), GFP_KERNEL
);
4270 if (drm_gem_object_init(dev
, &obj
->base
, size
) != 0) {
4275 i915_gem_info_add_obj(dev_priv
, size
);
4277 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
4278 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
4280 obj
->agp_type
= AGP_USER_MEMORY
;
4281 obj
->base
.driver_private
= NULL
;
4282 obj
->fence_reg
= I915_FENCE_REG_NONE
;
4283 INIT_LIST_HEAD(&obj
->list
);
4284 INIT_LIST_HEAD(&obj
->gpu_write_list
);
4285 obj
->madv
= I915_MADV_WILLNEED
;
4290 int i915_gem_init_object(struct drm_gem_object
*obj
)
4297 static void i915_gem_free_object_tail(struct drm_gem_object
*obj
)
4299 struct drm_device
*dev
= obj
->dev
;
4300 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4301 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
4304 ret
= i915_gem_object_unbind(obj
);
4305 if (ret
== -ERESTARTSYS
) {
4306 list_move(&obj_priv
->list
,
4307 &dev_priv
->mm
.deferred_free_list
);
4311 if (obj_priv
->mmap_offset
)
4312 i915_gem_free_mmap_offset(obj
);
4314 drm_gem_object_release(obj
);
4315 i915_gem_info_remove_obj(dev_priv
, obj
->size
);
4317 kfree(obj_priv
->page_cpu_valid
);
4318 kfree(obj_priv
->bit_17
);
4322 void i915_gem_free_object(struct drm_gem_object
*obj
)
4324 struct drm_device
*dev
= obj
->dev
;
4325 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
4327 trace_i915_gem_object_destroy(obj
);
4329 while (obj_priv
->pin_count
> 0)
4330 i915_gem_object_unpin(obj
);
4332 if (obj_priv
->phys_obj
)
4333 i915_gem_detach_phys_object(dev
, obj
);
4335 i915_gem_free_object_tail(obj
);
4339 i915_gem_idle(struct drm_device
*dev
)
4341 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4344 mutex_lock(&dev
->struct_mutex
);
4346 if (dev_priv
->mm
.suspended
) {
4347 mutex_unlock(&dev
->struct_mutex
);
4351 ret
= i915_gpu_idle(dev
);
4353 mutex_unlock(&dev
->struct_mutex
);
4357 /* Under UMS, be paranoid and evict. */
4358 if (!drm_core_check_feature(dev
, DRIVER_MODESET
)) {
4359 ret
= i915_gem_evict_inactive(dev
);
4361 mutex_unlock(&dev
->struct_mutex
);
4366 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4367 * We need to replace this with a semaphore, or something.
4368 * And not confound mm.suspended!
4370 dev_priv
->mm
.suspended
= 1;
4371 del_timer_sync(&dev_priv
->hangcheck_timer
);
4373 i915_kernel_lost_context(dev
);
4374 i915_gem_cleanup_ringbuffer(dev
);
4376 mutex_unlock(&dev
->struct_mutex
);
4378 /* Cancel the retire work handler, which should be idle now. */
4379 cancel_delayed_work_sync(&dev_priv
->mm
.retire_work
);
4385 * 965+ support PIPE_CONTROL commands, which provide finer grained control
4386 * over cache flushing.
4389 i915_gem_init_pipe_control(struct drm_device
*dev
)
4391 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4392 struct drm_gem_object
*obj
;
4393 struct drm_i915_gem_object
*obj_priv
;
4396 obj
= i915_gem_alloc_object(dev
, 4096);
4398 DRM_ERROR("Failed to allocate seqno page\n");
4402 obj_priv
= to_intel_bo(obj
);
4403 obj_priv
->agp_type
= AGP_USER_CACHED_MEMORY
;
4405 ret
= i915_gem_object_pin(obj
, 4096);
4409 dev_priv
->seqno_gfx_addr
= obj_priv
->gtt_offset
;
4410 dev_priv
->seqno_page
= kmap(obj_priv
->pages
[0]);
4411 if (dev_priv
->seqno_page
== NULL
)
4414 dev_priv
->seqno_obj
= obj
;
4415 memset(dev_priv
->seqno_page
, 0, PAGE_SIZE
);
4420 i915_gem_object_unpin(obj
);
4422 drm_gem_object_unreference(obj
);
4429 i915_gem_cleanup_pipe_control(struct drm_device
*dev
)
4431 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4432 struct drm_gem_object
*obj
;
4433 struct drm_i915_gem_object
*obj_priv
;
4435 obj
= dev_priv
->seqno_obj
;
4436 obj_priv
= to_intel_bo(obj
);
4437 kunmap(obj_priv
->pages
[0]);
4438 i915_gem_object_unpin(obj
);
4439 drm_gem_object_unreference(obj
);
4440 dev_priv
->seqno_obj
= NULL
;
4442 dev_priv
->seqno_page
= NULL
;
4446 i915_gem_init_ringbuffer(struct drm_device
*dev
)
4448 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4451 if (HAS_PIPE_CONTROL(dev
)) {
4452 ret
= i915_gem_init_pipe_control(dev
);
4457 ret
= intel_init_render_ring_buffer(dev
);
4459 goto cleanup_pipe_control
;
4462 ret
= intel_init_bsd_ring_buffer(dev
);
4464 goto cleanup_render_ring
;
4467 dev_priv
->next_seqno
= 1;
4471 cleanup_render_ring
:
4472 intel_cleanup_ring_buffer(dev
, &dev_priv
->render_ring
);
4473 cleanup_pipe_control
:
4474 if (HAS_PIPE_CONTROL(dev
))
4475 i915_gem_cleanup_pipe_control(dev
);
4480 i915_gem_cleanup_ringbuffer(struct drm_device
*dev
)
4482 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4484 intel_cleanup_ring_buffer(dev
, &dev_priv
->render_ring
);
4485 intel_cleanup_ring_buffer(dev
, &dev_priv
->bsd_ring
);
4486 if (HAS_PIPE_CONTROL(dev
))
4487 i915_gem_cleanup_pipe_control(dev
);
4491 i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
4492 struct drm_file
*file_priv
)
4494 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4497 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4500 if (atomic_read(&dev_priv
->mm
.wedged
)) {
4501 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4502 atomic_set(&dev_priv
->mm
.wedged
, 0);
4505 mutex_lock(&dev
->struct_mutex
);
4506 dev_priv
->mm
.suspended
= 0;
4508 ret
= i915_gem_init_ringbuffer(dev
);
4510 mutex_unlock(&dev
->struct_mutex
);
4514 BUG_ON(!list_empty(&dev_priv
->render_ring
.active_list
));
4515 BUG_ON(!list_empty(&dev_priv
->bsd_ring
.active_list
));
4516 BUG_ON(!list_empty(&dev_priv
->mm
.flushing_list
));
4517 BUG_ON(!list_empty(&dev_priv
->mm
.inactive_list
));
4518 BUG_ON(!list_empty(&dev_priv
->render_ring
.request_list
));
4519 BUG_ON(!list_empty(&dev_priv
->bsd_ring
.request_list
));
4520 mutex_unlock(&dev
->struct_mutex
);
4522 ret
= drm_irq_install(dev
);
4524 goto cleanup_ringbuffer
;
4529 mutex_lock(&dev
->struct_mutex
);
4530 i915_gem_cleanup_ringbuffer(dev
);
4531 dev_priv
->mm
.suspended
= 1;
4532 mutex_unlock(&dev
->struct_mutex
);
4538 i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
4539 struct drm_file
*file_priv
)
4541 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4544 drm_irq_uninstall(dev
);
4545 return i915_gem_idle(dev
);
4549 i915_gem_lastclose(struct drm_device
*dev
)
4553 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4556 ret
= i915_gem_idle(dev
);
4558 DRM_ERROR("failed to idle hardware: %d\n", ret
);
4562 i915_gem_load(struct drm_device
*dev
)
4565 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4567 INIT_LIST_HEAD(&dev_priv
->mm
.flushing_list
);
4568 INIT_LIST_HEAD(&dev_priv
->mm
.gpu_write_list
);
4569 INIT_LIST_HEAD(&dev_priv
->mm
.inactive_list
);
4570 INIT_LIST_HEAD(&dev_priv
->mm
.pinned_list
);
4571 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
4572 INIT_LIST_HEAD(&dev_priv
->mm
.deferred_free_list
);
4573 INIT_LIST_HEAD(&dev_priv
->render_ring
.active_list
);
4574 INIT_LIST_HEAD(&dev_priv
->render_ring
.request_list
);
4575 INIT_LIST_HEAD(&dev_priv
->bsd_ring
.active_list
);
4576 INIT_LIST_HEAD(&dev_priv
->bsd_ring
.request_list
);
4577 for (i
= 0; i
< 16; i
++)
4578 INIT_LIST_HEAD(&dev_priv
->fence_regs
[i
].lru_list
);
4579 INIT_DELAYED_WORK(&dev_priv
->mm
.retire_work
,
4580 i915_gem_retire_work_handler
);
4581 init_completion(&dev_priv
->error_completion
);
4582 spin_lock(&shrink_list_lock
);
4583 list_add(&dev_priv
->mm
.shrink_list
, &shrink_list
);
4584 spin_unlock(&shrink_list_lock
);
4586 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4588 u32 tmp
= I915_READ(MI_ARB_STATE
);
4589 if (!(tmp
& MI_ARB_C3_LP_WRITE_ENABLE
)) {
4590 /* arb state is a masked write, so set bit + bit in mask */
4591 tmp
= MI_ARB_C3_LP_WRITE_ENABLE
| (MI_ARB_C3_LP_WRITE_ENABLE
<< MI_ARB_MASK_SHIFT
);
4592 I915_WRITE(MI_ARB_STATE
, tmp
);
4596 /* Old X drivers will take 0-2 for front, back, depth buffers */
4597 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
4598 dev_priv
->fence_reg_start
= 3;
4600 if (INTEL_INFO(dev
)->gen
>= 4 || IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
4601 dev_priv
->num_fence_regs
= 16;
4603 dev_priv
->num_fence_regs
= 8;
4605 /* Initialize fence registers to zero */
4606 switch (INTEL_INFO(dev
)->gen
) {
4608 for (i
= 0; i
< 16; i
++)
4609 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0
+ (i
* 8), 0);
4613 for (i
= 0; i
< 16; i
++)
4614 I915_WRITE64(FENCE_REG_965_0
+ (i
* 8), 0);
4617 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
4618 for (i
= 0; i
< 8; i
++)
4619 I915_WRITE(FENCE_REG_945_8
+ (i
* 4), 0);
4621 for (i
= 0; i
< 8; i
++)
4622 I915_WRITE(FENCE_REG_830_0
+ (i
* 4), 0);
4625 i915_gem_detect_bit_6_swizzle(dev
);
4626 init_waitqueue_head(&dev_priv
->pending_flip_queue
);
4630 * Create a physically contiguous memory object for this object
4631 * e.g. for cursor + overlay regs
4633 static int i915_gem_init_phys_object(struct drm_device
*dev
,
4634 int id
, int size
, int align
)
4636 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4637 struct drm_i915_gem_phys_object
*phys_obj
;
4640 if (dev_priv
->mm
.phys_objs
[id
- 1] || !size
)
4643 phys_obj
= kzalloc(sizeof(struct drm_i915_gem_phys_object
), GFP_KERNEL
);
4649 phys_obj
->handle
= drm_pci_alloc(dev
, size
, align
);
4650 if (!phys_obj
->handle
) {
4655 set_memory_wc((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
4658 dev_priv
->mm
.phys_objs
[id
- 1] = phys_obj
;
4666 static void i915_gem_free_phys_object(struct drm_device
*dev
, int id
)
4668 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4669 struct drm_i915_gem_phys_object
*phys_obj
;
4671 if (!dev_priv
->mm
.phys_objs
[id
- 1])
4674 phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
4675 if (phys_obj
->cur_obj
) {
4676 i915_gem_detach_phys_object(dev
, phys_obj
->cur_obj
);
4680 set_memory_wb((unsigned long)phys_obj
->handle
->vaddr
, phys_obj
->handle
->size
/ PAGE_SIZE
);
4682 drm_pci_free(dev
, phys_obj
->handle
);
4684 dev_priv
->mm
.phys_objs
[id
- 1] = NULL
;
4687 void i915_gem_free_all_phys_object(struct drm_device
*dev
)
4691 for (i
= I915_GEM_PHYS_CURSOR_0
; i
<= I915_MAX_PHYS_OBJECT
; i
++)
4692 i915_gem_free_phys_object(dev
, i
);
4695 void i915_gem_detach_phys_object(struct drm_device
*dev
,
4696 struct drm_gem_object
*obj
)
4698 struct drm_i915_gem_object
*obj_priv
;
4703 obj_priv
= to_intel_bo(obj
);
4704 if (!obj_priv
->phys_obj
)
4707 ret
= i915_gem_object_get_pages(obj
, 0);
4711 page_count
= obj
->size
/ PAGE_SIZE
;
4713 for (i
= 0; i
< page_count
; i
++) {
4714 char *dst
= kmap_atomic(obj_priv
->pages
[i
], KM_USER0
);
4715 char *src
= obj_priv
->phys_obj
->handle
->vaddr
+ (i
* PAGE_SIZE
);
4717 memcpy(dst
, src
, PAGE_SIZE
);
4718 kunmap_atomic(dst
, KM_USER0
);
4720 drm_clflush_pages(obj_priv
->pages
, page_count
);
4721 drm_agp_chipset_flush(dev
);
4723 i915_gem_object_put_pages(obj
);
4725 obj_priv
->phys_obj
->cur_obj
= NULL
;
4726 obj_priv
->phys_obj
= NULL
;
4730 i915_gem_attach_phys_object(struct drm_device
*dev
,
4731 struct drm_gem_object
*obj
,
4735 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4736 struct drm_i915_gem_object
*obj_priv
;
4741 if (id
> I915_MAX_PHYS_OBJECT
)
4744 obj_priv
= to_intel_bo(obj
);
4746 if (obj_priv
->phys_obj
) {
4747 if (obj_priv
->phys_obj
->id
== id
)
4749 i915_gem_detach_phys_object(dev
, obj
);
4752 /* create a new object */
4753 if (!dev_priv
->mm
.phys_objs
[id
- 1]) {
4754 ret
= i915_gem_init_phys_object(dev
, id
,
4757 DRM_ERROR("failed to init phys object %d size: %zu\n", id
, obj
->size
);
4762 /* bind to the object */
4763 obj_priv
->phys_obj
= dev_priv
->mm
.phys_objs
[id
- 1];
4764 obj_priv
->phys_obj
->cur_obj
= obj
;
4766 ret
= i915_gem_object_get_pages(obj
, 0);
4768 DRM_ERROR("failed to get page list\n");
4772 page_count
= obj
->size
/ PAGE_SIZE
;
4774 for (i
= 0; i
< page_count
; i
++) {
4775 char *src
= kmap_atomic(obj_priv
->pages
[i
], KM_USER0
);
4776 char *dst
= obj_priv
->phys_obj
->handle
->vaddr
+ (i
* PAGE_SIZE
);
4778 memcpy(dst
, src
, PAGE_SIZE
);
4779 kunmap_atomic(src
, KM_USER0
);
4782 i915_gem_object_put_pages(obj
);
4790 i915_gem_phys_pwrite(struct drm_device
*dev
, struct drm_gem_object
*obj
,
4791 struct drm_i915_gem_pwrite
*args
,
4792 struct drm_file
*file_priv
)
4794 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
4797 char __user
*user_data
;
4799 user_data
= (char __user
*) (uintptr_t) args
->data_ptr
;
4800 obj_addr
= obj_priv
->phys_obj
->handle
->vaddr
+ args
->offset
;
4802 DRM_DEBUG_DRIVER("obj_addr %p, %lld\n", obj_addr
, args
->size
);
4803 ret
= copy_from_user(obj_addr
, user_data
, args
->size
);
4807 drm_agp_chipset_flush(dev
);
4811 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
)
4813 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
4815 /* Clean up our request list when the client is going away, so that
4816 * later retire_requests won't dereference our soon-to-be-gone
4819 spin_lock(&file_priv
->mm
.lock
);
4820 while (!list_empty(&file_priv
->mm
.request_list
)) {
4821 struct drm_i915_gem_request
*request
;
4823 request
= list_first_entry(&file_priv
->mm
.request_list
,
4824 struct drm_i915_gem_request
,
4826 list_del(&request
->client_list
);
4827 request
->file_priv
= NULL
;
4829 spin_unlock(&file_priv
->mm
.lock
);
4833 i915_gpu_is_active(struct drm_device
*dev
)
4835 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4838 lists_empty
= list_empty(&dev_priv
->mm
.flushing_list
) &&
4839 list_empty(&dev_priv
->render_ring
.active_list
) &&
4840 list_empty(&dev_priv
->bsd_ring
.active_list
);
4842 return !lists_empty
;
4846 i915_gem_shrink(struct shrinker
*shrink
, int nr_to_scan
, gfp_t gfp_mask
)
4848 drm_i915_private_t
*dev_priv
, *next_dev
;
4849 struct drm_i915_gem_object
*obj_priv
, *next_obj
;
4851 int would_deadlock
= 1;
4853 /* "fast-path" to count number of available objects */
4854 if (nr_to_scan
== 0) {
4855 spin_lock(&shrink_list_lock
);
4856 list_for_each_entry(dev_priv
, &shrink_list
, mm
.shrink_list
) {
4857 struct drm_device
*dev
= dev_priv
->dev
;
4859 if (mutex_trylock(&dev
->struct_mutex
)) {
4860 list_for_each_entry(obj_priv
,
4861 &dev_priv
->mm
.inactive_list
,
4864 mutex_unlock(&dev
->struct_mutex
);
4867 spin_unlock(&shrink_list_lock
);
4869 return (cnt
/ 100) * sysctl_vfs_cache_pressure
;
4872 spin_lock(&shrink_list_lock
);
4875 /* first scan for clean buffers */
4876 list_for_each_entry_safe(dev_priv
, next_dev
,
4877 &shrink_list
, mm
.shrink_list
) {
4878 struct drm_device
*dev
= dev_priv
->dev
;
4880 if (! mutex_trylock(&dev
->struct_mutex
))
4883 spin_unlock(&shrink_list_lock
);
4884 i915_gem_retire_requests(dev
);
4886 list_for_each_entry_safe(obj_priv
, next_obj
,
4887 &dev_priv
->mm
.inactive_list
,
4889 if (i915_gem_object_is_purgeable(obj_priv
)) {
4890 i915_gem_object_unbind(&obj_priv
->base
);
4891 if (--nr_to_scan
<= 0)
4896 spin_lock(&shrink_list_lock
);
4897 mutex_unlock(&dev
->struct_mutex
);
4901 if (nr_to_scan
<= 0)
4905 /* second pass, evict/count anything still on the inactive list */
4906 list_for_each_entry_safe(dev_priv
, next_dev
,
4907 &shrink_list
, mm
.shrink_list
) {
4908 struct drm_device
*dev
= dev_priv
->dev
;
4910 if (! mutex_trylock(&dev
->struct_mutex
))
4913 spin_unlock(&shrink_list_lock
);
4915 list_for_each_entry_safe(obj_priv
, next_obj
,
4916 &dev_priv
->mm
.inactive_list
,
4918 if (nr_to_scan
> 0) {
4919 i915_gem_object_unbind(&obj_priv
->base
);
4925 spin_lock(&shrink_list_lock
);
4926 mutex_unlock(&dev
->struct_mutex
);
4935 * We are desperate for pages, so as a last resort, wait
4936 * for the GPU to finish and discard whatever we can.
4937 * This has a dramatic impact to reduce the number of
4938 * OOM-killer events whilst running the GPU aggressively.
4940 list_for_each_entry(dev_priv
, &shrink_list
, mm
.shrink_list
) {
4941 struct drm_device
*dev
= dev_priv
->dev
;
4943 if (!mutex_trylock(&dev
->struct_mutex
))
4946 spin_unlock(&shrink_list_lock
);
4948 if (i915_gpu_is_active(dev
)) {
4953 spin_lock(&shrink_list_lock
);
4954 mutex_unlock(&dev
->struct_mutex
);
4961 spin_unlock(&shrink_list_lock
);
4966 return (cnt
/ 100) * sysctl_vfs_cache_pressure
;
4971 static struct shrinker shrinker
= {
4972 .shrink
= i915_gem_shrink
,
4973 .seeks
= DEFAULT_SEEKS
,
4977 i915_gem_shrinker_init(void)
4979 register_shrinker(&shrinker
);
4983 i915_gem_shrinker_exit(void)
4985 unregister_shrinker(&shrinker
);